2006.145.01:31:01.55;Log Opened: Mark IV Field System Version 9.7.7 2006.145.01:31:01.55;location,TSUKUB32,-140.09,36.10,61.0 2006.145.01:31:01.55;horizon1,0.,5.,360. 2006.145.01:31:01.55;antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.145.01:31:01.55;equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.145.01:31:01.55;drivev11,330,270,no 2006.145.01:31:01.55;drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.145.01:31:01.55;drivev13,15.000,268,10.000,10.000,10.000 2006.145.01:31:01.55;drivev21,330,270,no 2006.145.01:31:01.55;drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.145.01:31:01.55;drivev23,15.000,268,10.000,10.000,10.000 2006.145.01:31:01.55;head10,all,all,all,odd,adaptive,no,5.0000,1 2006.145.01:31:01.55;head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.145.01:31:01.55;head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.145.01:31:01.55;head20,all,all,all,odd,adaptive,no,5.0000,1 2006.145.01:31:01.55;head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.145.01:31:01.55;head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.145.01:31:01.55;time,-0.364,101.533,rate 2006.145.01:31:01.55;flagr,200 2006.145.01:31:01.55:" JD0605 2006 TSUKUB32 T Ts 2006.145.01:31:01.55:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.145.01:31:01.55:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.145.01:31:01.55:" 108 K4-TSUKB 0 9149 2006.145.01:31:01.55:" drudg version 050216 compiled under FS 9.7.07 2006.145.01:31:01.55:" Rack=K4-2/M4 Recorder 1=K4-2 Recorder 2=none 2006.145.01:31:01.55:exper_initi 2006.145.01:31:01.55&exper_initi/proc_library 2006.145.01:31:01.55&exper_initi/sched_initi 2006.145.01:31:01.55:scan_name=145-0200,jd0605,40 2006.145.01:31:01.55:source=3c454.3,225357.75,160853.6,2000.0,ccw 2006.145.01:31:02.14#antcn#PM 1 00019 2005 228 00 22 31 00 2006.145.01:31:02.14#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.145.01:31:02.14#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.145.01:31:02.14#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.145.01:31:02.14#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.145.01:31:02.14#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.145.01:31:03.14:ready_k5 2006.145.01:31:03.14&ready_k5/obsinfo=st 2006.145.01:31:03.14&ready_k5/autoobs=1 2006.145.01:31:03.14&ready_k5/autoobs=2 2006.145.01:31:03.14&ready_k5/autoobs=3 2006.145.01:31:03.14&ready_k5/autoobs=4 2006.145.01:31:03.14&ready_k5/obsinfo 2006.145.01:31:03.14#flagr#flagr/antenna,new-source 2006.145.01:31:03.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.145.01:31:06.83/autoobs//k5ts1/ autoobs started! 2006.145.01:31:10.23/autoobs//k5ts2/ autoobs started! 2006.145.01:31:13.93/autoobs//k5ts3/ autoobs started! 2006.145.01:31:17.55/autoobs//k5ts4/ autoobs started! 2006.145.01:31:17.58/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.01:31:17.58:setupk4=1 2006.145.01:31:17.58&setupk4/xlog=on 2006.145.01:31:17.58&setupk4/echo=on 2006.145.01:31:17.58&setupk4/pcalon 2006.145.01:31:17.58&setupk4/"tpicd=stop 2006.145.01:31:17.58&setupk4/"rec=synch_on 2006.145.01:31:17.58&setupk4/"rec_mode=128 2006.145.01:31:17.58&setupk4/!* 2006.145.01:31:17.58&setupk4/recpk4 2006.145.01:31:17.58&setupk4/vck44 2006.145.01:31:17.58&setupk4/ifdk4 2006.145.01:31:17.58&setupk4/!*+20s 2006.145.01:31:17.58&setupk4/"tpicd 2006.145.01:31:17.58&setupk4/echo=off 2006.145.01:31:17.58&setupk4/xlog=off 2006.145.01:31:17.58$setupk4/echo=on 2006.145.01:31:17.58$setupk4/pcalon 2006.145.01:31:17.58&pcalon/"no phase cal control is implemented here 2006.145.01:31:17.58$pcalon/"no phase cal control is implemented here 2006.145.01:31:17.58$setupk4/"tpicd=stop 2006.145.01:31:17.58$setupk4/"rec=synch_on 2006.145.01:31:17.58$setupk4/"rec_mode=128 2006.145.01:31:17.58$setupk4/!* 2006.145.01:31:17.58$setupk4/recpk4 2006.145.01:31:17.58&recpk4/recpatch= 2006.145.01:31:17.58&recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.01:31:17.58&recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.01:31:17.58$recpk4/recpatch= 2006.145.01:31:17.58$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.01:31:17.58$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.01:31:17.58$setupk4/vck44 2006.145.01:31:17.58&vck44/valo=1,524.99 2006.145.01:31:17.58&vck44/va=1,8 2006.145.01:31:17.58&vck44/valo=2,534.99 2006.145.01:31:17.58&vck44/va=2,7 2006.145.01:31:17.58&vck44/valo=3,564.99 2006.145.01:31:17.58&vck44/va=3,8 2006.145.01:31:17.58&vck44/valo=4,624.99 2006.145.01:31:17.58&vck44/va=4,7 2006.145.01:31:17.58&vck44/valo=5,734.99 2006.145.01:31:17.58&vck44/va=5,4 2006.145.01:31:17.58&vck44/valo=6,814.99 2006.145.01:31:17.58&vck44/va=6,4 2006.145.01:31:17.58&vck44/valo=7,864.99 2006.145.01:31:17.58&vck44/va=7,4 2006.145.01:31:17.58&vck44/valo=8,884.99 2006.145.01:31:17.58&vck44/va=8,4 2006.145.01:31:17.58&vck44/vblo=1,629.99 2006.145.01:31:17.58&vck44/vb=1,3 2006.145.01:31:17.58&vck44/vblo=2,634.99 2006.145.01:31:17.58&vck44/vb=2,4 2006.145.01:31:17.58&vck44/vblo=3,649.99 2006.145.01:31:17.58&vck44/vb=3,4 2006.145.01:31:17.58&vck44/vblo=4,679.99 2006.145.01:31:17.58&vck44/vb=4,4 2006.145.01:31:17.58&vck44/vblo=5,709.99 2006.145.01:31:17.58&vck44/vb=5,4 2006.145.01:31:17.58&vck44/vblo=6,719.99 2006.145.01:31:17.58&vck44/vb=6,4 2006.145.01:31:17.58&vck44/vblo=7,734.99 2006.145.01:31:17.58&vck44/vb=7,4 2006.145.01:31:17.58&vck44/vblo=8,744.99 2006.145.01:31:17.58&vck44/vb=8,4 2006.145.01:31:17.58&vck44/vabw=wide 2006.145.01:31:17.58&vck44/vbbw=wide 2006.145.01:31:17.59$vck44/valo=1,524.99 2006.145.01:31:17.59#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.01:31:17.59#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.01:31:17.59#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:17.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.01:31:17.59#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.01:31:17.59#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.01:31:17.63#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.01:31:17.69#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.01:31:17.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.01:31:17.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.01:31:17.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.01:31:17.69$vck44/va=1,8 2006.145.01:31:17.69#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.01:31:17.69#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.01:31:17.69#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:17.69#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.01:31:17.69#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.01:31:17.69#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.01:31:17.71#ibcon#[25=AT01-08\r\n] 2006.145.01:31:17.74#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.01:31:17.74#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.01:31:17.74#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.01:31:17.74#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:17.74#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.01:31:17.86#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.01:31:17.86#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.01:31:17.88#ibcon#[25=USB\r\n] 2006.145.01:31:17.91#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.01:31:17.91#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.01:31:17.91#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.01:31:17.91#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.01:31:17.91$vck44/valo=2,534.99 2006.145.01:31:17.91#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.01:31:17.91#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.01:31:17.91#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:17.91#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.01:31:17.91#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.01:31:17.91#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.01:31:17.95#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.01:31:17.99#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.01:31:17.99#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.01:31:17.99#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.01:31:17.99#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.01:31:17.99$vck44/va=2,7 2006.145.01:31:17.99#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.01:31:17.99#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.01:31:17.99#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:17.99#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.01:31:18.03#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.01:31:18.03#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.01:31:18.05#ibcon#[25=AT02-07\r\n] 2006.145.01:31:18.09#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.01:31:18.09#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.01:31:18.09#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.01:31:18.09#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:18.09#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.01:31:18.23#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.01:31:18.23#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.01:31:18.24#ibcon#[25=USB\r\n] 2006.145.01:31:18.27#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.01:31:18.27#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.01:31:18.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.01:31:18.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.01:31:18.27$vck44/valo=3,564.99 2006.145.01:31:18.27#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.01:31:18.27#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.01:31:18.27#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:18.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.01:31:18.27#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.01:31:18.27#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.01:31:18.29#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.01:31:18.33#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.01:31:18.33#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.01:31:18.33#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.01:31:18.33#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.01:31:18.33$vck44/va=3,8 2006.145.01:31:18.33#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.01:31:18.33#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.01:31:18.33#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:18.33#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.01:31:18.39#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.01:31:18.39#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.01:31:18.41#ibcon#[25=AT03-08\r\n] 2006.145.01:31:18.44#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.01:31:18.44#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.01:31:18.44#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.01:31:18.44#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:18.44#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.01:31:18.56#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.01:31:18.56#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.01:31:18.58#ibcon#[25=USB\r\n] 2006.145.01:31:18.60#abcon#<5=/05 3.3 6.7 19.35 651017.3\r\n> 2006.145.01:31:18.61#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.01:31:18.61#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.01:31:18.61#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.01:31:18.61#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.01:31:18.61$vck44/valo=4,624.99 2006.145.01:31:18.61#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.01:31:18.61#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.01:31:18.61#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:18.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.01:31:18.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.01:31:18.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.01:31:18.62#abcon#{5=INTERFACE CLEAR} 2006.145.01:31:18.63#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.01:31:18.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.01:31:18.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.01:31:18.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.01:31:18.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.01:31:18.67$vck44/va=4,7 2006.145.01:31:18.67#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.01:31:18.67#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.01:31:18.67#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:18.67#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.01:31:18.68#abcon#[5=S1D000X0/0*\r\n] 2006.145.01:31:18.73#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.01:31:18.73#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.01:31:18.75#ibcon#[25=AT04-07\r\n] 2006.145.01:31:18.78#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.01:31:18.78#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.01:31:18.78#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.01:31:18.78#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:18.78#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.01:31:18.90#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.01:31:18.90#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.01:31:18.92#ibcon#[25=USB\r\n] 2006.145.01:31:18.95#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.01:31:18.95#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.01:31:18.95#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.01:31:18.95#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.01:31:18.95$vck44/valo=5,734.99 2006.145.01:31:18.95#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.01:31:18.95#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.01:31:18.95#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:18.95#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.01:31:18.95#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.01:31:18.95#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.01:31:18.99#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.01:31:19.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.01:31:19.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.01:31:19.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.01:31:19.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.01:31:19.03$vck44/va=5,4 2006.145.01:31:19.03#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.01:31:19.03#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.01:31:19.03#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:19.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.01:31:19.07#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.01:31:19.07#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.01:31:19.09#ibcon#[25=AT05-04\r\n] 2006.145.01:31:19.12#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.01:31:19.12#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.01:31:19.12#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.01:31:19.12#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:19.12#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.01:31:19.24#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.01:31:19.24#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.01:31:19.26#ibcon#[25=USB\r\n] 2006.145.01:31:19.29#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.01:31:19.29#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.01:31:19.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.01:31:19.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.01:31:19.29$vck44/valo=6,814.99 2006.145.01:31:19.29#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.01:31:19.29#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.01:31:19.29#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:19.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.01:31:19.29#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.01:31:19.29#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.01:31:19.31#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.01:31:19.35#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.01:31:19.35#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.01:31:19.35#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.01:31:19.35#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.01:31:19.35$vck44/va=6,4 2006.145.01:31:19.35#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.01:31:19.35#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.01:31:19.35#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:19.35#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.01:31:19.41#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.01:31:19.41#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.01:31:19.43#ibcon#[25=AT06-04\r\n] 2006.145.01:31:19.46#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.01:31:19.46#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.01:31:19.46#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.01:31:19.46#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:19.46#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.01:31:19.58#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.01:31:19.58#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.01:31:19.60#ibcon#[25=USB\r\n] 2006.145.01:31:19.63#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.01:31:19.63#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.01:31:19.63#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.01:31:19.63#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.01:31:19.63$vck44/valo=7,864.99 2006.145.01:31:19.63#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.01:31:19.63#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.01:31:19.63#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:19.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.01:31:19.63#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.01:31:19.63#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.01:31:19.65#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.01:31:19.69#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.01:31:19.69#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.01:31:19.69#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.01:31:19.69#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.01:31:19.69$vck44/va=7,4 2006.145.01:31:19.69#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.01:31:19.69#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.01:31:19.69#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:19.69#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.01:31:19.75#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.01:31:19.75#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.01:31:19.77#ibcon#[25=AT07-04\r\n] 2006.145.01:31:19.80#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.01:31:19.80#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.01:31:19.80#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.01:31:19.80#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:19.80#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.01:31:19.92#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.01:31:19.92#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.01:31:19.94#ibcon#[25=USB\r\n] 2006.145.01:31:19.97#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.01:31:19.97#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.01:31:19.97#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.01:31:19.97#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.01:31:19.97$vck44/valo=8,884.99 2006.145.01:31:19.97#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.01:31:19.97#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.01:31:19.97#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:19.97#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.01:31:19.97#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.01:31:19.97#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.01:31:19.99#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.01:31:20.03#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.01:31:20.03#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.01:31:20.03#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.01:31:20.03#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.01:31:20.03$vck44/va=8,4 2006.145.01:31:20.03#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.01:31:20.03#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.01:31:20.03#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:20.03#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.01:31:20.09#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.01:31:20.09#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.01:31:20.11#ibcon#[25=AT08-04\r\n] 2006.145.01:31:20.14#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.01:31:20.14#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.01:31:20.14#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.01:31:20.14#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:20.14#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.01:31:20.26#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.01:31:20.26#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.01:31:20.28#ibcon#[25=USB\r\n] 2006.145.01:31:20.31#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.01:31:20.31#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.01:31:20.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.01:31:20.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.01:31:20.31$vck44/vblo=1,629.99 2006.145.01:31:20.31#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.01:31:20.31#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.01:31:20.31#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:20.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.01:31:20.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.01:31:20.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.01:31:20.33#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.01:31:20.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.01:31:20.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.01:31:20.39#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.01:31:20.39#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.01:31:20.39$vck44/vb=1,3 2006.145.01:31:20.39#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.01:31:20.39#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.01:31:20.39#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:20.39#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.01:31:20.39#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.01:31:20.39#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.01:31:20.41#ibcon#[27=AT01-03\r\n] 2006.145.01:31:20.44#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.01:31:20.44#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.01:31:20.44#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.01:31:20.44#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:20.44#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.01:31:20.56#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.01:31:20.56#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.01:31:20.58#ibcon#[27=USB\r\n] 2006.145.01:31:20.61#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.01:31:20.61#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.01:31:20.61#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.01:31:20.61#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.01:31:20.61$vck44/vblo=2,634.99 2006.145.01:31:20.61#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.01:31:20.61#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.01:31:20.61#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:20.61#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.01:31:20.61#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.01:31:20.61#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.01:31:20.63#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.01:31:20.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.01:31:20.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.01:31:20.67#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.01:31:20.67#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.01:31:20.67$vck44/vb=2,4 2006.145.01:31:20.67#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.01:31:20.67#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.01:31:20.67#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:20.67#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.01:31:20.73#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.01:31:20.73#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.01:31:20.75#ibcon#[27=AT02-04\r\n] 2006.145.01:31:20.78#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.01:31:20.78#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.01:31:20.78#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.01:31:20.78#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:20.78#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.01:31:20.90#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.01:31:20.90#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.01:31:20.92#ibcon#[27=USB\r\n] 2006.145.01:31:20.95#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.01:31:20.95#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.01:31:20.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.01:31:20.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.01:31:20.95$vck44/vblo=3,649.99 2006.145.01:31:20.95#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.01:31:20.95#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.01:31:20.95#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:20.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.01:31:20.95#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.01:31:20.95#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.01:31:20.97#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.01:31:21.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.01:31:21.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.01:31:21.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.01:31:21.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.01:31:21.01$vck44/vb=3,4 2006.145.01:31:21.01#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.01:31:21.01#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.01:31:21.01#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:21.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.01:31:21.07#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.01:31:21.07#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.01:31:21.09#ibcon#[27=AT03-04\r\n] 2006.145.01:31:21.12#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.01:31:21.12#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.01:31:21.12#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.01:31:21.12#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:21.12#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.01:31:21.24#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.01:31:21.24#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.01:31:21.26#ibcon#[27=USB\r\n] 2006.145.01:31:21.29#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.01:31:21.29#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.01:31:21.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.01:31:21.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.01:31:21.29$vck44/vblo=4,679.99 2006.145.01:31:21.29#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.01:31:21.29#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.01:31:21.29#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:21.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.01:31:21.29#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.01:31:21.29#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.01:31:21.31#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.01:31:21.35#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.01:31:21.35#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.01:31:21.35#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.01:31:21.35#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.01:31:21.35$vck44/vb=4,4 2006.145.01:31:21.35#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.01:31:21.35#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.01:31:21.35#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:21.35#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.01:31:21.41#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.01:31:21.41#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.01:31:21.43#ibcon#[27=AT04-04\r\n] 2006.145.01:31:21.46#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.01:31:21.46#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.01:31:21.46#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.01:31:21.46#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:21.46#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.01:31:21.58#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.01:31:21.58#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.01:31:21.60#ibcon#[27=USB\r\n] 2006.145.01:31:21.63#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.01:31:21.63#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.01:31:21.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.01:31:21.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.01:31:21.63$vck44/vblo=5,709.99 2006.145.01:31:21.63#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.01:31:21.63#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.01:31:21.63#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:21.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.01:31:21.63#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.01:31:21.63#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.01:31:21.65#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.01:31:21.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.01:31:21.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.01:31:21.69#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.01:31:21.69#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.01:31:21.69$vck44/vb=5,4 2006.145.01:31:21.69#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.01:31:21.69#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.01:31:21.69#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:21.69#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.01:31:21.75#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.01:31:21.75#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.01:31:21.77#ibcon#[27=AT05-04\r\n] 2006.145.01:31:21.80#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.01:31:21.80#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.01:31:21.80#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.01:31:21.80#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:21.80#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.01:31:21.92#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.01:31:21.92#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.01:31:21.94#ibcon#[27=USB\r\n] 2006.145.01:31:21.97#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.01:31:21.97#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.01:31:21.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.01:31:21.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.01:31:21.97$vck44/vblo=6,719.99 2006.145.01:31:21.97#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.01:31:21.97#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.01:31:21.97#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:21.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.01:31:21.97#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.01:31:21.97#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.01:31:21.99#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.01:31:22.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.01:31:22.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.01:31:22.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.01:31:22.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.01:31:22.03$vck44/vb=6,4 2006.145.01:31:22.03#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.01:31:22.03#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.01:31:22.03#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:22.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.01:31:22.09#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.01:31:22.09#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.01:31:22.11#ibcon#[27=AT06-04\r\n] 2006.145.01:31:22.14#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.01:31:22.14#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.01:31:22.14#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.01:31:22.14#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:22.14#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.01:31:22.26#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.01:31:22.26#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.01:31:22.28#ibcon#[27=USB\r\n] 2006.145.01:31:22.31#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.01:31:22.31#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.01:31:22.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.01:31:22.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.01:31:22.31$vck44/vblo=7,734.99 2006.145.01:31:22.31#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.01:31:22.31#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.01:31:22.31#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:22.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.01:31:22.31#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.01:31:22.31#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.01:31:22.33#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.01:31:22.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.01:31:22.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.01:31:22.37#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.01:31:22.37#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.01:31:22.37$vck44/vb=7,4 2006.145.01:31:22.37#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.01:31:22.37#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.01:31:22.37#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:22.37#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.01:31:22.43#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.01:31:22.43#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.01:31:22.45#ibcon#[27=AT07-04\r\n] 2006.145.01:31:22.48#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.01:31:22.48#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.01:31:22.48#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.01:31:22.48#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:22.48#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.01:31:22.60#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.01:31:22.60#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.01:31:22.62#ibcon#[27=USB\r\n] 2006.145.01:31:22.65#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.01:31:22.65#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.01:31:22.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.01:31:22.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.01:31:22.65$vck44/vblo=8,744.99 2006.145.01:31:22.65#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.01:31:22.65#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.01:31:22.65#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:22.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.01:31:22.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.01:31:22.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.01:31:22.67#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.01:31:22.71#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.01:31:22.71#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.01:31:22.71#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.01:31:22.71#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.01:31:22.71$vck44/vb=8,4 2006.145.01:31:22.71#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.01:31:22.71#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.01:31:22.71#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:22.71#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.01:31:22.77#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.01:31:22.77#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.01:31:22.79#ibcon#[27=AT08-04\r\n] 2006.145.01:31:22.82#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.01:31:22.82#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.01:31:22.82#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.01:31:22.82#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:22.82#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.01:31:22.94#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.01:31:22.94#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.01:31:22.96#ibcon#[27=USB\r\n] 2006.145.01:31:23.00#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.01:31:23.00#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.01:31:23.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.01:31:23.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.01:31:23.00$vck44/vabw=wide 2006.145.01:31:23.00#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.01:31:23.00#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.01:31:23.00#ibcon#ireg 8 cls_cnt 0 2006.145.01:31:23.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.01:31:23.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.01:31:23.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.01:31:23.01#ibcon#[25=BW32\r\n] 2006.145.01:31:23.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.01:31:23.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.01:31:23.04#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.01:31:23.04#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.01:31:23.04$vck44/vbbw=wide 2006.145.01:31:23.04#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.01:31:23.04#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.01:31:23.04#ibcon#ireg 8 cls_cnt 0 2006.145.01:31:23.04#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.01:31:23.12#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.01:31:23.12#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.01:31:23.14#ibcon#[27=BW32\r\n] 2006.145.01:31:23.17#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.01:31:23.17#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.01:31:23.17#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.01:31:23.17#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.01:31:23.17$setupk4/ifdk4 2006.145.01:31:23.17&ifdk4/lo= 2006.145.01:31:23.17&ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.01:31:23.17&ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.01:31:23.17&ifdk4/patch= 2006.145.01:31:23.17&ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.01:31:23.17&ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.01:31:23.17$ifdk4/lo= 2006.145.01:31:23.17$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.01:31:23.17$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.01:31:23.17$ifdk4/patch= 2006.145.01:31:23.17$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.01:31:23.17$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.01:31:23.17$setupk4/!*+20s 2006.145.01:31:23.17$exper_initi/proc_library 2006.145.01:31:23.17&proc_library/" jd0605 tsukub32 ts 2006.145.01:31:23.17&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.145.01:31:23.17&proc_library/"< k4-2/m4 rack >< k4-2 recorder 1> 2006.145.01:31:23.17$proc_library/" jd0605 tsukub32 ts 2006.145.01:31:23.17$proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.145.01:31:23.17$proc_library/"< k4-2/m4 rack >< k4-2 recorder 1> 2006.145.01:31:23.17$exper_initi/sched_initi 2006.145.01:31:23.17&sched_initi/startcheck 2006.145.01:31:23.17$sched_initi/startcheck 2006.145.01:31:23.17&startcheck/sy=check_fsrun.pl & 2006.145.01:31:23.17&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.145.01:31:23.17$startcheck/sy=check_fsrun.pl & 2006.145.01:31:23.24$startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.145.01:31:28.77#abcon#<5=/05 3.3 6.7 19.35 661017.3\r\n> 2006.145.01:31:28.79#abcon#{5=INTERFACE CLEAR} 2006.145.01:31:28.85#abcon#[5=S1D000X0/0*\r\n] 2006.145.01:31:37.60$setupk4/"tpicd 2006.145.01:31:37.60$setupk4/echo=off 2006.145.01:31:37.60$setupk4/xlog=off 2006.145.01:31:37.60:"ready=1 2006.145.01:31:37.60:setupk4=1 2006.145.01:31:37.60$setupk4/echo=on 2006.145.01:31:37.60$setupk4/pcalon 2006.145.01:31:37.60$pcalon/"no phase cal control is implemented here 2006.145.01:31:37.60$setupk4/"tpicd=stop 2006.145.01:31:37.60$setupk4/"rec=synch_on 2006.145.01:31:37.60$setupk4/"rec_mode=128 2006.145.01:31:37.60$setupk4/!* 2006.145.01:31:37.60$setupk4/recpk4 2006.145.01:31:37.60$recpk4/recpatch= 2006.145.01:31:37.60$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.01:31:37.60$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.01:31:37.60$setupk4/vck44 2006.145.01:31:37.60$vck44/valo=1,524.99 2006.145.01:31:37.60#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.01:31:37.60#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.01:31:37.60#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:37.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.01:31:37.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.01:31:37.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.01:31:37.62#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.01:31:37.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.01:31:37.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.01:31:37.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.01:31:37.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.01:31:37.66$vck44/va=1,8 2006.145.01:31:37.66#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.01:31:37.66#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.01:31:37.66#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:37.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.01:31:37.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.01:31:37.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.01:31:37.68#ibcon#[25=AT01-08\r\n] 2006.145.01:31:37.71#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.01:31:37.71#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.01:31:37.71#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.01:31:37.71#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:37.71#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.01:31:37.83#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.01:31:37.83#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.01:31:37.85#ibcon#[25=USB\r\n] 2006.145.01:31:37.88#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.01:31:37.88#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.01:31:37.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.01:31:37.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.01:31:37.88$vck44/valo=2,534.99 2006.145.01:31:37.88#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.01:31:37.88#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.01:31:37.88#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:37.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.01:31:37.88#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.01:31:37.88#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.01:31:37.90#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.01:31:37.94#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.01:31:37.94#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.01:31:37.94#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.01:31:37.94#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.01:31:37.94$vck44/va=2,7 2006.145.01:31:37.94#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.01:31:37.94#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.01:31:37.94#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:37.94#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.01:31:38.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.01:31:38.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.01:31:38.02#ibcon#[25=AT02-07\r\n] 2006.145.01:31:38.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.01:31:38.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.01:31:38.05#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.01:31:38.05#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:38.05#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.01:31:38.17#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.01:31:38.17#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.01:31:38.19#ibcon#[25=USB\r\n] 2006.145.01:31:38.22#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.01:31:38.22#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.01:31:38.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.01:31:38.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.01:31:38.22$vck44/valo=3,564.99 2006.145.01:31:38.22#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.01:31:38.22#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.01:31:38.22#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:38.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.01:31:38.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.01:31:38.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.01:31:38.24#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.01:31:38.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.01:31:38.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.01:31:38.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.01:31:38.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.01:31:38.28$vck44/va=3,8 2006.145.01:31:38.28#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.01:31:38.28#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.01:31:38.28#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:38.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.01:31:38.34#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.01:31:38.34#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.01:31:38.36#ibcon#[25=AT03-08\r\n] 2006.145.01:31:38.42#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.01:31:38.42#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.01:31:38.42#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.01:31:38.42#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:38.42#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.01:31:38.53#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.01:31:38.53#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.01:31:38.55#ibcon#[25=USB\r\n] 2006.145.01:31:38.58#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.01:31:38.58#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.01:31:38.58#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.01:31:38.58#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.01:31:38.58$vck44/valo=4,624.99 2006.145.01:31:38.58#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.01:31:38.58#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.01:31:38.58#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:38.58#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.01:31:38.58#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.01:31:38.58#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.01:31:38.60#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.01:31:38.64#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.01:31:38.64#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.01:31:38.64#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.01:31:38.64#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.01:31:38.64$vck44/va=4,7 2006.145.01:31:38.64#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.01:31:38.64#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.01:31:38.64#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:38.64#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.01:31:38.70#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.01:31:38.70#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.01:31:38.72#ibcon#[25=AT04-07\r\n] 2006.145.01:31:38.75#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.01:31:38.75#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.01:31:38.75#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.01:31:38.75#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:38.75#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.01:31:38.87#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.01:31:38.87#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.01:31:38.89#ibcon#[25=USB\r\n] 2006.145.01:31:38.92#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.01:31:38.92#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.01:31:38.92#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.01:31:38.92#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.01:31:38.92$vck44/valo=5,734.99 2006.145.01:31:38.92#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.01:31:38.92#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.01:31:38.92#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:38.92#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.01:31:38.92#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.01:31:38.92#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.01:31:38.94#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.01:31:38.94#abcon#<5=/05 3.3 6.7 19.34 671017.3\r\n> 2006.145.01:31:38.96#abcon#{5=INTERFACE CLEAR} 2006.145.01:31:38.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.01:31:38.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.01:31:38.98#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.01:31:38.98#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.01:31:38.98$vck44/va=5,4 2006.145.01:31:38.98#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.01:31:38.98#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.01:31:38.98#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:38.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.01:31:39.02#abcon#[5=S1D000X0/0*\r\n] 2006.145.01:31:39.04#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.01:31:39.04#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.01:31:39.06#ibcon#[25=AT05-04\r\n] 2006.145.01:31:39.09#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.01:31:39.09#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.01:31:39.09#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.01:31:39.09#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:39.09#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.01:31:39.21#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.01:31:39.21#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.01:31:39.23#ibcon#[25=USB\r\n] 2006.145.01:31:39.26#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.01:31:39.26#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.01:31:39.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.01:31:39.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.01:31:39.26$vck44/valo=6,814.99 2006.145.01:31:39.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.01:31:39.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.01:31:39.26#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:39.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.01:31:39.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.01:31:39.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.01:31:39.28#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.01:31:39.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.01:31:39.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.01:31:39.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.01:31:39.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.01:31:39.32$vck44/va=6,4 2006.145.01:31:39.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.01:31:39.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.01:31:39.32#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:39.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.01:31:39.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.01:31:39.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.01:31:39.40#ibcon#[25=AT06-04\r\n] 2006.145.01:31:39.43#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.01:31:39.43#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.01:31:39.43#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.01:31:39.43#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:39.43#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.01:31:39.55#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.01:31:39.55#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.01:31:39.57#ibcon#[25=USB\r\n] 2006.145.01:31:39.60#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.01:31:39.60#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.01:31:39.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.01:31:39.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.01:31:39.60$vck44/valo=7,864.99 2006.145.01:31:39.60#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.01:31:39.60#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.01:31:39.60#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:39.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.01:31:39.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.01:31:39.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.01:31:39.62#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.01:31:39.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.01:31:39.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.01:31:39.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.01:31:39.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.01:31:39.66$vck44/va=7,4 2006.145.01:31:39.66#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.01:31:39.66#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.01:31:39.66#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:39.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.01:31:39.72#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.01:31:39.72#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.01:31:39.74#ibcon#[25=AT07-04\r\n] 2006.145.01:31:39.77#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.01:31:39.77#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.01:31:39.77#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.01:31:39.77#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:39.77#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.01:31:39.89#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.01:31:39.89#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.01:31:39.91#ibcon#[25=USB\r\n] 2006.145.01:31:39.94#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.01:31:39.94#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.01:31:39.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.01:31:39.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.01:31:39.94$vck44/valo=8,884.99 2006.145.01:31:39.94#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.01:31:39.94#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.01:31:39.94#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:39.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.01:31:39.94#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.01:31:39.94#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.01:31:39.96#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.01:31:40.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.01:31:40.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.01:31:40.00#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.01:31:40.00#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.01:31:40.00$vck44/va=8,4 2006.145.01:31:40.00#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.01:31:40.00#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.01:31:40.00#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:40.00#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.01:31:40.06#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.01:31:40.06#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.01:31:40.08#ibcon#[25=AT08-04\r\n] 2006.145.01:31:40.11#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.01:31:40.11#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.01:31:40.11#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.01:31:40.11#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:40.11#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.01:31:40.23#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.01:31:40.23#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.01:31:40.25#ibcon#[25=USB\r\n] 2006.145.01:31:40.28#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.01:31:40.28#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.01:31:40.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.01:31:40.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.01:31:40.28$vck44/vblo=1,629.99 2006.145.01:31:40.28#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.01:31:40.28#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.01:31:40.28#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:40.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.01:31:40.28#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.01:31:40.28#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.01:31:40.30#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.01:31:40.35#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.01:31:40.35#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.01:31:40.35#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.01:31:40.35#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.01:31:40.35$vck44/vb=1,3 2006.145.01:31:40.35#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.01:31:40.35#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.01:31:40.35#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:40.35#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.01:31:40.35#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.01:31:40.35#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.01:31:40.36#ibcon#[27=AT01-03\r\n] 2006.145.01:31:40.39#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.01:31:40.39#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.01:31:40.39#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.01:31:40.39#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:40.39#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.01:31:40.51#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.01:31:40.51#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.01:31:40.53#ibcon#[27=USB\r\n] 2006.145.01:31:40.56#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.01:31:40.56#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.01:31:40.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.01:31:40.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.01:31:40.56$vck44/vblo=2,634.99 2006.145.01:31:40.56#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.01:31:40.56#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.01:31:40.56#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:40.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.01:31:40.56#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.01:31:40.56#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.01:31:40.58#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.01:31:40.62#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.01:31:40.62#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.01:31:40.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.01:31:40.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.01:31:40.62$vck44/vb=2,4 2006.145.01:31:40.62#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.01:31:40.62#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.01:31:40.62#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:40.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.01:31:40.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.01:31:40.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.01:31:40.70#ibcon#[27=AT02-04\r\n] 2006.145.01:31:40.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.01:31:40.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.01:31:40.73#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.01:31:40.73#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:40.73#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.01:31:40.85#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.01:31:40.85#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.01:31:40.87#ibcon#[27=USB\r\n] 2006.145.01:31:40.90#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.01:31:40.90#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.01:31:40.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.01:31:40.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.01:31:40.90$vck44/vblo=3,649.99 2006.145.01:31:40.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.01:31:40.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.01:31:40.90#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:40.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.01:31:40.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.01:31:40.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.01:31:40.92#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.01:31:40.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.01:31:40.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.01:31:40.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.01:31:40.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.01:31:40.96$vck44/vb=3,4 2006.145.01:31:40.96#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.01:31:40.96#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.01:31:40.96#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:40.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.01:31:41.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.01:31:41.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.01:31:41.04#ibcon#[27=AT03-04\r\n] 2006.145.01:31:41.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.01:31:41.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.01:31:41.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.01:31:41.07#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:41.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.01:31:41.14#trakl#Source acquired 2006.145.01:31:41.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.01:31:41.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.01:31:41.21#ibcon#[27=USB\r\n] 2006.145.01:31:41.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.01:31:41.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.01:31:41.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.01:31:41.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.01:31:41.24$vck44/vblo=4,679.99 2006.145.01:31:41.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.01:31:41.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.01:31:41.24#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:41.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.01:31:41.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.01:31:41.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.01:31:41.26#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.01:31:41.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.01:31:41.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.01:31:41.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.01:31:41.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.01:31:41.30$vck44/vb=4,4 2006.145.01:31:41.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.01:31:41.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.01:31:41.30#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:41.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.01:31:41.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.01:31:41.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.01:31:41.38#ibcon#[27=AT04-04\r\n] 2006.145.01:31:41.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.01:31:41.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.01:31:41.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.01:31:41.41#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:41.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.01:31:41.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.01:31:41.53#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.01:31:41.55#ibcon#[27=USB\r\n] 2006.145.01:31:41.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.01:31:41.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.01:31:41.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.01:31:41.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.01:31:41.58$vck44/vblo=5,709.99 2006.145.01:31:41.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.01:31:41.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.01:31:41.58#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:41.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.01:31:41.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.01:31:41.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.01:31:41.60#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.01:31:41.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.01:31:41.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.01:31:41.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.01:31:41.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.01:31:41.64$vck44/vb=5,4 2006.145.01:31:41.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.01:31:41.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.01:31:41.64#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:41.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.01:31:41.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.01:31:41.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.01:31:41.72#ibcon#[27=AT05-04\r\n] 2006.145.01:31:41.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.01:31:41.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.01:31:41.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.01:31:41.75#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:41.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.01:31:41.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.01:31:41.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.01:31:41.89#ibcon#[27=USB\r\n] 2006.145.01:31:41.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.01:31:41.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.01:31:41.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.01:31:41.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.01:31:41.92$vck44/vblo=6,719.99 2006.145.01:31:41.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.01:31:41.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.01:31:41.92#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:41.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.01:31:41.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.01:31:41.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.01:31:41.94#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.01:31:41.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.01:31:41.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.01:31:41.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.01:31:41.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.01:31:41.98$vck44/vb=6,4 2006.145.01:31:41.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.01:31:41.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.01:31:41.98#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:41.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.01:31:42.06#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.01:31:42.06#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.01:31:42.08#ibcon#[27=AT06-04\r\n] 2006.145.01:31:42.11#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.01:31:42.11#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.01:31:42.11#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.01:31:42.11#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:42.11#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.01:31:42.23#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.01:31:42.23#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.01:31:42.25#ibcon#[27=USB\r\n] 2006.145.01:31:42.28#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.01:31:42.28#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.01:31:42.28#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.01:31:42.28#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.01:31:42.28$vck44/vblo=7,734.99 2006.145.01:31:42.28#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.01:31:42.28#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.01:31:42.28#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:42.28#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.01:31:42.28#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.01:31:42.28#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.01:31:42.30#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.01:31:42.34#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.01:31:42.34#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.01:31:42.34#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.01:31:42.34#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.01:31:42.34$vck44/vb=7,4 2006.145.01:31:42.34#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.01:31:42.34#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.01:31:42.34#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:42.34#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.01:31:42.40#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.01:31:42.40#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.01:31:42.42#ibcon#[27=AT07-04\r\n] 2006.145.01:31:42.45#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.01:31:42.45#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.01:31:42.45#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.01:31:42.45#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:42.45#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.01:31:42.57#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.01:31:42.57#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.01:31:42.59#ibcon#[27=USB\r\n] 2006.145.01:31:42.62#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.01:31:42.62#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.01:31:42.62#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.01:31:42.62#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.01:31:42.62$vck44/vblo=8,744.99 2006.145.01:31:42.62#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.01:31:42.62#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.01:31:42.62#ibcon#ireg 17 cls_cnt 0 2006.145.01:31:42.62#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.01:31:42.62#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.01:31:42.62#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.01:31:42.64#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.01:31:42.68#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.01:31:42.68#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.01:31:42.68#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.01:31:42.68#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.01:31:42.68$vck44/vb=8,4 2006.145.01:31:42.68#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.01:31:42.68#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.01:31:42.68#ibcon#ireg 11 cls_cnt 2 2006.145.01:31:42.68#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.01:31:42.74#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.01:31:42.74#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.01:31:42.76#ibcon#[27=AT08-04\r\n] 2006.145.01:31:42.79#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.01:31:42.79#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.01:31:42.79#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.01:31:42.79#ibcon#ireg 7 cls_cnt 0 2006.145.01:31:42.79#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.01:31:42.91#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.01:31:42.91#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.01:31:42.93#ibcon#[27=USB\r\n] 2006.145.01:31:42.96#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.01:31:42.96#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.01:31:42.96#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.01:31:42.96#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.01:31:42.96$vck44/vabw=wide 2006.145.01:31:42.96#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.01:31:42.96#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.01:31:42.96#ibcon#ireg 8 cls_cnt 0 2006.145.01:31:42.96#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.01:31:42.96#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.01:31:42.96#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.01:31:42.98#ibcon#[25=BW32\r\n] 2006.145.01:31:43.01#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.01:31:43.01#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.01:31:43.01#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.01:31:43.01#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.01:31:43.01$vck44/vbbw=wide 2006.145.01:31:43.01#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.01:31:43.01#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.01:31:43.01#ibcon#ireg 8 cls_cnt 0 2006.145.01:31:43.01#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.01:31:43.08#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.01:31:43.08#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.01:31:43.10#ibcon#[27=BW32\r\n] 2006.145.01:31:43.13#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.01:31:43.13#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.01:31:43.13#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.01:31:43.13#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.01:31:43.13$setupk4/ifdk4 2006.145.01:31:43.13$ifdk4/lo= 2006.145.01:31:43.13$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.01:31:43.13$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.01:31:43.13$ifdk4/patch= 2006.145.01:31:43.13$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.01:31:43.13$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.01:31:43.13$setupk4/!*+20s 2006.145.01:31:43.14#flagr#flagr/antenna,acquired 2006.145.01:31:49.11#abcon#<5=/05 3.3 6.7 19.34 671017.3\r\n> 2006.145.01:31:49.13#abcon#{5=INTERFACE CLEAR} 2006.145.01:31:49.19#abcon#[5=S1D000X0/0*\r\n] 2006.145.01:31:57.61$setupk4/"tpicd 2006.145.01:31:57.61$setupk4/echo=off 2006.145.01:31:57.61$setupk4/xlog=off 2006.145.01:31:57.61:!2006.145.01:59:50 2006.145.01:32:54.70;"cable normal 2006.145.01:32:57.99;cable 2006.145.01:32:58.06/cable/+6.5499E-03 2006.145.01:33:59.17;"cable long 2006.145.01:34:02.68;cablelong 2006.145.01:34:02.77/cablelong/+7.1007E-03 2006.145.01:34:05.81;cablediff 2006.145.01:34:05.81/cablediff/550.8e-6,+ 2006.145.01:35:09.20;"cable normal again 2006.145.01:35:13.22;cable 2006.145.01:35:13.29/cable/+6.5516E-03 2006.145.01:35:22.48;wx 2006.145.01:35:22.48/wx/19.40,1017.3,69 2006.145.01:35:31.51;"Sky is fine. 2006.145.01:35:36.94;xfe 2006.145.01:35:37.02/xfe/off,on,15.2 2006.145.01:35:42.56;clockoff 2006.145.01:35:42.56&clockoff/"gps-fmout=1p 2006.145.01:35:42.56&clockoff/fmout-gps=1p 2006.145.01:35:43.07/fmout-gps/S +4.8E-08 2006.145.01:59:50.00:preob 2006.145.01:59:50.00&preob/onsource 2006.145.01:59:50.14/onsource/TRACKING 2006.145.01:59:50.14:!2006.145.02:00:00 2006.145.02:00:00.00:"tape 2006.145.02:00:00.00:"st=record 2006.145.02:00:00.00:data_valid=on 2006.145.02:00:00.00:midob 2006.145.02:00:00.00&midob/onsource 2006.145.02:00:00.00&midob/wx 2006.145.02:00:00.00&midob/cable 2006.145.02:00:00.00&midob/va 2006.145.02:00:00.00&midob/valo 2006.145.02:00:00.00&midob/vb 2006.145.02:00:00.00&midob/vblo 2006.145.02:00:00.00&midob/vabw 2006.145.02:00:00.00&midob/vbbw 2006.145.02:00:00.00&midob/"form 2006.145.02:00:00.00&midob/xfe 2006.145.02:00:00.00&midob/ifatt 2006.145.02:00:00.00&midob/clockoff 2006.145.02:00:00.00&midob/sy=logmail 2006.145.02:00:00.00&midob/"sy=run setcl adapt & 2006.145.02:00:01.14/onsource/TRACKING 2006.145.02:00:01.14/wx/19.41,1017.2,70 2006.145.02:00:01.29/cable/+6.5535E-03 2006.145.02:00:02.38/va/01,08,usb,yes,30,32 2006.145.02:00:02.38/va/02,07,usb,yes,32,32 2006.145.02:00:02.38/va/03,08,usb,yes,29,30 2006.145.02:00:02.38/va/04,07,usb,yes,33,34 2006.145.02:00:02.38/va/05,04,usb,yes,28,29 2006.145.02:00:02.38/va/06,04,usb,yes,32,32 2006.145.02:00:02.38/va/07,04,usb,yes,32,34 2006.145.02:00:02.38/va/08,04,usb,yes,27,33 2006.145.02:00:02.61/valo/01,524.99,yes,locked 2006.145.02:00:02.61/valo/02,534.99,yes,locked 2006.145.02:00:02.61/valo/03,564.99,yes,locked 2006.145.02:00:02.61/valo/04,624.99,yes,locked 2006.145.02:00:02.61/valo/05,734.99,yes,locked 2006.145.02:00:02.61/valo/06,814.99,yes,locked 2006.145.02:00:02.61/valo/07,864.99,yes,locked 2006.145.02:00:02.61/valo/08,884.99,yes,locked 2006.145.02:00:03.70/vb/01,03,usb,yes,37,35 2006.145.02:00:03.70/vb/02,04,usb,yes,33,32 2006.145.02:00:03.70/vb/03,04,usb,yes,29,32 2006.145.02:00:03.70/vb/04,04,usb,yes,34,33 2006.145.02:00:03.70/vb/05,04,usb,yes,26,29 2006.145.02:00:03.70/vb/06,04,usb,yes,31,27 2006.145.02:00:03.70/vb/07,04,usb,yes,31,30 2006.145.02:00:03.70/vb/08,04,usb,yes,28,31 2006.145.02:00:03.93/vblo/01,629.99,yes,locked 2006.145.02:00:03.93/vblo/02,634.99,yes,locked 2006.145.02:00:03.93/vblo/03,649.99,yes,locked 2006.145.02:00:03.93/vblo/04,679.99,yes,locked 2006.145.02:00:03.93/vblo/05,709.99,yes,locked 2006.145.02:00:03.93/vblo/06,719.99,yes,locked 2006.145.02:00:03.93/vblo/07,734.99,yes,locked 2006.145.02:00:03.93/vblo/08,744.99,yes,locked 2006.145.02:00:04.08/vabw/8 2006.145.02:00:04.23/vbbw/8 2006.145.02:00:04.39/xfe/off,on,15.0 2006.145.02:00:04.76/ifatt/23,28,28,28 2006.145.02:00:05.07/fmout-gps/S +5.5E-08 2006.145.02:00:05.11:!2006.145.02:00:40 2006.145.02:00:40.01:data_valid=off 2006.145.02:00:40.02:"et 2006.145.02:00:40.02:!+3s 2006.145.02:00:43.03:"tape 2006.145.02:00:43.04:postob 2006.145.02:00:43.04&postob/cable 2006.145.02:00:43.04&postob/wx 2006.145.02:00:43.05&postob/clockoff 2006.145.02:00:43.13/cable/+6.5487E-03 2006.145.02:00:43.14/wx/19.44,1017.2,67 2006.145.02:00:43.19/fmout-gps/S +5.5E-08 2006.145.02:00:43.20:scan_name=145-0201,jd0605,40 2006.145.02:00:43.20:source=nrao150,035929.75,505750.2,2000.0,cw 2006.145.02:00:45.14#flagr#flagr/antenna,new-source 2006.145.02:00:45.15:checkk5 2006.145.02:00:45.15&checkk5/chk_autoobs=1 2006.145.02:00:45.15&checkk5/chk_autoobs=2 2006.145.02:00:45.16&checkk5/chk_autoobs=3 2006.145.02:00:45.16&checkk5/chk_autoobs=4 2006.145.02:00:45.16&checkk5/chk_obsdata=1 2006.145.02:00:45.17&checkk5/chk_obsdata=2 2006.145.02:00:45.17&checkk5/chk_obsdata=3 2006.145.02:00:45.17&checkk5/chk_obsdata=4 2006.145.02:00:45.18&checkk5/k5log=1 2006.145.02:00:45.18&checkk5/k5log=2 2006.145.02:00:45.18&checkk5/k5log=3 2006.145.02:00:45.23&checkk5/k5log=4 2006.145.02:00:45.23&checkk5/obsinfo 2006.145.02:00:45.66/chk_autoobs//k5ts1/ autoobs is running! 2006.145.02:00:46.05/chk_autoobs//k5ts2/ autoobs is running! 2006.145.02:00:46.42/chk_autoobs//k5ts3/ autoobs is running! 2006.145.02:00:47.07/chk_autoobs//k5ts4/ autoobs is running! 2006.145.02:00:47.50/chk_obsdata//k5ts1/T1450200??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.02:00:47.95/chk_obsdata//k5ts2/T1450200??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.02:00:48.59/chk_obsdata//k5ts3/T1450200??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.02:00:49.11/chk_obsdata//k5ts4/T1450200??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.02:00:50.14/k5log//k5ts1_log_newline 2006.145.02:00:51.07/k5log//k5ts2_log_newline 2006.145.02:00:51.79/k5log//k5ts3_log_newline 2006.145.02:00:52.57/k5log//k5ts4_log_newline 2006.145.02:00:52.59/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.02:00:52.59:setupk4=1 2006.145.02:00:52.59$setupk4/echo=on 2006.145.02:00:52.59$setupk4/pcalon 2006.145.02:00:52.59$pcalon/"no phase cal control is implemented here 2006.145.02:00:52.59$setupk4/"tpicd=stop 2006.145.02:00:52.60$setupk4/"rec=synch_on 2006.145.02:00:52.60$setupk4/"rec_mode=128 2006.145.02:00:52.60$setupk4/!* 2006.145.02:00:52.60$setupk4/recpk4 2006.145.02:00:52.60$recpk4/recpatch= 2006.145.02:00:52.60$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.02:00:52.60$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.02:00:52.60$setupk4/vck44 2006.145.02:00:52.60$vck44/valo=1,524.99 2006.145.02:00:52.60#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.02:00:52.60#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.02:00:52.60#ibcon#ireg 17 cls_cnt 0 2006.145.02:00:52.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:00:52.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:00:52.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:00:52.61#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.02:00:52.66#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:00:52.66#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:00:52.66#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.02:00:52.66#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.02:00:52.66$vck44/va=1,8 2006.145.02:00:52.66#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.02:00:52.66#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.02:00:52.66#ibcon#ireg 11 cls_cnt 2 2006.145.02:00:52.66#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:00:52.66#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:00:52.66#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:00:52.68#ibcon#[25=AT01-08\r\n] 2006.145.02:00:52.71#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:00:52.71#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:00:52.71#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.02:00:52.71#ibcon#ireg 7 cls_cnt 0 2006.145.02:00:52.71#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:00:52.83#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:00:52.83#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:00:52.85#ibcon#[25=USB\r\n] 2006.145.02:00:52.88#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:00:52.88#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:00:52.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.02:00:52.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.02:00:52.88$vck44/valo=2,534.99 2006.145.02:00:52.88#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.02:00:52.88#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.02:00:52.88#ibcon#ireg 17 cls_cnt 0 2006.145.02:00:52.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:00:52.88#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:00:52.88#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:00:52.91#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.02:00:52.95#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:00:52.95#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:00:52.95#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.02:00:52.95#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.02:00:52.95$vck44/va=2,7 2006.145.02:00:52.95#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.02:00:52.95#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.02:00:52.95#ibcon#ireg 11 cls_cnt 2 2006.145.02:00:52.95#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:00:53.01#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:00:53.01#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:00:53.02#ibcon#[25=AT02-07\r\n] 2006.145.02:00:53.05#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:00:53.05#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:00:53.05#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.02:00:53.05#ibcon#ireg 7 cls_cnt 0 2006.145.02:00:53.05#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:00:53.17#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:00:53.17#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:00:53.19#ibcon#[25=USB\r\n] 2006.145.02:00:53.24#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:00:53.24#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:00:53.24#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.02:00:53.24#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.02:00:53.24$vck44/valo=3,564.99 2006.145.02:00:53.24#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.02:00:53.24#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.02:00:53.24#ibcon#ireg 17 cls_cnt 0 2006.145.02:00:53.24#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:00:53.24#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:00:53.24#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:00:53.25#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.02:00:53.29#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:00:53.29#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:00:53.29#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.02:00:53.29#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.02:00:53.29$vck44/va=3,8 2006.145.02:00:53.29#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.02:00:53.29#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.02:00:53.29#ibcon#ireg 11 cls_cnt 2 2006.145.02:00:53.29#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:00:53.36#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:00:53.36#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:00:53.38#ibcon#[25=AT03-08\r\n] 2006.145.02:00:53.41#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:00:53.41#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:00:53.41#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.02:00:53.41#ibcon#ireg 7 cls_cnt 0 2006.145.02:00:53.41#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:00:53.53#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:00:53.53#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:00:53.55#ibcon#[25=USB\r\n] 2006.145.02:00:53.58#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:00:53.58#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:00:53.58#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.02:00:53.58#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.02:00:53.58$vck44/valo=4,624.99 2006.145.02:00:53.58#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.02:00:53.58#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.02:00:53.58#ibcon#ireg 17 cls_cnt 0 2006.145.02:00:53.58#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:00:53.58#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:00:53.58#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:00:53.60#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.02:00:53.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:00:53.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:00:53.64#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.02:00:53.64#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.02:00:53.64$vck44/va=4,7 2006.145.02:00:53.64#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.02:00:53.64#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.02:00:53.64#ibcon#ireg 11 cls_cnt 2 2006.145.02:00:53.64#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:00:53.70#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:00:53.70#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:00:53.72#ibcon#[25=AT04-07\r\n] 2006.145.02:00:53.75#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:00:53.75#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:00:53.75#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.02:00:53.75#ibcon#ireg 7 cls_cnt 0 2006.145.02:00:53.75#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:00:53.87#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:00:53.87#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:00:53.89#ibcon#[25=USB\r\n] 2006.145.02:00:53.92#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:00:53.92#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:00:53.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.02:00:53.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.02:00:53.92$vck44/valo=5,734.99 2006.145.02:00:53.92#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.02:00:53.92#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.02:00:53.92#ibcon#ireg 17 cls_cnt 0 2006.145.02:00:53.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:00:53.92#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:00:53.92#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:00:53.94#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.02:00:53.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:00:53.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:00:53.98#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.02:00:53.98#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.02:00:53.98$vck44/va=5,4 2006.145.02:00:53.98#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.02:00:53.98#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.02:00:53.98#ibcon#ireg 11 cls_cnt 2 2006.145.02:00:53.98#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:00:54.04#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:00:54.04#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:00:54.06#ibcon#[25=AT05-04\r\n] 2006.145.02:00:54.09#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:00:54.09#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:00:54.09#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.02:00:54.09#ibcon#ireg 7 cls_cnt 0 2006.145.02:00:54.09#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:00:54.21#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:00:54.21#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:00:54.23#ibcon#[25=USB\r\n] 2006.145.02:00:54.26#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:00:54.26#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:00:54.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.02:00:54.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.02:00:54.26$vck44/valo=6,814.99 2006.145.02:00:54.26#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.02:00:54.26#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.02:00:54.26#ibcon#ireg 17 cls_cnt 0 2006.145.02:00:54.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:00:54.26#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:00:54.26#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:00:54.28#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.02:00:54.32#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:00:54.32#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:00:54.32#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.02:00:54.32#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.02:00:54.32$vck44/va=6,4 2006.145.02:00:54.32#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.02:00:54.32#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.02:00:54.32#ibcon#ireg 11 cls_cnt 2 2006.145.02:00:54.32#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:00:54.38#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:00:54.38#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:00:54.40#ibcon#[25=AT06-04\r\n] 2006.145.02:00:54.43#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:00:54.43#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:00:54.43#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.02:00:54.43#ibcon#ireg 7 cls_cnt 0 2006.145.02:00:54.43#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:00:54.55#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:00:54.55#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:00:54.57#ibcon#[25=USB\r\n] 2006.145.02:00:54.60#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:00:54.60#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:00:54.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.02:00:54.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.02:00:54.60$vck44/valo=7,864.99 2006.145.02:00:54.60#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.02:00:54.60#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.02:00:54.60#ibcon#ireg 17 cls_cnt 0 2006.145.02:00:54.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:00:54.60#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:00:54.60#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:00:54.62#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.02:00:54.66#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:00:54.66#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:00:54.66#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.02:00:54.66#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.02:00:54.66$vck44/va=7,4 2006.145.02:00:54.66#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.02:00:54.66#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.02:00:54.66#ibcon#ireg 11 cls_cnt 2 2006.145.02:00:54.66#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:00:54.72#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:00:54.72#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:00:54.74#ibcon#[25=AT07-04\r\n] 2006.145.02:00:54.77#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:00:54.77#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:00:54.77#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.02:00:54.77#ibcon#ireg 7 cls_cnt 0 2006.145.02:00:54.77#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:00:54.89#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:00:54.89#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:00:54.91#ibcon#[25=USB\r\n] 2006.145.02:00:54.94#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:00:54.94#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:00:54.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.02:00:54.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.02:00:54.94$vck44/valo=8,884.99 2006.145.02:00:54.94#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.02:00:54.94#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.02:00:54.94#ibcon#ireg 17 cls_cnt 0 2006.145.02:00:54.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:00:54.94#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:00:54.94#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:00:54.96#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.02:00:55.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:00:55.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:00:55.00#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.02:00:55.00#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.02:00:55.00$vck44/va=8,4 2006.145.02:00:55.00#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.02:00:55.00#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.02:00:55.00#ibcon#ireg 11 cls_cnt 2 2006.145.02:00:55.00#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.02:00:55.06#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.02:00:55.06#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.02:00:55.08#ibcon#[25=AT08-04\r\n] 2006.145.02:00:55.12#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.02:00:55.12#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.02:00:55.12#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.02:00:55.12#ibcon#ireg 7 cls_cnt 0 2006.145.02:00:55.12#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.02:00:55.24#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.02:00:55.24#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.02:00:55.26#ibcon#[25=USB\r\n] 2006.145.02:00:55.29#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.02:00:55.29#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.02:00:55.29#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.02:00:55.29#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.02:00:55.29$vck44/vblo=1,629.99 2006.145.02:00:55.29#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.02:00:55.29#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.02:00:55.29#ibcon#ireg 17 cls_cnt 0 2006.145.02:00:55.29#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:00:55.29#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:00:55.29#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:00:55.31#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.02:00:55.35#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:00:55.35#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:00:55.35#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.02:00:55.35#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.02:00:55.35$vck44/vb=1,3 2006.145.02:00:55.35#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.02:00:55.35#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.02:00:55.35#ibcon#ireg 11 cls_cnt 2 2006.145.02:00:55.35#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:00:55.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:00:55.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:00:55.37#ibcon#[27=AT01-03\r\n] 2006.145.02:00:55.40#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:00:55.40#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:00:55.40#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.02:00:55.40#ibcon#ireg 7 cls_cnt 0 2006.145.02:00:55.40#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:00:55.52#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:00:55.52#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:00:55.54#ibcon#[27=USB\r\n] 2006.145.02:00:55.57#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:00:55.57#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:00:55.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.02:00:55.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.02:00:55.57$vck44/vblo=2,634.99 2006.145.02:00:55.57#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.02:00:55.57#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.02:00:55.57#ibcon#ireg 17 cls_cnt 0 2006.145.02:00:55.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:00:55.57#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:00:55.57#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:00:55.59#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.02:00:55.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:00:55.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:00:55.63#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.02:00:55.63#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.02:00:55.63$vck44/vb=2,4 2006.145.02:00:55.63#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.02:00:55.63#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.02:00:55.63#ibcon#ireg 11 cls_cnt 2 2006.145.02:00:55.63#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:00:55.69#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:00:55.69#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:00:55.71#ibcon#[27=AT02-04\r\n] 2006.145.02:00:55.74#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:00:55.74#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:00:55.74#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.02:00:55.74#ibcon#ireg 7 cls_cnt 0 2006.145.02:00:55.74#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:00:55.86#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:00:55.86#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:00:55.88#ibcon#[27=USB\r\n] 2006.145.02:00:55.91#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:00:55.91#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:00:55.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.02:00:55.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.02:00:55.91$vck44/vblo=3,649.99 2006.145.02:00:55.91#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.02:00:55.91#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.02:00:55.91#ibcon#ireg 17 cls_cnt 0 2006.145.02:00:55.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:00:55.91#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:00:55.91#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:00:55.93#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.02:00:55.97#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:00:55.97#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:00:55.97#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.02:00:55.97#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.02:00:55.97$vck44/vb=3,4 2006.145.02:00:55.97#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.02:00:55.97#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.02:00:55.97#ibcon#ireg 11 cls_cnt 2 2006.145.02:00:55.97#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:00:56.03#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:00:56.03#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:00:56.05#ibcon#[27=AT03-04\r\n] 2006.145.02:00:56.08#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:00:56.08#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:00:56.08#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.02:00:56.08#ibcon#ireg 7 cls_cnt 0 2006.145.02:00:56.08#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:00:56.20#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:00:56.20#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:00:56.22#ibcon#[27=USB\r\n] 2006.145.02:00:56.25#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:00:56.25#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:00:56.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.02:00:56.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.02:00:56.25$vck44/vblo=4,679.99 2006.145.02:00:56.25#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.02:00:56.25#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.02:00:56.25#ibcon#ireg 17 cls_cnt 0 2006.145.02:00:56.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:00:56.25#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:00:56.25#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:00:56.27#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.02:00:56.31#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:00:56.31#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:00:56.31#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.02:00:56.31#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.02:00:56.31$vck44/vb=4,4 2006.145.02:00:56.31#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.02:00:56.31#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.02:00:56.31#ibcon#ireg 11 cls_cnt 2 2006.145.02:00:56.31#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:00:56.37#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:00:56.37#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:00:56.39#ibcon#[27=AT04-04\r\n] 2006.145.02:00:56.42#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:00:56.42#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:00:56.42#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.02:00:56.42#ibcon#ireg 7 cls_cnt 0 2006.145.02:00:56.42#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:00:56.54#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:00:56.54#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:00:56.56#ibcon#[27=USB\r\n] 2006.145.02:00:56.59#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:00:56.59#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:00:56.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.02:00:56.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.02:00:56.59$vck44/vblo=5,709.99 2006.145.02:00:56.59#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.02:00:56.59#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.02:00:56.59#ibcon#ireg 17 cls_cnt 0 2006.145.02:00:56.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:00:56.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:00:56.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:00:56.61#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.02:00:56.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:00:56.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:00:56.65#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.02:00:56.65#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.02:00:56.65$vck44/vb=5,4 2006.145.02:00:56.65#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.02:00:56.65#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.02:00:56.65#ibcon#ireg 11 cls_cnt 2 2006.145.02:00:56.65#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:00:56.71#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:00:56.71#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:00:56.73#ibcon#[27=AT05-04\r\n] 2006.145.02:00:56.76#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:00:56.76#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:00:56.76#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.02:00:56.76#ibcon#ireg 7 cls_cnt 0 2006.145.02:00:56.76#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:00:56.88#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:00:56.88#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:00:56.90#ibcon#[27=USB\r\n] 2006.145.02:00:56.93#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:00:56.93#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:00:56.93#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.02:00:56.93#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.02:00:56.93$vck44/vblo=6,719.99 2006.145.02:00:56.93#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.02:00:56.93#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.02:00:56.93#ibcon#ireg 17 cls_cnt 0 2006.145.02:00:56.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:00:56.93#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:00:56.93#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:00:56.95#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.02:00:56.99#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:00:56.99#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:00:56.99#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.02:00:56.99#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.02:00:56.99$vck44/vb=6,4 2006.145.02:00:56.99#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.02:00:56.99#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.02:00:56.99#ibcon#ireg 11 cls_cnt 2 2006.145.02:00:56.99#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:00:57.05#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:00:57.05#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:00:57.07#ibcon#[27=AT06-04\r\n] 2006.145.02:00:57.10#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:00:57.10#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:00:57.10#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.02:00:57.10#ibcon#ireg 7 cls_cnt 0 2006.145.02:00:57.10#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:00:57.22#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:00:57.22#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:00:57.24#ibcon#[27=USB\r\n] 2006.145.02:00:57.27#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:00:57.27#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:00:57.27#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.02:00:57.27#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.02:00:57.27$vck44/vblo=7,734.99 2006.145.02:00:57.27#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.02:00:57.27#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.02:00:57.27#ibcon#ireg 17 cls_cnt 0 2006.145.02:00:57.27#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:00:57.27#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:00:57.27#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:00:57.29#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.02:00:57.33#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:00:57.33#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:00:57.33#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.02:00:57.33#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.02:00:57.33$vck44/vb=7,4 2006.145.02:00:57.33#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.02:00:57.33#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.02:00:57.33#ibcon#ireg 11 cls_cnt 2 2006.145.02:00:57.33#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:00:57.39#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:00:57.39#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:00:57.41#ibcon#[27=AT07-04\r\n] 2006.145.02:00:57.45#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:00:57.45#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:00:57.45#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.02:00:57.45#ibcon#ireg 7 cls_cnt 0 2006.145.02:00:57.45#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:00:57.57#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:00:57.57#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:00:57.59#ibcon#[27=USB\r\n] 2006.145.02:00:57.62#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:00:57.62#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:00:57.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.02:00:57.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.02:00:57.62$vck44/vblo=8,744.99 2006.145.02:00:57.62#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.02:00:57.62#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.02:00:57.62#ibcon#ireg 17 cls_cnt 0 2006.145.02:00:57.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:00:57.62#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:00:57.62#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:00:57.64#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.02:00:57.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:00:57.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:00:57.68#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.02:00:57.68#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.02:00:57.68$vck44/vb=8,4 2006.145.02:00:57.68#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.02:00:57.68#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.02:00:57.68#ibcon#ireg 11 cls_cnt 2 2006.145.02:00:57.68#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:00:57.74#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:00:57.74#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:00:57.76#ibcon#[27=AT08-04\r\n] 2006.145.02:00:57.79#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:00:57.79#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:00:57.79#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.02:00:57.79#ibcon#ireg 7 cls_cnt 0 2006.145.02:00:57.79#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:00:57.91#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:00:57.91#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:00:57.93#ibcon#[27=USB\r\n] 2006.145.02:00:57.96#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:00:57.96#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:00:57.96#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.02:00:57.96#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.02:00:57.96$vck44/vabw=wide 2006.145.02:00:57.96#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.02:00:57.96#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.02:00:57.96#ibcon#ireg 8 cls_cnt 0 2006.145.02:00:57.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:00:57.96#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:00:57.96#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:00:57.98#ibcon#[25=BW32\r\n] 2006.145.02:00:58.01#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:00:58.01#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:00:58.01#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.02:00:58.01#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.02:00:58.01$vck44/vbbw=wide 2006.145.02:00:58.01#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.02:00:58.01#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.02:00:58.01#ibcon#ireg 8 cls_cnt 0 2006.145.02:00:58.01#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.02:00:58.08#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.02:00:58.08#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.02:00:58.10#ibcon#[27=BW32\r\n] 2006.145.02:00:58.13#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.02:00:58.13#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.02:00:58.13#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.02:00:58.13#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.02:00:58.13$setupk4/ifdk4 2006.145.02:00:58.13$ifdk4/lo= 2006.145.02:00:58.13$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.02:00:58.13$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.02:00:58.13$ifdk4/patch= 2006.145.02:00:58.13$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.02:00:58.13$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.02:00:58.13$setupk4/!*+20s 2006.145.02:00:58.68#abcon#<5=/06 4.2 8.6 19.46 641017.3\r\n> 2006.145.02:00:58.70#abcon#{5=INTERFACE CLEAR} 2006.145.02:00:58.78#abcon#[5=S1D000X0/0*\r\n] 2006.145.02:01:08.87#abcon#<5=/06 4.2 8.6 19.46 641017.3\r\n> 2006.145.02:01:08.89#abcon#{5=INTERFACE CLEAR} 2006.145.02:01:08.95#abcon#[5=S1D000X0/0*\r\n] 2006.145.02:01:12.61$setupk4/"tpicd 2006.145.02:01:12.61$setupk4/echo=off 2006.145.02:01:12.61$setupk4/xlog=off 2006.145.02:01:12.61:!2006.145.02:01:29 2006.145.02:01:27.14#trakl#Source acquired 2006.145.02:01:28.14#flagr#flagr/antenna,acquired 2006.145.02:01:29.00:preob 2006.145.02:01:29.14/onsource/TRACKING 2006.145.02:01:29.14:!2006.145.02:01:39 2006.145.02:01:39.00:"tape 2006.145.02:01:39.00:"st=record 2006.145.02:01:39.00:data_valid=on 2006.145.02:01:39.00:midob 2006.145.02:01:40.14/onsource/TRACKING 2006.145.02:01:40.14/wx/19.47,1017.3,64 2006.145.02:01:40.20/cable/+6.5491E-03 2006.145.02:01:41.30/va/01,08,usb,yes,28,30 2006.145.02:01:41.30/va/02,07,usb,yes,30,31 2006.145.02:01:41.30/va/03,08,usb,yes,27,28 2006.145.02:01:41.30/va/04,07,usb,yes,31,33 2006.145.02:01:41.30/va/05,04,usb,yes,27,28 2006.145.02:01:41.30/va/06,04,usb,yes,30,30 2006.145.02:01:41.30/va/07,04,usb,yes,31,32 2006.145.02:01:41.30/va/08,04,usb,yes,26,32 2006.145.02:01:41.53/valo/01,524.99,yes,locked 2006.145.02:01:41.53/valo/02,534.99,yes,locked 2006.145.02:01:41.53/valo/03,564.99,yes,locked 2006.145.02:01:41.53/valo/04,624.99,yes,locked 2006.145.02:01:41.53/valo/05,734.99,yes,locked 2006.145.02:01:41.53/valo/06,814.99,yes,locked 2006.145.02:01:41.53/valo/07,864.99,yes,locked 2006.145.02:01:41.53/valo/08,884.99,yes,locked 2006.145.02:01:42.62/vb/01,03,usb,yes,35,33 2006.145.02:01:42.62/vb/02,04,usb,yes,31,31 2006.145.02:01:42.62/vb/03,04,usb,yes,28,31 2006.145.02:01:42.62/vb/04,04,usb,yes,32,31 2006.145.02:01:42.62/vb/05,04,usb,yes,25,27 2006.145.02:01:42.62/vb/06,04,usb,yes,29,25 2006.145.02:01:42.62/vb/07,04,usb,yes,29,29 2006.145.02:01:42.62/vb/08,04,usb,yes,26,30 2006.145.02:01:42.86/vblo/01,629.99,yes,locked 2006.145.02:01:42.86/vblo/02,634.99,yes,locked 2006.145.02:01:42.86/vblo/03,649.99,yes,locked 2006.145.02:01:42.86/vblo/04,679.99,yes,locked 2006.145.02:01:42.86/vblo/05,709.99,yes,locked 2006.145.02:01:42.86/vblo/06,719.99,yes,locked 2006.145.02:01:42.86/vblo/07,734.99,yes,locked 2006.145.02:01:42.86/vblo/08,744.99,yes,locked 2006.145.02:01:43.01/vabw/8 2006.145.02:01:43.16/vbbw/8 2006.145.02:01:43.25/xfe/off,on,15.2 2006.145.02:01:43.62/ifatt/23,28,28,28 2006.145.02:01:44.07/fmout-gps/S +5.3E-08 2006.145.02:01:44.11:!2006.145.02:02:19 2006.145.02:02:19.01:data_valid=off 2006.145.02:02:19.02:"et 2006.145.02:02:19.02:!+3s 2006.145.02:02:22.03:"tape 2006.145.02:02:22.04:postob 2006.145.02:02:22.20/cable/+6.5475E-03 2006.145.02:02:22.21/wx/19.48,1017.3,64 2006.145.02:02:22.26/fmout-gps/S +5.3E-08 2006.145.02:02:22.27:scan_name=145-0211,jd0605,40 2006.145.02:02:22.27:source=4c39.25,092703.01,390220.9,2000.0,cw 2006.145.02:02:24.14#flagr#flagr/antenna,new-source 2006.145.02:02:24.15:checkk5 2006.145.02:02:24.53/chk_autoobs//k5ts1/ autoobs is running! 2006.145.02:02:24.96/chk_autoobs//k5ts2/ autoobs is running! 2006.145.02:02:25.37/chk_autoobs//k5ts3/ autoobs is running! 2006.145.02:02:25.74/chk_autoobs//k5ts4/ autoobs is running! 2006.145.02:02:26.18/chk_obsdata//k5ts1/T1450201??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.02:02:26.88/chk_obsdata//k5ts2/T1450201??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.02:02:27.27/chk_obsdata//k5ts3/T1450201??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.02:02:27.66/chk_obsdata//k5ts4/T1450201??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.02:02:28.60/k5log//k5ts1_log_newline 2006.145.02:02:29.39/k5log//k5ts2_log_newline 2006.145.02:02:30.18/k5log//k5ts3_log_newline 2006.145.02:02:31.00/k5log//k5ts4_log_newline 2006.145.02:02:31.02/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.02:02:31.02:setupk4=1 2006.145.02:02:31.02$setupk4/echo=on 2006.145.02:02:31.02$setupk4/pcalon 2006.145.02:02:31.02$pcalon/"no phase cal control is implemented here 2006.145.02:02:31.02$setupk4/"tpicd=stop 2006.145.02:02:31.02$setupk4/"rec=synch_on 2006.145.02:02:31.02$setupk4/"rec_mode=128 2006.145.02:02:31.02$setupk4/!* 2006.145.02:02:31.02$setupk4/recpk4 2006.145.02:02:31.02$recpk4/recpatch= 2006.145.02:02:31.02$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.02:02:31.03$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.02:02:31.03$setupk4/vck44 2006.145.02:02:31.03$vck44/valo=1,524.99 2006.145.02:02:31.03#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.02:02:31.03#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.02:02:31.03#ibcon#ireg 17 cls_cnt 0 2006.145.02:02:31.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:02:31.03#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:02:31.03#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:02:31.06#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.02:02:31.11#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:02:31.11#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:02:31.11#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.02:02:31.11#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.02:02:31.11$vck44/va=1,8 2006.145.02:02:31.11#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.02:02:31.11#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.02:02:31.11#ibcon#ireg 11 cls_cnt 2 2006.145.02:02:31.11#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:02:31.11#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:02:31.11#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:02:31.14#ibcon#[25=AT01-08\r\n] 2006.145.02:02:31.17#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:02:31.17#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:02:31.17#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.02:02:31.17#ibcon#ireg 7 cls_cnt 0 2006.145.02:02:31.17#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:02:31.29#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:02:31.29#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:02:31.31#ibcon#[25=USB\r\n] 2006.145.02:02:31.34#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:02:31.34#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:02:31.34#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.02:02:31.34#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.02:02:31.34$vck44/valo=2,534.99 2006.145.02:02:31.34#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.02:02:31.34#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.02:02:31.34#ibcon#ireg 17 cls_cnt 0 2006.145.02:02:31.34#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:02:31.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:02:31.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:02:31.37#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.02:02:31.41#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:02:31.41#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:02:31.41#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.02:02:31.41#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.02:02:31.41$vck44/va=2,7 2006.145.02:02:31.41#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.02:02:31.41#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.02:02:31.41#ibcon#ireg 11 cls_cnt 2 2006.145.02:02:31.41#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:02:31.47#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:02:31.47#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:02:31.48#ibcon#[25=AT02-07\r\n] 2006.145.02:02:31.51#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:02:31.51#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:02:31.51#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.02:02:31.51#ibcon#ireg 7 cls_cnt 0 2006.145.02:02:31.51#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:02:31.63#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:02:31.63#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:02:31.65#ibcon#[25=USB\r\n] 2006.145.02:02:31.68#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:02:31.68#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:02:31.68#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.02:02:31.68#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.02:02:31.68$vck44/valo=3,564.99 2006.145.02:02:31.68#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.02:02:31.68#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.02:02:31.68#ibcon#ireg 17 cls_cnt 0 2006.145.02:02:31.68#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:02:31.68#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:02:31.68#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:02:31.71#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.02:02:31.75#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:02:31.75#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:02:31.75#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.02:02:31.75#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.02:02:31.75$vck44/va=3,8 2006.145.02:02:31.75#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.02:02:31.75#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.02:02:31.75#ibcon#ireg 11 cls_cnt 2 2006.145.02:02:31.75#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:02:31.81#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:02:31.81#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:02:31.82#ibcon#[25=AT03-08\r\n] 2006.145.02:02:31.85#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:02:31.85#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:02:31.85#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.02:02:31.85#ibcon#ireg 7 cls_cnt 0 2006.145.02:02:31.85#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:02:31.97#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:02:31.97#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:02:31.99#ibcon#[25=USB\r\n] 2006.145.02:02:32.02#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:02:32.02#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:02:32.02#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.02:02:32.02#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.02:02:32.02$vck44/valo=4,624.99 2006.145.02:02:32.02#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.02:02:32.02#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.02:02:32.02#ibcon#ireg 17 cls_cnt 0 2006.145.02:02:32.02#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:02:32.02#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:02:32.02#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:02:32.04#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.02:02:32.08#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:02:32.08#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:02:32.08#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.02:02:32.08#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.02:02:32.08$vck44/va=4,7 2006.145.02:02:32.08#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.02:02:32.08#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.02:02:32.08#ibcon#ireg 11 cls_cnt 2 2006.145.02:02:32.08#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:02:32.14#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:02:32.14#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:02:32.16#ibcon#[25=AT04-07\r\n] 2006.145.02:02:32.19#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:02:32.19#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:02:32.19#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.02:02:32.19#ibcon#ireg 7 cls_cnt 0 2006.145.02:02:32.19#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:02:32.31#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:02:32.31#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:02:32.33#ibcon#[25=USB\r\n] 2006.145.02:02:32.36#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:02:32.36#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:02:32.36#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.02:02:32.36#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.02:02:32.36$vck44/valo=5,734.99 2006.145.02:02:32.36#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.02:02:32.36#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.02:02:32.36#ibcon#ireg 17 cls_cnt 0 2006.145.02:02:32.36#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:02:32.36#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:02:32.36#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:02:32.38#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.02:02:32.42#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:02:32.42#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:02:32.42#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.02:02:32.42#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.02:02:32.42$vck44/va=5,4 2006.145.02:02:32.42#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.02:02:32.42#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.02:02:32.42#ibcon#ireg 11 cls_cnt 2 2006.145.02:02:32.42#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:02:32.48#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:02:32.48#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:02:32.50#ibcon#[25=AT05-04\r\n] 2006.145.02:02:32.53#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:02:32.53#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:02:32.53#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.02:02:32.53#ibcon#ireg 7 cls_cnt 0 2006.145.02:02:32.53#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:02:32.65#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:02:32.65#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:02:32.67#ibcon#[25=USB\r\n] 2006.145.02:02:32.70#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:02:32.70#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:02:32.70#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.02:02:32.70#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.02:02:32.70$vck44/valo=6,814.99 2006.145.02:02:32.70#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.02:02:32.70#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.02:02:32.70#ibcon#ireg 17 cls_cnt 0 2006.145.02:02:32.70#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:02:32.70#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:02:32.70#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:02:32.72#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.02:02:32.76#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:02:32.76#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:02:32.76#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.02:02:32.76#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.02:02:32.76$vck44/va=6,4 2006.145.02:02:32.76#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.02:02:32.76#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.02:02:32.76#ibcon#ireg 11 cls_cnt 2 2006.145.02:02:32.76#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:02:32.82#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:02:32.82#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:02:32.84#ibcon#[25=AT06-04\r\n] 2006.145.02:02:32.87#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:02:32.87#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:02:32.87#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.02:02:32.87#ibcon#ireg 7 cls_cnt 0 2006.145.02:02:32.87#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:02:32.99#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:02:32.99#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:02:33.01#ibcon#[25=USB\r\n] 2006.145.02:02:33.04#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:02:33.04#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:02:33.04#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.02:02:33.04#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.02:02:33.04$vck44/valo=7,864.99 2006.145.02:02:33.04#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.02:02:33.04#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.02:02:33.04#ibcon#ireg 17 cls_cnt 0 2006.145.02:02:33.04#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:02:33.04#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:02:33.04#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:02:33.06#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.02:02:33.10#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:02:33.10#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:02:33.10#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.02:02:33.10#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.02:02:33.10$vck44/va=7,4 2006.145.02:02:33.10#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.02:02:33.10#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.02:02:33.10#ibcon#ireg 11 cls_cnt 2 2006.145.02:02:33.10#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:02:33.16#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:02:33.16#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:02:33.18#ibcon#[25=AT07-04\r\n] 2006.145.02:02:33.21#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:02:33.21#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:02:33.21#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.02:02:33.21#ibcon#ireg 7 cls_cnt 0 2006.145.02:02:33.21#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:02:33.33#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:02:33.33#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:02:33.35#ibcon#[25=USB\r\n] 2006.145.02:02:33.38#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:02:33.38#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:02:33.38#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.02:02:33.38#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.02:02:33.38$vck44/valo=8,884.99 2006.145.02:02:33.38#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.02:02:33.38#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.02:02:33.38#ibcon#ireg 17 cls_cnt 0 2006.145.02:02:33.38#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:02:33.38#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:02:33.38#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:02:33.40#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.02:02:33.44#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:02:33.44#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:02:33.44#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.02:02:33.44#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.02:02:33.44$vck44/va=8,4 2006.145.02:02:33.44#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.02:02:33.44#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.02:02:33.44#ibcon#ireg 11 cls_cnt 2 2006.145.02:02:33.44#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.02:02:33.50#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.02:02:33.50#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.02:02:33.52#ibcon#[25=AT08-04\r\n] 2006.145.02:02:33.55#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.02:02:33.55#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.02:02:33.55#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.02:02:33.55#ibcon#ireg 7 cls_cnt 0 2006.145.02:02:33.55#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.02:02:33.67#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.02:02:33.67#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.02:02:33.69#ibcon#[25=USB\r\n] 2006.145.02:02:33.72#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.02:02:33.72#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.02:02:33.72#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.02:02:33.72#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.02:02:33.72$vck44/vblo=1,629.99 2006.145.02:02:33.72#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.02:02:33.72#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.02:02:33.72#ibcon#ireg 17 cls_cnt 0 2006.145.02:02:33.72#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:02:33.72#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:02:33.72#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:02:33.74#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.02:02:33.78#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:02:33.78#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:02:33.78#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.02:02:33.78#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.02:02:33.78$vck44/vb=1,3 2006.145.02:02:33.78#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.02:02:33.78#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.02:02:33.78#ibcon#ireg 11 cls_cnt 2 2006.145.02:02:33.78#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:02:33.78#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:02:33.78#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:02:33.80#ibcon#[27=AT01-03\r\n] 2006.145.02:02:33.83#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:02:33.83#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:02:33.83#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.02:02:33.83#ibcon#ireg 7 cls_cnt 0 2006.145.02:02:33.83#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:02:33.95#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:02:33.95#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:02:33.97#ibcon#[27=USB\r\n] 2006.145.02:02:34.00#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:02:34.00#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:02:34.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.02:02:34.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.02:02:34.00$vck44/vblo=2,634.99 2006.145.02:02:34.00#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.02:02:34.00#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.02:02:34.00#ibcon#ireg 17 cls_cnt 0 2006.145.02:02:34.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:02:34.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:02:34.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:02:34.02#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.02:02:34.06#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:02:34.06#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:02:34.06#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.02:02:34.06#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.02:02:34.06$vck44/vb=2,4 2006.145.02:02:34.06#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.02:02:34.06#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.02:02:34.06#ibcon#ireg 11 cls_cnt 2 2006.145.02:02:34.06#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:02:34.12#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:02:34.12#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:02:34.14#ibcon#[27=AT02-04\r\n] 2006.145.02:02:34.17#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:02:34.17#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:02:34.17#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.02:02:34.17#ibcon#ireg 7 cls_cnt 0 2006.145.02:02:34.17#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:02:34.29#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:02:34.29#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:02:34.31#ibcon#[27=USB\r\n] 2006.145.02:02:34.34#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:02:34.34#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:02:34.34#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.02:02:34.34#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.02:02:34.34$vck44/vblo=3,649.99 2006.145.02:02:34.34#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.02:02:34.34#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.02:02:34.34#ibcon#ireg 17 cls_cnt 0 2006.145.02:02:34.34#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:02:34.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:02:34.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:02:34.36#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.02:02:34.40#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:02:34.40#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:02:34.40#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.02:02:34.40#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.02:02:34.40$vck44/vb=3,4 2006.145.02:02:34.40#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.02:02:34.40#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.02:02:34.40#ibcon#ireg 11 cls_cnt 2 2006.145.02:02:34.40#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:02:34.46#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:02:34.46#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:02:34.48#ibcon#[27=AT03-04\r\n] 2006.145.02:02:34.51#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:02:34.51#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:02:34.51#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.02:02:34.51#ibcon#ireg 7 cls_cnt 0 2006.145.02:02:34.51#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:02:34.63#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:02:34.63#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:02:34.65#ibcon#[27=USB\r\n] 2006.145.02:02:34.68#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:02:34.68#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:02:34.68#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.02:02:34.68#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.02:02:34.68$vck44/vblo=4,679.99 2006.145.02:02:34.68#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.02:02:34.68#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.02:02:34.68#ibcon#ireg 17 cls_cnt 0 2006.145.02:02:34.68#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:02:34.68#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:02:34.68#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:02:34.70#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.02:02:34.74#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:02:34.74#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:02:34.74#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.02:02:34.74#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.02:02:34.74$vck44/vb=4,4 2006.145.02:02:34.74#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.02:02:34.74#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.02:02:34.74#ibcon#ireg 11 cls_cnt 2 2006.145.02:02:34.74#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:02:34.80#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:02:34.80#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:02:34.82#ibcon#[27=AT04-04\r\n] 2006.145.02:02:34.85#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:02:34.85#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:02:34.85#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.02:02:34.85#ibcon#ireg 7 cls_cnt 0 2006.145.02:02:34.85#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:02:34.97#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:02:34.97#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:02:34.99#ibcon#[27=USB\r\n] 2006.145.02:02:35.02#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:02:35.02#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:02:35.02#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.02:02:35.02#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.02:02:35.02$vck44/vblo=5,709.99 2006.145.02:02:35.02#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.02:02:35.02#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.02:02:35.02#ibcon#ireg 17 cls_cnt 0 2006.145.02:02:35.02#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:02:35.02#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:02:35.02#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:02:35.04#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.02:02:35.09#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:02:35.09#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:02:35.09#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.02:02:35.09#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.02:02:35.09$vck44/vb=5,4 2006.145.02:02:35.09#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.02:02:35.09#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.02:02:35.09#ibcon#ireg 11 cls_cnt 2 2006.145.02:02:35.09#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:02:35.13#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:02:35.13#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:02:35.15#ibcon#[27=AT05-04\r\n] 2006.145.02:02:35.18#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:02:35.18#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:02:35.18#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.02:02:35.18#ibcon#ireg 7 cls_cnt 0 2006.145.02:02:35.18#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:02:35.30#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:02:35.30#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:02:35.32#ibcon#[27=USB\r\n] 2006.145.02:02:35.35#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:02:35.35#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:02:35.35#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.02:02:35.35#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.02:02:35.35$vck44/vblo=6,719.99 2006.145.02:02:35.35#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.02:02:35.35#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.02:02:35.35#ibcon#ireg 17 cls_cnt 0 2006.145.02:02:35.35#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:02:35.35#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:02:35.35#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:02:35.37#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.02:02:35.41#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:02:35.41#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:02:35.41#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.02:02:35.41#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.02:02:35.41$vck44/vb=6,4 2006.145.02:02:35.41#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.02:02:35.41#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.02:02:35.41#ibcon#ireg 11 cls_cnt 2 2006.145.02:02:35.41#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:02:35.47#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:02:35.47#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:02:35.49#ibcon#[27=AT06-04\r\n] 2006.145.02:02:35.52#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:02:35.52#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:02:35.52#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.02:02:35.52#ibcon#ireg 7 cls_cnt 0 2006.145.02:02:35.52#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:02:35.64#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:02:35.64#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:02:35.66#ibcon#[27=USB\r\n] 2006.145.02:02:35.69#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:02:35.69#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:02:35.69#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.02:02:35.69#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.02:02:35.69$vck44/vblo=7,734.99 2006.145.02:02:35.69#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.02:02:35.69#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.02:02:35.69#ibcon#ireg 17 cls_cnt 0 2006.145.02:02:35.69#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:02:35.69#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:02:35.69#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:02:35.71#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.02:02:35.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:02:35.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:02:35.75#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.02:02:35.75#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.02:02:35.75$vck44/vb=7,4 2006.145.02:02:35.75#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.02:02:35.75#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.02:02:35.75#ibcon#ireg 11 cls_cnt 2 2006.145.02:02:35.75#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:02:35.81#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:02:35.81#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:02:35.83#ibcon#[27=AT07-04\r\n] 2006.145.02:02:35.87#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:02:35.87#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:02:35.87#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.02:02:35.87#ibcon#ireg 7 cls_cnt 0 2006.145.02:02:35.87#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:02:35.99#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:02:35.99#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:02:36.01#ibcon#[27=USB\r\n] 2006.145.02:02:36.04#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:02:36.04#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:02:36.04#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.02:02:36.04#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.02:02:36.04$vck44/vblo=8,744.99 2006.145.02:02:36.04#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.02:02:36.04#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.02:02:36.04#ibcon#ireg 17 cls_cnt 0 2006.145.02:02:36.04#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:02:36.04#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:02:36.04#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:02:36.06#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.02:02:36.10#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:02:36.10#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:02:36.10#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.02:02:36.10#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.02:02:36.10$vck44/vb=8,4 2006.145.02:02:36.10#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.02:02:36.10#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.02:02:36.10#ibcon#ireg 11 cls_cnt 2 2006.145.02:02:36.10#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:02:36.16#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:02:36.16#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:02:36.18#ibcon#[27=AT08-04\r\n] 2006.145.02:02:36.21#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:02:36.21#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:02:36.21#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.02:02:36.21#ibcon#ireg 7 cls_cnt 0 2006.145.02:02:36.21#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:02:36.33#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:02:36.33#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:02:36.35#ibcon#[27=USB\r\n] 2006.145.02:02:36.38#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:02:36.38#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:02:36.38#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.02:02:36.38#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.02:02:36.38$vck44/vabw=wide 2006.145.02:02:36.38#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.02:02:36.38#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.02:02:36.38#ibcon#ireg 8 cls_cnt 0 2006.145.02:02:36.38#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:02:36.38#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:02:36.38#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:02:36.40#ibcon#[25=BW32\r\n] 2006.145.02:02:36.43#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:02:36.43#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:02:36.43#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.02:02:36.43#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.02:02:36.43$vck44/vbbw=wide 2006.145.02:02:36.43#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.02:02:36.43#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.02:02:36.43#ibcon#ireg 8 cls_cnt 0 2006.145.02:02:36.43#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.02:02:36.50#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.02:02:36.50#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.02:02:36.52#ibcon#[27=BW32\r\n] 2006.145.02:02:36.55#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.02:02:36.55#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.02:02:36.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.02:02:36.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.02:02:36.55$setupk4/ifdk4 2006.145.02:02:36.55$ifdk4/lo= 2006.145.02:02:36.55$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.02:02:36.55$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.02:02:36.55$ifdk4/patch= 2006.145.02:02:36.55$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.02:02:36.55$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.02:02:36.55$setupk4/!*+20s 2006.145.02:02:43.26#abcon#{5=INTERFACE CLEAR} 2006.145.02:02:43.33#abcon#[5=S1D000X0/0*\r\n] 2006.145.02:02:51.03$setupk4/"tpicd 2006.145.02:02:51.03$setupk4/echo=off 2006.145.02:02:51.03$setupk4/xlog=off 2006.145.02:02:51.03:!2006.145.02:10:55 2006.145.02:02:53.14#trakl#Source acquired 2006.145.02:02:55.14#flagr#flagr/antenna,acquired 2006.145.02:10:55.00:preob 2006.145.02:10:56.14/onsource/TRACKING 2006.145.02:10:56.14:!2006.145.02:11:05 2006.145.02:11:05.00:"tape 2006.145.02:11:05.00:"st=record 2006.145.02:11:05.00:data_valid=on 2006.145.02:11:05.00:midob 2006.145.02:11:05.14/onsource/TRACKING 2006.145.02:11:05.14/wx/19.45,1017.2,63 2006.145.02:11:05.32/cable/+6.5495E-03 2006.145.02:11:06.41/va/01,08,usb,yes,30,32 2006.145.02:11:06.41/va/02,07,usb,yes,32,33 2006.145.02:11:06.41/va/03,08,usb,yes,29,30 2006.145.02:11:06.41/va/04,07,usb,yes,33,35 2006.145.02:11:06.41/va/05,04,usb,yes,29,30 2006.145.02:11:06.41/va/06,04,usb,yes,32,32 2006.145.02:11:06.41/va/07,04,usb,yes,33,34 2006.145.02:11:06.41/va/08,04,usb,yes,28,34 2006.145.02:11:06.64/valo/01,524.99,yes,locked 2006.145.02:11:06.64/valo/02,534.99,yes,locked 2006.145.02:11:06.64/valo/03,564.99,yes,locked 2006.145.02:11:06.64/valo/04,624.99,yes,locked 2006.145.02:11:06.64/valo/05,734.99,yes,locked 2006.145.02:11:06.64/valo/06,814.99,yes,locked 2006.145.02:11:06.64/valo/07,864.99,yes,locked 2006.145.02:11:06.64/valo/08,884.99,yes,locked 2006.145.02:11:07.73/vb/01,03,usb,yes,37,34 2006.145.02:11:07.73/vb/02,04,usb,yes,32,32 2006.145.02:11:07.73/vb/03,04,usb,yes,29,32 2006.145.02:11:07.73/vb/04,04,usb,yes,34,32 2006.145.02:11:07.73/vb/05,04,usb,yes,26,29 2006.145.02:11:07.73/vb/06,04,usb,yes,31,27 2006.145.02:11:07.73/vb/07,04,usb,yes,30,30 2006.145.02:11:07.73/vb/08,04,usb,yes,28,31 2006.145.02:11:07.96/vblo/01,629.99,yes,locked 2006.145.02:11:07.96/vblo/02,634.99,yes,locked 2006.145.02:11:07.96/vblo/03,649.99,yes,locked 2006.145.02:11:07.96/vblo/04,679.99,yes,locked 2006.145.02:11:07.96/vblo/05,709.99,yes,locked 2006.145.02:11:07.96/vblo/06,719.99,yes,locked 2006.145.02:11:07.96/vblo/07,734.99,yes,locked 2006.145.02:11:07.96/vblo/08,744.99,yes,locked 2006.145.02:11:08.11/vabw/8 2006.145.02:11:08.26/vbbw/8 2006.145.02:11:08.35/xfe/off,on,16.0 2006.145.02:11:08.74/ifatt/23,28,28,28 2006.145.02:11:09.07/fmout-gps/S +5.4E-08 2006.145.02:11:09.11:!2006.145.02:11:45 2006.145.02:11:45.01:data_valid=off 2006.145.02:11:45.01:"et 2006.145.02:11:45.02:!+3s 2006.145.02:11:48.03:"tape 2006.145.02:11:48.03:postob 2006.145.02:11:48.10/cable/+6.5476E-03 2006.145.02:11:48.10/wx/19.45,1017.2,67 2006.145.02:11:48.17/fmout-gps/S +5.4E-08 2006.145.02:11:48.18:scan_name=145-0212,jd0605,70 2006.145.02:11:48.18:source=0727-115,073019.11,-114112.6,2000.0,cw 2006.145.02:11:50.14#flagr#flagr/antenna,new-source 2006.145.02:11:50.14:checkk5 2006.145.02:11:50.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.02:11:50.98/chk_autoobs//k5ts2/ autoobs is running! 2006.145.02:11:51.69/chk_autoobs//k5ts3/ autoobs is running! 2006.145.02:11:52.07/chk_autoobs//k5ts4/ autoobs is running! 2006.145.02:11:52.49/chk_obsdata//k5ts1/T1450211??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.02:11:52.89/chk_obsdata//k5ts2/T1450211??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.02:11:53.33/chk_obsdata//k5ts3/T1450211??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.02:11:53.75/chk_obsdata//k5ts4/T1450211??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.02:11:54.50/k5log//k5ts1_log_newline 2006.145.02:11:55.30/k5log//k5ts2_log_newline 2006.145.02:11:56.07/k5log//k5ts3_log_newline 2006.145.02:11:56.89/k5log//k5ts4_log_newline 2006.145.02:11:56.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.02:11:56.92:setupk4=1 2006.145.02:11:56.92$setupk4/echo=on 2006.145.02:11:56.92$setupk4/pcalon 2006.145.02:11:56.92$pcalon/"no phase cal control is implemented here 2006.145.02:11:56.92$setupk4/"tpicd=stop 2006.145.02:11:56.92$setupk4/"rec=synch_on 2006.145.02:11:56.92$setupk4/"rec_mode=128 2006.145.02:11:56.92$setupk4/!* 2006.145.02:11:56.92$setupk4/recpk4 2006.145.02:11:56.92$recpk4/recpatch= 2006.145.02:11:56.92$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.02:11:56.92$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.02:11:56.92$setupk4/vck44 2006.145.02:11:56.92$vck44/valo=1,524.99 2006.145.02:11:56.92#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.02:11:56.92#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.02:11:56.92#ibcon#ireg 17 cls_cnt 0 2006.145.02:11:56.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.02:11:56.92#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.02:11:56.92#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.02:11:56.96#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.02:11:57.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.02:11:57.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.02:11:57.01#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.02:11:57.01#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.02:11:57.01$vck44/va=1,8 2006.145.02:11:57.01#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.02:11:57.01#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.02:11:57.01#ibcon#ireg 11 cls_cnt 2 2006.145.02:11:57.01#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.02:11:57.01#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.02:11:57.01#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.02:11:57.04#ibcon#[25=AT01-08\r\n] 2006.145.02:11:57.07#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.02:11:57.07#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.02:11:57.07#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.02:11:57.07#ibcon#ireg 7 cls_cnt 0 2006.145.02:11:57.07#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.02:11:57.19#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.02:11:57.19#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.02:11:57.22#ibcon#[25=USB\r\n] 2006.145.02:11:57.25#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.02:11:57.25#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.02:11:57.25#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.02:11:57.25#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.02:11:57.25$vck44/valo=2,534.99 2006.145.02:11:57.25#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.02:11:57.25#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.02:11:57.25#ibcon#ireg 17 cls_cnt 0 2006.145.02:11:57.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.02:11:57.25#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.02:11:57.25#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.02:11:57.27#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.02:11:57.31#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.02:11:57.31#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.02:11:57.31#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.02:11:57.31#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.02:11:57.31$vck44/va=2,7 2006.145.02:11:57.31#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.02:11:57.31#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.02:11:57.31#ibcon#ireg 11 cls_cnt 2 2006.145.02:11:57.31#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.02:11:57.38#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.02:11:57.38#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.02:11:57.40#ibcon#[25=AT02-07\r\n] 2006.145.02:11:57.43#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.02:11:57.43#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.02:11:57.43#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.02:11:57.43#ibcon#ireg 7 cls_cnt 0 2006.145.02:11:57.43#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.02:11:57.55#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.02:11:57.55#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.02:11:57.57#ibcon#[25=USB\r\n] 2006.145.02:11:57.60#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.02:11:57.60#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.02:11:57.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.02:11:57.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.02:11:57.60$vck44/valo=3,564.99 2006.145.02:11:57.60#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.02:11:57.60#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.02:11:57.60#ibcon#ireg 17 cls_cnt 0 2006.145.02:11:57.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.02:11:57.60#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.02:11:57.60#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.02:11:57.63#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.02:11:57.67#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.02:11:57.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.02:11:57.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.02:11:57.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.02:11:57.67$vck44/va=3,8 2006.145.02:11:57.67#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.02:11:57.67#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.02:11:57.67#ibcon#ireg 11 cls_cnt 2 2006.145.02:11:57.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.02:11:57.72#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.02:11:57.72#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.02:11:57.74#ibcon#[25=AT03-08\r\n] 2006.145.02:11:57.77#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.02:11:57.77#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.02:11:57.77#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.02:11:57.77#ibcon#ireg 7 cls_cnt 0 2006.145.02:11:57.77#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.02:11:57.89#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.02:11:57.89#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.02:11:57.91#ibcon#[25=USB\r\n] 2006.145.02:11:57.94#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.02:11:57.94#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.02:11:57.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.02:11:57.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.02:11:57.94$vck44/valo=4,624.99 2006.145.02:11:57.94#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.02:11:57.94#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.02:11:57.94#ibcon#ireg 17 cls_cnt 0 2006.145.02:11:57.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.02:11:57.94#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.02:11:57.94#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.02:11:57.96#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.02:11:58.00#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.02:11:58.00#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.02:11:58.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.02:11:58.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.02:11:58.00$vck44/va=4,7 2006.145.02:11:58.00#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.02:11:58.00#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.02:11:58.00#ibcon#ireg 11 cls_cnt 2 2006.145.02:11:58.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.02:11:58.06#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.02:11:58.06#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.02:11:58.08#ibcon#[25=AT04-07\r\n] 2006.145.02:11:58.11#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.02:11:58.11#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.02:11:58.11#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.02:11:58.11#ibcon#ireg 7 cls_cnt 0 2006.145.02:11:58.11#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.02:11:58.23#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.02:11:58.23#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.02:11:58.25#ibcon#[25=USB\r\n] 2006.145.02:11:58.28#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.02:11:58.28#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.02:11:58.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.02:11:58.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.02:11:58.28$vck44/valo=5,734.99 2006.145.02:11:58.28#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.02:11:58.28#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.02:11:58.28#ibcon#ireg 17 cls_cnt 0 2006.145.02:11:58.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.02:11:58.28#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.02:11:58.28#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.02:11:58.30#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.02:11:58.34#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.02:11:58.34#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.02:11:58.34#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.02:11:58.34#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.02:11:58.34$vck44/va=5,4 2006.145.02:11:58.34#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.02:11:58.34#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.02:11:58.34#ibcon#ireg 11 cls_cnt 2 2006.145.02:11:58.34#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.02:11:58.40#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.02:11:58.40#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.02:11:58.42#ibcon#[25=AT05-04\r\n] 2006.145.02:11:58.45#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.02:11:58.45#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.02:11:58.45#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.02:11:58.45#ibcon#ireg 7 cls_cnt 0 2006.145.02:11:58.45#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.02:11:58.57#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.02:11:58.57#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.02:11:58.59#ibcon#[25=USB\r\n] 2006.145.02:11:58.62#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.02:11:58.62#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.02:11:58.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.02:11:58.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.02:11:58.62$vck44/valo=6,814.99 2006.145.02:11:58.62#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.02:11:58.62#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.02:11:58.62#ibcon#ireg 17 cls_cnt 0 2006.145.02:11:58.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.02:11:58.62#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.02:11:58.62#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.02:11:58.64#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.02:11:58.68#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.02:11:58.68#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.02:11:58.68#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.02:11:58.68#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.02:11:58.68$vck44/va=6,4 2006.145.02:11:58.68#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.02:11:58.68#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.02:11:58.68#ibcon#ireg 11 cls_cnt 2 2006.145.02:11:58.68#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.02:11:58.74#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.02:11:58.74#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.02:11:58.76#ibcon#[25=AT06-04\r\n] 2006.145.02:11:58.79#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.02:11:58.79#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.02:11:58.79#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.02:11:58.79#ibcon#ireg 7 cls_cnt 0 2006.145.02:11:58.79#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.02:11:58.91#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.02:11:58.91#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.02:11:58.93#ibcon#[25=USB\r\n] 2006.145.02:11:58.96#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.02:11:58.96#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.02:11:58.96#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.02:11:58.96#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.02:11:58.96$vck44/valo=7,864.99 2006.145.02:11:58.96#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.02:11:58.96#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.02:11:58.96#ibcon#ireg 17 cls_cnt 0 2006.145.02:11:58.96#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.02:11:58.96#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.02:11:58.96#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.02:11:58.98#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.02:11:59.02#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.02:11:59.02#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.02:11:59.02#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.02:11:59.02#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.02:11:59.02$vck44/va=7,4 2006.145.02:11:59.02#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.02:11:59.02#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.02:11:59.02#ibcon#ireg 11 cls_cnt 2 2006.145.02:11:59.02#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.02:11:59.08#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.02:11:59.08#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.02:11:59.10#ibcon#[25=AT07-04\r\n] 2006.145.02:11:59.13#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.02:11:59.13#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.02:11:59.13#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.02:11:59.13#ibcon#ireg 7 cls_cnt 0 2006.145.02:11:59.13#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.02:11:59.25#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.02:11:59.25#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.02:11:59.27#ibcon#[25=USB\r\n] 2006.145.02:11:59.30#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.02:11:59.30#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.02:11:59.30#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.02:11:59.30#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.02:11:59.30$vck44/valo=8,884.99 2006.145.02:11:59.30#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.02:11:59.30#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.02:11:59.30#ibcon#ireg 17 cls_cnt 0 2006.145.02:11:59.30#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.02:11:59.30#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.02:11:59.30#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.02:11:59.32#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.02:11:59.36#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.02:11:59.36#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.02:11:59.36#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.02:11:59.36#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.02:11:59.36$vck44/va=8,4 2006.145.02:11:59.36#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.02:11:59.36#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.02:11:59.36#ibcon#ireg 11 cls_cnt 2 2006.145.02:11:59.36#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.02:11:59.42#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.02:11:59.42#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.02:11:59.44#ibcon#[25=AT08-04\r\n] 2006.145.02:11:59.47#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.02:11:59.47#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.02:11:59.47#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.02:11:59.47#ibcon#ireg 7 cls_cnt 0 2006.145.02:11:59.47#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.02:11:59.59#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.02:11:59.59#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.02:11:59.61#ibcon#[25=USB\r\n] 2006.145.02:11:59.64#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.02:11:59.64#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.02:11:59.64#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.02:11:59.64#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.02:11:59.64$vck44/vblo=1,629.99 2006.145.02:11:59.64#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.02:11:59.64#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.02:11:59.64#ibcon#ireg 17 cls_cnt 0 2006.145.02:11:59.64#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.02:11:59.64#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.02:11:59.64#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.02:11:59.66#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.02:11:59.70#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.02:11:59.70#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.02:11:59.70#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.02:11:59.70#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.02:11:59.70$vck44/vb=1,3 2006.145.02:11:59.70#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.02:11:59.70#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.02:11:59.70#ibcon#ireg 11 cls_cnt 2 2006.145.02:11:59.70#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.02:11:59.70#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.02:11:59.70#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.02:11:59.72#ibcon#[27=AT01-03\r\n] 2006.145.02:11:59.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.02:11:59.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.02:11:59.75#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.02:11:59.75#ibcon#ireg 7 cls_cnt 0 2006.145.02:11:59.75#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.02:11:59.87#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.02:11:59.87#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.02:11:59.89#ibcon#[27=USB\r\n] 2006.145.02:11:59.92#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.02:11:59.92#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.02:11:59.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.02:11:59.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.02:11:59.92$vck44/vblo=2,634.99 2006.145.02:11:59.92#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.02:11:59.92#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.02:11:59.92#ibcon#ireg 17 cls_cnt 0 2006.145.02:11:59.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.02:11:59.92#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.02:11:59.92#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.02:11:59.94#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.02:11:59.98#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.02:11:59.98#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.02:11:59.98#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.02:11:59.98#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.02:11:59.98$vck44/vb=2,4 2006.145.02:11:59.98#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.02:11:59.98#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.02:11:59.98#ibcon#ireg 11 cls_cnt 2 2006.145.02:11:59.98#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.02:12:00.04#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.02:12:00.04#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.02:12:00.06#ibcon#[27=AT02-04\r\n] 2006.145.02:12:00.09#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.02:12:00.09#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.02:12:00.09#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.02:12:00.09#ibcon#ireg 7 cls_cnt 0 2006.145.02:12:00.09#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.02:12:00.21#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.02:12:00.21#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.02:12:00.23#ibcon#[27=USB\r\n] 2006.145.02:12:00.26#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.02:12:00.26#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.02:12:00.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.02:12:00.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.02:12:00.26$vck44/vblo=3,649.99 2006.145.02:12:00.26#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.02:12:00.26#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.02:12:00.26#ibcon#ireg 17 cls_cnt 0 2006.145.02:12:00.26#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.02:12:00.26#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.02:12:00.26#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.02:12:00.28#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.02:12:00.32#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.02:12:00.32#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.02:12:00.32#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.02:12:00.32#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.02:12:00.32$vck44/vb=3,4 2006.145.02:12:00.32#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.02:12:00.32#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.02:12:00.32#ibcon#ireg 11 cls_cnt 2 2006.145.02:12:00.32#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.02:12:00.38#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.02:12:00.38#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.02:12:00.40#ibcon#[27=AT03-04\r\n] 2006.145.02:12:00.43#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.02:12:00.43#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.02:12:00.43#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.02:12:00.43#ibcon#ireg 7 cls_cnt 0 2006.145.02:12:00.43#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.02:12:00.55#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.02:12:00.55#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.02:12:00.57#ibcon#[27=USB\r\n] 2006.145.02:12:00.60#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.02:12:00.60#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.02:12:00.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.02:12:00.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.02:12:00.60$vck44/vblo=4,679.99 2006.145.02:12:00.60#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.02:12:00.60#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.02:12:00.60#ibcon#ireg 17 cls_cnt 0 2006.145.02:12:00.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.02:12:00.60#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.02:12:00.60#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.02:12:00.62#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.02:12:00.66#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.02:12:00.66#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.02:12:00.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.02:12:00.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.02:12:00.66$vck44/vb=4,4 2006.145.02:12:00.66#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.02:12:00.66#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.02:12:00.66#ibcon#ireg 11 cls_cnt 2 2006.145.02:12:00.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.02:12:00.72#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.02:12:00.72#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.02:12:00.74#ibcon#[27=AT04-04\r\n] 2006.145.02:12:00.77#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.02:12:00.77#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.02:12:00.77#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.02:12:00.77#ibcon#ireg 7 cls_cnt 0 2006.145.02:12:00.77#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.02:12:00.89#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.02:12:00.89#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.02:12:00.91#ibcon#[27=USB\r\n] 2006.145.02:12:00.94#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.02:12:00.94#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.02:12:00.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.02:12:00.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.02:12:00.94$vck44/vblo=5,709.99 2006.145.02:12:00.94#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.02:12:00.94#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.02:12:00.94#ibcon#ireg 17 cls_cnt 0 2006.145.02:12:00.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.02:12:00.94#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.02:12:00.94#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.02:12:00.96#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.02:12:01.00#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.02:12:01.00#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.02:12:01.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.02:12:01.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.02:12:01.00$vck44/vb=5,4 2006.145.02:12:01.00#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.02:12:01.00#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.02:12:01.00#ibcon#ireg 11 cls_cnt 2 2006.145.02:12:01.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.02:12:01.06#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.02:12:01.06#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.02:12:01.08#ibcon#[27=AT05-04\r\n] 2006.145.02:12:01.11#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.02:12:01.11#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.02:12:01.11#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.02:12:01.11#ibcon#ireg 7 cls_cnt 0 2006.145.02:12:01.11#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.02:12:01.23#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.02:12:01.23#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.02:12:01.25#ibcon#[27=USB\r\n] 2006.145.02:12:01.28#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.02:12:01.28#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.02:12:01.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.02:12:01.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.02:12:01.28$vck44/vblo=6,719.99 2006.145.02:12:01.28#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.02:12:01.28#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.02:12:01.28#ibcon#ireg 17 cls_cnt 0 2006.145.02:12:01.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.02:12:01.28#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.02:12:01.28#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.02:12:01.30#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.02:12:01.34#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.02:12:01.34#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.02:12:01.34#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.02:12:01.34#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.02:12:01.34$vck44/vb=6,4 2006.145.02:12:01.34#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.02:12:01.34#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.02:12:01.34#ibcon#ireg 11 cls_cnt 2 2006.145.02:12:01.34#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.02:12:01.40#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.02:12:01.40#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.02:12:01.42#ibcon#[27=AT06-04\r\n] 2006.145.02:12:01.45#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.02:12:01.45#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.02:12:01.45#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.02:12:01.45#ibcon#ireg 7 cls_cnt 0 2006.145.02:12:01.45#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.02:12:01.57#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.02:12:01.57#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.02:12:01.59#ibcon#[27=USB\r\n] 2006.145.02:12:01.62#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.02:12:01.62#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.02:12:01.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.02:12:01.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.02:12:01.62$vck44/vblo=7,734.99 2006.145.02:12:01.62#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.02:12:01.62#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.02:12:01.62#ibcon#ireg 17 cls_cnt 0 2006.145.02:12:01.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.02:12:01.62#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.02:12:01.62#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.02:12:01.64#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.02:12:01.68#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.02:12:01.68#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.02:12:01.68#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.02:12:01.68#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.02:12:01.68$vck44/vb=7,4 2006.145.02:12:01.68#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.02:12:01.68#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.02:12:01.68#ibcon#ireg 11 cls_cnt 2 2006.145.02:12:01.68#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.02:12:01.74#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.02:12:01.74#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.02:12:01.76#ibcon#[27=AT07-04\r\n] 2006.145.02:12:01.79#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.02:12:01.79#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.02:12:01.79#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.02:12:01.79#ibcon#ireg 7 cls_cnt 0 2006.145.02:12:01.79#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.02:12:01.91#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.02:12:01.91#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.02:12:01.93#ibcon#[27=USB\r\n] 2006.145.02:12:01.96#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.02:12:01.96#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.02:12:01.96#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.02:12:01.96#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.02:12:01.96$vck44/vblo=8,744.99 2006.145.02:12:01.96#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.02:12:01.96#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.02:12:01.96#ibcon#ireg 17 cls_cnt 0 2006.145.02:12:01.96#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.02:12:01.96#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.02:12:01.96#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.02:12:01.98#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.02:12:02.02#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.02:12:02.02#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.02:12:02.02#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.02:12:02.02#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.02:12:02.02$vck44/vb=8,4 2006.145.02:12:02.02#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.02:12:02.02#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.02:12:02.02#ibcon#ireg 11 cls_cnt 2 2006.145.02:12:02.02#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.02:12:02.08#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.02:12:02.08#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.02:12:02.10#ibcon#[27=AT08-04\r\n] 2006.145.02:12:02.13#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.02:12:02.13#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.02:12:02.13#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.02:12:02.13#ibcon#ireg 7 cls_cnt 0 2006.145.02:12:02.13#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.02:12:02.25#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.02:12:02.25#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.02:12:02.27#ibcon#[27=USB\r\n] 2006.145.02:12:02.30#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.02:12:02.30#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.02:12:02.30#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.02:12:02.30#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.02:12:02.30$vck44/vabw=wide 2006.145.02:12:02.30#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.02:12:02.30#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.02:12:02.30#ibcon#ireg 8 cls_cnt 0 2006.145.02:12:02.30#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.02:12:02.30#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.02:12:02.30#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.02:12:02.32#ibcon#[25=BW32\r\n] 2006.145.02:12:02.35#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.02:12:02.35#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.02:12:02.35#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.02:12:02.35#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.02:12:02.35$vck44/vbbw=wide 2006.145.02:12:02.35#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.02:12:02.35#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.02:12:02.35#ibcon#ireg 8 cls_cnt 0 2006.145.02:12:02.35#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.02:12:02.42#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.02:12:02.42#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.02:12:02.44#ibcon#[27=BW32\r\n] 2006.145.02:12:02.47#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.02:12:02.47#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.02:12:02.47#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.02:12:02.47#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.02:12:02.47$setupk4/ifdk4 2006.145.02:12:02.47$ifdk4/lo= 2006.145.02:12:02.47$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.02:12:02.47$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.02:12:02.47$ifdk4/patch= 2006.145.02:12:02.47$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.02:12:02.47$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.02:12:02.47$setupk4/!*+20s 2006.145.02:12:02.73#abcon#<5=/04 2.9 7.2 19.46 651017.2\r\n> 2006.145.02:12:02.75#abcon#{5=INTERFACE CLEAR} 2006.145.02:12:02.81#abcon#[5=S1D000X0/0*\r\n] 2006.145.02:12:12.90#abcon#<5=/04 2.8 7.2 19.46 641017.2\r\n> 2006.145.02:12:12.92#abcon#{5=INTERFACE CLEAR} 2006.145.02:12:12.98#abcon#[5=S1D000X0/0*\r\n] 2006.145.02:12:16.93$setupk4/"tpicd 2006.145.02:12:16.93$setupk4/echo=off 2006.145.02:12:16.93$setupk4/xlog=off 2006.145.02:12:16.93:!2006.145.02:12:47 2006.145.02:12:19.14#trakl#Source acquired 2006.145.02:12:21.14#flagr#flagr/antenna,acquired 2006.145.02:12:47.00:preob 2006.145.02:12:47.14/onsource/TRACKING 2006.145.02:12:47.14:!2006.145.02:12:57 2006.145.02:12:57.00:"tape 2006.145.02:12:57.00:"st=record 2006.145.02:12:57.00:data_valid=on 2006.145.02:12:57.00:midob 2006.145.02:12:57.14/onsource/TRACKING 2006.145.02:12:57.14/wx/19.48,1017.3,63 2006.145.02:12:57.20/cable/+6.5501E-03 2006.145.02:12:58.29/va/01,08,usb,yes,30,33 2006.145.02:12:58.29/va/02,07,usb,yes,32,33 2006.145.02:12:58.29/va/03,08,usb,yes,29,31 2006.145.02:12:58.29/va/04,07,usb,yes,33,35 2006.145.02:12:58.29/va/05,04,usb,yes,29,30 2006.145.02:12:58.29/va/06,04,usb,yes,33,33 2006.145.02:12:58.29/va/07,04,usb,yes,33,34 2006.145.02:12:58.29/va/08,04,usb,yes,28,34 2006.145.02:12:58.52/valo/01,524.99,yes,locked 2006.145.02:12:58.52/valo/02,534.99,yes,locked 2006.145.02:12:58.52/valo/03,564.99,yes,locked 2006.145.02:12:58.52/valo/04,624.99,yes,locked 2006.145.02:12:58.52/valo/05,734.99,yes,locked 2006.145.02:12:58.52/valo/06,814.99,yes,locked 2006.145.02:12:58.52/valo/07,864.99,yes,locked 2006.145.02:12:58.52/valo/08,884.99,yes,locked 2006.145.02:12:59.61/vb/01,03,usb,yes,37,34 2006.145.02:12:59.61/vb/02,04,usb,yes,32,32 2006.145.02:12:59.61/vb/03,04,usb,yes,29,32 2006.145.02:12:59.61/vb/04,04,usb,yes,34,33 2006.145.02:12:59.61/vb/05,04,usb,yes,26,29 2006.145.02:12:59.61/vb/06,04,usb,yes,31,27 2006.145.02:12:59.61/vb/07,04,usb,yes,30,30 2006.145.02:12:59.61/vb/08,04,usb,yes,28,31 2006.145.02:12:59.85/vblo/01,629.99,yes,locked 2006.145.02:12:59.85/vblo/02,634.99,yes,locked 2006.145.02:12:59.85/vblo/03,649.99,yes,locked 2006.145.02:12:59.85/vblo/04,679.99,yes,locked 2006.145.02:12:59.85/vblo/05,709.99,yes,locked 2006.145.02:12:59.85/vblo/06,719.99,yes,locked 2006.145.02:12:59.85/vblo/07,734.99,yes,locked 2006.145.02:12:59.85/vblo/08,744.99,yes,locked 2006.145.02:13:00.00/vabw/8 2006.145.02:13:00.15/vbbw/8 2006.145.02:13:00.24/xfe/off,on,14.7 2006.145.02:13:00.62/ifatt/23,28,28,28 2006.145.02:13:01.07/fmout-gps/S +5.4E-08 2006.145.02:13:01.11:!2006.145.02:14:07 2006.145.02:14:07.01:data_valid=off 2006.145.02:14:07.01:"et 2006.145.02:14:07.02:!+3s 2006.145.02:14:10.03:"tape 2006.145.02:14:10.03:postob 2006.145.02:14:10.25/cable/+6.5480E-03 2006.145.02:14:10.25/wx/19.50,1017.3,66 2006.145.02:14:10.33/fmout-gps/S +5.4E-08 2006.145.02:14:10.34:scan_name=145-0217,jd0605,40 2006.145.02:14:10.34:source=0537-441,053850.36,-440508.9,2000.0,cw 2006.145.02:14:12.14#flagr#flagr/antenna,new-source 2006.145.02:14:12.14:checkk5 2006.145.02:14:12.57/chk_autoobs//k5ts1/ autoobs is running! 2006.145.02:14:12.98/chk_autoobs//k5ts2/ autoobs is running! 2006.145.02:14:13.38/chk_autoobs//k5ts3/ autoobs is running! 2006.145.02:14:13.87/chk_autoobs//k5ts4/ autoobs is running! 2006.145.02:14:14.27/chk_obsdata//k5ts1/T1450212??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.02:14:14.68/chk_obsdata//k5ts2/T1450212??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.02:14:15.14/chk_obsdata//k5ts3/T1450212??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.02:14:15.55/chk_obsdata//k5ts4/T1450212??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.02:14:16.84/k5log//k5ts1_log_newline 2006.145.02:14:17.68/k5log//k5ts2_log_newline 2006.145.02:14:18.38/k5log//k5ts3_log_newline 2006.145.02:14:19.10/k5log//k5ts4_log_newline 2006.145.02:14:19.12/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.02:14:19.12:setupk4=1 2006.145.02:14:19.12$setupk4/echo=on 2006.145.02:14:19.12$setupk4/pcalon 2006.145.02:14:19.12$pcalon/"no phase cal control is implemented here 2006.145.02:14:19.12$setupk4/"tpicd=stop 2006.145.02:14:19.13$setupk4/"rec=synch_on 2006.145.02:14:19.13$setupk4/"rec_mode=128 2006.145.02:14:19.13$setupk4/!* 2006.145.02:14:19.13$setupk4/recpk4 2006.145.02:14:19.13$recpk4/recpatch= 2006.145.02:14:19.13$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.02:14:19.13$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.02:14:19.13$setupk4/vck44 2006.145.02:14:19.13$vck44/valo=1,524.99 2006.145.02:14:19.13#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.02:14:19.13#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.02:14:19.13#ibcon#ireg 17 cls_cnt 0 2006.145.02:14:19.13#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:14:19.13#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:14:19.13#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:14:19.17#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.02:14:19.22#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:14:19.22#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:14:19.22#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.02:14:19.22#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.02:14:19.22$vck44/va=1,8 2006.145.02:14:19.22#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.02:14:19.22#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.02:14:19.22#ibcon#ireg 11 cls_cnt 2 2006.145.02:14:19.22#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:14:19.22#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:14:19.22#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:14:19.25#ibcon#[25=AT01-08\r\n] 2006.145.02:14:19.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:14:19.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:14:19.28#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.02:14:19.28#ibcon#ireg 7 cls_cnt 0 2006.145.02:14:19.28#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:14:19.40#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:14:19.40#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:14:19.42#ibcon#[25=USB\r\n] 2006.145.02:14:19.47#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:14:19.47#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:14:19.47#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.02:14:19.47#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.02:14:19.47$vck44/valo=2,534.99 2006.145.02:14:19.47#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.02:14:19.47#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.02:14:19.47#ibcon#ireg 17 cls_cnt 0 2006.145.02:14:19.47#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:14:19.47#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:14:19.47#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:14:19.48#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.02:14:19.52#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:14:19.52#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:14:19.52#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.02:14:19.52#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.02:14:19.52$vck44/va=2,7 2006.145.02:14:19.52#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.02:14:19.52#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.02:14:19.52#ibcon#ireg 11 cls_cnt 2 2006.145.02:14:19.52#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:14:19.59#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:14:19.59#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:14:19.61#ibcon#[25=AT02-07\r\n] 2006.145.02:14:19.64#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:14:19.64#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:14:19.64#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.02:14:19.64#ibcon#ireg 7 cls_cnt 0 2006.145.02:14:19.64#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:14:19.76#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:14:19.76#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:14:19.78#ibcon#[25=USB\r\n] 2006.145.02:14:19.83#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:14:19.83#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:14:19.83#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.02:14:19.83#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.02:14:19.83$vck44/valo=3,564.99 2006.145.02:14:19.83#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.02:14:19.83#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.02:14:19.83#ibcon#ireg 17 cls_cnt 0 2006.145.02:14:19.83#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:14:19.83#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:14:19.83#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:14:19.84#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.02:14:19.88#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:14:19.88#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:14:19.88#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.02:14:19.88#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.02:14:19.88$vck44/va=3,8 2006.145.02:14:19.88#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.02:14:19.88#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.02:14:19.88#ibcon#ireg 11 cls_cnt 2 2006.145.02:14:19.88#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.02:14:19.95#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.02:14:19.95#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.02:14:19.97#ibcon#[25=AT03-08\r\n] 2006.145.02:14:20.00#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.02:14:20.00#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.02:14:20.00#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.02:14:20.00#ibcon#ireg 7 cls_cnt 0 2006.145.02:14:20.00#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.02:14:20.12#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.02:14:20.12#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.02:14:20.14#ibcon#[25=USB\r\n] 2006.145.02:14:20.17#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.02:14:20.17#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.02:14:20.17#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.02:14:20.17#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.02:14:20.17$vck44/valo=4,624.99 2006.145.02:14:20.17#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.02:14:20.17#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.02:14:20.17#ibcon#ireg 17 cls_cnt 0 2006.145.02:14:20.17#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:14:20.17#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:14:20.17#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:14:20.19#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.02:14:20.23#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:14:20.23#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:14:20.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.02:14:20.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.02:14:20.23$vck44/va=4,7 2006.145.02:14:20.23#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.02:14:20.23#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.02:14:20.23#ibcon#ireg 11 cls_cnt 2 2006.145.02:14:20.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:14:20.29#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:14:20.29#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:14:20.31#ibcon#[25=AT04-07\r\n] 2006.145.02:14:20.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:14:20.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:14:20.34#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.02:14:20.34#ibcon#ireg 7 cls_cnt 0 2006.145.02:14:20.34#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:14:20.46#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:14:20.46#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:14:20.48#ibcon#[25=USB\r\n] 2006.145.02:14:20.51#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:14:20.51#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:14:20.51#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.02:14:20.51#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.02:14:20.51$vck44/valo=5,734.99 2006.145.02:14:20.51#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.02:14:20.51#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.02:14:20.51#ibcon#ireg 17 cls_cnt 0 2006.145.02:14:20.51#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:14:20.51#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:14:20.51#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:14:20.53#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.02:14:20.57#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:14:20.57#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:14:20.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.02:14:20.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.02:14:20.57$vck44/va=5,4 2006.145.02:14:20.57#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.02:14:20.57#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.02:14:20.57#ibcon#ireg 11 cls_cnt 2 2006.145.02:14:20.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:14:20.63#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:14:20.63#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:14:20.65#ibcon#[25=AT05-04\r\n] 2006.145.02:14:20.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:14:20.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:14:20.68#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.02:14:20.68#ibcon#ireg 7 cls_cnt 0 2006.145.02:14:20.68#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:14:20.80#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:14:20.80#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:14:20.82#ibcon#[25=USB\r\n] 2006.145.02:14:20.85#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:14:20.85#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:14:20.85#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.02:14:20.85#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.02:14:20.85$vck44/valo=6,814.99 2006.145.02:14:20.85#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.02:14:20.85#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.02:14:20.85#ibcon#ireg 17 cls_cnt 0 2006.145.02:14:20.85#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:14:20.85#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:14:20.85#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:14:20.87#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.02:14:20.91#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:14:20.91#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:14:20.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.02:14:20.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.02:14:20.91$vck44/va=6,4 2006.145.02:14:20.91#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.02:14:20.91#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.02:14:20.91#ibcon#ireg 11 cls_cnt 2 2006.145.02:14:20.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:14:20.97#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:14:20.97#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:14:20.99#ibcon#[25=AT06-04\r\n] 2006.145.02:14:21.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:14:21.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:14:21.02#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.02:14:21.02#ibcon#ireg 7 cls_cnt 0 2006.145.02:14:21.02#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:14:21.14#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:14:21.14#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:14:21.16#ibcon#[25=USB\r\n] 2006.145.02:14:21.19#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:14:21.19#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:14:21.19#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.02:14:21.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.02:14:21.19$vck44/valo=7,864.99 2006.145.02:14:21.19#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.02:14:21.19#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.02:14:21.19#ibcon#ireg 17 cls_cnt 0 2006.145.02:14:21.19#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:14:21.19#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:14:21.19#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:14:21.21#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.02:14:21.25#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:14:21.25#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:14:21.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.02:14:21.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.02:14:21.25$vck44/va=7,4 2006.145.02:14:21.25#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.02:14:21.25#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.02:14:21.25#ibcon#ireg 11 cls_cnt 2 2006.145.02:14:21.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:14:21.31#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:14:21.31#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:14:21.33#ibcon#[25=AT07-04\r\n] 2006.145.02:14:21.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:14:21.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:14:21.36#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.02:14:21.36#ibcon#ireg 7 cls_cnt 0 2006.145.02:14:21.36#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:14:21.48#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:14:21.48#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:14:21.50#ibcon#[25=USB\r\n] 2006.145.02:14:21.53#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:14:21.53#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:14:21.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.02:14:21.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.02:14:21.53$vck44/valo=8,884.99 2006.145.02:14:21.53#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.02:14:21.53#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.02:14:21.53#ibcon#ireg 17 cls_cnt 0 2006.145.02:14:21.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:14:21.53#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:14:21.53#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:14:21.56#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.02:14:21.60#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:14:21.60#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:14:21.60#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.02:14:21.60#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.02:14:21.60$vck44/va=8,4 2006.145.02:14:21.60#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.02:14:21.60#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.02:14:21.60#ibcon#ireg 11 cls_cnt 2 2006.145.02:14:21.60#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:14:21.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:14:21.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:14:21.67#ibcon#[25=AT08-04\r\n] 2006.145.02:14:21.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:14:21.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:14:21.70#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.02:14:21.70#ibcon#ireg 7 cls_cnt 0 2006.145.02:14:21.70#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:14:21.82#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:14:21.82#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:14:21.84#ibcon#[25=USB\r\n] 2006.145.02:14:21.87#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:14:21.87#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:14:21.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.02:14:21.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.02:14:21.87$vck44/vblo=1,629.99 2006.145.02:14:21.87#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.02:14:21.87#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.02:14:21.87#ibcon#ireg 17 cls_cnt 0 2006.145.02:14:21.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:14:21.87#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:14:21.87#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:14:21.89#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.02:14:21.93#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:14:21.93#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:14:21.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.02:14:21.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.02:14:21.93$vck44/vb=1,3 2006.145.02:14:21.93#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.02:14:21.93#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.02:14:21.93#ibcon#ireg 11 cls_cnt 2 2006.145.02:14:21.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:14:21.93#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:14:21.93#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:14:21.95#ibcon#[27=AT01-03\r\n] 2006.145.02:14:21.98#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:14:21.98#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:14:21.98#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.02:14:21.98#ibcon#ireg 7 cls_cnt 0 2006.145.02:14:21.98#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:14:22.10#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:14:22.10#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:14:22.12#ibcon#[27=USB\r\n] 2006.145.02:14:22.15#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:14:22.15#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:14:22.15#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.02:14:22.15#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.02:14:22.15$vck44/vblo=2,634.99 2006.145.02:14:22.15#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.02:14:22.15#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.02:14:22.15#ibcon#ireg 17 cls_cnt 0 2006.145.02:14:22.15#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:14:22.15#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:14:22.15#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:14:22.17#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.02:14:22.21#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:14:22.21#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:14:22.21#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.02:14:22.21#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.02:14:22.21$vck44/vb=2,4 2006.145.02:14:22.21#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.02:14:22.21#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.02:14:22.21#ibcon#ireg 11 cls_cnt 2 2006.145.02:14:22.21#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:14:22.27#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:14:22.27#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:14:22.29#ibcon#[27=AT02-04\r\n] 2006.145.02:14:22.32#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:14:22.32#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:14:22.32#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.02:14:22.32#ibcon#ireg 7 cls_cnt 0 2006.145.02:14:22.32#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:14:22.44#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:14:22.44#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:14:22.46#ibcon#[27=USB\r\n] 2006.145.02:14:22.49#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:14:22.49#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:14:22.49#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.02:14:22.49#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.02:14:22.49$vck44/vblo=3,649.99 2006.145.02:14:22.49#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.02:14:22.49#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.02:14:22.49#ibcon#ireg 17 cls_cnt 0 2006.145.02:14:22.49#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:14:22.49#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:14:22.49#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:14:22.51#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.02:14:22.55#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:14:22.55#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:14:22.55#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.02:14:22.55#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.02:14:22.55$vck44/vb=3,4 2006.145.02:14:22.55#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.02:14:22.55#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.02:14:22.55#ibcon#ireg 11 cls_cnt 2 2006.145.02:14:22.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:14:22.61#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:14:22.61#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:14:22.63#ibcon#[27=AT03-04\r\n] 2006.145.02:14:22.66#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:14:22.66#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:14:22.66#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.02:14:22.66#ibcon#ireg 7 cls_cnt 0 2006.145.02:14:22.66#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:14:22.78#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:14:22.78#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:14:22.80#ibcon#[27=USB\r\n] 2006.145.02:14:22.83#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:14:22.83#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:14:22.83#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.02:14:22.83#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.02:14:22.83$vck44/vblo=4,679.99 2006.145.02:14:22.83#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.02:14:22.83#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.02:14:22.83#ibcon#ireg 17 cls_cnt 0 2006.145.02:14:22.83#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:14:22.83#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:14:22.83#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:14:22.85#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.02:14:22.89#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:14:22.89#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:14:22.89#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.02:14:22.89#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.02:14:22.89$vck44/vb=4,4 2006.145.02:14:22.89#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.02:14:22.89#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.02:14:22.89#ibcon#ireg 11 cls_cnt 2 2006.145.02:14:22.89#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.02:14:22.95#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.02:14:22.95#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.02:14:22.97#ibcon#[27=AT04-04\r\n] 2006.145.02:14:23.00#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.02:14:23.00#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.02:14:23.00#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.02:14:23.00#ibcon#ireg 7 cls_cnt 0 2006.145.02:14:23.00#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.02:14:23.12#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.02:14:23.12#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.02:14:23.14#ibcon#[27=USB\r\n] 2006.145.02:14:23.17#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.02:14:23.17#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.02:14:23.17#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.02:14:23.17#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.02:14:23.17$vck44/vblo=5,709.99 2006.145.02:14:23.17#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.02:14:23.17#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.02:14:23.17#ibcon#ireg 17 cls_cnt 0 2006.145.02:14:23.17#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:14:23.17#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:14:23.17#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:14:23.19#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.02:14:23.23#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:14:23.23#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:14:23.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.02:14:23.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.02:14:23.23$vck44/vb=5,4 2006.145.02:14:23.23#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.02:14:23.23#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.02:14:23.23#ibcon#ireg 11 cls_cnt 2 2006.145.02:14:23.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:14:23.29#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:14:23.29#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:14:23.31#ibcon#[27=AT05-04\r\n] 2006.145.02:14:23.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:14:23.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:14:23.34#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.02:14:23.34#ibcon#ireg 7 cls_cnt 0 2006.145.02:14:23.34#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:14:23.46#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:14:23.46#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:14:23.48#ibcon#[27=USB\r\n] 2006.145.02:14:23.51#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:14:23.51#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:14:23.51#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.02:14:23.51#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.02:14:23.51$vck44/vblo=6,719.99 2006.145.02:14:23.51#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.02:14:23.51#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.02:14:23.51#ibcon#ireg 17 cls_cnt 0 2006.145.02:14:23.51#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:14:23.51#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:14:23.51#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:14:23.53#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.02:14:23.57#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:14:23.57#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:14:23.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.02:14:23.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.02:14:23.57$vck44/vb=6,4 2006.145.02:14:23.57#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.02:14:23.57#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.02:14:23.57#ibcon#ireg 11 cls_cnt 2 2006.145.02:14:23.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:14:23.63#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:14:23.63#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:14:23.65#ibcon#[27=AT06-04\r\n] 2006.145.02:14:23.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:14:23.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:14:23.68#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.02:14:23.68#ibcon#ireg 7 cls_cnt 0 2006.145.02:14:23.68#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:14:23.80#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:14:23.80#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:14:23.82#ibcon#[27=USB\r\n] 2006.145.02:14:23.87#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:14:23.87#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:14:23.87#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.02:14:23.87#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.02:14:23.87$vck44/vblo=7,734.99 2006.145.02:14:23.87#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.02:14:23.87#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.02:14:23.87#ibcon#ireg 17 cls_cnt 0 2006.145.02:14:23.87#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:14:23.87#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:14:23.87#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:14:23.88#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.02:14:23.92#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:14:23.92#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:14:23.92#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.02:14:23.92#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.02:14:23.92$vck44/vb=7,4 2006.145.02:14:23.92#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.02:14:23.92#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.02:14:23.92#ibcon#ireg 11 cls_cnt 2 2006.145.02:14:23.92#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:14:23.99#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:14:23.99#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:14:24.01#ibcon#[27=AT07-04\r\n] 2006.145.02:14:24.04#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:14:24.04#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:14:24.04#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.02:14:24.04#ibcon#ireg 7 cls_cnt 0 2006.145.02:14:24.04#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:14:24.16#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:14:24.16#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:14:24.18#ibcon#[27=USB\r\n] 2006.145.02:14:24.21#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:14:24.21#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:14:24.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.02:14:24.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.02:14:24.21$vck44/vblo=8,744.99 2006.145.02:14:24.21#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.02:14:24.21#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.02:14:24.21#ibcon#ireg 17 cls_cnt 0 2006.145.02:14:24.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:14:24.21#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:14:24.21#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:14:24.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.02:14:24.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:14:24.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:14:24.27#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.02:14:24.27#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.02:14:24.27$vck44/vb=8,4 2006.145.02:14:24.27#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.02:14:24.27#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.02:14:24.27#ibcon#ireg 11 cls_cnt 2 2006.145.02:14:24.27#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:14:24.33#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:14:24.33#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:14:24.35#ibcon#[27=AT08-04\r\n] 2006.145.02:14:24.38#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:14:24.38#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:14:24.38#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.02:14:24.38#ibcon#ireg 7 cls_cnt 0 2006.145.02:14:24.38#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:14:24.50#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:14:24.50#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:14:24.52#ibcon#[27=USB\r\n] 2006.145.02:14:24.55#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:14:24.55#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:14:24.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.02:14:24.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.02:14:24.55$vck44/vabw=wide 2006.145.02:14:24.55#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.02:14:24.55#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.02:14:24.55#ibcon#ireg 8 cls_cnt 0 2006.145.02:14:24.55#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:14:24.55#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:14:24.55#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:14:24.57#ibcon#[25=BW32\r\n] 2006.145.02:14:24.60#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:14:24.60#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:14:24.60#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.02:14:24.60#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.02:14:24.60$vck44/vbbw=wide 2006.145.02:14:24.60#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.02:14:24.60#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.02:14:24.60#ibcon#ireg 8 cls_cnt 0 2006.145.02:14:24.60#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.02:14:24.67#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.02:14:24.67#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.02:14:24.69#ibcon#[27=BW32\r\n] 2006.145.02:14:24.72#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.02:14:24.72#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.02:14:24.72#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.02:14:24.72#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.02:14:24.72$setupk4/ifdk4 2006.145.02:14:24.72$ifdk4/lo= 2006.145.02:14:24.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.02:14:24.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.02:14:24.72$ifdk4/patch= 2006.145.02:14:24.72$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.02:14:24.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.02:14:24.72$setupk4/!*+20s 2006.145.02:14:25.12#abcon#<5=/05 3.0 7.2 19.50 641017.3\r\n> 2006.145.02:14:25.14#abcon#{5=INTERFACE CLEAR} 2006.145.02:14:25.20#abcon#[5=S1D000X0/0*\r\n] 2006.145.02:14:34.13#trakl#Source acquired 2006.145.02:14:34.13#flagr#flagr/antenna,acquired 2006.145.02:14:35.29#abcon#<5=/05 3.0 7.1 19.51 641017.3\r\n> 2006.145.02:14:35.31#abcon#{5=INTERFACE CLEAR} 2006.145.02:14:35.37#abcon#[5=S1D000X0/0*\r\n] 2006.145.02:14:39.14$setupk4/"tpicd 2006.145.02:14:39.14$setupk4/echo=off 2006.145.02:14:39.14$setupk4/xlog=off 2006.145.02:14:39.14:!2006.145.02:17:03 2006.145.02:17:03.00:preob 2006.145.02:17:03.14/onsource/TRACKING 2006.145.02:17:03.14:!2006.145.02:17:13 2006.145.02:17:13.00:"tape 2006.145.02:17:13.00:"st=record 2006.145.02:17:13.00:data_valid=on 2006.145.02:17:13.00:midob 2006.145.02:17:13.14/onsource/TRACKING 2006.145.02:17:13.14/wx/19.56,1017.3,69 2006.145.02:17:13.26/cable/+6.5482E-03 2006.145.02:17:14.35/va/01,08,usb,yes,38,41 2006.145.02:17:14.35/va/02,07,usb,yes,41,42 2006.145.02:17:14.35/va/03,08,usb,yes,37,39 2006.145.02:17:14.35/va/04,07,usb,yes,42,44 2006.145.02:17:14.35/va/05,04,usb,yes,37,38 2006.145.02:17:14.35/va/06,04,usb,yes,41,41 2006.145.02:17:14.35/va/07,04,usb,yes,42,43 2006.145.02:17:14.35/va/08,04,usb,yes,36,43 2006.145.02:17:14.58/valo/01,524.99,yes,locked 2006.145.02:17:14.58/valo/02,534.99,yes,locked 2006.145.02:17:14.58/valo/03,564.99,yes,locked 2006.145.02:17:14.58/valo/04,624.99,yes,locked 2006.145.02:17:14.58/valo/05,734.99,yes,locked 2006.145.02:17:14.58/valo/06,814.99,yes,locked 2006.145.02:17:14.58/valo/07,864.99,yes,locked 2006.145.02:17:14.58/valo/08,884.99,yes,locked 2006.145.02:17:15.67/vb/01,03,usb,yes,40,39 2006.145.02:17:15.67/vb/02,04,usb,yes,35,36 2006.145.02:17:15.67/vb/03,04,usb,yes,32,35 2006.145.02:17:15.67/vb/04,04,usb,yes,36,35 2006.145.02:17:15.67/vb/05,04,usb,yes,29,31 2006.145.02:17:15.67/vb/06,04,usb,yes,34,30 2006.145.02:17:15.67/vb/07,04,usb,yes,33,33 2006.145.02:17:15.67/vb/08,04,usb,yes,31,34 2006.145.02:17:15.90/vblo/01,629.99,yes,locked 2006.145.02:17:15.90/vblo/02,634.99,yes,locked 2006.145.02:17:15.90/vblo/03,649.99,yes,locked 2006.145.02:17:15.90/vblo/04,679.99,yes,locked 2006.145.02:17:15.90/vblo/05,709.99,yes,locked 2006.145.02:17:15.90/vblo/06,719.99,yes,locked 2006.145.02:17:15.90/vblo/07,734.99,yes,locked 2006.145.02:17:15.90/vblo/08,744.99,yes,locked 2006.145.02:17:16.05/vabw/8 2006.145.02:17:16.20/vbbw/8 2006.145.02:17:16.37/xfe/off,on,15.2 2006.145.02:17:16.75/ifatt/23,28,28,28 2006.145.02:17:17.07/fmout-gps/S +5.3E-08 2006.145.02:17:17.11:!2006.145.02:17:53 2006.145.02:17:53.01:data_valid=off 2006.145.02:17:53.01:"et 2006.145.02:17:53.02:!+3s 2006.145.02:17:56.03:"tape 2006.145.02:17:56.03:postob 2006.145.02:17:56.12/cable/+6.5507E-03 2006.145.02:17:56.12/wx/19.58,1017.3,68 2006.145.02:17:56.20/fmout-gps/S +5.2E-08 2006.145.02:17:56.20:scan_name=145-0221,jd0605,250 2006.145.02:17:56.21:source=cta26,033930.94,-014635.8,2000.0,cw 2006.145.02:17:58.14#flagr#flagr/antenna,new-source 2006.145.02:17:58.14:checkk5 2006.145.02:17:58.56/chk_autoobs//k5ts1/ autoobs is running! 2006.145.02:17:58.98/chk_autoobs//k5ts2/ autoobs is running! 2006.145.02:17:59.41/chk_autoobs//k5ts3/ autoobs is running! 2006.145.02:18:00.01/chk_autoobs//k5ts4/ autoobs is running! 2006.145.02:18:00.40/chk_obsdata//k5ts1/T1450217??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.02:18:00.88/chk_obsdata//k5ts2/T1450217??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.02:18:01.27/chk_obsdata//k5ts3/T1450217??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.02:18:01.74/chk_obsdata//k5ts4/T1450217??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.02:18:02.49/k5log//k5ts1_log_newline 2006.145.02:18:03.53/k5log//k5ts2_log_newline 2006.145.02:18:04.31/k5log//k5ts3_log_newline 2006.145.02:18:05.10/k5log//k5ts4_log_newline 2006.145.02:18:05.13/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.02:18:05.13:setupk4=1 2006.145.02:18:05.13$setupk4/echo=on 2006.145.02:18:05.13$setupk4/pcalon 2006.145.02:18:05.13$pcalon/"no phase cal control is implemented here 2006.145.02:18:05.13$setupk4/"tpicd=stop 2006.145.02:18:05.13$setupk4/"rec=synch_on 2006.145.02:18:05.13$setupk4/"rec_mode=128 2006.145.02:18:05.13$setupk4/!* 2006.145.02:18:05.13$setupk4/recpk4 2006.145.02:18:05.13$recpk4/recpatch= 2006.145.02:18:05.13$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.02:18:05.13$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.02:18:05.13$setupk4/vck44 2006.145.02:18:05.13$vck44/valo=1,524.99 2006.145.02:18:05.13#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.02:18:05.13#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.02:18:05.13#ibcon#ireg 17 cls_cnt 0 2006.145.02:18:05.13#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.02:18:05.13#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.02:18:05.13#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.02:18:05.17#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.02:18:05.22#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.02:18:05.22#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.02:18:05.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.02:18:05.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.02:18:05.22$vck44/va=1,8 2006.145.02:18:05.22#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.02:18:05.22#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.02:18:05.22#ibcon#ireg 11 cls_cnt 2 2006.145.02:18:05.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.02:18:05.22#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.02:18:05.22#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.02:18:05.25#ibcon#[25=AT01-08\r\n] 2006.145.02:18:05.28#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.02:18:05.28#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.02:18:05.28#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.02:18:05.28#ibcon#ireg 7 cls_cnt 0 2006.145.02:18:05.28#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.02:18:05.40#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.02:18:05.40#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.02:18:05.42#ibcon#[25=USB\r\n] 2006.145.02:18:05.46#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.02:18:05.46#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.02:18:05.46#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.02:18:05.46#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.02:18:05.46$vck44/valo=2,534.99 2006.145.02:18:05.46#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.02:18:05.46#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.02:18:05.46#ibcon#ireg 17 cls_cnt 0 2006.145.02:18:05.46#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.02:18:05.46#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.02:18:05.46#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.02:18:05.48#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.02:18:05.52#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.02:18:05.52#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.02:18:05.52#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.02:18:05.52#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.02:18:05.52$vck44/va=2,7 2006.145.02:18:05.52#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.02:18:05.52#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.02:18:05.52#ibcon#ireg 11 cls_cnt 2 2006.145.02:18:05.52#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.02:18:05.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.02:18:05.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.02:18:05.60#ibcon#[25=AT02-07\r\n] 2006.145.02:18:05.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.02:18:05.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.02:18:05.63#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.02:18:05.63#ibcon#ireg 7 cls_cnt 0 2006.145.02:18:05.63#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.02:18:05.75#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.02:18:05.75#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.02:18:05.77#ibcon#[25=USB\r\n] 2006.145.02:18:05.81#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.02:18:05.81#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.02:18:05.81#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.02:18:05.81#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.02:18:05.81$vck44/valo=3,564.99 2006.145.02:18:05.81#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.02:18:05.81#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.02:18:05.81#ibcon#ireg 17 cls_cnt 0 2006.145.02:18:05.81#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.02:18:05.81#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.02:18:05.81#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.02:18:05.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.02:18:05.87#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.02:18:05.87#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.02:18:05.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.02:18:05.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.02:18:05.87$vck44/va=3,8 2006.145.02:18:05.87#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.02:18:05.87#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.02:18:05.87#ibcon#ireg 11 cls_cnt 2 2006.145.02:18:05.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.02:18:05.93#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.02:18:05.93#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.02:18:05.95#ibcon#[25=AT03-08\r\n] 2006.145.02:18:05.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.02:18:05.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.02:18:05.98#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.02:18:05.98#ibcon#ireg 7 cls_cnt 0 2006.145.02:18:05.98#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.02:18:06.10#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.02:18:06.10#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.02:18:06.12#ibcon#[25=USB\r\n] 2006.145.02:18:06.15#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.02:18:06.15#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.02:18:06.15#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.02:18:06.15#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.02:18:06.15$vck44/valo=4,624.99 2006.145.02:18:06.15#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.02:18:06.15#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.02:18:06.15#ibcon#ireg 17 cls_cnt 0 2006.145.02:18:06.15#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.02:18:06.15#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.02:18:06.15#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.02:18:06.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.02:18:06.21#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.02:18:06.21#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.02:18:06.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.02:18:06.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.02:18:06.21$vck44/va=4,7 2006.145.02:18:06.21#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.02:18:06.21#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.02:18:06.21#ibcon#ireg 11 cls_cnt 2 2006.145.02:18:06.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.02:18:06.27#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.02:18:06.27#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.02:18:06.29#ibcon#[25=AT04-07\r\n] 2006.145.02:18:06.32#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.02:18:06.32#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.02:18:06.32#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.02:18:06.32#ibcon#ireg 7 cls_cnt 0 2006.145.02:18:06.32#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.02:18:06.44#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.02:18:06.44#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.02:18:06.46#ibcon#[25=USB\r\n] 2006.145.02:18:06.49#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.02:18:06.49#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.02:18:06.49#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.02:18:06.49#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.02:18:06.49$vck44/valo=5,734.99 2006.145.02:18:06.49#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.02:18:06.49#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.02:18:06.49#ibcon#ireg 17 cls_cnt 0 2006.145.02:18:06.49#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.02:18:06.49#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.02:18:06.49#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.02:18:06.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.02:18:06.55#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.02:18:06.55#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.02:18:06.55#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.02:18:06.55#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.02:18:06.55$vck44/va=5,4 2006.145.02:18:06.55#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.02:18:06.55#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.02:18:06.55#ibcon#ireg 11 cls_cnt 2 2006.145.02:18:06.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.02:18:06.61#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.02:18:06.61#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.02:18:06.63#ibcon#[25=AT05-04\r\n] 2006.145.02:18:06.66#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.02:18:06.66#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.02:18:06.66#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.02:18:06.66#ibcon#ireg 7 cls_cnt 0 2006.145.02:18:06.66#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.02:18:06.78#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.02:18:06.78#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.02:18:06.80#ibcon#[25=USB\r\n] 2006.145.02:18:06.83#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.02:18:06.83#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.02:18:06.83#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.02:18:06.83#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.02:18:06.83$vck44/valo=6,814.99 2006.145.02:18:06.83#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.02:18:06.83#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.02:18:06.83#ibcon#ireg 17 cls_cnt 0 2006.145.02:18:06.83#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.02:18:06.83#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.02:18:06.83#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.02:18:06.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.02:18:06.89#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.02:18:06.89#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.02:18:06.89#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.02:18:06.89#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.02:18:06.89$vck44/va=6,4 2006.145.02:18:06.89#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.02:18:06.89#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.02:18:06.89#ibcon#ireg 11 cls_cnt 2 2006.145.02:18:06.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.02:18:06.95#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.02:18:06.95#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.02:18:06.97#ibcon#[25=AT06-04\r\n] 2006.145.02:18:07.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.02:18:07.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.02:18:07.00#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.02:18:07.00#ibcon#ireg 7 cls_cnt 0 2006.145.02:18:07.00#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.02:18:07.12#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.02:18:07.12#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.02:18:07.14#ibcon#[25=USB\r\n] 2006.145.02:18:07.17#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.02:18:07.17#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.02:18:07.17#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.02:18:07.17#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.02:18:07.17$vck44/valo=7,864.99 2006.145.02:18:07.17#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.02:18:07.17#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.02:18:07.17#ibcon#ireg 17 cls_cnt 0 2006.145.02:18:07.17#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.02:18:07.17#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.02:18:07.17#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.02:18:07.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.02:18:07.23#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.02:18:07.23#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.02:18:07.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.02:18:07.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.02:18:07.23$vck44/va=7,4 2006.145.02:18:07.23#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.02:18:07.23#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.02:18:07.23#ibcon#ireg 11 cls_cnt 2 2006.145.02:18:07.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.02:18:07.29#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.02:18:07.29#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.02:18:07.31#ibcon#[25=AT07-04\r\n] 2006.145.02:18:07.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.02:18:07.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.02:18:07.34#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.02:18:07.34#ibcon#ireg 7 cls_cnt 0 2006.145.02:18:07.34#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.02:18:07.46#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.02:18:07.46#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.02:18:07.48#ibcon#[25=USB\r\n] 2006.145.02:18:07.51#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.02:18:07.51#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.02:18:07.51#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.02:18:07.51#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.02:18:07.51$vck44/valo=8,884.99 2006.145.02:18:07.51#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.02:18:07.51#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.02:18:07.51#ibcon#ireg 17 cls_cnt 0 2006.145.02:18:07.51#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.02:18:07.51#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.02:18:07.51#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.02:18:07.54#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.02:18:07.59#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.02:18:07.59#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.02:18:07.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.02:18:07.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.02:18:07.59$vck44/va=8,4 2006.145.02:18:07.59#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.02:18:07.59#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.02:18:07.59#ibcon#ireg 11 cls_cnt 2 2006.145.02:18:07.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.02:18:07.63#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.02:18:07.63#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.02:18:07.65#ibcon#[25=AT08-04\r\n] 2006.145.02:18:07.68#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.02:18:07.68#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.02:18:07.68#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.02:18:07.68#ibcon#ireg 7 cls_cnt 0 2006.145.02:18:07.68#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.02:18:07.80#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.02:18:07.80#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.02:18:07.82#ibcon#[25=USB\r\n] 2006.145.02:18:07.85#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.02:18:07.85#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.02:18:07.85#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.02:18:07.85#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.02:18:07.85$vck44/vblo=1,629.99 2006.145.02:18:07.85#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.02:18:07.85#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.02:18:07.85#ibcon#ireg 17 cls_cnt 0 2006.145.02:18:07.85#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.02:18:07.85#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.02:18:07.85#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.02:18:07.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.02:18:07.91#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.02:18:07.91#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.02:18:07.91#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.02:18:07.91#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.02:18:07.91$vck44/vb=1,3 2006.145.02:18:07.91#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.02:18:07.91#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.02:18:07.91#ibcon#ireg 11 cls_cnt 2 2006.145.02:18:07.91#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.02:18:07.91#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.02:18:07.91#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.02:18:07.93#ibcon#[27=AT01-03\r\n] 2006.145.02:18:07.96#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.02:18:07.96#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.02:18:07.96#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.02:18:07.96#ibcon#ireg 7 cls_cnt 0 2006.145.02:18:07.96#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.02:18:08.08#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.02:18:08.08#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.02:18:08.10#ibcon#[27=USB\r\n] 2006.145.02:18:08.13#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.02:18:08.13#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.02:18:08.13#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.02:18:08.13#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.02:18:08.13$vck44/vblo=2,634.99 2006.145.02:18:08.13#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.02:18:08.13#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.02:18:08.13#ibcon#ireg 17 cls_cnt 0 2006.145.02:18:08.13#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.02:18:08.13#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.02:18:08.13#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.02:18:08.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.02:18:08.19#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.02:18:08.19#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.02:18:08.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.02:18:08.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.02:18:08.19$vck44/vb=2,4 2006.145.02:18:08.19#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.02:18:08.19#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.02:18:08.19#ibcon#ireg 11 cls_cnt 2 2006.145.02:18:08.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.02:18:08.25#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.02:18:08.25#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.02:18:08.27#ibcon#[27=AT02-04\r\n] 2006.145.02:18:08.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.02:18:08.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.02:18:08.30#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.02:18:08.30#ibcon#ireg 7 cls_cnt 0 2006.145.02:18:08.30#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.02:18:08.42#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.02:18:08.42#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.02:18:08.44#ibcon#[27=USB\r\n] 2006.145.02:18:08.47#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.02:18:08.47#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.02:18:08.47#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.02:18:08.47#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.02:18:08.47$vck44/vblo=3,649.99 2006.145.02:18:08.47#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.02:18:08.47#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.02:18:08.47#ibcon#ireg 17 cls_cnt 0 2006.145.02:18:08.47#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.02:18:08.47#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.02:18:08.47#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.02:18:08.49#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.02:18:08.53#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.02:18:08.53#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.02:18:08.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.02:18:08.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.02:18:08.53$vck44/vb=3,4 2006.145.02:18:08.53#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.02:18:08.53#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.02:18:08.53#ibcon#ireg 11 cls_cnt 2 2006.145.02:18:08.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.02:18:08.59#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.02:18:08.59#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.02:18:08.61#ibcon#[27=AT03-04\r\n] 2006.145.02:18:08.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.02:18:08.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.02:18:08.64#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.02:18:08.64#ibcon#ireg 7 cls_cnt 0 2006.145.02:18:08.64#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.02:18:08.76#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.02:18:08.76#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.02:18:08.78#ibcon#[27=USB\r\n] 2006.145.02:18:08.81#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.02:18:08.81#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.02:18:08.81#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.02:18:08.81#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.02:18:08.81$vck44/vblo=4,679.99 2006.145.02:18:08.81#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.02:18:08.81#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.02:18:08.81#ibcon#ireg 17 cls_cnt 0 2006.145.02:18:08.81#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.02:18:08.81#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.02:18:08.81#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.02:18:08.83#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.02:18:08.86#abcon#<5=/05 3.8 7.1 19.59 651017.3\r\n> 2006.145.02:18:08.87#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.02:18:08.87#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.02:18:08.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.02:18:08.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.02:18:08.87$vck44/vb=4,4 2006.145.02:18:08.87#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.02:18:08.87#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.02:18:08.87#ibcon#ireg 11 cls_cnt 2 2006.145.02:18:08.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.02:18:08.88#abcon#{5=INTERFACE CLEAR} 2006.145.02:18:08.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.02:18:08.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.02:18:08.94#abcon#[5=S1D000X0/0*\r\n] 2006.145.02:18:08.95#ibcon#[27=AT04-04\r\n] 2006.145.02:18:08.98#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.02:18:08.98#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.02:18:08.98#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.02:18:08.98#ibcon#ireg 7 cls_cnt 0 2006.145.02:18:08.98#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.02:18:09.10#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.02:18:09.10#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.02:18:09.12#ibcon#[27=USB\r\n] 2006.145.02:18:09.15#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.02:18:09.15#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.02:18:09.15#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.02:18:09.15#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.02:18:09.15$vck44/vblo=5,709.99 2006.145.02:18:09.15#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.02:18:09.15#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.02:18:09.15#ibcon#ireg 17 cls_cnt 0 2006.145.02:18:09.15#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.02:18:09.15#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.02:18:09.15#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.02:18:09.17#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.02:18:09.21#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.02:18:09.21#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.02:18:09.21#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.02:18:09.21#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.02:18:09.21$vck44/vb=5,4 2006.145.02:18:09.21#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.02:18:09.21#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.02:18:09.21#ibcon#ireg 11 cls_cnt 2 2006.145.02:18:09.21#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.02:18:09.27#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.02:18:09.27#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.02:18:09.29#ibcon#[27=AT05-04\r\n] 2006.145.02:18:09.32#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.02:18:09.32#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.02:18:09.32#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.02:18:09.32#ibcon#ireg 7 cls_cnt 0 2006.145.02:18:09.32#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.02:18:09.44#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.02:18:09.44#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.02:18:09.46#ibcon#[27=USB\r\n] 2006.145.02:18:09.49#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.02:18:09.49#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.02:18:09.49#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.02:18:09.49#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.02:18:09.49$vck44/vblo=6,719.99 2006.145.02:18:09.49#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.02:18:09.49#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.02:18:09.49#ibcon#ireg 17 cls_cnt 0 2006.145.02:18:09.49#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.02:18:09.49#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.02:18:09.49#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.02:18:09.51#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.02:18:09.55#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.02:18:09.55#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.02:18:09.55#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.02:18:09.55#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.02:18:09.55$vck44/vb=6,4 2006.145.02:18:09.55#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.02:18:09.55#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.02:18:09.55#ibcon#ireg 11 cls_cnt 2 2006.145.02:18:09.55#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.02:18:09.61#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.02:18:09.61#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.02:18:09.63#ibcon#[27=AT06-04\r\n] 2006.145.02:18:09.66#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.02:18:09.66#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.02:18:09.66#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.02:18:09.66#ibcon#ireg 7 cls_cnt 0 2006.145.02:18:09.66#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.02:18:09.78#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.02:18:09.78#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.02:18:09.80#ibcon#[27=USB\r\n] 2006.145.02:18:09.83#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.02:18:09.83#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.02:18:09.83#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.02:18:09.83#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.02:18:09.83$vck44/vblo=7,734.99 2006.145.02:18:09.83#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.02:18:09.83#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.02:18:09.83#ibcon#ireg 17 cls_cnt 0 2006.145.02:18:09.83#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.02:18:09.83#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.02:18:09.83#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.02:18:09.85#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.02:18:09.90#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.02:18:09.90#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.02:18:09.90#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.02:18:09.90#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.02:18:09.90$vck44/vb=7,4 2006.145.02:18:09.90#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.02:18:09.90#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.02:18:09.90#ibcon#ireg 11 cls_cnt 2 2006.145.02:18:09.90#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.02:18:09.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.02:18:09.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.02:18:09.96#ibcon#[27=AT07-04\r\n] 2006.145.02:18:09.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.02:18:09.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.02:18:09.99#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.02:18:09.99#ibcon#ireg 7 cls_cnt 0 2006.145.02:18:09.99#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.02:18:10.11#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.02:18:10.11#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.02:18:10.13#ibcon#[27=USB\r\n] 2006.145.02:18:10.16#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.02:18:10.16#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.02:18:10.16#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.02:18:10.16#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.02:18:10.16$vck44/vblo=8,744.99 2006.145.02:18:10.16#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.02:18:10.16#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.02:18:10.16#ibcon#ireg 17 cls_cnt 0 2006.145.02:18:10.16#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.02:18:10.16#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.02:18:10.16#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.02:18:10.18#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.02:18:10.22#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.02:18:10.22#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.02:18:10.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.02:18:10.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.02:18:10.22$vck44/vb=8,4 2006.145.02:18:10.22#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.02:18:10.22#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.02:18:10.22#ibcon#ireg 11 cls_cnt 2 2006.145.02:18:10.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.02:18:10.28#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.02:18:10.28#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.02:18:10.30#ibcon#[27=AT08-04\r\n] 2006.145.02:18:10.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.02:18:10.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.02:18:10.33#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.02:18:10.33#ibcon#ireg 7 cls_cnt 0 2006.145.02:18:10.33#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.02:18:10.45#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.02:18:10.45#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.02:18:10.47#ibcon#[27=USB\r\n] 2006.145.02:18:10.50#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.02:18:10.50#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.02:18:10.50#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.02:18:10.50#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.02:18:10.50$vck44/vabw=wide 2006.145.02:18:10.50#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.02:18:10.50#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.02:18:10.50#ibcon#ireg 8 cls_cnt 0 2006.145.02:18:10.50#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.02:18:10.50#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.02:18:10.50#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.02:18:10.52#ibcon#[25=BW32\r\n] 2006.145.02:18:10.55#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.02:18:10.55#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.02:18:10.55#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.02:18:10.55#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.02:18:10.55$vck44/vbbw=wide 2006.145.02:18:10.55#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.02:18:10.55#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.02:18:10.55#ibcon#ireg 8 cls_cnt 0 2006.145.02:18:10.55#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.02:18:10.62#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.02:18:10.62#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.02:18:10.64#ibcon#[27=BW32\r\n] 2006.145.02:18:10.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.02:18:10.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.02:18:10.67#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.02:18:10.67#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.02:18:10.67$setupk4/ifdk4 2006.145.02:18:10.67$ifdk4/lo= 2006.145.02:18:10.67$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.02:18:10.67$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.02:18:10.67$ifdk4/patch= 2006.145.02:18:10.67$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.02:18:10.67$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.02:18:10.67$setupk4/!*+20s 2006.145.02:18:19.03#abcon#<5=/05 3.9 7.1 19.60 631017.2\r\n> 2006.145.02:18:19.05#abcon#{5=INTERFACE CLEAR} 2006.145.02:18:19.11#abcon#[5=S1D000X0/0*\r\n] 2006.145.02:18:23.14#trakl#Source acquired 2006.145.02:18:23.14#flagr#flagr/antenna,acquired 2006.145.02:18:25.14$setupk4/"tpicd 2006.145.02:18:25.14$setupk4/echo=off 2006.145.02:18:25.14$setupk4/xlog=off 2006.145.02:18:25.14:!2006.145.02:21:29 2006.145.02:21:29.00:preob 2006.145.02:21:30.14/onsource/TRACKING 2006.145.02:21:30.14:!2006.145.02:21:39 2006.145.02:21:39.00:"tape 2006.145.02:21:39.00:"st=record 2006.145.02:21:39.00:data_valid=on 2006.145.02:21:39.00:midob 2006.145.02:21:39.14/onsource/TRACKING 2006.145.02:21:39.14/wx/19.66,1017.2,66 2006.145.02:21:39.28/cable/+6.5483E-03 2006.145.02:21:40.37/va/01,08,usb,yes,28,30 2006.145.02:21:40.37/va/02,07,usb,yes,30,31 2006.145.02:21:40.37/va/03,08,usb,yes,27,28 2006.145.02:21:40.37/va/04,07,usb,yes,31,33 2006.145.02:21:40.37/va/05,04,usb,yes,27,28 2006.145.02:21:40.37/va/06,04,usb,yes,30,30 2006.145.02:21:40.37/va/07,04,usb,yes,31,32 2006.145.02:21:40.37/va/08,04,usb,yes,26,32 2006.145.02:21:40.60/valo/01,524.99,yes,locked 2006.145.02:21:40.60/valo/02,534.99,yes,locked 2006.145.02:21:40.60/valo/03,564.99,yes,locked 2006.145.02:21:40.60/valo/04,624.99,yes,locked 2006.145.02:21:40.60/valo/05,734.99,yes,locked 2006.145.02:21:40.60/valo/06,814.99,yes,locked 2006.145.02:21:40.60/valo/07,864.99,yes,locked 2006.145.02:21:40.60/valo/08,884.99,yes,locked 2006.145.02:21:41.69/vb/01,03,usb,yes,36,33 2006.145.02:21:41.69/vb/02,04,usb,yes,31,31 2006.145.02:21:41.69/vb/03,04,usb,yes,28,31 2006.145.02:21:41.69/vb/04,04,usb,yes,32,31 2006.145.02:21:41.69/vb/05,04,usb,yes,25,27 2006.145.02:21:41.69/vb/06,04,usb,yes,29,26 2006.145.02:21:41.69/vb/07,04,usb,yes,29,29 2006.145.02:21:41.69/vb/08,04,usb,yes,27,30 2006.145.02:21:41.92/vblo/01,629.99,yes,locked 2006.145.02:21:41.92/vblo/02,634.99,yes,locked 2006.145.02:21:41.92/vblo/03,649.99,yes,locked 2006.145.02:21:41.92/vblo/04,679.99,yes,locked 2006.145.02:21:41.92/vblo/05,709.99,yes,locked 2006.145.02:21:41.92/vblo/06,719.99,yes,locked 2006.145.02:21:41.92/vblo/07,734.99,yes,locked 2006.145.02:21:41.92/vblo/08,744.99,yes,locked 2006.145.02:21:42.07/vabw/8 2006.145.02:21:42.22/vbbw/8 2006.145.02:21:42.31/xfe/off,on,14.7 2006.145.02:21:42.69/ifatt/23,28,28,28 2006.145.02:21:43.07/fmout-gps/S +5.2E-08 2006.145.02:21:43.11:!2006.145.02:25:49 2006.145.02:25:49.00:data_valid=off 2006.145.02:25:49.00:"et 2006.145.02:25:49.00:!+3s 2006.145.02:25:52.02:"tape 2006.145.02:25:52.02:postob 2006.145.02:25:52.13/cable/+6.5475E-03 2006.145.02:25:52.13/wx/19.74,1017.1,68 2006.145.02:25:53.08/fmout-gps/S +5.4E-08 2006.145.02:25:53.08:scan_name=145-0235,jd0605,190 2006.145.02:25:53.08:source=1044+719,104827.62,714335.9,2000.0,cw 2006.145.02:25:54.14#flagr#flagr/antenna,new-source 2006.145.02:25:54.14:checkk5 2006.145.02:25:54.55/chk_autoobs//k5ts1/ autoobs is running! 2006.145.02:25:54.93/chk_autoobs//k5ts2/ autoobs is running! 2006.145.02:25:55.32/chk_autoobs//k5ts3/ autoobs is running! 2006.145.02:25:55.71/chk_autoobs//k5ts4/ autoobs is running! 2006.145.02:25:56.12/chk_obsdata//k5ts1/T1450221??a.dat file size is correct (nominal:1000MB, actual:996MB). 2006.145.02:25:56.68/chk_obsdata//k5ts2/T1450221??b.dat file size is correct (nominal:1000MB, actual:996MB). 2006.145.02:25:57.27/chk_obsdata//k5ts3/T1450221??c.dat file size is correct (nominal:1000MB, actual:996MB). 2006.145.02:25:57.64/chk_obsdata//k5ts4/T1450221??d.dat file size is correct (nominal:1000MB, actual:996MB). 2006.145.02:25:58.67/k5log//k5ts1_log_newline 2006.145.02:25:59.75/k5log//k5ts2_log_newline 2006.145.02:26:00.48/k5log//k5ts3_log_newline 2006.145.02:26:01.30/k5log//k5ts4_log_newline 2006.145.02:26:01.33/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.02:26:01.33:setupk4=1 2006.145.02:26:01.33$setupk4/echo=on 2006.145.02:26:01.33$setupk4/pcalon 2006.145.02:26:01.33$pcalon/"no phase cal control is implemented here 2006.145.02:26:01.33$setupk4/"tpicd=stop 2006.145.02:26:01.33$setupk4/"rec=synch_on 2006.145.02:26:01.33$setupk4/"rec_mode=128 2006.145.02:26:01.33$setupk4/!* 2006.145.02:26:01.33$setupk4/recpk4 2006.145.02:26:01.33$recpk4/recpatch= 2006.145.02:26:01.33$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.02:26:01.33$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.02:26:01.33$setupk4/vck44 2006.145.02:26:01.33$vck44/valo=1,524.99 2006.145.02:26:01.33#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.02:26:01.33#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.02:26:01.33#ibcon#ireg 17 cls_cnt 0 2006.145.02:26:01.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.02:26:01.33#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.02:26:01.33#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.02:26:01.37#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.02:26:01.42#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.02:26:01.42#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.02:26:01.42#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.02:26:01.42#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.02:26:01.42$vck44/va=1,8 2006.145.02:26:01.42#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.02:26:01.42#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.02:26:01.42#ibcon#ireg 11 cls_cnt 2 2006.145.02:26:01.42#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.02:26:01.42#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.02:26:01.42#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.02:26:01.44#ibcon#[25=AT01-08\r\n] 2006.145.02:26:01.48#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.02:26:01.48#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.02:26:01.48#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.02:26:01.48#ibcon#ireg 7 cls_cnt 0 2006.145.02:26:01.48#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.02:26:01.60#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.02:26:01.60#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.02:26:01.62#ibcon#[25=USB\r\n] 2006.145.02:26:01.66#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.02:26:01.66#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.02:26:01.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.02:26:01.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.02:26:01.66$vck44/valo=2,534.99 2006.145.02:26:01.66#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.02:26:01.66#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.02:26:01.66#ibcon#ireg 17 cls_cnt 0 2006.145.02:26:01.66#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.02:26:01.66#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.02:26:01.66#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.02:26:01.68#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.02:26:01.72#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.02:26:01.72#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.02:26:01.72#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.02:26:01.72#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.02:26:01.72$vck44/va=2,7 2006.145.02:26:01.72#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.02:26:01.72#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.02:26:01.72#ibcon#ireg 11 cls_cnt 2 2006.145.02:26:01.72#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.02:26:01.78#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.02:26:01.78#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.02:26:01.80#ibcon#[25=AT02-07\r\n] 2006.145.02:26:01.83#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.02:26:01.83#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.02:26:01.83#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.02:26:01.83#ibcon#ireg 7 cls_cnt 0 2006.145.02:26:01.83#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.02:26:01.95#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.02:26:01.95#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.02:26:01.97#ibcon#[25=USB\r\n] 2006.145.02:26:02.01#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.02:26:02.01#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.02:26:02.01#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.02:26:02.01#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.02:26:02.01$vck44/valo=3,564.99 2006.145.02:26:02.01#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.02:26:02.01#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.02:26:02.01#ibcon#ireg 17 cls_cnt 0 2006.145.02:26:02.01#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.02:26:02.01#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.02:26:02.01#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.02:26:02.03#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.02:26:02.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.02:26:02.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.02:26:02.07#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.02:26:02.07#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.02:26:02.07$vck44/va=3,8 2006.145.02:26:02.07#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.02:26:02.07#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.02:26:02.07#ibcon#ireg 11 cls_cnt 2 2006.145.02:26:02.07#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.02:26:02.13#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.02:26:02.13#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.02:26:02.15#ibcon#[25=AT03-08\r\n] 2006.145.02:26:02.18#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.02:26:02.18#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.02:26:02.18#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.02:26:02.18#ibcon#ireg 7 cls_cnt 0 2006.145.02:26:02.18#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.02:26:02.30#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.02:26:02.30#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.02:26:02.32#ibcon#[25=USB\r\n] 2006.145.02:26:02.35#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.02:26:02.35#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.02:26:02.35#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.02:26:02.35#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.02:26:02.35$vck44/valo=4,624.99 2006.145.02:26:02.35#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.02:26:02.35#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.02:26:02.35#ibcon#ireg 17 cls_cnt 0 2006.145.02:26:02.35#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.02:26:02.35#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.02:26:02.35#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.02:26:02.37#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.02:26:02.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.02:26:02.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.02:26:02.41#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.02:26:02.41#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.02:26:02.41$vck44/va=4,7 2006.145.02:26:02.41#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.02:26:02.41#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.02:26:02.41#ibcon#ireg 11 cls_cnt 2 2006.145.02:26:02.41#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.02:26:02.47#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.02:26:02.47#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.02:26:02.49#ibcon#[25=AT04-07\r\n] 2006.145.02:26:02.52#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.02:26:02.52#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.02:26:02.52#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.02:26:02.52#ibcon#ireg 7 cls_cnt 0 2006.145.02:26:02.52#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.02:26:02.64#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.02:26:02.64#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.02:26:02.66#ibcon#[25=USB\r\n] 2006.145.02:26:02.69#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.02:26:02.69#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.02:26:02.69#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.02:26:02.69#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.02:26:02.69$vck44/valo=5,734.99 2006.145.02:26:02.69#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.02:26:02.69#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.02:26:02.69#ibcon#ireg 17 cls_cnt 0 2006.145.02:26:02.69#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.02:26:02.69#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.02:26:02.69#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.02:26:02.71#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.02:26:02.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.02:26:02.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.02:26:02.75#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.02:26:02.75#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.02:26:02.75$vck44/va=5,4 2006.145.02:26:02.75#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.02:26:02.75#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.02:26:02.75#ibcon#ireg 11 cls_cnt 2 2006.145.02:26:02.75#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.02:26:02.81#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.02:26:02.81#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.02:26:02.83#ibcon#[25=AT05-04\r\n] 2006.145.02:26:02.86#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.02:26:02.86#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.02:26:02.86#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.02:26:02.86#ibcon#ireg 7 cls_cnt 0 2006.145.02:26:02.86#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.02:26:02.98#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.02:26:02.98#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.02:26:03.00#ibcon#[25=USB\r\n] 2006.145.02:26:03.03#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.02:26:03.03#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.02:26:03.03#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.02:26:03.03#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.02:26:03.03$vck44/valo=6,814.99 2006.145.02:26:03.03#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.02:26:03.03#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.02:26:03.03#ibcon#ireg 17 cls_cnt 0 2006.145.02:26:03.03#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.02:26:03.03#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.02:26:03.03#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.02:26:03.06#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.02:26:03.11#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.02:26:03.11#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.02:26:03.11#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.02:26:03.11#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.02:26:03.11$vck44/va=6,4 2006.145.02:26:03.11#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.02:26:03.11#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.02:26:03.11#ibcon#ireg 11 cls_cnt 2 2006.145.02:26:03.11#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.02:26:03.15#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.02:26:03.15#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.02:26:03.17#ibcon#[25=AT06-04\r\n] 2006.145.02:26:03.20#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.02:26:03.20#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.02:26:03.20#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.02:26:03.20#ibcon#ireg 7 cls_cnt 0 2006.145.02:26:03.20#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.02:26:03.32#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.02:26:03.32#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.02:26:03.34#ibcon#[25=USB\r\n] 2006.145.02:26:03.37#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.02:26:03.37#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.02:26:03.37#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.02:26:03.37#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.02:26:03.37$vck44/valo=7,864.99 2006.145.02:26:03.37#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.02:26:03.37#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.02:26:03.37#ibcon#ireg 17 cls_cnt 0 2006.145.02:26:03.37#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.02:26:03.37#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.02:26:03.37#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.02:26:03.39#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.02:26:03.43#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.02:26:03.43#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.02:26:03.43#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.02:26:03.43#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.02:26:03.43$vck44/va=7,4 2006.145.02:26:03.43#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.02:26:03.43#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.02:26:03.43#ibcon#ireg 11 cls_cnt 2 2006.145.02:26:03.43#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.02:26:03.49#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.02:26:03.49#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.02:26:03.51#ibcon#[25=AT07-04\r\n] 2006.145.02:26:03.54#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.02:26:03.54#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.02:26:03.54#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.02:26:03.54#ibcon#ireg 7 cls_cnt 0 2006.145.02:26:03.54#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.02:26:03.66#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.02:26:03.66#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.02:26:03.68#ibcon#[25=USB\r\n] 2006.145.02:26:03.71#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.02:26:03.71#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.02:26:03.71#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.02:26:03.71#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.02:26:03.71$vck44/valo=8,884.99 2006.145.02:26:03.71#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.02:26:03.71#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.02:26:03.71#ibcon#ireg 17 cls_cnt 0 2006.145.02:26:03.71#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.02:26:03.71#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.02:26:03.71#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.02:26:03.73#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.02:26:03.77#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.02:26:03.77#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.02:26:03.77#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.02:26:03.77#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.02:26:03.77$vck44/va=8,4 2006.145.02:26:03.77#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.02:26:03.77#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.02:26:03.77#ibcon#ireg 11 cls_cnt 2 2006.145.02:26:03.77#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.02:26:03.83#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.02:26:03.83#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.02:26:03.85#ibcon#[25=AT08-04\r\n] 2006.145.02:26:03.89#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.02:26:03.89#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.02:26:03.89#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.02:26:03.89#ibcon#ireg 7 cls_cnt 0 2006.145.02:26:03.89#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.02:26:04.01#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.02:26:04.01#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.02:26:04.03#ibcon#[25=USB\r\n] 2006.145.02:26:04.06#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.02:26:04.06#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.02:26:04.06#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.02:26:04.06#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.02:26:04.06$vck44/vblo=1,629.99 2006.145.02:26:04.06#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.02:26:04.06#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.02:26:04.06#ibcon#ireg 17 cls_cnt 0 2006.145.02:26:04.06#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.02:26:04.06#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.02:26:04.06#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.02:26:04.08#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.02:26:04.12#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.02:26:04.12#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.02:26:04.12#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.02:26:04.12#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.02:26:04.12$vck44/vb=1,3 2006.145.02:26:04.12#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.02:26:04.12#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.02:26:04.12#ibcon#ireg 11 cls_cnt 2 2006.145.02:26:04.12#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.02:26:04.12#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.02:26:04.12#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.02:26:04.14#ibcon#[27=AT01-03\r\n] 2006.145.02:26:04.17#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.02:26:04.17#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.02:26:04.17#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.02:26:04.17#ibcon#ireg 7 cls_cnt 0 2006.145.02:26:04.17#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.02:26:04.29#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.02:26:04.29#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.02:26:04.31#ibcon#[27=USB\r\n] 2006.145.02:26:04.34#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.02:26:04.34#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.02:26:04.34#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.02:26:04.34#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.02:26:04.34$vck44/vblo=2,634.99 2006.145.02:26:04.34#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.02:26:04.34#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.02:26:04.34#ibcon#ireg 17 cls_cnt 0 2006.145.02:26:04.34#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.02:26:04.34#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.02:26:04.34#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.02:26:04.36#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.02:26:04.40#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.02:26:04.40#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.02:26:04.40#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.02:26:04.40#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.02:26:04.40$vck44/vb=2,4 2006.145.02:26:04.40#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.02:26:04.40#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.02:26:04.40#ibcon#ireg 11 cls_cnt 2 2006.145.02:26:04.40#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.02:26:04.46#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.02:26:04.46#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.02:26:04.48#ibcon#[27=AT02-04\r\n] 2006.145.02:26:04.51#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.02:26:04.51#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.02:26:04.51#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.02:26:04.51#ibcon#ireg 7 cls_cnt 0 2006.145.02:26:04.51#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.02:26:04.63#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.02:26:04.63#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.02:26:04.65#ibcon#[27=USB\r\n] 2006.145.02:26:04.68#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.02:26:04.68#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.02:26:04.68#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.02:26:04.68#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.02:26:04.68$vck44/vblo=3,649.99 2006.145.02:26:04.68#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.02:26:04.68#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.02:26:04.68#ibcon#ireg 17 cls_cnt 0 2006.145.02:26:04.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.02:26:04.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.02:26:04.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.02:26:04.70#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.02:26:04.74#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.02:26:04.75#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.02:26:04.75#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.02:26:04.75#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.02:26:04.75$vck44/vb=3,4 2006.145.02:26:04.75#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.02:26:04.75#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.02:26:04.75#ibcon#ireg 11 cls_cnt 2 2006.145.02:26:04.75#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.02:26:04.80#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.02:26:04.80#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.02:26:04.82#ibcon#[27=AT03-04\r\n] 2006.145.02:26:04.85#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.02:26:04.85#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.02:26:04.85#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.02:26:04.85#ibcon#ireg 7 cls_cnt 0 2006.145.02:26:04.85#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.02:26:04.97#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.02:26:04.97#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.02:26:04.99#ibcon#[27=USB\r\n] 2006.145.02:26:05.02#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.02:26:05.02#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.02:26:05.02#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.02:26:05.02#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.02:26:05.02$vck44/vblo=4,679.99 2006.145.02:26:05.02#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.02:26:05.02#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.02:26:05.02#ibcon#ireg 17 cls_cnt 0 2006.145.02:26:05.02#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.02:26:05.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.02:26:05.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.02:26:05.04#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.02:26:05.08#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.02:26:05.08#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.02:26:05.08#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.02:26:05.08#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.02:26:05.08$vck44/vb=4,4 2006.145.02:26:05.08#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.02:26:05.08#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.02:26:05.08#ibcon#ireg 11 cls_cnt 2 2006.145.02:26:05.08#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.02:26:05.14#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.02:26:05.14#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.02:26:05.16#ibcon#[27=AT04-04\r\n] 2006.145.02:26:05.19#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.02:26:05.19#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.02:26:05.19#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.02:26:05.19#ibcon#ireg 7 cls_cnt 0 2006.145.02:26:05.19#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.02:26:05.31#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.02:26:05.31#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.02:26:05.33#ibcon#[27=USB\r\n] 2006.145.02:26:05.36#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.02:26:05.36#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.02:26:05.36#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.02:26:05.36#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.02:26:05.36$vck44/vblo=5,709.99 2006.145.02:26:05.36#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.02:26:05.36#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.02:26:05.36#ibcon#ireg 17 cls_cnt 0 2006.145.02:26:05.36#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.02:26:05.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.02:26:05.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.02:26:05.38#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.02:26:05.42#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.02:26:05.42#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.02:26:05.42#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.02:26:05.42#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.02:26:05.42$vck44/vb=5,4 2006.145.02:26:05.42#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.02:26:05.42#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.02:26:05.42#ibcon#ireg 11 cls_cnt 2 2006.145.02:26:05.42#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.02:26:05.48#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.02:26:05.48#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.02:26:05.50#ibcon#[27=AT05-04\r\n] 2006.145.02:26:05.53#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.02:26:05.53#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.02:26:05.53#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.02:26:05.53#ibcon#ireg 7 cls_cnt 0 2006.145.02:26:05.53#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.02:26:05.65#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.02:26:05.65#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.02:26:05.67#ibcon#[27=USB\r\n] 2006.145.02:26:05.70#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.02:26:05.70#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.02:26:05.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.02:26:05.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.02:26:05.70$vck44/vblo=6,719.99 2006.145.02:26:05.70#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.02:26:05.70#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.02:26:05.70#ibcon#ireg 17 cls_cnt 0 2006.145.02:26:05.70#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.02:26:05.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.02:26:05.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.02:26:05.72#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.02:26:05.76#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.02:26:05.76#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.02:26:05.76#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.02:26:05.76#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.02:26:05.76$vck44/vb=6,4 2006.145.02:26:05.76#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.02:26:05.76#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.02:26:05.76#ibcon#ireg 11 cls_cnt 2 2006.145.02:26:05.76#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.02:26:05.82#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.02:26:05.82#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.02:26:05.84#ibcon#[27=AT06-04\r\n] 2006.145.02:26:05.87#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.02:26:05.87#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.02:26:05.87#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.02:26:05.87#ibcon#ireg 7 cls_cnt 0 2006.145.02:26:05.87#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.02:26:05.99#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.02:26:05.99#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.02:26:06.01#ibcon#[27=USB\r\n] 2006.145.02:26:06.04#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.02:26:06.04#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.02:26:06.04#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.02:26:06.04#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.02:26:06.04$vck44/vblo=7,734.99 2006.145.02:26:06.04#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.02:26:06.04#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.02:26:06.04#ibcon#ireg 17 cls_cnt 0 2006.145.02:26:06.04#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.02:26:06.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.02:26:06.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.02:26:06.06#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.02:26:06.10#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.02:26:06.10#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.02:26:06.10#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.02:26:06.10#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.02:26:06.10$vck44/vb=7,4 2006.145.02:26:06.10#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.02:26:06.10#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.02:26:06.10#ibcon#ireg 11 cls_cnt 2 2006.145.02:26:06.10#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.02:26:06.16#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.02:26:06.16#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.02:26:06.18#ibcon#[27=AT07-04\r\n] 2006.145.02:26:06.21#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.02:26:06.21#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.02:26:06.21#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.02:26:06.21#ibcon#ireg 7 cls_cnt 0 2006.145.02:26:06.21#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.02:26:06.33#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.02:26:06.33#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.02:26:06.35#ibcon#[27=USB\r\n] 2006.145.02:26:06.38#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.02:26:06.38#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.02:26:06.38#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.02:26:06.38#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.02:26:06.38$vck44/vblo=8,744.99 2006.145.02:26:06.38#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.02:26:06.38#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.02:26:06.38#ibcon#ireg 17 cls_cnt 0 2006.145.02:26:06.38#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.02:26:06.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.02:26:06.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.02:26:06.40#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.02:26:06.44#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.02:26:06.44#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.02:26:06.44#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.02:26:06.44#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.02:26:06.44$vck44/vb=8,4 2006.145.02:26:06.44#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.02:26:06.44#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.02:26:06.44#ibcon#ireg 11 cls_cnt 2 2006.145.02:26:06.44#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.02:26:06.50#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.02:26:06.50#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.02:26:06.52#ibcon#[27=AT08-04\r\n] 2006.145.02:26:06.55#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.02:26:06.55#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.02:26:06.55#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.02:26:06.55#ibcon#ireg 7 cls_cnt 0 2006.145.02:26:06.55#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.02:26:06.67#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.02:26:06.67#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.02:26:06.69#ibcon#[27=USB\r\n] 2006.145.02:26:06.72#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.02:26:06.72#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.02:26:06.72#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.02:26:06.72#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.02:26:06.72$vck44/vabw=wide 2006.145.02:26:06.72#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.02:26:06.72#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.02:26:06.72#ibcon#ireg 8 cls_cnt 0 2006.145.02:26:06.72#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.02:26:06.72#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.02:26:06.72#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.02:26:06.74#ibcon#[25=BW32\r\n] 2006.145.02:26:06.77#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.02:26:06.77#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.02:26:06.77#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.02:26:06.77#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.02:26:06.77$vck44/vbbw=wide 2006.145.02:26:06.77#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.02:26:06.77#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.02:26:06.77#ibcon#ireg 8 cls_cnt 0 2006.145.02:26:06.77#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:26:06.84#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:26:06.84#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:26:06.86#ibcon#[27=BW32\r\n] 2006.145.02:26:06.89#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:26:06.89#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:26:06.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.02:26:06.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.02:26:06.89$setupk4/ifdk4 2006.145.02:26:06.89$ifdk4/lo= 2006.145.02:26:06.89$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.02:26:06.89$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.02:26:06.89$ifdk4/patch= 2006.145.02:26:06.89$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.02:26:06.89$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.02:26:06.89$setupk4/!*+20s 2006.145.02:26:07.25#abcon#<5=/05 3.6 8.6 19.75 651017.1\r\n> 2006.145.02:26:07.27#abcon#{5=INTERFACE CLEAR} 2006.145.02:26:07.33#abcon#[5=S1D000X0/0*\r\n] 2006.145.02:26:17.42#abcon#<5=/05 3.6 8.6 19.75 661017.1\r\n> 2006.145.02:26:17.44#abcon#{5=INTERFACE CLEAR} 2006.145.02:26:17.50#abcon#[5=S1D000X0/0*\r\n] 2006.145.02:26:21.34$setupk4/"tpicd 2006.145.02:26:21.34$setupk4/echo=off 2006.145.02:26:21.34$setupk4/xlog=off 2006.145.02:26:21.34:!2006.145.02:35:43 2006.145.02:26:57.14#trakl#Source acquired 2006.145.02:26:58.14#flagr#flagr/antenna,acquired 2006.145.02:35:43.00:preob 2006.145.02:35:44.14/onsource/TRACKING 2006.145.02:35:44.14:!2006.145.02:35:53 2006.145.02:35:53.00:"tape 2006.145.02:35:53.00:"st=record 2006.145.02:35:53.00:data_valid=on 2006.145.02:35:53.00:midob 2006.145.02:35:53.14/onsource/TRACKING 2006.145.02:35:53.14/wx/19.68,1017.1,67 2006.145.02:35:53.33/cable/+6.5497E-03 2006.145.02:35:54.42/va/01,08,usb,yes,29,31 2006.145.02:35:54.42/va/02,07,usb,yes,31,31 2006.145.02:35:54.42/va/03,08,usb,yes,28,29 2006.145.02:35:54.42/va/04,07,usb,yes,32,34 2006.145.02:35:54.42/va/05,04,usb,yes,28,28 2006.145.02:35:54.42/va/06,04,usb,yes,31,31 2006.145.02:35:54.42/va/07,04,usb,yes,31,33 2006.145.02:35:54.42/va/08,04,usb,yes,27,32 2006.145.02:35:54.65/valo/01,524.99,yes,locked 2006.145.02:35:54.65/valo/02,534.99,yes,locked 2006.145.02:35:54.65/valo/03,564.99,yes,locked 2006.145.02:35:54.65/valo/04,624.99,yes,locked 2006.145.02:35:54.65/valo/05,734.99,yes,locked 2006.145.02:35:54.65/valo/06,814.99,yes,locked 2006.145.02:35:54.65/valo/07,864.99,yes,locked 2006.145.02:35:54.65/valo/08,884.99,yes,locked 2006.145.02:35:55.74/vb/01,03,usb,yes,36,33 2006.145.02:35:55.74/vb/02,04,usb,yes,31,31 2006.145.02:35:55.74/vb/03,04,usb,yes,28,31 2006.145.02:35:55.74/vb/04,04,usb,yes,33,32 2006.145.02:35:55.74/vb/05,04,usb,yes,25,28 2006.145.02:35:55.74/vb/06,04,usb,yes,30,26 2006.145.02:35:55.74/vb/07,04,usb,yes,30,29 2006.145.02:35:55.74/vb/08,04,usb,yes,27,30 2006.145.02:35:55.97/vblo/01,629.99,yes,locked 2006.145.02:35:55.97/vblo/02,634.99,yes,locked 2006.145.02:35:55.97/vblo/03,649.99,yes,locked 2006.145.02:35:55.97/vblo/04,679.99,yes,locked 2006.145.02:35:55.97/vblo/05,709.99,yes,locked 2006.145.02:35:55.97/vblo/06,719.99,yes,locked 2006.145.02:35:55.97/vblo/07,734.99,yes,locked 2006.145.02:35:55.97/vblo/08,744.99,yes,locked 2006.145.02:35:56.12/vabw/8 2006.145.02:35:56.27/vbbw/8 2006.145.02:35:56.36/xfe/off,on,14.7 2006.145.02:35:56.74/ifatt/23,28,28,28 2006.145.02:35:57.07/fmout-gps/S +5.2E-08 2006.145.02:35:57.11:!2006.145.02:39:03 2006.145.02:39:03.01:data_valid=off 2006.145.02:39:03.02:"et 2006.145.02:39:03.02:!+3s 2006.145.02:39:06.03:"tape 2006.145.02:39:06.04:postob 2006.145.02:39:06.21/cable/+6.5472E-03 2006.145.02:39:06.22/wx/19.68,1017.0,63 2006.145.02:39:06.29/fmout-gps/S +5.1E-08 2006.145.02:39:06.30:scan_name=145-0242,jd0605,410 2006.145.02:39:06.30:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.145.02:39:08.14#flagr#flagr/antenna,new-source 2006.145.02:39:08.15:checkk5 2006.145.02:39:08.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.02:39:09.26/chk_autoobs//k5ts2/ autoobs is running! 2006.145.02:39:09.71/chk_autoobs//k5ts3/ autoobs is running! 2006.145.02:39:10.14/chk_autoobs//k5ts4/ autoobs is running! 2006.145.02:39:10.59/chk_obsdata//k5ts1/T1450235??a.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.02:39:11.03/chk_obsdata//k5ts2/T1450235??b.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.02:39:11.72/chk_obsdata//k5ts3/T1450235??c.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.02:39:12.17/chk_obsdata//k5ts4/T1450235??d.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.02:39:12.94/k5log//k5ts1_log_newline 2006.145.02:39:13.78/k5log//k5ts2_log_newline 2006.145.02:39:14.60/k5log//k5ts3_log_newline 2006.145.02:39:15.37/k5log//k5ts4_log_newline 2006.145.02:39:15.40/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.02:39:15.40:setupk4=1 2006.145.02:39:15.40$setupk4/echo=on 2006.145.02:39:15.40$setupk4/pcalon 2006.145.02:39:15.40$pcalon/"no phase cal control is implemented here 2006.145.02:39:15.40$setupk4/"tpicd=stop 2006.145.02:39:15.40$setupk4/"rec=synch_on 2006.145.02:39:15.40$setupk4/"rec_mode=128 2006.145.02:39:15.40$setupk4/!* 2006.145.02:39:15.40$setupk4/recpk4 2006.145.02:39:15.40$recpk4/recpatch= 2006.145.02:39:15.40$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.02:39:15.40$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.02:39:15.40$setupk4/vck44 2006.145.02:39:15.40$vck44/valo=1,524.99 2006.145.02:39:15.41#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.02:39:15.41#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.02:39:15.41#ibcon#ireg 17 cls_cnt 0 2006.145.02:39:15.41#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.02:39:15.41#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.02:39:15.41#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.02:39:15.44#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.02:39:15.48#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.02:39:15.48#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.02:39:15.48#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.02:39:15.48#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.02:39:15.48$vck44/va=1,8 2006.145.02:39:15.48#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.02:39:15.48#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.02:39:15.48#ibcon#ireg 11 cls_cnt 2 2006.145.02:39:15.48#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.02:39:15.48#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.02:39:15.48#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.02:39:15.51#ibcon#[25=AT01-08\r\n] 2006.145.02:39:15.54#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.02:39:15.54#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.02:39:15.54#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.02:39:15.54#ibcon#ireg 7 cls_cnt 0 2006.145.02:39:15.54#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.02:39:15.66#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.02:39:15.66#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.02:39:15.68#ibcon#[25=USB\r\n] 2006.145.02:39:15.71#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.02:39:15.71#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.02:39:15.71#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.02:39:15.71#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.02:39:15.71$vck44/valo=2,534.99 2006.145.02:39:15.71#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.02:39:15.71#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.02:39:15.71#ibcon#ireg 17 cls_cnt 0 2006.145.02:39:15.71#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.02:39:15.71#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.02:39:15.71#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.02:39:15.74#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.02:39:15.78#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.02:39:15.78#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.02:39:15.78#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.02:39:15.78#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.02:39:15.78$vck44/va=2,7 2006.145.02:39:15.78#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.02:39:15.78#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.02:39:15.78#ibcon#ireg 11 cls_cnt 2 2006.145.02:39:15.78#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.02:39:15.84#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.02:39:15.84#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.02:39:15.85#ibcon#[25=AT02-07\r\n] 2006.145.02:39:15.88#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.02:39:15.88#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.02:39:15.88#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.02:39:15.88#ibcon#ireg 7 cls_cnt 0 2006.145.02:39:15.88#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.02:39:16.00#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.02:39:16.00#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.02:39:16.02#ibcon#[25=USB\r\n] 2006.145.02:39:16.05#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.02:39:16.05#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.02:39:16.05#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.02:39:16.05#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.02:39:16.05$vck44/valo=3,564.99 2006.145.02:39:16.05#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.02:39:16.05#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.02:39:16.05#ibcon#ireg 17 cls_cnt 0 2006.145.02:39:16.05#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.02:39:16.05#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.02:39:16.05#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.02:39:16.08#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.02:39:16.12#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.02:39:16.12#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.02:39:16.12#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.02:39:16.12#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.02:39:16.12$vck44/va=3,8 2006.145.02:39:16.12#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.02:39:16.12#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.02:39:16.12#ibcon#ireg 11 cls_cnt 2 2006.145.02:39:16.12#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.02:39:16.17#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.02:39:16.17#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.02:39:16.19#ibcon#[25=AT03-08\r\n] 2006.145.02:39:16.22#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.02:39:16.22#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.02:39:16.22#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.02:39:16.22#ibcon#ireg 7 cls_cnt 0 2006.145.02:39:16.22#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.02:39:16.34#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.02:39:16.34#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.02:39:16.36#ibcon#[25=USB\r\n] 2006.145.02:39:16.39#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.02:39:16.39#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.02:39:16.39#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.02:39:16.39#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.02:39:16.39$vck44/valo=4,624.99 2006.145.02:39:16.39#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.02:39:16.39#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.02:39:16.39#ibcon#ireg 17 cls_cnt 0 2006.145.02:39:16.39#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.02:39:16.39#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.02:39:16.39#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.02:39:16.41#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.02:39:16.45#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.02:39:16.45#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.02:39:16.45#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.02:39:16.45#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.02:39:16.45$vck44/va=4,7 2006.145.02:39:16.45#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.02:39:16.45#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.02:39:16.45#ibcon#ireg 11 cls_cnt 2 2006.145.02:39:16.45#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.02:39:16.51#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.02:39:16.51#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.02:39:16.53#ibcon#[25=AT04-07\r\n] 2006.145.02:39:16.56#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.02:39:16.56#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.02:39:16.56#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.02:39:16.56#ibcon#ireg 7 cls_cnt 0 2006.145.02:39:16.56#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.02:39:16.68#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.02:39:16.68#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.02:39:16.70#ibcon#[25=USB\r\n] 2006.145.02:39:16.73#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.02:39:16.73#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.02:39:16.73#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.02:39:16.73#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.02:39:16.73$vck44/valo=5,734.99 2006.145.02:39:16.73#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.02:39:16.73#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.02:39:16.73#ibcon#ireg 17 cls_cnt 0 2006.145.02:39:16.73#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.02:39:16.73#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.02:39:16.73#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.02:39:16.75#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.02:39:16.79#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.02:39:16.79#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.02:39:16.79#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.02:39:16.79#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.02:39:16.79$vck44/va=5,4 2006.145.02:39:16.79#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.02:39:16.79#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.02:39:16.79#ibcon#ireg 11 cls_cnt 2 2006.145.02:39:16.79#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.02:39:16.85#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.02:39:16.85#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.02:39:16.87#ibcon#[25=AT05-04\r\n] 2006.145.02:39:16.90#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.02:39:16.90#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.02:39:16.90#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.02:39:16.90#ibcon#ireg 7 cls_cnt 0 2006.145.02:39:16.90#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.02:39:17.02#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.02:39:17.02#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.02:39:17.04#ibcon#[25=USB\r\n] 2006.145.02:39:17.07#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.02:39:17.07#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.02:39:17.07#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.02:39:17.07#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.02:39:17.07$vck44/valo=6,814.99 2006.145.02:39:17.07#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.02:39:17.07#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.02:39:17.07#ibcon#ireg 17 cls_cnt 0 2006.145.02:39:17.07#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.02:39:17.07#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.02:39:17.07#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.02:39:17.09#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.02:39:17.13#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.02:39:17.13#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.02:39:17.13#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.02:39:17.13#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.02:39:17.13$vck44/va=6,4 2006.145.02:39:17.13#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.02:39:17.13#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.02:39:17.13#ibcon#ireg 11 cls_cnt 2 2006.145.02:39:17.13#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.02:39:17.19#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.02:39:17.19#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.02:39:17.21#ibcon#[25=AT06-04\r\n] 2006.145.02:39:17.24#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.02:39:17.24#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.02:39:17.24#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.02:39:17.24#ibcon#ireg 7 cls_cnt 0 2006.145.02:39:17.24#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.02:39:17.36#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.02:39:17.36#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.02:39:17.38#ibcon#[25=USB\r\n] 2006.145.02:39:17.41#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.02:39:17.41#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.02:39:17.41#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.02:39:17.41#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.02:39:17.41$vck44/valo=7,864.99 2006.145.02:39:17.41#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.02:39:17.41#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.02:39:17.41#ibcon#ireg 17 cls_cnt 0 2006.145.02:39:17.41#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.02:39:17.41#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.02:39:17.41#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.02:39:17.43#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.02:39:17.47#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.02:39:17.47#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.02:39:17.47#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.02:39:17.47#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.02:39:17.47$vck44/va=7,4 2006.145.02:39:17.47#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.02:39:17.47#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.02:39:17.47#ibcon#ireg 11 cls_cnt 2 2006.145.02:39:17.47#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.02:39:17.53#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.02:39:17.53#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.02:39:17.55#ibcon#[25=AT07-04\r\n] 2006.145.02:39:17.58#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.02:39:17.58#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.02:39:17.58#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.02:39:17.58#ibcon#ireg 7 cls_cnt 0 2006.145.02:39:17.58#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.02:39:17.70#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.02:39:17.70#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.02:39:17.72#ibcon#[25=USB\r\n] 2006.145.02:39:17.75#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.02:39:17.75#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.02:39:17.75#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.02:39:17.75#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.02:39:17.75$vck44/valo=8,884.99 2006.145.02:39:17.75#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.02:39:17.75#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.02:39:17.75#ibcon#ireg 17 cls_cnt 0 2006.145.02:39:17.75#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.02:39:17.75#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.02:39:17.75#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.02:39:17.77#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.02:39:17.81#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.02:39:17.81#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.02:39:17.81#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.02:39:17.81#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.02:39:17.81$vck44/va=8,4 2006.145.02:39:17.81#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.02:39:17.81#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.02:39:17.81#ibcon#ireg 11 cls_cnt 2 2006.145.02:39:17.81#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.02:39:17.87#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.02:39:17.87#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.02:39:17.89#ibcon#[25=AT08-04\r\n] 2006.145.02:39:17.92#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.02:39:17.92#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.02:39:17.92#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.02:39:17.92#ibcon#ireg 7 cls_cnt 0 2006.145.02:39:17.92#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.02:39:18.04#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.02:39:18.04#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.02:39:18.06#ibcon#[25=USB\r\n] 2006.145.02:39:18.09#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.02:39:18.09#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.02:39:18.09#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.02:39:18.09#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.02:39:18.09$vck44/vblo=1,629.99 2006.145.02:39:18.09#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.02:39:18.09#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.02:39:18.09#ibcon#ireg 17 cls_cnt 0 2006.145.02:39:18.09#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.02:39:18.09#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.02:39:18.09#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.02:39:18.11#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.02:39:18.15#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.02:39:18.15#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.02:39:18.15#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.02:39:18.15#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.02:39:18.15$vck44/vb=1,3 2006.145.02:39:18.15#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.02:39:18.15#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.02:39:18.15#ibcon#ireg 11 cls_cnt 2 2006.145.02:39:18.15#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.02:39:18.15#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.02:39:18.15#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.02:39:18.17#ibcon#[27=AT01-03\r\n] 2006.145.02:39:18.20#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.02:39:18.20#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.02:39:18.20#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.02:39:18.20#ibcon#ireg 7 cls_cnt 0 2006.145.02:39:18.20#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.02:39:18.32#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.02:39:18.32#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.02:39:18.34#ibcon#[27=USB\r\n] 2006.145.02:39:18.37#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.02:39:18.37#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.02:39:18.37#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.02:39:18.37#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.02:39:18.37$vck44/vblo=2,634.99 2006.145.02:39:18.37#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.02:39:18.37#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.02:39:18.37#ibcon#ireg 17 cls_cnt 0 2006.145.02:39:18.37#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.02:39:18.37#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.02:39:18.37#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.02:39:18.39#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.02:39:18.43#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.02:39:18.43#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.02:39:18.43#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.02:39:18.43#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.02:39:18.43$vck44/vb=2,4 2006.145.02:39:18.43#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.02:39:18.43#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.02:39:18.43#ibcon#ireg 11 cls_cnt 2 2006.145.02:39:18.43#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.02:39:18.49#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.02:39:18.49#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.02:39:18.51#ibcon#[27=AT02-04\r\n] 2006.145.02:39:18.54#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.02:39:18.54#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.02:39:18.54#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.02:39:18.54#ibcon#ireg 7 cls_cnt 0 2006.145.02:39:18.54#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.02:39:18.66#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.02:39:18.66#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.02:39:18.68#ibcon#[27=USB\r\n] 2006.145.02:39:18.71#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.02:39:18.71#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.02:39:18.71#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.02:39:18.71#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.02:39:18.71$vck44/vblo=3,649.99 2006.145.02:39:18.71#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.02:39:18.71#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.02:39:18.71#ibcon#ireg 17 cls_cnt 0 2006.145.02:39:18.71#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.02:39:18.71#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.02:39:18.71#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.02:39:18.73#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.02:39:18.77#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.02:39:18.77#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.02:39:18.77#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.02:39:18.77#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.02:39:18.77$vck44/vb=3,4 2006.145.02:39:18.77#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.02:39:18.77#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.02:39:18.77#ibcon#ireg 11 cls_cnt 2 2006.145.02:39:18.77#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.02:39:18.83#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.02:39:18.83#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.02:39:18.85#ibcon#[27=AT03-04\r\n] 2006.145.02:39:18.88#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.02:39:18.88#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.02:39:18.88#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.02:39:18.88#ibcon#ireg 7 cls_cnt 0 2006.145.02:39:18.88#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.02:39:19.00#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.02:39:19.00#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.02:39:19.02#ibcon#[27=USB\r\n] 2006.145.02:39:19.05#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.02:39:19.05#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.02:39:19.05#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.02:39:19.05#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.02:39:19.05$vck44/vblo=4,679.99 2006.145.02:39:19.05#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.02:39:19.05#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.02:39:19.05#ibcon#ireg 17 cls_cnt 0 2006.145.02:39:19.05#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.02:39:19.05#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.02:39:19.05#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.02:39:19.07#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.02:39:19.11#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.02:39:19.11#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.02:39:19.11#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.02:39:19.11#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.02:39:19.11$vck44/vb=4,4 2006.145.02:39:19.11#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.02:39:19.11#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.02:39:19.11#ibcon#ireg 11 cls_cnt 2 2006.145.02:39:19.11#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.02:39:19.17#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.02:39:19.17#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.02:39:19.19#ibcon#[27=AT04-04\r\n] 2006.145.02:39:19.22#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.02:39:19.22#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.02:39:19.22#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.02:39:19.22#ibcon#ireg 7 cls_cnt 0 2006.145.02:39:19.22#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.02:39:19.34#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.02:39:19.34#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.02:39:19.36#ibcon#[27=USB\r\n] 2006.145.02:39:19.39#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.02:39:19.39#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.02:39:19.39#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.02:39:19.39#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.02:39:19.39$vck44/vblo=5,709.99 2006.145.02:39:19.39#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.02:39:19.39#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.02:39:19.39#ibcon#ireg 17 cls_cnt 0 2006.145.02:39:19.39#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.02:39:19.39#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.02:39:19.39#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.02:39:19.41#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.02:39:19.45#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.02:39:19.45#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.02:39:19.45#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.02:39:19.45#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.02:39:19.45$vck44/vb=5,4 2006.145.02:39:19.45#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.02:39:19.45#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.02:39:19.45#ibcon#ireg 11 cls_cnt 2 2006.145.02:39:19.45#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.02:39:19.51#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.02:39:19.51#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.02:39:19.53#ibcon#[27=AT05-04\r\n] 2006.145.02:39:19.56#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.02:39:19.56#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.02:39:19.56#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.02:39:19.56#ibcon#ireg 7 cls_cnt 0 2006.145.02:39:19.56#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.02:39:19.68#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.02:39:19.68#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.02:39:19.70#ibcon#[27=USB\r\n] 2006.145.02:39:19.73#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.02:39:19.73#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.02:39:19.73#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.02:39:19.73#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.02:39:19.73$vck44/vblo=6,719.99 2006.145.02:39:19.73#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.02:39:19.73#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.02:39:19.73#ibcon#ireg 17 cls_cnt 0 2006.145.02:39:19.73#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.02:39:19.73#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.02:39:19.73#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.02:39:19.75#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.02:39:19.79#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.02:39:19.79#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.02:39:19.79#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.02:39:19.79#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.02:39:19.79$vck44/vb=6,4 2006.145.02:39:19.79#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.02:39:19.79#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.02:39:19.79#ibcon#ireg 11 cls_cnt 2 2006.145.02:39:19.79#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.02:39:19.85#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.02:39:19.85#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.02:39:19.87#ibcon#[27=AT06-04\r\n] 2006.145.02:39:19.90#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.02:39:19.90#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.02:39:19.90#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.02:39:19.90#ibcon#ireg 7 cls_cnt 0 2006.145.02:39:19.90#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.02:39:20.02#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.02:39:20.02#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.02:39:20.04#ibcon#[27=USB\r\n] 2006.145.02:39:20.07#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.02:39:20.07#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.02:39:20.07#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.02:39:20.07#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.02:39:20.07$vck44/vblo=7,734.99 2006.145.02:39:20.07#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.02:39:20.07#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.02:39:20.07#ibcon#ireg 17 cls_cnt 0 2006.145.02:39:20.07#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.02:39:20.07#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.02:39:20.07#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.02:39:20.09#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.02:39:20.13#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.02:39:20.13#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.02:39:20.13#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.02:39:20.13#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.02:39:20.13$vck44/vb=7,4 2006.145.02:39:20.13#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.02:39:20.13#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.02:39:20.13#ibcon#ireg 11 cls_cnt 2 2006.145.02:39:20.13#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.02:39:20.19#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.02:39:20.19#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.02:39:20.21#ibcon#[27=AT07-04\r\n] 2006.145.02:39:20.24#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.02:39:20.24#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.02:39:20.24#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.02:39:20.24#ibcon#ireg 7 cls_cnt 0 2006.145.02:39:20.24#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.02:39:20.36#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.02:39:20.36#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.02:39:20.38#ibcon#[27=USB\r\n] 2006.145.02:39:20.41#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.02:39:20.41#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.02:39:20.41#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.02:39:20.41#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.02:39:20.41$vck44/vblo=8,744.99 2006.145.02:39:20.41#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.02:39:20.41#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.02:39:20.41#ibcon#ireg 17 cls_cnt 0 2006.145.02:39:20.41#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.02:39:20.41#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.02:39:20.41#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.02:39:20.43#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.02:39:20.47#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.02:39:20.47#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.02:39:20.47#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.02:39:20.47#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.02:39:20.47$vck44/vb=8,4 2006.145.02:39:20.47#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.02:39:20.47#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.02:39:20.47#ibcon#ireg 11 cls_cnt 2 2006.145.02:39:20.47#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.02:39:20.53#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.02:39:20.53#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.02:39:20.55#ibcon#[27=AT08-04\r\n] 2006.145.02:39:20.58#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.02:39:20.58#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.02:39:20.58#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.02:39:20.58#ibcon#ireg 7 cls_cnt 0 2006.145.02:39:20.58#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.02:39:20.70#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.02:39:20.70#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.02:39:20.72#ibcon#[27=USB\r\n] 2006.145.02:39:20.72#abcon#<5=/05 3.8 7.0 19.68 651017.0\r\n> 2006.145.02:39:20.74#abcon#{5=INTERFACE CLEAR} 2006.145.02:39:20.75#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.02:39:20.75#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.02:39:20.75#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.02:39:20.75#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.02:39:20.75$vck44/vabw=wide 2006.145.02:39:20.75#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.02:39:20.75#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.02:39:20.75#ibcon#ireg 8 cls_cnt 0 2006.145.02:39:20.75#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:39:20.75#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:39:20.75#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:39:20.77#ibcon#[25=BW32\r\n] 2006.145.02:39:20.80#abcon#[5=S1D000X0/0*\r\n] 2006.145.02:39:20.80#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:39:20.80#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:39:20.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.02:39:20.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.02:39:20.80$vck44/vbbw=wide 2006.145.02:39:20.80#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.02:39:20.80#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.02:39:20.80#ibcon#ireg 8 cls_cnt 0 2006.145.02:39:20.80#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.02:39:20.87#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.02:39:20.87#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.02:39:20.89#ibcon#[27=BW32\r\n] 2006.145.02:39:20.92#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.02:39:20.92#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.02:39:20.92#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.02:39:20.92#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.02:39:20.92$setupk4/ifdk4 2006.145.02:39:20.92$ifdk4/lo= 2006.145.02:39:20.92$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.02:39:20.92$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.02:39:20.92$ifdk4/patch= 2006.145.02:39:20.92$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.02:39:20.92$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.02:39:20.92$setupk4/!*+20s 2006.145.02:39:30.89#abcon#<5=/05 3.8 7.0 19.69 651017.0\r\n> 2006.145.02:39:30.91#abcon#{5=INTERFACE CLEAR} 2006.145.02:39:30.97#abcon#[5=S1D000X0/0*\r\n] 2006.145.02:39:35.41$setupk4/"tpicd 2006.145.02:39:35.41$setupk4/echo=off 2006.145.02:39:35.41$setupk4/xlog=off 2006.145.02:39:35.41:!2006.145.02:42:09 2006.145.02:39:36.13#trakl#Source acquired 2006.145.02:39:36.13#flagr#flagr/antenna,acquired 2006.145.02:42:09.00:preob 2006.145.02:42:10.14/onsource/TRACKING 2006.145.02:42:10.14:!2006.145.02:42:19 2006.145.02:42:19.00:"tape 2006.145.02:42:19.00:"st=record 2006.145.02:42:19.00:data_valid=on 2006.145.02:42:19.00:midob 2006.145.02:42:19.14/onsource/TRACKING 2006.145.02:42:19.14/wx/19.71,1016.9,71 2006.145.02:42:19.21/cable/+6.5487E-03 2006.145.02:42:20.30/va/01,08,usb,yes,28,30 2006.145.02:42:20.30/va/02,07,usb,yes,30,31 2006.145.02:42:20.30/va/03,08,usb,yes,27,29 2006.145.02:42:20.30/va/04,07,usb,yes,31,33 2006.145.02:42:20.30/va/05,04,usb,yes,27,28 2006.145.02:42:20.30/va/06,04,usb,yes,30,30 2006.145.02:42:20.30/va/07,04,usb,yes,31,32 2006.145.02:42:20.30/va/08,04,usb,yes,26,32 2006.145.02:42:20.53/valo/01,524.99,yes,locked 2006.145.02:42:20.53/valo/02,534.99,yes,locked 2006.145.02:42:20.53/valo/03,564.99,yes,locked 2006.145.02:42:20.53/valo/04,624.99,yes,locked 2006.145.02:42:20.53/valo/05,734.99,yes,locked 2006.145.02:42:20.53/valo/06,814.99,yes,locked 2006.145.02:42:20.53/valo/07,864.99,yes,locked 2006.145.02:42:20.53/valo/08,884.99,yes,locked 2006.145.02:42:21.62/vb/01,03,usb,yes,35,33 2006.145.02:42:21.62/vb/02,04,usb,yes,31,31 2006.145.02:42:21.62/vb/03,04,usb,yes,28,31 2006.145.02:42:21.62/vb/04,04,usb,yes,32,31 2006.145.02:42:21.62/vb/05,04,usb,yes,25,27 2006.145.02:42:21.62/vb/06,04,usb,yes,29,25 2006.145.02:42:21.62/vb/07,04,usb,yes,29,28 2006.145.02:42:21.62/vb/08,04,usb,yes,26,30 2006.145.02:42:21.85/vblo/01,629.99,yes,locked 2006.145.02:42:21.85/vblo/02,634.99,yes,locked 2006.145.02:42:21.85/vblo/03,649.99,yes,locked 2006.145.02:42:21.85/vblo/04,679.99,yes,locked 2006.145.02:42:21.85/vblo/05,709.99,yes,locked 2006.145.02:42:21.85/vblo/06,719.99,yes,locked 2006.145.02:42:21.85/vblo/07,734.99,yes,locked 2006.145.02:42:21.85/vblo/08,744.99,yes,locked 2006.145.02:42:22.00/vabw/8 2006.145.02:42:22.15/vbbw/8 2006.145.02:42:22.24/xfe/off,on,16.0 2006.145.02:42:22.61/ifatt/23,28,28,28 2006.145.02:42:23.07/fmout-gps/S +5.0E-08 2006.145.02:42:23.11:!2006.145.02:49:09 2006.145.02:49:09.00:data_valid=off 2006.145.02:49:09.00:"et 2006.145.02:49:09.01:!+3s 2006.145.02:49:12.02:"tape 2006.145.02:49:12.02:postob 2006.145.02:49:12.21/cable/+6.5508E-03 2006.145.02:49:12.21/wx/19.98,1016.8,63 2006.145.02:49:12.29/fmout-gps/S +4.9E-08 2006.145.02:49:12.30:scan_name=145-0254,jd0605,190 2006.145.02:49:12.30:source=0642+449,064632.03,445116.6,2000.0,cw 2006.145.02:49:13.13#flagr#flagr/antenna,new-source 2006.145.02:49:13.13:checkk5 2006.145.02:49:13.51/chk_autoobs//k5ts1/ autoobs is running! 2006.145.02:49:13.94/chk_autoobs//k5ts2/ autoobs is running! 2006.145.02:49:14.37/chk_autoobs//k5ts3/ autoobs is running! 2006.145.02:49:14.81/chk_autoobs//k5ts4/ autoobs is running! 2006.145.02:49:15.22/chk_obsdata//k5ts1/T1450242??a.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.145.02:49:15.64/chk_obsdata//k5ts2/T1450242??b.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.145.02:49:16.03/chk_obsdata//k5ts3/T1450242??c.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.145.02:49:16.47/chk_obsdata//k5ts4/T1450242??d.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.145.02:49:17.79/k5log//k5ts1_log_newline 2006.145.02:49:18.48/k5log//k5ts2_log_newline 2006.145.02:49:19.23/k5log//k5ts3_log_newline 2006.145.02:49:19.99/k5log//k5ts4_log_newline 2006.145.02:49:20.01/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.02:49:20.01:setupk4=1 2006.145.02:49:20.01$setupk4/echo=on 2006.145.02:49:20.01$setupk4/pcalon 2006.145.02:49:20.01$pcalon/"no phase cal control is implemented here 2006.145.02:49:20.01$setupk4/"tpicd=stop 2006.145.02:49:20.01$setupk4/"rec=synch_on 2006.145.02:49:20.01$setupk4/"rec_mode=128 2006.145.02:49:20.01$setupk4/!* 2006.145.02:49:20.01$setupk4/recpk4 2006.145.02:49:20.01$recpk4/recpatch= 2006.145.02:49:20.01$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.02:49:20.01$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.02:49:20.01$setupk4/vck44 2006.145.02:49:20.01$vck44/valo=1,524.99 2006.145.02:49:20.01#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.02:49:20.01#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.02:49:20.01#ibcon#ireg 17 cls_cnt 0 2006.145.02:49:20.01#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:49:20.01#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:49:20.01#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:49:20.03#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.02:49:20.08#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:49:20.08#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:49:20.08#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.02:49:20.08#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.02:49:20.08$vck44/va=1,8 2006.145.02:49:20.08#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.02:49:20.08#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.02:49:20.08#ibcon#ireg 11 cls_cnt 2 2006.145.02:49:20.08#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:49:20.08#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:49:20.08#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:49:20.10#ibcon#[25=AT01-08\r\n] 2006.145.02:49:20.13#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:49:20.13#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:49:20.13#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.02:49:20.13#ibcon#ireg 7 cls_cnt 0 2006.145.02:49:20.13#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:49:20.25#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:49:20.25#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:49:20.27#ibcon#[25=USB\r\n] 2006.145.02:49:20.30#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:49:20.30#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:49:20.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.02:49:20.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.02:49:20.30$vck44/valo=2,534.99 2006.145.02:49:20.30#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.02:49:20.30#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.02:49:20.30#ibcon#ireg 17 cls_cnt 0 2006.145.02:49:20.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:49:20.30#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:49:20.30#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:49:20.33#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.02:49:20.37#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:49:20.37#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:49:20.37#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.02:49:20.37#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.02:49:20.37$vck44/va=2,7 2006.145.02:49:20.37#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.02:49:20.37#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.02:49:20.37#ibcon#ireg 11 cls_cnt 2 2006.145.02:49:20.37#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:49:20.42#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:49:20.42#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:49:20.44#ibcon#[25=AT02-07\r\n] 2006.145.02:49:20.47#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:49:20.47#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:49:20.47#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.02:49:20.47#ibcon#ireg 7 cls_cnt 0 2006.145.02:49:20.47#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:49:20.59#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:49:20.59#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:49:20.61#ibcon#[25=USB\r\n] 2006.145.02:49:20.64#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:49:20.64#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:49:20.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.02:49:20.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.02:49:20.64$vck44/valo=3,564.99 2006.145.02:49:20.64#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.02:49:20.64#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.02:49:20.64#ibcon#ireg 17 cls_cnt 0 2006.145.02:49:20.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:49:20.64#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:49:20.64#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:49:20.67#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.02:49:20.71#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:49:20.71#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:49:20.71#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.02:49:20.71#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.02:49:20.71$vck44/va=3,8 2006.145.02:49:20.71#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.02:49:20.71#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.02:49:20.71#ibcon#ireg 11 cls_cnt 2 2006.145.02:49:20.71#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:49:20.76#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:49:20.76#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:49:20.78#ibcon#[25=AT03-08\r\n] 2006.145.02:49:20.81#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:49:20.81#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:49:20.81#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.02:49:20.81#ibcon#ireg 7 cls_cnt 0 2006.145.02:49:20.81#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:49:20.93#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:49:20.93#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:49:20.95#ibcon#[25=USB\r\n] 2006.145.02:49:20.98#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:49:20.98#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:49:20.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.02:49:20.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.02:49:20.98$vck44/valo=4,624.99 2006.145.02:49:20.98#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.02:49:20.98#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.02:49:20.98#ibcon#ireg 17 cls_cnt 0 2006.145.02:49:20.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.02:49:20.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.02:49:20.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.02:49:21.00#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.02:49:21.02#abcon#<5=/05 4.0 7.5 19.98 631016.8\r\n> 2006.145.02:49:21.04#abcon#{5=INTERFACE CLEAR} 2006.145.02:49:21.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.02:49:21.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.02:49:21.04#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.02:49:21.04#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.02:49:21.04$vck44/va=4,7 2006.145.02:49:21.04#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.02:49:21.04#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.02:49:21.04#ibcon#ireg 11 cls_cnt 2 2006.145.02:49:21.04#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.02:49:21.10#abcon#[5=S1D000X0/0*\r\n] 2006.145.02:49:21.10#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.02:49:21.10#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.02:49:21.12#ibcon#[25=AT04-07\r\n] 2006.145.02:49:21.15#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.02:49:21.15#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.02:49:21.15#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.02:49:21.15#ibcon#ireg 7 cls_cnt 0 2006.145.02:49:21.15#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.02:49:21.27#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.02:49:21.27#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.02:49:21.29#ibcon#[25=USB\r\n] 2006.145.02:49:21.32#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.02:49:21.32#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.02:49:21.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.02:49:21.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.02:49:21.32$vck44/valo=5,734.99 2006.145.02:49:21.32#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.02:49:21.32#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.02:49:21.32#ibcon#ireg 17 cls_cnt 0 2006.145.02:49:21.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:49:21.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:49:21.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:49:21.34#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.02:49:21.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:49:21.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:49:21.38#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.02:49:21.38#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.02:49:21.38$vck44/va=5,4 2006.145.02:49:21.38#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.02:49:21.38#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.02:49:21.38#ibcon#ireg 11 cls_cnt 2 2006.145.02:49:21.38#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:49:21.44#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:49:21.44#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:49:21.46#ibcon#[25=AT05-04\r\n] 2006.145.02:49:21.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:49:21.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:49:21.49#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.02:49:21.49#ibcon#ireg 7 cls_cnt 0 2006.145.02:49:21.49#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:49:21.61#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:49:21.61#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:49:21.63#ibcon#[25=USB\r\n] 2006.145.02:49:21.66#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:49:21.66#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:49:21.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.02:49:21.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.02:49:21.66$vck44/valo=6,814.99 2006.145.02:49:21.66#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.02:49:21.66#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.02:49:21.66#ibcon#ireg 17 cls_cnt 0 2006.145.02:49:21.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:49:21.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:49:21.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:49:21.68#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.02:49:21.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:49:21.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:49:21.72#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.02:49:21.72#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.02:49:21.72$vck44/va=6,4 2006.145.02:49:21.72#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.02:49:21.72#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.02:49:21.72#ibcon#ireg 11 cls_cnt 2 2006.145.02:49:21.72#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:49:21.78#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:49:21.78#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:49:21.80#ibcon#[25=AT06-04\r\n] 2006.145.02:49:21.83#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:49:21.83#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:49:21.83#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.02:49:21.83#ibcon#ireg 7 cls_cnt 0 2006.145.02:49:21.83#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:49:21.95#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:49:21.95#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:49:21.97#ibcon#[25=USB\r\n] 2006.145.02:49:22.00#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:49:22.00#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:49:22.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.02:49:22.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.02:49:22.00$vck44/valo=7,864.99 2006.145.02:49:22.00#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.02:49:22.00#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.02:49:22.00#ibcon#ireg 17 cls_cnt 0 2006.145.02:49:22.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:49:22.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:49:22.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:49:22.02#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.02:49:22.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:49:22.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:49:22.06#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.02:49:22.06#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.02:49:22.06$vck44/va=7,4 2006.145.02:49:22.06#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.02:49:22.06#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.02:49:22.06#ibcon#ireg 11 cls_cnt 2 2006.145.02:49:22.06#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:49:22.12#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:49:22.12#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:49:22.14#ibcon#[25=AT07-04\r\n] 2006.145.02:49:22.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:49:22.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:49:22.17#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.02:49:22.17#ibcon#ireg 7 cls_cnt 0 2006.145.02:49:22.17#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:49:22.29#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:49:22.29#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:49:22.31#ibcon#[25=USB\r\n] 2006.145.02:49:22.34#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:49:22.34#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:49:22.34#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.02:49:22.34#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.02:49:22.34$vck44/valo=8,884.99 2006.145.02:49:22.34#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.02:49:22.34#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.02:49:22.34#ibcon#ireg 17 cls_cnt 0 2006.145.02:49:22.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:49:22.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:49:22.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:49:22.36#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.02:49:22.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:49:22.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:49:22.40#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.02:49:22.40#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.02:49:22.40$vck44/va=8,4 2006.145.02:49:22.40#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.02:49:22.40#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.02:49:22.40#ibcon#ireg 11 cls_cnt 2 2006.145.02:49:22.40#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:49:22.46#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:49:22.46#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:49:22.48#ibcon#[25=AT08-04\r\n] 2006.145.02:49:22.51#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:49:22.51#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.02:49:22.51#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.02:49:22.51#ibcon#ireg 7 cls_cnt 0 2006.145.02:49:22.51#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:49:22.63#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:49:22.63#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:49:22.65#ibcon#[25=USB\r\n] 2006.145.02:49:22.68#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:49:22.68#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.02:49:22.68#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.02:49:22.68#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.02:49:22.68$vck44/vblo=1,629.99 2006.145.02:49:22.68#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.02:49:22.68#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.02:49:22.68#ibcon#ireg 17 cls_cnt 0 2006.145.02:49:22.68#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:49:22.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:49:22.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:49:22.70#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.02:49:22.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:49:22.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.02:49:22.74#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.02:49:22.74#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.02:49:22.74$vck44/vb=1,3 2006.145.02:49:22.74#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.02:49:22.74#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.02:49:22.74#ibcon#ireg 11 cls_cnt 2 2006.145.02:49:22.74#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:49:22.74#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:49:22.74#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:49:22.76#ibcon#[27=AT01-03\r\n] 2006.145.02:49:22.79#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:49:22.79#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.02:49:22.79#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.02:49:22.79#ibcon#ireg 7 cls_cnt 0 2006.145.02:49:22.79#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:49:22.91#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:49:22.91#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:49:22.93#ibcon#[27=USB\r\n] 2006.145.02:49:22.96#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:49:22.96#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.02:49:22.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.02:49:22.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.02:49:22.96$vck44/vblo=2,634.99 2006.145.02:49:22.96#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.02:49:22.96#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.02:49:22.96#ibcon#ireg 17 cls_cnt 0 2006.145.02:49:22.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:49:22.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:49:22.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:49:22.98#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.02:49:23.02#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:49:23.02#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.02:49:23.02#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.02:49:23.02#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.02:49:23.02$vck44/vb=2,4 2006.145.02:49:23.02#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.02:49:23.02#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.02:49:23.02#ibcon#ireg 11 cls_cnt 2 2006.145.02:49:23.02#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:49:23.08#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:49:23.08#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:49:23.10#ibcon#[27=AT02-04\r\n] 2006.145.02:49:23.13#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:49:23.13#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.02:49:23.13#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.02:49:23.13#ibcon#ireg 7 cls_cnt 0 2006.145.02:49:23.13#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:49:23.25#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:49:23.25#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:49:23.27#ibcon#[27=USB\r\n] 2006.145.02:49:23.30#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:49:23.30#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.02:49:23.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.02:49:23.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.02:49:23.30$vck44/vblo=3,649.99 2006.145.02:49:23.30#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.02:49:23.30#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.02:49:23.30#ibcon#ireg 17 cls_cnt 0 2006.145.02:49:23.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:49:23.30#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:49:23.30#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:49:23.32#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.02:49:23.36#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:49:23.36#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.02:49:23.36#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.02:49:23.36#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.02:49:23.36$vck44/vb=3,4 2006.145.02:49:23.36#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.02:49:23.36#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.02:49:23.36#ibcon#ireg 11 cls_cnt 2 2006.145.02:49:23.36#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:49:23.42#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:49:23.42#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:49:23.44#ibcon#[27=AT03-04\r\n] 2006.145.02:49:23.47#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:49:23.47#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.02:49:23.47#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.02:49:23.47#ibcon#ireg 7 cls_cnt 0 2006.145.02:49:23.47#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:49:23.59#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:49:23.59#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:49:23.61#ibcon#[27=USB\r\n] 2006.145.02:49:23.64#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:49:23.64#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.02:49:23.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.02:49:23.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.02:49:23.64$vck44/vblo=4,679.99 2006.145.02:49:23.64#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.02:49:23.64#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.02:49:23.64#ibcon#ireg 17 cls_cnt 0 2006.145.02:49:23.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:49:23.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:49:23.64#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:49:23.66#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.02:49:23.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:49:23.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.02:49:23.70#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.02:49:23.70#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.02:49:23.70$vck44/vb=4,4 2006.145.02:49:23.70#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.02:49:23.70#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.02:49:23.70#ibcon#ireg 11 cls_cnt 2 2006.145.02:49:23.70#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:49:23.76#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:49:23.76#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:49:23.78#ibcon#[27=AT04-04\r\n] 2006.145.02:49:23.81#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:49:23.81#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.02:49:23.81#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.02:49:23.81#ibcon#ireg 7 cls_cnt 0 2006.145.02:49:23.81#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:49:23.93#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:49:23.93#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:49:23.95#ibcon#[27=USB\r\n] 2006.145.02:49:23.98#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:49:23.98#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.02:49:23.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.02:49:23.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.02:49:23.98$vck44/vblo=5,709.99 2006.145.02:49:23.98#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.02:49:23.98#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.02:49:23.98#ibcon#ireg 17 cls_cnt 0 2006.145.02:49:23.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:49:23.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:49:23.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:49:24.00#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.02:49:24.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:49:24.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.02:49:24.04#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.02:49:24.04#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.02:49:24.04$vck44/vb=5,4 2006.145.02:49:24.04#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.02:49:24.04#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.02:49:24.04#ibcon#ireg 11 cls_cnt 2 2006.145.02:49:24.04#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.02:49:24.10#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.02:49:24.10#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.02:49:24.12#ibcon#[27=AT05-04\r\n] 2006.145.02:49:24.15#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.02:49:24.15#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.02:49:24.15#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.02:49:24.15#ibcon#ireg 7 cls_cnt 0 2006.145.02:49:24.15#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.02:49:24.27#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.02:49:24.27#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.02:49:24.29#ibcon#[27=USB\r\n] 2006.145.02:49:24.32#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.02:49:24.32#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.02:49:24.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.02:49:24.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.02:49:24.32$vck44/vblo=6,719.99 2006.145.02:49:24.32#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.02:49:24.32#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.02:49:24.32#ibcon#ireg 17 cls_cnt 0 2006.145.02:49:24.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:49:24.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:49:24.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:49:24.34#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.02:49:24.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:49:24.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.02:49:24.38#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.02:49:24.38#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.02:49:24.38$vck44/vb=6,4 2006.145.02:49:24.38#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.02:49:24.38#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.02:49:24.38#ibcon#ireg 11 cls_cnt 2 2006.145.02:49:24.38#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:49:24.44#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:49:24.44#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:49:24.46#ibcon#[27=AT06-04\r\n] 2006.145.02:49:24.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:49:24.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.02:49:24.49#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.02:49:24.49#ibcon#ireg 7 cls_cnt 0 2006.145.02:49:24.49#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:49:24.61#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:49:24.61#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:49:24.63#ibcon#[27=USB\r\n] 2006.145.02:49:24.66#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:49:24.66#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.02:49:24.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.02:49:24.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.02:49:24.66$vck44/vblo=7,734.99 2006.145.02:49:24.66#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.02:49:24.66#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.02:49:24.66#ibcon#ireg 17 cls_cnt 0 2006.145.02:49:24.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:49:24.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:49:24.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:49:24.68#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.02:49:24.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:49:24.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.02:49:24.72#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.02:49:24.72#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.02:49:24.72$vck44/vb=7,4 2006.145.02:49:24.72#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.02:49:24.72#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.02:49:24.72#ibcon#ireg 11 cls_cnt 2 2006.145.02:49:24.72#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:49:24.78#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:49:24.78#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:49:24.80#ibcon#[27=AT07-04\r\n] 2006.145.02:49:24.83#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:49:24.83#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.02:49:24.83#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.02:49:24.83#ibcon#ireg 7 cls_cnt 0 2006.145.02:49:24.83#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:49:24.95#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:49:24.95#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:49:24.97#ibcon#[27=USB\r\n] 2006.145.02:49:25.00#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:49:25.00#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.02:49:25.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.02:49:25.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.02:49:25.00$vck44/vblo=8,744.99 2006.145.02:49:25.00#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.02:49:25.00#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.02:49:25.00#ibcon#ireg 17 cls_cnt 0 2006.145.02:49:25.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:49:25.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:49:25.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:49:25.02#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.02:49:25.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:49:25.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.02:49:25.06#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.02:49:25.06#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.02:49:25.06$vck44/vb=8,4 2006.145.02:49:25.06#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.02:49:25.06#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.02:49:25.06#ibcon#ireg 11 cls_cnt 2 2006.145.02:49:25.06#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:49:25.12#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:49:25.12#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:49:25.14#ibcon#[27=AT08-04\r\n] 2006.145.02:49:25.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:49:25.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.02:49:25.17#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.02:49:25.17#ibcon#ireg 7 cls_cnt 0 2006.145.02:49:25.17#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:49:25.29#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:49:25.29#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:49:25.31#ibcon#[27=USB\r\n] 2006.145.02:49:25.34#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:49:25.34#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.02:49:25.34#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.02:49:25.34#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.02:49:25.34$vck44/vabw=wide 2006.145.02:49:25.34#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.02:49:25.34#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.02:49:25.34#ibcon#ireg 8 cls_cnt 0 2006.145.02:49:25.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:49:25.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:49:25.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:49:25.36#ibcon#[25=BW32\r\n] 2006.145.02:49:25.39#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:49:25.39#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.02:49:25.39#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.02:49:25.39#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.02:49:25.39$vck44/vbbw=wide 2006.145.02:49:25.39#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.02:49:25.39#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.02:49:25.39#ibcon#ireg 8 cls_cnt 0 2006.145.02:49:25.39#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.02:49:25.46#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.02:49:25.46#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.02:49:25.48#ibcon#[27=BW32\r\n] 2006.145.02:49:25.51#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.02:49:25.51#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.02:49:25.51#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.02:49:25.51#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.02:49:25.51$setupk4/ifdk4 2006.145.02:49:25.51$ifdk4/lo= 2006.145.02:49:25.51$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.02:49:25.51$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.02:49:25.51$ifdk4/patch= 2006.145.02:49:25.51$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.02:49:25.51$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.02:49:25.51$setupk4/!*+20s 2006.145.02:49:31.19#abcon#<5=/05 4.0 7.5 19.99 651016.8\r\n> 2006.145.02:49:31.21#abcon#{5=INTERFACE CLEAR} 2006.145.02:49:31.28#abcon#[5=S1D000X0/0*\r\n] 2006.145.02:49:40.02$setupk4/"tpicd 2006.145.02:49:40.02$setupk4/echo=off 2006.145.02:49:40.02$setupk4/xlog=off 2006.145.02:49:40.02:!2006.145.02:54:49 2006.145.02:49:54.13#trakl#Source acquired 2006.145.02:49:56.13#flagr#flagr/antenna,acquired 2006.145.02:54:49.00:preob 2006.145.02:54:49.14/onsource/TRACKING 2006.145.02:54:49.14:!2006.145.02:54:59 2006.145.02:54:59.00:"tape 2006.145.02:54:59.00:"st=record 2006.145.02:54:59.00:data_valid=on 2006.145.02:54:59.00:midob 2006.145.02:54:59.14/onsource/TRACKING 2006.145.02:54:59.14/wx/20.06,1016.8,64 2006.145.02:54:59.30/cable/+6.5464E-03 2006.145.02:55:00.39/va/01,08,usb,yes,28,30 2006.145.02:55:00.39/va/02,07,usb,yes,30,31 2006.145.02:55:00.39/va/03,08,usb,yes,27,28 2006.145.02:55:00.39/va/04,07,usb,yes,31,33 2006.145.02:55:00.39/va/05,04,usb,yes,27,27 2006.145.02:55:00.39/va/06,04,usb,yes,30,30 2006.145.02:55:00.39/va/07,04,usb,yes,31,32 2006.145.02:55:00.39/va/08,04,usb,yes,26,31 2006.145.02:55:00.62/valo/01,524.99,yes,locked 2006.145.02:55:00.62/valo/02,534.99,yes,locked 2006.145.02:55:00.62/valo/03,564.99,yes,locked 2006.145.02:55:00.62/valo/04,624.99,yes,locked 2006.145.02:55:00.62/valo/05,734.99,yes,locked 2006.145.02:55:00.62/valo/06,814.99,yes,locked 2006.145.02:55:00.62/valo/07,864.99,yes,locked 2006.145.02:55:00.62/valo/08,884.99,yes,locked 2006.145.02:55:01.71/vb/01,03,usb,yes,35,33 2006.145.02:55:01.71/vb/02,04,usb,yes,31,31 2006.145.02:55:01.71/vb/03,04,usb,yes,28,31 2006.145.02:55:01.71/vb/04,04,usb,yes,32,31 2006.145.02:55:01.71/vb/05,04,usb,yes,25,27 2006.145.02:55:01.71/vb/06,04,usb,yes,29,25 2006.145.02:55:01.71/vb/07,04,usb,yes,29,29 2006.145.02:55:01.71/vb/08,04,usb,yes,27,30 2006.145.02:55:01.94/vblo/01,629.99,yes,locked 2006.145.02:55:01.94/vblo/02,634.99,yes,locked 2006.145.02:55:01.94/vblo/03,649.99,yes,locked 2006.145.02:55:01.94/vblo/04,679.99,yes,locked 2006.145.02:55:01.94/vblo/05,709.99,yes,locked 2006.145.02:55:01.94/vblo/06,719.99,yes,locked 2006.145.02:55:01.94/vblo/07,734.99,yes,locked 2006.145.02:55:01.94/vblo/08,744.99,yes,locked 2006.145.02:55:02.09/vabw/8 2006.145.02:55:02.24/vbbw/8 2006.145.02:55:02.33/xfe/off,on,15.0 2006.145.02:55:02.72/ifatt/23,28,28,28 2006.145.02:55:03.07/fmout-gps/S +4.8E-08 2006.145.02:55:03.11:!2006.145.02:58:09 2006.145.02:58:09.01:data_valid=off 2006.145.02:58:09.01:"et 2006.145.02:58:09.01:!+3s 2006.145.02:58:12.03:"tape 2006.145.02:58:12.03:postob 2006.145.02:58:12.21/cable/+6.5478E-03 2006.145.02:58:12.21/wx/20.09,1016.8,63 2006.145.02:58:12.29/fmout-gps/S +4.7E-08 2006.145.02:58:12.29:scan_name=145-0300,jd0605,80 2006.145.02:58:12.30:source=0528+134,053056.42,133155.1,2000.0,cw 2006.145.02:58:14.13#flagr#flagr/antenna,new-source 2006.145.02:58:14.13:checkk5 2006.145.02:58:14.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.02:58:15.10/chk_autoobs//k5ts2/ autoobs is running! 2006.145.02:58:15.50/chk_autoobs//k5ts3/ autoobs is running! 2006.145.02:58:15.93/chk_autoobs//k5ts4/ autoobs is running! 2006.145.02:58:16.34/chk_obsdata//k5ts1/T1450254??a.dat file size is correct (nominal:760MB, actual:760MB). 2006.145.02:58:16.76/chk_obsdata//k5ts2/T1450254??b.dat file size is correct (nominal:760MB, actual:760MB). 2006.145.02:58:17.16/chk_obsdata//k5ts3/T1450254??c.dat file size is correct (nominal:760MB, actual:760MB). 2006.145.02:58:17.56/chk_obsdata//k5ts4/T1450254??d.dat file size is correct (nominal:760MB, actual:760MB). 2006.145.02:58:18.29/k5log//k5ts1_log_newline 2006.145.02:58:19.41/k5log//k5ts2_log_newline 2006.145.02:58:20.47/k5log//k5ts3_log_newline 2006.145.02:58:21.39/k5log//k5ts4_log_newline 2006.145.02:58:21.41/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.02:58:21.41:setupk4=1 2006.145.02:58:21.41$setupk4/echo=on 2006.145.02:58:21.41$setupk4/pcalon 2006.145.02:58:21.41$pcalon/"no phase cal control is implemented here 2006.145.02:58:21.41$setupk4/"tpicd=stop 2006.145.02:58:21.41$setupk4/"rec=synch_on 2006.145.02:58:21.42$setupk4/"rec_mode=128 2006.145.02:58:21.42$setupk4/!* 2006.145.02:58:21.42$setupk4/recpk4 2006.145.02:58:21.42$recpk4/recpatch= 2006.145.02:58:21.42$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.02:58:21.42$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.02:58:21.42$setupk4/vck44 2006.145.02:58:21.42$vck44/valo=1,524.99 2006.145.02:58:21.42#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.02:58:21.42#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.02:58:21.42#ibcon#ireg 17 cls_cnt 0 2006.145.02:58:21.42#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.02:58:21.42#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.02:58:21.42#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.02:58:21.46#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.02:58:21.51#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.02:58:21.51#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.02:58:21.51#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.02:58:21.51#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.02:58:21.51$vck44/va=1,8 2006.145.02:58:21.51#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.02:58:21.51#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.02:58:21.51#ibcon#ireg 11 cls_cnt 2 2006.145.02:58:21.51#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.02:58:21.51#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.02:58:21.51#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.02:58:21.54#ibcon#[25=AT01-08\r\n] 2006.145.02:58:21.57#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.02:58:21.57#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.02:58:21.57#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.02:58:21.57#ibcon#ireg 7 cls_cnt 0 2006.145.02:58:21.57#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.02:58:21.69#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.02:58:21.69#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.02:58:21.71#ibcon#[25=USB\r\n] 2006.145.02:58:21.75#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.02:58:21.75#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.02:58:21.75#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.02:58:21.75#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.02:58:21.75$vck44/valo=2,534.99 2006.145.02:58:21.75#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.02:58:21.75#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.02:58:21.75#ibcon#ireg 17 cls_cnt 0 2006.145.02:58:21.75#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.02:58:21.75#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.02:58:21.75#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.02:58:21.77#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.02:58:21.81#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.02:58:21.81#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.02:58:21.81#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.02:58:21.81#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.02:58:21.81$vck44/va=2,7 2006.145.02:58:21.81#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.02:58:21.81#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.02:58:21.81#ibcon#ireg 11 cls_cnt 2 2006.145.02:58:21.81#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.02:58:21.87#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.02:58:21.87#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.02:58:21.89#ibcon#[25=AT02-07\r\n] 2006.145.02:58:21.92#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.02:58:21.92#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.02:58:21.92#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.02:58:21.92#ibcon#ireg 7 cls_cnt 0 2006.145.02:58:21.92#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.02:58:22.04#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.02:58:22.04#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.02:58:22.06#ibcon#[25=USB\r\n] 2006.145.02:58:22.09#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.02:58:22.09#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.02:58:22.09#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.02:58:22.09#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.02:58:22.09$vck44/valo=3,564.99 2006.145.02:58:22.09#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.02:58:22.09#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.02:58:22.09#ibcon#ireg 17 cls_cnt 0 2006.145.02:58:22.09#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.02:58:22.09#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.02:58:22.09#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.02:58:22.11#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.02:58:22.16#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.02:58:22.16#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.02:58:22.16#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.02:58:22.16#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.02:58:22.16$vck44/va=3,8 2006.145.02:58:22.16#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.02:58:22.16#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.02:58:22.16#ibcon#ireg 11 cls_cnt 2 2006.145.02:58:22.16#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.02:58:22.20#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.02:58:22.20#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.02:58:22.22#ibcon#[25=AT03-08\r\n] 2006.145.02:58:22.25#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.02:58:22.25#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.02:58:22.25#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.02:58:22.25#ibcon#ireg 7 cls_cnt 0 2006.145.02:58:22.25#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.02:58:22.37#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.02:58:22.37#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.02:58:22.39#ibcon#[25=USB\r\n] 2006.145.02:58:22.42#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.02:58:22.42#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.02:58:22.42#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.02:58:22.42#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.02:58:22.42$vck44/valo=4,624.99 2006.145.02:58:22.42#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.02:58:22.42#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.02:58:22.42#ibcon#ireg 17 cls_cnt 0 2006.145.02:58:22.42#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.02:58:22.42#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.02:58:22.42#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.02:58:22.44#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.02:58:22.48#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.02:58:22.48#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.02:58:22.48#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.02:58:22.48#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.02:58:22.48$vck44/va=4,7 2006.145.02:58:22.48#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.02:58:22.48#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.02:58:22.48#ibcon#ireg 11 cls_cnt 2 2006.145.02:58:22.48#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.02:58:22.54#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.02:58:22.54#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.02:58:22.56#ibcon#[25=AT04-07\r\n] 2006.145.02:58:22.59#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.02:58:22.59#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.02:58:22.59#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.02:58:22.59#ibcon#ireg 7 cls_cnt 0 2006.145.02:58:22.59#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.02:58:22.71#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.02:58:22.71#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.02:58:22.73#ibcon#[25=USB\r\n] 2006.145.02:58:22.76#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.02:58:22.76#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.02:58:22.76#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.02:58:22.76#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.02:58:22.76$vck44/valo=5,734.99 2006.145.02:58:22.76#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.02:58:22.76#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.02:58:22.76#ibcon#ireg 17 cls_cnt 0 2006.145.02:58:22.76#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.02:58:22.76#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.02:58:22.76#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.02:58:22.78#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.02:58:22.82#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.02:58:22.82#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.02:58:22.82#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.02:58:22.82#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.02:58:22.82$vck44/va=5,4 2006.145.02:58:22.82#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.02:58:22.82#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.02:58:22.82#ibcon#ireg 11 cls_cnt 2 2006.145.02:58:22.82#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.02:58:22.88#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.02:58:22.88#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.02:58:22.90#ibcon#[25=AT05-04\r\n] 2006.145.02:58:22.93#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.02:58:22.93#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.02:58:22.93#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.02:58:22.93#ibcon#ireg 7 cls_cnt 0 2006.145.02:58:22.93#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.02:58:23.05#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.02:58:23.05#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.02:58:23.07#ibcon#[25=USB\r\n] 2006.145.02:58:23.10#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.02:58:23.10#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.02:58:23.10#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.02:58:23.10#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.02:58:23.10$vck44/valo=6,814.99 2006.145.02:58:23.10#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.02:58:23.10#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.02:58:23.10#ibcon#ireg 17 cls_cnt 0 2006.145.02:58:23.10#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.02:58:23.10#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.02:58:23.10#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.02:58:23.12#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.02:58:23.16#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.02:58:23.16#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.02:58:23.16#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.02:58:23.16#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.02:58:23.16$vck44/va=6,4 2006.145.02:58:23.16#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.02:58:23.16#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.02:58:23.16#ibcon#ireg 11 cls_cnt 2 2006.145.02:58:23.16#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.02:58:23.22#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.02:58:23.22#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.02:58:23.24#ibcon#[25=AT06-04\r\n] 2006.145.02:58:23.27#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.02:58:23.27#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.02:58:23.27#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.02:58:23.27#ibcon#ireg 7 cls_cnt 0 2006.145.02:58:23.27#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.02:58:23.39#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.02:58:23.39#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.02:58:23.41#ibcon#[25=USB\r\n] 2006.145.02:58:23.44#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.02:58:23.44#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.02:58:23.44#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.02:58:23.44#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.02:58:23.44$vck44/valo=7,864.99 2006.145.02:58:23.44#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.02:58:23.44#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.02:58:23.44#ibcon#ireg 17 cls_cnt 0 2006.145.02:58:23.44#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.02:58:23.44#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.02:58:23.44#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.02:58:23.46#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.02:58:23.50#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.02:58:23.50#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.02:58:23.50#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.02:58:23.50#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.02:58:23.50$vck44/va=7,4 2006.145.02:58:23.50#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.02:58:23.50#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.02:58:23.50#ibcon#ireg 11 cls_cnt 2 2006.145.02:58:23.50#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.02:58:23.56#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.02:58:23.56#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.02:58:23.58#ibcon#[25=AT07-04\r\n] 2006.145.02:58:23.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.02:58:23.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.02:58:23.61#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.02:58:23.61#ibcon#ireg 7 cls_cnt 0 2006.145.02:58:23.61#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.02:58:23.73#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.02:58:23.73#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.02:58:23.75#ibcon#[25=USB\r\n] 2006.145.02:58:23.78#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.02:58:23.78#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.02:58:23.78#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.02:58:23.78#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.02:58:23.78$vck44/valo=8,884.99 2006.145.02:58:23.78#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.02:58:23.78#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.02:58:23.78#ibcon#ireg 17 cls_cnt 0 2006.145.02:58:23.78#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.02:58:23.78#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.02:58:23.78#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.02:58:23.81#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.02:58:23.85#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.02:58:23.85#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.02:58:23.85#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.02:58:23.85#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.02:58:23.85$vck44/va=8,4 2006.145.02:58:23.85#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.02:58:23.85#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.02:58:23.85#ibcon#ireg 11 cls_cnt 2 2006.145.02:58:23.85#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.02:58:23.90#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.02:58:23.90#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.02:58:23.92#ibcon#[25=AT08-04\r\n] 2006.145.02:58:23.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.02:58:23.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.02:58:23.95#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.02:58:23.95#ibcon#ireg 7 cls_cnt 0 2006.145.02:58:23.95#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.02:58:24.07#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.02:58:24.07#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.02:58:24.09#ibcon#[25=USB\r\n] 2006.145.02:58:24.12#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.02:58:24.12#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.02:58:24.12#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.02:58:24.12#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.02:58:24.12$vck44/vblo=1,629.99 2006.145.02:58:24.12#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.02:58:24.12#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.02:58:24.12#ibcon#ireg 17 cls_cnt 0 2006.145.02:58:24.12#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.02:58:24.12#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.02:58:24.12#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.02:58:24.14#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.02:58:24.18#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.02:58:24.18#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.02:58:24.18#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.02:58:24.18#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.02:58:24.18$vck44/vb=1,3 2006.145.02:58:24.18#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.02:58:24.18#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.02:58:24.18#ibcon#ireg 11 cls_cnt 2 2006.145.02:58:24.18#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.02:58:24.18#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.02:58:24.18#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.02:58:24.20#ibcon#[27=AT01-03\r\n] 2006.145.02:58:24.23#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.02:58:24.23#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.02:58:24.23#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.02:58:24.23#ibcon#ireg 7 cls_cnt 0 2006.145.02:58:24.23#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.02:58:24.35#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.02:58:24.35#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.02:58:24.37#ibcon#[27=USB\r\n] 2006.145.02:58:24.40#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.02:58:24.40#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.02:58:24.40#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.02:58:24.40#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.02:58:24.40$vck44/vblo=2,634.99 2006.145.02:58:24.40#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.02:58:24.40#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.02:58:24.40#ibcon#ireg 17 cls_cnt 0 2006.145.02:58:24.40#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.02:58:24.40#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.02:58:24.40#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.02:58:24.42#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.02:58:24.46#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.02:58:24.46#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.02:58:24.46#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.02:58:24.46#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.02:58:24.46$vck44/vb=2,4 2006.145.02:58:24.46#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.02:58:24.46#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.02:58:24.46#ibcon#ireg 11 cls_cnt 2 2006.145.02:58:24.46#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.02:58:24.52#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.02:58:24.52#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.02:58:24.54#ibcon#[27=AT02-04\r\n] 2006.145.02:58:24.57#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.02:58:24.57#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.02:58:24.57#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.02:58:24.57#ibcon#ireg 7 cls_cnt 0 2006.145.02:58:24.57#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.02:58:24.69#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.02:58:24.69#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.02:58:24.71#ibcon#[27=USB\r\n] 2006.145.02:58:24.74#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.02:58:24.74#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.02:58:24.74#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.02:58:24.74#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.02:58:24.74$vck44/vblo=3,649.99 2006.145.02:58:24.74#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.02:58:24.74#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.02:58:24.74#ibcon#ireg 17 cls_cnt 0 2006.145.02:58:24.74#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.02:58:24.74#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.02:58:24.74#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.02:58:24.76#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.02:58:24.80#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.02:58:24.80#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.02:58:24.80#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.02:58:24.80#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.02:58:24.80$vck44/vb=3,4 2006.145.02:58:24.80#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.02:58:24.80#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.02:58:24.80#ibcon#ireg 11 cls_cnt 2 2006.145.02:58:24.80#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.02:58:24.86#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.02:58:24.86#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.02:58:24.88#ibcon#[27=AT03-04\r\n] 2006.145.02:58:24.91#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.02:58:24.91#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.02:58:24.91#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.02:58:24.91#ibcon#ireg 7 cls_cnt 0 2006.145.02:58:24.91#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.02:58:25.03#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.02:58:25.03#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.02:58:25.05#ibcon#[27=USB\r\n] 2006.145.02:58:25.08#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.02:58:25.08#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.02:58:25.08#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.02:58:25.08#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.02:58:25.08$vck44/vblo=4,679.99 2006.145.02:58:25.08#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.02:58:25.08#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.02:58:25.08#ibcon#ireg 17 cls_cnt 0 2006.145.02:58:25.08#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.02:58:25.08#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.02:58:25.08#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.02:58:25.10#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.02:58:25.14#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.02:58:25.14#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.02:58:25.14#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.02:58:25.14#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.02:58:25.14$vck44/vb=4,4 2006.145.02:58:25.14#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.02:58:25.14#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.02:58:25.14#ibcon#ireg 11 cls_cnt 2 2006.145.02:58:25.14#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.02:58:25.20#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.02:58:25.20#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.02:58:25.22#ibcon#[27=AT04-04\r\n] 2006.145.02:58:25.25#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.02:58:25.25#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.02:58:25.25#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.02:58:25.25#ibcon#ireg 7 cls_cnt 0 2006.145.02:58:25.25#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.02:58:25.37#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.02:58:25.37#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.02:58:25.39#ibcon#[27=USB\r\n] 2006.145.02:58:25.42#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.02:58:25.42#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.02:58:25.42#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.02:58:25.42#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.02:58:25.42$vck44/vblo=5,709.99 2006.145.02:58:25.42#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.02:58:25.42#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.02:58:25.42#ibcon#ireg 17 cls_cnt 0 2006.145.02:58:25.42#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.02:58:25.42#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.02:58:25.42#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.02:58:25.44#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.02:58:25.48#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.02:58:25.48#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.02:58:25.48#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.02:58:25.48#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.02:58:25.48$vck44/vb=5,4 2006.145.02:58:25.48#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.02:58:25.48#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.02:58:25.48#ibcon#ireg 11 cls_cnt 2 2006.145.02:58:25.48#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.02:58:25.54#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.02:58:25.54#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.02:58:25.56#ibcon#[27=AT05-04\r\n] 2006.145.02:58:25.59#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.02:58:25.59#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.02:58:25.59#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.02:58:25.59#ibcon#ireg 7 cls_cnt 0 2006.145.02:58:25.59#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.02:58:25.71#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.02:58:25.71#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.02:58:25.73#ibcon#[27=USB\r\n] 2006.145.02:58:25.76#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.02:58:25.76#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.02:58:25.76#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.02:58:25.76#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.02:58:25.76$vck44/vblo=6,719.99 2006.145.02:58:25.76#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.02:58:25.76#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.02:58:25.76#ibcon#ireg 17 cls_cnt 0 2006.145.02:58:25.76#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.02:58:25.76#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.02:58:25.76#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.02:58:25.78#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.02:58:25.82#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.02:58:25.82#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.02:58:25.82#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.02:58:25.82#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.02:58:25.82$vck44/vb=6,4 2006.145.02:58:25.82#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.02:58:25.82#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.02:58:25.82#ibcon#ireg 11 cls_cnt 2 2006.145.02:58:25.82#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.02:58:25.88#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.02:58:25.88#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.02:58:25.90#ibcon#[27=AT06-04\r\n] 2006.145.02:58:25.93#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.02:58:25.93#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.02:58:25.93#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.02:58:25.93#ibcon#ireg 7 cls_cnt 0 2006.145.02:58:25.93#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.02:58:26.05#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.02:58:26.05#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.02:58:26.07#ibcon#[27=USB\r\n] 2006.145.02:58:26.10#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.02:58:26.10#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.02:58:26.10#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.02:58:26.10#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.02:58:26.10$vck44/vblo=7,734.99 2006.145.02:58:26.10#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.02:58:26.10#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.02:58:26.10#ibcon#ireg 17 cls_cnt 0 2006.145.02:58:26.10#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.02:58:26.10#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.02:58:26.10#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.02:58:26.12#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.02:58:26.16#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.02:58:26.16#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.02:58:26.16#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.02:58:26.16#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.02:58:26.16$vck44/vb=7,4 2006.145.02:58:26.16#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.02:58:26.16#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.02:58:26.16#ibcon#ireg 11 cls_cnt 2 2006.145.02:58:26.16#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.02:58:26.22#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.02:58:26.22#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.02:58:26.24#ibcon#[27=AT07-04\r\n] 2006.145.02:58:26.27#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.02:58:26.27#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.02:58:26.27#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.02:58:26.27#ibcon#ireg 7 cls_cnt 0 2006.145.02:58:26.27#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.02:58:26.39#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.02:58:26.39#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.02:58:26.41#ibcon#[27=USB\r\n] 2006.145.02:58:26.44#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.02:58:26.44#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.02:58:26.44#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.02:58:26.44#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.02:58:26.44$vck44/vblo=8,744.99 2006.145.02:58:26.44#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.02:58:26.44#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.02:58:26.44#ibcon#ireg 17 cls_cnt 0 2006.145.02:58:26.44#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.02:58:26.44#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.02:58:26.44#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.02:58:26.46#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.02:58:26.50#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.02:58:26.50#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.02:58:26.50#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.02:58:26.50#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.02:58:26.50$vck44/vb=8,4 2006.145.02:58:26.50#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.02:58:26.50#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.02:58:26.50#ibcon#ireg 11 cls_cnt 2 2006.145.02:58:26.50#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.02:58:26.56#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.02:58:26.56#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.02:58:26.58#ibcon#[27=AT08-04\r\n] 2006.145.02:58:26.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.02:58:26.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.02:58:26.61#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.02:58:26.61#ibcon#ireg 7 cls_cnt 0 2006.145.02:58:26.61#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.02:58:26.73#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.02:58:26.73#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.02:58:26.75#ibcon#[27=USB\r\n] 2006.145.02:58:26.78#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.02:58:26.78#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.02:58:26.78#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.02:58:26.78#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.02:58:26.78$vck44/vabw=wide 2006.145.02:58:26.78#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.02:58:26.78#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.02:58:26.78#ibcon#ireg 8 cls_cnt 0 2006.145.02:58:26.78#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.02:58:26.78#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.02:58:26.78#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.02:58:26.80#ibcon#[25=BW32\r\n] 2006.145.02:58:26.83#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.02:58:26.83#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.02:58:26.83#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.02:58:26.83#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.02:58:26.83$vck44/vbbw=wide 2006.145.02:58:26.83#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.02:58:26.83#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.02:58:26.83#ibcon#ireg 8 cls_cnt 0 2006.145.02:58:26.83#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.02:58:26.90#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.02:58:26.90#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.02:58:26.92#ibcon#[27=BW32\r\n] 2006.145.02:58:26.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.02:58:26.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.02:58:26.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.02:58:26.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.02:58:26.95$setupk4/ifdk4 2006.145.02:58:26.95$ifdk4/lo= 2006.145.02:58:26.95$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.02:58:26.95$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.02:58:26.95$ifdk4/patch= 2006.145.02:58:26.95$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.02:58:26.95$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.02:58:26.95$setupk4/!*+20s 2006.145.02:58:30.35#abcon#<5=/05 3.8 7.6 20.09 671016.8\r\n> 2006.145.02:58:30.37#abcon#{5=INTERFACE CLEAR} 2006.145.02:58:30.43#abcon#[5=S1D000X0/0*\r\n] 2006.145.02:58:40.52#abcon#<5=/05 3.8 7.6 20.09 661016.8\r\n> 2006.145.02:58:40.54#abcon#{5=INTERFACE CLEAR} 2006.145.02:58:40.60#abcon#[5=S1D000X0/0*\r\n] 2006.145.02:58:41.43$setupk4/"tpicd 2006.145.02:58:41.43$setupk4/echo=off 2006.145.02:58:41.43$setupk4/xlog=off 2006.145.02:58:41.43:!2006.145.03:00:49 2006.145.02:58:49.14#trakl#Source acquired 2006.145.02:58:51.14#flagr#flagr/antenna,acquired 2006.145.03:00:49.00:preob 2006.145.03:00:49.14/onsource/TRACKING 2006.145.03:00:49.14:!2006.145.03:00:59 2006.145.03:00:59.00:"tape 2006.145.03:00:59.00:"st=record 2006.145.03:00:59.00:data_valid=on 2006.145.03:00:59.00:midob 2006.145.03:01:00.14/onsource/TRACKING 2006.145.03:01:00.14/wx/20.06,1016.8,60 2006.145.03:01:00.22/cable/+6.5469E-03 2006.145.03:01:01.31/va/01,08,usb,yes,28,30 2006.145.03:01:01.31/va/02,07,usb,yes,30,31 2006.145.03:01:01.31/va/03,08,usb,yes,27,28 2006.145.03:01:01.31/va/04,07,usb,yes,31,33 2006.145.03:01:01.31/va/05,04,usb,yes,27,27 2006.145.03:01:01.31/va/06,04,usb,yes,30,30 2006.145.03:01:01.31/va/07,04,usb,yes,31,32 2006.145.03:01:01.31/va/08,04,usb,yes,26,31 2006.145.03:01:01.54/valo/01,524.99,yes,locked 2006.145.03:01:01.54/valo/02,534.99,yes,locked 2006.145.03:01:01.54/valo/03,564.99,yes,locked 2006.145.03:01:01.54/valo/04,624.99,yes,locked 2006.145.03:01:01.54/valo/05,734.99,yes,locked 2006.145.03:01:01.54/valo/06,814.99,yes,locked 2006.145.03:01:01.54/valo/07,864.99,yes,locked 2006.145.03:01:01.54/valo/08,884.99,yes,locked 2006.145.03:01:02.63/vb/01,03,usb,yes,35,33 2006.145.03:01:02.63/vb/02,04,usb,yes,31,31 2006.145.03:01:02.63/vb/03,04,usb,yes,28,31 2006.145.03:01:02.63/vb/04,04,usb,yes,32,31 2006.145.03:01:02.63/vb/05,04,usb,yes,25,27 2006.145.03:01:02.63/vb/06,04,usb,yes,29,25 2006.145.03:01:02.63/vb/07,04,usb,yes,29,29 2006.145.03:01:02.63/vb/08,04,usb,yes,27,30 2006.145.03:01:02.86/vblo/01,629.99,yes,locked 2006.145.03:01:02.86/vblo/02,634.99,yes,locked 2006.145.03:01:02.86/vblo/03,649.99,yes,locked 2006.145.03:01:02.86/vblo/04,679.99,yes,locked 2006.145.03:01:02.86/vblo/05,709.99,yes,locked 2006.145.03:01:02.86/vblo/06,719.99,yes,locked 2006.145.03:01:02.86/vblo/07,734.99,yes,locked 2006.145.03:01:02.86/vblo/08,744.99,yes,locked 2006.145.03:01:03.01/vabw/8 2006.145.03:01:03.16/vbbw/8 2006.145.03:01:03.25/xfe/off,on,15.0 2006.145.03:01:03.62/ifatt/23,28,28,28 2006.145.03:01:04.08/fmout-gps/S +4.7E-08 2006.145.03:01:04.12:!2006.145.03:02:19 2006.145.03:02:19.00:data_valid=off 2006.145.03:02:19.00:"et 2006.145.03:02:19.00:!+3s 2006.145.03:02:22.01:"tape 2006.145.03:02:22.01:postob 2006.145.03:02:22.17/cable/+6.5467E-03 2006.145.03:02:22.17/wx/20.02,1016.9,59 2006.145.03:02:23.08/fmout-gps/S +4.8E-08 2006.145.03:02:23.08:scan_name=145-0305,jd0605,40 2006.145.03:02:23.08:source=3c454.3,225357.75,160853.6,2000.0,cw 2006.145.03:02:24.14:checkk5 2006.145.03:02:24.14#flagr#flagr/antenna,new-source 2006.145.03:02:24.50/chk_autoobs//k5ts1/ autoobs is running! 2006.145.03:02:25.11/chk_autoobs//k5ts2/ autoobs is running! 2006.145.03:02:25.54/chk_autoobs//k5ts3/ autoobs is running! 2006.145.03:02:25.96/chk_autoobs//k5ts4/ autoobs is running! 2006.145.03:02:26.75/chk_obsdata//k5ts1/T1450300??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.03:02:27.15/chk_obsdata//k5ts2/T1450300??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.03:02:27.61/chk_obsdata//k5ts3/T1450300??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.03:02:28.02/chk_obsdata//k5ts4/T1450300??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.03:02:29.12/k5log//k5ts1_log_newline 2006.145.03:02:29.96/k5log//k5ts2_log_newline 2006.145.03:02:30.78/k5log//k5ts3_log_newline 2006.145.03:02:31.69/k5log//k5ts4_log_newline 2006.145.03:02:31.72/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.03:02:31.72:setupk4=1 2006.145.03:02:31.72$setupk4/echo=on 2006.145.03:02:31.72$setupk4/pcalon 2006.145.03:02:31.72$pcalon/"no phase cal control is implemented here 2006.145.03:02:31.72$setupk4/"tpicd=stop 2006.145.03:02:31.72$setupk4/"rec=synch_on 2006.145.03:02:31.72$setupk4/"rec_mode=128 2006.145.03:02:31.72$setupk4/!* 2006.145.03:02:31.72$setupk4/recpk4 2006.145.03:02:31.72$recpk4/recpatch= 2006.145.03:02:31.72$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.03:02:31.73$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.03:02:31.73$setupk4/vck44 2006.145.03:02:31.73$vck44/valo=1,524.99 2006.145.03:02:31.73#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.03:02:31.73#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.03:02:31.73#ibcon#ireg 17 cls_cnt 0 2006.145.03:02:31.73#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:02:31.73#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:02:31.73#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:02:31.76#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.03:02:31.81#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:02:31.81#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:02:31.81#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.03:02:31.81#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.03:02:31.82$vck44/va=1,8 2006.145.03:02:31.82#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.03:02:31.82#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.03:02:31.82#ibcon#ireg 11 cls_cnt 2 2006.145.03:02:31.82#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.03:02:31.82#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.03:02:31.82#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.03:02:31.84#ibcon#[25=AT01-08\r\n] 2006.145.03:02:31.88#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.03:02:31.88#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.03:02:31.88#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.03:02:31.88#ibcon#ireg 7 cls_cnt 0 2006.145.03:02:31.88#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.03:02:32.00#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.03:02:32.00#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.03:02:32.02#ibcon#[25=USB\r\n] 2006.145.03:02:32.06#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.03:02:32.06#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.03:02:32.06#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.03:02:32.06#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.03:02:32.07$vck44/valo=2,534.99 2006.145.03:02:32.07#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.03:02:32.07#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.03:02:32.07#ibcon#ireg 17 cls_cnt 0 2006.145.03:02:32.07#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:02:32.07#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:02:32.07#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:02:32.09#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.03:02:32.13#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:02:32.13#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:02:32.13#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.03:02:32.13#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.03:02:32.13$vck44/va=2,7 2006.145.03:02:32.13#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.03:02:32.13#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.03:02:32.13#ibcon#ireg 11 cls_cnt 2 2006.145.03:02:32.13#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.03:02:32.18#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.03:02:32.18#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.03:02:32.20#ibcon#[25=AT02-07\r\n] 2006.145.03:02:32.23#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.03:02:32.23#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.03:02:32.23#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.03:02:32.23#ibcon#ireg 7 cls_cnt 0 2006.145.03:02:32.23#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.03:02:32.35#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.03:02:32.35#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.03:02:32.37#ibcon#[25=USB\r\n] 2006.145.03:02:32.40#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.03:02:32.40#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.03:02:32.40#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.03:02:32.40#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.03:02:32.40$vck44/valo=3,564.99 2006.145.03:02:32.40#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.03:02:32.40#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.03:02:32.40#ibcon#ireg 17 cls_cnt 0 2006.145.03:02:32.40#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:02:32.40#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:02:32.40#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:02:32.43#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.03:02:32.47#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:02:32.47#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:02:32.47#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.03:02:32.47#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.03:02:32.47$vck44/va=3,8 2006.145.03:02:32.47#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.03:02:32.47#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.03:02:32.47#ibcon#ireg 11 cls_cnt 2 2006.145.03:02:32.47#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:02:32.53#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:02:32.53#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:02:32.55#ibcon#[25=AT03-08\r\n] 2006.145.03:02:32.58#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:02:32.58#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:02:32.58#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.03:02:32.58#ibcon#ireg 7 cls_cnt 0 2006.145.03:02:32.58#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:02:32.70#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:02:32.70#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:02:32.72#ibcon#[25=USB\r\n] 2006.145.03:02:32.75#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:02:32.75#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:02:32.75#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.03:02:32.75#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.03:02:32.75$vck44/valo=4,624.99 2006.145.03:02:32.75#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.03:02:32.75#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.03:02:32.75#ibcon#ireg 17 cls_cnt 0 2006.145.03:02:32.75#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:02:32.75#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:02:32.75#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:02:32.77#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.03:02:32.81#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:02:32.81#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:02:32.81#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.03:02:32.81#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.03:02:32.81$vck44/va=4,7 2006.145.03:02:32.81#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.03:02:32.81#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.03:02:32.81#ibcon#ireg 11 cls_cnt 2 2006.145.03:02:32.81#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:02:32.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:02:32.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:02:32.89#ibcon#[25=AT04-07\r\n] 2006.145.03:02:32.92#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:02:32.92#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:02:32.92#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.03:02:32.92#ibcon#ireg 7 cls_cnt 0 2006.145.03:02:32.92#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:02:33.04#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:02:33.04#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:02:33.06#ibcon#[25=USB\r\n] 2006.145.03:02:33.09#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:02:33.09#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:02:33.09#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.03:02:33.09#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.03:02:33.09$vck44/valo=5,734.99 2006.145.03:02:33.09#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.03:02:33.09#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.03:02:33.09#ibcon#ireg 17 cls_cnt 0 2006.145.03:02:33.09#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:02:33.09#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:02:33.09#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:02:33.11#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.03:02:33.15#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:02:33.15#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:02:33.15#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.03:02:33.15#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.03:02:33.15$vck44/va=5,4 2006.145.03:02:33.15#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.03:02:33.15#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.03:02:33.15#ibcon#ireg 11 cls_cnt 2 2006.145.03:02:33.15#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.03:02:33.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.03:02:33.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.03:02:33.23#ibcon#[25=AT05-04\r\n] 2006.145.03:02:33.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.03:02:33.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.03:02:33.26#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.03:02:33.26#ibcon#ireg 7 cls_cnt 0 2006.145.03:02:33.26#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.03:02:33.38#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.03:02:33.38#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.03:02:33.40#ibcon#[25=USB\r\n] 2006.145.03:02:33.44#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.03:02:33.44#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.03:02:33.44#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.03:02:33.44#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.03:02:33.44$vck44/valo=6,814.99 2006.145.03:02:33.44#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.03:02:33.44#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.03:02:33.44#ibcon#ireg 17 cls_cnt 0 2006.145.03:02:33.44#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:02:33.44#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:02:33.44#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:02:33.46#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.03:02:33.50#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:02:33.50#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:02:33.50#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.03:02:33.50#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.03:02:33.50$vck44/va=6,4 2006.145.03:02:33.50#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.03:02:33.50#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.03:02:33.50#ibcon#ireg 11 cls_cnt 2 2006.145.03:02:33.50#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:02:33.56#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:02:33.56#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:02:33.58#ibcon#[25=AT06-04\r\n] 2006.145.03:02:33.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:02:33.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:02:33.61#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.03:02:33.61#ibcon#ireg 7 cls_cnt 0 2006.145.03:02:33.61#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:02:33.73#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:02:33.73#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:02:33.75#ibcon#[25=USB\r\n] 2006.145.03:02:33.78#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:02:33.78#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:02:33.78#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.03:02:33.78#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.03:02:33.78$vck44/valo=7,864.99 2006.145.03:02:33.78#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.03:02:33.78#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.03:02:33.78#ibcon#ireg 17 cls_cnt 0 2006.145.03:02:33.78#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:02:33.78#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:02:33.78#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:02:33.80#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.03:02:33.84#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:02:33.84#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:02:33.84#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.03:02:33.84#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.03:02:33.84$vck44/va=7,4 2006.145.03:02:33.84#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.03:02:33.84#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.03:02:33.84#ibcon#ireg 11 cls_cnt 2 2006.145.03:02:33.84#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:02:33.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:02:33.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:02:33.92#ibcon#[25=AT07-04\r\n] 2006.145.03:02:33.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:02:33.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:02:33.95#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.03:02:33.95#ibcon#ireg 7 cls_cnt 0 2006.145.03:02:33.95#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:02:34.07#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:02:34.07#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:02:34.09#ibcon#[25=USB\r\n] 2006.145.03:02:34.12#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:02:34.12#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:02:34.12#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.03:02:34.12#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.03:02:34.12$vck44/valo=8,884.99 2006.145.03:02:34.12#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.03:02:34.12#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.03:02:34.12#ibcon#ireg 17 cls_cnt 0 2006.145.03:02:34.12#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:02:34.12#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:02:34.12#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:02:34.14#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.03:02:34.18#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:02:34.18#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:02:34.18#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.03:02:34.18#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.03:02:34.18$vck44/va=8,4 2006.145.03:02:34.18#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.03:02:34.18#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.03:02:34.18#ibcon#ireg 11 cls_cnt 2 2006.145.03:02:34.18#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:02:34.24#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:02:34.24#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:02:34.26#ibcon#[25=AT08-04\r\n] 2006.145.03:02:34.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:02:34.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:02:34.30#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.03:02:34.30#ibcon#ireg 7 cls_cnt 0 2006.145.03:02:34.30#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:02:34.42#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:02:34.42#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:02:34.43#abcon#<5=/05 4.4 7.7 20.01 621016.9\r\n> 2006.145.03:02:34.44#ibcon#[25=USB\r\n] 2006.145.03:02:34.45#abcon#{5=INTERFACE CLEAR} 2006.145.03:02:34.47#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:02:34.47#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:02:34.47#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.03:02:34.47#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.03:02:34.47$vck44/vblo=1,629.99 2006.145.03:02:34.47#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.03:02:34.47#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.03:02:34.47#ibcon#ireg 17 cls_cnt 0 2006.145.03:02:34.47#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.03:02:34.47#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.03:02:34.47#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.03:02:34.49#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.03:02:34.51#abcon#[5=S1D000X0/0*\r\n] 2006.145.03:02:34.53#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.03:02:34.53#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.03:02:34.53#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.03:02:34.53#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.03:02:34.53$vck44/vb=1,3 2006.145.03:02:34.53#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.03:02:34.53#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.03:02:34.53#ibcon#ireg 11 cls_cnt 2 2006.145.03:02:34.53#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.03:02:34.53#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.03:02:34.53#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.03:02:34.55#ibcon#[27=AT01-03\r\n] 2006.145.03:02:34.58#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.03:02:34.58#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.03:02:34.58#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.03:02:34.58#ibcon#ireg 7 cls_cnt 0 2006.145.03:02:34.58#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.03:02:34.70#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.03:02:34.70#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.03:02:34.72#ibcon#[27=USB\r\n] 2006.145.03:02:34.75#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.03:02:34.75#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.03:02:34.75#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.03:02:34.75#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.03:02:34.75$vck44/vblo=2,634.99 2006.145.03:02:34.75#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.03:02:34.75#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.03:02:34.75#ibcon#ireg 17 cls_cnt 0 2006.145.03:02:34.75#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:02:34.75#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:02:34.75#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:02:34.77#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.03:02:34.81#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:02:34.81#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:02:34.81#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.03:02:34.81#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.03:02:34.81$vck44/vb=2,4 2006.145.03:02:34.81#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.03:02:34.81#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.03:02:34.81#ibcon#ireg 11 cls_cnt 2 2006.145.03:02:34.81#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.03:02:34.87#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.03:02:34.87#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.03:02:34.89#ibcon#[27=AT02-04\r\n] 2006.145.03:02:34.92#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.03:02:34.92#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.03:02:34.92#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.03:02:34.92#ibcon#ireg 7 cls_cnt 0 2006.145.03:02:34.92#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.03:02:35.04#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.03:02:35.04#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.03:02:35.06#ibcon#[27=USB\r\n] 2006.145.03:02:35.09#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.03:02:35.09#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.03:02:35.09#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.03:02:35.09#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.03:02:35.09$vck44/vblo=3,649.99 2006.145.03:02:35.09#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.03:02:35.09#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.03:02:35.09#ibcon#ireg 17 cls_cnt 0 2006.145.03:02:35.09#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:02:35.09#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:02:35.09#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:02:35.11#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.03:02:35.16#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:02:35.16#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:02:35.16#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.03:02:35.16#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.03:02:35.16$vck44/vb=3,4 2006.145.03:02:35.16#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.03:02:35.16#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.03:02:35.16#ibcon#ireg 11 cls_cnt 2 2006.145.03:02:35.16#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:02:35.21#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:02:35.21#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:02:35.23#ibcon#[27=AT03-04\r\n] 2006.145.03:02:35.26#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:02:35.26#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:02:35.26#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.03:02:35.26#ibcon#ireg 7 cls_cnt 0 2006.145.03:02:35.26#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:02:35.38#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:02:35.38#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:02:35.40#ibcon#[27=USB\r\n] 2006.145.03:02:35.43#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:02:35.43#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:02:35.43#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.03:02:35.43#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.03:02:35.43$vck44/vblo=4,679.99 2006.145.03:02:35.43#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.03:02:35.43#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.03:02:35.43#ibcon#ireg 17 cls_cnt 0 2006.145.03:02:35.43#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:02:35.43#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:02:35.43#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:02:35.45#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.03:02:35.49#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:02:35.49#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:02:35.49#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.03:02:35.49#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.03:02:35.49$vck44/vb=4,4 2006.145.03:02:35.49#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.03:02:35.49#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.03:02:35.49#ibcon#ireg 11 cls_cnt 2 2006.145.03:02:35.49#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:02:35.55#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:02:35.55#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:02:35.57#ibcon#[27=AT04-04\r\n] 2006.145.03:02:35.60#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:02:35.60#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:02:35.60#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.03:02:35.60#ibcon#ireg 7 cls_cnt 0 2006.145.03:02:35.60#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:02:35.72#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:02:35.72#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:02:35.74#ibcon#[27=USB\r\n] 2006.145.03:02:35.77#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:02:35.77#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:02:35.77#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.03:02:35.77#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.03:02:35.77$vck44/vblo=5,709.99 2006.145.03:02:35.77#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.03:02:35.77#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.03:02:35.77#ibcon#ireg 17 cls_cnt 0 2006.145.03:02:35.77#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:02:35.77#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:02:35.77#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:02:35.79#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.03:02:35.83#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:02:35.83#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:02:35.83#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.03:02:35.83#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.03:02:35.83$vck44/vb=5,4 2006.145.03:02:35.83#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.03:02:35.83#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.03:02:35.83#ibcon#ireg 11 cls_cnt 2 2006.145.03:02:35.83#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.03:02:35.89#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.03:02:35.89#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.03:02:35.91#ibcon#[27=AT05-04\r\n] 2006.145.03:02:35.94#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.03:02:35.94#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.03:02:35.94#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.03:02:35.94#ibcon#ireg 7 cls_cnt 0 2006.145.03:02:35.94#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.03:02:36.06#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.03:02:36.06#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.03:02:36.08#ibcon#[27=USB\r\n] 2006.145.03:02:36.11#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.03:02:36.11#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.03:02:36.11#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.03:02:36.11#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.03:02:36.11$vck44/vblo=6,719.99 2006.145.03:02:36.11#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.03:02:36.11#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.03:02:36.11#ibcon#ireg 17 cls_cnt 0 2006.145.03:02:36.11#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:02:36.11#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:02:36.11#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:02:36.13#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.03:02:36.17#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:02:36.17#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:02:36.17#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.03:02:36.17#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.03:02:36.17$vck44/vb=6,4 2006.145.03:02:36.17#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.03:02:36.17#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.03:02:36.17#ibcon#ireg 11 cls_cnt 2 2006.145.03:02:36.17#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:02:36.23#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:02:36.23#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:02:36.25#ibcon#[27=AT06-04\r\n] 2006.145.03:02:36.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:02:36.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:02:36.28#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.03:02:36.28#ibcon#ireg 7 cls_cnt 0 2006.145.03:02:36.28#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:02:36.40#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:02:36.40#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:02:36.42#ibcon#[27=USB\r\n] 2006.145.03:02:36.45#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:02:36.45#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:02:36.45#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.03:02:36.45#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.03:02:36.45$vck44/vblo=7,734.99 2006.145.03:02:36.45#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.03:02:36.45#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.03:02:36.45#ibcon#ireg 17 cls_cnt 0 2006.145.03:02:36.45#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:02:36.45#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:02:36.45#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:02:36.47#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.03:02:36.51#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:02:36.51#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:02:36.51#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.03:02:36.51#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.03:02:36.51$vck44/vb=7,4 2006.145.03:02:36.51#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.03:02:36.51#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.03:02:36.51#ibcon#ireg 11 cls_cnt 2 2006.145.03:02:36.51#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:02:36.57#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:02:36.57#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:02:36.59#ibcon#[27=AT07-04\r\n] 2006.145.03:02:36.62#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:02:36.62#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:02:36.62#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.03:02:36.62#ibcon#ireg 7 cls_cnt 0 2006.145.03:02:36.62#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:02:36.74#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:02:36.74#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:02:36.76#ibcon#[27=USB\r\n] 2006.145.03:02:36.79#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:02:36.79#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:02:36.79#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.03:02:36.79#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.03:02:36.79$vck44/vblo=8,744.99 2006.145.03:02:36.79#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.03:02:36.79#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.03:02:36.79#ibcon#ireg 17 cls_cnt 0 2006.145.03:02:36.79#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:02:36.79#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:02:36.79#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:02:36.81#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.03:02:36.85#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:02:36.85#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:02:36.85#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.03:02:36.85#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.03:02:36.85$vck44/vb=8,4 2006.145.03:02:36.85#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.03:02:36.85#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.03:02:36.85#ibcon#ireg 11 cls_cnt 2 2006.145.03:02:36.85#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:02:36.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:02:36.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:02:36.93#ibcon#[27=AT08-04\r\n] 2006.145.03:02:36.96#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:02:36.96#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:02:36.96#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.03:02:36.96#ibcon#ireg 7 cls_cnt 0 2006.145.03:02:36.96#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:02:37.08#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:02:37.08#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:02:37.10#ibcon#[27=USB\r\n] 2006.145.03:02:37.13#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:02:37.13#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:02:37.13#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.03:02:37.13#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.03:02:37.13$vck44/vabw=wide 2006.145.03:02:37.13#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.03:02:37.13#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.03:02:37.13#ibcon#ireg 8 cls_cnt 0 2006.145.03:02:37.13#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.03:02:37.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.03:02:37.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.03:02:37.15#ibcon#[25=BW32\r\n] 2006.145.03:02:37.18#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.03:02:37.18#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.03:02:37.18#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.03:02:37.18#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.03:02:37.18$vck44/vbbw=wide 2006.145.03:02:37.18#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.03:02:37.18#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.03:02:37.18#ibcon#ireg 8 cls_cnt 0 2006.145.03:02:37.18#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:02:37.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:02:37.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:02:37.27#ibcon#[27=BW32\r\n] 2006.145.03:02:37.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:02:37.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:02:37.30#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.03:02:37.30#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.03:02:37.30$setupk4/ifdk4 2006.145.03:02:37.30$ifdk4/lo= 2006.145.03:02:37.30$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.03:02:37.30$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.03:02:37.30$ifdk4/patch= 2006.145.03:02:37.30$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.03:02:37.30$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.03:02:37.30$setupk4/!*+20s 2006.145.03:02:44.60#abcon#<5=/05 4.4 7.7 20.00 641016.9\r\n> 2006.145.03:02:44.62#abcon#{5=INTERFACE CLEAR} 2006.145.03:02:44.68#abcon#[5=S1D000X0/0*\r\n] 2006.145.03:02:51.73$setupk4/"tpicd 2006.145.03:02:51.73$setupk4/echo=off 2006.145.03:02:51.73$setupk4/xlog=off 2006.145.03:02:51.73:!2006.145.03:05:40 2006.145.03:03:15.14#trakl#Source acquired 2006.145.03:03:17.14#flagr#flagr/antenna,acquired 2006.145.03:05:40.02:preob 2006.145.03:05:41.14/onsource/TRACKING 2006.145.03:05:41.14:!2006.145.03:05:50 2006.145.03:05:50.02:"tape 2006.145.03:05:50.02:"st=record 2006.145.03:05:50.02:data_valid=on 2006.145.03:05:50.02:midob 2006.145.03:05:51.14/onsource/TRACKING 2006.145.03:05:51.14/wx/19.93,1016.8,65 2006.145.03:05:51.23/cable/+6.5475E-03 2006.145.03:05:52.32/va/01,08,usb,yes,32,34 2006.145.03:05:52.32/va/02,07,usb,yes,34,35 2006.145.03:05:52.32/va/03,08,usb,yes,31,33 2006.145.03:05:52.32/va/04,07,usb,yes,35,37 2006.145.03:05:52.32/va/05,04,usb,yes,31,32 2006.145.03:05:52.32/va/06,04,usb,yes,35,35 2006.145.03:05:52.32/va/07,04,usb,yes,35,36 2006.145.03:05:52.32/va/08,04,usb,yes,30,36 2006.145.03:05:52.55/valo/01,524.99,yes,locked 2006.145.03:05:52.55/valo/02,534.99,yes,locked 2006.145.03:05:52.55/valo/03,564.99,yes,locked 2006.145.03:05:52.55/valo/04,624.99,yes,locked 2006.145.03:05:52.55/valo/05,734.99,yes,locked 2006.145.03:05:52.55/valo/06,814.99,yes,locked 2006.145.03:05:52.55/valo/07,864.99,yes,locked 2006.145.03:05:52.55/valo/08,884.99,yes,locked 2006.145.03:05:53.64/vb/01,03,usb,yes,39,36 2006.145.03:05:53.64/vb/02,04,usb,yes,34,34 2006.145.03:05:53.64/vb/03,04,usb,yes,31,34 2006.145.03:05:53.64/vb/04,04,usb,yes,35,34 2006.145.03:05:53.64/vb/05,04,usb,yes,28,30 2006.145.03:05:53.64/vb/06,04,usb,yes,32,28 2006.145.03:05:53.64/vb/07,04,usb,yes,32,32 2006.145.03:05:53.64/vb/08,04,usb,yes,30,33 2006.145.03:05:53.87/vblo/01,629.99,yes,locked 2006.145.03:05:53.87/vblo/02,634.99,yes,locked 2006.145.03:05:53.87/vblo/03,649.99,yes,locked 2006.145.03:05:53.87/vblo/04,679.99,yes,locked 2006.145.03:05:53.87/vblo/05,709.99,yes,locked 2006.145.03:05:53.87/vblo/06,719.99,yes,locked 2006.145.03:05:53.87/vblo/07,734.99,yes,locked 2006.145.03:05:53.87/vblo/08,744.99,yes,locked 2006.145.03:05:54.02/vabw/8 2006.145.03:05:54.17/vbbw/8 2006.145.03:05:54.26/xfe/off,on,15.2 2006.145.03:05:54.64/ifatt/23,28,28,28 2006.145.03:05:55.07/fmout-gps/S +4.7E-08 2006.145.03:05:55.12:!2006.145.03:06:30 2006.145.03:06:30.02:data_valid=off 2006.145.03:06:30.02:"et 2006.145.03:06:30.02:!+3s 2006.145.03:06:33.05:"tape 2006.145.03:06:33.06:postob 2006.145.03:06:33.28/cable/+6.5475E-03 2006.145.03:06:33.29/wx/19.93,1016.8,67 2006.145.03:06:33.34/fmout-gps/S +4.7E-08 2006.145.03:06:33.35:scan_name=145-0309,jd0605,70 2006.145.03:06:33.35:source=0727-115,073019.11,-114112.6,2000.0,cw 2006.145.03:06:34.14#flagr#flagr/antenna,new-source 2006.145.03:06:34.14:checkk5 2006.145.03:06:34.56/chk_autoobs//k5ts1/ autoobs is running! 2006.145.03:06:34.96/chk_autoobs//k5ts2/ autoobs is running! 2006.145.03:06:35.36/chk_autoobs//k5ts3/ autoobs is running! 2006.145.03:06:35.76/chk_autoobs//k5ts4/ autoobs is running! 2006.145.03:06:36.20/chk_obsdata//k5ts1/T1450305??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.03:06:36.59/chk_obsdata//k5ts2/T1450305??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.03:06:37.00/chk_obsdata//k5ts3/T1450305??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.03:06:37.41/chk_obsdata//k5ts4/T1450305??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.03:06:38.13/k5log//k5ts1_log_newline 2006.145.03:06:38.92/k5log//k5ts2_log_newline 2006.145.03:06:39.63/k5log//k5ts3_log_newline 2006.145.03:06:40.35/k5log//k5ts4_log_newline 2006.145.03:06:40.38/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.03:06:40.38:setupk4=1 2006.145.03:06:40.38$setupk4/echo=on 2006.145.03:06:40.38$setupk4/pcalon 2006.145.03:06:40.38$pcalon/"no phase cal control is implemented here 2006.145.03:06:40.38$setupk4/"tpicd=stop 2006.145.03:06:40.38$setupk4/"rec=synch_on 2006.145.03:06:40.38$setupk4/"rec_mode=128 2006.145.03:06:40.38$setupk4/!* 2006.145.03:06:40.38$setupk4/recpk4 2006.145.03:06:40.38$recpk4/recpatch= 2006.145.03:06:40.38$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.03:06:40.38$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.03:06:40.38$setupk4/vck44 2006.145.03:06:40.38$vck44/valo=1,524.99 2006.145.03:06:40.38#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.03:06:40.38#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.03:06:40.38#ibcon#ireg 17 cls_cnt 0 2006.145.03:06:40.38#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.03:06:40.38#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.03:06:40.38#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.03:06:40.42#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.03:06:40.46#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.03:06:40.46#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.03:06:40.46#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.03:06:40.46#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.03:06:40.46$vck44/va=1,8 2006.145.03:06:40.46#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.03:06:40.46#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.03:06:40.46#ibcon#ireg 11 cls_cnt 2 2006.145.03:06:40.46#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.03:06:40.46#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.03:06:40.46#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.03:06:40.49#ibcon#[25=AT01-08\r\n] 2006.145.03:06:40.52#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.03:06:40.52#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.03:06:40.52#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.03:06:40.52#ibcon#ireg 7 cls_cnt 0 2006.145.03:06:40.52#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.03:06:40.64#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.03:06:40.64#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.03:06:40.66#ibcon#[25=USB\r\n] 2006.145.03:06:40.71#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.03:06:40.71#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.03:06:40.71#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.03:06:40.71#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.03:06:40.71$vck44/valo=2,534.99 2006.145.03:06:40.71#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.03:06:40.71#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.03:06:40.71#ibcon#ireg 17 cls_cnt 0 2006.145.03:06:40.71#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.03:06:40.71#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.03:06:40.71#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.03:06:40.72#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.03:06:40.76#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.03:06:40.76#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.03:06:40.76#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.03:06:40.76#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.03:06:40.76$vck44/va=2,7 2006.145.03:06:40.76#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.03:06:40.76#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.03:06:40.76#ibcon#ireg 11 cls_cnt 2 2006.145.03:06:40.76#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.03:06:40.83#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.03:06:40.83#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.03:06:40.85#ibcon#[25=AT02-07\r\n] 2006.145.03:06:40.88#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.03:06:40.88#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.03:06:40.88#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.03:06:40.88#ibcon#ireg 7 cls_cnt 0 2006.145.03:06:40.88#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.03:06:41.00#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.03:06:41.00#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.03:06:41.02#ibcon#[25=USB\r\n] 2006.145.03:06:41.05#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.03:06:41.05#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.03:06:41.05#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.03:06:41.05#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.03:06:41.05$vck44/valo=3,564.99 2006.145.03:06:41.05#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.03:06:41.05#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.03:06:41.05#ibcon#ireg 17 cls_cnt 0 2006.145.03:06:41.05#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.03:06:41.05#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.03:06:41.05#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.03:06:41.09#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.03:06:41.12#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.03:06:41.12#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.03:06:41.12#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.03:06:41.12#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.03:06:41.12$vck44/va=3,8 2006.145.03:06:41.12#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.03:06:41.12#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.03:06:41.12#ibcon#ireg 11 cls_cnt 2 2006.145.03:06:41.12#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.03:06:41.17#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.03:06:41.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.03:06:41.20#ibcon#[25=AT03-08\r\n] 2006.145.03:06:41.22#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.03:06:41.22#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.03:06:41.22#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.03:06:41.22#ibcon#ireg 7 cls_cnt 0 2006.145.03:06:41.22#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.03:06:41.34#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.03:06:41.34#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.03:06:41.36#ibcon#[25=USB\r\n] 2006.145.03:06:41.39#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.03:06:41.39#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.03:06:41.39#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.03:06:41.39#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.03:06:41.39$vck44/valo=4,624.99 2006.145.03:06:41.39#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.03:06:41.39#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.03:06:41.39#ibcon#ireg 17 cls_cnt 0 2006.145.03:06:41.39#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.03:06:41.39#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.03:06:41.39#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.03:06:41.41#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.03:06:41.45#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.03:06:41.45#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.03:06:41.45#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.03:06:41.45#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.03:06:41.45$vck44/va=4,7 2006.145.03:06:41.45#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.03:06:41.45#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.03:06:41.45#ibcon#ireg 11 cls_cnt 2 2006.145.03:06:41.45#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.03:06:41.51#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.03:06:41.51#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.03:06:41.53#ibcon#[25=AT04-07\r\n] 2006.145.03:06:41.56#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.03:06:41.56#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.03:06:41.56#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.03:06:41.56#ibcon#ireg 7 cls_cnt 0 2006.145.03:06:41.56#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.03:06:41.68#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.03:06:41.68#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.03:06:41.70#ibcon#[25=USB\r\n] 2006.145.03:06:41.73#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.03:06:41.73#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.03:06:41.73#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.03:06:41.73#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.03:06:41.73$vck44/valo=5,734.99 2006.145.03:06:41.73#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.03:06:41.73#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.03:06:41.73#ibcon#ireg 17 cls_cnt 0 2006.145.03:06:41.73#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.03:06:41.73#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.03:06:41.73#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.03:06:41.75#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.03:06:41.79#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.03:06:41.79#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.03:06:41.79#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.03:06:41.79#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.03:06:41.79$vck44/va=5,4 2006.145.03:06:41.79#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.03:06:41.79#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.03:06:41.79#ibcon#ireg 11 cls_cnt 2 2006.145.03:06:41.79#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.03:06:41.85#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.03:06:41.85#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.03:06:41.87#ibcon#[25=AT05-04\r\n] 2006.145.03:06:41.90#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.03:06:41.90#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.03:06:41.90#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.03:06:41.90#ibcon#ireg 7 cls_cnt 0 2006.145.03:06:41.90#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.03:06:42.02#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.03:06:42.02#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.03:06:42.04#ibcon#[25=USB\r\n] 2006.145.03:06:42.07#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.03:06:42.07#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.03:06:42.07#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.03:06:42.07#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.03:06:42.07$vck44/valo=6,814.99 2006.145.03:06:42.07#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.03:06:42.07#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.03:06:42.07#ibcon#ireg 17 cls_cnt 0 2006.145.03:06:42.07#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.03:06:42.07#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.03:06:42.07#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.03:06:42.09#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.03:06:42.13#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.03:06:42.13#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.03:06:42.13#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.03:06:42.13#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.03:06:42.13$vck44/va=6,4 2006.145.03:06:42.13#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.03:06:42.13#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.03:06:42.13#ibcon#ireg 11 cls_cnt 2 2006.145.03:06:42.13#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.03:06:42.19#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.03:06:42.19#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.03:06:42.21#ibcon#[25=AT06-04\r\n] 2006.145.03:06:42.24#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.03:06:42.24#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.03:06:42.24#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.03:06:42.24#ibcon#ireg 7 cls_cnt 0 2006.145.03:06:42.24#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.03:06:42.36#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.03:06:42.36#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.03:06:42.38#ibcon#[25=USB\r\n] 2006.145.03:06:42.41#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.03:06:42.41#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.03:06:42.41#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.03:06:42.41#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.03:06:42.41$vck44/valo=7,864.99 2006.145.03:06:42.41#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.03:06:42.41#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.03:06:42.41#ibcon#ireg 17 cls_cnt 0 2006.145.03:06:42.41#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.03:06:42.41#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.03:06:42.41#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.03:06:42.43#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.03:06:42.47#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.03:06:42.47#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.03:06:42.47#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.03:06:42.47#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.03:06:42.47$vck44/va=7,4 2006.145.03:06:42.47#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.03:06:42.47#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.03:06:42.47#ibcon#ireg 11 cls_cnt 2 2006.145.03:06:42.47#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.03:06:42.53#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.03:06:42.53#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.03:06:42.55#ibcon#[25=AT07-04\r\n] 2006.145.03:06:42.58#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.03:06:42.58#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.03:06:42.58#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.03:06:42.58#ibcon#ireg 7 cls_cnt 0 2006.145.03:06:42.58#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.03:06:42.70#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.03:06:42.70#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.03:06:42.72#ibcon#[25=USB\r\n] 2006.145.03:06:42.75#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.03:06:42.75#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.03:06:42.75#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.03:06:42.75#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.03:06:42.75$vck44/valo=8,884.99 2006.145.03:06:42.75#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.03:06:42.75#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.03:06:42.75#ibcon#ireg 17 cls_cnt 0 2006.145.03:06:42.75#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.03:06:42.75#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.03:06:42.75#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.03:06:42.77#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.03:06:42.81#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.03:06:42.81#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.03:06:42.81#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.03:06:42.81#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.03:06:42.81$vck44/va=8,4 2006.145.03:06:42.81#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.03:06:42.81#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.03:06:42.81#ibcon#ireg 11 cls_cnt 2 2006.145.03:06:42.81#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.03:06:42.87#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.03:06:42.87#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.03:06:42.89#ibcon#[25=AT08-04\r\n] 2006.145.03:06:42.92#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.03:06:42.92#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.03:06:42.92#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.03:06:42.92#ibcon#ireg 7 cls_cnt 0 2006.145.03:06:42.92#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.03:06:43.04#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.03:06:43.04#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.03:06:43.06#ibcon#[25=USB\r\n] 2006.145.03:06:43.09#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.03:06:43.09#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.03:06:43.09#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.03:06:43.09#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.03:06:43.09$vck44/vblo=1,629.99 2006.145.03:06:43.09#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.03:06:43.09#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.03:06:43.09#ibcon#ireg 17 cls_cnt 0 2006.145.03:06:43.09#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.03:06:43.09#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.03:06:43.09#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.03:06:43.11#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.03:06:43.15#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.03:06:43.15#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.03:06:43.15#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.03:06:43.15#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.03:06:43.15$vck44/vb=1,3 2006.145.03:06:43.15#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.03:06:43.15#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.03:06:43.15#ibcon#ireg 11 cls_cnt 2 2006.145.03:06:43.15#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.03:06:43.15#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.03:06:43.15#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.03:06:43.17#ibcon#[27=AT01-03\r\n] 2006.145.03:06:43.20#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.03:06:43.20#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.03:06:43.20#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.03:06:43.20#ibcon#ireg 7 cls_cnt 0 2006.145.03:06:43.20#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.03:06:43.32#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.03:06:43.32#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.03:06:43.34#ibcon#[27=USB\r\n] 2006.145.03:06:43.37#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.03:06:43.37#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.03:06:43.37#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.03:06:43.37#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.03:06:43.38$vck44/vblo=2,634.99 2006.145.03:06:43.38#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.03:06:43.38#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.03:06:43.38#ibcon#ireg 17 cls_cnt 0 2006.145.03:06:43.38#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.03:06:43.38#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.03:06:43.38#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.03:06:43.39#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.03:06:43.43#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.03:06:43.43#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.03:06:43.43#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.03:06:43.43#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.03:06:43.43$vck44/vb=2,4 2006.145.03:06:43.43#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.03:06:43.43#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.03:06:43.43#ibcon#ireg 11 cls_cnt 2 2006.145.03:06:43.43#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.03:06:43.49#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.03:06:43.49#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.03:06:43.51#ibcon#[27=AT02-04\r\n] 2006.145.03:06:43.54#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.03:06:43.54#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.03:06:43.54#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.03:06:43.54#ibcon#ireg 7 cls_cnt 0 2006.145.03:06:43.54#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.03:06:43.66#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.03:06:43.66#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.03:06:43.68#ibcon#[27=USB\r\n] 2006.145.03:06:43.71#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.03:06:43.71#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.03:06:43.71#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.03:06:43.71#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.03:06:43.71$vck44/vblo=3,649.99 2006.145.03:06:43.71#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.03:06:43.71#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.03:06:43.71#ibcon#ireg 17 cls_cnt 0 2006.145.03:06:43.71#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.03:06:43.71#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.03:06:43.71#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.03:06:43.73#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.03:06:43.77#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.03:06:43.77#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.03:06:43.77#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.03:06:43.77#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.03:06:43.77$vck44/vb=3,4 2006.145.03:06:43.77#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.03:06:43.77#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.03:06:43.77#ibcon#ireg 11 cls_cnt 2 2006.145.03:06:43.77#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.03:06:43.83#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.03:06:43.83#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.03:06:43.85#ibcon#[27=AT03-04\r\n] 2006.145.03:06:43.88#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.03:06:43.88#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.03:06:43.88#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.03:06:43.88#ibcon#ireg 7 cls_cnt 0 2006.145.03:06:43.88#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.03:06:44.00#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.03:06:44.00#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.03:06:44.02#ibcon#[27=USB\r\n] 2006.145.03:06:44.05#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.03:06:44.05#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.03:06:44.05#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.03:06:44.05#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.03:06:44.05$vck44/vblo=4,679.99 2006.145.03:06:44.05#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.03:06:44.05#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.03:06:44.05#ibcon#ireg 17 cls_cnt 0 2006.145.03:06:44.05#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.03:06:44.05#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.03:06:44.05#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.03:06:44.07#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.03:06:44.11#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.03:06:44.11#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.03:06:44.11#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.03:06:44.11#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.03:06:44.11$vck44/vb=4,4 2006.145.03:06:44.11#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.03:06:44.11#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.03:06:44.11#ibcon#ireg 11 cls_cnt 2 2006.145.03:06:44.11#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.03:06:44.17#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.03:06:44.17#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.03:06:44.19#ibcon#[27=AT04-04\r\n] 2006.145.03:06:44.22#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.03:06:44.22#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.03:06:44.22#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.03:06:44.22#ibcon#ireg 7 cls_cnt 0 2006.145.03:06:44.22#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.03:06:44.34#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.03:06:44.34#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.03:06:44.36#ibcon#[27=USB\r\n] 2006.145.03:06:44.39#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.03:06:44.39#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.03:06:44.39#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.03:06:44.39#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.03:06:44.39$vck44/vblo=5,709.99 2006.145.03:06:44.39#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.03:06:44.39#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.03:06:44.39#ibcon#ireg 17 cls_cnt 0 2006.145.03:06:44.39#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.03:06:44.39#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.03:06:44.39#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.03:06:44.41#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.03:06:44.45#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.03:06:44.45#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.03:06:44.45#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.03:06:44.45#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.03:06:44.45$vck44/vb=5,4 2006.145.03:06:44.45#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.03:06:44.45#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.03:06:44.45#ibcon#ireg 11 cls_cnt 2 2006.145.03:06:44.45#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.03:06:44.51#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.03:06:44.51#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.03:06:44.53#ibcon#[27=AT05-04\r\n] 2006.145.03:06:44.56#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.03:06:44.56#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.03:06:44.56#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.03:06:44.56#ibcon#ireg 7 cls_cnt 0 2006.145.03:06:44.56#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.03:06:44.68#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.03:06:44.68#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.03:06:44.70#ibcon#[27=USB\r\n] 2006.145.03:06:44.73#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.03:06:44.73#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.03:06:44.73#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.03:06:44.73#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.03:06:44.73$vck44/vblo=6,719.99 2006.145.03:06:44.73#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.03:06:44.73#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.03:06:44.73#ibcon#ireg 17 cls_cnt 0 2006.145.03:06:44.73#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.03:06:44.73#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.03:06:44.73#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.03:06:44.75#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.03:06:44.79#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.03:06:44.79#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.03:06:44.79#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.03:06:44.79#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.03:06:44.79$vck44/vb=6,4 2006.145.03:06:44.79#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.03:06:44.79#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.03:06:44.79#ibcon#ireg 11 cls_cnt 2 2006.145.03:06:44.79#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.03:06:44.85#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.03:06:44.85#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.03:06:44.87#ibcon#[27=AT06-04\r\n] 2006.145.03:06:44.90#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.03:06:44.90#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.03:06:44.90#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.03:06:44.90#ibcon#ireg 7 cls_cnt 0 2006.145.03:06:44.90#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.03:06:45.02#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.03:06:45.02#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.03:06:45.04#ibcon#[27=USB\r\n] 2006.145.03:06:45.07#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.03:06:45.07#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.03:06:45.07#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.03:06:45.07#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.03:06:45.07$vck44/vblo=7,734.99 2006.145.03:06:45.07#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.03:06:45.07#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.03:06:45.07#ibcon#ireg 17 cls_cnt 0 2006.145.03:06:45.07#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.03:06:45.07#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.03:06:45.07#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.03:06:45.09#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.03:06:45.13#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.03:06:45.13#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.03:06:45.13#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.03:06:45.13#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.03:06:45.13$vck44/vb=7,4 2006.145.03:06:45.13#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.03:06:45.13#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.03:06:45.13#ibcon#ireg 11 cls_cnt 2 2006.145.03:06:45.13#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.03:06:45.19#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.03:06:45.19#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.03:06:45.21#ibcon#[27=AT07-04\r\n] 2006.145.03:06:45.24#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.03:06:45.24#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.03:06:45.24#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.03:06:45.24#ibcon#ireg 7 cls_cnt 0 2006.145.03:06:45.24#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.03:06:45.36#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.03:06:45.36#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.03:06:45.38#ibcon#[27=USB\r\n] 2006.145.03:06:45.41#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.03:06:45.41#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.03:06:45.41#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.03:06:45.41#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.03:06:45.41$vck44/vblo=8,744.99 2006.145.03:06:45.41#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.03:06:45.41#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.03:06:45.41#ibcon#ireg 17 cls_cnt 0 2006.145.03:06:45.41#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.03:06:45.41#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.03:06:45.41#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.03:06:45.43#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.03:06:45.47#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.03:06:45.47#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.03:06:45.47#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.03:06:45.47#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.03:06:45.47$vck44/vb=8,4 2006.145.03:06:45.47#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.03:06:45.47#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.03:06:45.47#ibcon#ireg 11 cls_cnt 2 2006.145.03:06:45.47#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.03:06:45.53#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.03:06:45.53#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.03:06:45.55#ibcon#[27=AT08-04\r\n] 2006.145.03:06:45.58#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.03:06:45.58#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.03:06:45.58#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.03:06:45.58#ibcon#ireg 7 cls_cnt 0 2006.145.03:06:45.58#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.03:06:45.70#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.03:06:45.70#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.03:06:45.72#ibcon#[27=USB\r\n] 2006.145.03:06:45.75#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.03:06:45.75#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.03:06:45.75#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.03:06:45.75#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.03:06:45.75$vck44/vabw=wide 2006.145.03:06:45.75#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.03:06:45.75#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.03:06:45.75#ibcon#ireg 8 cls_cnt 0 2006.145.03:06:45.75#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.03:06:45.75#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.03:06:45.75#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.03:06:45.77#ibcon#[25=BW32\r\n] 2006.145.03:06:45.80#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.03:06:45.80#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.03:06:45.80#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.03:06:45.80#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.03:06:45.80$vck44/vbbw=wide 2006.145.03:06:45.80#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.03:06:45.80#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.03:06:45.80#ibcon#ireg 8 cls_cnt 0 2006.145.03:06:45.80#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.03:06:45.87#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.03:06:45.87#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.03:06:45.89#ibcon#[27=BW32\r\n] 2006.145.03:06:45.92#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.03:06:45.92#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.03:06:45.92#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.03:06:45.92#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.03:06:45.92$setupk4/ifdk4 2006.145.03:06:45.92$ifdk4/lo= 2006.145.03:06:45.92$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.03:06:45.93$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.03:06:45.93$ifdk4/patch= 2006.145.03:06:45.93$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.03:06:45.93$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.03:06:45.93$setupk4/!*+20s 2006.145.03:06:48.76#abcon#<5=/05 4.5 7.7 19.94 641016.8\r\n> 2006.145.03:06:48.78#abcon#{5=INTERFACE CLEAR} 2006.145.03:06:48.84#abcon#[5=S1D000X0/0*\r\n] 2006.145.03:06:58.93#abcon#<5=/05 4.5 7.7 19.94 631016.7\r\n> 2006.145.03:06:58.95#abcon#{5=INTERFACE CLEAR} 2006.145.03:06:59.01#abcon#[5=S1D000X0/0*\r\n] 2006.145.03:07:00.40$setupk4/"tpicd 2006.145.03:07:00.40$setupk4/echo=off 2006.145.03:07:00.40$setupk4/xlog=off 2006.145.03:07:00.40:!2006.145.03:08:55 2006.145.03:07:32.14#trakl#Source acquired 2006.145.03:07:33.14#flagr#flagr/antenna,acquired 2006.145.03:08:55.00:preob 2006.145.03:08:55.14/onsource/TRACKING 2006.145.03:08:55.14:!2006.145.03:09:05 2006.145.03:09:05.00:"tape 2006.145.03:09:05.00:"st=record 2006.145.03:09:05.00:data_valid=on 2006.145.03:09:05.00:midob 2006.145.03:09:06.14/onsource/TRACKING 2006.145.03:09:06.14/wx/19.96,1016.7,58 2006.145.03:09:06.28/cable/+6.5477E-03 2006.145.03:09:07.37/va/01,08,usb,yes,29,31 2006.145.03:09:07.37/va/02,07,usb,yes,31,32 2006.145.03:09:07.37/va/03,08,usb,yes,28,29 2006.145.03:09:07.37/va/04,07,usb,yes,32,34 2006.145.03:09:07.37/va/05,04,usb,yes,28,29 2006.145.03:09:07.37/va/06,04,usb,yes,32,31 2006.145.03:09:07.37/va/07,04,usb,yes,32,33 2006.145.03:09:07.37/va/08,04,usb,yes,27,33 2006.145.03:09:07.60/valo/01,524.99,yes,locked 2006.145.03:09:07.60/valo/02,534.99,yes,locked 2006.145.03:09:07.60/valo/03,564.99,yes,locked 2006.145.03:09:07.60/valo/04,624.99,yes,locked 2006.145.03:09:07.60/valo/05,734.99,yes,locked 2006.145.03:09:07.60/valo/06,814.99,yes,locked 2006.145.03:09:07.60/valo/07,864.99,yes,locked 2006.145.03:09:07.60/valo/08,884.99,yes,locked 2006.145.03:09:08.69/vb/01,03,usb,yes,36,34 2006.145.03:09:08.69/vb/02,04,usb,yes,32,32 2006.145.03:09:08.69/vb/03,04,usb,yes,29,32 2006.145.03:09:08.69/vb/04,04,usb,yes,33,32 2006.145.03:09:08.69/vb/05,04,usb,yes,26,28 2006.145.03:09:08.69/vb/06,04,usb,yes,30,26 2006.145.03:09:08.69/vb/07,04,usb,yes,30,30 2006.145.03:09:08.69/vb/08,04,usb,yes,27,31 2006.145.03:09:08.92/vblo/01,629.99,yes,locked 2006.145.03:09:08.92/vblo/02,634.99,yes,locked 2006.145.03:09:08.92/vblo/03,649.99,yes,locked 2006.145.03:09:08.92/vblo/04,679.99,yes,locked 2006.145.03:09:08.92/vblo/05,709.99,yes,locked 2006.145.03:09:08.92/vblo/06,719.99,yes,locked 2006.145.03:09:08.92/vblo/07,734.99,yes,locked 2006.145.03:09:08.92/vblo/08,744.99,yes,locked 2006.145.03:09:09.07/vabw/8 2006.145.03:09:09.22/vbbw/8 2006.145.03:09:09.31/xfe/off,on,14.7 2006.145.03:09:09.71/ifatt/23,28,28,28 2006.145.03:09:10.07/fmout-gps/S +4.7E-08 2006.145.03:09:10.15:!2006.145.03:10:15 2006.145.03:10:15.01:data_valid=off 2006.145.03:10:15.02:"et 2006.145.03:10:15.02:!+3s 2006.145.03:10:18.05:"tape 2006.145.03:10:18.06:postob 2006.145.03:10:18.24/cable/+6.5459E-03 2006.145.03:10:18.25/wx/19.95,1016.7,65 2006.145.03:10:18.30/fmout-gps/S +4.7E-08 2006.145.03:10:18.30:scan_name=145-0312,jd0605,190 2006.145.03:10:18.30:source=0014+813,001708.47,813508.1,2000.0,neutral 2006.145.03:10:20.14#flagr#flagr/antenna,new-source 2006.145.03:10:20.15:checkk5 2006.145.03:10:20.63/chk_autoobs//k5ts1/ autoobs is running! 2006.145.03:10:21.08/chk_autoobs//k5ts2/ autoobs is running! 2006.145.03:10:21.59/chk_autoobs//k5ts3/ autoobs is running! 2006.145.03:10:22.05/chk_autoobs//k5ts4/ autoobs is running! 2006.145.03:10:22.59/chk_obsdata//k5ts1/T1450309??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.03:10:23.11/chk_obsdata//k5ts2/T1450309??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.03:10:23.62/chk_obsdata//k5ts3/T1450309??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.03:10:24.09/chk_obsdata//k5ts4/T1450309??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.03:10:24.95/k5log//k5ts1_log_newline 2006.145.03:10:26.00/k5log//k5ts2_log_newline 2006.145.03:10:26.80/k5log//k5ts3_log_newline 2006.145.03:10:27.64/k5log//k5ts4_log_newline 2006.145.03:10:27.66/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.03:10:27.66:setupk4=1 2006.145.03:10:27.66$setupk4/echo=on 2006.145.03:10:27.66$setupk4/pcalon 2006.145.03:10:27.66$pcalon/"no phase cal control is implemented here 2006.145.03:10:27.66$setupk4/"tpicd=stop 2006.145.03:10:27.66$setupk4/"rec=synch_on 2006.145.03:10:27.66$setupk4/"rec_mode=128 2006.145.03:10:27.66$setupk4/!* 2006.145.03:10:27.66$setupk4/recpk4 2006.145.03:10:27.66$recpk4/recpatch= 2006.145.03:10:27.67$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.03:10:27.67$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.03:10:27.67$setupk4/vck44 2006.145.03:10:27.67$vck44/valo=1,524.99 2006.145.03:10:27.67#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.03:10:27.67#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.03:10:27.67#ibcon#ireg 17 cls_cnt 0 2006.145.03:10:27.67#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.03:10:27.67#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.03:10:27.67#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.03:10:27.71#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.03:10:27.75#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.03:10:27.75#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.03:10:27.75#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.03:10:27.75#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.03:10:27.75$vck44/va=1,8 2006.145.03:10:27.75#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.03:10:27.75#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.03:10:27.75#ibcon#ireg 11 cls_cnt 2 2006.145.03:10:27.75#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.03:10:27.75#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.03:10:27.75#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.03:10:27.77#ibcon#[25=AT01-08\r\n] 2006.145.03:10:27.81#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.03:10:27.81#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.03:10:27.81#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.03:10:27.81#ibcon#ireg 7 cls_cnt 0 2006.145.03:10:27.81#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.03:10:27.92#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.03:10:27.92#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.03:10:27.94#ibcon#[25=USB\r\n] 2006.145.03:10:27.99#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.03:10:27.99#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.03:10:27.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.03:10:27.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.03:10:27.99$vck44/valo=2,534.99 2006.145.03:10:27.99#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.03:10:27.99#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.03:10:27.99#ibcon#ireg 17 cls_cnt 0 2006.145.03:10:27.99#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.03:10:27.99#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.03:10:27.99#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.03:10:28.00#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.03:10:28.04#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.03:10:28.04#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.03:10:28.04#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.03:10:28.04#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.03:10:28.04$vck44/va=2,7 2006.145.03:10:28.04#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.03:10:28.04#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.03:10:28.04#ibcon#ireg 11 cls_cnt 2 2006.145.03:10:28.04#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.03:10:28.11#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.03:10:28.11#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.03:10:28.13#ibcon#[25=AT02-07\r\n] 2006.145.03:10:28.16#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.03:10:28.16#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.03:10:28.16#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.03:10:28.16#ibcon#ireg 7 cls_cnt 0 2006.145.03:10:28.16#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.03:10:28.28#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.03:10:28.28#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.03:10:28.30#ibcon#[25=USB\r\n] 2006.145.03:10:28.33#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.03:10:28.33#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.03:10:28.33#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.03:10:28.33#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.03:10:28.33$vck44/valo=3,564.99 2006.145.03:10:28.33#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.03:10:28.33#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.03:10:28.33#ibcon#ireg 17 cls_cnt 0 2006.145.03:10:28.33#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.03:10:28.33#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.03:10:28.33#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.03:10:28.35#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.03:10:28.39#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.03:10:28.39#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.03:10:28.39#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.03:10:28.39#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.03:10:28.39$vck44/va=3,8 2006.145.03:10:28.39#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.03:10:28.39#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.03:10:28.39#ibcon#ireg 11 cls_cnt 2 2006.145.03:10:28.39#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.03:10:28.45#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.03:10:28.45#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.03:10:28.47#ibcon#[25=AT03-08\r\n] 2006.145.03:10:28.50#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.03:10:28.50#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.03:10:28.50#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.03:10:28.50#ibcon#ireg 7 cls_cnt 0 2006.145.03:10:28.50#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.03:10:28.62#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.03:10:28.62#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.03:10:28.64#ibcon#[25=USB\r\n] 2006.145.03:10:28.67#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.03:10:28.67#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.03:10:28.67#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.03:10:28.67#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.03:10:28.67$vck44/valo=4,624.99 2006.145.03:10:28.67#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.03:10:28.67#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.03:10:28.67#ibcon#ireg 17 cls_cnt 0 2006.145.03:10:28.67#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.03:10:28.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.03:10:28.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.03:10:28.69#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.03:10:28.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.03:10:28.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.03:10:28.73#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.03:10:28.73#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.03:10:28.73$vck44/va=4,7 2006.145.03:10:28.73#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.03:10:28.73#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.03:10:28.73#ibcon#ireg 11 cls_cnt 2 2006.145.03:10:28.73#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.03:10:28.79#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.03:10:28.79#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.03:10:28.81#ibcon#[25=AT04-07\r\n] 2006.145.03:10:28.84#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.03:10:28.84#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.03:10:28.84#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.03:10:28.84#ibcon#ireg 7 cls_cnt 0 2006.145.03:10:28.84#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.03:10:28.96#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.03:10:28.96#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.03:10:28.98#ibcon#[25=USB\r\n] 2006.145.03:10:29.01#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.03:10:29.01#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.03:10:29.01#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.03:10:29.01#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.03:10:29.01$vck44/valo=5,734.99 2006.145.03:10:29.01#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.03:10:29.01#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.03:10:29.01#ibcon#ireg 17 cls_cnt 0 2006.145.03:10:29.01#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.03:10:29.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.03:10:29.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.03:10:29.03#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.03:10:29.07#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.03:10:29.07#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.03:10:29.07#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.03:10:29.07#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.03:10:29.07$vck44/va=5,4 2006.145.03:10:29.07#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.03:10:29.07#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.03:10:29.07#ibcon#ireg 11 cls_cnt 2 2006.145.03:10:29.07#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.03:10:29.13#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.03:10:29.13#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.03:10:29.15#ibcon#[25=AT05-04\r\n] 2006.145.03:10:29.18#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.03:10:29.18#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.03:10:29.18#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.03:10:29.18#ibcon#ireg 7 cls_cnt 0 2006.145.03:10:29.18#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.03:10:29.30#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.03:10:29.30#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.03:10:29.32#ibcon#[25=USB\r\n] 2006.145.03:10:29.35#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.03:10:29.35#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.03:10:29.35#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.03:10:29.35#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.03:10:29.35$vck44/valo=6,814.99 2006.145.03:10:29.35#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.03:10:29.35#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.03:10:29.35#ibcon#ireg 17 cls_cnt 0 2006.145.03:10:29.35#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.03:10:29.35#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.03:10:29.35#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.03:10:29.37#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.03:10:29.41#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.03:10:29.41#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.03:10:29.41#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.03:10:29.41#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.03:10:29.41$vck44/va=6,4 2006.145.03:10:29.41#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.03:10:29.41#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.03:10:29.41#ibcon#ireg 11 cls_cnt 2 2006.145.03:10:29.41#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.03:10:29.47#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.03:10:29.47#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.03:10:29.49#ibcon#[25=AT06-04\r\n] 2006.145.03:10:29.52#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.03:10:29.52#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.03:10:29.52#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.03:10:29.52#ibcon#ireg 7 cls_cnt 0 2006.145.03:10:29.52#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.03:10:29.65#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.03:10:29.65#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.03:10:29.66#ibcon#[25=USB\r\n] 2006.145.03:10:29.69#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.03:10:29.69#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.03:10:29.69#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.03:10:29.69#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.03:10:29.69$vck44/valo=7,864.99 2006.145.03:10:29.69#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.03:10:29.69#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.03:10:29.69#ibcon#ireg 17 cls_cnt 0 2006.145.03:10:29.69#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.03:10:29.69#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.03:10:29.69#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.03:10:29.71#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.03:10:29.75#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.03:10:29.75#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.03:10:29.75#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.03:10:29.75#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.03:10:29.75$vck44/va=7,4 2006.145.03:10:29.76#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.03:10:29.76#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.03:10:29.76#ibcon#ireg 11 cls_cnt 2 2006.145.03:10:29.76#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.03:10:29.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.03:10:29.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.03:10:29.83#ibcon#[25=AT07-04\r\n] 2006.145.03:10:29.86#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.03:10:29.86#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.03:10:29.86#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.03:10:29.86#ibcon#ireg 7 cls_cnt 0 2006.145.03:10:29.86#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.03:10:29.98#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.03:10:29.98#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.03:10:30.00#ibcon#[25=USB\r\n] 2006.145.03:10:30.03#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.03:10:30.03#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.03:10:30.03#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.03:10:30.03#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.03:10:30.03$vck44/valo=8,884.99 2006.145.03:10:30.03#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.03:10:30.03#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.03:10:30.03#ibcon#ireg 17 cls_cnt 0 2006.145.03:10:30.03#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:10:30.03#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:10:30.03#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:10:30.05#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.03:10:30.09#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:10:30.09#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:10:30.09#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.03:10:30.09#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.03:10:30.09$vck44/va=8,4 2006.145.03:10:30.09#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.03:10:30.09#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.03:10:30.09#ibcon#ireg 11 cls_cnt 2 2006.145.03:10:30.09#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.03:10:30.15#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.03:10:30.15#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.03:10:30.17#ibcon#[25=AT08-04\r\n] 2006.145.03:10:30.20#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.03:10:30.20#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.03:10:30.20#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.03:10:30.20#ibcon#ireg 7 cls_cnt 0 2006.145.03:10:30.20#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.03:10:30.32#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.03:10:30.32#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.03:10:30.34#ibcon#[25=USB\r\n] 2006.145.03:10:30.37#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.03:10:30.37#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.03:10:30.37#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.03:10:30.37#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.03:10:30.37$vck44/vblo=1,629.99 2006.145.03:10:30.37#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.03:10:30.37#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.03:10:30.37#ibcon#ireg 17 cls_cnt 0 2006.145.03:10:30.37#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.03:10:30.37#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.03:10:30.37#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.03:10:30.39#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.03:10:30.43#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.03:10:30.43#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.03:10:30.43#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.03:10:30.43#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.03:10:30.43$vck44/vb=1,3 2006.145.03:10:30.43#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.03:10:30.43#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.03:10:30.43#ibcon#ireg 11 cls_cnt 2 2006.145.03:10:30.43#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.03:10:30.43#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.03:10:30.43#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.03:10:30.45#ibcon#[27=AT01-03\r\n] 2006.145.03:10:30.48#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.03:10:30.48#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.03:10:30.48#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.03:10:30.48#ibcon#ireg 7 cls_cnt 0 2006.145.03:10:30.48#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.03:10:30.60#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.03:10:30.60#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.03:10:30.62#ibcon#[27=USB\r\n] 2006.145.03:10:30.65#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.03:10:30.65#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.03:10:30.65#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.03:10:30.65#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.03:10:30.65$vck44/vblo=2,634.99 2006.145.03:10:30.65#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.03:10:30.65#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.03:10:30.65#ibcon#ireg 17 cls_cnt 0 2006.145.03:10:30.65#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.03:10:30.65#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.03:10:30.65#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.03:10:30.67#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.03:10:30.71#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.03:10:30.71#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.03:10:30.71#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.03:10:30.71#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.03:10:30.71$vck44/vb=2,4 2006.145.03:10:30.71#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.03:10:30.71#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.03:10:30.71#ibcon#ireg 11 cls_cnt 2 2006.145.03:10:30.71#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.03:10:30.77#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.03:10:30.77#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.03:10:30.79#ibcon#[27=AT02-04\r\n] 2006.145.03:10:30.82#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.03:10:30.82#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.03:10:30.82#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.03:10:30.82#ibcon#ireg 7 cls_cnt 0 2006.145.03:10:30.82#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.03:10:30.94#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.03:10:30.94#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.03:10:30.96#ibcon#[27=USB\r\n] 2006.145.03:10:30.99#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.03:10:30.99#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.03:10:30.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.03:10:30.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.03:10:30.99$vck44/vblo=3,649.99 2006.145.03:10:30.99#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.03:10:30.99#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.03:10:30.99#ibcon#ireg 17 cls_cnt 0 2006.145.03:10:30.99#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.03:10:30.99#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.03:10:30.99#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.03:10:31.01#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.03:10:31.05#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.03:10:31.05#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.03:10:31.05#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.03:10:31.05#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.03:10:31.05$vck44/vb=3,4 2006.145.03:10:31.05#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.03:10:31.05#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.03:10:31.05#ibcon#ireg 11 cls_cnt 2 2006.145.03:10:31.05#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.03:10:31.11#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.03:10:31.11#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.03:10:31.13#ibcon#[27=AT03-04\r\n] 2006.145.03:10:31.16#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.03:10:31.16#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.03:10:31.16#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.03:10:31.16#ibcon#ireg 7 cls_cnt 0 2006.145.03:10:31.16#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.03:10:31.28#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.03:10:31.28#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.03:10:31.30#ibcon#[27=USB\r\n] 2006.145.03:10:31.33#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.03:10:31.33#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.03:10:31.33#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.03:10:31.33#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.03:10:31.33$vck44/vblo=4,679.99 2006.145.03:10:31.33#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.03:10:31.33#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.03:10:31.33#ibcon#ireg 17 cls_cnt 0 2006.145.03:10:31.33#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.03:10:31.33#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.03:10:31.33#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.03:10:31.35#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.03:10:31.39#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.03:10:31.39#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.03:10:31.39#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.03:10:31.39#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.03:10:31.39$vck44/vb=4,4 2006.145.03:10:31.39#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.03:10:31.39#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.03:10:31.39#ibcon#ireg 11 cls_cnt 2 2006.145.03:10:31.39#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.03:10:31.45#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.03:10:31.45#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.03:10:31.47#ibcon#[27=AT04-04\r\n] 2006.145.03:10:31.50#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.03:10:31.50#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.03:10:31.50#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.03:10:31.50#ibcon#ireg 7 cls_cnt 0 2006.145.03:10:31.50#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.03:10:31.62#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.03:10:31.62#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.03:10:31.64#ibcon#[27=USB\r\n] 2006.145.03:10:31.67#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.03:10:31.67#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.03:10:31.67#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.03:10:31.67#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.03:10:31.67$vck44/vblo=5,709.99 2006.145.03:10:31.67#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.03:10:31.67#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.03:10:31.67#ibcon#ireg 17 cls_cnt 0 2006.145.03:10:31.67#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.03:10:31.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.03:10:31.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.03:10:31.69#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.03:10:31.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.03:10:31.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.03:10:31.73#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.03:10:31.73#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.03:10:31.73$vck44/vb=5,4 2006.145.03:10:31.73#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.03:10:31.73#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.03:10:31.73#ibcon#ireg 11 cls_cnt 2 2006.145.03:10:31.73#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.03:10:31.79#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.03:10:31.79#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.03:10:31.81#ibcon#[27=AT05-04\r\n] 2006.145.03:10:31.84#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.03:10:31.84#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.03:10:31.84#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.03:10:31.84#ibcon#ireg 7 cls_cnt 0 2006.145.03:10:31.84#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.03:10:31.96#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.03:10:31.96#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.03:10:31.98#ibcon#[27=USB\r\n] 2006.145.03:10:32.01#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.03:10:32.01#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.03:10:32.01#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.03:10:32.01#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.03:10:32.01$vck44/vblo=6,719.99 2006.145.03:10:32.01#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.03:10:32.01#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.03:10:32.01#ibcon#ireg 17 cls_cnt 0 2006.145.03:10:32.01#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.03:10:32.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.03:10:32.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.03:10:32.03#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.03:10:32.07#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.03:10:32.07#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.03:10:32.07#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.03:10:32.07#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.03:10:32.07$vck44/vb=6,4 2006.145.03:10:32.07#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.03:10:32.07#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.03:10:32.07#ibcon#ireg 11 cls_cnt 2 2006.145.03:10:32.07#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.03:10:32.13#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.03:10:32.13#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.03:10:32.15#ibcon#[27=AT06-04\r\n] 2006.145.03:10:32.18#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.03:10:32.18#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.03:10:32.18#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.03:10:32.18#ibcon#ireg 7 cls_cnt 0 2006.145.03:10:32.18#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.03:10:32.30#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.03:10:32.30#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.03:10:32.32#ibcon#[27=USB\r\n] 2006.145.03:10:32.35#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.03:10:32.35#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.03:10:32.35#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.03:10:32.35#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.03:10:32.35$vck44/vblo=7,734.99 2006.145.03:10:32.35#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.03:10:32.35#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.03:10:32.35#ibcon#ireg 17 cls_cnt 0 2006.145.03:10:32.35#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.03:10:32.35#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.03:10:32.35#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.03:10:32.37#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.03:10:32.41#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.03:10:32.41#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.03:10:32.41#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.03:10:32.41#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.03:10:32.41$vck44/vb=7,4 2006.145.03:10:32.41#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.03:10:32.41#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.03:10:32.41#ibcon#ireg 11 cls_cnt 2 2006.145.03:10:32.41#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.03:10:32.47#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.03:10:32.47#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.03:10:32.49#ibcon#[27=AT07-04\r\n] 2006.145.03:10:32.52#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.03:10:32.52#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.03:10:32.52#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.03:10:32.52#ibcon#ireg 7 cls_cnt 0 2006.145.03:10:32.52#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.03:10:32.55#abcon#<5=/05 4.1 7.4 19.95 651016.7\r\n> 2006.145.03:10:32.57#abcon#{5=INTERFACE CLEAR} 2006.145.03:10:32.63#abcon#[5=S1D000X0/0*\r\n] 2006.145.03:10:32.64#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.03:10:32.64#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.03:10:32.66#ibcon#[27=USB\r\n] 2006.145.03:10:32.69#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.03:10:32.69#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.03:10:32.69#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.03:10:32.69#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.03:10:32.69$vck44/vblo=8,744.99 2006.145.03:10:32.69#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.03:10:32.69#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.03:10:32.69#ibcon#ireg 17 cls_cnt 0 2006.145.03:10:32.69#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:10:32.69#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:10:32.69#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:10:32.71#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.03:10:32.75#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:10:32.75#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:10:32.75#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.03:10:32.75#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.03:10:32.75$vck44/vb=8,4 2006.145.03:10:32.75#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.03:10:32.75#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.03:10:32.75#ibcon#ireg 11 cls_cnt 2 2006.145.03:10:32.75#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.03:10:32.81#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.03:10:32.81#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.03:10:32.83#ibcon#[27=AT08-04\r\n] 2006.145.03:10:32.86#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.03:10:32.86#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.03:10:32.86#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.03:10:32.86#ibcon#ireg 7 cls_cnt 0 2006.145.03:10:32.86#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.03:10:32.98#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.03:10:32.98#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.03:10:33.00#ibcon#[27=USB\r\n] 2006.145.03:10:33.03#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.03:10:33.03#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.03:10:33.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.03:10:33.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.03:10:33.03$vck44/vabw=wide 2006.145.03:10:33.03#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.03:10:33.03#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.03:10:33.03#ibcon#ireg 8 cls_cnt 0 2006.145.03:10:33.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.03:10:33.03#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.03:10:33.03#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.03:10:33.05#ibcon#[25=BW32\r\n] 2006.145.03:10:33.08#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.03:10:33.08#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.03:10:33.08#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.03:10:33.08#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.03:10:33.08$vck44/vbbw=wide 2006.145.03:10:33.08#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.03:10:33.08#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.03:10:33.08#ibcon#ireg 8 cls_cnt 0 2006.145.03:10:33.08#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:10:33.15#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:10:33.15#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:10:33.17#ibcon#[27=BW32\r\n] 2006.145.03:10:33.20#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:10:33.20#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:10:33.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.03:10:33.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.03:10:33.20$setupk4/ifdk4 2006.145.03:10:33.20$ifdk4/lo= 2006.145.03:10:33.20$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.03:10:33.20$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.03:10:33.20$ifdk4/patch= 2006.145.03:10:33.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.03:10:33.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.03:10:33.21$setupk4/!*+20s 2006.145.03:10:42.72#abcon#<5=/05 4.1 7.4 19.95 631016.7\r\n> 2006.145.03:10:42.74#abcon#{5=INTERFACE CLEAR} 2006.145.03:10:42.80#abcon#[5=S1D000X0/0*\r\n] 2006.145.03:10:47.68$setupk4/"tpicd 2006.145.03:10:47.68$setupk4/echo=off 2006.145.03:10:47.68$setupk4/xlog=off 2006.145.03:10:47.68:!2006.145.03:12:43 2006.145.03:11:15.14#trakl#Source acquired 2006.145.03:11:15.14#flagr#flagr/antenna,acquired 2006.145.03:12:43.00:preob 2006.145.03:12:43.14/onsource/TRACKING 2006.145.03:12:43.14:!2006.145.03:12:53 2006.145.03:12:53.00:"tape 2006.145.03:12:53.00:"st=record 2006.145.03:12:53.00:data_valid=on 2006.145.03:12:53.00:midob 2006.145.03:12:54.13/onsource/TRACKING 2006.145.03:12:54.13/wx/19.98,1016.6,60 2006.145.03:12:54.33/cable/+6.5461E-03 2006.145.03:12:55.42/va/01,08,usb,yes,28,30 2006.145.03:12:55.42/va/02,07,usb,yes,30,31 2006.145.03:12:55.42/va/03,08,usb,yes,27,29 2006.145.03:12:55.42/va/04,07,usb,yes,31,33 2006.145.03:12:55.42/va/05,04,usb,yes,27,28 2006.145.03:12:55.42/va/06,04,usb,yes,31,30 2006.145.03:12:55.42/va/07,04,usb,yes,31,32 2006.145.03:12:55.42/va/08,04,usb,yes,26,32 2006.145.03:12:55.65/valo/01,524.99,yes,locked 2006.145.03:12:55.65/valo/02,534.99,yes,locked 2006.145.03:12:55.65/valo/03,564.99,yes,locked 2006.145.03:12:55.65/valo/04,624.99,yes,locked 2006.145.03:12:55.65/valo/05,734.99,yes,locked 2006.145.03:12:55.65/valo/06,814.99,yes,locked 2006.145.03:12:55.65/valo/07,864.99,yes,locked 2006.145.03:12:55.65/valo/08,884.99,yes,locked 2006.145.03:12:56.74/vb/01,03,usb,yes,36,34 2006.145.03:12:56.74/vb/02,04,usb,yes,32,31 2006.145.03:12:56.74/vb/03,04,usb,yes,28,31 2006.145.03:12:56.74/vb/04,04,usb,yes,33,32 2006.145.03:12:56.74/vb/05,04,usb,yes,25,28 2006.145.03:12:56.74/vb/06,04,usb,yes,30,26 2006.145.03:12:56.74/vb/07,04,usb,yes,30,29 2006.145.03:12:56.74/vb/08,04,usb,yes,27,31 2006.145.03:12:56.97/vblo/01,629.99,yes,locked 2006.145.03:12:56.97/vblo/02,634.99,yes,locked 2006.145.03:12:56.97/vblo/03,649.99,yes,locked 2006.145.03:12:56.97/vblo/04,679.99,yes,locked 2006.145.03:12:56.97/vblo/05,709.99,yes,locked 2006.145.03:12:56.97/vblo/06,719.99,yes,locked 2006.145.03:12:56.97/vblo/07,734.99,yes,locked 2006.145.03:12:56.97/vblo/08,744.99,yes,locked 2006.145.03:12:57.12/vabw/8 2006.145.03:12:57.27/vbbw/8 2006.145.03:12:57.36/xfe/off,on,14.0 2006.145.03:12:57.73/ifatt/23,28,28,28 2006.145.03:12:58.07/fmout-gps/S +4.7E-08 2006.145.03:12:58.15:!2006.145.03:16:03 2006.145.03:16:03.01:data_valid=off 2006.145.03:16:03.02:"et 2006.145.03:16:03.02:!+3s 2006.145.03:16:06.03:"tape 2006.145.03:16:06.04:postob 2006.145.03:16:06.13/cable/+6.5469E-03 2006.145.03:16:06.14/wx/19.96,1016.6,64 2006.145.03:16:06.20/fmout-gps/S +4.5E-08 2006.145.03:16:06.20:scan_name=145-0326,jd0605,310 2006.145.03:16:06.20:source=nrao150,035929.75,505750.2,2000.0,ccw 2006.145.03:16:08.14#flagr#flagr/antenna,new-source 2006.145.03:16:08.15:checkk5 2006.145.03:16:08.62/chk_autoobs//k5ts1/ autoobs is running! 2006.145.03:16:09.11/chk_autoobs//k5ts2/ autoobs is running! 2006.145.03:16:09.58/chk_autoobs//k5ts3/ autoobs is running! 2006.145.03:16:10.26/chk_autoobs//k5ts4/ autoobs is running! 2006.145.03:16:10.69/chk_obsdata//k5ts1/T1450312??a.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.03:16:11.19/chk_obsdata//k5ts2/T1450312??b.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.03:16:11.67/chk_obsdata//k5ts3/T1450312??c.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.03:16:12.17/chk_obsdata//k5ts4/T1450312??d.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.03:16:13.01/k5log//k5ts1_log_newline 2006.145.03:16:13.76/k5log//k5ts2_log_newline 2006.145.03:16:14.64/k5log//k5ts3_log_newline 2006.145.03:16:15.47/k5log//k5ts4_log_newline 2006.145.03:16:15.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.03:16:15.49:setupk4=1 2006.145.03:16:15.49$setupk4/echo=on 2006.145.03:16:15.49$setupk4/pcalon 2006.145.03:16:15.50$pcalon/"no phase cal control is implemented here 2006.145.03:16:15.50$setupk4/"tpicd=stop 2006.145.03:16:15.50$setupk4/"rec=synch_on 2006.145.03:16:15.50$setupk4/"rec_mode=128 2006.145.03:16:15.50$setupk4/!* 2006.145.03:16:15.50$setupk4/recpk4 2006.145.03:16:15.50$recpk4/recpatch= 2006.145.03:16:15.50$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.03:16:15.50$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.03:16:15.50$setupk4/vck44 2006.145.03:16:15.50$vck44/valo=1,524.99 2006.145.03:16:15.50#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.03:16:15.50#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.03:16:15.50#ibcon#ireg 17 cls_cnt 0 2006.145.03:16:15.50#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.03:16:15.50#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.03:16:15.50#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.03:16:15.51#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.03:16:15.56#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.03:16:15.56#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.03:16:15.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.03:16:15.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.03:16:15.56$vck44/va=1,8 2006.145.03:16:15.56#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.03:16:15.56#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.03:16:15.56#ibcon#ireg 11 cls_cnt 2 2006.145.03:16:15.56#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.03:16:15.56#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.03:16:15.56#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.03:16:15.58#ibcon#[25=AT01-08\r\n] 2006.145.03:16:15.61#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.03:16:15.61#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.03:16:15.61#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.03:16:15.61#ibcon#ireg 7 cls_cnt 0 2006.145.03:16:15.61#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.03:16:15.73#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.03:16:15.73#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.03:16:15.75#ibcon#[25=USB\r\n] 2006.145.03:16:15.78#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.03:16:15.78#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.03:16:15.78#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.03:16:15.78#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.03:16:15.78$vck44/valo=2,534.99 2006.145.03:16:15.78#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.03:16:15.78#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.03:16:15.78#ibcon#ireg 17 cls_cnt 0 2006.145.03:16:15.78#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.03:16:15.78#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.03:16:15.78#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.03:16:15.81#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.03:16:15.85#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.03:16:15.85#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.03:16:15.85#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.03:16:15.85#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.03:16:15.85$vck44/va=2,7 2006.145.03:16:15.85#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.03:16:15.85#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.03:16:15.85#ibcon#ireg 11 cls_cnt 2 2006.145.03:16:15.85#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.03:16:15.90#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.03:16:15.90#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.03:16:15.92#ibcon#[25=AT02-07\r\n] 2006.145.03:16:15.95#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.03:16:15.95#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.03:16:15.95#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.03:16:15.95#ibcon#ireg 7 cls_cnt 0 2006.145.03:16:15.95#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.03:16:16.08#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.03:16:16.08#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.03:16:16.09#ibcon#[25=USB\r\n] 2006.145.03:16:16.12#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.03:16:16.12#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.03:16:16.12#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.03:16:16.12#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.03:16:16.12$vck44/valo=3,564.99 2006.145.03:16:16.12#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.03:16:16.12#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.03:16:16.12#ibcon#ireg 17 cls_cnt 0 2006.145.03:16:16.12#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.03:16:16.12#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.03:16:16.12#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.03:16:16.14#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.03:16:16.18#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.03:16:16.18#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.03:16:16.18#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.03:16:16.18#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.03:16:16.18$vck44/va=3,8 2006.145.03:16:16.18#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.03:16:16.18#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.03:16:16.18#ibcon#ireg 11 cls_cnt 2 2006.145.03:16:16.18#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.03:16:16.24#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.03:16:16.24#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.03:16:16.26#ibcon#[25=AT03-08\r\n] 2006.145.03:16:16.29#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.03:16:16.29#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.03:16:16.29#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.03:16:16.29#ibcon#ireg 7 cls_cnt 0 2006.145.03:16:16.29#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.03:16:16.41#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.03:16:16.41#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.03:16:16.43#ibcon#[25=USB\r\n] 2006.145.03:16:16.46#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.03:16:16.46#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.03:16:16.46#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.03:16:16.46#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.03:16:16.46$vck44/valo=4,624.99 2006.145.03:16:16.46#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.03:16:16.46#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.03:16:16.46#ibcon#ireg 17 cls_cnt 0 2006.145.03:16:16.46#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.03:16:16.46#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.03:16:16.46#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.03:16:16.48#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.03:16:16.52#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.03:16:16.52#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.03:16:16.52#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.03:16:16.52#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.03:16:16.52$vck44/va=4,7 2006.145.03:16:16.52#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.03:16:16.52#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.03:16:16.52#ibcon#ireg 11 cls_cnt 2 2006.145.03:16:16.52#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.03:16:16.58#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.03:16:16.58#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.03:16:16.60#ibcon#[25=AT04-07\r\n] 2006.145.03:16:16.63#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.03:16:16.63#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.03:16:16.63#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.03:16:16.63#ibcon#ireg 7 cls_cnt 0 2006.145.03:16:16.63#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.03:16:16.75#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.03:16:16.75#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.03:16:16.77#ibcon#[25=USB\r\n] 2006.145.03:16:16.80#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.03:16:16.80#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.03:16:16.80#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.03:16:16.80#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.03:16:16.80$vck44/valo=5,734.99 2006.145.03:16:16.80#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.03:16:16.80#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.03:16:16.80#ibcon#ireg 17 cls_cnt 0 2006.145.03:16:16.80#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.03:16:16.80#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.03:16:16.80#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.03:16:16.82#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.03:16:16.86#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.03:16:16.86#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.03:16:16.86#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.03:16:16.86#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.03:16:16.86$vck44/va=5,4 2006.145.03:16:16.86#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.03:16:16.86#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.03:16:16.86#ibcon#ireg 11 cls_cnt 2 2006.145.03:16:16.86#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.03:16:16.92#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.03:16:16.92#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.03:16:16.94#ibcon#[25=AT05-04\r\n] 2006.145.03:16:16.97#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.03:16:16.97#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.03:16:16.97#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.03:16:16.97#ibcon#ireg 7 cls_cnt 0 2006.145.03:16:16.97#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.03:16:17.09#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.03:16:17.09#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.03:16:17.11#ibcon#[25=USB\r\n] 2006.145.03:16:17.14#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.03:16:17.14#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.03:16:17.14#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.03:16:17.14#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.03:16:17.14$vck44/valo=6,814.99 2006.145.03:16:17.14#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.03:16:17.14#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.03:16:17.14#ibcon#ireg 17 cls_cnt 0 2006.145.03:16:17.14#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.03:16:17.14#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.03:16:17.14#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.03:16:17.16#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.03:16:17.20#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.03:16:17.20#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.03:16:17.20#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.03:16:17.20#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.03:16:17.20$vck44/va=6,4 2006.145.03:16:17.20#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.03:16:17.20#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.03:16:17.20#ibcon#ireg 11 cls_cnt 2 2006.145.03:16:17.20#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.03:16:17.26#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.03:16:17.26#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.03:16:17.28#ibcon#[25=AT06-04\r\n] 2006.145.03:16:17.31#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.03:16:17.31#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.03:16:17.31#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.03:16:17.31#ibcon#ireg 7 cls_cnt 0 2006.145.03:16:17.31#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.03:16:17.43#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.03:16:17.43#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.03:16:17.45#ibcon#[25=USB\r\n] 2006.145.03:16:17.48#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.03:16:17.48#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.03:16:17.48#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.03:16:17.48#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.03:16:17.48$vck44/valo=7,864.99 2006.145.03:16:17.48#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.03:16:17.48#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.03:16:17.48#ibcon#ireg 17 cls_cnt 0 2006.145.03:16:17.48#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.03:16:17.48#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.03:16:17.48#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.03:16:17.50#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.03:16:17.54#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.03:16:17.54#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.03:16:17.54#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.03:16:17.54#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.03:16:17.54$vck44/va=7,4 2006.145.03:16:17.54#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.03:16:17.54#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.03:16:17.54#ibcon#ireg 11 cls_cnt 2 2006.145.03:16:17.54#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.03:16:17.60#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.03:16:17.60#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.03:16:17.62#ibcon#[25=AT07-04\r\n] 2006.145.03:16:17.65#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.03:16:17.65#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.03:16:17.65#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.03:16:17.65#ibcon#ireg 7 cls_cnt 0 2006.145.03:16:17.65#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.03:16:17.77#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.03:16:17.77#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.03:16:17.79#ibcon#[25=USB\r\n] 2006.145.03:16:17.82#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.03:16:17.82#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.03:16:17.82#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.03:16:17.82#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.03:16:17.82$vck44/valo=8,884.99 2006.145.03:16:17.82#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.03:16:17.82#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.03:16:17.82#ibcon#ireg 17 cls_cnt 0 2006.145.03:16:17.82#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.03:16:17.82#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.03:16:17.82#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.03:16:17.84#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.03:16:17.88#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.03:16:17.88#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.03:16:17.88#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.03:16:17.88#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.03:16:17.88$vck44/va=8,4 2006.145.03:16:17.88#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.03:16:17.88#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.03:16:17.88#ibcon#ireg 11 cls_cnt 2 2006.145.03:16:17.88#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.03:16:17.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.03:16:17.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.03:16:17.96#ibcon#[25=AT08-04\r\n] 2006.145.03:16:17.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.03:16:17.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.03:16:17.99#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.03:16:17.99#ibcon#ireg 7 cls_cnt 0 2006.145.03:16:17.99#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.03:16:18.11#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.03:16:18.11#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.03:16:18.13#ibcon#[25=USB\r\n] 2006.145.03:16:18.16#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.03:16:18.16#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.03:16:18.16#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.03:16:18.16#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.03:16:18.16$vck44/vblo=1,629.99 2006.145.03:16:18.16#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.03:16:18.16#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.03:16:18.16#ibcon#ireg 17 cls_cnt 0 2006.145.03:16:18.16#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.03:16:18.16#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.03:16:18.16#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.03:16:18.18#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.03:16:18.22#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.03:16:18.22#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.03:16:18.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.03:16:18.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.03:16:18.22$vck44/vb=1,3 2006.145.03:16:18.22#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.03:16:18.22#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.03:16:18.22#ibcon#ireg 11 cls_cnt 2 2006.145.03:16:18.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.03:16:18.22#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.03:16:18.22#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.03:16:18.24#ibcon#[27=AT01-03\r\n] 2006.145.03:16:18.27#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.03:16:18.27#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.03:16:18.27#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.03:16:18.27#ibcon#ireg 7 cls_cnt 0 2006.145.03:16:18.27#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.03:16:18.39#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.03:16:18.39#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.03:16:18.41#ibcon#[27=USB\r\n] 2006.145.03:16:18.43#abcon#<5=/06 4.5 8.2 19.96 651016.6\r\n> 2006.145.03:16:18.44#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.03:16:18.44#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.03:16:18.44#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.03:16:18.44#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.03:16:18.44$vck44/vblo=2,634.99 2006.145.03:16:18.44#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.03:16:18.44#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.03:16:18.44#ibcon#ireg 17 cls_cnt 0 2006.145.03:16:18.44#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:16:18.44#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:16:18.44#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:16:18.45#abcon#{5=INTERFACE CLEAR} 2006.145.03:16:18.46#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.03:16:18.50#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:16:18.50#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:16:18.50#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.03:16:18.50#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.03:16:18.50$vck44/vb=2,4 2006.145.03:16:18.50#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.03:16:18.50#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.03:16:18.50#ibcon#ireg 11 cls_cnt 2 2006.145.03:16:18.50#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.03:16:18.53#abcon#[5=S1D000X0/0*\r\n] 2006.145.03:16:18.56#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.03:16:18.56#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.03:16:18.58#ibcon#[27=AT02-04\r\n] 2006.145.03:16:18.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.03:16:18.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.03:16:18.61#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.03:16:18.61#ibcon#ireg 7 cls_cnt 0 2006.145.03:16:18.61#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.03:16:18.73#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.03:16:18.73#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.03:16:18.75#ibcon#[27=USB\r\n] 2006.145.03:16:18.78#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.03:16:18.78#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.03:16:18.78#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.03:16:18.78#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.03:16:18.78$vck44/vblo=3,649.99 2006.145.03:16:18.78#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.03:16:18.78#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.03:16:18.78#ibcon#ireg 17 cls_cnt 0 2006.145.03:16:18.78#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.03:16:18.78#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.03:16:18.78#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.03:16:18.80#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.03:16:18.84#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.03:16:18.84#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.03:16:18.84#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.03:16:18.84#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.03:16:18.84$vck44/vb=3,4 2006.145.03:16:18.84#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.03:16:18.84#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.03:16:18.84#ibcon#ireg 11 cls_cnt 2 2006.145.03:16:18.84#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.03:16:18.90#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.03:16:18.90#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.03:16:18.92#ibcon#[27=AT03-04\r\n] 2006.145.03:16:18.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.03:16:18.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.03:16:18.95#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.03:16:18.95#ibcon#ireg 7 cls_cnt 0 2006.145.03:16:18.95#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.03:16:19.07#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.03:16:19.07#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.03:16:19.09#ibcon#[27=USB\r\n] 2006.145.03:16:19.12#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.03:16:19.12#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.03:16:19.12#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.03:16:19.12#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.03:16:19.12$vck44/vblo=4,679.99 2006.145.03:16:19.12#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.03:16:19.12#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.03:16:19.12#ibcon#ireg 17 cls_cnt 0 2006.145.03:16:19.12#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.03:16:19.12#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.03:16:19.12#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.03:16:19.14#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.03:16:19.18#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.03:16:19.18#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.03:16:19.18#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.03:16:19.18#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.03:16:19.18$vck44/vb=4,4 2006.145.03:16:19.18#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.03:16:19.18#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.03:16:19.18#ibcon#ireg 11 cls_cnt 2 2006.145.03:16:19.18#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.03:16:19.24#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.03:16:19.24#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.03:16:19.26#ibcon#[27=AT04-04\r\n] 2006.145.03:16:19.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.03:16:19.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.03:16:19.29#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.03:16:19.29#ibcon#ireg 7 cls_cnt 0 2006.145.03:16:19.29#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.03:16:19.41#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.03:16:19.41#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.03:16:19.43#ibcon#[27=USB\r\n] 2006.145.03:16:19.46#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.03:16:19.46#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.03:16:19.46#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.03:16:19.46#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.03:16:19.46$vck44/vblo=5,709.99 2006.145.03:16:19.46#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.03:16:19.46#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.03:16:19.46#ibcon#ireg 17 cls_cnt 0 2006.145.03:16:19.46#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.03:16:19.46#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.03:16:19.46#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.03:16:19.48#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.03:16:19.52#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.03:16:19.52#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.03:16:19.52#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.03:16:19.52#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.03:16:19.52$vck44/vb=5,4 2006.145.03:16:19.52#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.03:16:19.52#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.03:16:19.52#ibcon#ireg 11 cls_cnt 2 2006.145.03:16:19.52#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.03:16:19.58#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.03:16:19.58#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.03:16:19.60#ibcon#[27=AT05-04\r\n] 2006.145.03:16:19.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.03:16:19.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.03:16:19.63#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.03:16:19.63#ibcon#ireg 7 cls_cnt 0 2006.145.03:16:19.63#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.03:16:19.75#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.03:16:19.75#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.03:16:19.77#ibcon#[27=USB\r\n] 2006.145.03:16:19.80#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.03:16:19.80#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.03:16:19.80#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.03:16:19.80#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.03:16:19.80$vck44/vblo=6,719.99 2006.145.03:16:19.80#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.03:16:19.80#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.03:16:19.80#ibcon#ireg 17 cls_cnt 0 2006.145.03:16:19.80#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.03:16:19.80#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.03:16:19.80#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.03:16:19.82#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.03:16:19.86#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.03:16:19.86#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.03:16:19.86#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.03:16:19.86#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.03:16:19.86$vck44/vb=6,4 2006.145.03:16:19.86#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.03:16:19.86#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.03:16:19.86#ibcon#ireg 11 cls_cnt 2 2006.145.03:16:19.86#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.03:16:19.92#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.03:16:19.92#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.03:16:19.94#ibcon#[27=AT06-04\r\n] 2006.145.03:16:19.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.03:16:19.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.03:16:19.97#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.03:16:19.97#ibcon#ireg 7 cls_cnt 0 2006.145.03:16:19.97#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.03:16:20.09#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.03:16:20.09#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.03:16:20.11#ibcon#[27=USB\r\n] 2006.145.03:16:20.14#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.03:16:20.14#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.03:16:20.14#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.03:16:20.14#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.03:16:20.14$vck44/vblo=7,734.99 2006.145.03:16:20.14#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.03:16:20.14#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.03:16:20.14#ibcon#ireg 17 cls_cnt 0 2006.145.03:16:20.14#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.03:16:20.14#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.03:16:20.14#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.03:16:20.16#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.03:16:20.20#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.03:16:20.20#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.03:16:20.20#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.03:16:20.20#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.03:16:20.20$vck44/vb=7,4 2006.145.03:16:20.20#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.03:16:20.20#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.03:16:20.20#ibcon#ireg 11 cls_cnt 2 2006.145.03:16:20.20#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.03:16:20.26#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.03:16:20.26#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.03:16:20.28#ibcon#[27=AT07-04\r\n] 2006.145.03:16:20.31#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.03:16:20.31#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.03:16:20.31#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.03:16:20.31#ibcon#ireg 7 cls_cnt 0 2006.145.03:16:20.31#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.03:16:20.43#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.03:16:20.43#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.03:16:20.45#ibcon#[27=USB\r\n] 2006.145.03:16:20.48#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.03:16:20.48#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.03:16:20.48#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.03:16:20.48#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.03:16:20.48$vck44/vblo=8,744.99 2006.145.03:16:20.48#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.03:16:20.48#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.03:16:20.48#ibcon#ireg 17 cls_cnt 0 2006.145.03:16:20.48#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.03:16:20.48#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.03:16:20.48#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.03:16:20.50#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.03:16:20.54#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.03:16:20.54#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.03:16:20.54#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.03:16:20.54#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.03:16:20.54$vck44/vb=8,4 2006.145.03:16:20.54#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.03:16:20.54#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.03:16:20.54#ibcon#ireg 11 cls_cnt 2 2006.145.03:16:20.54#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.03:16:20.60#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.03:16:20.60#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.03:16:20.62#ibcon#[27=AT08-04\r\n] 2006.145.03:16:20.65#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.03:16:20.65#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.03:16:20.65#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.03:16:20.65#ibcon#ireg 7 cls_cnt 0 2006.145.03:16:20.65#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.03:16:20.77#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.03:16:20.77#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.03:16:20.79#ibcon#[27=USB\r\n] 2006.145.03:16:20.82#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.03:16:20.82#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.03:16:20.82#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.03:16:20.82#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.03:16:20.82$vck44/vabw=wide 2006.145.03:16:20.82#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.03:16:20.82#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.03:16:20.82#ibcon#ireg 8 cls_cnt 0 2006.145.03:16:20.82#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.03:16:20.82#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.03:16:20.82#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.03:16:20.84#ibcon#[25=BW32\r\n] 2006.145.03:16:20.87#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.03:16:20.87#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.03:16:20.87#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.03:16:20.87#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.03:16:20.87$vck44/vbbw=wide 2006.145.03:16:20.87#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.03:16:20.87#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.03:16:20.87#ibcon#ireg 8 cls_cnt 0 2006.145.03:16:20.87#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.03:16:20.94#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.03:16:20.94#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.03:16:20.96#ibcon#[27=BW32\r\n] 2006.145.03:16:20.99#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.03:16:20.99#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.03:16:20.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.03:16:20.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.03:16:20.99$setupk4/ifdk4 2006.145.03:16:20.99$ifdk4/lo= 2006.145.03:16:20.99$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.03:16:20.99$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.03:16:20.99$ifdk4/patch= 2006.145.03:16:20.99$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.03:16:20.99$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.03:16:20.99$setupk4/!*+20s 2006.145.03:16:28.62#abcon#<5=/06 4.5 8.2 19.95 651016.6\r\n> 2006.145.03:16:28.64#abcon#{5=INTERFACE CLEAR} 2006.145.03:16:28.70#abcon#[5=S1D000X0/0*\r\n] 2006.145.03:16:29.14#trakl#Source acquired 2006.145.03:16:30.14#flagr#flagr/antenna,acquired 2006.145.03:16:35.51$setupk4/"tpicd 2006.145.03:16:35.51$setupk4/echo=off 2006.145.03:16:35.51$setupk4/xlog=off 2006.145.03:16:35.51:!2006.145.03:26:23 2006.145.03:26:23.00:preob 2006.145.03:26:23.14/onsource/TRACKING 2006.145.03:26:23.14:!2006.145.03:26:33 2006.145.03:26:33.00:"tape 2006.145.03:26:33.00:"st=record 2006.145.03:26:33.00:data_valid=on 2006.145.03:26:33.00:midob 2006.145.03:26:33.14/onsource/TRACKING 2006.145.03:26:33.14/wx/20.00,1016.8,64 2006.145.03:26:33.24/cable/+6.5457E-03 2006.145.03:26:34.33/va/01,08,usb,yes,28,30 2006.145.03:26:34.33/va/02,07,usb,yes,30,31 2006.145.03:26:34.33/va/03,08,usb,yes,27,29 2006.145.03:26:34.33/va/04,07,usb,yes,31,33 2006.145.03:26:34.33/va/05,04,usb,yes,27,28 2006.145.03:26:34.33/va/06,04,usb,yes,31,30 2006.145.03:26:34.33/va/07,04,usb,yes,31,32 2006.145.03:26:34.33/va/08,04,usb,yes,26,32 2006.145.03:26:34.56/valo/01,524.99,yes,locked 2006.145.03:26:34.56/valo/02,534.99,yes,locked 2006.145.03:26:34.56/valo/03,564.99,yes,locked 2006.145.03:26:34.56/valo/04,624.99,yes,locked 2006.145.03:26:34.56/valo/05,734.99,yes,locked 2006.145.03:26:34.56/valo/06,814.99,yes,locked 2006.145.03:26:34.56/valo/07,864.99,yes,locked 2006.145.03:26:34.56/valo/08,884.99,yes,locked 2006.145.03:26:35.65/vb/01,03,usb,yes,36,33 2006.145.03:26:35.65/vb/02,04,usb,yes,31,31 2006.145.03:26:35.65/vb/03,04,usb,yes,28,31 2006.145.03:26:35.65/vb/04,04,usb,yes,32,31 2006.145.03:26:35.65/vb/05,04,usb,yes,25,28 2006.145.03:26:35.65/vb/06,04,usb,yes,30,26 2006.145.03:26:35.65/vb/07,04,usb,yes,29,29 2006.145.03:26:35.65/vb/08,04,usb,yes,27,30 2006.145.03:26:35.88/vblo/01,629.99,yes,locked 2006.145.03:26:35.88/vblo/02,634.99,yes,locked 2006.145.03:26:35.88/vblo/03,649.99,yes,locked 2006.145.03:26:35.88/vblo/04,679.99,yes,locked 2006.145.03:26:35.88/vblo/05,709.99,yes,locked 2006.145.03:26:35.88/vblo/06,719.99,yes,locked 2006.145.03:26:35.88/vblo/07,734.99,yes,locked 2006.145.03:26:35.88/vblo/08,744.99,yes,locked 2006.145.03:26:36.03/vabw/8 2006.145.03:26:36.18/vbbw/8 2006.145.03:26:36.27/xfe/off,on,14.7 2006.145.03:26:36.65/ifatt/23,28,28,28 2006.145.03:26:37.07/fmout-gps/S +4.7E-08 2006.145.03:26:37.13:!2006.145.03:31:43 2006.145.03:31:43.00:data_valid=off 2006.145.03:31:43.00:"et 2006.145.03:31:43.01:!+3s 2006.145.03:31:46.02:"tape 2006.145.03:31:46.02:postob 2006.145.03:31:46.25/cable/+6.5457E-03 2006.145.03:31:46.25/wx/20.02,1016.8,62 2006.145.03:31:47.07/fmout-gps/S +4.9E-08 2006.145.03:31:47.07:scan_name=145-0336,jd0605,40 2006.145.03:31:47.07:source=4c39.25,092703.01,390220.9,2000.0,cw 2006.145.03:31:48.14#flagr#flagr/antenna,new-source 2006.145.03:31:48.14:checkk5 2006.145.03:31:48.62/chk_autoobs//k5ts1/ autoobs is running! 2006.145.03:31:49.09/chk_autoobs//k5ts2/ autoobs is running! 2006.145.03:31:49.55/chk_autoobs//k5ts3/ autoobs is running! 2006.145.03:31:49.98/chk_autoobs//k5ts4/ autoobs is running! 2006.145.03:31:50.41/chk_obsdata//k5ts1/T1450326??a.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.145.03:31:50.88/chk_obsdata//k5ts2/T1450326??b.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.145.03:31:51.33/chk_obsdata//k5ts3/T1450326??c.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.145.03:31:51.79/chk_obsdata//k5ts4/T1450326??d.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.145.03:31:52.87/k5log//k5ts1_log_newline 2006.145.03:31:53.92/k5log//k5ts2_log_newline 2006.145.03:31:54.69/k5log//k5ts3_log_newline 2006.145.03:31:55.49/k5log//k5ts4_log_newline 2006.145.03:31:55.51/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.03:31:55.51:setupk4=1 2006.145.03:31:55.51$setupk4/echo=on 2006.145.03:31:55.51$setupk4/pcalon 2006.145.03:31:55.51$pcalon/"no phase cal control is implemented here 2006.145.03:31:55.51$setupk4/"tpicd=stop 2006.145.03:31:55.51$setupk4/"rec=synch_on 2006.145.03:31:55.51$setupk4/"rec_mode=128 2006.145.03:31:55.51$setupk4/!* 2006.145.03:31:55.51$setupk4/recpk4 2006.145.03:31:55.51$recpk4/recpatch= 2006.145.03:31:55.52$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.03:31:55.52$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.03:31:55.52$setupk4/vck44 2006.145.03:31:55.52$vck44/valo=1,524.99 2006.145.03:31:55.52#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.03:31:55.52#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.03:31:55.52#ibcon#ireg 17 cls_cnt 0 2006.145.03:31:55.52#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:31:55.52#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:31:55.52#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:31:55.56#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.03:31:55.60#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:31:55.60#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:31:55.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.03:31:55.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.03:31:55.60$vck44/va=1,8 2006.145.03:31:55.60#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.03:31:55.60#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.03:31:55.60#ibcon#ireg 11 cls_cnt 2 2006.145.03:31:55.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:31:55.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:31:55.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:31:55.62#ibcon#[25=AT01-08\r\n] 2006.145.03:31:55.65#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:31:55.65#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:31:55.65#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.03:31:55.65#ibcon#ireg 7 cls_cnt 0 2006.145.03:31:55.65#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:31:55.77#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:31:55.77#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:31:55.79#ibcon#[25=USB\r\n] 2006.145.03:31:55.82#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:31:55.82#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:31:55.82#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.03:31:55.82#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.03:31:55.82$vck44/valo=2,534.99 2006.145.03:31:55.82#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.03:31:55.82#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.03:31:55.82#ibcon#ireg 17 cls_cnt 0 2006.145.03:31:55.82#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:31:55.82#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:31:55.82#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:31:55.85#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.03:31:55.89#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:31:55.89#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:31:55.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.03:31:55.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.03:31:55.89$vck44/va=2,7 2006.145.03:31:55.89#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.03:31:55.89#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.03:31:55.89#ibcon#ireg 11 cls_cnt 2 2006.145.03:31:55.89#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:31:55.94#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:31:55.94#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:31:55.96#ibcon#[25=AT02-07\r\n] 2006.145.03:31:55.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:31:55.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:31:55.99#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.03:31:55.99#ibcon#ireg 7 cls_cnt 0 2006.145.03:31:55.99#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:31:56.11#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:31:56.11#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:31:56.13#ibcon#[25=USB\r\n] 2006.145.03:31:56.16#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:31:56.16#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:31:56.16#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.03:31:56.16#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.03:31:56.16$vck44/valo=3,564.99 2006.145.03:31:56.16#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.03:31:56.16#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.03:31:56.16#ibcon#ireg 17 cls_cnt 0 2006.145.03:31:56.16#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:31:56.16#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:31:56.16#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:31:56.18#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.03:31:56.22#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:31:56.22#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:31:56.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.03:31:56.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.03:31:56.22$vck44/va=3,8 2006.145.03:31:56.22#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.03:31:56.22#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.03:31:56.22#ibcon#ireg 11 cls_cnt 2 2006.145.03:31:56.22#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.03:31:56.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.03:31:56.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.03:31:56.30#ibcon#[25=AT03-08\r\n] 2006.145.03:31:56.33#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.03:31:56.33#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.03:31:56.33#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.03:31:56.33#ibcon#ireg 7 cls_cnt 0 2006.145.03:31:56.33#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.03:31:56.45#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.03:31:56.45#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.03:31:56.47#ibcon#[25=USB\r\n] 2006.145.03:31:56.50#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.03:31:56.50#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.03:31:56.50#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.03:31:56.50#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.03:31:56.50$vck44/valo=4,624.99 2006.145.03:31:56.50#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.03:31:56.50#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.03:31:56.50#ibcon#ireg 17 cls_cnt 0 2006.145.03:31:56.50#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:31:56.50#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:31:56.50#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:31:56.52#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.03:31:56.56#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:31:56.56#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:31:56.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.03:31:56.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.03:31:56.56$vck44/va=4,7 2006.145.03:31:56.56#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.03:31:56.56#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.03:31:56.56#ibcon#ireg 11 cls_cnt 2 2006.145.03:31:56.56#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:31:56.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:31:56.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:31:56.64#ibcon#[25=AT04-07\r\n] 2006.145.03:31:56.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:31:56.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:31:56.67#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.03:31:56.67#ibcon#ireg 7 cls_cnt 0 2006.145.03:31:56.67#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:31:56.79#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:31:56.79#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:31:56.81#ibcon#[25=USB\r\n] 2006.145.03:31:56.84#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:31:56.84#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:31:56.84#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.03:31:56.84#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.03:31:56.84$vck44/valo=5,734.99 2006.145.03:31:56.84#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.03:31:56.84#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.03:31:56.84#ibcon#ireg 17 cls_cnt 0 2006.145.03:31:56.84#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:31:56.84#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:31:56.84#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:31:56.86#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.03:31:56.90#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:31:56.90#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:31:56.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.03:31:56.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.03:31:56.90$vck44/va=5,4 2006.145.03:31:56.90#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.03:31:56.90#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.03:31:56.90#ibcon#ireg 11 cls_cnt 2 2006.145.03:31:56.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:31:56.96#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:31:56.96#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:31:56.98#ibcon#[25=AT05-04\r\n] 2006.145.03:31:57.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:31:57.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:31:57.01#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.03:31:57.01#ibcon#ireg 7 cls_cnt 0 2006.145.03:31:57.01#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:31:57.13#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:31:57.13#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:31:57.15#ibcon#[25=USB\r\n] 2006.145.03:31:57.18#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:31:57.18#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:31:57.18#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.03:31:57.18#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.03:31:57.18$vck44/valo=6,814.99 2006.145.03:31:57.18#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.03:31:57.18#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.03:31:57.18#ibcon#ireg 17 cls_cnt 0 2006.145.03:31:57.18#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:31:57.18#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:31:57.18#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:31:57.20#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.03:31:57.24#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:31:57.24#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:31:57.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.03:31:57.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.03:31:57.24$vck44/va=6,4 2006.145.03:31:57.24#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.03:31:57.24#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.03:31:57.24#ibcon#ireg 11 cls_cnt 2 2006.145.03:31:57.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:31:57.30#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:31:57.30#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:31:57.32#ibcon#[25=AT06-04\r\n] 2006.145.03:31:57.35#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:31:57.35#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:31:57.35#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.03:31:57.35#ibcon#ireg 7 cls_cnt 0 2006.145.03:31:57.35#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:31:57.47#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:31:57.47#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:31:57.49#ibcon#[25=USB\r\n] 2006.145.03:31:57.52#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:31:57.52#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:31:57.52#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.03:31:57.52#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.03:31:57.52$vck44/valo=7,864.99 2006.145.03:31:57.52#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.03:31:57.52#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.03:31:57.52#ibcon#ireg 17 cls_cnt 0 2006.145.03:31:57.52#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.03:31:57.52#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.03:31:57.52#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.03:31:57.54#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.03:31:57.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.03:31:57.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.03:31:57.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.03:31:57.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.03:31:57.58$vck44/va=7,4 2006.145.03:31:57.58#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.03:31:57.58#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.03:31:57.58#ibcon#ireg 11 cls_cnt 2 2006.145.03:31:57.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.03:31:57.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.03:31:57.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.03:31:57.66#ibcon#[25=AT07-04\r\n] 2006.145.03:31:57.69#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.03:31:57.69#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.03:31:57.69#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.03:31:57.69#ibcon#ireg 7 cls_cnt 0 2006.145.03:31:57.69#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.03:31:57.81#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.03:31:57.81#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.03:31:57.83#ibcon#[25=USB\r\n] 2006.145.03:31:57.86#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.03:31:57.86#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.03:31:57.86#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.03:31:57.86#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.03:31:57.86$vck44/valo=8,884.99 2006.145.03:31:57.86#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.03:31:57.86#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.03:31:57.86#ibcon#ireg 17 cls_cnt 0 2006.145.03:31:57.86#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:31:57.86#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:31:57.86#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:31:57.88#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.03:31:57.92#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:31:57.92#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:31:57.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.03:31:57.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.03:31:57.92$vck44/va=8,4 2006.145.03:31:57.92#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.03:31:57.92#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.03:31:57.92#ibcon#ireg 11 cls_cnt 2 2006.145.03:31:57.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.03:31:57.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.03:31:57.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.03:31:58.00#ibcon#[25=AT08-04\r\n] 2006.145.03:31:58.03#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.03:31:58.03#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.03:31:58.03#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.03:31:58.03#ibcon#ireg 7 cls_cnt 0 2006.145.03:31:58.03#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.03:31:58.15#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.03:31:58.15#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.03:31:58.17#ibcon#[25=USB\r\n] 2006.145.03:31:58.20#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.03:31:58.20#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.03:31:58.20#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.03:31:58.20#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.03:31:58.20$vck44/vblo=1,629.99 2006.145.03:31:58.20#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.03:31:58.20#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.03:31:58.20#ibcon#ireg 17 cls_cnt 0 2006.145.03:31:58.20#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:31:58.20#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:31:58.20#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:31:58.22#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.03:31:58.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:31:58.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:31:58.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.03:31:58.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.03:31:58.26$vck44/vb=1,3 2006.145.03:31:58.26#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.03:31:58.26#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.03:31:58.26#ibcon#ireg 11 cls_cnt 2 2006.145.03:31:58.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.03:31:58.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.03:31:58.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.03:31:58.28#ibcon#[27=AT01-03\r\n] 2006.145.03:31:58.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.03:31:58.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.03:31:58.31#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.03:31:58.31#ibcon#ireg 7 cls_cnt 0 2006.145.03:31:58.31#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.03:31:58.43#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.03:31:58.43#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.03:31:58.45#ibcon#[27=USB\r\n] 2006.145.03:31:58.48#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.03:31:58.48#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.03:31:58.48#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.03:31:58.48#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.03:31:58.48$vck44/vblo=2,634.99 2006.145.03:31:58.48#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.03:31:58.48#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.03:31:58.48#ibcon#ireg 17 cls_cnt 0 2006.145.03:31:58.48#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:31:58.48#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:31:58.48#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:31:58.50#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.03:31:58.54#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:31:58.54#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:31:58.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.03:31:58.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.03:31:58.54$vck44/vb=2,4 2006.145.03:31:58.54#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.03:31:58.54#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.03:31:58.54#ibcon#ireg 11 cls_cnt 2 2006.145.03:31:58.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:31:58.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:31:58.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:31:58.62#ibcon#[27=AT02-04\r\n] 2006.145.03:31:58.65#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:31:58.65#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:31:58.65#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.03:31:58.65#ibcon#ireg 7 cls_cnt 0 2006.145.03:31:58.65#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:31:58.77#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:31:58.77#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:31:58.79#ibcon#[27=USB\r\n] 2006.145.03:31:58.82#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:31:58.82#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:31:58.82#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.03:31:58.82#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.03:31:58.82$vck44/vblo=3,649.99 2006.145.03:31:58.82#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.03:31:58.82#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.03:31:58.82#ibcon#ireg 17 cls_cnt 0 2006.145.03:31:58.82#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:31:58.82#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:31:58.82#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:31:58.84#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.03:31:58.88#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:31:58.88#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:31:58.88#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.03:31:58.88#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.03:31:58.88$vck44/vb=3,4 2006.145.03:31:58.88#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.03:31:58.88#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.03:31:58.88#ibcon#ireg 11 cls_cnt 2 2006.145.03:31:58.88#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:31:58.94#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:31:58.94#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:31:58.96#ibcon#[27=AT03-04\r\n] 2006.145.03:31:58.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:31:58.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:31:58.99#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.03:31:58.99#ibcon#ireg 7 cls_cnt 0 2006.145.03:31:58.99#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:31:59.11#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:31:59.11#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:31:59.13#ibcon#[27=USB\r\n] 2006.145.03:31:59.16#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:31:59.16#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:31:59.16#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.03:31:59.16#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.03:31:59.16$vck44/vblo=4,679.99 2006.145.03:31:59.16#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.03:31:59.16#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.03:31:59.16#ibcon#ireg 17 cls_cnt 0 2006.145.03:31:59.16#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:31:59.16#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:31:59.16#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:31:59.18#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.03:31:59.22#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:31:59.22#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:31:59.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.03:31:59.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.03:31:59.22$vck44/vb=4,4 2006.145.03:31:59.22#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.03:31:59.22#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.03:31:59.22#ibcon#ireg 11 cls_cnt 2 2006.145.03:31:59.22#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.03:31:59.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.03:31:59.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.03:31:59.30#ibcon#[27=AT04-04\r\n] 2006.145.03:31:59.33#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.03:31:59.33#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.03:31:59.33#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.03:31:59.33#ibcon#ireg 7 cls_cnt 0 2006.145.03:31:59.33#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.03:31:59.45#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.03:31:59.45#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.03:31:59.47#ibcon#[27=USB\r\n] 2006.145.03:31:59.50#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.03:31:59.50#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.03:31:59.50#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.03:31:59.50#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.03:31:59.50$vck44/vblo=5,709.99 2006.145.03:31:59.50#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.03:31:59.50#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.03:31:59.50#ibcon#ireg 17 cls_cnt 0 2006.145.03:31:59.50#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:31:59.50#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:31:59.50#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:31:59.52#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.03:31:59.56#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:31:59.56#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:31:59.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.03:31:59.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.03:31:59.56$vck44/vb=5,4 2006.145.03:31:59.56#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.03:31:59.56#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.03:31:59.56#ibcon#ireg 11 cls_cnt 2 2006.145.03:31:59.56#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:31:59.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:31:59.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:31:59.64#ibcon#[27=AT05-04\r\n] 2006.145.03:31:59.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:31:59.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:31:59.67#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.03:31:59.67#ibcon#ireg 7 cls_cnt 0 2006.145.03:31:59.67#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:31:59.79#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:31:59.79#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:31:59.81#ibcon#[27=USB\r\n] 2006.145.03:31:59.84#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:31:59.84#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:31:59.84#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.03:31:59.84#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.03:31:59.84$vck44/vblo=6,719.99 2006.145.03:31:59.84#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.03:31:59.84#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.03:31:59.84#ibcon#ireg 17 cls_cnt 0 2006.145.03:31:59.84#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:31:59.84#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:31:59.84#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:31:59.86#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.03:31:59.90#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:31:59.90#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:31:59.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.03:31:59.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.03:31:59.90$vck44/vb=6,4 2006.145.03:31:59.90#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.03:31:59.90#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.03:31:59.90#ibcon#ireg 11 cls_cnt 2 2006.145.03:31:59.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:31:59.96#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:31:59.96#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:31:59.98#ibcon#[27=AT06-04\r\n] 2006.145.03:32:00.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:32:00.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:32:00.01#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.03:32:00.01#ibcon#ireg 7 cls_cnt 0 2006.145.03:32:00.01#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:32:00.13#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:32:00.13#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:32:00.15#ibcon#[27=USB\r\n] 2006.145.03:32:00.18#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:32:00.18#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:32:00.18#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.03:32:00.18#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.03:32:00.18$vck44/vblo=7,734.99 2006.145.03:32:00.18#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.03:32:00.18#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.03:32:00.18#ibcon#ireg 17 cls_cnt 0 2006.145.03:32:00.18#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:32:00.18#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:32:00.18#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:32:00.20#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.03:32:00.24#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:32:00.24#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:32:00.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.03:32:00.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.03:32:00.24$vck44/vb=7,4 2006.145.03:32:00.24#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.03:32:00.24#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.03:32:00.24#ibcon#ireg 11 cls_cnt 2 2006.145.03:32:00.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:32:00.30#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:32:00.30#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:32:00.32#ibcon#[27=AT07-04\r\n] 2006.145.03:32:00.35#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:32:00.35#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:32:00.35#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.03:32:00.35#ibcon#ireg 7 cls_cnt 0 2006.145.03:32:00.35#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:32:00.47#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:32:00.47#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:32:00.49#ibcon#[27=USB\r\n] 2006.145.03:32:00.52#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:32:00.52#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:32:00.52#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.03:32:00.52#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.03:32:00.52$vck44/vblo=8,744.99 2006.145.03:32:00.52#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.03:32:00.52#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.03:32:00.52#ibcon#ireg 17 cls_cnt 0 2006.145.03:32:00.52#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.03:32:00.52#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.03:32:00.52#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.03:32:00.54#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.03:32:00.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.03:32:00.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.03:32:00.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.03:32:00.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.03:32:00.58$vck44/vb=8,4 2006.145.03:32:00.58#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.03:32:00.58#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.03:32:00.58#ibcon#ireg 11 cls_cnt 2 2006.145.03:32:00.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.03:32:00.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.03:32:00.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.03:32:00.66#ibcon#[27=AT08-04\r\n] 2006.145.03:32:00.69#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.03:32:00.69#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.03:32:00.69#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.03:32:00.69#ibcon#ireg 7 cls_cnt 0 2006.145.03:32:00.69#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.03:32:00.81#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.03:32:00.81#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.03:32:00.83#ibcon#[27=USB\r\n] 2006.145.03:32:00.86#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.03:32:00.86#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.03:32:00.86#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.03:32:00.86#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.03:32:00.86$vck44/vabw=wide 2006.145.03:32:00.86#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.03:32:00.86#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.03:32:00.86#ibcon#ireg 8 cls_cnt 0 2006.145.03:32:00.86#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:32:00.86#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:32:00.86#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:32:00.88#ibcon#[25=BW32\r\n] 2006.145.03:32:00.91#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:32:00.91#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:32:00.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.03:32:00.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.03:32:00.91$vck44/vbbw=wide 2006.145.03:32:00.91#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.03:32:00.91#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.03:32:00.91#ibcon#ireg 8 cls_cnt 0 2006.145.03:32:00.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.03:32:00.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.03:32:00.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.03:32:01.00#ibcon#[27=BW32\r\n] 2006.145.03:32:01.03#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.03:32:01.03#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.03:32:01.03#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.03:32:01.03#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.03:32:01.03$setupk4/ifdk4 2006.145.03:32:01.03$ifdk4/lo= 2006.145.03:32:01.03$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.03:32:01.03$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.03:32:01.03$ifdk4/patch= 2006.145.03:32:01.03$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.03:32:01.03$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.03:32:01.03$setupk4/!*+20s 2006.145.03:32:04.59#abcon#<5=/05 4.1 8.0 20.03 621016.8\r\n> 2006.145.03:32:04.61#abcon#{5=INTERFACE CLEAR} 2006.145.03:32:04.67#abcon#[5=S1D000X0/0*\r\n] 2006.145.03:32:14.76#abcon#<5=/05 4.1 8.0 20.03 601016.8\r\n> 2006.145.03:32:14.78#abcon#{5=INTERFACE CLEAR} 2006.145.03:32:14.86#abcon#[5=S1D000X0/0*\r\n] 2006.145.03:32:15.52$setupk4/"tpicd 2006.145.03:32:15.52$setupk4/echo=off 2006.145.03:32:15.52$setupk4/xlog=off 2006.145.03:32:15.52:!2006.145.03:35:52 2006.145.03:32:28.14#trakl#Source acquired 2006.145.03:32:28.14#flagr#flagr/antenna,acquired 2006.145.03:35:52.00:preob 2006.145.03:35:53.14/onsource/TRACKING 2006.145.03:35:53.14:!2006.145.03:36:02 2006.145.03:36:02.00:"tape 2006.145.03:36:02.00:"st=record 2006.145.03:36:02.00:data_valid=on 2006.145.03:36:02.00:midob 2006.145.03:36:02.14/onsource/TRACKING 2006.145.03:36:02.14/wx/20.03,1017.0,60 2006.145.03:36:02.30/cable/+6.5447E-03 2006.145.03:36:03.39/va/01,08,usb,yes,29,31 2006.145.03:36:03.39/va/02,07,usb,yes,31,32 2006.145.03:36:03.39/va/03,08,usb,yes,28,29 2006.145.03:36:03.39/va/04,07,usb,yes,32,34 2006.145.03:36:03.39/va/05,04,usb,yes,28,28 2006.145.03:36:03.39/va/06,04,usb,yes,31,31 2006.145.03:36:03.39/va/07,04,usb,yes,32,33 2006.145.03:36:03.39/va/08,04,usb,yes,27,33 2006.145.03:36:03.62/valo/01,524.99,yes,locked 2006.145.03:36:03.62/valo/02,534.99,yes,locked 2006.145.03:36:03.62/valo/03,564.99,yes,locked 2006.145.03:36:03.62/valo/04,624.99,yes,locked 2006.145.03:36:03.62/valo/05,734.99,yes,locked 2006.145.03:36:03.62/valo/06,814.99,yes,locked 2006.145.03:36:03.62/valo/07,864.99,yes,locked 2006.145.03:36:03.62/valo/08,884.99,yes,locked 2006.145.03:36:04.71/vb/01,03,usb,yes,36,33 2006.145.03:36:04.71/vb/02,04,usb,yes,31,31 2006.145.03:36:04.71/vb/03,04,usb,yes,28,31 2006.145.03:36:04.71/vb/04,04,usb,yes,33,31 2006.145.03:36:04.71/vb/05,04,usb,yes,25,28 2006.145.03:36:04.71/vb/06,04,usb,yes,30,26 2006.145.03:36:04.71/vb/07,04,usb,yes,29,29 2006.145.03:36:04.71/vb/08,04,usb,yes,27,30 2006.145.03:36:04.94/vblo/01,629.99,yes,locked 2006.145.03:36:04.94/vblo/02,634.99,yes,locked 2006.145.03:36:04.94/vblo/03,649.99,yes,locked 2006.145.03:36:04.94/vblo/04,679.99,yes,locked 2006.145.03:36:04.94/vblo/05,709.99,yes,locked 2006.145.03:36:04.94/vblo/06,719.99,yes,locked 2006.145.03:36:04.94/vblo/07,734.99,yes,locked 2006.145.03:36:04.94/vblo/08,744.99,yes,locked 2006.145.03:36:05.09/vabw/8 2006.145.03:36:05.24/vbbw/8 2006.145.03:36:05.33/xfe/off,on,14.0 2006.145.03:36:05.72/ifatt/23,28,28,28 2006.145.03:36:06.08/fmout-gps/S +4.9E-08 2006.145.03:36:06.16:!2006.145.03:36:42 2006.145.03:36:42.00:data_valid=off 2006.145.03:36:42.00:"et 2006.145.03:36:42.00:!+3s 2006.145.03:36:45.02:"tape 2006.145.03:36:45.02:postob 2006.145.03:36:45.14/cable/+6.5459E-03 2006.145.03:36:45.14/wx/20.02,1017.0,63 2006.145.03:36:46.08/fmout-gps/S +4.9E-08 2006.145.03:36:46.08:scan_name=145-0337,jd0605,40 2006.145.03:36:46.09:source=0537-441,053850.36,-440508.9,2000.0,cw 2006.145.03:36:47.14#flagr#flagr/antenna,new-source 2006.145.03:36:47.14:checkk5 2006.145.03:36:47.63/chk_autoobs//k5ts1/ autoobs is running! 2006.145.03:36:48.14/chk_autoobs//k5ts2/ autoobs is running! 2006.145.03:36:48.61/chk_autoobs//k5ts3/ autoobs is running! 2006.145.03:36:49.06/chk_autoobs//k5ts4/ autoobs is running! 2006.145.03:36:49.54/chk_obsdata//k5ts1/T1450336??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.03:36:50.06/chk_obsdata//k5ts2/T1450336??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.03:36:50.63/chk_obsdata//k5ts3/T1450336??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.03:36:51.12/chk_obsdata//k5ts4/T1450336??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.03:36:52.04/k5log//k5ts1_log_newline 2006.145.03:36:53.51/k5log//k5ts2_log_newline 2006.145.03:36:54.39/k5log//k5ts3_log_newline 2006.145.03:36:55.17/k5log//k5ts4_log_newline 2006.145.03:36:55.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.03:36:55.23:setupk4=1 2006.145.03:36:55.23$setupk4/echo=on 2006.145.03:36:55.23$setupk4/pcalon 2006.145.03:36:55.23$pcalon/"no phase cal control is implemented here 2006.145.03:36:55.23$setupk4/"tpicd=stop 2006.145.03:36:55.24$setupk4/"rec=synch_on 2006.145.03:36:55.24$setupk4/"rec_mode=128 2006.145.03:36:55.24$setupk4/!* 2006.145.03:36:55.24$setupk4/recpk4 2006.145.03:36:55.24$recpk4/recpatch= 2006.145.03:36:55.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.03:36:55.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.03:36:55.24$setupk4/vck44 2006.145.03:36:55.24$vck44/valo=1,524.99 2006.145.03:36:55.24#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.03:36:55.24#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.03:36:55.24#ibcon#ireg 17 cls_cnt 0 2006.145.03:36:55.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.03:36:55.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.03:36:55.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.03:36:55.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.03:36:55.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.03:36:55.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.03:36:55.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.03:36:55.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.03:36:55.31$vck44/va=1,8 2006.145.03:36:55.31#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.03:36:55.31#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.03:36:55.31#ibcon#ireg 11 cls_cnt 2 2006.145.03:36:55.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.03:36:55.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.03:36:55.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.03:36:55.33#ibcon#[25=AT01-08\r\n] 2006.145.03:36:55.36#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.03:36:55.36#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.03:36:55.36#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.03:36:55.36#ibcon#ireg 7 cls_cnt 0 2006.145.03:36:55.36#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.03:36:55.48#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.03:36:55.48#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.03:36:55.50#ibcon#[25=USB\r\n] 2006.145.03:36:55.53#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.03:36:55.53#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.03:36:55.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.03:36:55.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.03:36:55.53$vck44/valo=2,534.99 2006.145.03:36:55.53#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.03:36:55.53#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.03:36:55.53#ibcon#ireg 17 cls_cnt 0 2006.145.03:36:55.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.03:36:55.53#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.03:36:55.53#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.03:36:55.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.03:36:55.60#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.03:36:55.60#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.03:36:55.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.03:36:55.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.03:36:55.60$vck44/va=2,7 2006.145.03:36:55.60#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.03:36:55.60#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.03:36:55.60#ibcon#ireg 11 cls_cnt 2 2006.145.03:36:55.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.03:36:55.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.03:36:55.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.03:36:55.67#ibcon#[25=AT02-07\r\n] 2006.145.03:36:55.70#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.03:36:55.70#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.03:36:55.70#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.03:36:55.70#ibcon#ireg 7 cls_cnt 0 2006.145.03:36:55.70#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.03:36:55.82#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.03:36:55.82#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.03:36:55.84#ibcon#[25=USB\r\n] 2006.145.03:36:55.87#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.03:36:55.87#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.03:36:55.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.03:36:55.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.03:36:55.87$vck44/valo=3,564.99 2006.145.03:36:55.87#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.03:36:55.87#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.03:36:55.87#ibcon#ireg 17 cls_cnt 0 2006.145.03:36:55.87#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.03:36:55.87#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.03:36:55.87#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.03:36:55.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.03:36:55.94#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.03:36:55.94#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.03:36:55.94#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.03:36:55.94#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.03:36:55.94$vck44/va=3,8 2006.145.03:36:55.94#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.03:36:55.94#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.03:36:55.94#ibcon#ireg 11 cls_cnt 2 2006.145.03:36:55.94#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.03:36:55.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.03:36:55.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.03:36:56.01#ibcon#[25=AT03-08\r\n] 2006.145.03:36:56.04#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.03:36:56.04#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.03:36:56.04#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.03:36:56.04#ibcon#ireg 7 cls_cnt 0 2006.145.03:36:56.04#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.03:36:56.16#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.03:36:56.16#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.03:36:56.18#ibcon#[25=USB\r\n] 2006.145.03:36:56.21#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.03:36:56.21#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.03:36:56.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.03:36:56.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.03:36:56.21$vck44/valo=4,624.99 2006.145.03:36:56.21#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.03:36:56.21#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.03:36:56.21#ibcon#ireg 17 cls_cnt 0 2006.145.03:36:56.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.03:36:56.21#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.03:36:56.21#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.03:36:56.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.03:36:56.27#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.03:36:56.27#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.03:36:56.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.03:36:56.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.03:36:56.27$vck44/va=4,7 2006.145.03:36:56.27#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.03:36:56.27#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.03:36:56.27#ibcon#ireg 11 cls_cnt 2 2006.145.03:36:56.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.03:36:56.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.03:36:56.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.03:36:56.35#ibcon#[25=AT04-07\r\n] 2006.145.03:36:56.38#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.03:36:56.38#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.03:36:56.38#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.03:36:56.38#ibcon#ireg 7 cls_cnt 0 2006.145.03:36:56.38#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.03:36:56.50#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.03:36:56.50#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.03:36:56.52#ibcon#[25=USB\r\n] 2006.145.03:36:56.55#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.03:36:56.55#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.03:36:56.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.03:36:56.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.03:36:56.55$vck44/valo=5,734.99 2006.145.03:36:56.55#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.03:36:56.55#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.03:36:56.55#ibcon#ireg 17 cls_cnt 0 2006.145.03:36:56.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.03:36:56.55#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.03:36:56.55#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.03:36:56.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.03:36:56.61#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.03:36:56.61#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.03:36:56.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.03:36:56.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.03:36:56.61$vck44/va=5,4 2006.145.03:36:56.61#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.03:36:56.61#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.03:36:56.61#ibcon#ireg 11 cls_cnt 2 2006.145.03:36:56.61#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.03:36:56.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.03:36:56.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.03:36:56.69#ibcon#[25=AT05-04\r\n] 2006.145.03:36:56.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.03:36:56.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.03:36:56.72#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.03:36:56.72#ibcon#ireg 7 cls_cnt 0 2006.145.03:36:56.72#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.03:36:56.84#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.03:36:56.84#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.03:36:56.86#ibcon#[25=USB\r\n] 2006.145.03:36:56.89#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.03:36:56.89#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.03:36:56.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.03:36:56.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.03:36:56.89$vck44/valo=6,814.99 2006.145.03:36:56.89#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.03:36:56.89#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.03:36:56.89#ibcon#ireg 17 cls_cnt 0 2006.145.03:36:56.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.03:36:56.89#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.03:36:56.89#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.03:36:56.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.03:36:56.95#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.03:36:56.95#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.03:36:56.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.03:36:56.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.03:36:56.95$vck44/va=6,4 2006.145.03:36:56.95#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.03:36:56.95#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.03:36:56.95#ibcon#ireg 11 cls_cnt 2 2006.145.03:36:56.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.03:36:57.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.03:36:57.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.03:36:57.03#ibcon#[25=AT06-04\r\n] 2006.145.03:36:57.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.03:36:57.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.03:36:57.06#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.03:36:57.06#ibcon#ireg 7 cls_cnt 0 2006.145.03:36:57.06#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.03:36:57.18#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.03:36:57.18#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.03:36:57.20#ibcon#[25=USB\r\n] 2006.145.03:36:57.23#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.03:36:57.23#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.03:36:57.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.03:36:57.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.03:36:57.23$vck44/valo=7,864.99 2006.145.03:36:57.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.03:36:57.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.03:36:57.23#ibcon#ireg 17 cls_cnt 0 2006.145.03:36:57.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.03:36:57.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.03:36:57.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.03:36:57.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.03:36:57.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.03:36:57.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.03:36:57.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.03:36:57.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.03:36:57.29$vck44/va=7,4 2006.145.03:36:57.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.03:36:57.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.03:36:57.29#ibcon#ireg 11 cls_cnt 2 2006.145.03:36:57.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.03:36:57.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.03:36:57.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.03:36:57.37#ibcon#[25=AT07-04\r\n] 2006.145.03:36:57.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.03:36:57.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.03:36:57.40#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.03:36:57.40#ibcon#ireg 7 cls_cnt 0 2006.145.03:36:57.40#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.03:36:57.52#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.03:36:57.52#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.03:36:57.54#ibcon#[25=USB\r\n] 2006.145.03:36:57.57#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.03:36:57.57#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.03:36:57.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.03:36:57.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.03:36:57.57$vck44/valo=8,884.99 2006.145.03:36:57.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.03:36:57.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.03:36:57.57#ibcon#ireg 17 cls_cnt 0 2006.145.03:36:57.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.03:36:57.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.03:36:57.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.03:36:57.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.03:36:57.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.03:36:57.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.03:36:57.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.03:36:57.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.03:36:57.63$vck44/va=8,4 2006.145.03:36:57.63#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.03:36:57.63#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.03:36:57.63#ibcon#ireg 11 cls_cnt 2 2006.145.03:36:57.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.03:36:57.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.03:36:57.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.03:36:57.71#ibcon#[25=AT08-04\r\n] 2006.145.03:36:57.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.03:36:57.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.03:36:57.74#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.03:36:57.74#ibcon#ireg 7 cls_cnt 0 2006.145.03:36:57.74#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.03:36:57.86#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.03:36:57.86#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.03:36:57.88#ibcon#[25=USB\r\n] 2006.145.03:36:57.91#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.03:36:57.91#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.03:36:57.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.03:36:57.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.03:36:57.91$vck44/vblo=1,629.99 2006.145.03:36:57.91#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.03:36:57.91#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.03:36:57.91#ibcon#ireg 17 cls_cnt 0 2006.145.03:36:57.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.03:36:57.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.03:36:57.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.03:36:57.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.03:36:57.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.03:36:57.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.03:36:57.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.03:36:57.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.03:36:57.97$vck44/vb=1,3 2006.145.03:36:57.97#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.03:36:57.97#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.03:36:57.97#ibcon#ireg 11 cls_cnt 2 2006.145.03:36:57.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.03:36:57.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.03:36:57.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.03:36:57.99#ibcon#[27=AT01-03\r\n] 2006.145.03:36:58.02#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.03:36:58.02#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.03:36:58.02#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.03:36:58.02#ibcon#ireg 7 cls_cnt 0 2006.145.03:36:58.02#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.03:36:58.14#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.03:36:58.14#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.03:36:58.16#ibcon#[27=USB\r\n] 2006.145.03:36:58.19#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.03:36:58.19#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.03:36:58.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.03:36:58.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.03:36:58.19$vck44/vblo=2,634.99 2006.145.03:36:58.19#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.03:36:58.19#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.03:36:58.19#ibcon#ireg 17 cls_cnt 0 2006.145.03:36:58.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.03:36:58.19#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.03:36:58.19#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.03:36:58.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.03:36:58.25#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.03:36:58.25#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.03:36:58.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.03:36:58.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.03:36:58.25$vck44/vb=2,4 2006.145.03:36:58.25#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.03:36:58.25#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.03:36:58.25#ibcon#ireg 11 cls_cnt 2 2006.145.03:36:58.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.03:36:58.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.03:36:58.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.03:36:58.33#ibcon#[27=AT02-04\r\n] 2006.145.03:36:58.36#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.03:36:58.36#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.03:36:58.36#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.03:36:58.36#ibcon#ireg 7 cls_cnt 0 2006.145.03:36:58.36#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.03:36:58.48#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.03:36:58.48#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.03:36:58.50#ibcon#[27=USB\r\n] 2006.145.03:36:58.53#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.03:36:58.53#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.03:36:58.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.03:36:58.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.03:36:58.53$vck44/vblo=3,649.99 2006.145.03:36:58.53#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.03:36:58.53#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.03:36:58.53#ibcon#ireg 17 cls_cnt 0 2006.145.03:36:58.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.03:36:58.53#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.03:36:58.53#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.03:36:58.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.03:36:58.59#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.03:36:58.59#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.03:36:58.59#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.03:36:58.59#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.03:36:58.59$vck44/vb=3,4 2006.145.03:36:58.59#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.03:36:58.59#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.03:36:58.59#ibcon#ireg 11 cls_cnt 2 2006.145.03:36:58.59#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.03:36:58.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.03:36:58.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.03:36:58.67#ibcon#[27=AT03-04\r\n] 2006.145.03:36:58.70#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.03:36:58.70#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.03:36:58.70#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.03:36:58.70#ibcon#ireg 7 cls_cnt 0 2006.145.03:36:58.70#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.03:36:58.82#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.03:36:58.82#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.03:36:58.84#ibcon#[27=USB\r\n] 2006.145.03:36:58.87#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.03:36:58.87#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.03:36:58.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.03:36:58.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.03:36:58.87$vck44/vblo=4,679.99 2006.145.03:36:58.87#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.03:36:58.87#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.03:36:58.87#ibcon#ireg 17 cls_cnt 0 2006.145.03:36:58.87#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.03:36:58.87#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.03:36:58.87#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.03:36:58.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.03:36:58.93#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.03:36:58.93#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.03:36:58.93#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.03:36:58.93#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.03:36:58.93$vck44/vb=4,4 2006.145.03:36:58.93#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.03:36:58.93#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.03:36:58.93#ibcon#ireg 11 cls_cnt 2 2006.145.03:36:58.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.03:36:58.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.03:36:58.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.03:36:59.01#ibcon#[27=AT04-04\r\n] 2006.145.03:36:59.04#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.03:36:59.04#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.03:36:59.04#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.03:36:59.04#ibcon#ireg 7 cls_cnt 0 2006.145.03:36:59.04#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.03:36:59.16#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.03:36:59.16#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.03:36:59.18#ibcon#[27=USB\r\n] 2006.145.03:36:59.21#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.03:36:59.21#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.03:36:59.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.03:36:59.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.03:36:59.21$vck44/vblo=5,709.99 2006.145.03:36:59.21#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.03:36:59.21#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.03:36:59.21#ibcon#ireg 17 cls_cnt 0 2006.145.03:36:59.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.03:36:59.21#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.03:36:59.21#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.03:36:59.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.03:36:59.27#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.03:36:59.27#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.03:36:59.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.03:36:59.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.03:36:59.27$vck44/vb=5,4 2006.145.03:36:59.27#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.03:36:59.27#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.03:36:59.27#ibcon#ireg 11 cls_cnt 2 2006.145.03:36:59.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.03:36:59.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.03:36:59.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.03:36:59.35#ibcon#[27=AT05-04\r\n] 2006.145.03:36:59.38#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.03:36:59.38#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.03:36:59.38#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.03:36:59.38#ibcon#ireg 7 cls_cnt 0 2006.145.03:36:59.38#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.03:36:59.50#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.03:36:59.50#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.03:36:59.52#ibcon#[27=USB\r\n] 2006.145.03:36:59.55#abcon#<5=/05 3.6 6.8 20.02 681017.0\r\n> 2006.145.03:36:59.55#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.03:36:59.55#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.03:36:59.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.03:36:59.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.03:36:59.55$vck44/vblo=6,719.99 2006.145.03:36:59.55#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.03:36:59.55#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.03:36:59.55#ibcon#ireg 17 cls_cnt 0 2006.145.03:36:59.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:36:59.55#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:36:59.55#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:36:59.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.03:36:59.57#abcon#{5=INTERFACE CLEAR} 2006.145.03:36:59.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:36:59.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:36:59.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.03:36:59.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.03:36:59.61$vck44/vb=6,4 2006.145.03:36:59.61#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.03:36:59.61#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.03:36:59.61#ibcon#ireg 11 cls_cnt 2 2006.145.03:36:59.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.03:36:59.63#abcon#[5=S1D000X0/0*\r\n] 2006.145.03:36:59.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.03:36:59.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.03:36:59.69#ibcon#[27=AT06-04\r\n] 2006.145.03:36:59.72#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.03:36:59.72#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.03:36:59.72#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.03:36:59.72#ibcon#ireg 7 cls_cnt 0 2006.145.03:36:59.72#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.03:36:59.84#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.03:36:59.84#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.03:36:59.86#ibcon#[27=USB\r\n] 2006.145.03:36:59.89#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.03:36:59.89#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.03:36:59.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.03:36:59.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.03:36:59.89$vck44/vblo=7,734.99 2006.145.03:36:59.89#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.03:36:59.89#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.03:36:59.89#ibcon#ireg 17 cls_cnt 0 2006.145.03:36:59.89#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.03:36:59.89#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.03:36:59.89#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.03:36:59.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.03:36:59.95#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.03:36:59.95#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.03:36:59.95#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.03:36:59.95#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.03:36:59.95$vck44/vb=7,4 2006.145.03:36:59.95#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.03:36:59.95#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.03:36:59.95#ibcon#ireg 11 cls_cnt 2 2006.145.03:36:59.95#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.03:37:00.01#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.03:37:00.01#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.03:37:00.03#ibcon#[27=AT07-04\r\n] 2006.145.03:37:00.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.03:37:00.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.03:37:00.06#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.03:37:00.06#ibcon#ireg 7 cls_cnt 0 2006.145.03:37:00.06#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.03:37:00.18#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.03:37:00.18#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.03:37:00.20#ibcon#[27=USB\r\n] 2006.145.03:37:00.23#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.03:37:00.23#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.03:37:00.23#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.03:37:00.23#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.03:37:00.23$vck44/vblo=8,744.99 2006.145.03:37:00.23#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.03:37:00.23#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.03:37:00.23#ibcon#ireg 17 cls_cnt 0 2006.145.03:37:00.23#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.03:37:00.23#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.03:37:00.23#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.03:37:00.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.03:37:00.29#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.03:37:00.29#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.03:37:00.29#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.03:37:00.29#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.03:37:00.29$vck44/vb=8,4 2006.145.03:37:00.29#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.03:37:00.29#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.03:37:00.29#ibcon#ireg 11 cls_cnt 2 2006.145.03:37:00.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.03:37:00.35#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.03:37:00.35#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.03:37:00.37#ibcon#[27=AT08-04\r\n] 2006.145.03:37:00.40#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.03:37:00.40#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.03:37:00.40#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.03:37:00.40#ibcon#ireg 7 cls_cnt 0 2006.145.03:37:00.40#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.03:37:00.52#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.03:37:00.52#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.03:37:00.54#ibcon#[27=USB\r\n] 2006.145.03:37:00.57#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.03:37:00.57#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.03:37:00.57#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.03:37:00.57#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.03:37:00.57$vck44/vabw=wide 2006.145.03:37:00.57#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.03:37:00.57#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.03:37:00.57#ibcon#ireg 8 cls_cnt 0 2006.145.03:37:00.57#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.03:37:00.57#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.03:37:00.57#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.03:37:00.59#ibcon#[25=BW32\r\n] 2006.145.03:37:00.62#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.03:37:00.62#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.03:37:00.62#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.03:37:00.62#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.03:37:00.62$vck44/vbbw=wide 2006.145.03:37:00.62#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.03:37:00.62#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.03:37:00.62#ibcon#ireg 8 cls_cnt 0 2006.145.03:37:00.62#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.03:37:00.69#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.03:37:00.69#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.03:37:00.71#ibcon#[27=BW32\r\n] 2006.145.03:37:00.74#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.03:37:00.74#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.03:37:00.74#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.03:37:00.74#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.03:37:00.74$setupk4/ifdk4 2006.145.03:37:00.74$ifdk4/lo= 2006.145.03:37:00.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.03:37:00.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.03:37:00.74$ifdk4/patch= 2006.145.03:37:00.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.03:37:00.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.03:37:00.74$setupk4/!*+20s 2006.145.03:37:09.72#abcon#<5=/05 3.6 6.8 20.01 701017.0\r\n> 2006.145.03:37:09.74#abcon#{5=INTERFACE CLEAR} 2006.145.03:37:09.80#abcon#[5=S1D000X0/0*\r\n] 2006.145.03:37:15.25$setupk4/"tpicd 2006.145.03:37:15.25$setupk4/echo=off 2006.145.03:37:15.25$setupk4/xlog=off 2006.145.03:37:15.25:!2006.145.03:37:33 2006.145.03:37:30.14#trakl#Source acquired 2006.145.03:37:30.14#flagr#flagr/antenna,acquired 2006.145.03:37:33.00:preob 2006.145.03:37:34.14/onsource/TRACKING 2006.145.03:37:34.14:!2006.145.03:37:43 2006.145.03:37:43.00:"tape 2006.145.03:37:43.00:"st=record 2006.145.03:37:43.00:data_valid=on 2006.145.03:37:43.00:midob 2006.145.03:37:43.14/onsource/TRACKING 2006.145.03:37:43.14/wx/20.03,1017.0,65 2006.145.03:37:43.24/cable/+6.5474E-03 2006.145.03:37:44.33/va/01,08,usb,yes,34,37 2006.145.03:37:44.33/va/02,07,usb,yes,37,37 2006.145.03:37:44.33/va/03,08,usb,yes,33,35 2006.145.03:37:44.33/va/04,07,usb,yes,38,40 2006.145.03:37:44.33/va/05,04,usb,yes,33,34 2006.145.03:37:44.33/va/06,04,usb,yes,37,37 2006.145.03:37:44.33/va/07,04,usb,yes,37,39 2006.145.03:37:44.33/va/08,04,usb,yes,32,38 2006.145.03:37:44.56/valo/01,524.99,yes,locked 2006.145.03:37:44.56/valo/02,534.99,yes,locked 2006.145.03:37:44.56/valo/03,564.99,yes,locked 2006.145.03:37:44.56/valo/04,624.99,yes,locked 2006.145.03:37:44.56/valo/05,734.99,yes,locked 2006.145.03:37:44.56/valo/06,814.99,yes,locked 2006.145.03:37:44.56/valo/07,864.99,yes,locked 2006.145.03:37:44.56/valo/08,884.99,yes,locked 2006.145.03:37:45.65/vb/01,03,usb,yes,40,37 2006.145.03:37:45.65/vb/02,04,usb,yes,35,35 2006.145.03:37:45.65/vb/03,04,usb,yes,31,35 2006.145.03:37:45.65/vb/04,04,usb,yes,36,35 2006.145.03:37:45.65/vb/05,04,usb,yes,28,31 2006.145.03:37:45.65/vb/06,04,usb,yes,33,29 2006.145.03:37:45.65/vb/07,04,usb,yes,33,33 2006.145.03:37:45.65/vb/08,04,usb,yes,30,34 2006.145.03:37:45.88/vblo/01,629.99,yes,locked 2006.145.03:37:45.88/vblo/02,634.99,yes,locked 2006.145.03:37:45.88/vblo/03,649.99,yes,locked 2006.145.03:37:45.88/vblo/04,679.99,yes,locked 2006.145.03:37:45.88/vblo/05,709.99,yes,locked 2006.145.03:37:45.88/vblo/06,719.99,yes,locked 2006.145.03:37:45.88/vblo/07,734.99,yes,locked 2006.145.03:37:45.88/vblo/08,744.99,yes,locked 2006.145.03:37:46.03/vabw/8 2006.145.03:37:46.18/vbbw/8 2006.145.03:37:46.27/xfe/off,on,15.0 2006.145.03:37:46.67/ifatt/23,28,28,28 2006.145.03:37:47.08/fmout-gps/S +4.7E-08 2006.145.03:37:47.16:!2006.145.03:38:23 2006.145.03:38:23.00:data_valid=off 2006.145.03:38:23.00:"et 2006.145.03:38:23.00:!+3s 2006.145.03:38:26.02:"tape 2006.145.03:38:26.02:postob 2006.145.03:38:26.09/cable/+6.5452E-03 2006.145.03:38:26.09/wx/20.04,1017.0,67 2006.145.03:38:26.16/fmout-gps/S +4.8E-08 2006.145.03:38:26.17:scan_name=145-0339,jd0605,784 2006.145.03:38:26.17:source=1418+546,141946.60,542314.8,2000.0,cw 2006.145.03:38:28.13#flagr#flagr/antenna,new-source 2006.145.03:38:28.13:checkk5 2006.145.03:38:28.65/chk_autoobs//k5ts1/ autoobs is running! 2006.145.03:38:29.25/chk_autoobs//k5ts2/ autoobs is running! 2006.145.03:38:29.90/chk_autoobs//k5ts3/ autoobs is running! 2006.145.03:38:30.39/chk_autoobs//k5ts4/ autoobs is running! 2006.145.03:38:30.92/chk_obsdata//k5ts1/T1450337??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.03:38:31.42/chk_obsdata//k5ts2/T1450337??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.03:38:31.97/chk_obsdata//k5ts3/T1450337??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.03:38:32.57/chk_obsdata//k5ts4/T1450337??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.03:38:33.46/k5log//k5ts1_log_newline 2006.145.03:38:34.72/k5log//k5ts2_log_newline 2006.145.03:38:35.79/k5log//k5ts3_log_newline 2006.145.03:38:36.70/k5log//k5ts4_log_newline 2006.145.03:38:36.72/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.03:38:36.72:setupk4=1 2006.145.03:38:36.72$setupk4/echo=on 2006.145.03:38:36.72$setupk4/pcalon 2006.145.03:38:36.72$pcalon/"no phase cal control is implemented here 2006.145.03:38:36.72$setupk4/"tpicd=stop 2006.145.03:38:36.72$setupk4/"rec=synch_on 2006.145.03:38:36.72$setupk4/"rec_mode=128 2006.145.03:38:36.72$setupk4/!* 2006.145.03:38:36.72$setupk4/recpk4 2006.145.03:38:36.72$recpk4/recpatch= 2006.145.03:38:36.73$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.03:38:36.73$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.03:38:36.73$setupk4/vck44 2006.145.03:38:36.73$vck44/valo=1,524.99 2006.145.03:38:36.73#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.03:38:36.73#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.03:38:36.73#ibcon#ireg 17 cls_cnt 0 2006.145.03:38:36.73#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.03:38:36.73#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.03:38:36.73#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.03:38:36.77#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.03:38:36.82#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.03:38:36.82#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.03:38:36.82#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.03:38:36.82#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.03:38:36.82$vck44/va=1,8 2006.145.03:38:36.82#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.03:38:36.82#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.03:38:36.82#ibcon#ireg 11 cls_cnt 2 2006.145.03:38:36.82#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.03:38:36.82#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.03:38:36.82#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.03:38:36.84#ibcon#[25=AT01-08\r\n] 2006.145.03:38:36.87#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.03:38:36.87#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.03:38:36.87#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.03:38:36.87#ibcon#ireg 7 cls_cnt 0 2006.145.03:38:36.87#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.03:38:36.99#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.03:38:36.99#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.03:38:37.01#ibcon#[25=USB\r\n] 2006.145.03:38:37.04#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.03:38:37.04#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.03:38:37.04#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.03:38:37.04#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.03:38:37.04$vck44/valo=2,534.99 2006.145.03:38:37.04#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.03:38:37.04#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.03:38:37.04#ibcon#ireg 17 cls_cnt 0 2006.145.03:38:37.04#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.03:38:37.04#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.03:38:37.04#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.03:38:37.06#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.03:38:37.10#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.03:38:37.10#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.03:38:37.10#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.03:38:37.10#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.03:38:37.10$vck44/va=2,7 2006.145.03:38:37.10#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.03:38:37.10#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.03:38:37.10#ibcon#ireg 11 cls_cnt 2 2006.145.03:38:37.10#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.03:38:37.16#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.03:38:37.16#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.03:38:37.18#ibcon#[25=AT02-07\r\n] 2006.145.03:38:37.22#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.03:38:37.22#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.03:38:37.22#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.03:38:37.22#ibcon#ireg 7 cls_cnt 0 2006.145.03:38:37.22#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.03:38:37.34#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.03:38:37.34#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.03:38:37.36#ibcon#[25=USB\r\n] 2006.145.03:38:37.39#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.03:38:37.39#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.03:38:37.39#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.03:38:37.39#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.03:38:37.39$vck44/valo=3,564.99 2006.145.03:38:37.39#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.03:38:37.39#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.03:38:37.39#ibcon#ireg 17 cls_cnt 0 2006.145.03:38:37.39#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.03:38:37.39#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.03:38:37.39#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.03:38:37.41#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.03:38:37.45#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.03:38:37.45#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.03:38:37.45#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.03:38:37.45#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.03:38:37.45$vck44/va=3,8 2006.145.03:38:37.45#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.03:38:37.45#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.03:38:37.45#ibcon#ireg 11 cls_cnt 2 2006.145.03:38:37.45#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.03:38:37.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.03:38:37.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.03:38:37.53#ibcon#[25=AT03-08\r\n] 2006.145.03:38:37.56#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.03:38:37.56#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.03:38:37.56#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.03:38:37.56#ibcon#ireg 7 cls_cnt 0 2006.145.03:38:37.56#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.03:38:37.68#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.03:38:37.68#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.03:38:37.70#ibcon#[25=USB\r\n] 2006.145.03:38:37.73#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.03:38:37.73#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.03:38:37.73#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.03:38:37.73#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.03:38:37.73$vck44/valo=4,624.99 2006.145.03:38:37.73#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.03:38:37.73#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.03:38:37.73#ibcon#ireg 17 cls_cnt 0 2006.145.03:38:37.73#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.03:38:37.73#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.03:38:37.73#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.03:38:37.75#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.03:38:37.79#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.03:38:37.79#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.03:38:37.79#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.03:38:37.79#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.03:38:37.79$vck44/va=4,7 2006.145.03:38:37.79#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.03:38:37.79#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.03:38:37.79#ibcon#ireg 11 cls_cnt 2 2006.145.03:38:37.79#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.03:38:37.85#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.03:38:37.85#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.03:38:37.87#ibcon#[25=AT04-07\r\n] 2006.145.03:38:37.90#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.03:38:37.90#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.03:38:37.90#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.03:38:37.90#ibcon#ireg 7 cls_cnt 0 2006.145.03:38:37.90#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.03:38:38.02#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.03:38:38.02#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.03:38:38.04#ibcon#[25=USB\r\n] 2006.145.03:38:38.07#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.03:38:38.07#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.03:38:38.07#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.03:38:38.07#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.03:38:38.07$vck44/valo=5,734.99 2006.145.03:38:38.07#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.03:38:38.07#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.03:38:38.07#ibcon#ireg 17 cls_cnt 0 2006.145.03:38:38.07#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:38:38.07#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:38:38.07#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:38:38.09#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.03:38:38.13#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:38:38.13#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:38:38.13#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.03:38:38.13#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.03:38:38.13$vck44/va=5,4 2006.145.03:38:38.13#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.03:38:38.13#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.03:38:38.13#ibcon#ireg 11 cls_cnt 2 2006.145.03:38:38.13#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.03:38:38.19#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.03:38:38.19#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.03:38:38.21#ibcon#[25=AT05-04\r\n] 2006.145.03:38:38.24#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.03:38:38.24#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.03:38:38.24#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.03:38:38.24#ibcon#ireg 7 cls_cnt 0 2006.145.03:38:38.24#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.03:38:38.36#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.03:38:38.36#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.03:38:38.38#ibcon#[25=USB\r\n] 2006.145.03:38:38.41#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.03:38:38.41#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.03:38:38.41#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.03:38:38.41#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.03:38:38.41$vck44/valo=6,814.99 2006.145.03:38:38.41#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.03:38:38.41#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.03:38:38.41#ibcon#ireg 17 cls_cnt 0 2006.145.03:38:38.41#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.03:38:38.41#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.03:38:38.41#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.03:38:38.43#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.03:38:38.47#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.03:38:38.47#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.03:38:38.47#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.03:38:38.47#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.03:38:38.47$vck44/va=6,4 2006.145.03:38:38.47#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.03:38:38.47#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.03:38:38.47#ibcon#ireg 11 cls_cnt 2 2006.145.03:38:38.47#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.03:38:38.53#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.03:38:38.53#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.03:38:38.55#ibcon#[25=AT06-04\r\n] 2006.145.03:38:38.58#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.03:38:38.58#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.03:38:38.58#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.03:38:38.58#ibcon#ireg 7 cls_cnt 0 2006.145.03:38:38.58#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.03:38:38.70#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.03:38:38.70#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.03:38:38.72#ibcon#[25=USB\r\n] 2006.145.03:38:38.75#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.03:38:38.75#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.03:38:38.75#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.03:38:38.75#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.03:38:38.75$vck44/valo=7,864.99 2006.145.03:38:38.75#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.03:38:38.75#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.03:38:38.75#ibcon#ireg 17 cls_cnt 0 2006.145.03:38:38.75#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.03:38:38.75#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.03:38:38.75#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.03:38:38.78#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.03:38:38.82#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.03:38:38.82#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.03:38:38.82#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.03:38:38.82#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.03:38:38.82$vck44/va=7,4 2006.145.03:38:38.82#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.03:38:38.82#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.03:38:38.82#ibcon#ireg 11 cls_cnt 2 2006.145.03:38:38.82#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.03:38:38.87#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.03:38:38.87#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.03:38:38.89#ibcon#[25=AT07-04\r\n] 2006.145.03:38:38.92#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.03:38:38.92#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.03:38:38.92#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.03:38:38.92#ibcon#ireg 7 cls_cnt 0 2006.145.03:38:38.92#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.03:38:39.04#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.03:38:39.04#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.03:38:39.06#ibcon#[25=USB\r\n] 2006.145.03:38:39.09#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.03:38:39.09#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.03:38:39.09#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.03:38:39.09#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.03:38:39.09$vck44/valo=8,884.99 2006.145.03:38:39.09#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.03:38:39.09#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.03:38:39.09#ibcon#ireg 17 cls_cnt 0 2006.145.03:38:39.09#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.03:38:39.09#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.03:38:39.09#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.03:38:39.11#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.03:38:39.15#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.03:38:39.15#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.03:38:39.15#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.03:38:39.15#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.03:38:39.15$vck44/va=8,4 2006.145.03:38:39.15#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.03:38:39.15#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.03:38:39.15#ibcon#ireg 11 cls_cnt 2 2006.145.03:38:39.15#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.03:38:39.21#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.03:38:39.21#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.03:38:39.23#ibcon#[25=AT08-04\r\n] 2006.145.03:38:39.26#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.03:38:39.26#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.03:38:39.26#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.03:38:39.26#ibcon#ireg 7 cls_cnt 0 2006.145.03:38:39.26#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.03:38:39.38#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.03:38:39.38#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.03:38:39.40#ibcon#[25=USB\r\n] 2006.145.03:38:39.43#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.03:38:39.43#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.03:38:39.43#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.03:38:39.43#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.03:38:39.43$vck44/vblo=1,629.99 2006.145.03:38:39.43#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.03:38:39.43#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.03:38:39.43#ibcon#ireg 17 cls_cnt 0 2006.145.03:38:39.43#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.03:38:39.43#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.03:38:39.43#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.03:38:39.45#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.03:38:39.49#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.03:38:39.49#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.03:38:39.49#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.03:38:39.49#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.03:38:39.49$vck44/vb=1,3 2006.145.03:38:39.49#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.03:38:39.49#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.03:38:39.49#ibcon#ireg 11 cls_cnt 2 2006.145.03:38:39.49#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.03:38:39.49#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.03:38:39.49#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.03:38:39.51#ibcon#[27=AT01-03\r\n] 2006.145.03:38:39.54#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.03:38:39.54#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.03:38:39.54#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.03:38:39.54#ibcon#ireg 7 cls_cnt 0 2006.145.03:38:39.54#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.03:38:39.66#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.03:38:39.66#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.03:38:39.68#ibcon#[27=USB\r\n] 2006.145.03:38:39.71#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.03:38:39.71#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.03:38:39.71#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.03:38:39.71#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.03:38:39.71$vck44/vblo=2,634.99 2006.145.03:38:39.71#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.03:38:39.71#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.03:38:39.71#ibcon#ireg 17 cls_cnt 0 2006.145.03:38:39.71#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.03:38:39.71#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.03:38:39.71#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.03:38:39.73#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.03:38:39.77#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.03:38:39.77#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.03:38:39.77#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.03:38:39.77#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.03:38:39.77$vck44/vb=2,4 2006.145.03:38:39.77#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.03:38:39.77#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.03:38:39.77#ibcon#ireg 11 cls_cnt 2 2006.145.03:38:39.77#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.03:38:39.83#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.03:38:39.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.03:38:39.85#ibcon#[27=AT02-04\r\n] 2006.145.03:38:39.88#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.03:38:39.88#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.03:38:39.88#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.03:38:39.88#ibcon#ireg 7 cls_cnt 0 2006.145.03:38:39.88#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.03:38:40.00#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.03:38:40.00#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.03:38:40.02#ibcon#[27=USB\r\n] 2006.145.03:38:40.05#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.03:38:40.05#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.03:38:40.05#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.03:38:40.05#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.03:38:40.05$vck44/vblo=3,649.99 2006.145.03:38:40.05#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.03:38:40.05#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.03:38:40.05#ibcon#ireg 17 cls_cnt 0 2006.145.03:38:40.05#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.03:38:40.05#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.03:38:40.05#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.03:38:40.07#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.03:38:40.11#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.03:38:40.11#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.03:38:40.11#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.03:38:40.11#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.03:38:40.11$vck44/vb=3,4 2006.145.03:38:40.11#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.03:38:40.11#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.03:38:40.11#ibcon#ireg 11 cls_cnt 2 2006.145.03:38:40.11#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.03:38:40.17#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.03:38:40.17#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.03:38:40.19#ibcon#[27=AT03-04\r\n] 2006.145.03:38:40.22#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.03:38:40.22#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.03:38:40.22#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.03:38:40.22#ibcon#ireg 7 cls_cnt 0 2006.145.03:38:40.22#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.03:38:40.34#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.03:38:40.34#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.03:38:40.36#ibcon#[27=USB\r\n] 2006.145.03:38:40.39#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.03:38:40.39#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.03:38:40.39#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.03:38:40.39#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.03:38:40.39$vck44/vblo=4,679.99 2006.145.03:38:40.39#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.03:38:40.39#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.03:38:40.39#ibcon#ireg 17 cls_cnt 0 2006.145.03:38:40.39#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.03:38:40.39#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.03:38:40.39#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.03:38:40.41#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.03:38:40.45#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.03:38:40.45#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.03:38:40.45#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.03:38:40.45#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.03:38:40.45$vck44/vb=4,4 2006.145.03:38:40.45#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.03:38:40.45#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.03:38:40.45#ibcon#ireg 11 cls_cnt 2 2006.145.03:38:40.45#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.03:38:40.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.03:38:40.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.03:38:40.53#ibcon#[27=AT04-04\r\n] 2006.145.03:38:40.56#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.03:38:40.56#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.03:38:40.56#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.03:38:40.56#ibcon#ireg 7 cls_cnt 0 2006.145.03:38:40.56#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.03:38:40.68#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.03:38:40.68#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.03:38:40.70#ibcon#[27=USB\r\n] 2006.145.03:38:40.73#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.03:38:40.73#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.03:38:40.73#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.03:38:40.73#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.03:38:40.73$vck44/vblo=5,709.99 2006.145.03:38:40.73#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.03:38:40.73#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.03:38:40.73#ibcon#ireg 17 cls_cnt 0 2006.145.03:38:40.73#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.03:38:40.73#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.03:38:40.73#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.03:38:40.75#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.03:38:40.79#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.03:38:40.79#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.03:38:40.79#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.03:38:40.79#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.03:38:40.79$vck44/vb=5,4 2006.145.03:38:40.79#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.03:38:40.79#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.03:38:40.79#ibcon#ireg 11 cls_cnt 2 2006.145.03:38:40.79#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.03:38:40.85#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.03:38:40.85#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.03:38:40.87#ibcon#[27=AT05-04\r\n] 2006.145.03:38:40.90#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.03:38:40.90#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.03:38:40.90#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.03:38:40.90#ibcon#ireg 7 cls_cnt 0 2006.145.03:38:40.90#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.03:38:41.02#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.03:38:41.02#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.03:38:41.04#ibcon#[27=USB\r\n] 2006.145.03:38:41.07#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.03:38:41.07#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.03:38:41.07#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.03:38:41.07#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.03:38:41.07$vck44/vblo=6,719.99 2006.145.03:38:41.07#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.03:38:41.07#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.03:38:41.07#ibcon#ireg 17 cls_cnt 0 2006.145.03:38:41.07#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:38:41.07#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:38:41.07#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:38:41.09#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.03:38:41.13#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:38:41.13#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.03:38:41.13#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.03:38:41.13#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.03:38:41.13$vck44/vb=6,4 2006.145.03:38:41.13#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.03:38:41.13#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.03:38:41.13#ibcon#ireg 11 cls_cnt 2 2006.145.03:38:41.13#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.03:38:41.19#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.03:38:41.19#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.03:38:41.21#ibcon#[27=AT06-04\r\n] 2006.145.03:38:41.24#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.03:38:41.24#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.03:38:41.24#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.03:38:41.24#ibcon#ireg 7 cls_cnt 0 2006.145.03:38:41.24#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.03:38:41.36#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.03:38:41.36#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.03:38:41.37#abcon#<5=/05 3.6 6.8 20.05 681017.0\r\n> 2006.145.03:38:41.38#ibcon#[27=USB\r\n] 2006.145.03:38:41.39#abcon#{5=INTERFACE CLEAR} 2006.145.03:38:41.41#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.03:38:41.41#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.03:38:41.41#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.03:38:41.41#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.03:38:41.41$vck44/vblo=7,734.99 2006.145.03:38:41.41#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.03:38:41.41#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.03:38:41.41#ibcon#ireg 17 cls_cnt 0 2006.145.03:38:41.41#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.03:38:41.41#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.03:38:41.41#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.03:38:41.43#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.03:38:41.45#abcon#[5=S1D000X0/0*\r\n] 2006.145.03:38:41.47#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.03:38:41.47#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.03:38:41.47#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.03:38:41.47#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.03:38:41.47$vck44/vb=7,4 2006.145.03:38:41.47#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.03:38:41.47#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.03:38:41.47#ibcon#ireg 11 cls_cnt 2 2006.145.03:38:41.47#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.03:38:41.53#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.03:38:41.53#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.03:38:41.55#ibcon#[27=AT07-04\r\n] 2006.145.03:38:41.58#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.03:38:41.58#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.03:38:41.58#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.03:38:41.58#ibcon#ireg 7 cls_cnt 0 2006.145.03:38:41.58#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.03:38:41.70#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.03:38:41.70#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.03:38:41.72#ibcon#[27=USB\r\n] 2006.145.03:38:41.75#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.03:38:41.75#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.03:38:41.75#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.03:38:41.75#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.03:38:41.75$vck44/vblo=8,744.99 2006.145.03:38:41.75#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.03:38:41.75#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.03:38:41.75#ibcon#ireg 17 cls_cnt 0 2006.145.03:38:41.75#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.03:38:41.75#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.03:38:41.75#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.03:38:41.77#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.03:38:41.81#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.03:38:41.81#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.03:38:41.81#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.03:38:41.81#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.03:38:41.81$vck44/vb=8,4 2006.145.03:38:41.81#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.03:38:41.81#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.03:38:41.81#ibcon#ireg 11 cls_cnt 2 2006.145.03:38:41.81#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.03:38:41.87#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.03:38:41.87#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.03:38:41.89#ibcon#[27=AT08-04\r\n] 2006.145.03:38:41.92#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.03:38:41.92#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.03:38:41.92#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.03:38:41.92#ibcon#ireg 7 cls_cnt 0 2006.145.03:38:41.92#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.03:38:42.04#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.03:38:42.04#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.03:38:42.06#ibcon#[27=USB\r\n] 2006.145.03:38:42.09#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.03:38:42.09#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.03:38:42.09#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.03:38:42.09#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.03:38:42.09$vck44/vabw=wide 2006.145.03:38:42.09#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.03:38:42.09#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.03:38:42.09#ibcon#ireg 8 cls_cnt 0 2006.145.03:38:42.09#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.03:38:42.09#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.03:38:42.09#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.03:38:42.11#ibcon#[25=BW32\r\n] 2006.145.03:38:42.14#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.03:38:42.14#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.03:38:42.14#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.03:38:42.14#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.03:38:42.14$vck44/vbbw=wide 2006.145.03:38:42.14#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.03:38:42.14#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.03:38:42.14#ibcon#ireg 8 cls_cnt 0 2006.145.03:38:42.14#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:38:42.21#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:38:42.21#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:38:42.23#ibcon#[27=BW32\r\n] 2006.145.03:38:42.26#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:38:42.26#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:38:42.26#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.03:38:42.26#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.03:38:42.26$setupk4/ifdk4 2006.145.03:38:42.26$ifdk4/lo= 2006.145.03:38:42.26$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.03:38:42.26$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.03:38:42.26$ifdk4/patch= 2006.145.03:38:42.26$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.03:38:42.26$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.03:38:42.26$setupk4/!*+20s 2006.145.03:38:51.54#abcon#<5=/05 3.7 6.8 20.06 651017.0\r\n> 2006.145.03:38:51.56#abcon#{5=INTERFACE CLEAR} 2006.145.03:38:51.62#abcon#[5=S1D000X0/0*\r\n] 2006.145.03:38:56.73$setupk4/"tpicd 2006.145.03:38:56.73$setupk4/echo=off 2006.145.03:38:56.73$setupk4/xlog=off 2006.145.03:38:56.73:!2006.145.03:39:28 2006.145.03:39:26.13#trakl#Source acquired 2006.145.03:39:26.13#flagr#flagr/antenna,acquired 2006.145.03:39:28.00:preob 2006.145.03:39:28.13/onsource/TRACKING 2006.145.03:39:28.13:!2006.145.03:39:38 2006.145.03:39:38.00:"tape 2006.145.03:39:38.00:"st=record 2006.145.03:39:38.00:data_valid=on 2006.145.03:39:38.00:midob 2006.145.03:39:38.13/onsource/TRACKING 2006.145.03:39:38.13/wx/20.09,1017.0,62 2006.145.03:39:38.29/cable/+6.5453E-03 2006.145.03:39:39.38/va/01,08,usb,yes,35,38 2006.145.03:39:39.38/va/02,07,usb,yes,37,38 2006.145.03:39:39.38/va/03,08,usb,yes,34,36 2006.145.03:39:39.38/va/04,07,usb,yes,39,41 2006.145.03:39:39.38/va/05,04,usb,yes,34,35 2006.145.03:39:39.38/va/06,04,usb,yes,38,38 2006.145.03:39:39.38/va/07,04,usb,yes,38,40 2006.145.03:39:39.38/va/08,04,usb,yes,33,39 2006.145.03:39:39.61/valo/01,524.99,yes,locked 2006.145.03:39:39.61/valo/02,534.99,yes,locked 2006.145.03:39:39.61/valo/03,564.99,yes,locked 2006.145.03:39:39.61/valo/04,624.99,yes,locked 2006.145.03:39:39.61/valo/05,734.99,yes,locked 2006.145.03:39:39.61/valo/06,814.99,yes,locked 2006.145.03:39:39.61/valo/07,864.99,yes,locked 2006.145.03:39:39.61/valo/08,884.99,yes,locked 2006.145.03:39:40.70/vb/01,03,usb,yes,43,97 2006.145.03:39:40.70/vb/02,04,usb,yes,34,88 2006.145.03:39:40.70/vb/03,04,usb,yes,31,57 2006.145.03:39:40.70/vb/04,04,usb,yes,35,34 2006.145.03:39:40.70/vb/05,04,usb,yes,29,31 2006.145.03:39:40.70/vb/06,04,usb,yes,37,30 2006.145.03:39:40.70/vb/07,04,usb,yes,32,35 2006.145.03:39:40.70/vb/08,04,usb,yes,30,35 2006.145.03:39:40.93/vblo/01,629.99,yes,locked 2006.145.03:39:40.93/vblo/02,634.99,yes,locked 2006.145.03:39:40.93/vblo/03,649.99,yes,locked 2006.145.03:39:40.93/vblo/04,679.99,yes,locked 2006.145.03:39:40.93/vblo/05,709.99,yes,locked 2006.145.03:39:40.93/vblo/06,719.99,yes,locked 2006.145.03:39:40.93/vblo/07,734.99,yes,locked 2006.145.03:39:40.93/vblo/08,744.99,yes,locked 2006.145.03:39:41.08/vabw/8 2006.145.03:39:41.23/vbbw/8 2006.145.03:39:41.32/xfe/off,on,15.0 2006.145.03:39:41.71/ifatt/23,28,28,28 2006.145.03:39:42.08/fmout-gps/S +5.0E-08 2006.145.03:39:42.12:!2006.145.03:52:42 2006.145.03:52:42.00:data_valid=off 2006.145.03:52:42.01:"et 2006.145.03:52:42.01:!+3s 2006.145.03:52:45.02:"tape 2006.145.03:52:45.02:postob 2006.145.03:52:45.20/cable/+6.5443E-03 2006.145.03:52:45.20/wx/20.35,1016.7,62 2006.145.03:52:45.28/fmout-gps/S +5.2E-08 2006.145.03:52:45.28:scan_name=145-0354,jd0605,50 2006.145.03:52:45.28:source=0552+398,055530.81,394849.2,2000.0,cw 2006.145.03:52:47.14#flagr#flagr/antenna,new-source 2006.145.03:52:47.14:checkk5 2006.145.03:52:47.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.03:52:48.05/chk_autoobs//k5ts2/ autoobs is running! 2006.145.03:52:48.63/chk_autoobs//k5ts3/ autoobs is running! 2006.145.03:52:49.15/chk_autoobs//k5ts4/ autoobs is running! 2006.145.03:52:49.92/chk_obsdata//k5ts1/T1450339??a.dat file size is correct (nominal:3136MB, actual:3136MB). 2006.145.03:52:50.71/chk_obsdata//k5ts2/T1450339??b.dat file size is correct (nominal:3136MB, actual:3136MB). 2006.145.03:52:51.63/chk_obsdata//k5ts3/T1450339??c.dat file size is correct (nominal:3136MB, actual:3136MB). 2006.145.03:52:52.44/chk_obsdata//k5ts4/T1450339??d.dat file size is correct (nominal:3136MB, actual:3136MB). 2006.145.03:52:53.23/k5log//k5ts1_log_newline 2006.145.03:52:54.06/k5log//k5ts2_log_newline 2006.145.03:52:54.89/k5log//k5ts3_log_newline 2006.145.03:52:55.70/k5log//k5ts4_log_newline 2006.145.03:52:55.72/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.03:52:55.72:setupk4=1 2006.145.03:52:55.72$setupk4/echo=on 2006.145.03:52:55.72$setupk4/pcalon 2006.145.03:52:55.72$pcalon/"no phase cal control is implemented here 2006.145.03:52:55.72$setupk4/"tpicd=stop 2006.145.03:52:55.72$setupk4/"rec=synch_on 2006.145.03:52:55.72$setupk4/"rec_mode=128 2006.145.03:52:55.72$setupk4/!* 2006.145.03:52:55.72$setupk4/recpk4 2006.145.03:52:55.72$recpk4/recpatch= 2006.145.03:52:55.73$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.03:52:55.73$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.03:52:55.73$setupk4/vck44 2006.145.03:52:55.73$vck44/valo=1,524.99 2006.145.03:52:55.73#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.03:52:55.73#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.03:52:55.73#ibcon#ireg 17 cls_cnt 0 2006.145.03:52:55.73#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.03:52:55.73#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.03:52:55.73#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.03:52:55.77#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.03:52:55.81#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.03:52:55.81#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.03:52:55.81#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.03:52:55.81#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.03:52:55.81$vck44/va=1,8 2006.145.03:52:55.81#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.03:52:55.81#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.03:52:55.81#ibcon#ireg 11 cls_cnt 2 2006.145.03:52:55.81#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.03:52:55.81#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.03:52:55.81#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.03:52:55.83#ibcon#[25=AT01-08\r\n] 2006.145.03:52:55.86#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.03:52:55.86#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.03:52:55.86#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.03:52:55.86#ibcon#ireg 7 cls_cnt 0 2006.145.03:52:55.86#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.03:52:55.87#abcon#<5=/06 4.1 8.1 20.36 591016.7\r\n> 2006.145.03:52:55.89#abcon#{5=INTERFACE CLEAR} 2006.145.03:52:55.95#abcon#[5=S1D000X0/0*\r\n] 2006.145.03:52:55.98#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.03:52:55.98#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.03:52:56.00#ibcon#[25=USB\r\n] 2006.145.03:52:56.03#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.03:52:56.03#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.03:52:56.03#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.03:52:56.03#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.03:52:56.03$vck44/valo=2,534.99 2006.145.03:52:56.03#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.03:52:56.03#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.03:52:56.03#ibcon#ireg 17 cls_cnt 0 2006.145.03:52:56.03#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.03:52:56.03#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.03:52:56.03#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.03:52:56.05#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.03:52:56.11#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.03:52:56.11#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.03:52:56.11#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.03:52:56.11#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.03:52:56.11$vck44/va=2,7 2006.145.03:52:56.11#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.03:52:56.11#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.03:52:56.11#ibcon#ireg 11 cls_cnt 2 2006.145.03:52:56.11#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.03:52:56.14#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.03:52:56.14#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.03:52:56.16#ibcon#[25=AT02-07\r\n] 2006.145.03:52:56.19#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.03:52:56.19#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.03:52:56.19#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.03:52:56.19#ibcon#ireg 7 cls_cnt 0 2006.145.03:52:56.19#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.03:52:56.31#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.03:52:56.31#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.03:52:56.33#ibcon#[25=USB\r\n] 2006.145.03:52:56.36#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.03:52:56.36#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.03:52:56.36#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.03:52:56.36#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.03:52:56.36$vck44/valo=3,564.99 2006.145.03:52:56.36#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.03:52:56.36#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.03:52:56.36#ibcon#ireg 17 cls_cnt 0 2006.145.03:52:56.36#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.03:52:56.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.03:52:56.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.03:52:56.38#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.03:52:56.42#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.03:52:56.42#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.03:52:56.42#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.03:52:56.42#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.03:52:56.42$vck44/va=3,8 2006.145.03:52:56.42#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.03:52:56.42#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.03:52:56.42#ibcon#ireg 11 cls_cnt 2 2006.145.03:52:56.42#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.03:52:56.48#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.03:52:56.48#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.03:52:56.50#ibcon#[25=AT03-08\r\n] 2006.145.03:52:56.53#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.03:52:56.53#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.03:52:56.53#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.03:52:56.53#ibcon#ireg 7 cls_cnt 0 2006.145.03:52:56.53#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.03:52:56.65#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.03:52:56.65#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.03:52:56.67#ibcon#[25=USB\r\n] 2006.145.03:52:56.70#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.03:52:56.70#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.03:52:56.70#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.03:52:56.70#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.03:52:56.70$vck44/valo=4,624.99 2006.145.03:52:56.70#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.03:52:56.70#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.03:52:56.70#ibcon#ireg 17 cls_cnt 0 2006.145.03:52:56.70#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.03:52:56.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.03:52:56.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.03:52:56.72#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.03:52:56.76#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.03:52:56.76#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.03:52:56.76#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.03:52:56.76#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.03:52:56.76$vck44/va=4,7 2006.145.03:52:56.76#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.03:52:56.76#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.03:52:56.76#ibcon#ireg 11 cls_cnt 2 2006.145.03:52:56.76#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.03:52:56.82#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.03:52:56.82#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.03:52:56.84#ibcon#[25=AT04-07\r\n] 2006.145.03:52:56.87#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.03:52:56.87#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.03:52:56.87#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.03:52:56.87#ibcon#ireg 7 cls_cnt 0 2006.145.03:52:56.87#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.03:52:56.99#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.03:52:56.99#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.03:52:57.01#ibcon#[25=USB\r\n] 2006.145.03:52:57.04#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.03:52:57.04#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.03:52:57.04#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.03:52:57.04#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.03:52:57.04$vck44/valo=5,734.99 2006.145.03:52:57.04#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.03:52:57.04#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.03:52:57.04#ibcon#ireg 17 cls_cnt 0 2006.145.03:52:57.04#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.03:52:57.04#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.03:52:57.04#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.03:52:57.06#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.03:52:57.10#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.03:52:57.10#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.03:52:57.10#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.03:52:57.10#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.03:52:57.10$vck44/va=5,4 2006.145.03:52:57.10#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.03:52:57.10#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.03:52:57.10#ibcon#ireg 11 cls_cnt 2 2006.145.03:52:57.10#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.03:52:57.16#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.03:52:57.16#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.03:52:57.18#ibcon#[25=AT05-04\r\n] 2006.145.03:52:57.21#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.03:52:57.21#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.03:52:57.21#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.03:52:57.21#ibcon#ireg 7 cls_cnt 0 2006.145.03:52:57.21#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.03:52:57.33#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.03:52:57.33#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.03:52:57.35#ibcon#[25=USB\r\n] 2006.145.03:52:57.38#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.03:52:57.38#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.03:52:57.38#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.03:52:57.38#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.03:52:57.38$vck44/valo=6,814.99 2006.145.03:52:57.38#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.03:52:57.38#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.03:52:57.38#ibcon#ireg 17 cls_cnt 0 2006.145.03:52:57.38#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.03:52:57.38#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.03:52:57.38#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.03:52:57.40#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.03:52:57.44#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.03:52:57.44#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.03:52:57.44#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.03:52:57.44#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.03:52:57.44$vck44/va=6,4 2006.145.03:52:57.44#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.03:52:57.44#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.03:52:57.44#ibcon#ireg 11 cls_cnt 2 2006.145.03:52:57.44#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.03:52:57.50#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.03:52:57.50#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.03:52:57.52#ibcon#[25=AT06-04\r\n] 2006.145.03:52:57.55#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.03:52:57.55#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.03:52:57.55#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.03:52:57.55#ibcon#ireg 7 cls_cnt 0 2006.145.03:52:57.55#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.03:52:57.68#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.03:52:57.68#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.03:52:57.69#ibcon#[25=USB\r\n] 2006.145.03:52:57.72#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.03:52:57.72#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.03:52:57.72#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.03:52:57.72#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.03:52:57.72$vck44/valo=7,864.99 2006.145.03:52:57.72#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.03:52:57.72#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.03:52:57.72#ibcon#ireg 17 cls_cnt 0 2006.145.03:52:57.72#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.03:52:57.72#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.03:52:57.72#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.03:52:57.74#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.03:52:57.79#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.03:52:57.79#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.03:52:57.79#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.03:52:57.79#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.03:52:57.79$vck44/va=7,4 2006.145.03:52:57.79#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.03:52:57.79#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.03:52:57.79#ibcon#ireg 11 cls_cnt 2 2006.145.03:52:57.79#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.03:52:57.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.03:52:57.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.03:52:57.85#ibcon#[25=AT07-04\r\n] 2006.145.03:52:57.88#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.03:52:57.88#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.03:52:57.88#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.03:52:57.88#ibcon#ireg 7 cls_cnt 0 2006.145.03:52:57.88#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.03:52:58.00#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.03:52:58.00#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.03:52:58.02#ibcon#[25=USB\r\n] 2006.145.03:52:58.05#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.03:52:58.05#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.03:52:58.05#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.03:52:58.05#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.03:52:58.05$vck44/valo=8,884.99 2006.145.03:52:58.05#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.03:52:58.05#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.03:52:58.05#ibcon#ireg 17 cls_cnt 0 2006.145.03:52:58.05#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.03:52:58.05#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.03:52:58.05#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.03:52:58.07#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.03:52:58.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.03:52:58.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.03:52:58.11#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.03:52:58.11#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.03:52:58.11$vck44/va=8,4 2006.145.03:52:58.11#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.03:52:58.11#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.03:52:58.11#ibcon#ireg 11 cls_cnt 2 2006.145.03:52:58.11#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.03:52:58.17#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.03:52:58.17#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.03:52:58.19#ibcon#[25=AT08-04\r\n] 2006.145.03:52:58.22#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.03:52:58.22#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.03:52:58.22#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.03:52:58.22#ibcon#ireg 7 cls_cnt 0 2006.145.03:52:58.22#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.03:52:58.34#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.03:52:58.34#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.03:52:58.36#ibcon#[25=USB\r\n] 2006.145.03:52:58.39#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.03:52:58.39#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.03:52:58.39#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.03:52:58.39#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.03:52:58.39$vck44/vblo=1,629.99 2006.145.03:52:58.39#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.03:52:58.39#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.03:52:58.39#ibcon#ireg 17 cls_cnt 0 2006.145.03:52:58.39#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.03:52:58.39#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.03:52:58.39#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.03:52:58.41#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.03:52:58.45#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.03:52:58.45#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.03:52:58.45#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.03:52:58.45#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.03:52:58.45$vck44/vb=1,3 2006.145.03:52:58.45#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.03:52:58.45#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.03:52:58.45#ibcon#ireg 11 cls_cnt 2 2006.145.03:52:58.45#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.03:52:58.45#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.03:52:58.45#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.03:52:58.47#ibcon#[27=AT01-03\r\n] 2006.145.03:52:58.50#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.03:52:58.50#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.03:52:58.50#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.03:52:58.50#ibcon#ireg 7 cls_cnt 0 2006.145.03:52:58.50#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.03:52:58.62#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.03:52:58.62#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.03:52:58.64#ibcon#[27=USB\r\n] 2006.145.03:52:58.67#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.03:52:58.67#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.03:52:58.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.03:52:58.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.03:52:58.67$vck44/vblo=2,634.99 2006.145.03:52:58.67#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.03:52:58.67#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.03:52:58.67#ibcon#ireg 17 cls_cnt 0 2006.145.03:52:58.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.03:52:58.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.03:52:58.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.03:52:58.69#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.03:52:58.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.03:52:58.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.03:52:58.73#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.03:52:58.73#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.03:52:58.73$vck44/vb=2,4 2006.145.03:52:58.73#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.03:52:58.73#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.03:52:58.73#ibcon#ireg 11 cls_cnt 2 2006.145.03:52:58.73#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.03:52:58.79#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.03:52:58.79#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.03:52:58.81#ibcon#[27=AT02-04\r\n] 2006.145.03:52:58.84#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.03:52:58.84#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.03:52:58.84#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.03:52:58.84#ibcon#ireg 7 cls_cnt 0 2006.145.03:52:58.84#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.03:52:58.96#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.03:52:58.96#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.03:52:58.98#ibcon#[27=USB\r\n] 2006.145.03:52:59.01#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.03:52:59.01#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.03:52:59.01#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.03:52:59.01#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.03:52:59.01$vck44/vblo=3,649.99 2006.145.03:52:59.01#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.03:52:59.01#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.03:52:59.01#ibcon#ireg 17 cls_cnt 0 2006.145.03:52:59.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.03:52:59.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.03:52:59.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.03:52:59.04#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.03:52:59.08#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.03:52:59.08#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.03:52:59.08#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.03:52:59.08#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.03:52:59.08$vck44/vb=3,4 2006.145.03:52:59.08#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.03:52:59.08#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.03:52:59.08#ibcon#ireg 11 cls_cnt 2 2006.145.03:52:59.08#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.03:52:59.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.03:52:59.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.03:52:59.15#ibcon#[27=AT03-04\r\n] 2006.145.03:52:59.18#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.03:52:59.18#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.03:52:59.18#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.03:52:59.18#ibcon#ireg 7 cls_cnt 0 2006.145.03:52:59.18#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.03:52:59.30#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.03:52:59.30#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.03:52:59.32#ibcon#[27=USB\r\n] 2006.145.03:52:59.35#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.03:52:59.35#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.03:52:59.35#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.03:52:59.35#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.03:52:59.35$vck44/vblo=4,679.99 2006.145.03:52:59.35#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.03:52:59.35#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.03:52:59.35#ibcon#ireg 17 cls_cnt 0 2006.145.03:52:59.35#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.03:52:59.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.03:52:59.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.03:52:59.37#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.03:52:59.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.03:52:59.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.03:52:59.41#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.03:52:59.41#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.03:52:59.41$vck44/vb=4,4 2006.145.03:52:59.41#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.03:52:59.41#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.03:52:59.41#ibcon#ireg 11 cls_cnt 2 2006.145.03:52:59.41#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.03:52:59.47#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.03:52:59.47#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.03:52:59.49#ibcon#[27=AT04-04\r\n] 2006.145.03:52:59.52#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.03:52:59.52#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.03:52:59.52#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.03:52:59.52#ibcon#ireg 7 cls_cnt 0 2006.145.03:52:59.52#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.03:52:59.64#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.03:52:59.64#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.03:52:59.66#ibcon#[27=USB\r\n] 2006.145.03:52:59.69#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.03:52:59.69#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.03:52:59.69#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.03:52:59.69#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.03:52:59.69$vck44/vblo=5,709.99 2006.145.03:52:59.69#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.03:52:59.69#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.03:52:59.69#ibcon#ireg 17 cls_cnt 0 2006.145.03:52:59.69#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.03:52:59.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.03:52:59.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.03:52:59.71#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.03:52:59.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.03:52:59.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.03:52:59.75#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.03:52:59.75#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.03:52:59.75$vck44/vb=5,4 2006.145.03:52:59.75#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.03:52:59.75#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.03:52:59.75#ibcon#ireg 11 cls_cnt 2 2006.145.03:52:59.75#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.03:52:59.81#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.03:52:59.81#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.03:52:59.83#ibcon#[27=AT05-04\r\n] 2006.145.03:52:59.86#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.03:52:59.86#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.03:52:59.86#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.03:52:59.86#ibcon#ireg 7 cls_cnt 0 2006.145.03:52:59.86#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.03:52:59.98#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.03:52:59.98#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.03:53:00.00#ibcon#[27=USB\r\n] 2006.145.03:53:00.03#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.03:53:00.03#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.03:53:00.03#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.03:53:00.03#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.03:53:00.03$vck44/vblo=6,719.99 2006.145.03:53:00.03#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.03:53:00.03#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.03:53:00.03#ibcon#ireg 17 cls_cnt 0 2006.145.03:53:00.03#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.03:53:00.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.03:53:00.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.03:53:00.05#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.03:53:00.09#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.03:53:00.09#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.03:53:00.09#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.03:53:00.09#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.03:53:00.09$vck44/vb=6,4 2006.145.03:53:00.09#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.03:53:00.09#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.03:53:00.09#ibcon#ireg 11 cls_cnt 2 2006.145.03:53:00.09#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.03:53:00.15#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.03:53:00.15#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.03:53:00.17#ibcon#[27=AT06-04\r\n] 2006.145.03:53:00.20#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.03:53:00.20#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.03:53:00.20#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.03:53:00.20#ibcon#ireg 7 cls_cnt 0 2006.145.03:53:00.20#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.03:53:00.32#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.03:53:00.32#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.03:53:00.34#ibcon#[27=USB\r\n] 2006.145.03:53:00.37#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.03:53:00.37#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.03:53:00.37#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.03:53:00.37#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.03:53:00.37$vck44/vblo=7,734.99 2006.145.03:53:00.37#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.03:53:00.37#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.03:53:00.37#ibcon#ireg 17 cls_cnt 0 2006.145.03:53:00.37#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.03:53:00.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.03:53:00.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.03:53:00.39#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.03:53:00.43#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.03:53:00.43#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.03:53:00.43#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.03:53:00.43#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.03:53:00.43$vck44/vb=7,4 2006.145.03:53:00.43#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.03:53:00.43#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.03:53:00.43#ibcon#ireg 11 cls_cnt 2 2006.145.03:53:00.43#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.03:53:00.49#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.03:53:00.49#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.03:53:00.51#ibcon#[27=AT07-04\r\n] 2006.145.03:53:00.54#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.03:53:00.54#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.03:53:00.54#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.03:53:00.54#ibcon#ireg 7 cls_cnt 0 2006.145.03:53:00.54#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.03:53:00.66#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.03:53:00.66#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.03:53:00.68#ibcon#[27=USB\r\n] 2006.145.03:53:00.71#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.03:53:00.71#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.03:53:00.71#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.03:53:00.71#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.03:53:00.71$vck44/vblo=8,744.99 2006.145.03:53:00.71#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.03:53:00.71#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.03:53:00.71#ibcon#ireg 17 cls_cnt 0 2006.145.03:53:00.71#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.03:53:00.71#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.03:53:00.71#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.03:53:00.73#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.03:53:00.77#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.03:53:00.77#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.03:53:00.77#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.03:53:00.77#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.03:53:00.77$vck44/vb=8,4 2006.145.03:53:00.77#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.03:53:00.77#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.03:53:00.77#ibcon#ireg 11 cls_cnt 2 2006.145.03:53:00.77#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.03:53:00.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.03:53:00.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.03:53:00.85#ibcon#[27=AT08-04\r\n] 2006.145.03:53:00.88#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.03:53:00.88#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.03:53:00.88#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.03:53:00.88#ibcon#ireg 7 cls_cnt 0 2006.145.03:53:00.88#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.03:53:01.00#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.03:53:01.00#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.03:53:01.02#ibcon#[27=USB\r\n] 2006.145.03:53:01.05#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.03:53:01.05#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.03:53:01.05#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.03:53:01.05#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.03:53:01.05$vck44/vabw=wide 2006.145.03:53:01.05#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.03:53:01.05#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.03:53:01.05#ibcon#ireg 8 cls_cnt 0 2006.145.03:53:01.05#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.03:53:01.05#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.03:53:01.05#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.03:53:01.07#ibcon#[25=BW32\r\n] 2006.145.03:53:01.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.03:53:01.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.03:53:01.10#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.03:53:01.10#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.03:53:01.10$vck44/vbbw=wide 2006.145.03:53:01.10#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.03:53:01.10#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.03:53:01.10#ibcon#ireg 8 cls_cnt 0 2006.145.03:53:01.10#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.03:53:01.17#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.03:53:01.17#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.03:53:01.19#ibcon#[27=BW32\r\n] 2006.145.03:53:01.22#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.03:53:01.22#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.03:53:01.22#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.03:53:01.22#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.03:53:01.22$setupk4/ifdk4 2006.145.03:53:01.22$ifdk4/lo= 2006.145.03:53:01.22$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.03:53:01.22$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.03:53:01.22$ifdk4/patch= 2006.145.03:53:01.22$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.03:53:01.22$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.03:53:01.22$setupk4/!*+20s 2006.145.03:53:06.04#abcon#<5=/06 4.1 8.1 20.36 601016.7\r\n> 2006.145.03:53:06.06#abcon#{5=INTERFACE CLEAR} 2006.145.03:53:06.12#abcon#[5=S1D000X0/0*\r\n] 2006.145.03:53:15.73$setupk4/"tpicd 2006.145.03:53:15.73$setupk4/echo=off 2006.145.03:53:15.73$setupk4/xlog=off 2006.145.03:53:15.73:!2006.145.03:54:24 2006.145.03:53:22.14#trakl#Source acquired 2006.145.03:53:24.14#flagr#flagr/antenna,acquired 2006.145.03:54:24.00:preob 2006.145.03:54:25.14/onsource/TRACKING 2006.145.03:54:25.14:!2006.145.03:54:34 2006.145.03:54:34.00:"tape 2006.145.03:54:34.00:"st=record 2006.145.03:54:34.00:data_valid=on 2006.145.03:54:34.00:midob 2006.145.03:54:34.14/onsource/TRACKING 2006.145.03:54:34.14/wx/20.35,1016.7,60 2006.145.03:54:34.32/cable/+6.5450E-03 2006.145.03:54:35.41/va/01,08,usb,yes,28,30 2006.145.03:54:35.41/va/02,07,usb,yes,30,30 2006.145.03:54:35.41/va/03,08,usb,yes,27,28 2006.145.03:54:35.41/va/04,07,usb,yes,31,33 2006.145.03:54:35.41/va/05,04,usb,yes,27,27 2006.145.03:54:35.41/va/06,04,usb,yes,30,30 2006.145.03:54:35.41/va/07,04,usb,yes,31,32 2006.145.03:54:35.41/va/08,04,usb,yes,26,31 2006.145.03:54:35.64/valo/01,524.99,yes,locked 2006.145.03:54:35.64/valo/02,534.99,yes,locked 2006.145.03:54:35.64/valo/03,564.99,yes,locked 2006.145.03:54:35.64/valo/04,624.99,yes,locked 2006.145.03:54:35.64/valo/05,734.99,yes,locked 2006.145.03:54:35.64/valo/06,814.99,yes,locked 2006.145.03:54:35.64/valo/07,864.99,yes,locked 2006.145.03:54:35.64/valo/08,884.99,yes,locked 2006.145.03:54:36.73/vb/01,03,usb,yes,35,33 2006.145.03:54:36.73/vb/02,04,usb,yes,31,31 2006.145.03:54:36.73/vb/03,04,usb,yes,28,31 2006.145.03:54:36.73/vb/04,04,usb,yes,32,31 2006.145.03:54:36.73/vb/05,04,usb,yes,25,27 2006.145.03:54:36.73/vb/06,04,usb,yes,29,25 2006.145.03:54:36.73/vb/07,04,usb,yes,29,29 2006.145.03:54:36.73/vb/08,04,usb,yes,26,30 2006.145.03:54:36.96/vblo/01,629.99,yes,locked 2006.145.03:54:36.96/vblo/02,634.99,yes,locked 2006.145.03:54:36.96/vblo/03,649.99,yes,locked 2006.145.03:54:36.96/vblo/04,679.99,yes,locked 2006.145.03:54:36.96/vblo/05,709.99,yes,locked 2006.145.03:54:36.96/vblo/06,719.99,yes,locked 2006.145.03:54:36.96/vblo/07,734.99,yes,locked 2006.145.03:54:36.96/vblo/08,744.99,yes,locked 2006.145.03:54:37.11/vabw/8 2006.145.03:54:37.26/vbbw/8 2006.145.03:54:37.35/xfe/off,on,14.2 2006.145.03:54:37.73/ifatt/23,28,28,28 2006.145.03:54:38.07/fmout-gps/S +5.3E-08 2006.145.03:54:38.12:!2006.145.03:55:24 2006.145.03:55:24.01:data_valid=off 2006.145.03:55:24.02:"et 2006.145.03:55:24.02:!+3s 2006.145.03:55:27.03:"tape 2006.145.03:55:27.04:postob 2006.145.03:55:27.24/cable/+6.5429E-03 2006.145.03:55:27.25/wx/20.35,1016.7,62 2006.145.03:55:27.33/fmout-gps/S +5.4E-08 2006.145.03:55:27.33:scan_name=145-0358,jd0605,260 2006.145.03:55:27.33:source=cta26,033930.94,-014635.8,2000.0,cw 2006.145.03:55:28.13#flagr#flagr/antenna,new-source 2006.145.03:55:28.14:checkk5 2006.145.03:55:28.62/chk_autoobs//k5ts1/ autoobs is running! 2006.145.03:55:29.08/chk_autoobs//k5ts2/ autoobs is running! 2006.145.03:55:29.60/chk_autoobs//k5ts3/ autoobs is running! 2006.145.03:55:30.04/chk_autoobs//k5ts4/ autoobs is running! 2006.145.03:55:30.48/chk_obsdata//k5ts1/T1450354??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.03:55:31.01/chk_obsdata//k5ts2/T1450354??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.03:55:31.47/chk_obsdata//k5ts3/T1450354??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.03:55:31.95/chk_obsdata//k5ts4/T1450354??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.03:55:32.99/k5log//k5ts1_log_newline 2006.145.03:55:33.90/k5log//k5ts2_log_newline 2006.145.03:55:35.11/k5log//k5ts3_log_newline 2006.145.03:55:36.29/k5log//k5ts4_log_newline 2006.145.03:55:36.31/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.03:55:36.31:setupk4=1 2006.145.03:55:36.31$setupk4/echo=on 2006.145.03:55:36.31$setupk4/pcalon 2006.145.03:55:36.31$pcalon/"no phase cal control is implemented here 2006.145.03:55:36.31$setupk4/"tpicd=stop 2006.145.03:55:36.31$setupk4/"rec=synch_on 2006.145.03:55:36.31$setupk4/"rec_mode=128 2006.145.03:55:36.31$setupk4/!* 2006.145.03:55:36.31$setupk4/recpk4 2006.145.03:55:36.31$recpk4/recpatch= 2006.145.03:55:36.31$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.03:55:36.31$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.03:55:36.31$setupk4/vck44 2006.145.03:55:36.31$vck44/valo=1,524.99 2006.145.03:55:36.32#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.03:55:36.32#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.03:55:36.32#ibcon#ireg 17 cls_cnt 0 2006.145.03:55:36.32#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:55:36.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:55:36.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:55:36.36#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.03:55:36.40#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:55:36.40#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:55:36.40#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.03:55:36.40#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.03:55:36.40$vck44/va=1,8 2006.145.03:55:36.40#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.03:55:36.40#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.03:55:36.40#ibcon#ireg 11 cls_cnt 2 2006.145.03:55:36.40#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:55:36.40#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:55:36.40#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:55:36.42#ibcon#[25=AT01-08\r\n] 2006.145.03:55:36.45#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:55:36.45#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:55:36.45#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.03:55:36.45#ibcon#ireg 7 cls_cnt 0 2006.145.03:55:36.45#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:55:36.58#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:55:36.58#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:55:36.59#ibcon#[25=USB\r\n] 2006.145.03:55:36.62#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:55:36.62#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:55:36.62#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.03:55:36.62#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.03:55:36.62$vck44/valo=2,534.99 2006.145.03:55:36.62#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.03:55:36.62#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.03:55:36.62#ibcon#ireg 17 cls_cnt 0 2006.145.03:55:36.62#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:55:36.62#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:55:36.62#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:55:36.66#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.03:55:36.70#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:55:36.70#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:55:36.70#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.03:55:36.70#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.03:55:36.70$vck44/va=2,7 2006.145.03:55:36.70#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.03:55:36.70#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.03:55:36.70#ibcon#ireg 11 cls_cnt 2 2006.145.03:55:36.70#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:55:36.74#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:55:36.74#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:55:36.76#ibcon#[25=AT02-07\r\n] 2006.145.03:55:36.79#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:55:36.79#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:55:36.79#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.03:55:36.79#ibcon#ireg 7 cls_cnt 0 2006.145.03:55:36.79#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:55:36.91#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:55:36.91#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:55:36.93#ibcon#[25=USB\r\n] 2006.145.03:55:36.96#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:55:36.96#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:55:36.96#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.03:55:36.96#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.03:55:36.96$vck44/valo=3,564.99 2006.145.03:55:36.96#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.03:55:36.96#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.03:55:36.96#ibcon#ireg 17 cls_cnt 0 2006.145.03:55:36.96#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:55:36.96#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:55:36.96#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:55:36.98#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.03:55:37.02#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:55:37.02#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:55:37.02#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.03:55:37.02#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.03:55:37.02$vck44/va=3,8 2006.145.03:55:37.02#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.03:55:37.02#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.03:55:37.02#ibcon#ireg 11 cls_cnt 2 2006.145.03:55:37.02#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:55:37.08#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:55:37.08#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:55:37.10#ibcon#[25=AT03-08\r\n] 2006.145.03:55:37.13#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:55:37.13#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:55:37.13#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.03:55:37.13#ibcon#ireg 7 cls_cnt 0 2006.145.03:55:37.13#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:55:37.25#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:55:37.25#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:55:37.27#ibcon#[25=USB\r\n] 2006.145.03:55:37.30#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:55:37.30#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:55:37.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.03:55:37.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.03:55:37.30$vck44/valo=4,624.99 2006.145.03:55:37.30#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.03:55:37.30#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.03:55:37.30#ibcon#ireg 17 cls_cnt 0 2006.145.03:55:37.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.03:55:37.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.03:55:37.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.03:55:37.32#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.03:55:37.36#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.03:55:37.36#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.03:55:37.36#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.03:55:37.36#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.03:55:37.36$vck44/va=4,7 2006.145.03:55:37.36#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.03:55:37.36#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.03:55:37.36#ibcon#ireg 11 cls_cnt 2 2006.145.03:55:37.36#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.03:55:37.42#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.03:55:37.42#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.03:55:37.44#ibcon#[25=AT04-07\r\n] 2006.145.03:55:37.47#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.03:55:37.47#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.03:55:37.47#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.03:55:37.47#ibcon#ireg 7 cls_cnt 0 2006.145.03:55:37.47#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.03:55:37.59#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.03:55:37.59#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.03:55:37.61#ibcon#[25=USB\r\n] 2006.145.03:55:37.64#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.03:55:37.64#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.03:55:37.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.03:55:37.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.03:55:37.64$vck44/valo=5,734.99 2006.145.03:55:37.64#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.03:55:37.64#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.03:55:37.64#ibcon#ireg 17 cls_cnt 0 2006.145.03:55:37.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:55:37.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:55:37.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:55:37.66#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.03:55:37.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:55:37.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:55:37.70#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.03:55:37.70#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.03:55:37.70$vck44/va=5,4 2006.145.03:55:37.70#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.03:55:37.70#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.03:55:37.70#ibcon#ireg 11 cls_cnt 2 2006.145.03:55:37.70#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.03:55:37.76#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.03:55:37.76#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.03:55:37.78#ibcon#[25=AT05-04\r\n] 2006.145.03:55:37.81#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.03:55:37.81#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.03:55:37.81#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.03:55:37.81#ibcon#ireg 7 cls_cnt 0 2006.145.03:55:37.81#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.03:55:37.93#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.03:55:37.93#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.03:55:37.95#ibcon#[25=USB\r\n] 2006.145.03:55:37.98#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.03:55:37.98#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.03:55:37.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.03:55:37.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.03:55:37.98$vck44/valo=6,814.99 2006.145.03:55:37.98#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.03:55:37.98#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.03:55:37.98#ibcon#ireg 17 cls_cnt 0 2006.145.03:55:37.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:55:37.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:55:37.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:55:38.01#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.03:55:38.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:55:38.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:55:38.04#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.03:55:38.04#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.03:55:38.04$vck44/va=6,4 2006.145.03:55:38.04#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.03:55:38.04#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.03:55:38.04#ibcon#ireg 11 cls_cnt 2 2006.145.03:55:38.04#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.03:55:38.10#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.03:55:38.10#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.03:55:38.13#ibcon#[25=AT06-04\r\n] 2006.145.03:55:38.16#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.03:55:38.16#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.03:55:38.16#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.03:55:38.16#ibcon#ireg 7 cls_cnt 0 2006.145.03:55:38.16#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.03:55:38.28#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.03:55:38.28#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.03:55:38.30#ibcon#[25=USB\r\n] 2006.145.03:55:38.33#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.03:55:38.33#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.03:55:38.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.03:55:38.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.03:55:38.33$vck44/valo=7,864.99 2006.145.03:55:38.33#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.03:55:38.33#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.03:55:38.33#ibcon#ireg 17 cls_cnt 0 2006.145.03:55:38.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:55:38.33#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:55:38.33#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:55:38.35#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.03:55:38.39#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:55:38.39#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:55:38.39#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.03:55:38.39#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.03:55:38.39$vck44/va=7,4 2006.145.03:55:38.39#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.03:55:38.39#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.03:55:38.39#ibcon#ireg 11 cls_cnt 2 2006.145.03:55:38.39#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:55:38.45#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:55:38.45#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:55:38.47#ibcon#[25=AT07-04\r\n] 2006.145.03:55:38.50#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:55:38.50#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:55:38.50#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.03:55:38.50#ibcon#ireg 7 cls_cnt 0 2006.145.03:55:38.50#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:55:38.62#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:55:38.62#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:55:38.64#ibcon#[25=USB\r\n] 2006.145.03:55:38.67#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:55:38.67#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:55:38.67#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.03:55:38.67#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.03:55:38.67$vck44/valo=8,884.99 2006.145.03:55:38.67#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.03:55:38.67#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.03:55:38.67#ibcon#ireg 17 cls_cnt 0 2006.145.03:55:38.67#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:55:38.67#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:55:38.67#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:55:38.69#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.03:55:38.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:55:38.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:55:38.73#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.03:55:38.73#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.03:55:38.73$vck44/va=8,4 2006.145.03:55:38.73#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.03:55:38.73#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.03:55:38.73#ibcon#ireg 11 cls_cnt 2 2006.145.03:55:38.73#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:55:38.79#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:55:38.79#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:55:38.81#ibcon#[25=AT08-04\r\n] 2006.145.03:55:38.81#abcon#<5=/06 4.2 6.8 20.35 641016.7\r\n> 2006.145.03:55:38.83#abcon#{5=INTERFACE CLEAR} 2006.145.03:55:38.84#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:55:38.84#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:55:38.84#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.03:55:38.84#ibcon#ireg 7 cls_cnt 0 2006.145.03:55:38.84#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:55:38.89#abcon#[5=S1D000X0/0*\r\n] 2006.145.03:55:38.96#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:55:38.96#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:55:38.98#ibcon#[25=USB\r\n] 2006.145.03:55:39.01#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:55:39.01#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:55:39.01#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.03:55:39.01#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.03:55:39.01$vck44/vblo=1,629.99 2006.145.03:55:39.01#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.03:55:39.01#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.03:55:39.01#ibcon#ireg 17 cls_cnt 0 2006.145.03:55:39.01#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:55:39.01#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:55:39.01#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:55:39.03#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.03:55:39.07#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:55:39.07#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.03:55:39.07#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.03:55:39.07#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.03:55:39.07$vck44/vb=1,3 2006.145.03:55:39.07#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.03:55:39.07#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.03:55:39.07#ibcon#ireg 11 cls_cnt 2 2006.145.03:55:39.07#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:55:39.07#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:55:39.07#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:55:39.09#ibcon#[27=AT01-03\r\n] 2006.145.03:55:39.12#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:55:39.12#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.03:55:39.12#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.03:55:39.12#ibcon#ireg 7 cls_cnt 0 2006.145.03:55:39.12#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:55:39.24#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:55:39.24#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:55:39.26#ibcon#[27=USB\r\n] 2006.145.03:55:39.29#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:55:39.29#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.03:55:39.29#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.03:55:39.29#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.03:55:39.29$vck44/vblo=2,634.99 2006.145.03:55:39.29#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.03:55:39.29#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.03:55:39.29#ibcon#ireg 17 cls_cnt 0 2006.145.03:55:39.29#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:55:39.29#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:55:39.29#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:55:39.31#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.03:55:39.35#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:55:39.35#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.03:55:39.35#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.03:55:39.35#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.03:55:39.35$vck44/vb=2,4 2006.145.03:55:39.35#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.03:55:39.35#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.03:55:39.35#ibcon#ireg 11 cls_cnt 2 2006.145.03:55:39.35#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:55:39.41#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:55:39.41#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:55:39.43#ibcon#[27=AT02-04\r\n] 2006.145.03:55:39.46#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:55:39.46#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.03:55:39.46#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.03:55:39.46#ibcon#ireg 7 cls_cnt 0 2006.145.03:55:39.46#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:55:39.58#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:55:39.58#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:55:39.60#ibcon#[27=USB\r\n] 2006.145.03:55:39.63#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:55:39.63#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.03:55:39.63#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.03:55:39.63#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.03:55:39.63$vck44/vblo=3,649.99 2006.145.03:55:39.63#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.03:55:39.63#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.03:55:39.63#ibcon#ireg 17 cls_cnt 0 2006.145.03:55:39.63#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:55:39.63#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:55:39.63#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:55:39.65#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.03:55:39.69#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:55:39.69#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.03:55:39.69#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.03:55:39.69#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.03:55:39.69$vck44/vb=3,4 2006.145.03:55:39.69#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.03:55:39.69#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.03:55:39.69#ibcon#ireg 11 cls_cnt 2 2006.145.03:55:39.69#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:55:39.75#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:55:39.75#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:55:39.77#ibcon#[27=AT03-04\r\n] 2006.145.03:55:39.80#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:55:39.80#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.03:55:39.80#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.03:55:39.80#ibcon#ireg 7 cls_cnt 0 2006.145.03:55:39.80#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:55:39.92#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:55:39.92#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:55:39.94#ibcon#[27=USB\r\n] 2006.145.03:55:39.97#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:55:39.97#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.03:55:39.97#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.03:55:39.97#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.03:55:39.97$vck44/vblo=4,679.99 2006.145.03:55:39.97#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.03:55:39.97#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.03:55:39.97#ibcon#ireg 17 cls_cnt 0 2006.145.03:55:39.97#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.03:55:39.97#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.03:55:39.97#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.03:55:39.99#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.03:55:40.03#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.03:55:40.03#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.03:55:40.03#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.03:55:40.03#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.03:55:40.03$vck44/vb=4,4 2006.145.03:55:40.03#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.03:55:40.03#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.03:55:40.03#ibcon#ireg 11 cls_cnt 2 2006.145.03:55:40.03#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.03:55:40.09#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.03:55:40.09#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.03:55:40.11#ibcon#[27=AT04-04\r\n] 2006.145.03:55:40.14#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.03:55:40.14#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.03:55:40.14#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.03:55:40.14#ibcon#ireg 7 cls_cnt 0 2006.145.03:55:40.14#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.03:55:40.26#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.03:55:40.26#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.03:55:40.28#ibcon#[27=USB\r\n] 2006.145.03:55:40.31#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.03:55:40.31#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.03:55:40.31#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.03:55:40.31#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.03:55:40.31$vck44/vblo=5,709.99 2006.145.03:55:40.31#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.03:55:40.31#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.03:55:40.31#ibcon#ireg 17 cls_cnt 0 2006.145.03:55:40.31#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:55:40.31#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:55:40.31#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:55:40.33#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.03:55:40.37#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:55:40.37#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.03:55:40.37#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.03:55:40.37#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.03:55:40.37$vck44/vb=5,4 2006.145.03:55:40.37#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.03:55:40.37#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.03:55:40.37#ibcon#ireg 11 cls_cnt 2 2006.145.03:55:40.37#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.03:55:40.43#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.03:55:40.43#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.03:55:40.45#ibcon#[27=AT05-04\r\n] 2006.145.03:55:40.48#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.03:55:40.48#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.03:55:40.48#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.03:55:40.48#ibcon#ireg 7 cls_cnt 0 2006.145.03:55:40.48#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.03:55:40.60#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.03:55:40.60#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.03:55:40.62#ibcon#[27=USB\r\n] 2006.145.03:55:40.65#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.03:55:40.65#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.03:55:40.65#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.03:55:40.65#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.03:55:40.65$vck44/vblo=6,719.99 2006.145.03:55:40.65#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.03:55:40.65#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.03:55:40.65#ibcon#ireg 17 cls_cnt 0 2006.145.03:55:40.65#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:55:40.65#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:55:40.65#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:55:40.67#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.03:55:40.71#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:55:40.71#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.03:55:40.71#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.03:55:40.71#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.03:55:40.71$vck44/vb=6,4 2006.145.03:55:40.71#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.03:55:40.71#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.03:55:40.71#ibcon#ireg 11 cls_cnt 2 2006.145.03:55:40.71#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.03:55:40.77#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.03:55:40.77#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.03:55:40.79#ibcon#[27=AT06-04\r\n] 2006.145.03:55:40.82#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.03:55:40.82#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.03:55:40.82#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.03:55:40.82#ibcon#ireg 7 cls_cnt 0 2006.145.03:55:40.82#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.03:55:40.94#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.03:55:40.94#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.03:55:40.96#ibcon#[27=USB\r\n] 2006.145.03:55:40.99#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.03:55:40.99#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.03:55:40.99#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.03:55:40.99#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.03:55:40.99$vck44/vblo=7,734.99 2006.145.03:55:40.99#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.03:55:40.99#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.03:55:40.99#ibcon#ireg 17 cls_cnt 0 2006.145.03:55:40.99#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:55:40.99#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:55:40.99#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:55:41.01#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.03:55:41.05#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:55:41.05#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.03:55:41.05#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.03:55:41.05#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.03:55:41.05$vck44/vb=7,4 2006.145.03:55:41.05#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.03:55:41.05#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.03:55:41.05#ibcon#ireg 11 cls_cnt 2 2006.145.03:55:41.05#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:55:41.11#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:55:41.11#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:55:41.13#ibcon#[27=AT07-04\r\n] 2006.145.03:55:41.16#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:55:41.16#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.03:55:41.16#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.03:55:41.16#ibcon#ireg 7 cls_cnt 0 2006.145.03:55:41.16#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:55:41.28#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:55:41.28#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:55:41.30#ibcon#[27=USB\r\n] 2006.145.03:55:41.33#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:55:41.33#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.03:55:41.33#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.03:55:41.33#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.03:55:41.33$vck44/vblo=8,744.99 2006.145.03:55:41.33#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.03:55:41.33#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.03:55:41.33#ibcon#ireg 17 cls_cnt 0 2006.145.03:55:41.33#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:55:41.33#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:55:41.33#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:55:41.35#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.03:55:41.39#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:55:41.39#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.03:55:41.39#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.03:55:41.39#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.03:55:41.39$vck44/vb=8,4 2006.145.03:55:41.39#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.03:55:41.39#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.03:55:41.39#ibcon#ireg 11 cls_cnt 2 2006.145.03:55:41.39#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:55:41.45#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:55:41.45#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:55:41.47#ibcon#[27=AT08-04\r\n] 2006.145.03:55:41.50#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:55:41.50#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.03:55:41.50#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.03:55:41.50#ibcon#ireg 7 cls_cnt 0 2006.145.03:55:41.50#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:55:41.62#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:55:41.62#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:55:41.64#ibcon#[27=USB\r\n] 2006.145.03:55:41.67#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:55:41.67#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.03:55:41.67#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.03:55:41.67#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.03:55:41.67$vck44/vabw=wide 2006.145.03:55:41.67#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.03:55:41.67#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.03:55:41.67#ibcon#ireg 8 cls_cnt 0 2006.145.03:55:41.67#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:55:41.67#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:55:41.67#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:55:41.69#ibcon#[25=BW32\r\n] 2006.145.03:55:41.72#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:55:41.72#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.03:55:41.72#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.03:55:41.72#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.03:55:41.72$vck44/vbbw=wide 2006.145.03:55:41.72#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.03:55:41.72#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.03:55:41.72#ibcon#ireg 8 cls_cnt 0 2006.145.03:55:41.72#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.03:55:41.79#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.03:55:41.79#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.03:55:41.81#ibcon#[27=BW32\r\n] 2006.145.03:55:41.84#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.03:55:41.84#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.03:55:41.84#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.03:55:41.84#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.03:55:41.84$setupk4/ifdk4 2006.145.03:55:41.84$ifdk4/lo= 2006.145.03:55:41.84$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.03:55:41.84$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.03:55:41.84$ifdk4/patch= 2006.145.03:55:41.84$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.03:55:41.84$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.03:55:41.84$setupk4/!*+20s 2006.145.03:55:48.98#abcon#<5=/06 4.1 6.8 20.35 671016.7\r\n> 2006.145.03:55:49.00#abcon#{5=INTERFACE CLEAR} 2006.145.03:55:49.08#abcon#[5=S1D000X0/0*\r\n] 2006.145.03:55:56.32$setupk4/"tpicd 2006.145.03:55:56.32$setupk4/echo=off 2006.145.03:55:56.32$setupk4/xlog=off 2006.145.03:55:56.32:!2006.145.03:58:06 2006.145.03:56:28.13#trakl#Source acquired 2006.145.03:56:29.13#flagr#flagr/antenna,acquired 2006.145.03:58:06.00:preob 2006.145.03:58:06.14/onsource/TRACKING 2006.145.03:58:06.14:!2006.145.03:58:16 2006.145.03:58:16.00:"tape 2006.145.03:58:16.00:"st=record 2006.145.03:58:16.00:data_valid=on 2006.145.03:58:16.00:midob 2006.145.03:58:17.14/onsource/TRACKING 2006.145.03:58:17.14/wx/20.40,1016.7,63 2006.145.03:58:17.37/cable/+6.5476E-03 2006.145.03:58:18.46/va/01,08,usb,yes,28,30 2006.145.03:58:18.46/va/02,07,usb,yes,30,31 2006.145.03:58:18.46/va/03,08,usb,yes,27,28 2006.145.03:58:18.46/va/04,07,usb,yes,31,33 2006.145.03:58:18.46/va/05,04,usb,yes,27,28 2006.145.03:58:18.46/va/06,04,usb,yes,30,30 2006.145.03:58:18.46/va/07,04,usb,yes,31,32 2006.145.03:58:18.46/va/08,04,usb,yes,26,32 2006.145.03:58:18.69/valo/01,524.99,yes,locked 2006.145.03:58:18.69/valo/02,534.99,yes,locked 2006.145.03:58:18.69/valo/03,564.99,yes,locked 2006.145.03:58:18.69/valo/04,624.99,yes,locked 2006.145.03:58:18.69/valo/05,734.99,yes,locked 2006.145.03:58:18.69/valo/06,814.99,yes,locked 2006.145.03:58:18.69/valo/07,864.99,yes,locked 2006.145.03:58:18.69/valo/08,884.99,yes,locked 2006.145.03:58:19.78/vb/01,03,usb,yes,36,33 2006.145.03:58:19.78/vb/02,04,usb,yes,31,31 2006.145.03:58:19.78/vb/03,04,usb,yes,28,31 2006.145.03:58:19.78/vb/04,04,usb,yes,32,31 2006.145.03:58:19.78/vb/05,04,usb,yes,25,27 2006.145.03:58:19.78/vb/06,04,usb,yes,29,26 2006.145.03:58:19.78/vb/07,04,usb,yes,29,29 2006.145.03:58:19.78/vb/08,04,usb,yes,27,30 2006.145.03:58:20.01/vblo/01,629.99,yes,locked 2006.145.03:58:20.01/vblo/02,634.99,yes,locked 2006.145.03:58:20.01/vblo/03,649.99,yes,locked 2006.145.03:58:20.01/vblo/04,679.99,yes,locked 2006.145.03:58:20.01/vblo/05,709.99,yes,locked 2006.145.03:58:20.01/vblo/06,719.99,yes,locked 2006.145.03:58:20.01/vblo/07,734.99,yes,locked 2006.145.03:58:20.01/vblo/08,744.99,yes,locked 2006.145.03:58:20.16/vabw/8 2006.145.03:58:20.31/vbbw/8 2006.145.03:58:20.40/xfe/off,on,14.7 2006.145.03:58:20.78/ifatt/23,28,28,28 2006.145.03:58:21.07/fmout-gps/S +5.3E-08 2006.145.03:58:21.11:!2006.145.04:02:36 2006.145.04:02:36.01:data_valid=off 2006.145.04:02:36.02:"et 2006.145.04:02:36.02:!+3s 2006.145.04:02:39.03:"tape 2006.145.04:02:39.03:postob 2006.145.04:02:39.20/cable/+6.5450E-03 2006.145.04:02:39.20/wx/20.40,1016.7,62 2006.145.04:02:39.26/fmout-gps/S +5.4E-08 2006.145.04:02:39.26:scan_name=145-0411,jd0605,80 2006.145.04:02:39.27:source=0528+134,053056.42,133155.1,2000.0,cw 2006.145.04:02:40.14#flagr#flagr/antenna,new-source 2006.145.04:02:40.15:checkk5 2006.145.04:02:40.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.04:02:41.04/chk_autoobs//k5ts2/ autoobs is running! 2006.145.04:02:41.53/chk_autoobs//k5ts3/ autoobs is running! 2006.145.04:02:42.01/chk_autoobs//k5ts4/ autoobs is running! 2006.145.04:02:42.49/chk_obsdata//k5ts1/T1450358??a.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.145.04:02:43.24/chk_obsdata//k5ts2/T1450358??b.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.145.04:02:43.69/chk_obsdata//k5ts3/T1450358??c.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.145.04:02:44.16/chk_obsdata//k5ts4/T1450358??d.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.145.04:02:45.01/k5log//k5ts1_log_newline 2006.145.04:02:45.84/k5log//k5ts2_log_newline 2006.145.04:02:46.60/k5log//k5ts3_log_newline 2006.145.04:02:47.52/k5log//k5ts4_log_newline 2006.145.04:02:47.54/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.04:02:47.54:setupk4=1 2006.145.04:02:47.54$setupk4/echo=on 2006.145.04:02:47.54$setupk4/pcalon 2006.145.04:02:47.54$pcalon/"no phase cal control is implemented here 2006.145.04:02:47.54$setupk4/"tpicd=stop 2006.145.04:02:47.54$setupk4/"rec=synch_on 2006.145.04:02:47.54$setupk4/"rec_mode=128 2006.145.04:02:47.54$setupk4/!* 2006.145.04:02:47.54$setupk4/recpk4 2006.145.04:02:47.54$recpk4/recpatch= 2006.145.04:02:47.54$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.04:02:47.54$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.04:02:47.54$setupk4/vck44 2006.145.04:02:47.54$vck44/valo=1,524.99 2006.145.04:02:47.54#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.04:02:47.54#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.04:02:47.54#ibcon#ireg 17 cls_cnt 0 2006.145.04:02:47.54#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:02:47.54#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:02:47.54#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:02:47.59#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.04:02:47.63#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:02:47.63#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:02:47.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.04:02:47.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.04:02:47.63$vck44/va=1,8 2006.145.04:02:47.63#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.04:02:47.63#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.04:02:47.63#ibcon#ireg 11 cls_cnt 2 2006.145.04:02:47.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:02:47.63#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:02:47.63#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:02:47.65#ibcon#[25=AT01-08\r\n] 2006.145.04:02:47.68#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:02:47.68#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:02:47.68#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.04:02:47.68#ibcon#ireg 7 cls_cnt 0 2006.145.04:02:47.68#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:02:47.81#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:02:47.81#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:02:47.82#ibcon#[25=USB\r\n] 2006.145.04:02:47.85#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:02:47.85#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:02:47.85#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.04:02:47.85#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.04:02:47.85$vck44/valo=2,534.99 2006.145.04:02:47.85#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.04:02:47.85#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.04:02:47.85#ibcon#ireg 17 cls_cnt 0 2006.145.04:02:47.85#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:02:47.85#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:02:47.85#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:02:47.88#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.04:02:47.92#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:02:47.92#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:02:47.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.04:02:47.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.04:02:47.92$vck44/va=2,7 2006.145.04:02:47.92#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.04:02:47.92#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.04:02:47.92#ibcon#ireg 11 cls_cnt 2 2006.145.04:02:47.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:02:47.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:02:47.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:02:47.99#ibcon#[25=AT02-07\r\n] 2006.145.04:02:48.02#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:02:48.02#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:02:48.02#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.04:02:48.02#ibcon#ireg 7 cls_cnt 0 2006.145.04:02:48.02#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:02:48.14#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:02:48.14#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:02:48.16#ibcon#[25=USB\r\n] 2006.145.04:02:48.19#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:02:48.19#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:02:48.19#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.04:02:48.19#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.04:02:48.19$vck44/valo=3,564.99 2006.145.04:02:48.19#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.04:02:48.19#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.04:02:48.19#ibcon#ireg 17 cls_cnt 0 2006.145.04:02:48.19#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:02:48.19#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:02:48.19#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:02:48.21#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.04:02:48.25#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:02:48.25#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:02:48.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.04:02:48.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.04:02:48.25$vck44/va=3,8 2006.145.04:02:48.25#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.04:02:48.25#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.04:02:48.25#ibcon#ireg 11 cls_cnt 2 2006.145.04:02:48.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:02:48.31#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:02:48.31#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:02:48.33#ibcon#[25=AT03-08\r\n] 2006.145.04:02:48.36#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:02:48.36#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:02:48.36#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.04:02:48.36#ibcon#ireg 7 cls_cnt 0 2006.145.04:02:48.36#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:02:48.48#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:02:48.48#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:02:48.50#ibcon#[25=USB\r\n] 2006.145.04:02:48.53#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:02:48.53#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:02:48.53#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.04:02:48.53#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.04:02:48.53$vck44/valo=4,624.99 2006.145.04:02:48.53#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.04:02:48.53#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.04:02:48.53#ibcon#ireg 17 cls_cnt 0 2006.145.04:02:48.53#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:02:48.53#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:02:48.53#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:02:48.55#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.04:02:48.59#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:02:48.59#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:02:48.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.04:02:48.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.04:02:48.59$vck44/va=4,7 2006.145.04:02:48.59#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.04:02:48.59#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.04:02:48.59#ibcon#ireg 11 cls_cnt 2 2006.145.04:02:48.59#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.04:02:48.65#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.04:02:48.65#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.04:02:48.67#ibcon#[25=AT04-07\r\n] 2006.145.04:02:48.70#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.04:02:48.70#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.04:02:48.70#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.04:02:48.70#ibcon#ireg 7 cls_cnt 0 2006.145.04:02:48.70#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.04:02:48.82#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.04:02:48.82#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.04:02:48.84#ibcon#[25=USB\r\n] 2006.145.04:02:48.87#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.04:02:48.87#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.04:02:48.87#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.04:02:48.87#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.04:02:48.87$vck44/valo=5,734.99 2006.145.04:02:48.87#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.04:02:48.87#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.04:02:48.87#ibcon#ireg 17 cls_cnt 0 2006.145.04:02:48.87#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:02:48.87#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:02:48.87#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:02:48.89#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.04:02:48.93#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:02:48.93#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:02:48.93#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.04:02:48.93#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.04:02:48.93$vck44/va=5,4 2006.145.04:02:48.93#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.04:02:48.93#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.04:02:48.93#ibcon#ireg 11 cls_cnt 2 2006.145.04:02:48.93#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.04:02:48.99#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.04:02:48.99#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.04:02:49.01#ibcon#[25=AT05-04\r\n] 2006.145.04:02:49.04#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.04:02:49.04#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.04:02:49.04#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.04:02:49.04#ibcon#ireg 7 cls_cnt 0 2006.145.04:02:49.04#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.04:02:49.18#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.04:02:49.18#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.04:02:49.19#ibcon#[25=USB\r\n] 2006.145.04:02:49.22#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.04:02:49.22#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.04:02:49.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.04:02:49.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.04:02:49.22$vck44/valo=6,814.99 2006.145.04:02:49.22#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.04:02:49.22#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.04:02:49.22#ibcon#ireg 17 cls_cnt 0 2006.145.04:02:49.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:02:49.22#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:02:49.22#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:02:49.24#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.04:02:49.28#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:02:49.28#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:02:49.28#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.04:02:49.28#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.04:02:49.28$vck44/va=6,4 2006.145.04:02:49.28#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.04:02:49.28#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.04:02:49.28#ibcon#ireg 11 cls_cnt 2 2006.145.04:02:49.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:02:49.34#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:02:49.34#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:02:49.36#ibcon#[25=AT06-04\r\n] 2006.145.04:02:49.39#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:02:49.39#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:02:49.39#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.04:02:49.39#ibcon#ireg 7 cls_cnt 0 2006.145.04:02:49.39#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:02:49.51#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:02:49.51#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:02:49.53#ibcon#[25=USB\r\n] 2006.145.04:02:49.56#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:02:49.56#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:02:49.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.04:02:49.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.04:02:49.56$vck44/valo=7,864.99 2006.145.04:02:49.56#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.04:02:49.56#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.04:02:49.56#ibcon#ireg 17 cls_cnt 0 2006.145.04:02:49.56#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:02:49.56#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:02:49.56#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:02:49.58#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.04:02:49.62#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:02:49.62#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:02:49.62#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.04:02:49.62#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.04:02:49.62$vck44/va=7,4 2006.145.04:02:49.62#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.04:02:49.62#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.04:02:49.62#ibcon#ireg 11 cls_cnt 2 2006.145.04:02:49.62#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:02:49.68#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:02:49.68#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:02:49.70#ibcon#[25=AT07-04\r\n] 2006.145.04:02:49.73#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:02:49.73#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:02:49.73#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.04:02:49.73#ibcon#ireg 7 cls_cnt 0 2006.145.04:02:49.73#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:02:49.85#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:02:49.85#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:02:49.87#ibcon#[25=USB\r\n] 2006.145.04:02:49.90#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:02:49.90#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:02:49.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.04:02:49.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.04:02:49.90$vck44/valo=8,884.99 2006.145.04:02:49.90#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.04:02:49.90#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.04:02:49.90#ibcon#ireg 17 cls_cnt 0 2006.145.04:02:49.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.04:02:49.90#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.04:02:49.90#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.04:02:49.92#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.04:02:49.96#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.04:02:49.96#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.04:02:49.96#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.04:02:49.96#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.04:02:49.96$vck44/va=8,4 2006.145.04:02:49.96#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.04:02:49.96#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.04:02:49.96#ibcon#ireg 11 cls_cnt 2 2006.145.04:02:49.96#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.04:02:50.02#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.04:02:50.02#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.04:02:50.04#ibcon#[25=AT08-04\r\n] 2006.145.04:02:50.07#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.04:02:50.07#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.04:02:50.07#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.04:02:50.07#ibcon#ireg 7 cls_cnt 0 2006.145.04:02:50.07#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.04:02:50.19#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.04:02:50.19#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.04:02:50.21#ibcon#[25=USB\r\n] 2006.145.04:02:50.24#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.04:02:50.24#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.04:02:50.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.04:02:50.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.04:02:50.24$vck44/vblo=1,629.99 2006.145.04:02:50.24#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.04:02:50.24#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.04:02:50.24#ibcon#ireg 17 cls_cnt 0 2006.145.04:02:50.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.04:02:50.24#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.04:02:50.24#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.04:02:50.26#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.04:02:50.30#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.04:02:50.30#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.04:02:50.30#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.04:02:50.30#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.04:02:50.30$vck44/vb=1,3 2006.145.04:02:50.30#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.04:02:50.30#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.04:02:50.30#ibcon#ireg 11 cls_cnt 2 2006.145.04:02:50.30#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.04:02:50.30#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.04:02:50.30#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.04:02:50.32#ibcon#[27=AT01-03\r\n] 2006.145.04:02:50.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.04:02:50.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.04:02:50.35#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.04:02:50.35#ibcon#ireg 7 cls_cnt 0 2006.145.04:02:50.35#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.04:02:50.47#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.04:02:50.47#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.04:02:50.49#ibcon#[27=USB\r\n] 2006.145.04:02:50.52#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.04:02:50.52#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.04:02:50.52#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.04:02:50.52#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.04:02:50.52$vck44/vblo=2,634.99 2006.145.04:02:50.52#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.04:02:50.52#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.04:02:50.52#ibcon#ireg 17 cls_cnt 0 2006.145.04:02:50.52#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:02:50.52#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:02:50.52#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:02:50.54#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.04:02:50.58#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:02:50.58#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:02:50.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.04:02:50.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.04:02:50.58$vck44/vb=2,4 2006.145.04:02:50.58#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.04:02:50.58#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.04:02:50.58#ibcon#ireg 11 cls_cnt 2 2006.145.04:02:50.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:02:50.64#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:02:50.64#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:02:50.66#ibcon#[27=AT02-04\r\n] 2006.145.04:02:50.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:02:50.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:02:50.69#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.04:02:50.69#ibcon#ireg 7 cls_cnt 0 2006.145.04:02:50.69#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:02:50.81#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:02:50.81#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:02:50.83#ibcon#[27=USB\r\n] 2006.145.04:02:50.86#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:02:50.86#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:02:50.86#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.04:02:50.86#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.04:02:50.86$vck44/vblo=3,649.99 2006.145.04:02:50.86#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.04:02:50.86#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.04:02:50.86#ibcon#ireg 17 cls_cnt 0 2006.145.04:02:50.86#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:02:50.86#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:02:50.86#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:02:50.88#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.04:02:50.92#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:02:50.92#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:02:50.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.04:02:50.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.04:02:50.92$vck44/vb=3,4 2006.145.04:02:50.92#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.04:02:50.92#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.04:02:50.92#ibcon#ireg 11 cls_cnt 2 2006.145.04:02:50.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:02:50.98#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:02:50.98#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:02:51.00#ibcon#[27=AT03-04\r\n] 2006.145.04:02:51.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:02:51.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:02:51.03#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.04:02:51.03#ibcon#ireg 7 cls_cnt 0 2006.145.04:02:51.03#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:02:51.15#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:02:51.15#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:02:51.17#ibcon#[27=USB\r\n] 2006.145.04:02:51.20#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:02:51.20#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:02:51.20#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.04:02:51.20#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.04:02:51.20$vck44/vblo=4,679.99 2006.145.04:02:51.20#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.04:02:51.20#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.04:02:51.20#ibcon#ireg 17 cls_cnt 0 2006.145.04:02:51.20#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:02:51.20#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:02:51.20#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:02:51.22#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.04:02:51.26#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:02:51.26#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:02:51.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.04:02:51.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.04:02:51.26$vck44/vb=4,4 2006.145.04:02:51.26#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.04:02:51.26#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.04:02:51.26#ibcon#ireg 11 cls_cnt 2 2006.145.04:02:51.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:02:51.32#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:02:51.32#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:02:51.34#ibcon#[27=AT04-04\r\n] 2006.145.04:02:51.39#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:02:51.39#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:02:51.39#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.04:02:51.39#ibcon#ireg 7 cls_cnt 0 2006.145.04:02:51.39#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:02:51.51#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:02:51.51#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:02:51.53#ibcon#[27=USB\r\n] 2006.145.04:02:51.56#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:02:51.56#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:02:51.56#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.04:02:51.56#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.04:02:51.56$vck44/vblo=5,709.99 2006.145.04:02:51.56#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.04:02:51.56#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.04:02:51.56#ibcon#ireg 17 cls_cnt 0 2006.145.04:02:51.56#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:02:51.56#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:02:51.56#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:02:51.58#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.04:02:51.62#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:02:51.62#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:02:51.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.04:02:51.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.04:02:51.62$vck44/vb=5,4 2006.145.04:02:51.62#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.04:02:51.62#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.04:02:51.62#ibcon#ireg 11 cls_cnt 2 2006.145.04:02:51.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.04:02:51.68#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.04:02:51.68#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.04:02:51.70#ibcon#[27=AT05-04\r\n] 2006.145.04:02:51.73#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.04:02:51.73#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.04:02:51.73#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.04:02:51.73#ibcon#ireg 7 cls_cnt 0 2006.145.04:02:51.73#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.04:02:51.85#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.04:02:51.85#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.04:02:51.87#ibcon#[27=USB\r\n] 2006.145.04:02:51.90#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.04:02:51.90#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.04:02:51.90#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.04:02:51.90#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.04:02:51.90$vck44/vblo=6,719.99 2006.145.04:02:51.90#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.04:02:51.90#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.04:02:51.90#ibcon#ireg 17 cls_cnt 0 2006.145.04:02:51.90#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:02:51.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:02:51.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:02:51.92#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.04:02:51.96#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:02:51.96#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:02:51.96#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.04:02:51.96#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.04:02:51.96$vck44/vb=6,4 2006.145.04:02:51.96#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.04:02:51.96#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.04:02:51.96#ibcon#ireg 11 cls_cnt 2 2006.145.04:02:51.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.04:02:52.02#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.04:02:52.02#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.04:02:52.04#ibcon#[27=AT06-04\r\n] 2006.145.04:02:52.07#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.04:02:52.07#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.04:02:52.07#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.04:02:52.07#ibcon#ireg 7 cls_cnt 0 2006.145.04:02:52.07#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.04:02:52.19#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.04:02:52.19#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.04:02:52.21#ibcon#[27=USB\r\n] 2006.145.04:02:52.24#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.04:02:52.24#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.04:02:52.24#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.04:02:52.24#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.04:02:52.24$vck44/vblo=7,734.99 2006.145.04:02:52.24#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.04:02:52.24#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.04:02:52.24#ibcon#ireg 17 cls_cnt 0 2006.145.04:02:52.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:02:52.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:02:52.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:02:52.26#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.04:02:52.30#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:02:52.30#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:02:52.30#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.04:02:52.30#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.04:02:52.30$vck44/vb=7,4 2006.145.04:02:52.30#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.04:02:52.30#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.04:02:52.30#ibcon#ireg 11 cls_cnt 2 2006.145.04:02:52.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:02:52.36#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:02:52.36#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:02:52.38#ibcon#[27=AT07-04\r\n] 2006.145.04:02:52.41#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:02:52.41#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:02:52.41#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.04:02:52.41#ibcon#ireg 7 cls_cnt 0 2006.145.04:02:52.41#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:02:52.53#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:02:52.53#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:02:52.55#ibcon#[27=USB\r\n] 2006.145.04:02:52.58#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:02:52.58#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:02:52.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.04:02:52.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.04:02:52.58$vck44/vblo=8,744.99 2006.145.04:02:52.58#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.04:02:52.58#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.04:02:52.58#ibcon#ireg 17 cls_cnt 0 2006.145.04:02:52.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:02:52.58#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:02:52.58#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:02:52.60#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.04:02:52.64#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:02:52.64#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:02:52.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.04:02:52.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.04:02:52.64$vck44/vb=8,4 2006.145.04:02:52.64#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.04:02:52.64#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.04:02:52.64#ibcon#ireg 11 cls_cnt 2 2006.145.04:02:52.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:02:52.70#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:02:52.70#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:02:52.72#ibcon#[27=AT08-04\r\n] 2006.145.04:02:52.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:02:52.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:02:52.75#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.04:02:52.75#ibcon#ireg 7 cls_cnt 0 2006.145.04:02:52.75#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:02:52.87#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:02:52.87#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:02:52.89#ibcon#[27=USB\r\n] 2006.145.04:02:52.92#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:02:52.92#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:02:52.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.04:02:52.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.04:02:52.92$vck44/vabw=wide 2006.145.04:02:52.92#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.04:02:52.92#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.04:02:52.92#ibcon#ireg 8 cls_cnt 0 2006.145.04:02:52.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.04:02:52.92#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.04:02:52.92#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.04:02:52.94#ibcon#[25=BW32\r\n] 2006.145.04:02:52.97#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.04:02:52.97#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.04:02:52.97#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.04:02:52.97#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.04:02:52.97$vck44/vbbw=wide 2006.145.04:02:52.97#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.04:02:52.97#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.04:02:52.97#ibcon#ireg 8 cls_cnt 0 2006.145.04:02:52.97#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.04:02:53.04#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.04:02:53.04#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.04:02:53.06#ibcon#[27=BW32\r\n] 2006.145.04:02:53.09#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.04:02:53.09#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.04:02:53.09#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.04:02:53.09#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.04:02:53.09$setupk4/ifdk4 2006.145.04:02:53.09$ifdk4/lo= 2006.145.04:02:53.09$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.04:02:53.09$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.04:02:53.09$ifdk4/patch= 2006.145.04:02:53.09$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.04:02:53.09$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.04:02:53.09$setupk4/!*+20s 2006.145.04:02:56.39#abcon#<5=/06 4.3 7.5 20.39 601016.7\r\n> 2006.145.04:02:56.41#abcon#{5=INTERFACE CLEAR} 2006.145.04:02:56.47#abcon#[5=S1D000X0/0*\r\n] 2006.145.04:03:02.14#trakl#Source acquired 2006.145.04:03:02.14#flagr#flagr/antenna,acquired 2006.145.04:03:06.56#abcon#<5=/06 4.3 7.5 20.39 621016.7\r\n> 2006.145.04:03:06.58#abcon#{5=INTERFACE CLEAR} 2006.145.04:03:06.64#abcon#[5=S1D000X0/0*\r\n] 2006.145.04:03:07.55$setupk4/"tpicd 2006.145.04:03:07.55$setupk4/echo=off 2006.145.04:03:07.55$setupk4/xlog=off 2006.145.04:03:07.55:!2006.145.04:11:46 2006.145.04:11:46.00:preob 2006.145.04:11:46.13/onsource/TRACKING 2006.145.04:11:46.13:!2006.145.04:11:56 2006.145.04:11:56.00:"tape 2006.145.04:11:56.00:"st=record 2006.145.04:11:56.00:data_valid=on 2006.145.04:11:56.00:midob 2006.145.04:11:56.13/onsource/TRACKING 2006.145.04:11:56.13/wx/20.54,1016.6,62 2006.145.04:11:56.20/cable/+6.5450E-03 2006.145.04:11:57.29/va/01,08,usb,yes,28,30 2006.145.04:11:57.29/va/02,07,usb,yes,30,30 2006.145.04:11:57.29/va/03,08,usb,yes,27,28 2006.145.04:11:57.29/va/04,07,usb,yes,31,33 2006.145.04:11:57.29/va/05,04,usb,yes,27,27 2006.145.04:11:57.29/va/06,04,usb,yes,30,30 2006.145.04:11:57.29/va/07,04,usb,yes,30,32 2006.145.04:11:57.29/va/08,04,usb,yes,26,31 2006.145.04:11:57.52/valo/01,524.99,yes,locked 2006.145.04:11:57.52/valo/02,534.99,yes,locked 2006.145.04:11:57.52/valo/03,564.99,yes,locked 2006.145.04:11:57.52/valo/04,624.99,yes,locked 2006.145.04:11:57.52/valo/05,734.99,yes,locked 2006.145.04:11:57.52/valo/06,814.99,yes,locked 2006.145.04:11:57.52/valo/07,864.99,yes,locked 2006.145.04:11:57.52/valo/08,884.99,yes,locked 2006.145.04:11:58.61/vb/01,03,usb,yes,35,33 2006.145.04:11:58.61/vb/02,04,usb,yes,31,31 2006.145.04:11:58.61/vb/03,04,usb,yes,28,31 2006.145.04:11:58.61/vb/04,04,usb,yes,32,31 2006.145.04:11:58.61/vb/05,04,usb,yes,25,27 2006.145.04:11:58.61/vb/06,04,usb,yes,29,26 2006.145.04:11:58.61/vb/07,04,usb,yes,29,29 2006.145.04:11:58.61/vb/08,04,usb,yes,27,30 2006.145.04:11:58.84/vblo/01,629.99,yes,locked 2006.145.04:11:58.84/vblo/02,634.99,yes,locked 2006.145.04:11:58.84/vblo/03,649.99,yes,locked 2006.145.04:11:58.84/vblo/04,679.99,yes,locked 2006.145.04:11:58.84/vblo/05,709.99,yes,locked 2006.145.04:11:58.84/vblo/06,719.99,yes,locked 2006.145.04:11:58.84/vblo/07,734.99,yes,locked 2006.145.04:11:58.84/vblo/08,744.99,yes,locked 2006.145.04:11:58.99/vabw/8 2006.145.04:11:59.14/vbbw/8 2006.145.04:11:59.28/xfe/off,on,15.0 2006.145.04:11:59.67/ifatt/23,28,28,28 2006.145.04:12:00.07/fmout-gps/S +5.2E-08 2006.145.04:12:00.15:!2006.145.04:13:16 2006.145.04:13:16.00:data_valid=off 2006.145.04:13:16.00:"et 2006.145.04:13:16.01:!+3s 2006.145.04:13:19.02:"tape 2006.145.04:13:19.02:postob 2006.145.04:13:19.25/cable/+6.5459E-03 2006.145.04:13:19.25/wx/20.52,1016.6,66 2006.145.04:13:19.34/fmout-gps/S +5.1E-08 2006.145.04:13:19.34:scan_name=145-0416,jd0605,60 2006.145.04:13:19.34:source=0727-115,073019.11,-114112.6,2000.0,cw 2006.145.04:13:20.13#flagr#flagr/antenna,new-source 2006.145.04:13:20.13:checkk5 2006.145.04:13:20.63/chk_autoobs//k5ts1/ autoobs is running! 2006.145.04:13:21.08/chk_autoobs//k5ts2/ autoobs is running! 2006.145.04:13:21.56/chk_autoobs//k5ts3/ autoobs is running! 2006.145.04:13:22.02/chk_autoobs//k5ts4/ autoobs is running! 2006.145.04:13:22.46/chk_obsdata//k5ts1/T1450411??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.145.04:13:22.99/chk_obsdata//k5ts2/T1450411??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.145.04:13:23.48/chk_obsdata//k5ts3/T1450411??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.145.04:13:23.99/chk_obsdata//k5ts4/T1450411??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.145.04:13:24.92/k5log//k5ts1_log_newline 2006.145.04:13:25.88/k5log//k5ts2_log_newline 2006.145.04:13:27.03/k5log//k5ts3_log_newline 2006.145.04:13:27.80/k5log//k5ts4_log_newline 2006.145.04:13:27.82/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.04:13:27.82:setupk4=1 2006.145.04:13:27.82$setupk4/echo=on 2006.145.04:13:27.82$setupk4/pcalon 2006.145.04:13:27.82$pcalon/"no phase cal control is implemented here 2006.145.04:13:27.82$setupk4/"tpicd=stop 2006.145.04:13:27.82$setupk4/"rec=synch_on 2006.145.04:13:27.82$setupk4/"rec_mode=128 2006.145.04:13:27.82$setupk4/!* 2006.145.04:13:27.82$setupk4/recpk4 2006.145.04:13:27.83$recpk4/recpatch= 2006.145.04:13:27.83$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.04:13:27.83$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.04:13:27.83$setupk4/vck44 2006.145.04:13:27.83$vck44/valo=1,524.99 2006.145.04:13:27.83#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.04:13:27.83#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.04:13:27.83#ibcon#ireg 17 cls_cnt 0 2006.145.04:13:27.83#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.04:13:27.83#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.04:13:27.83#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.04:13:27.87#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.04:13:27.92#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.04:13:27.92#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.04:13:27.92#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.04:13:27.92#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.04:13:27.92$vck44/va=1,8 2006.145.04:13:27.92#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.04:13:27.92#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.04:13:27.92#ibcon#ireg 11 cls_cnt 2 2006.145.04:13:27.92#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.04:13:27.92#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.04:13:27.92#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.04:13:27.94#ibcon#[25=AT01-08\r\n] 2006.145.04:13:27.97#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.04:13:27.97#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.04:13:27.97#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.04:13:27.97#ibcon#ireg 7 cls_cnt 0 2006.145.04:13:27.97#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.04:13:28.09#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.04:13:28.09#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.04:13:28.13#ibcon#[25=USB\r\n] 2006.145.04:13:28.16#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.04:13:28.16#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.04:13:28.16#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.04:13:28.16#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.04:13:28.16$vck44/valo=2,534.99 2006.145.04:13:28.16#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.04:13:28.16#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.04:13:28.16#ibcon#ireg 17 cls_cnt 0 2006.145.04:13:28.16#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.04:13:28.16#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.04:13:28.16#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.04:13:28.18#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.04:13:28.22#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.04:13:28.22#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.04:13:28.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.04:13:28.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.04:13:28.22$vck44/va=2,7 2006.145.04:13:28.22#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.04:13:28.22#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.04:13:28.22#ibcon#ireg 11 cls_cnt 2 2006.145.04:13:28.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.04:13:28.28#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.04:13:28.28#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.04:13:28.30#ibcon#[25=AT02-07\r\n] 2006.145.04:13:28.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.04:13:28.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.04:13:28.33#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.04:13:28.33#ibcon#ireg 7 cls_cnt 0 2006.145.04:13:28.33#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.04:13:28.45#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.04:13:28.45#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.04:13:28.47#ibcon#[25=USB\r\n] 2006.145.04:13:28.50#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.04:13:28.50#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.04:13:28.50#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.04:13:28.50#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.04:13:28.50$vck44/valo=3,564.99 2006.145.04:13:28.50#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.04:13:28.50#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.04:13:28.50#ibcon#ireg 17 cls_cnt 0 2006.145.04:13:28.50#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.04:13:28.50#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.04:13:28.50#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.04:13:28.52#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.04:13:28.56#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.04:13:28.56#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.04:13:28.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.04:13:28.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.04:13:28.56$vck44/va=3,8 2006.145.04:13:28.56#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.04:13:28.56#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.04:13:28.56#ibcon#ireg 11 cls_cnt 2 2006.145.04:13:28.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.04:13:28.62#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.04:13:28.62#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.04:13:28.64#ibcon#[25=AT03-08\r\n] 2006.145.04:13:28.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.04:13:28.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.04:13:28.67#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.04:13:28.67#ibcon#ireg 7 cls_cnt 0 2006.145.04:13:28.67#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.04:13:28.79#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.04:13:28.79#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.04:13:28.81#ibcon#[25=USB\r\n] 2006.145.04:13:28.84#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.04:13:28.84#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.04:13:28.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.04:13:28.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.04:13:28.84$vck44/valo=4,624.99 2006.145.04:13:28.84#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.04:13:28.84#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.04:13:28.84#ibcon#ireg 17 cls_cnt 0 2006.145.04:13:28.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.04:13:28.84#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.04:13:28.84#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.04:13:28.86#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.04:13:28.90#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.04:13:28.90#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.04:13:28.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.04:13:28.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.04:13:28.90$vck44/va=4,7 2006.145.04:13:28.90#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.04:13:28.90#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.04:13:28.90#ibcon#ireg 11 cls_cnt 2 2006.145.04:13:28.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.04:13:28.96#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.04:13:28.96#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.04:13:28.98#ibcon#[25=AT04-07\r\n] 2006.145.04:13:29.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.04:13:29.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.04:13:29.01#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.04:13:29.01#ibcon#ireg 7 cls_cnt 0 2006.145.04:13:29.01#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.04:13:29.13#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.04:13:29.13#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.04:13:29.15#ibcon#[25=USB\r\n] 2006.145.04:13:29.18#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.04:13:29.18#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.04:13:29.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.04:13:29.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.04:13:29.18$vck44/valo=5,734.99 2006.145.04:13:29.18#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.04:13:29.18#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.04:13:29.18#ibcon#ireg 17 cls_cnt 0 2006.145.04:13:29.18#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.04:13:29.18#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.04:13:29.18#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.04:13:29.20#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.04:13:29.24#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.04:13:29.24#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.04:13:29.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.04:13:29.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.04:13:29.24$vck44/va=5,4 2006.145.04:13:29.24#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.04:13:29.24#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.04:13:29.24#ibcon#ireg 11 cls_cnt 2 2006.145.04:13:29.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.04:13:29.30#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.04:13:29.30#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.04:13:29.32#ibcon#[25=AT05-04\r\n] 2006.145.04:13:29.35#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.04:13:29.35#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.04:13:29.35#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.04:13:29.35#ibcon#ireg 7 cls_cnt 0 2006.145.04:13:29.35#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.04:13:29.47#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.04:13:29.47#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.04:13:29.49#ibcon#[25=USB\r\n] 2006.145.04:13:29.52#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.04:13:29.52#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.04:13:29.52#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.04:13:29.52#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.04:13:29.52$vck44/valo=6,814.99 2006.145.04:13:29.52#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.04:13:29.52#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.04:13:29.52#ibcon#ireg 17 cls_cnt 0 2006.145.04:13:29.52#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.04:13:29.52#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.04:13:29.52#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.04:13:29.54#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.04:13:29.58#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.04:13:29.58#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.04:13:29.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.04:13:29.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.04:13:29.58$vck44/va=6,4 2006.145.04:13:29.58#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.04:13:29.58#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.04:13:29.58#ibcon#ireg 11 cls_cnt 2 2006.145.04:13:29.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.04:13:29.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.04:13:29.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.04:13:29.66#ibcon#[25=AT06-04\r\n] 2006.145.04:13:29.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.04:13:29.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.04:13:29.69#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.04:13:29.69#ibcon#ireg 7 cls_cnt 0 2006.145.04:13:29.69#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.04:13:29.81#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.04:13:29.81#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.04:13:29.83#ibcon#[25=USB\r\n] 2006.145.04:13:29.86#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.04:13:29.86#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.04:13:29.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.04:13:29.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.04:13:29.86$vck44/valo=7,864.99 2006.145.04:13:29.86#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.04:13:29.86#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.04:13:29.86#ibcon#ireg 17 cls_cnt 0 2006.145.04:13:29.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.04:13:29.86#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.04:13:29.86#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.04:13:29.88#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.04:13:29.92#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.04:13:29.92#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.04:13:29.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.04:13:29.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.04:13:29.92$vck44/va=7,4 2006.145.04:13:29.92#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.04:13:29.92#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.04:13:29.92#ibcon#ireg 11 cls_cnt 2 2006.145.04:13:29.92#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.04:13:29.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.04:13:29.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.04:13:30.00#ibcon#[25=AT07-04\r\n] 2006.145.04:13:30.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.04:13:30.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.04:13:30.03#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.04:13:30.03#ibcon#ireg 7 cls_cnt 0 2006.145.04:13:30.03#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.04:13:30.15#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.04:13:30.15#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.04:13:30.17#ibcon#[25=USB\r\n] 2006.145.04:13:30.20#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.04:13:30.20#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.04:13:30.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.04:13:30.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.04:13:30.20$vck44/valo=8,884.99 2006.145.04:13:30.20#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.04:13:30.20#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.04:13:30.20#ibcon#ireg 17 cls_cnt 0 2006.145.04:13:30.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.04:13:30.20#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.04:13:30.20#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.04:13:30.22#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.04:13:30.26#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.04:13:30.26#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.04:13:30.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.04:13:30.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.04:13:30.26$vck44/va=8,4 2006.145.04:13:30.26#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.04:13:30.26#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.04:13:30.26#ibcon#ireg 11 cls_cnt 2 2006.145.04:13:30.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.04:13:30.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.04:13:30.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.04:13:30.34#ibcon#[25=AT08-04\r\n] 2006.145.04:13:30.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.04:13:30.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.04:13:30.37#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.04:13:30.37#ibcon#ireg 7 cls_cnt 0 2006.145.04:13:30.37#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.04:13:30.49#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.04:13:30.49#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.04:13:30.51#ibcon#[25=USB\r\n] 2006.145.04:13:30.54#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.04:13:30.54#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.04:13:30.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.04:13:30.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.04:13:30.54$vck44/vblo=1,629.99 2006.145.04:13:30.54#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.04:13:30.54#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.04:13:30.54#ibcon#ireg 17 cls_cnt 0 2006.145.04:13:30.54#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.04:13:30.54#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.04:13:30.54#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.04:13:30.56#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.04:13:30.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.04:13:30.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.04:13:30.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.04:13:30.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.04:13:30.60$vck44/vb=1,3 2006.145.04:13:30.60#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.04:13:30.60#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.04:13:30.60#ibcon#ireg 11 cls_cnt 2 2006.145.04:13:30.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.04:13:30.60#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.04:13:30.60#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.04:13:30.62#ibcon#[27=AT01-03\r\n] 2006.145.04:13:30.65#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.04:13:30.65#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.04:13:30.65#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.04:13:30.65#ibcon#ireg 7 cls_cnt 0 2006.145.04:13:30.65#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.04:13:30.77#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.04:13:30.77#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.04:13:30.79#ibcon#[27=USB\r\n] 2006.145.04:13:30.82#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.04:13:30.82#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.04:13:30.82#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.04:13:30.82#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.04:13:30.82$vck44/vblo=2,634.99 2006.145.04:13:30.82#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.04:13:30.82#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.04:13:30.82#ibcon#ireg 17 cls_cnt 0 2006.145.04:13:30.82#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.04:13:30.82#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.04:13:30.82#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.04:13:30.84#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.04:13:30.88#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.04:13:30.88#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.04:13:30.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.04:13:30.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.04:13:30.88$vck44/vb=2,4 2006.145.04:13:30.88#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.04:13:30.88#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.04:13:30.88#ibcon#ireg 11 cls_cnt 2 2006.145.04:13:30.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.04:13:30.94#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.04:13:30.94#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.04:13:30.96#ibcon#[27=AT02-04\r\n] 2006.145.04:13:30.99#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.04:13:30.99#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.04:13:30.99#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.04:13:30.99#ibcon#ireg 7 cls_cnt 0 2006.145.04:13:30.99#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.04:13:31.11#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.04:13:31.11#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.04:13:31.13#ibcon#[27=USB\r\n] 2006.145.04:13:31.16#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.04:13:31.16#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.04:13:31.16#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.04:13:31.16#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.04:13:31.16$vck44/vblo=3,649.99 2006.145.04:13:31.16#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.04:13:31.16#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.04:13:31.16#ibcon#ireg 17 cls_cnt 0 2006.145.04:13:31.16#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.04:13:31.16#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.04:13:31.16#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.04:13:31.18#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.04:13:31.22#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.04:13:31.22#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.04:13:31.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.04:13:31.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.04:13:31.22$vck44/vb=3,4 2006.145.04:13:31.22#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.04:13:31.22#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.04:13:31.22#ibcon#ireg 11 cls_cnt 2 2006.145.04:13:31.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.04:13:31.28#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.04:13:31.28#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.04:13:31.30#ibcon#[27=AT03-04\r\n] 2006.145.04:13:31.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.04:13:31.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.04:13:31.33#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.04:13:31.33#ibcon#ireg 7 cls_cnt 0 2006.145.04:13:31.33#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.04:13:31.45#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.04:13:31.45#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.04:13:31.47#ibcon#[27=USB\r\n] 2006.145.04:13:31.50#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.04:13:31.50#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.04:13:31.50#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.04:13:31.50#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.04:13:31.50$vck44/vblo=4,679.99 2006.145.04:13:31.50#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.04:13:31.50#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.04:13:31.50#ibcon#ireg 17 cls_cnt 0 2006.145.04:13:31.50#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.04:13:31.50#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.04:13:31.50#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.04:13:31.52#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.04:13:31.56#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.04:13:31.56#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.04:13:31.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.04:13:31.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.04:13:31.56$vck44/vb=4,4 2006.145.04:13:31.56#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.04:13:31.56#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.04:13:31.56#ibcon#ireg 11 cls_cnt 2 2006.145.04:13:31.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.04:13:31.62#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.04:13:31.62#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.04:13:31.64#ibcon#[27=AT04-04\r\n] 2006.145.04:13:31.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.04:13:31.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.04:13:31.67#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.04:13:31.67#ibcon#ireg 7 cls_cnt 0 2006.145.04:13:31.67#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.04:13:31.79#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.04:13:31.79#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.04:13:31.81#ibcon#[27=USB\r\n] 2006.145.04:13:31.84#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.04:13:31.84#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.04:13:31.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.04:13:31.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.04:13:31.84$vck44/vblo=5,709.99 2006.145.04:13:31.84#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.04:13:31.84#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.04:13:31.84#ibcon#ireg 17 cls_cnt 0 2006.145.04:13:31.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.04:13:31.84#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.04:13:31.84#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.04:13:31.86#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.04:13:31.90#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.04:13:31.90#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.04:13:31.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.04:13:31.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.04:13:31.90$vck44/vb=5,4 2006.145.04:13:31.90#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.04:13:31.90#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.04:13:31.90#ibcon#ireg 11 cls_cnt 2 2006.145.04:13:31.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.04:13:31.96#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.04:13:31.96#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.04:13:31.98#ibcon#[27=AT05-04\r\n] 2006.145.04:13:32.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.04:13:32.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.04:13:32.01#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.04:13:32.01#ibcon#ireg 7 cls_cnt 0 2006.145.04:13:32.01#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.04:13:32.13#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.04:13:32.13#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.04:13:32.15#ibcon#[27=USB\r\n] 2006.145.04:13:32.18#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.04:13:32.18#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.04:13:32.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.04:13:32.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.04:13:32.18$vck44/vblo=6,719.99 2006.145.04:13:32.18#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.04:13:32.18#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.04:13:32.18#ibcon#ireg 17 cls_cnt 0 2006.145.04:13:32.18#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.04:13:32.18#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.04:13:32.18#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.04:13:32.20#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.04:13:32.24#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.04:13:32.24#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.04:13:32.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.04:13:32.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.04:13:32.24$vck44/vb=6,4 2006.145.04:13:32.24#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.04:13:32.24#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.04:13:32.24#ibcon#ireg 11 cls_cnt 2 2006.145.04:13:32.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.04:13:32.30#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.04:13:32.30#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.04:13:32.32#ibcon#[27=AT06-04\r\n] 2006.145.04:13:32.35#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.04:13:32.35#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.04:13:32.35#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.04:13:32.35#ibcon#ireg 7 cls_cnt 0 2006.145.04:13:32.35#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.04:13:32.47#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.04:13:32.47#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.04:13:32.49#ibcon#[27=USB\r\n] 2006.145.04:13:32.52#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.04:13:32.52#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.04:13:32.52#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.04:13:32.52#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.04:13:32.52$vck44/vblo=7,734.99 2006.145.04:13:32.52#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.04:13:32.52#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.04:13:32.52#ibcon#ireg 17 cls_cnt 0 2006.145.04:13:32.52#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.04:13:32.52#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.04:13:32.52#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.04:13:32.54#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.04:13:32.58#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.04:13:32.58#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.04:13:32.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.04:13:32.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.04:13:32.58$vck44/vb=7,4 2006.145.04:13:32.58#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.04:13:32.58#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.04:13:32.58#ibcon#ireg 11 cls_cnt 2 2006.145.04:13:32.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.04:13:32.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.04:13:32.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.04:13:32.66#ibcon#[27=AT07-04\r\n] 2006.145.04:13:32.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.04:13:32.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.04:13:32.69#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.04:13:32.69#ibcon#ireg 7 cls_cnt 0 2006.145.04:13:32.69#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.04:13:32.81#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.04:13:32.81#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.04:13:32.83#ibcon#[27=USB\r\n] 2006.145.04:13:32.86#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.04:13:32.86#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.04:13:32.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.04:13:32.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.04:13:32.86$vck44/vblo=8,744.99 2006.145.04:13:32.86#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.04:13:32.86#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.04:13:32.86#ibcon#ireg 17 cls_cnt 0 2006.145.04:13:32.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.04:13:32.86#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.04:13:32.86#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.04:13:32.88#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.04:13:32.92#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.04:13:32.92#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.04:13:32.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.04:13:32.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.04:13:32.92$vck44/vb=8,4 2006.145.04:13:32.92#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.04:13:32.92#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.04:13:32.92#ibcon#ireg 11 cls_cnt 2 2006.145.04:13:32.92#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.04:13:32.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.04:13:32.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.04:13:33.00#ibcon#[27=AT08-04\r\n] 2006.145.04:13:33.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.04:13:33.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.04:13:33.03#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.04:13:33.03#ibcon#ireg 7 cls_cnt 0 2006.145.04:13:33.03#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.04:13:33.15#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.04:13:33.15#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.04:13:33.17#ibcon#[27=USB\r\n] 2006.145.04:13:33.20#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.04:13:33.20#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.04:13:33.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.04:13:33.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.04:13:33.20$vck44/vabw=wide 2006.145.04:13:33.20#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.04:13:33.20#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.04:13:33.20#ibcon#ireg 8 cls_cnt 0 2006.145.04:13:33.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.04:13:33.20#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.04:13:33.20#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.04:13:33.22#ibcon#[25=BW32\r\n] 2006.145.04:13:33.25#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.04:13:33.25#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.04:13:33.25#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.04:13:33.25#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.04:13:33.25$vck44/vbbw=wide 2006.145.04:13:33.25#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.04:13:33.25#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.04:13:33.25#ibcon#ireg 8 cls_cnt 0 2006.145.04:13:33.25#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.04:13:33.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.04:13:33.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.04:13:33.34#ibcon#[27=BW32\r\n] 2006.145.04:13:33.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.04:13:33.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.04:13:33.37#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.04:13:33.37#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.04:13:33.37$setupk4/ifdk4 2006.145.04:13:33.37$ifdk4/lo= 2006.145.04:13:33.37$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.04:13:33.37$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.04:13:33.37$ifdk4/patch= 2006.145.04:13:33.37$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.04:13:33.37$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.04:13:33.37$setupk4/!*+20s 2006.145.04:13:37.49#abcon#<5=/06 4.9 9.2 20.52 661016.6\r\n> 2006.145.04:13:37.51#abcon#{5=INTERFACE CLEAR} 2006.145.04:13:37.57#abcon#[5=S1D000X0/0*\r\n] 2006.145.04:13:44.14#trakl#Source acquired 2006.145.04:13:45.14#flagr#flagr/antenna,acquired 2006.145.04:13:47.66#abcon#<5=/06 4.9 9.2 20.52 671016.6\r\n> 2006.145.04:13:47.68#abcon#{5=INTERFACE CLEAR} 2006.145.04:13:47.74#abcon#[5=S1D000X0/0*\r\n] 2006.145.04:13:47.83$setupk4/"tpicd 2006.145.04:13:47.83$setupk4/echo=off 2006.145.04:13:47.83$setupk4/xlog=off 2006.145.04:13:47.83:!2006.145.04:16:02 2006.145.04:15:14.14#trakl#Off source 2006.145.04:15:14.14?ERROR st -7 Antenna off-source! 2006.145.04:15:14.14#trakl#az 147.656 el 36.188 azerr*cos(el) -0.0035 elerr -0.0192 2006.145.04:15:15.14#flagr#flagr/antenna,off-source 2006.145.04:15:20.14#trakl#Source re-acquired 2006.145.04:15:21.14#flagr#flagr/antenna,re-acquired 2006.145.04:16:02.00:preob 2006.145.04:16:02.14/onsource/TRACKING 2006.145.04:16:02.14:!2006.145.04:16:12 2006.145.04:16:12.00:"tape 2006.145.04:16:12.00:"st=record 2006.145.04:16:12.00:data_valid=on 2006.145.04:16:12.00:midob 2006.145.04:16:12.14/onsource/TRACKING 2006.145.04:16:12.14/wx/20.53,1016.6,63 2006.145.04:16:12.33/cable/+6.5441E-03 2006.145.04:16:13.42/va/01,08,usb,yes,29,31 2006.145.04:16:13.42/va/02,07,usb,yes,31,31 2006.145.04:16:13.42/va/03,08,usb,yes,28,29 2006.145.04:16:13.42/va/04,07,usb,yes,32,33 2006.145.04:16:13.42/va/05,04,usb,yes,28,28 2006.145.04:16:13.42/va/06,04,usb,yes,31,31 2006.145.04:16:13.42/va/07,04,usb,yes,31,33 2006.145.04:16:13.42/va/08,04,usb,yes,27,32 2006.145.04:16:13.65/valo/01,524.99,yes,locked 2006.145.04:16:13.65/valo/02,534.99,yes,locked 2006.145.04:16:13.65/valo/03,564.99,yes,locked 2006.145.04:16:13.65/valo/04,624.99,yes,locked 2006.145.04:16:13.65/valo/05,734.99,yes,locked 2006.145.04:16:13.65/valo/06,814.99,yes,locked 2006.145.04:16:13.65/valo/07,864.99,yes,locked 2006.145.04:16:13.65/valo/08,884.99,yes,locked 2006.145.04:16:14.74/vb/01,03,usb,yes,36,34 2006.145.04:16:14.74/vb/02,04,usb,yes,32,31 2006.145.04:16:14.74/vb/03,04,usb,yes,28,31 2006.145.04:16:14.74/vb/04,04,usb,yes,33,32 2006.145.04:16:14.74/vb/05,04,usb,yes,25,28 2006.145.04:16:14.74/vb/06,04,usb,yes,30,26 2006.145.04:16:14.74/vb/07,04,usb,yes,29,29 2006.145.04:16:14.74/vb/08,04,usb,yes,27,30 2006.145.04:16:14.97/vblo/01,629.99,yes,locked 2006.145.04:16:14.97/vblo/02,634.99,yes,locked 2006.145.04:16:14.97/vblo/03,649.99,yes,locked 2006.145.04:16:14.97/vblo/04,679.99,yes,locked 2006.145.04:16:14.97/vblo/05,709.99,yes,locked 2006.145.04:16:14.97/vblo/06,719.99,yes,locked 2006.145.04:16:14.97/vblo/07,734.99,yes,locked 2006.145.04:16:14.97/vblo/08,744.99,yes,locked 2006.145.04:16:15.12/vabw/8 2006.145.04:16:15.27/vbbw/8 2006.145.04:16:15.36/xfe/off,on,14.2 2006.145.04:16:15.74/ifatt/23,28,28,28 2006.145.04:16:16.08/fmout-gps/S +5.0E-08 2006.145.04:16:16.14:!2006.145.04:17:12 2006.145.04:17:12.00:data_valid=off 2006.145.04:17:12.00:"et 2006.145.04:17:12.00:!+3s 2006.145.04:17:15.02:"tape 2006.145.04:17:15.02:postob 2006.145.04:17:15.09/cable/+6.5451E-03 2006.145.04:17:15.09/wx/20.53,1016.6,60 2006.145.04:17:16.08/fmout-gps/S +5.0E-08 2006.145.04:17:16.08:scan_name=145-0419,jd0605,784 2006.145.04:17:16.08:source=0458-020,050112.81,-015914.3,2000.0,cw 2006.145.04:17:16.14#flagr#flagr/antenna,new-source 2006.145.04:17:17.14:checkk5 2006.145.04:17:17.61/chk_autoobs//k5ts1/ autoobs is running! 2006.145.04:17:18.06/chk_autoobs//k5ts2/ autoobs is running! 2006.145.04:17:18.79/chk_autoobs//k5ts3/ autoobs is running! 2006.145.04:17:19.28/chk_autoobs//k5ts4/ autoobs is running! 2006.145.04:17:19.77/chk_obsdata//k5ts1/T1450416??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.145.04:17:20.24/chk_obsdata//k5ts2/T1450416??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.145.04:17:20.70/chk_obsdata//k5ts3/T1450416??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.145.04:17:21.21/chk_obsdata//k5ts4/T1450416??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.145.04:17:22.03/k5log//k5ts1_log_newline 2006.145.04:17:23.14/k5log//k5ts2_log_newline 2006.145.04:17:24.21/k5log//k5ts3_log_newline 2006.145.04:17:25.05/k5log//k5ts4_log_newline 2006.145.04:17:25.07/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.04:17:25.07:setupk4=1 2006.145.04:17:25.07$setupk4/echo=on 2006.145.04:17:25.07$setupk4/pcalon 2006.145.04:17:25.07$pcalon/"no phase cal control is implemented here 2006.145.04:17:25.07$setupk4/"tpicd=stop 2006.145.04:17:25.07$setupk4/"rec=synch_on 2006.145.04:17:25.07$setupk4/"rec_mode=128 2006.145.04:17:25.07$setupk4/!* 2006.145.04:17:25.07$setupk4/recpk4 2006.145.04:17:25.07$recpk4/recpatch= 2006.145.04:17:25.08$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.04:17:25.08$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.04:17:25.08$setupk4/vck44 2006.145.04:17:25.08$vck44/valo=1,524.99 2006.145.04:17:25.08#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.04:17:25.08#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.04:17:25.08#ibcon#ireg 17 cls_cnt 0 2006.145.04:17:25.08#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:17:25.08#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:17:25.08#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:17:25.11#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.04:17:25.16#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:17:25.16#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:17:25.16#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.04:17:25.16#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.04:17:25.16$vck44/va=1,8 2006.145.04:17:25.16#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.04:17:25.16#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.04:17:25.16#ibcon#ireg 11 cls_cnt 2 2006.145.04:17:25.16#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:17:25.16#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:17:25.16#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:17:25.18#ibcon#[25=AT01-08\r\n] 2006.145.04:17:25.21#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:17:25.21#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:17:25.21#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.04:17:25.21#ibcon#ireg 7 cls_cnt 0 2006.145.04:17:25.21#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:17:25.33#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:17:25.33#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:17:25.35#ibcon#[25=USB\r\n] 2006.145.04:17:25.38#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:17:25.38#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:17:25.38#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.04:17:25.38#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.04:17:25.38$vck44/valo=2,534.99 2006.145.04:17:25.38#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.04:17:25.38#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.04:17:25.38#ibcon#ireg 17 cls_cnt 0 2006.145.04:17:25.38#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:17:25.38#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:17:25.38#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:17:25.41#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.04:17:25.45#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:17:25.45#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:17:25.45#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.04:17:25.45#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.04:17:25.45$vck44/va=2,7 2006.145.04:17:25.45#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.04:17:25.45#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.04:17:25.45#ibcon#ireg 11 cls_cnt 2 2006.145.04:17:25.45#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:17:25.50#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:17:25.50#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:17:25.52#ibcon#[25=AT02-07\r\n] 2006.145.04:17:25.55#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:17:25.55#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:17:25.55#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.04:17:25.55#ibcon#ireg 7 cls_cnt 0 2006.145.04:17:25.55#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:17:25.67#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:17:25.67#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:17:25.69#ibcon#[25=USB\r\n] 2006.145.04:17:25.72#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:17:25.72#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:17:25.72#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.04:17:25.72#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.04:17:25.72$vck44/valo=3,564.99 2006.145.04:17:25.72#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.04:17:25.72#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.04:17:25.72#ibcon#ireg 17 cls_cnt 0 2006.145.04:17:25.72#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.04:17:25.72#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.04:17:25.72#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.04:17:25.74#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.04:17:25.78#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.04:17:25.78#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.04:17:25.78#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.04:17:25.78#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.04:17:25.78$vck44/va=3,8 2006.145.04:17:25.78#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.04:17:25.78#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.04:17:25.78#ibcon#ireg 11 cls_cnt 2 2006.145.04:17:25.78#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.04:17:25.84#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.04:17:25.84#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.04:17:25.86#ibcon#[25=AT03-08\r\n] 2006.145.04:17:25.89#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.04:17:25.89#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.04:17:25.89#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.04:17:25.89#ibcon#ireg 7 cls_cnt 0 2006.145.04:17:25.89#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.04:17:26.01#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.04:17:26.01#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.04:17:26.03#ibcon#[25=USB\r\n] 2006.145.04:17:26.06#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.04:17:26.06#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.04:17:26.06#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.04:17:26.06#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.04:17:26.06$vck44/valo=4,624.99 2006.145.04:17:26.06#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.04:17:26.06#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.04:17:26.06#ibcon#ireg 17 cls_cnt 0 2006.145.04:17:26.06#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.04:17:26.06#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.04:17:26.06#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.04:17:26.08#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.04:17:26.12#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.04:17:26.12#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.04:17:26.12#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.04:17:26.12#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.04:17:26.12$vck44/va=4,7 2006.145.04:17:26.12#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.04:17:26.12#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.04:17:26.12#ibcon#ireg 11 cls_cnt 2 2006.145.04:17:26.12#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.04:17:26.18#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.04:17:26.18#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.04:17:26.20#ibcon#[25=AT04-07\r\n] 2006.145.04:17:26.23#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.04:17:26.23#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.04:17:26.23#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.04:17:26.23#ibcon#ireg 7 cls_cnt 0 2006.145.04:17:26.23#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.04:17:26.35#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.04:17:26.35#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.04:17:26.37#ibcon#[25=USB\r\n] 2006.145.04:17:26.40#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.04:17:26.40#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.04:17:26.40#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.04:17:26.40#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.04:17:26.40$vck44/valo=5,734.99 2006.145.04:17:26.40#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.04:17:26.40#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.04:17:26.40#ibcon#ireg 17 cls_cnt 0 2006.145.04:17:26.40#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:17:26.40#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:17:26.40#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:17:26.42#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.04:17:26.46#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:17:26.46#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:17:26.46#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.04:17:26.46#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.04:17:26.46$vck44/va=5,4 2006.145.04:17:26.46#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.04:17:26.46#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.04:17:26.46#ibcon#ireg 11 cls_cnt 2 2006.145.04:17:26.46#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:17:26.52#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:17:26.52#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:17:26.54#ibcon#[25=AT05-04\r\n] 2006.145.04:17:26.57#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:17:26.57#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:17:26.57#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.04:17:26.57#ibcon#ireg 7 cls_cnt 0 2006.145.04:17:26.57#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:17:26.69#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:17:26.69#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:17:26.71#ibcon#[25=USB\r\n] 2006.145.04:17:26.74#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:17:26.74#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:17:26.74#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.04:17:26.74#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.04:17:26.74$vck44/valo=6,814.99 2006.145.04:17:26.74#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.04:17:26.74#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.04:17:26.74#ibcon#ireg 17 cls_cnt 0 2006.145.04:17:26.74#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:17:26.74#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:17:26.74#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:17:26.76#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.04:17:26.80#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:17:26.80#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:17:26.80#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.04:17:26.80#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.04:17:26.80$vck44/va=6,4 2006.145.04:17:26.80#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.04:17:26.80#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.04:17:26.80#ibcon#ireg 11 cls_cnt 2 2006.145.04:17:26.80#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:17:26.86#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:17:26.86#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:17:26.88#ibcon#[25=AT06-04\r\n] 2006.145.04:17:26.91#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:17:26.91#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:17:26.91#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.04:17:26.91#ibcon#ireg 7 cls_cnt 0 2006.145.04:17:26.91#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:17:27.03#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:17:27.03#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:17:27.05#ibcon#[25=USB\r\n] 2006.145.04:17:27.08#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:17:27.08#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:17:27.08#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.04:17:27.08#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.04:17:27.08$vck44/valo=7,864.99 2006.145.04:17:27.08#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.04:17:27.08#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.04:17:27.08#ibcon#ireg 17 cls_cnt 0 2006.145.04:17:27.08#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:17:27.08#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:17:27.08#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:17:27.10#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.04:17:27.14#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:17:27.14#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:17:27.14#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.04:17:27.14#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.04:17:27.14$vck44/va=7,4 2006.145.04:17:27.14#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.04:17:27.14#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.04:17:27.14#ibcon#ireg 11 cls_cnt 2 2006.145.04:17:27.14#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:17:27.20#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:17:27.20#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:17:27.22#ibcon#[25=AT07-04\r\n] 2006.145.04:17:27.25#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:17:27.25#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:17:27.25#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.04:17:27.25#ibcon#ireg 7 cls_cnt 0 2006.145.04:17:27.25#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:17:27.37#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:17:27.37#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:17:27.39#ibcon#[25=USB\r\n] 2006.145.04:17:27.42#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:17:27.42#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:17:27.42#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.04:17:27.42#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.04:17:27.42$vck44/valo=8,884.99 2006.145.04:17:27.42#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.04:17:27.42#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.04:17:27.42#ibcon#ireg 17 cls_cnt 0 2006.145.04:17:27.42#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:17:27.42#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:17:27.42#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:17:27.44#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.04:17:27.48#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:17:27.48#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:17:27.48#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.04:17:27.48#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.04:17:27.48$vck44/va=8,4 2006.145.04:17:27.48#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.04:17:27.48#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.04:17:27.48#ibcon#ireg 11 cls_cnt 2 2006.145.04:17:27.48#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.04:17:27.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.04:17:27.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.04:17:27.56#ibcon#[25=AT08-04\r\n] 2006.145.04:17:27.59#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.04:17:27.59#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.04:17:27.59#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.04:17:27.59#ibcon#ireg 7 cls_cnt 0 2006.145.04:17:27.59#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.04:17:27.71#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.04:17:27.71#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.04:17:27.73#ibcon#[25=USB\r\n] 2006.145.04:17:27.76#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.04:17:27.76#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.04:17:27.76#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.04:17:27.76#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.04:17:27.76$vck44/vblo=1,629.99 2006.145.04:17:27.76#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.04:17:27.76#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.04:17:27.76#ibcon#ireg 17 cls_cnt 0 2006.145.04:17:27.76#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:17:27.76#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:17:27.76#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:17:27.78#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.04:17:27.82#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:17:27.82#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:17:27.82#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.04:17:27.82#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.04:17:27.82$vck44/vb=1,3 2006.145.04:17:27.82#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.04:17:27.82#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.04:17:27.82#ibcon#ireg 11 cls_cnt 2 2006.145.04:17:27.82#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.04:17:27.82#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.04:17:27.82#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.04:17:27.84#ibcon#[27=AT01-03\r\n] 2006.145.04:17:27.87#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.04:17:27.87#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.04:17:27.87#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.04:17:27.87#ibcon#ireg 7 cls_cnt 0 2006.145.04:17:27.87#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.04:17:27.99#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.04:17:27.99#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.04:17:28.01#ibcon#[27=USB\r\n] 2006.145.04:17:28.04#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.04:17:28.04#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.04:17:28.04#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.04:17:28.04#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.04:17:28.04$vck44/vblo=2,634.99 2006.145.04:17:28.04#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.04:17:28.04#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.04:17:28.04#ibcon#ireg 17 cls_cnt 0 2006.145.04:17:28.04#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:17:28.04#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:17:28.04#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:17:28.06#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.04:17:28.10#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:17:28.10#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:17:28.10#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.04:17:28.10#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.04:17:28.10$vck44/vb=2,4 2006.145.04:17:28.10#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.04:17:28.10#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.04:17:28.10#ibcon#ireg 11 cls_cnt 2 2006.145.04:17:28.10#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:17:28.16#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:17:28.16#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:17:28.18#ibcon#[27=AT02-04\r\n] 2006.145.04:17:28.21#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:17:28.21#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:17:28.21#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.04:17:28.21#ibcon#ireg 7 cls_cnt 0 2006.145.04:17:28.21#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:17:28.33#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:17:28.33#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:17:28.35#ibcon#[27=USB\r\n] 2006.145.04:17:28.38#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:17:28.38#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:17:28.38#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.04:17:28.38#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.04:17:28.38$vck44/vblo=3,649.99 2006.145.04:17:28.38#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.04:17:28.38#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.04:17:28.38#ibcon#ireg 17 cls_cnt 0 2006.145.04:17:28.38#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:17:28.38#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:17:28.38#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:17:28.40#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.04:17:28.44#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:17:28.44#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:17:28.44#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.04:17:28.44#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.04:17:28.44$vck44/vb=3,4 2006.145.04:17:28.44#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.04:17:28.44#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.04:17:28.44#ibcon#ireg 11 cls_cnt 2 2006.145.04:17:28.44#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:17:28.50#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:17:28.50#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:17:28.52#ibcon#[27=AT03-04\r\n] 2006.145.04:17:28.55#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:17:28.55#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:17:28.55#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.04:17:28.55#ibcon#ireg 7 cls_cnt 0 2006.145.04:17:28.55#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:17:28.67#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:17:28.67#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:17:28.69#ibcon#[27=USB\r\n] 2006.145.04:17:28.72#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:17:28.72#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:17:28.72#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.04:17:28.72#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.04:17:28.72$vck44/vblo=4,679.99 2006.145.04:17:28.72#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.04:17:28.72#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.04:17:28.72#ibcon#ireg 17 cls_cnt 0 2006.145.04:17:28.72#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.04:17:28.72#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.04:17:28.72#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.04:17:28.74#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.04:17:28.78#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.04:17:28.78#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.04:17:28.78#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.04:17:28.78#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.04:17:28.78$vck44/vb=4,4 2006.145.04:17:28.78#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.04:17:28.78#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.04:17:28.78#ibcon#ireg 11 cls_cnt 2 2006.145.04:17:28.78#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.04:17:28.84#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.04:17:28.84#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.04:17:28.86#ibcon#[27=AT04-04\r\n] 2006.145.04:17:28.89#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.04:17:28.89#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.04:17:28.89#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.04:17:28.89#ibcon#ireg 7 cls_cnt 0 2006.145.04:17:28.89#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.04:17:29.01#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.04:17:29.01#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.04:17:29.03#ibcon#[27=USB\r\n] 2006.145.04:17:29.06#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.04:17:29.06#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.04:17:29.06#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.04:17:29.06#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.04:17:29.06$vck44/vblo=5,709.99 2006.145.04:17:29.06#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.04:17:29.06#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.04:17:29.06#ibcon#ireg 17 cls_cnt 0 2006.145.04:17:29.06#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.04:17:29.06#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.04:17:29.06#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.04:17:29.08#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.04:17:29.12#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.04:17:29.12#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.04:17:29.12#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.04:17:29.12#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.04:17:29.12$vck44/vb=5,4 2006.145.04:17:29.12#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.04:17:29.12#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.04:17:29.12#ibcon#ireg 11 cls_cnt 2 2006.145.04:17:29.12#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.04:17:29.18#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.04:17:29.18#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.04:17:29.20#ibcon#[27=AT05-04\r\n] 2006.145.04:17:29.23#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.04:17:29.23#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.04:17:29.23#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.04:17:29.23#ibcon#ireg 7 cls_cnt 0 2006.145.04:17:29.23#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.04:17:29.35#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.04:17:29.35#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.04:17:29.37#ibcon#[27=USB\r\n] 2006.145.04:17:29.40#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.04:17:29.40#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.04:17:29.40#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.04:17:29.40#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.04:17:29.40$vck44/vblo=6,719.99 2006.145.04:17:29.40#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.04:17:29.40#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.04:17:29.40#ibcon#ireg 17 cls_cnt 0 2006.145.04:17:29.40#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:17:29.40#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:17:29.40#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:17:29.42#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.04:17:29.46#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:17:29.46#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:17:29.46#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.04:17:29.46#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.04:17:29.46$vck44/vb=6,4 2006.145.04:17:29.46#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.04:17:29.46#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.04:17:29.46#ibcon#ireg 11 cls_cnt 2 2006.145.04:17:29.46#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:17:29.52#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:17:29.52#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:17:29.54#ibcon#[27=AT06-04\r\n] 2006.145.04:17:29.57#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:17:29.57#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:17:29.57#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.04:17:29.57#ibcon#ireg 7 cls_cnt 0 2006.145.04:17:29.57#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:17:29.69#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:17:29.69#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:17:29.71#ibcon#[27=USB\r\n] 2006.145.04:17:29.74#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:17:29.74#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:17:29.74#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.04:17:29.74#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.04:17:29.74$vck44/vblo=7,734.99 2006.145.04:17:29.74#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.04:17:29.74#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.04:17:29.74#ibcon#ireg 17 cls_cnt 0 2006.145.04:17:29.74#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:17:29.74#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:17:29.74#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:17:29.76#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.04:17:29.80#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:17:29.80#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:17:29.80#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.04:17:29.80#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.04:17:29.80$vck44/vb=7,4 2006.145.04:17:29.80#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.04:17:29.80#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.04:17:29.80#ibcon#ireg 11 cls_cnt 2 2006.145.04:17:29.80#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:17:29.86#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:17:29.86#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:17:29.88#ibcon#[27=AT07-04\r\n] 2006.145.04:17:29.91#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:17:29.91#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:17:29.91#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.04:17:29.91#ibcon#ireg 7 cls_cnt 0 2006.145.04:17:29.91#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:17:30.03#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:17:30.03#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:17:30.05#ibcon#[27=USB\r\n] 2006.145.04:17:30.08#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:17:30.08#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:17:30.08#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.04:17:30.08#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.04:17:30.08$vck44/vblo=8,744.99 2006.145.04:17:30.08#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.04:17:30.08#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.04:17:30.08#ibcon#ireg 17 cls_cnt 0 2006.145.04:17:30.08#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:17:30.08#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:17:30.08#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:17:30.10#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.04:17:30.14#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:17:30.14#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:17:30.14#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.04:17:30.14#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.04:17:30.14$vck44/vb=8,4 2006.145.04:17:30.14#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.04:17:30.14#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.04:17:30.14#ibcon#ireg 11 cls_cnt 2 2006.145.04:17:30.14#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:17:30.20#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:17:30.20#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:17:30.22#ibcon#[27=AT08-04\r\n] 2006.145.04:17:30.25#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:17:30.25#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:17:30.25#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.04:17:30.25#ibcon#ireg 7 cls_cnt 0 2006.145.04:17:30.25#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:17:30.37#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:17:30.37#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:17:30.39#ibcon#[27=USB\r\n] 2006.145.04:17:30.42#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:17:30.42#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:17:30.42#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.04:17:30.42#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.04:17:30.42$vck44/vabw=wide 2006.145.04:17:30.42#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.04:17:30.42#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.04:17:30.42#ibcon#ireg 8 cls_cnt 0 2006.145.04:17:30.42#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:17:30.42#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:17:30.42#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:17:30.44#ibcon#[25=BW32\r\n] 2006.145.04:17:30.47#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:17:30.47#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:17:30.47#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.04:17:30.47#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.04:17:30.47$vck44/vbbw=wide 2006.145.04:17:30.47#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.04:17:30.47#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.04:17:30.47#ibcon#ireg 8 cls_cnt 0 2006.145.04:17:30.47#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.04:17:30.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.04:17:30.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.04:17:30.56#ibcon#[27=BW32\r\n] 2006.145.04:17:30.59#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.04:17:30.59#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.04:17:30.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.04:17:30.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.04:17:30.59$setupk4/ifdk4 2006.145.04:17:30.59$ifdk4/lo= 2006.145.04:17:30.59$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.04:17:30.59$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.04:17:30.59$ifdk4/patch= 2006.145.04:17:30.59$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.04:17:30.59$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.04:17:30.59$setupk4/!*+20s 2006.145.04:17:31.54#abcon#<5=/06 4.9 9.2 20.52 631016.6\r\n> 2006.145.04:17:31.56#abcon#{5=INTERFACE CLEAR} 2006.145.04:17:31.62#abcon#[5=S1D000X0/0*\r\n] 2006.145.04:17:41.71#abcon#<5=/06 4.9 9.2 20.52 611016.6\r\n> 2006.145.04:17:41.73#abcon#{5=INTERFACE CLEAR} 2006.145.04:17:41.79#abcon#[5=S1D000X0/0*\r\n] 2006.145.04:17:42.14#trakl#Source acquired 2006.145.04:17:43.14#flagr#flagr/antenna,acquired 2006.145.04:17:45.08$setupk4/"tpicd 2006.145.04:17:45.08$setupk4/echo=off 2006.145.04:17:45.08$setupk4/xlog=off 2006.145.04:17:45.08:!2006.145.04:19:08 2006.145.04:19:08.00:preob 2006.145.04:19:08.14/onsource/TRACKING 2006.145.04:19:08.14:!2006.145.04:19:18 2006.145.04:19:18.00:"tape 2006.145.04:19:18.00:"st=record 2006.145.04:19:18.00:data_valid=on 2006.145.04:19:18.00:midob 2006.145.04:19:19.14/onsource/TRACKING 2006.145.04:19:19.14/wx/20.49,1016.6,65 2006.145.04:19:19.33/cable/+6.5446E-03 2006.145.04:19:20.42/va/01,08,usb,yes,28,30 2006.145.04:19:20.42/va/02,07,usb,yes,30,31 2006.145.04:19:20.42/va/03,08,usb,yes,27,28 2006.145.04:19:20.42/va/04,07,usb,yes,31,33 2006.145.04:19:20.42/va/05,04,usb,yes,27,27 2006.145.04:19:20.42/va/06,04,usb,yes,30,30 2006.145.04:19:20.42/va/07,04,usb,yes,31,32 2006.145.04:19:20.42/va/08,04,usb,yes,26,31 2006.145.04:19:20.65/valo/01,524.99,yes,locked 2006.145.04:19:20.65/valo/02,534.99,yes,locked 2006.145.04:19:20.65/valo/03,564.99,yes,locked 2006.145.04:19:20.65/valo/04,624.99,yes,locked 2006.145.04:19:20.65/valo/05,734.99,yes,locked 2006.145.04:19:20.65/valo/06,814.99,yes,locked 2006.145.04:19:20.65/valo/07,864.99,yes,locked 2006.145.04:19:20.65/valo/08,884.99,yes,locked 2006.145.04:19:21.74/vb/01,03,usb,yes,35,33 2006.145.04:19:21.74/vb/02,04,usb,yes,31,31 2006.145.04:19:21.74/vb/03,04,usb,yes,28,31 2006.145.04:19:21.74/vb/04,04,usb,yes,32,31 2006.145.04:19:21.74/vb/05,04,usb,yes,25,27 2006.145.04:19:21.74/vb/06,04,usb,yes,29,26 2006.145.04:19:21.74/vb/07,04,usb,yes,29,29 2006.145.04:19:21.74/vb/08,04,usb,yes,27,30 2006.145.04:19:21.97/vblo/01,629.99,yes,locked 2006.145.04:19:21.97/vblo/02,634.99,yes,locked 2006.145.04:19:21.97/vblo/03,649.99,yes,locked 2006.145.04:19:21.97/vblo/04,679.99,yes,locked 2006.145.04:19:21.97/vblo/05,709.99,yes,locked 2006.145.04:19:21.97/vblo/06,719.99,yes,locked 2006.145.04:19:21.97/vblo/07,734.99,yes,locked 2006.145.04:19:21.97/vblo/08,744.99,yes,locked 2006.145.04:19:22.12/vabw/8 2006.145.04:19:22.27/vbbw/8 2006.145.04:19:22.36/xfe/off,on,14.2 2006.145.04:19:22.74/ifatt/23,28,28,28 2006.145.04:19:23.08/fmout-gps/S +5.0E-08 2006.145.04:19:23.17:!2006.145.04:32:22 2006.145.04:32:22.00:data_valid=off 2006.145.04:32:22.01:"et 2006.145.04:32:22.01:!+3s 2006.145.04:32:25.03:"tape 2006.145.04:32:25.03:postob 2006.145.04:32:25.20/cable/+6.5426E-03 2006.145.04:32:25.20/wx/20.50,1016.7,64 2006.145.04:32:25.28/fmout-gps/S +4.8E-08 2006.145.04:32:25.28:scan_name=145-0434,jd0605,430 2006.145.04:32:25.28:source=0059+581,010245.76,582411.1,2000.0,cw 2006.145.04:32:27.14:checkk5 2006.145.04:32:27.14#flagr#flagr/antenna,new-source 2006.145.04:32:27.72/chk_autoobs//k5ts1/ autoobs is running! 2006.145.04:32:28.25/chk_autoobs//k5ts2/ autoobs is running! 2006.145.04:32:28.74/chk_autoobs//k5ts3/ autoobs is running! 2006.145.04:32:29.42/chk_autoobs//k5ts4/ autoobs is running! 2006.145.04:32:30.38/chk_obsdata//k5ts1/T1450419??a.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.04:32:31.18/chk_obsdata//k5ts2/T1450419??b.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.04:32:31.99/chk_obsdata//k5ts3/T1450419??c.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.04:32:33.00/chk_obsdata//k5ts4/T1450419??d.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.04:32:33.78/k5log//k5ts1_log_newline 2006.145.04:32:34.76/k5log//k5ts2_log_newline 2006.145.04:32:35.54/k5log//k5ts3_log_newline 2006.145.04:32:36.42/k5log//k5ts4_log_newline 2006.145.04:32:36.44/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.04:32:36.44:setupk4=1 2006.145.04:32:36.44$setupk4/echo=on 2006.145.04:32:36.44$setupk4/pcalon 2006.145.04:32:36.44$pcalon/"no phase cal control is implemented here 2006.145.04:32:36.44$setupk4/"tpicd=stop 2006.145.04:32:36.44$setupk4/"rec=synch_on 2006.145.04:32:36.44$setupk4/"rec_mode=128 2006.145.04:32:36.44$setupk4/!* 2006.145.04:32:36.44$setupk4/recpk4 2006.145.04:32:36.44$recpk4/recpatch= 2006.145.04:32:36.45$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.04:32:36.45$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.04:32:36.45$setupk4/vck44 2006.145.04:32:36.45$vck44/valo=1,524.99 2006.145.04:32:36.45#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.04:32:36.45#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.04:32:36.45#ibcon#ireg 17 cls_cnt 0 2006.145.04:32:36.45#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.04:32:36.45#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.04:32:36.45#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.04:32:36.48#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.04:32:36.53#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.04:32:36.53#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.04:32:36.53#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.04:32:36.53#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.04:32:36.53$vck44/va=1,8 2006.145.04:32:36.53#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.04:32:36.53#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.04:32:36.53#ibcon#ireg 11 cls_cnt 2 2006.145.04:32:36.53#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.04:32:36.53#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.04:32:36.53#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.04:32:36.55#ibcon#[25=AT01-08\r\n] 2006.145.04:32:36.58#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.04:32:36.58#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.04:32:36.58#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.04:32:36.58#ibcon#ireg 7 cls_cnt 0 2006.145.04:32:36.58#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.04:32:36.70#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.04:32:36.70#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.04:32:36.72#ibcon#[25=USB\r\n] 2006.145.04:32:36.75#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.04:32:36.75#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.04:32:36.75#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.04:32:36.75#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.04:32:36.75$vck44/valo=2,534.99 2006.145.04:32:36.75#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.04:32:36.75#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.04:32:36.75#ibcon#ireg 17 cls_cnt 0 2006.145.04:32:36.75#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:32:36.75#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:32:36.75#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:32:36.79#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.04:32:36.81#abcon#<5=/06 3.9 7.2 20.50 601016.7\r\n> 2006.145.04:32:36.82#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:32:36.82#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:32:36.82#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.04:32:36.82#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.04:32:36.82$vck44/va=2,7 2006.145.04:32:36.82#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.04:32:36.82#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.04:32:36.82#ibcon#ireg 11 cls_cnt 2 2006.145.04:32:36.82#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.04:32:36.83#abcon#{5=INTERFACE CLEAR} 2006.145.04:32:36.87#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.04:32:36.87#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.04:32:36.89#ibcon#[25=AT02-07\r\n] 2006.145.04:32:36.89#abcon#[5=S1D000X0/0*\r\n] 2006.145.04:32:36.92#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.04:32:36.92#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.04:32:36.92#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.04:32:36.92#ibcon#ireg 7 cls_cnt 0 2006.145.04:32:36.92#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.04:32:37.04#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.04:32:37.04#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.04:32:37.06#ibcon#[25=USB\r\n] 2006.145.04:32:37.09#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.04:32:37.09#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.04:32:37.09#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.04:32:37.09#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.04:32:37.09$vck44/valo=3,564.99 2006.145.04:32:37.09#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.04:32:37.09#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.04:32:37.09#ibcon#ireg 17 cls_cnt 0 2006.145.04:32:37.09#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.04:32:37.09#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.04:32:37.09#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.04:32:37.11#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.04:32:37.15#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.04:32:37.15#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.04:32:37.15#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.04:32:37.15#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.04:32:37.15$vck44/va=3,8 2006.145.04:32:37.15#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.04:32:37.15#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.04:32:37.15#ibcon#ireg 11 cls_cnt 2 2006.145.04:32:37.15#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.04:32:37.21#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.04:32:37.21#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.04:32:37.23#ibcon#[25=AT03-08\r\n] 2006.145.04:32:37.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.04:32:37.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.04:32:37.26#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.04:32:37.26#ibcon#ireg 7 cls_cnt 0 2006.145.04:32:37.26#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.04:32:37.38#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.04:32:37.38#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.04:32:37.40#ibcon#[25=USB\r\n] 2006.145.04:32:37.43#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.04:32:37.43#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.04:32:37.43#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.04:32:37.43#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.04:32:37.43$vck44/valo=4,624.99 2006.145.04:32:37.43#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.04:32:37.43#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.04:32:37.43#ibcon#ireg 17 cls_cnt 0 2006.145.04:32:37.43#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.04:32:37.43#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.04:32:37.43#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.04:32:37.45#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.04:32:37.49#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.04:32:37.49#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.04:32:37.49#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.04:32:37.49#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.04:32:37.49$vck44/va=4,7 2006.145.04:32:37.49#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.04:32:37.49#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.04:32:37.49#ibcon#ireg 11 cls_cnt 2 2006.145.04:32:37.49#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.04:32:37.55#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.04:32:37.55#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.04:32:37.57#ibcon#[25=AT04-07\r\n] 2006.145.04:32:37.60#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.04:32:37.60#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.04:32:37.60#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.04:32:37.60#ibcon#ireg 7 cls_cnt 0 2006.145.04:32:37.60#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.04:32:37.72#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.04:32:37.72#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.04:32:37.74#ibcon#[25=USB\r\n] 2006.145.04:32:37.77#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.04:32:37.77#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.04:32:37.77#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.04:32:37.77#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.04:32:37.77$vck44/valo=5,734.99 2006.145.04:32:37.77#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.04:32:37.77#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.04:32:37.77#ibcon#ireg 17 cls_cnt 0 2006.145.04:32:37.77#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.04:32:37.77#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.04:32:37.77#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.04:32:37.79#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.04:32:37.83#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.04:32:37.83#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.04:32:37.83#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.04:32:37.83#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.04:32:37.83$vck44/va=5,4 2006.145.04:32:37.83#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.04:32:37.83#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.04:32:37.83#ibcon#ireg 11 cls_cnt 2 2006.145.04:32:37.83#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.04:32:37.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.04:32:37.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.04:32:37.91#ibcon#[25=AT05-04\r\n] 2006.145.04:32:37.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.04:32:37.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.04:32:37.94#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.04:32:37.94#ibcon#ireg 7 cls_cnt 0 2006.145.04:32:37.94#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.04:32:38.06#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.04:32:38.06#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.04:32:38.08#ibcon#[25=USB\r\n] 2006.145.04:32:38.11#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.04:32:38.11#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.04:32:38.11#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.04:32:38.11#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.04:32:38.11$vck44/valo=6,814.99 2006.145.04:32:38.11#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.04:32:38.11#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.04:32:38.11#ibcon#ireg 17 cls_cnt 0 2006.145.04:32:38.11#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.04:32:38.11#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.04:32:38.11#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.04:32:38.13#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.04:32:38.17#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.04:32:38.17#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.04:32:38.17#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.04:32:38.17#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.04:32:38.17$vck44/va=6,4 2006.145.04:32:38.17#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.04:32:38.17#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.04:32:38.17#ibcon#ireg 11 cls_cnt 2 2006.145.04:32:38.17#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.04:32:38.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.04:32:38.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.04:32:38.26#ibcon#[25=AT06-04\r\n] 2006.145.04:32:38.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.04:32:38.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.04:32:38.28#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.04:32:38.28#ibcon#ireg 7 cls_cnt 0 2006.145.04:32:38.28#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.04:32:38.40#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.04:32:38.40#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.04:32:38.42#ibcon#[25=USB\r\n] 2006.145.04:32:38.45#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.04:32:38.45#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.04:32:38.45#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.04:32:38.45#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.04:32:38.45$vck44/valo=7,864.99 2006.145.04:32:38.45#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.04:32:38.45#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.04:32:38.45#ibcon#ireg 17 cls_cnt 0 2006.145.04:32:38.45#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.04:32:38.45#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.04:32:38.45#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.04:32:38.48#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.04:32:38.52#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.04:32:38.52#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.04:32:38.52#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.04:32:38.52#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.04:32:38.52$vck44/va=7,4 2006.145.04:32:38.52#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.04:32:38.52#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.04:32:38.52#ibcon#ireg 11 cls_cnt 2 2006.145.04:32:38.52#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.04:32:38.57#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.04:32:38.57#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.04:32:38.59#ibcon#[25=AT07-04\r\n] 2006.145.04:32:38.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.04:32:38.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.04:32:38.62#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.04:32:38.62#ibcon#ireg 7 cls_cnt 0 2006.145.04:32:38.62#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.04:32:38.74#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.04:32:38.74#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.04:32:38.76#ibcon#[25=USB\r\n] 2006.145.04:32:38.79#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.04:32:38.79#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.04:32:38.79#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.04:32:38.79#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.04:32:38.79$vck44/valo=8,884.99 2006.145.04:32:38.79#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.04:32:38.79#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.04:32:38.79#ibcon#ireg 17 cls_cnt 0 2006.145.04:32:38.79#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.04:32:38.79#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.04:32:38.79#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.04:32:38.81#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.04:32:38.85#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.04:32:38.85#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.04:32:38.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.04:32:38.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.04:32:38.85$vck44/va=8,4 2006.145.04:32:38.85#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.04:32:38.85#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.04:32:38.85#ibcon#ireg 11 cls_cnt 2 2006.145.04:32:38.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.04:32:38.91#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.04:32:38.91#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.04:32:38.93#ibcon#[25=AT08-04\r\n] 2006.145.04:32:38.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.04:32:38.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.04:32:38.96#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.04:32:38.96#ibcon#ireg 7 cls_cnt 0 2006.145.04:32:38.96#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.04:32:39.08#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.04:32:39.08#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.04:32:39.10#ibcon#[25=USB\r\n] 2006.145.04:32:39.13#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.04:32:39.13#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.04:32:39.13#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.04:32:39.13#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.04:32:39.13$vck44/vblo=1,629.99 2006.145.04:32:39.13#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.04:32:39.13#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.04:32:39.13#ibcon#ireg 17 cls_cnt 0 2006.145.04:32:39.13#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.04:32:39.13#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.04:32:39.13#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.04:32:39.15#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.04:32:39.19#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.04:32:39.19#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.04:32:39.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.04:32:39.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.04:32:39.19$vck44/vb=1,3 2006.145.04:32:39.19#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.04:32:39.19#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.04:32:39.19#ibcon#ireg 11 cls_cnt 2 2006.145.04:32:39.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.04:32:39.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.04:32:39.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.04:32:39.21#ibcon#[27=AT01-03\r\n] 2006.145.04:32:39.24#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.04:32:39.24#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.04:32:39.24#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.04:32:39.24#ibcon#ireg 7 cls_cnt 0 2006.145.04:32:39.24#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.04:32:39.36#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.04:32:39.36#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.04:32:39.38#ibcon#[27=USB\r\n] 2006.145.04:32:39.41#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.04:32:39.41#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.04:32:39.41#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.04:32:39.41#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.04:32:39.41$vck44/vblo=2,634.99 2006.145.04:32:39.41#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.04:32:39.41#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.04:32:39.41#ibcon#ireg 17 cls_cnt 0 2006.145.04:32:39.41#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.04:32:39.41#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.04:32:39.41#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.04:32:39.43#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.04:32:39.47#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.04:32:39.47#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.04:32:39.47#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.04:32:39.47#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.04:32:39.47$vck44/vb=2,4 2006.145.04:32:39.47#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.04:32:39.47#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.04:32:39.47#ibcon#ireg 11 cls_cnt 2 2006.145.04:32:39.47#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.04:32:39.53#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.04:32:39.53#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.04:32:39.55#ibcon#[27=AT02-04\r\n] 2006.145.04:32:39.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.04:32:39.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.04:32:39.58#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.04:32:39.58#ibcon#ireg 7 cls_cnt 0 2006.145.04:32:39.58#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.04:32:39.70#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.04:32:39.70#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.04:32:39.72#ibcon#[27=USB\r\n] 2006.145.04:32:39.75#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.04:32:39.75#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.04:32:39.75#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.04:32:39.75#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.04:32:39.75$vck44/vblo=3,649.99 2006.145.04:32:39.75#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.04:32:39.75#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.04:32:39.75#ibcon#ireg 17 cls_cnt 0 2006.145.04:32:39.75#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.04:32:39.75#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.04:32:39.75#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.04:32:39.77#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.04:32:39.81#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.04:32:39.81#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.04:32:39.81#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.04:32:39.81#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.04:32:39.81$vck44/vb=3,4 2006.145.04:32:39.81#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.04:32:39.81#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.04:32:39.81#ibcon#ireg 11 cls_cnt 2 2006.145.04:32:39.81#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.04:32:39.87#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.04:32:39.87#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.04:32:39.89#ibcon#[27=AT03-04\r\n] 2006.145.04:32:39.93#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.04:32:39.93#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.04:32:39.93#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.04:32:39.93#ibcon#ireg 7 cls_cnt 0 2006.145.04:32:39.93#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.04:32:40.04#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.04:32:40.04#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.04:32:40.06#ibcon#[27=USB\r\n] 2006.145.04:32:40.09#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.04:32:40.09#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.04:32:40.09#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.04:32:40.09#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.04:32:40.09$vck44/vblo=4,679.99 2006.145.04:32:40.09#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.04:32:40.09#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.04:32:40.09#ibcon#ireg 17 cls_cnt 0 2006.145.04:32:40.09#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.04:32:40.09#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.04:32:40.09#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.04:32:40.11#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.04:32:40.15#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.04:32:40.15#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.04:32:40.15#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.04:32:40.15#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.04:32:40.15$vck44/vb=4,4 2006.145.04:32:40.15#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.04:32:40.15#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.04:32:40.15#ibcon#ireg 11 cls_cnt 2 2006.145.04:32:40.15#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.04:32:40.21#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.04:32:40.21#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.04:32:40.23#ibcon#[27=AT04-04\r\n] 2006.145.04:32:40.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.04:32:40.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.04:32:40.26#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.04:32:40.26#ibcon#ireg 7 cls_cnt 0 2006.145.04:32:40.26#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.04:32:40.38#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.04:32:40.38#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.04:32:40.40#ibcon#[27=USB\r\n] 2006.145.04:32:40.43#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.04:32:40.43#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.04:32:40.43#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.04:32:40.43#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.04:32:40.43$vck44/vblo=5,709.99 2006.145.04:32:40.43#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.04:32:40.43#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.04:32:40.43#ibcon#ireg 17 cls_cnt 0 2006.145.04:32:40.43#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.04:32:40.43#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.04:32:40.43#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.04:32:40.45#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.04:32:40.49#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.04:32:40.49#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.04:32:40.49#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.04:32:40.49#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.04:32:40.49$vck44/vb=5,4 2006.145.04:32:40.49#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.04:32:40.49#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.04:32:40.49#ibcon#ireg 11 cls_cnt 2 2006.145.04:32:40.49#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.04:32:40.55#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.04:32:40.55#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.04:32:40.57#ibcon#[27=AT05-04\r\n] 2006.145.04:32:40.60#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.04:32:40.60#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.04:32:40.60#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.04:32:40.60#ibcon#ireg 7 cls_cnt 0 2006.145.04:32:40.60#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.04:32:40.72#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.04:32:40.72#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.04:32:40.74#ibcon#[27=USB\r\n] 2006.145.04:32:40.77#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.04:32:40.77#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.04:32:40.77#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.04:32:40.77#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.04:32:40.77$vck44/vblo=6,719.99 2006.145.04:32:40.77#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.04:32:40.77#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.04:32:40.77#ibcon#ireg 17 cls_cnt 0 2006.145.04:32:40.77#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.04:32:40.77#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.04:32:40.77#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.04:32:40.79#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.04:32:40.83#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.04:32:40.83#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.04:32:40.83#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.04:32:40.83#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.04:32:40.83$vck44/vb=6,4 2006.145.04:32:40.83#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.04:32:40.83#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.04:32:40.83#ibcon#ireg 11 cls_cnt 2 2006.145.04:32:40.83#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.04:32:40.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.04:32:40.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.04:32:40.91#ibcon#[27=AT06-04\r\n] 2006.145.04:32:40.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.04:32:40.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.04:32:40.94#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.04:32:40.94#ibcon#ireg 7 cls_cnt 0 2006.145.04:32:40.94#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.04:32:41.06#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.04:32:41.06#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.04:32:41.08#ibcon#[27=USB\r\n] 2006.145.04:32:41.11#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.04:32:41.11#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.04:32:41.11#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.04:32:41.11#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.04:32:41.11$vck44/vblo=7,734.99 2006.145.04:32:41.11#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.04:32:41.11#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.04:32:41.11#ibcon#ireg 17 cls_cnt 0 2006.145.04:32:41.11#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.04:32:41.11#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.04:32:41.11#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.04:32:41.13#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.04:32:41.17#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.04:32:41.17#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.04:32:41.17#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.04:32:41.17#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.04:32:41.17$vck44/vb=7,4 2006.145.04:32:41.17#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.04:32:41.17#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.04:32:41.17#ibcon#ireg 11 cls_cnt 2 2006.145.04:32:41.17#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.04:32:41.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.04:32:41.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.04:32:41.25#ibcon#[27=AT07-04\r\n] 2006.145.04:32:41.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.04:32:41.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.04:32:41.28#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.04:32:41.28#ibcon#ireg 7 cls_cnt 0 2006.145.04:32:41.28#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.04:32:41.40#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.04:32:41.40#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.04:32:41.42#ibcon#[27=USB\r\n] 2006.145.04:32:41.45#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.04:32:41.45#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.04:32:41.45#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.04:32:41.45#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.04:32:41.45$vck44/vblo=8,744.99 2006.145.04:32:41.45#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.04:32:41.45#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.04:32:41.45#ibcon#ireg 17 cls_cnt 0 2006.145.04:32:41.45#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.04:32:41.45#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.04:32:41.45#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.04:32:41.47#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.04:32:41.51#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.04:32:41.51#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.04:32:41.51#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.04:32:41.51#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.04:32:41.51$vck44/vb=8,4 2006.145.04:32:41.51#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.04:32:41.51#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.04:32:41.51#ibcon#ireg 11 cls_cnt 2 2006.145.04:32:41.51#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.04:32:41.57#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.04:32:41.57#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.04:32:41.59#ibcon#[27=AT08-04\r\n] 2006.145.04:32:41.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.04:32:41.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.04:32:41.62#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.04:32:41.62#ibcon#ireg 7 cls_cnt 0 2006.145.04:32:41.62#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.04:32:41.74#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.04:32:41.74#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.04:32:41.76#ibcon#[27=USB\r\n] 2006.145.04:32:41.79#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.04:32:41.79#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.04:32:41.79#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.04:32:41.79#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.04:32:41.79$vck44/vabw=wide 2006.145.04:32:41.79#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.04:32:41.79#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.04:32:41.79#ibcon#ireg 8 cls_cnt 0 2006.145.04:32:41.79#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.04:32:41.79#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.04:32:41.79#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.04:32:41.81#ibcon#[25=BW32\r\n] 2006.145.04:32:41.84#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.04:32:41.84#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.04:32:41.84#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.04:32:41.84#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.04:32:41.84$vck44/vbbw=wide 2006.145.04:32:41.84#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.04:32:41.84#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.04:32:41.84#ibcon#ireg 8 cls_cnt 0 2006.145.04:32:41.84#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.04:32:41.91#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.04:32:41.91#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.04:32:41.93#ibcon#[27=BW32\r\n] 2006.145.04:32:41.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.04:32:41.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.04:32:41.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.04:32:41.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.04:32:41.96$setupk4/ifdk4 2006.145.04:32:41.96$ifdk4/lo= 2006.145.04:32:41.96$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.04:32:41.96$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.04:32:41.96$ifdk4/patch= 2006.145.04:32:41.96$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.04:32:41.96$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.04:32:41.97$setupk4/!*+20s 2006.145.04:32:46.98#abcon#<5=/06 3.9 7.2 20.51 601016.7\r\n> 2006.145.04:32:47.00#abcon#{5=INTERFACE CLEAR} 2006.145.04:32:47.06#abcon#[5=S1D000X0/0*\r\n] 2006.145.04:32:56.46$setupk4/"tpicd 2006.145.04:32:56.46$setupk4/echo=off 2006.145.04:32:56.46$setupk4/xlog=off 2006.145.04:32:56.46:!2006.145.04:34:16 2006.145.04:33:12.14#trakl#Source acquired 2006.145.04:33:13.14#flagr#flagr/antenna,acquired 2006.145.04:34:16.00:preob 2006.145.04:34:17.14/onsource/TRACKING 2006.145.04:34:17.14:!2006.145.04:34:26 2006.145.04:34:26.00:"tape 2006.145.04:34:26.00:"st=record 2006.145.04:34:26.00:data_valid=on 2006.145.04:34:26.00:midob 2006.145.04:34:26.14/onsource/TRACKING 2006.145.04:34:26.14/wx/20.51,1016.7,63 2006.145.04:34:26.33/cable/+6.5422E-03 2006.145.04:34:27.42/va/01,08,usb,yes,29,31 2006.145.04:34:27.42/va/02,07,usb,yes,31,31 2006.145.04:34:27.42/va/03,08,usb,yes,28,29 2006.145.04:34:27.42/va/04,07,usb,yes,32,33 2006.145.04:34:27.42/va/05,04,usb,yes,27,28 2006.145.04:34:27.42/va/06,04,usb,yes,31,31 2006.145.04:34:27.42/va/07,04,usb,yes,31,32 2006.145.04:34:27.42/va/08,04,usb,yes,26,32 2006.145.04:34:27.65/valo/01,524.99,yes,locked 2006.145.04:34:27.65/valo/02,534.99,yes,locked 2006.145.04:34:27.65/valo/03,564.99,yes,locked 2006.145.04:34:27.65/valo/04,624.99,yes,locked 2006.145.04:34:27.65/valo/05,734.99,yes,locked 2006.145.04:34:27.65/valo/06,814.99,yes,locked 2006.145.04:34:27.65/valo/07,864.99,yes,locked 2006.145.04:34:27.65/valo/08,884.99,yes,locked 2006.145.04:34:28.74/vb/01,03,usb,yes,36,33 2006.145.04:34:28.74/vb/02,04,usb,yes,31,31 2006.145.04:34:28.74/vb/03,04,usb,yes,28,31 2006.145.04:34:28.74/vb/04,04,usb,yes,32,31 2006.145.04:34:28.74/vb/05,04,usb,yes,25,27 2006.145.04:34:28.74/vb/06,04,usb,yes,29,26 2006.145.04:34:28.74/vb/07,04,usb,yes,29,29 2006.145.04:34:28.74/vb/08,04,usb,yes,27,30 2006.145.04:34:28.98/vblo/01,629.99,yes,locked 2006.145.04:34:28.98/vblo/02,634.99,yes,locked 2006.145.04:34:28.98/vblo/03,649.99,yes,locked 2006.145.04:34:28.98/vblo/04,679.99,yes,locked 2006.145.04:34:28.98/vblo/05,709.99,yes,locked 2006.145.04:34:28.98/vblo/06,719.99,yes,locked 2006.145.04:34:28.98/vblo/07,734.99,yes,locked 2006.145.04:34:28.98/vblo/08,744.99,yes,locked 2006.145.04:34:29.13/vabw/8 2006.145.04:34:29.28/vbbw/8 2006.145.04:34:29.37/xfe/off,on,14.7 2006.145.04:34:29.77/ifatt/23,28,28,28 2006.145.04:34:30.07/fmout-gps/S +4.7E-08 2006.145.04:34:30.15:!2006.145.04:41:36 2006.145.04:41:36.00:data_valid=off 2006.145.04:41:36.00:"et 2006.145.04:41:36.01:!+3s 2006.145.04:41:39.02:"tape 2006.145.04:41:39.02:postob 2006.145.04:41:39.10/cable/+6.5433E-03 2006.145.04:41:39.10/wx/20.61,1016.6,58 2006.145.04:41:39.17/fmout-gps/S +4.7E-08 2006.145.04:41:39.17:scan_name=145-0447,jd0605,40 2006.145.04:41:39.17:source=0537-441,053850.36,-440508.9,2000.0,cw 2006.145.04:41:41.14#flagr#flagr/antenna,new-source 2006.145.04:41:41.14:checkk5 2006.145.04:41:41.61/chk_autoobs//k5ts1/ autoobs is running! 2006.145.04:41:42.13/chk_autoobs//k5ts2/ autoobs is running! 2006.145.04:41:42.64/chk_autoobs//k5ts3/ autoobs is running! 2006.145.04:41:43.10/chk_autoobs//k5ts4/ autoobs is running! 2006.145.04:41:43.99/chk_obsdata//k5ts1/T1450434??a.dat file size is correct (nominal:1720MB, actual:1720MB). 2006.145.04:41:44.54/chk_obsdata//k5ts2/T1450434??b.dat file size is correct (nominal:1720MB, actual:1720MB). 2006.145.04:41:44.99/chk_obsdata//k5ts3/T1450434??c.dat file size is correct (nominal:1720MB, actual:1720MB). 2006.145.04:41:45.46/chk_obsdata//k5ts4/T1450434??d.dat file size is correct (nominal:1720MB, actual:1720MB). 2006.145.04:41:46.28/k5log//k5ts1_log_newline 2006.145.04:41:47.14/k5log//k5ts2_log_newline 2006.145.04:41:50.93/k5log//k5ts3_log_newline 2006.145.04:41:51.73/k5log//k5ts4_log_newline 2006.145.04:41:51.75/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.04:41:51.75:setupk4=1 2006.145.04:41:51.75$setupk4/echo=on 2006.145.04:41:51.75$setupk4/pcalon 2006.145.04:41:51.75$pcalon/"no phase cal control is implemented here 2006.145.04:41:51.75$setupk4/"tpicd=stop 2006.145.04:41:51.75$setupk4/"rec=synch_on 2006.145.04:41:51.75$setupk4/"rec_mode=128 2006.145.04:41:51.75$setupk4/!* 2006.145.04:41:51.75$setupk4/recpk4 2006.145.04:41:51.75$recpk4/recpatch= 2006.145.04:41:51.75$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.04:41:51.75$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.04:41:51.75$setupk4/vck44 2006.145.04:41:51.75$vck44/valo=1,524.99 2006.145.04:41:51.75#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.04:41:51.75#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.04:41:51.75#ibcon#ireg 17 cls_cnt 0 2006.145.04:41:51.75#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.04:41:51.75#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.04:41:51.76#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.04:41:51.79#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.04:41:51.84#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.04:41:51.84#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.04:41:51.84#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.04:41:51.84#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.04:41:51.84$vck44/va=1,8 2006.145.04:41:51.84#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.04:41:51.84#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.04:41:51.84#ibcon#ireg 11 cls_cnt 2 2006.145.04:41:51.84#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.04:41:51.84#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.04:41:51.84#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.04:41:51.86#ibcon#[25=AT01-08\r\n] 2006.145.04:41:51.89#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.04:41:51.89#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.04:41:51.89#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.04:41:51.89#ibcon#ireg 7 cls_cnt 0 2006.145.04:41:51.89#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.04:41:52.01#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.04:41:52.01#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.04:41:52.03#ibcon#[25=USB\r\n] 2006.145.04:41:52.06#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.04:41:52.06#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.04:41:52.06#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.04:41:52.06#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.04:41:52.06$vck44/valo=2,534.99 2006.145.04:41:52.06#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.04:41:52.06#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.04:41:52.06#ibcon#ireg 17 cls_cnt 0 2006.145.04:41:52.06#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.04:41:52.06#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.04:41:52.06#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.04:41:52.09#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.04:41:52.13#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.04:41:52.13#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.04:41:52.13#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.04:41:52.13#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.04:41:52.13$vck44/va=2,7 2006.145.04:41:52.13#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.04:41:52.13#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.04:41:52.13#ibcon#ireg 11 cls_cnt 2 2006.145.04:41:52.13#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.04:41:52.18#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.04:41:52.18#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.04:41:52.20#ibcon#[25=AT02-07\r\n] 2006.145.04:41:52.23#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.04:41:52.23#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.04:41:52.23#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.04:41:52.23#ibcon#ireg 7 cls_cnt 0 2006.145.04:41:52.23#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.04:41:52.35#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.04:41:52.35#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.04:41:52.37#ibcon#[25=USB\r\n] 2006.145.04:41:52.40#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.04:41:52.40#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.04:41:52.40#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.04:41:52.40#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.04:41:52.40$vck44/valo=3,564.99 2006.145.04:41:52.40#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.04:41:52.40#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.04:41:52.40#ibcon#ireg 17 cls_cnt 0 2006.145.04:41:52.40#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.04:41:52.40#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.04:41:52.40#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.04:41:52.42#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.04:41:52.46#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.04:41:52.46#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.04:41:52.46#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.04:41:52.46#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.04:41:52.46$vck44/va=3,8 2006.145.04:41:52.46#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.04:41:52.46#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.04:41:52.46#ibcon#ireg 11 cls_cnt 2 2006.145.04:41:52.46#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.04:41:52.52#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.04:41:52.52#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.04:41:52.54#ibcon#[25=AT03-08\r\n] 2006.145.04:41:52.57#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.04:41:52.57#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.04:41:52.57#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.04:41:52.57#ibcon#ireg 7 cls_cnt 0 2006.145.04:41:52.57#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.04:41:52.69#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.04:41:52.69#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.04:41:52.71#ibcon#[25=USB\r\n] 2006.145.04:41:52.74#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.04:41:52.74#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.04:41:52.74#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.04:41:52.74#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.04:41:52.74$vck44/valo=4,624.99 2006.145.04:41:52.74#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.04:41:52.74#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.04:41:52.74#ibcon#ireg 17 cls_cnt 0 2006.145.04:41:52.74#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.04:41:52.74#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.04:41:52.74#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.04:41:52.76#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.04:41:52.80#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.04:41:52.80#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.04:41:52.80#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.04:41:52.80#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.04:41:52.80$vck44/va=4,7 2006.145.04:41:52.80#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.04:41:52.80#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.04:41:52.80#ibcon#ireg 11 cls_cnt 2 2006.145.04:41:52.80#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.04:41:52.86#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.04:41:52.86#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.04:41:52.88#ibcon#[25=AT04-07\r\n] 2006.145.04:41:52.91#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.04:41:52.91#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.04:41:52.91#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.04:41:52.91#ibcon#ireg 7 cls_cnt 0 2006.145.04:41:52.91#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.04:41:53.03#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.04:41:53.03#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.04:41:53.05#ibcon#[25=USB\r\n] 2006.145.04:41:53.08#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.04:41:53.08#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.04:41:53.08#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.04:41:53.08#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.04:41:53.08$vck44/valo=5,734.99 2006.145.04:41:53.08#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.04:41:53.08#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.04:41:53.08#ibcon#ireg 17 cls_cnt 0 2006.145.04:41:53.08#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.04:41:53.08#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.04:41:53.08#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.04:41:53.10#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.04:41:53.14#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.04:41:53.14#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.04:41:53.14#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.04:41:53.14#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.04:41:53.14$vck44/va=5,4 2006.145.04:41:53.14#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.04:41:53.14#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.04:41:53.14#ibcon#ireg 11 cls_cnt 2 2006.145.04:41:53.14#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.04:41:53.20#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.04:41:53.20#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.04:41:53.22#ibcon#[25=AT05-04\r\n] 2006.145.04:41:53.25#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.04:41:53.25#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.04:41:53.25#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.04:41:53.25#ibcon#ireg 7 cls_cnt 0 2006.145.04:41:53.25#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.04:41:53.37#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.04:41:53.37#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.04:41:53.39#ibcon#[25=USB\r\n] 2006.145.04:41:53.44#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.04:41:53.44#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.04:41:53.44#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.04:41:53.44#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.04:41:53.44$vck44/valo=6,814.99 2006.145.04:41:53.44#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.04:41:53.44#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.04:41:53.44#ibcon#ireg 17 cls_cnt 0 2006.145.04:41:53.44#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.04:41:53.44#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.04:41:53.44#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.04:41:53.45#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.04:41:53.49#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.04:41:53.49#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.04:41:53.49#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.04:41:53.49#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.04:41:53.49$vck44/va=6,4 2006.145.04:41:53.49#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.04:41:53.49#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.04:41:53.49#ibcon#ireg 11 cls_cnt 2 2006.145.04:41:53.49#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.04:41:53.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.04:41:53.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.04:41:53.58#ibcon#[25=AT06-04\r\n] 2006.145.04:41:53.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.04:41:53.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.04:41:53.61#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.04:41:53.61#ibcon#ireg 7 cls_cnt 0 2006.145.04:41:53.61#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.04:41:53.73#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.04:41:53.73#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.04:41:53.75#ibcon#[25=USB\r\n] 2006.145.04:41:53.78#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.04:41:53.78#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.04:41:53.78#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.04:41:53.78#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.04:41:53.78$vck44/valo=7,864.99 2006.145.04:41:53.78#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.04:41:53.78#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.04:41:53.78#ibcon#ireg 17 cls_cnt 0 2006.145.04:41:53.78#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.04:41:53.78#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.04:41:53.78#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.04:41:53.80#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.04:41:53.84#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.04:41:53.84#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.04:41:53.84#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.04:41:53.84#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.04:41:53.84$vck44/va=7,4 2006.145.04:41:53.84#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.04:41:53.84#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.04:41:53.84#ibcon#ireg 11 cls_cnt 2 2006.145.04:41:53.84#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.04:41:53.90#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.04:41:53.90#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.04:41:53.92#ibcon#[25=AT07-04\r\n] 2006.145.04:41:53.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.04:41:53.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.04:41:53.95#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.04:41:53.95#ibcon#ireg 7 cls_cnt 0 2006.145.04:41:53.95#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.04:41:54.07#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.04:41:54.07#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.04:41:54.09#ibcon#[25=USB\r\n] 2006.145.04:41:54.12#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.04:41:54.12#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.04:41:54.12#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.04:41:54.12#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.04:41:54.12$vck44/valo=8,884.99 2006.145.04:41:54.12#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.04:41:54.12#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.04:41:54.12#ibcon#ireg 17 cls_cnt 0 2006.145.04:41:54.12#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.04:41:54.12#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.04:41:54.12#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.04:41:54.14#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.04:41:54.18#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.04:41:54.18#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.04:41:54.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.04:41:54.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.04:41:54.18$vck44/va=8,4 2006.145.04:41:54.18#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.04:41:54.18#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.04:41:54.18#ibcon#ireg 11 cls_cnt 2 2006.145.04:41:54.18#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.04:41:54.24#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.04:41:54.24#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.04:41:54.26#ibcon#[25=AT08-04\r\n] 2006.145.04:41:54.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.04:41:54.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.04:41:54.29#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.04:41:54.29#ibcon#ireg 7 cls_cnt 0 2006.145.04:41:54.29#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.04:41:54.41#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.04:41:54.41#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.04:41:54.43#ibcon#[25=USB\r\n] 2006.145.04:41:54.46#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.04:41:54.46#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.04:41:54.46#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.04:41:54.46#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.04:41:54.46$vck44/vblo=1,629.99 2006.145.04:41:54.46#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.04:41:54.46#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.04:41:54.46#ibcon#ireg 17 cls_cnt 0 2006.145.04:41:54.46#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.04:41:54.46#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.04:41:54.46#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.04:41:54.48#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.04:41:54.52#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.04:41:54.52#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.04:41:54.52#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.04:41:54.52#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.04:41:54.52$vck44/vb=1,3 2006.145.04:41:54.52#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.04:41:54.52#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.04:41:54.52#ibcon#ireg 11 cls_cnt 2 2006.145.04:41:54.52#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.04:41:54.52#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.04:41:54.52#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.04:41:54.54#ibcon#[27=AT01-03\r\n] 2006.145.04:41:54.57#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.04:41:54.57#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.04:41:54.57#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.04:41:54.57#ibcon#ireg 7 cls_cnt 0 2006.145.04:41:54.57#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.04:41:54.69#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.04:41:54.69#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.04:41:54.71#ibcon#[27=USB\r\n] 2006.145.04:41:54.74#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.04:41:54.74#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.04:41:54.74#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.04:41:54.74#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.04:41:54.74$vck44/vblo=2,634.99 2006.145.04:41:54.74#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.04:41:54.74#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.04:41:54.74#ibcon#ireg 17 cls_cnt 0 2006.145.04:41:54.74#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.04:41:54.74#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.04:41:54.74#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.04:41:54.76#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.04:41:54.80#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.04:41:54.80#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.04:41:54.80#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.04:41:54.80#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.04:41:54.80$vck44/vb=2,4 2006.145.04:41:54.80#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.04:41:54.80#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.04:41:54.80#ibcon#ireg 11 cls_cnt 2 2006.145.04:41:54.80#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.04:41:54.86#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.04:41:54.86#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.04:41:54.88#ibcon#[27=AT02-04\r\n] 2006.145.04:41:54.91#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.04:41:54.91#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.04:41:54.91#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.04:41:54.91#ibcon#ireg 7 cls_cnt 0 2006.145.04:41:54.91#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.04:41:55.03#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.04:41:55.03#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.04:41:55.05#ibcon#[27=USB\r\n] 2006.145.04:41:55.08#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.04:41:55.08#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.04:41:55.08#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.04:41:55.08#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.04:41:55.08$vck44/vblo=3,649.99 2006.145.04:41:55.08#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.04:41:55.08#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.04:41:55.08#ibcon#ireg 17 cls_cnt 0 2006.145.04:41:55.08#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.04:41:55.08#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.04:41:55.08#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.04:41:55.10#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.04:41:55.14#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.04:41:55.14#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.04:41:55.14#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.04:41:55.14#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.04:41:55.14$vck44/vb=3,4 2006.145.04:41:55.14#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.04:41:55.14#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.04:41:55.14#ibcon#ireg 11 cls_cnt 2 2006.145.04:41:55.14#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.04:41:55.20#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.04:41:55.20#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.04:41:55.22#ibcon#[27=AT03-04\r\n] 2006.145.04:41:55.25#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.04:41:55.25#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.04:41:55.25#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.04:41:55.25#ibcon#ireg 7 cls_cnt 0 2006.145.04:41:55.25#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.04:41:55.37#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.04:41:55.37#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.04:41:55.39#ibcon#[27=USB\r\n] 2006.145.04:41:55.42#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.04:41:55.42#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.04:41:55.42#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.04:41:55.42#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.04:41:55.42$vck44/vblo=4,679.99 2006.145.04:41:55.42#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.04:41:55.42#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.04:41:55.42#ibcon#ireg 17 cls_cnt 0 2006.145.04:41:55.42#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.04:41:55.42#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.04:41:55.42#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.04:41:55.44#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.04:41:55.48#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.04:41:55.48#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.04:41:55.48#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.04:41:55.48#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.04:41:55.48$vck44/vb=4,4 2006.145.04:41:55.48#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.04:41:55.48#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.04:41:55.48#ibcon#ireg 11 cls_cnt 2 2006.145.04:41:55.48#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.04:41:55.54#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.04:41:55.54#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.04:41:55.56#ibcon#[27=AT04-04\r\n] 2006.145.04:41:55.59#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.04:41:55.59#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.04:41:55.59#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.04:41:55.59#ibcon#ireg 7 cls_cnt 0 2006.145.04:41:55.59#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.04:41:55.71#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.04:41:55.71#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.04:41:55.73#ibcon#[27=USB\r\n] 2006.145.04:41:55.76#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.04:41:55.76#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.04:41:55.76#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.04:41:55.76#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.04:41:55.76$vck44/vblo=5,709.99 2006.145.04:41:55.76#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.04:41:55.76#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.04:41:55.76#ibcon#ireg 17 cls_cnt 0 2006.145.04:41:55.76#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.04:41:55.76#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.04:41:55.76#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.04:41:55.78#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.04:41:55.82#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.04:41:55.82#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.04:41:55.82#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.04:41:55.82#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.04:41:55.82$vck44/vb=5,4 2006.145.04:41:55.82#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.04:41:55.82#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.04:41:55.82#ibcon#ireg 11 cls_cnt 2 2006.145.04:41:55.82#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.04:41:55.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.04:41:55.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.04:41:55.90#ibcon#[27=AT05-04\r\n] 2006.145.04:41:55.93#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.04:41:55.93#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.04:41:55.93#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.04:41:55.93#ibcon#ireg 7 cls_cnt 0 2006.145.04:41:55.93#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.04:41:56.05#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.04:41:56.05#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.04:41:56.07#ibcon#[27=USB\r\n] 2006.145.04:41:56.10#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.04:41:56.10#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.04:41:56.10#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.04:41:56.10#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.04:41:56.10$vck44/vblo=6,719.99 2006.145.04:41:56.10#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.04:41:56.10#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.04:41:56.10#ibcon#ireg 17 cls_cnt 0 2006.145.04:41:56.10#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.04:41:56.10#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.04:41:56.10#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.04:41:56.12#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.04:41:56.16#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.04:41:56.16#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.04:41:56.16#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.04:41:56.16#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.04:41:56.16$vck44/vb=6,4 2006.145.04:41:56.16#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.04:41:56.16#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.04:41:56.16#ibcon#ireg 11 cls_cnt 2 2006.145.04:41:56.16#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.04:41:56.22#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.04:41:56.22#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.04:41:56.24#ibcon#[27=AT06-04\r\n] 2006.145.04:41:56.27#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.04:41:56.27#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.04:41:56.27#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.04:41:56.27#ibcon#ireg 7 cls_cnt 0 2006.145.04:41:56.27#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.04:41:56.31#abcon#<5=/05 3.3 7.4 20.61 601016.7\r\n> 2006.145.04:41:56.33#abcon#{5=INTERFACE CLEAR} 2006.145.04:41:56.39#abcon#[5=S1D000X0/0*\r\n] 2006.145.04:41:56.39#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.04:41:56.39#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.04:41:56.41#ibcon#[27=USB\r\n] 2006.145.04:41:56.44#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.04:41:56.44#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.04:41:56.44#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.04:41:56.44#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.04:41:56.44$vck44/vblo=7,734.99 2006.145.04:41:56.44#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.04:41:56.44#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.04:41:56.44#ibcon#ireg 17 cls_cnt 0 2006.145.04:41:56.44#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.04:41:56.44#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.04:41:56.44#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.04:41:56.46#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.04:41:56.50#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.04:41:56.50#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.04:41:56.50#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.04:41:56.50#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.04:41:56.50$vck44/vb=7,4 2006.145.04:41:56.50#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.04:41:56.50#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.04:41:56.50#ibcon#ireg 11 cls_cnt 2 2006.145.04:41:56.50#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.04:41:56.56#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.04:41:56.56#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.04:41:56.58#ibcon#[27=AT07-04\r\n] 2006.145.04:41:56.61#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.04:41:56.61#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.04:41:56.61#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.04:41:56.61#ibcon#ireg 7 cls_cnt 0 2006.145.04:41:56.61#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.04:41:56.73#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.04:41:56.73#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.04:41:56.75#ibcon#[27=USB\r\n] 2006.145.04:41:56.78#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.04:41:56.78#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.04:41:56.78#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.04:41:56.78#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.04:41:56.78$vck44/vblo=8,744.99 2006.145.04:41:56.78#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.04:41:56.78#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.04:41:56.78#ibcon#ireg 17 cls_cnt 0 2006.145.04:41:56.78#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.04:41:56.78#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.04:41:56.78#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.04:41:56.80#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.04:41:56.84#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.04:41:56.84#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.04:41:56.84#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.04:41:56.84#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.04:41:56.84$vck44/vb=8,4 2006.145.04:41:56.84#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.04:41:56.84#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.04:41:56.84#ibcon#ireg 11 cls_cnt 2 2006.145.04:41:56.84#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.04:41:56.90#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.04:41:56.90#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.04:41:56.92#ibcon#[27=AT08-04\r\n] 2006.145.04:41:56.95#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.04:41:56.95#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.04:41:56.95#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.04:41:56.95#ibcon#ireg 7 cls_cnt 0 2006.145.04:41:56.95#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.04:41:57.07#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.04:41:57.07#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.04:41:57.09#ibcon#[27=USB\r\n] 2006.145.04:41:57.12#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.04:41:57.12#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.04:41:57.12#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.04:41:57.12#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.04:41:57.12$vck44/vabw=wide 2006.145.04:41:57.12#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.04:41:57.12#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.04:41:57.12#ibcon#ireg 8 cls_cnt 0 2006.145.04:41:57.12#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.04:41:57.12#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.04:41:57.12#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.04:41:57.14#ibcon#[25=BW32\r\n] 2006.145.04:41:57.17#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.04:41:57.17#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.04:41:57.17#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.04:41:57.17#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.04:41:57.17$vck44/vbbw=wide 2006.145.04:41:57.17#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.04:41:57.17#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.04:41:57.17#ibcon#ireg 8 cls_cnt 0 2006.145.04:41:57.17#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:41:57.24#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:41:57.24#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:41:57.26#ibcon#[27=BW32\r\n] 2006.145.04:41:57.29#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:41:57.29#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:41:57.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.04:41:57.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.04:41:57.29$setupk4/ifdk4 2006.145.04:41:57.29$ifdk4/lo= 2006.145.04:41:57.29$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.04:41:57.29$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.04:41:57.29$ifdk4/patch= 2006.145.04:41:57.29$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.04:41:57.29$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.04:41:57.29$setupk4/!*+20s 2006.145.04:42:06.48#abcon#<5=/05 3.3 7.4 20.62 601016.6\r\n> 2006.145.04:42:06.50#abcon#{5=INTERFACE CLEAR} 2006.145.04:42:06.56#abcon#[5=S1D000X0/0*\r\n] 2006.145.04:42:11.76$setupk4/"tpicd 2006.145.04:42:11.76$setupk4/echo=off 2006.145.04:42:11.76$setupk4/xlog=off 2006.145.04:42:11.76:!2006.145.04:47:44 2006.145.04:42:32.14#trakl#Source acquired 2006.145.04:42:33.14#flagr#flagr/antenna,acquired 2006.145.04:47:44.00:preob 2006.145.04:47:44.14/onsource/TRACKING 2006.145.04:47:44.14:!2006.145.04:47:54 2006.145.04:47:54.00:"tape 2006.145.04:47:54.00:"st=record 2006.145.04:47:54.00:data_valid=on 2006.145.04:47:54.00:midob 2006.145.04:47:54.14/onsource/TRACKING 2006.145.04:47:54.14/wx/20.65,1016.6,58 2006.145.04:47:54.25/cable/+6.5431E-03 2006.145.04:47:55.34/va/01,08,usb,yes,34,36 2006.145.04:47:55.34/va/02,07,usb,yes,36,37 2006.145.04:47:55.34/va/03,08,usb,yes,33,34 2006.145.04:47:55.34/va/04,07,usb,yes,37,39 2006.145.04:47:55.34/va/05,04,usb,yes,33,33 2006.145.04:47:55.34/va/06,04,usb,yes,37,36 2006.145.04:47:55.34/va/07,04,usb,yes,37,38 2006.145.04:47:55.34/va/08,04,usb,yes,32,38 2006.145.04:47:55.57/valo/01,524.99,yes,locked 2006.145.04:47:55.57/valo/02,534.99,yes,locked 2006.145.04:47:55.57/valo/03,564.99,yes,locked 2006.145.04:47:55.57/valo/04,624.99,yes,locked 2006.145.04:47:55.57/valo/05,734.99,yes,locked 2006.145.04:47:55.57/valo/06,814.99,yes,locked 2006.145.04:47:55.57/valo/07,864.99,yes,locked 2006.145.04:47:55.57/valo/08,884.99,yes,locked 2006.145.04:47:56.66/vb/01,03,usb,yes,40,37 2006.145.04:47:56.66/vb/02,04,usb,yes,35,35 2006.145.04:47:56.66/vb/03,04,usb,yes,32,35 2006.145.04:47:56.66/vb/04,04,usb,yes,36,35 2006.145.04:47:56.66/vb/05,04,usb,yes,29,31 2006.145.04:47:56.66/vb/06,04,usb,yes,33,29 2006.145.04:47:56.66/vb/07,04,usb,yes,33,33 2006.145.04:47:56.66/vb/08,04,usb,yes,30,34 2006.145.04:47:56.89/vblo/01,629.99,yes,locked 2006.145.04:47:56.89/vblo/02,634.99,yes,locked 2006.145.04:47:56.89/vblo/03,649.99,yes,locked 2006.145.04:47:56.89/vblo/04,679.99,yes,locked 2006.145.04:47:56.89/vblo/05,709.99,yes,locked 2006.145.04:47:56.89/vblo/06,719.99,yes,locked 2006.145.04:47:56.89/vblo/07,734.99,yes,locked 2006.145.04:47:56.89/vblo/08,744.99,yes,locked 2006.145.04:47:57.04/vabw/8 2006.145.04:47:57.19/vbbw/8 2006.145.04:47:57.28/xfe/off,on,14.7 2006.145.04:47:57.66/ifatt/23,28,28,28 2006.145.04:47:58.08/fmout-gps/S +5.0E-08 2006.145.04:47:58.13:!2006.145.04:48:34 2006.145.04:48:34.00:data_valid=off 2006.145.04:48:34.00:"et 2006.145.04:48:34.01:!+3s 2006.145.04:48:37.02:"tape 2006.145.04:48:37.02:postob 2006.145.04:48:37.17/cable/+6.5424E-03 2006.145.04:48:37.17/wx/20.65,1016.6,57 2006.145.04:48:38.08/fmout-gps/S +5.1E-08 2006.145.04:48:38.08:scan_name=145-0451,jd0605,50 2006.145.04:48:38.09:source=0552+398,055530.81,394849.2,2000.0,cw 2006.145.04:48:39.14#flagr#flagr/antenna,new-source 2006.145.04:48:39.14:checkk5 2006.145.04:48:39.61/chk_autoobs//k5ts1/ autoobs is running! 2006.145.04:48:40.07/chk_autoobs//k5ts2/ autoobs is running! 2006.145.04:48:40.66/chk_autoobs//k5ts3/ autoobs is running! 2006.145.04:48:41.12/chk_autoobs//k5ts4/ autoobs is running! 2006.145.04:48:41.65/chk_obsdata//k5ts1/T1450447??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.04:48:42.23/chk_obsdata//k5ts2/T1450447??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.04:48:42.72/chk_obsdata//k5ts3/T1450447??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.04:48:43.22/chk_obsdata//k5ts4/T1450447??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.04:48:44.03/k5log//k5ts1_log_newline 2006.145.04:48:44.84/k5log//k5ts2_log_newline 2006.145.04:48:45.83/k5log//k5ts3_log_newline 2006.145.04:48:47.08/k5log//k5ts4_log_newline 2006.145.04:48:47.10/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.04:48:47.10:setupk4=1 2006.145.04:48:47.10$setupk4/echo=on 2006.145.04:48:47.10$setupk4/pcalon 2006.145.04:48:47.10$pcalon/"no phase cal control is implemented here 2006.145.04:48:47.10$setupk4/"tpicd=stop 2006.145.04:48:47.10$setupk4/"rec=synch_on 2006.145.04:48:47.10$setupk4/"rec_mode=128 2006.145.04:48:47.10$setupk4/!* 2006.145.04:48:47.10$setupk4/recpk4 2006.145.04:48:47.10$recpk4/recpatch= 2006.145.04:48:47.10$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.04:48:47.10$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.04:48:47.10$setupk4/vck44 2006.145.04:48:47.10$vck44/valo=1,524.99 2006.145.04:48:47.10#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.04:48:47.10#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.04:48:47.10#ibcon#ireg 17 cls_cnt 0 2006.145.04:48:47.10#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.04:48:47.10#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.04:48:47.10#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.04:48:47.12#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.04:48:47.17#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.04:48:47.17#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.04:48:47.17#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.04:48:47.17#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.04:48:47.17$vck44/va=1,8 2006.145.04:48:47.17#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.04:48:47.17#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.04:48:47.17#ibcon#ireg 11 cls_cnt 2 2006.145.04:48:47.17#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.04:48:47.17#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.04:48:47.17#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.04:48:47.19#ibcon#[25=AT01-08\r\n] 2006.145.04:48:47.22#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.04:48:47.22#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.04:48:47.22#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.04:48:47.22#ibcon#ireg 7 cls_cnt 0 2006.145.04:48:47.22#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.04:48:47.34#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.04:48:47.34#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.04:48:47.36#ibcon#[25=USB\r\n] 2006.145.04:48:47.39#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.04:48:47.39#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.04:48:47.39#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.04:48:47.39#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.04:48:47.39$vck44/valo=2,534.99 2006.145.04:48:47.39#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.04:48:47.39#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.04:48:47.39#ibcon#ireg 17 cls_cnt 0 2006.145.04:48:47.39#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.04:48:47.39#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.04:48:47.39#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.04:48:47.42#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.04:48:47.46#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.04:48:47.46#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.04:48:47.46#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.04:48:47.46#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.04:48:47.46$vck44/va=2,7 2006.145.04:48:47.46#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.04:48:47.46#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.04:48:47.46#ibcon#ireg 11 cls_cnt 2 2006.145.04:48:47.46#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.04:48:47.51#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.04:48:47.51#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.04:48:47.53#ibcon#[25=AT02-07\r\n] 2006.145.04:48:47.56#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.04:48:47.56#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.04:48:47.56#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.04:48:47.56#ibcon#ireg 7 cls_cnt 0 2006.145.04:48:47.56#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.04:48:47.68#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.04:48:47.68#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.04:48:47.70#ibcon#[25=USB\r\n] 2006.145.04:48:47.73#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.04:48:47.73#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.04:48:47.73#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.04:48:47.73#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.04:48:47.73$vck44/valo=3,564.99 2006.145.04:48:47.73#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.04:48:47.73#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.04:48:47.73#ibcon#ireg 17 cls_cnt 0 2006.145.04:48:47.73#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.04:48:47.73#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.04:48:47.73#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.04:48:47.76#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.04:48:47.80#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.04:48:47.80#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.04:48:47.80#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.04:48:47.80#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.04:48:47.80$vck44/va=3,8 2006.145.04:48:47.80#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.04:48:47.80#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.04:48:47.80#ibcon#ireg 11 cls_cnt 2 2006.145.04:48:47.80#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.04:48:47.85#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.04:48:47.85#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.04:48:47.87#ibcon#[25=AT03-08\r\n] 2006.145.04:48:47.90#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.04:48:47.90#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.04:48:47.90#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.04:48:47.90#ibcon#ireg 7 cls_cnt 0 2006.145.04:48:47.90#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.04:48:48.02#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.04:48:48.02#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.04:48:48.04#ibcon#[25=USB\r\n] 2006.145.04:48:48.07#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.04:48:48.07#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.04:48:48.07#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.04:48:48.07#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.04:48:48.07$vck44/valo=4,624.99 2006.145.04:48:48.07#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.04:48:48.07#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.04:48:48.07#ibcon#ireg 17 cls_cnt 0 2006.145.04:48:48.07#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.04:48:48.07#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.04:48:48.07#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.04:48:48.09#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.04:48:48.13#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.04:48:48.13#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.04:48:48.13#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.04:48:48.13#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.04:48:48.13$vck44/va=4,7 2006.145.04:48:48.13#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.04:48:48.13#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.04:48:48.13#ibcon#ireg 11 cls_cnt 2 2006.145.04:48:48.13#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.04:48:48.19#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.04:48:48.19#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.04:48:48.21#ibcon#[25=AT04-07\r\n] 2006.145.04:48:48.24#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.04:48:48.24#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.04:48:48.24#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.04:48:48.24#ibcon#ireg 7 cls_cnt 0 2006.145.04:48:48.24#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.04:48:48.36#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.04:48:48.36#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.04:48:48.38#ibcon#[25=USB\r\n] 2006.145.04:48:48.41#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.04:48:48.41#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.04:48:48.41#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.04:48:48.41#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.04:48:48.41$vck44/valo=5,734.99 2006.145.04:48:48.41#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.04:48:48.41#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.04:48:48.41#ibcon#ireg 17 cls_cnt 0 2006.145.04:48:48.41#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.04:48:48.41#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.04:48:48.41#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.04:48:48.43#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.04:48:48.47#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.04:48:48.47#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.04:48:48.47#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.04:48:48.47#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.04:48:48.47$vck44/va=5,4 2006.145.04:48:48.47#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.04:48:48.47#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.04:48:48.47#ibcon#ireg 11 cls_cnt 2 2006.145.04:48:48.47#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.04:48:48.53#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.04:48:48.53#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.04:48:48.55#ibcon#[25=AT05-04\r\n] 2006.145.04:48:48.58#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.04:48:48.58#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.04:48:48.58#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.04:48:48.58#ibcon#ireg 7 cls_cnt 0 2006.145.04:48:48.58#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.04:48:48.70#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.04:48:48.70#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.04:48:48.72#ibcon#[25=USB\r\n] 2006.145.04:48:48.75#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.04:48:48.75#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.04:48:48.75#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.04:48:48.75#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.04:48:48.75$vck44/valo=6,814.99 2006.145.04:48:48.75#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.04:48:48.75#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.04:48:48.75#ibcon#ireg 17 cls_cnt 0 2006.145.04:48:48.75#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.04:48:48.75#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.04:48:48.75#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.04:48:48.77#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.04:48:48.81#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.04:48:48.81#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.04:48:48.81#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.04:48:48.81#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.04:48:48.81$vck44/va=6,4 2006.145.04:48:48.81#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.04:48:48.81#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.04:48:48.81#ibcon#ireg 11 cls_cnt 2 2006.145.04:48:48.81#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.04:48:48.87#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.04:48:48.87#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.04:48:48.89#ibcon#[25=AT06-04\r\n] 2006.145.04:48:48.92#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.04:48:48.92#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.04:48:48.92#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.04:48:48.92#ibcon#ireg 7 cls_cnt 0 2006.145.04:48:48.92#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.04:48:49.04#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.04:48:49.04#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.04:48:49.06#ibcon#[25=USB\r\n] 2006.145.04:48:49.09#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.04:48:49.09#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.04:48:49.09#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.04:48:49.09#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.04:48:49.09$vck44/valo=7,864.99 2006.145.04:48:49.09#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.04:48:49.09#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.04:48:49.09#ibcon#ireg 17 cls_cnt 0 2006.145.04:48:49.09#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.04:48:49.09#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.04:48:49.09#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.04:48:49.11#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.04:48:49.15#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.04:48:49.15#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.04:48:49.15#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.04:48:49.15#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.04:48:49.15$vck44/va=7,4 2006.145.04:48:49.15#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.04:48:49.15#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.04:48:49.15#ibcon#ireg 11 cls_cnt 2 2006.145.04:48:49.15#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.04:48:49.21#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.04:48:49.21#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.04:48:49.23#ibcon#[25=AT07-04\r\n] 2006.145.04:48:49.26#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.04:48:49.26#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.04:48:49.26#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.04:48:49.26#ibcon#ireg 7 cls_cnt 0 2006.145.04:48:49.26#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.04:48:49.38#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.04:48:49.38#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.04:48:49.40#ibcon#[25=USB\r\n] 2006.145.04:48:49.43#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.04:48:49.43#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.04:48:49.43#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.04:48:49.43#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.04:48:49.43$vck44/valo=8,884.99 2006.145.04:48:49.43#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.04:48:49.43#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.04:48:49.43#ibcon#ireg 17 cls_cnt 0 2006.145.04:48:49.43#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.04:48:49.43#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.04:48:49.43#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.04:48:49.45#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.04:48:49.49#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.04:48:49.49#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.04:48:49.49#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.04:48:49.49#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.04:48:49.49$vck44/va=8,4 2006.145.04:48:49.49#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.04:48:49.49#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.04:48:49.49#ibcon#ireg 11 cls_cnt 2 2006.145.04:48:49.49#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.04:48:49.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.04:48:49.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.04:48:49.57#ibcon#[25=AT08-04\r\n] 2006.145.04:48:49.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.04:48:49.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.04:48:49.60#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.04:48:49.60#ibcon#ireg 7 cls_cnt 0 2006.145.04:48:49.60#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.04:48:49.72#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.04:48:49.72#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.04:48:49.74#ibcon#[25=USB\r\n] 2006.145.04:48:49.77#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.04:48:49.77#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.04:48:49.77#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.04:48:49.77#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.04:48:49.77$vck44/vblo=1,629.99 2006.145.04:48:49.77#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.04:48:49.77#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.04:48:49.77#ibcon#ireg 17 cls_cnt 0 2006.145.04:48:49.77#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.04:48:49.77#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.04:48:49.77#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.04:48:49.79#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.04:48:49.83#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.04:48:49.83#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.04:48:49.83#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.04:48:49.83#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.04:48:49.83$vck44/vb=1,3 2006.145.04:48:49.83#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.04:48:49.83#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.04:48:49.83#ibcon#ireg 11 cls_cnt 2 2006.145.04:48:49.83#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.04:48:49.83#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.04:48:49.83#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.04:48:49.85#ibcon#[27=AT01-03\r\n] 2006.145.04:48:49.88#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.04:48:49.88#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.04:48:49.88#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.04:48:49.88#ibcon#ireg 7 cls_cnt 0 2006.145.04:48:49.88#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.04:48:50.00#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.04:48:50.00#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.04:48:50.02#ibcon#[27=USB\r\n] 2006.145.04:48:50.05#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.04:48:50.05#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.04:48:50.05#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.04:48:50.05#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.04:48:50.05$vck44/vblo=2,634.99 2006.145.04:48:50.05#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.04:48:50.05#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.04:48:50.05#ibcon#ireg 17 cls_cnt 0 2006.145.04:48:50.05#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.04:48:50.05#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.04:48:50.05#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.04:48:50.07#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.04:48:50.11#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.04:48:50.11#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.04:48:50.11#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.04:48:50.11#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.04:48:50.11$vck44/vb=2,4 2006.145.04:48:50.11#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.04:48:50.11#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.04:48:50.11#ibcon#ireg 11 cls_cnt 2 2006.145.04:48:50.11#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.04:48:50.17#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.04:48:50.17#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.04:48:50.19#ibcon#[27=AT02-04\r\n] 2006.145.04:48:50.22#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.04:48:50.22#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.04:48:50.22#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.04:48:50.22#ibcon#ireg 7 cls_cnt 0 2006.145.04:48:50.22#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.04:48:50.34#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.04:48:50.34#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.04:48:50.36#ibcon#[27=USB\r\n] 2006.145.04:48:50.39#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.04:48:50.39#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.04:48:50.39#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.04:48:50.39#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.04:48:50.39$vck44/vblo=3,649.99 2006.145.04:48:50.39#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.04:48:50.39#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.04:48:50.39#ibcon#ireg 17 cls_cnt 0 2006.145.04:48:50.39#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.04:48:50.39#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.04:48:50.39#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.04:48:50.41#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.04:48:50.45#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.04:48:50.45#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.04:48:50.45#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.04:48:50.45#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.04:48:50.45$vck44/vb=3,4 2006.145.04:48:50.45#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.04:48:50.45#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.04:48:50.45#ibcon#ireg 11 cls_cnt 2 2006.145.04:48:50.45#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.04:48:50.51#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.04:48:50.51#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.04:48:50.53#ibcon#[27=AT03-04\r\n] 2006.145.04:48:50.56#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.04:48:50.56#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.04:48:50.56#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.04:48:50.56#ibcon#ireg 7 cls_cnt 0 2006.145.04:48:50.56#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.04:48:50.68#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.04:48:50.68#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.04:48:50.70#ibcon#[27=USB\r\n] 2006.145.04:48:50.73#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.04:48:50.73#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.04:48:50.73#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.04:48:50.73#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.04:48:50.73$vck44/vblo=4,679.99 2006.145.04:48:50.73#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.04:48:50.73#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.04:48:50.73#ibcon#ireg 17 cls_cnt 0 2006.145.04:48:50.73#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.04:48:50.73#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.04:48:50.73#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.04:48:50.75#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.04:48:50.79#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.04:48:50.79#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.04:48:50.79#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.04:48:50.79#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.04:48:50.79$vck44/vb=4,4 2006.145.04:48:50.79#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.04:48:50.79#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.04:48:50.79#ibcon#ireg 11 cls_cnt 2 2006.145.04:48:50.79#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.04:48:50.85#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.04:48:50.85#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.04:48:50.87#ibcon#[27=AT04-04\r\n] 2006.145.04:48:50.90#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.04:48:50.90#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.04:48:50.90#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.04:48:50.90#ibcon#ireg 7 cls_cnt 0 2006.145.04:48:50.90#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.04:48:51.02#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.04:48:51.02#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.04:48:51.04#ibcon#[27=USB\r\n] 2006.145.04:48:51.07#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.04:48:51.07#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.04:48:51.07#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.04:48:51.07#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.04:48:51.07$vck44/vblo=5,709.99 2006.145.04:48:51.07#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.04:48:51.07#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.04:48:51.07#ibcon#ireg 17 cls_cnt 0 2006.145.04:48:51.07#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.04:48:51.07#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.04:48:51.07#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.04:48:51.09#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.04:48:51.13#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.04:48:51.13#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.04:48:51.13#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.04:48:51.13#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.04:48:51.13$vck44/vb=5,4 2006.145.04:48:51.13#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.04:48:51.13#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.04:48:51.13#ibcon#ireg 11 cls_cnt 2 2006.145.04:48:51.13#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.04:48:51.19#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.04:48:51.19#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.04:48:51.21#ibcon#[27=AT05-04\r\n] 2006.145.04:48:51.24#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.04:48:51.24#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.04:48:51.24#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.04:48:51.24#ibcon#ireg 7 cls_cnt 0 2006.145.04:48:51.24#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.04:48:51.36#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.04:48:51.36#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.04:48:51.38#ibcon#[27=USB\r\n] 2006.145.04:48:51.41#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.04:48:51.41#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.04:48:51.41#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.04:48:51.41#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.04:48:51.41$vck44/vblo=6,719.99 2006.145.04:48:51.41#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.04:48:51.41#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.04:48:51.41#ibcon#ireg 17 cls_cnt 0 2006.145.04:48:51.41#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.04:48:51.41#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.04:48:51.41#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.04:48:51.43#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.04:48:51.47#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.04:48:51.47#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.04:48:51.47#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.04:48:51.47#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.04:48:51.47$vck44/vb=6,4 2006.145.04:48:51.47#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.04:48:51.47#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.04:48:51.47#ibcon#ireg 11 cls_cnt 2 2006.145.04:48:51.47#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.04:48:51.53#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.04:48:51.53#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.04:48:51.55#ibcon#[27=AT06-04\r\n] 2006.145.04:48:51.58#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.04:48:51.58#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.04:48:51.58#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.04:48:51.58#ibcon#ireg 7 cls_cnt 0 2006.145.04:48:51.58#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.04:48:51.70#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.04:48:51.70#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.04:48:51.72#ibcon#[27=USB\r\n] 2006.145.04:48:51.75#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.04:48:51.75#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.04:48:51.75#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.04:48:51.75#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.04:48:51.75$vck44/vblo=7,734.99 2006.145.04:48:51.75#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.04:48:51.75#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.04:48:51.75#ibcon#ireg 17 cls_cnt 0 2006.145.04:48:51.75#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.04:48:51.75#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.04:48:51.75#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.04:48:51.77#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.04:48:51.81#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.04:48:51.81#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.04:48:51.81#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.04:48:51.81#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.04:48:51.81$vck44/vb=7,4 2006.145.04:48:51.81#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.04:48:51.81#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.04:48:51.81#ibcon#ireg 11 cls_cnt 2 2006.145.04:48:51.81#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.04:48:51.87#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.04:48:51.87#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.04:48:51.89#ibcon#[27=AT07-04\r\n] 2006.145.04:48:51.92#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.04:48:51.92#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.04:48:51.92#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.04:48:51.92#ibcon#ireg 7 cls_cnt 0 2006.145.04:48:51.92#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.04:48:52.04#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.04:48:52.04#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.04:48:52.06#ibcon#[27=USB\r\n] 2006.145.04:48:52.09#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.04:48:52.09#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.04:48:52.09#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.04:48:52.09#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.04:48:52.09$vck44/vblo=8,744.99 2006.145.04:48:52.09#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.04:48:52.09#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.04:48:52.09#ibcon#ireg 17 cls_cnt 0 2006.145.04:48:52.09#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.04:48:52.09#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.04:48:52.09#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.04:48:52.11#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.04:48:52.15#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.04:48:52.15#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.04:48:52.15#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.04:48:52.15#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.04:48:52.15$vck44/vb=8,4 2006.145.04:48:52.15#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.04:48:52.15#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.04:48:52.15#ibcon#ireg 11 cls_cnt 2 2006.145.04:48:52.15#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.04:48:52.21#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.04:48:52.21#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.04:48:52.23#ibcon#[27=AT08-04\r\n] 2006.145.04:48:52.26#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.04:48:52.26#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.04:48:52.26#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.04:48:52.26#ibcon#ireg 7 cls_cnt 0 2006.145.04:48:52.26#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.04:48:52.38#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.04:48:52.38#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.04:48:52.40#ibcon#[27=USB\r\n] 2006.145.04:48:52.43#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.04:48:52.43#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.04:48:52.43#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.04:48:52.43#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.04:48:52.43$vck44/vabw=wide 2006.145.04:48:52.43#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.04:48:52.43#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.04:48:52.43#ibcon#ireg 8 cls_cnt 0 2006.145.04:48:52.43#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.04:48:52.43#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.04:48:52.43#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.04:48:52.45#ibcon#[25=BW32\r\n] 2006.145.04:48:52.48#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.04:48:52.48#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.04:48:52.48#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.04:48:52.48#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.04:48:52.48$vck44/vbbw=wide 2006.145.04:48:52.48#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.04:48:52.48#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.04:48:52.48#ibcon#ireg 8 cls_cnt 0 2006.145.04:48:52.48#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.04:48:52.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.04:48:52.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.04:48:52.57#ibcon#[27=BW32\r\n] 2006.145.04:48:52.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.04:48:52.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.04:48:52.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.04:48:52.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.04:48:52.60$setupk4/ifdk4 2006.145.04:48:52.60$ifdk4/lo= 2006.145.04:48:52.60$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.04:48:52.60$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.04:48:52.60$ifdk4/patch= 2006.145.04:48:52.60$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.04:48:52.60$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.04:48:52.60$setupk4/!*+20s 2006.145.04:48:53.57#abcon#<5=/04 3.8 6.4 20.65 611016.6\r\n> 2006.145.04:48:53.59#abcon#{5=INTERFACE CLEAR} 2006.145.04:48:53.65#abcon#[5=S1D000X0/0*\r\n] 2006.145.04:49:03.74#abcon#<5=/04 3.8 6.4 20.65 621016.6\r\n> 2006.145.04:49:03.76#abcon#{5=INTERFACE CLEAR} 2006.145.04:49:03.82#abcon#[5=S1D000X0/0*\r\n] 2006.145.04:49:07.11$setupk4/"tpicd 2006.145.04:49:07.11$setupk4/echo=off 2006.145.04:49:07.11$setupk4/xlog=off 2006.145.04:49:07.11:!2006.145.04:51:20 2006.145.04:49:26.14#trakl#Source acquired 2006.145.04:49:28.14#flagr#flagr/antenna,acquired 2006.145.04:51:20.00:preob 2006.145.04:51:20.14/onsource/TRACKING 2006.145.04:51:20.14:!2006.145.04:51:30 2006.145.04:51:30.00:"tape 2006.145.04:51:30.00:"st=record 2006.145.04:51:30.00:data_valid=on 2006.145.04:51:30.00:midob 2006.145.04:51:31.14/onsource/TRACKING 2006.145.04:51:31.14/wx/20.65,1016.6,56 2006.145.04:51:31.25/cable/+6.5430E-03 2006.145.04:51:32.34/va/01,08,usb,yes,28,30 2006.145.04:51:32.34/va/02,07,usb,yes,30,30 2006.145.04:51:32.34/va/03,08,usb,yes,27,28 2006.145.04:51:32.34/va/04,07,usb,yes,31,33 2006.145.04:51:32.34/va/05,04,usb,yes,27,27 2006.145.04:51:32.34/va/06,04,usb,yes,30,30 2006.145.04:51:32.34/va/07,04,usb,yes,31,32 2006.145.04:51:32.34/va/08,04,usb,yes,26,31 2006.145.04:51:32.57/valo/01,524.99,yes,locked 2006.145.04:51:32.57/valo/02,534.99,yes,locked 2006.145.04:51:32.57/valo/03,564.99,yes,locked 2006.145.04:51:32.57/valo/04,624.99,yes,locked 2006.145.04:51:32.57/valo/05,734.99,yes,locked 2006.145.04:51:32.57/valo/06,814.99,yes,locked 2006.145.04:51:32.57/valo/07,864.99,yes,locked 2006.145.04:51:32.57/valo/08,884.99,yes,locked 2006.145.04:51:33.66/vb/01,03,usb,yes,36,33 2006.145.04:51:33.66/vb/02,04,usb,yes,31,31 2006.145.04:51:33.66/vb/03,04,usb,yes,28,31 2006.145.04:51:33.66/vb/04,04,usb,yes,33,32 2006.145.04:51:33.66/vb/05,04,usb,yes,25,28 2006.145.04:51:33.66/vb/06,04,usb,yes,30,26 2006.145.04:51:33.66/vb/07,04,usb,yes,29,29 2006.145.04:51:33.66/vb/08,04,usb,yes,27,30 2006.145.04:51:33.89/vblo/01,629.99,yes,locked 2006.145.04:51:33.89/vblo/02,634.99,yes,locked 2006.145.04:51:33.89/vblo/03,649.99,yes,locked 2006.145.04:51:33.89/vblo/04,679.99,yes,locked 2006.145.04:51:33.89/vblo/05,709.99,yes,locked 2006.145.04:51:33.89/vblo/06,719.99,yes,locked 2006.145.04:51:33.89/vblo/07,734.99,yes,locked 2006.145.04:51:33.89/vblo/08,744.99,yes,locked 2006.145.04:51:34.04/vabw/8 2006.145.04:51:34.19/vbbw/8 2006.145.04:51:34.33/xfe/off,on,14.7 2006.145.04:51:34.70/ifatt/23,28,28,28 2006.145.04:51:35.08/fmout-gps/S +5.1E-08 2006.145.04:51:35.12:!2006.145.04:52:20 2006.145.04:52:20.00:data_valid=off 2006.145.04:52:20.00:"et 2006.145.04:52:20.01:!+3s 2006.145.04:52:23.02:"tape 2006.145.04:52:23.02:postob 2006.145.04:52:23.18/cable/+6.5439E-03 2006.145.04:52:23.18/wx/20.66,1016.6,56 2006.145.04:52:24.07/fmout-gps/S +5.1E-08 2006.145.04:52:24.07:scan_name=145-0455,jd0605,280 2006.145.04:52:24.08:source=cta26,033930.94,-014635.8,2000.0,cw 2006.145.04:52:25.14#flagr#flagr/antenna,new-source 2006.145.04:52:25.14:checkk5 2006.145.04:52:25.64/chk_autoobs//k5ts1/ autoobs is running! 2006.145.04:52:26.23/chk_autoobs//k5ts2/ autoobs is running! 2006.145.04:52:26.96/chk_autoobs//k5ts3/ autoobs is running! 2006.145.04:52:27.43/chk_autoobs//k5ts4/ autoobs is running! 2006.145.04:52:27.88/chk_obsdata//k5ts1/T1450451??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.04:52:28.33/chk_obsdata//k5ts2/T1450451??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.04:52:29.06/chk_obsdata//k5ts3/T1450451??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.04:52:29.54/chk_obsdata//k5ts4/T1450451??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.04:52:30.51/k5log//k5ts1_log_newline 2006.145.04:52:31.33/k5log//k5ts2_log_newline 2006.145.04:52:32.33/k5log//k5ts3_log_newline 2006.145.04:52:33.24/k5log//k5ts4_log_newline 2006.145.04:52:33.27/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.04:52:33.27:setupk4=1 2006.145.04:52:33.27$setupk4/echo=on 2006.145.04:52:33.27$setupk4/pcalon 2006.145.04:52:33.27$pcalon/"no phase cal control is implemented here 2006.145.04:52:33.27$setupk4/"tpicd=stop 2006.145.04:52:33.27$setupk4/"rec=synch_on 2006.145.04:52:33.27$setupk4/"rec_mode=128 2006.145.04:52:33.27$setupk4/!* 2006.145.04:52:33.27$setupk4/recpk4 2006.145.04:52:33.27$recpk4/recpatch= 2006.145.04:52:33.28$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.04:52:33.28$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.04:52:33.28$setupk4/vck44 2006.145.04:52:33.28$vck44/valo=1,524.99 2006.145.04:52:33.28#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.04:52:33.28#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.04:52:33.28#ibcon#ireg 17 cls_cnt 0 2006.145.04:52:33.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:52:33.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:52:33.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:52:33.31#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.04:52:33.36#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:52:33.36#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:52:33.36#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.04:52:33.36#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.04:52:33.36$vck44/va=1,8 2006.145.04:52:33.36#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.04:52:33.36#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.04:52:33.36#ibcon#ireg 11 cls_cnt 2 2006.145.04:52:33.36#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.04:52:33.36#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.04:52:33.36#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.04:52:33.38#ibcon#[25=AT01-08\r\n] 2006.145.04:52:33.41#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.04:52:33.41#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.04:52:33.41#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.04:52:33.41#ibcon#ireg 7 cls_cnt 0 2006.145.04:52:33.41#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.04:52:33.53#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.04:52:33.53#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.04:52:33.55#ibcon#[25=USB\r\n] 2006.145.04:52:33.58#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.04:52:33.58#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.04:52:33.58#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.04:52:33.58#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.04:52:33.58$vck44/valo=2,534.99 2006.145.04:52:33.58#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.04:52:33.58#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.04:52:33.58#ibcon#ireg 17 cls_cnt 0 2006.145.04:52:33.58#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:52:33.58#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:52:33.58#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:52:33.60#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.04:52:33.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:52:33.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:52:33.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.04:52:33.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.04:52:33.64$vck44/va=2,7 2006.145.04:52:33.64#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.04:52:33.64#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.04:52:33.64#ibcon#ireg 11 cls_cnt 2 2006.145.04:52:33.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:52:33.70#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:52:33.70#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:52:33.72#ibcon#[25=AT02-07\r\n] 2006.145.04:52:33.76#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:52:33.76#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:52:33.76#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.04:52:33.76#ibcon#ireg 7 cls_cnt 0 2006.145.04:52:33.76#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:52:33.87#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:52:33.87#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:52:33.89#ibcon#[25=USB\r\n] 2006.145.04:52:33.92#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:52:33.92#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:52:33.92#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.04:52:33.92#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.04:52:33.92$vck44/valo=3,564.99 2006.145.04:52:33.92#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.04:52:33.92#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.04:52:33.92#ibcon#ireg 17 cls_cnt 0 2006.145.04:52:33.92#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:52:33.92#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:52:33.92#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:52:33.94#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.04:52:33.98#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:52:33.98#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:52:33.98#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.04:52:33.98#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.04:52:33.98$vck44/va=3,8 2006.145.04:52:33.98#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.04:52:33.98#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.04:52:33.98#ibcon#ireg 11 cls_cnt 2 2006.145.04:52:33.98#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:52:34.04#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:52:34.04#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:52:34.06#ibcon#[25=AT03-08\r\n] 2006.145.04:52:34.09#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:52:34.09#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:52:34.09#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.04:52:34.09#ibcon#ireg 7 cls_cnt 0 2006.145.04:52:34.09#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:52:34.21#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:52:34.21#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:52:34.23#ibcon#[25=USB\r\n] 2006.145.04:52:34.26#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:52:34.26#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:52:34.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.04:52:34.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.04:52:34.26$vck44/valo=4,624.99 2006.145.04:52:34.26#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.04:52:34.26#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.04:52:34.26#ibcon#ireg 17 cls_cnt 0 2006.145.04:52:34.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.04:52:34.26#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.04:52:34.26#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.04:52:34.28#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.04:52:34.32#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.04:52:34.32#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.04:52:34.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.04:52:34.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.04:52:34.32$vck44/va=4,7 2006.145.04:52:34.32#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.04:52:34.32#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.04:52:34.32#ibcon#ireg 11 cls_cnt 2 2006.145.04:52:34.32#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.04:52:34.38#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.04:52:34.38#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.04:52:34.40#ibcon#[25=AT04-07\r\n] 2006.145.04:52:34.43#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.04:52:34.43#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.04:52:34.43#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.04:52:34.43#ibcon#ireg 7 cls_cnt 0 2006.145.04:52:34.43#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.04:52:34.55#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.04:52:34.55#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.04:52:34.57#ibcon#[25=USB\r\n] 2006.145.04:52:34.60#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.04:52:34.60#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.04:52:34.60#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.04:52:34.60#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.04:52:34.60$vck44/valo=5,734.99 2006.145.04:52:34.60#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.04:52:34.60#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.04:52:34.60#ibcon#ireg 17 cls_cnt 0 2006.145.04:52:34.60#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.04:52:34.60#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.04:52:34.60#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.04:52:34.62#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.04:52:34.66#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.04:52:34.66#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.04:52:34.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.04:52:34.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.04:52:34.66$vck44/va=5,4 2006.145.04:52:34.66#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.04:52:34.66#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.04:52:34.66#ibcon#ireg 11 cls_cnt 2 2006.145.04:52:34.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.04:52:34.72#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.04:52:34.72#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.04:52:34.74#ibcon#[25=AT05-04\r\n] 2006.145.04:52:34.77#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.04:52:34.77#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.04:52:34.77#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.04:52:34.77#ibcon#ireg 7 cls_cnt 0 2006.145.04:52:34.77#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.04:52:34.89#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.04:52:34.89#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.04:52:34.91#ibcon#[25=USB\r\n] 2006.145.04:52:34.94#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.04:52:34.94#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.04:52:34.94#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.04:52:34.94#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.04:52:34.94$vck44/valo=6,814.99 2006.145.04:52:34.94#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.04:52:34.94#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.04:52:34.94#ibcon#ireg 17 cls_cnt 0 2006.145.04:52:34.94#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:52:34.94#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:52:34.94#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:52:34.96#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.04:52:35.00#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:52:35.00#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:52:35.00#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.04:52:35.00#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.04:52:35.00$vck44/va=6,4 2006.145.04:52:35.00#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.04:52:35.00#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.04:52:35.00#ibcon#ireg 11 cls_cnt 2 2006.145.04:52:35.00#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:52:35.07#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:52:35.07#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:52:35.09#ibcon#[25=AT06-04\r\n] 2006.145.04:52:35.12#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:52:35.12#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:52:35.12#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.04:52:35.12#ibcon#ireg 7 cls_cnt 0 2006.145.04:52:35.12#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:52:35.24#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:52:35.24#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:52:35.26#ibcon#[25=USB\r\n] 2006.145.04:52:35.29#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:52:35.29#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:52:35.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.04:52:35.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.04:52:35.29$vck44/valo=7,864.99 2006.145.04:52:35.29#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.04:52:35.29#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.04:52:35.29#ibcon#ireg 17 cls_cnt 0 2006.145.04:52:35.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:52:35.29#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:52:35.29#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:52:35.32#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.04:52:35.36#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:52:35.36#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:52:35.36#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.04:52:35.36#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.04:52:35.36$vck44/va=7,4 2006.145.04:52:35.36#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.04:52:35.36#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.04:52:35.36#ibcon#ireg 11 cls_cnt 2 2006.145.04:52:35.36#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:52:35.41#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:52:35.41#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:52:35.43#ibcon#[25=AT07-04\r\n] 2006.145.04:52:35.46#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:52:35.46#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:52:35.46#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.04:52:35.46#ibcon#ireg 7 cls_cnt 0 2006.145.04:52:35.46#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:52:35.58#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:52:35.58#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:52:35.60#ibcon#[25=USB\r\n] 2006.145.04:52:35.63#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:52:35.63#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:52:35.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.04:52:35.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.04:52:35.63$vck44/valo=8,884.99 2006.145.04:52:35.63#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.04:52:35.63#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.04:52:35.63#ibcon#ireg 17 cls_cnt 0 2006.145.04:52:35.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:52:35.63#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:52:35.63#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:52:35.65#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.04:52:35.69#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:52:35.69#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:52:35.69#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.04:52:35.69#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.04:52:35.69$vck44/va=8,4 2006.145.04:52:35.69#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.04:52:35.69#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.04:52:35.69#ibcon#ireg 11 cls_cnt 2 2006.145.04:52:35.69#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:52:35.75#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:52:35.75#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:52:35.77#ibcon#[25=AT08-04\r\n] 2006.145.04:52:35.80#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:52:35.80#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:52:35.80#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.04:52:35.80#ibcon#ireg 7 cls_cnt 0 2006.145.04:52:35.80#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:52:35.92#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:52:35.92#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:52:35.94#ibcon#[25=USB\r\n] 2006.145.04:52:35.97#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:52:35.97#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:52:35.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.04:52:35.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.04:52:35.97$vck44/vblo=1,629.99 2006.145.04:52:35.97#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.04:52:35.97#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.04:52:35.97#ibcon#ireg 17 cls_cnt 0 2006.145.04:52:35.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:52:35.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:52:35.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:52:35.99#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.04:52:36.03#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:52:36.03#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:52:36.03#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.04:52:36.03#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.04:52:36.03$vck44/vb=1,3 2006.145.04:52:36.03#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.04:52:36.03#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.04:52:36.03#ibcon#ireg 11 cls_cnt 2 2006.145.04:52:36.03#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.04:52:36.03#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.04:52:36.03#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.04:52:36.05#ibcon#[27=AT01-03\r\n] 2006.145.04:52:36.08#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.04:52:36.08#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.04:52:36.08#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.04:52:36.08#ibcon#ireg 7 cls_cnt 0 2006.145.04:52:36.08#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.04:52:36.20#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.04:52:36.20#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.04:52:36.22#ibcon#[27=USB\r\n] 2006.145.04:52:36.25#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.04:52:36.25#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.04:52:36.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.04:52:36.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.04:52:36.25$vck44/vblo=2,634.99 2006.145.04:52:36.25#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.04:52:36.25#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.04:52:36.25#ibcon#ireg 17 cls_cnt 0 2006.145.04:52:36.25#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:52:36.25#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:52:36.25#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:52:36.27#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.04:52:36.31#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:52:36.31#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.04:52:36.31#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.04:52:36.31#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.04:52:36.31$vck44/vb=2,4 2006.145.04:52:36.31#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.04:52:36.31#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.04:52:36.31#ibcon#ireg 11 cls_cnt 2 2006.145.04:52:36.31#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.04:52:36.37#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.04:52:36.37#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.04:52:36.39#ibcon#[27=AT02-04\r\n] 2006.145.04:52:36.42#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.04:52:36.42#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.04:52:36.42#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.04:52:36.42#ibcon#ireg 7 cls_cnt 0 2006.145.04:52:36.42#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.04:52:36.54#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.04:52:36.54#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.04:52:36.56#ibcon#[27=USB\r\n] 2006.145.04:52:36.59#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.04:52:36.59#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.04:52:36.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.04:52:36.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.04:52:36.59$vck44/vblo=3,649.99 2006.145.04:52:36.59#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.04:52:36.59#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.04:52:36.59#ibcon#ireg 17 cls_cnt 0 2006.145.04:52:36.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:52:36.59#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:52:36.59#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:52:36.61#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.04:52:36.65#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:52:36.65#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.04:52:36.65#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.04:52:36.65#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.04:52:36.65$vck44/vb=3,4 2006.145.04:52:36.65#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.04:52:36.65#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.04:52:36.65#ibcon#ireg 11 cls_cnt 2 2006.145.04:52:36.65#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:52:36.71#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:52:36.71#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:52:36.73#ibcon#[27=AT03-04\r\n] 2006.145.04:52:36.76#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:52:36.76#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.04:52:36.76#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.04:52:36.76#ibcon#ireg 7 cls_cnt 0 2006.145.04:52:36.76#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:52:36.88#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:52:36.88#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:52:36.90#ibcon#[27=USB\r\n] 2006.145.04:52:36.93#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:52:36.93#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.04:52:36.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.04:52:36.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.04:52:36.93$vck44/vblo=4,679.99 2006.145.04:52:36.93#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.04:52:36.93#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.04:52:36.93#ibcon#ireg 17 cls_cnt 0 2006.145.04:52:36.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:52:36.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:52:36.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:52:36.95#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.04:52:36.99#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:52:36.99#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.04:52:36.99#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.04:52:36.99#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.04:52:36.99$vck44/vb=4,4 2006.145.04:52:36.99#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.04:52:36.99#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.04:52:36.99#ibcon#ireg 11 cls_cnt 2 2006.145.04:52:36.99#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:52:37.05#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:52:37.05#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:52:37.07#ibcon#[27=AT04-04\r\n] 2006.145.04:52:37.10#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:52:37.10#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.04:52:37.10#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.04:52:37.10#ibcon#ireg 7 cls_cnt 0 2006.145.04:52:37.10#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:52:37.22#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:52:37.22#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:52:37.24#ibcon#[27=USB\r\n] 2006.145.04:52:37.27#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:52:37.27#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.04:52:37.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.04:52:37.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.04:52:37.27$vck44/vblo=5,709.99 2006.145.04:52:37.27#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.04:52:37.27#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.04:52:37.27#ibcon#ireg 17 cls_cnt 0 2006.145.04:52:37.27#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.04:52:37.27#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.04:52:37.27#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.04:52:37.29#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.04:52:37.31#abcon#<5=/05 3.7 6.4 20.66 581016.6\r\n> 2006.145.04:52:37.33#abcon#{5=INTERFACE CLEAR} 2006.145.04:52:37.33#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.04:52:37.33#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.04:52:37.33#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.04:52:37.33#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.04:52:37.33$vck44/vb=5,4 2006.145.04:52:37.33#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.04:52:37.33#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.04:52:37.33#ibcon#ireg 11 cls_cnt 2 2006.145.04:52:37.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.04:52:37.39#abcon#[5=S1D000X0/0*\r\n] 2006.145.04:52:37.39#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.04:52:37.39#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.04:52:37.41#ibcon#[27=AT05-04\r\n] 2006.145.04:52:37.44#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.04:52:37.44#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.04:52:37.44#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.04:52:37.44#ibcon#ireg 7 cls_cnt 0 2006.145.04:52:37.44#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.04:52:37.56#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.04:52:37.56#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.04:52:37.58#ibcon#[27=USB\r\n] 2006.145.04:52:37.61#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.04:52:37.61#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.04:52:37.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.04:52:37.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.04:52:37.61$vck44/vblo=6,719.99 2006.145.04:52:37.61#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.04:52:37.61#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.04:52:37.61#ibcon#ireg 17 cls_cnt 0 2006.145.04:52:37.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:52:37.61#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:52:37.61#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:52:37.63#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.04:52:37.67#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:52:37.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.04:52:37.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.04:52:37.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.04:52:37.67$vck44/vb=6,4 2006.145.04:52:37.67#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.04:52:37.67#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.04:52:37.67#ibcon#ireg 11 cls_cnt 2 2006.145.04:52:37.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:52:37.73#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:52:37.73#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:52:37.75#ibcon#[27=AT06-04\r\n] 2006.145.04:52:37.78#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:52:37.78#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.04:52:37.78#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.04:52:37.78#ibcon#ireg 7 cls_cnt 0 2006.145.04:52:37.78#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:52:37.90#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:52:37.90#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:52:37.92#ibcon#[27=USB\r\n] 2006.145.04:52:37.95#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:52:37.95#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.04:52:37.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.04:52:37.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.04:52:37.95$vck44/vblo=7,734.99 2006.145.04:52:37.95#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.04:52:37.95#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.04:52:37.95#ibcon#ireg 17 cls_cnt 0 2006.145.04:52:37.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:52:37.95#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:52:37.95#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:52:37.97#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.04:52:38.01#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:52:38.01#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.04:52:38.01#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.04:52:38.01#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.04:52:38.01$vck44/vb=7,4 2006.145.04:52:38.01#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.04:52:38.01#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.04:52:38.01#ibcon#ireg 11 cls_cnt 2 2006.145.04:52:38.01#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:52:38.07#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:52:38.07#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:52:38.09#ibcon#[27=AT07-04\r\n] 2006.145.04:52:38.12#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:52:38.12#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.04:52:38.12#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.04:52:38.12#ibcon#ireg 7 cls_cnt 0 2006.145.04:52:38.12#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:52:38.24#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:52:38.24#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:52:38.26#ibcon#[27=USB\r\n] 2006.145.04:52:38.29#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:52:38.29#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.04:52:38.29#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.04:52:38.29#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.04:52:38.29$vck44/vblo=8,744.99 2006.145.04:52:38.29#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.04:52:38.29#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.04:52:38.29#ibcon#ireg 17 cls_cnt 0 2006.145.04:52:38.29#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:52:38.29#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:52:38.29#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:52:38.31#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.04:52:38.35#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:52:38.35#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.04:52:38.35#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.04:52:38.35#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.04:52:38.35$vck44/vb=8,4 2006.145.04:52:38.35#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.04:52:38.35#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.04:52:38.35#ibcon#ireg 11 cls_cnt 2 2006.145.04:52:38.35#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:52:38.41#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:52:38.41#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:52:38.43#ibcon#[27=AT08-04\r\n] 2006.145.04:52:38.46#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:52:38.46#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.04:52:38.46#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.04:52:38.46#ibcon#ireg 7 cls_cnt 0 2006.145.04:52:38.46#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:52:38.58#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:52:38.58#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:52:38.60#ibcon#[27=USB\r\n] 2006.145.04:52:38.63#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:52:38.63#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.04:52:38.63#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.04:52:38.63#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.04:52:38.63$vck44/vabw=wide 2006.145.04:52:38.63#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.04:52:38.63#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.04:52:38.63#ibcon#ireg 8 cls_cnt 0 2006.145.04:52:38.63#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:52:38.63#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:52:38.63#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:52:38.65#ibcon#[25=BW32\r\n] 2006.145.04:52:38.68#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:52:38.68#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.04:52:38.68#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.04:52:38.68#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.04:52:38.68$vck44/vbbw=wide 2006.145.04:52:38.68#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.04:52:38.68#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.04:52:38.68#ibcon#ireg 8 cls_cnt 0 2006.145.04:52:38.68#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.04:52:38.75#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.04:52:38.75#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.04:52:38.77#ibcon#[27=BW32\r\n] 2006.145.04:52:38.80#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.04:52:38.80#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.04:52:38.80#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.04:52:38.80#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.04:52:38.80$setupk4/ifdk4 2006.145.04:52:38.80$ifdk4/lo= 2006.145.04:52:38.80$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.04:52:38.80$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.04:52:38.80$ifdk4/patch= 2006.145.04:52:38.80$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.04:52:38.80$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.04:52:38.80$setupk4/!*+20s 2006.145.04:52:47.48#abcon#<5=/05 3.6 6.4 20.66 591016.6\r\n> 2006.145.04:52:47.50#abcon#{5=INTERFACE CLEAR} 2006.145.04:52:47.56#abcon#[5=S1D000X0/0*\r\n] 2006.145.04:52:53.28$setupk4/"tpicd 2006.145.04:52:53.28$setupk4/echo=off 2006.145.04:52:53.28$setupk4/xlog=off 2006.145.04:52:53.28:!2006.145.04:54:58 2006.145.04:52:57.14#trakl#Source acquired 2006.145.04:52:57.14#flagr#flagr/antenna,acquired 2006.145.04:54:58.00:preob 2006.145.04:54:58.13/onsource/TRACKING 2006.145.04:54:58.13:!2006.145.04:55:08 2006.145.04:55:08.00:"tape 2006.145.04:55:08.00:"st=record 2006.145.04:55:08.00:data_valid=on 2006.145.04:55:08.00:midob 2006.145.04:55:09.13/onsource/TRACKING 2006.145.04:55:09.13/wx/20.69,1016.6,58 2006.145.04:55:09.36/cable/+6.5417E-03 2006.145.04:55:10.45/va/01,08,usb,yes,28,30 2006.145.04:55:10.45/va/02,07,usb,yes,30,31 2006.145.04:55:10.45/va/03,08,usb,yes,28,29 2006.145.04:55:10.45/va/04,07,usb,yes,31,33 2006.145.04:55:10.45/va/05,04,usb,yes,27,28 2006.145.04:55:10.45/va/06,04,usb,yes,31,30 2006.145.04:55:10.45/va/07,04,usb,yes,31,32 2006.145.04:55:10.45/va/08,04,usb,yes,26,32 2006.145.04:55:10.68/valo/01,524.99,yes,locked 2006.145.04:55:10.68/valo/02,534.99,yes,locked 2006.145.04:55:10.68/valo/03,564.99,yes,locked 2006.145.04:55:10.68/valo/04,624.99,yes,locked 2006.145.04:55:10.68/valo/05,734.99,yes,locked 2006.145.04:55:10.68/valo/06,814.99,yes,locked 2006.145.04:55:10.68/valo/07,864.99,yes,locked 2006.145.04:55:10.68/valo/08,884.99,yes,locked 2006.145.04:55:11.77/vb/01,03,usb,yes,38,34 2006.145.04:55:11.77/vb/02,04,usb,yes,31,33 2006.145.04:55:11.77/vb/03,04,usb,yes,28,32 2006.145.04:55:11.77/vb/04,04,usb,yes,32,31 2006.145.04:55:11.77/vb/05,04,usb,yes,25,27 2006.145.04:55:11.77/vb/06,04,usb,yes,29,26 2006.145.04:55:11.77/vb/07,04,usb,yes,29,29 2006.145.04:55:11.77/vb/08,04,usb,yes,27,30 2006.145.04:55:12.01/vblo/01,629.99,yes,locked 2006.145.04:55:12.01/vblo/02,634.99,yes,locked 2006.145.04:55:12.01/vblo/03,649.99,yes,locked 2006.145.04:55:12.01/vblo/04,679.99,yes,locked 2006.145.04:55:12.01/vblo/05,709.99,yes,locked 2006.145.04:55:12.01/vblo/06,719.99,yes,locked 2006.145.04:55:12.01/vblo/07,734.99,yes,locked 2006.145.04:55:12.01/vblo/08,744.99,yes,locked 2006.145.04:55:12.16/vabw/8 2006.145.04:55:12.31/vbbw/8 2006.145.04:55:12.49/xfe/off,on,14.0 2006.145.04:55:12.87/ifatt/23,28,28,28 2006.145.04:55:13.07/fmout-gps/S +5.1E-08 2006.145.04:55:13.11:!2006.145.04:59:48 2006.145.04:59:48.00:data_valid=off 2006.145.04:59:48.00:"et 2006.145.04:59:48.00:!+3s 2006.145.04:59:51.02:"tape 2006.145.04:59:51.02:postob 2006.145.04:59:51.13/cable/+6.5428E-03 2006.145.04:59:51.13/wx/20.78,1016.5,60 2006.145.04:59:52.08/fmout-gps/S +5.1E-08 2006.145.04:59:52.08:scan_name=145-0508,jd0605,60 2006.145.04:59:52.08:source=0727-115,073019.11,-114112.6,2000.0,cw 2006.145.04:59:53.14#flagr#flagr/antenna,new-source 2006.145.04:59:53.14:checkk5 2006.145.04:59:53.61/chk_autoobs//k5ts1/ autoobs is running! 2006.145.04:59:54.08/chk_autoobs//k5ts2/ autoobs is running! 2006.145.04:59:54.53/chk_autoobs//k5ts3/ autoobs is running! 2006.145.04:59:54.97/chk_autoobs//k5ts4/ autoobs is running! 2006.145.04:59:55.48/chk_obsdata//k5ts1/T1450455??a.dat file size is correct (nominal:1120MB, actual:1120MB). 2006.145.04:59:55.95/chk_obsdata//k5ts2/T1450455??b.dat file size is correct (nominal:1120MB, actual:1120MB). 2006.145.04:59:56.41/chk_obsdata//k5ts3/T1450455??c.dat file size is correct (nominal:1120MB, actual:1120MB). 2006.145.04:59:56.87/chk_obsdata//k5ts4/T1450455??d.dat file size is correct (nominal:1120MB, actual:1120MB). 2006.145.04:59:57.75/k5log//k5ts1_log_newline 2006.145.05:00:03.59/k5log//k5ts2_log_newline 2006.145.05:00:04.44/k5log//k5ts3_log_newline 2006.145.05:00:05.35/k5log//k5ts4_log_newline 2006.145.05:00:05.37/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.05:00:05.37:setupk4=1 2006.145.05:00:05.37$setupk4/echo=on 2006.145.05:00:05.37$setupk4/pcalon 2006.145.05:00:05.37$pcalon/"no phase cal control is implemented here 2006.145.05:00:05.37$setupk4/"tpicd=stop 2006.145.05:00:05.37$setupk4/"rec=synch_on 2006.145.05:00:05.37$setupk4/"rec_mode=128 2006.145.05:00:05.37$setupk4/!* 2006.145.05:00:05.37$setupk4/recpk4 2006.145.05:00:05.37$recpk4/recpatch= 2006.145.05:00:05.38$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.05:00:05.38$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.05:00:05.38$setupk4/vck44 2006.145.05:00:05.38$vck44/valo=1,524.99 2006.145.05:00:05.38#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.05:00:05.38#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.05:00:05.38#ibcon#ireg 17 cls_cnt 0 2006.145.05:00:05.38#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.05:00:05.38#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.05:00:05.38#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.05:00:05.42#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.05:00:05.47#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.05:00:05.47#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.05:00:05.47#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.05:00:05.47#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.05:00:05.47$vck44/va=1,8 2006.145.05:00:05.47#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.05:00:05.47#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.05:00:05.47#ibcon#ireg 11 cls_cnt 2 2006.145.05:00:05.47#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.05:00:05.47#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.05:00:05.47#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.05:00:05.49#ibcon#[25=AT01-08\r\n] 2006.145.05:00:05.52#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.05:00:05.52#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.05:00:05.52#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.05:00:05.52#ibcon#ireg 7 cls_cnt 0 2006.145.05:00:05.52#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.05:00:05.64#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.05:00:05.64#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.05:00:05.66#ibcon#[25=USB\r\n] 2006.145.05:00:05.70#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.05:00:05.70#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.05:00:05.70#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.05:00:05.70#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.05:00:05.71$vck44/valo=2,534.99 2006.145.05:00:05.71#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.05:00:05.71#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.05:00:05.71#ibcon#ireg 17 cls_cnt 0 2006.145.05:00:05.71#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.05:00:05.71#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.05:00:05.71#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.05:00:05.72#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.05:00:05.76#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.05:00:05.76#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.05:00:05.76#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.05:00:05.76#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.05:00:05.76$vck44/va=2,7 2006.145.05:00:05.76#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.05:00:05.76#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.05:00:05.76#ibcon#ireg 11 cls_cnt 2 2006.145.05:00:05.76#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.05:00:05.82#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.05:00:05.82#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.05:00:05.84#ibcon#[25=AT02-07\r\n] 2006.145.05:00:05.87#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.05:00:05.87#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.05:00:05.87#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.05:00:05.87#ibcon#ireg 7 cls_cnt 0 2006.145.05:00:05.87#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.05:00:05.99#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.05:00:05.99#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.05:00:06.01#ibcon#[25=USB\r\n] 2006.145.05:00:06.04#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.05:00:06.04#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.05:00:06.04#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.05:00:06.04#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.05:00:06.04$vck44/valo=3,564.99 2006.145.05:00:06.04#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.05:00:06.04#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.05:00:06.04#ibcon#ireg 17 cls_cnt 0 2006.145.05:00:06.04#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.05:00:06.04#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.05:00:06.04#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.05:00:06.06#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.05:00:06.10#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.05:00:06.10#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.05:00:06.10#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.05:00:06.10#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.05:00:06.10$vck44/va=3,8 2006.145.05:00:06.10#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.05:00:06.10#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.05:00:06.10#ibcon#ireg 11 cls_cnt 2 2006.145.05:00:06.10#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.05:00:06.16#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.05:00:06.16#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.05:00:06.18#ibcon#[25=AT03-08\r\n] 2006.145.05:00:06.21#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.05:00:06.21#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.05:00:06.21#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.05:00:06.21#ibcon#ireg 7 cls_cnt 0 2006.145.05:00:06.21#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.05:00:06.33#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.05:00:06.33#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.05:00:06.35#ibcon#[25=USB\r\n] 2006.145.05:00:06.38#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.05:00:06.38#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.05:00:06.38#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.05:00:06.38#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.05:00:06.38$vck44/valo=4,624.99 2006.145.05:00:06.38#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.05:00:06.38#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.05:00:06.38#ibcon#ireg 17 cls_cnt 0 2006.145.05:00:06.38#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.05:00:06.38#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.05:00:06.38#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.05:00:06.40#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.05:00:06.44#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.05:00:06.44#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.05:00:06.44#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.05:00:06.44#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.05:00:06.44$vck44/va=4,7 2006.145.05:00:06.44#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.05:00:06.44#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.05:00:06.44#ibcon#ireg 11 cls_cnt 2 2006.145.05:00:06.44#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.05:00:06.50#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.05:00:06.50#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.05:00:06.52#ibcon#[25=AT04-07\r\n] 2006.145.05:00:06.55#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.05:00:06.55#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.05:00:06.55#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.05:00:06.55#ibcon#ireg 7 cls_cnt 0 2006.145.05:00:06.55#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.05:00:06.67#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.05:00:06.67#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.05:00:06.69#ibcon#[25=USB\r\n] 2006.145.05:00:06.72#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.05:00:06.72#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.05:00:06.72#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.05:00:06.72#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.05:00:06.72$vck44/valo=5,734.99 2006.145.05:00:06.72#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.05:00:06.72#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.05:00:06.72#ibcon#ireg 17 cls_cnt 0 2006.145.05:00:06.72#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.05:00:06.72#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.05:00:06.72#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.05:00:06.74#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.05:00:06.78#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.05:00:06.78#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.05:00:06.78#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.05:00:06.78#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.05:00:06.78$vck44/va=5,4 2006.145.05:00:06.78#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.05:00:06.78#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.05:00:06.78#ibcon#ireg 11 cls_cnt 2 2006.145.05:00:06.78#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.05:00:06.84#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.05:00:06.84#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.05:00:06.86#ibcon#[25=AT05-04\r\n] 2006.145.05:00:06.89#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.05:00:06.89#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.05:00:06.89#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.05:00:06.89#ibcon#ireg 7 cls_cnt 0 2006.145.05:00:06.89#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.05:00:07.01#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.05:00:07.01#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.05:00:07.03#ibcon#[25=USB\r\n] 2006.145.05:00:07.06#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.05:00:07.06#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.05:00:07.06#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.05:00:07.06#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.05:00:07.06$vck44/valo=6,814.99 2006.145.05:00:07.06#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.05:00:07.06#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.05:00:07.06#ibcon#ireg 17 cls_cnt 0 2006.145.05:00:07.06#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.05:00:07.06#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.05:00:07.06#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.05:00:07.08#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.05:00:07.12#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.05:00:07.12#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.05:00:07.12#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.05:00:07.12#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.05:00:07.12$vck44/va=6,4 2006.145.05:00:07.12#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.05:00:07.12#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.05:00:07.12#ibcon#ireg 11 cls_cnt 2 2006.145.05:00:07.12#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.05:00:07.18#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.05:00:07.18#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.05:00:07.20#ibcon#[25=AT06-04\r\n] 2006.145.05:00:07.23#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.05:00:07.23#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.05:00:07.23#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.05:00:07.23#ibcon#ireg 7 cls_cnt 0 2006.145.05:00:07.23#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.05:00:07.35#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.05:00:07.35#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.05:00:07.37#ibcon#[25=USB\r\n] 2006.145.05:00:07.41#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.05:00:07.41#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.05:00:07.41#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.05:00:07.41#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.05:00:07.41$vck44/valo=7,864.99 2006.145.05:00:07.41#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.05:00:07.41#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.05:00:07.41#ibcon#ireg 17 cls_cnt 0 2006.145.05:00:07.41#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.05:00:07.41#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.05:00:07.41#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.05:00:07.43#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.05:00:07.47#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.05:00:07.47#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.05:00:07.47#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.05:00:07.47#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.05:00:07.47$vck44/va=7,4 2006.145.05:00:07.47#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.05:00:07.47#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.05:00:07.47#ibcon#ireg 11 cls_cnt 2 2006.145.05:00:07.47#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.05:00:07.53#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.05:00:07.53#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.05:00:07.55#ibcon#[25=AT07-04\r\n] 2006.145.05:00:07.59#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.05:00:07.59#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.05:00:07.59#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.05:00:07.59#ibcon#ireg 7 cls_cnt 0 2006.145.05:00:07.59#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.05:00:07.70#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.05:00:07.70#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.05:00:07.72#ibcon#[25=USB\r\n] 2006.145.05:00:07.75#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.05:00:07.75#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.05:00:07.75#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.05:00:07.75#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.05:00:07.75$vck44/valo=8,884.99 2006.145.05:00:07.75#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.05:00:07.75#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.05:00:07.75#ibcon#ireg 17 cls_cnt 0 2006.145.05:00:07.75#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.05:00:07.75#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.05:00:07.75#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.05:00:07.77#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.05:00:07.81#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.05:00:07.81#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.05:00:07.81#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.05:00:07.81#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.05:00:07.81$vck44/va=8,4 2006.145.05:00:07.81#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.05:00:07.81#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.05:00:07.81#ibcon#ireg 11 cls_cnt 2 2006.145.05:00:07.81#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.05:00:07.87#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.05:00:07.87#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.05:00:07.89#ibcon#[25=AT08-04\r\n] 2006.145.05:00:07.92#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.05:00:07.92#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.05:00:07.92#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.05:00:07.92#ibcon#ireg 7 cls_cnt 0 2006.145.05:00:07.92#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.05:00:08.04#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.05:00:08.04#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.05:00:08.06#ibcon#[25=USB\r\n] 2006.145.05:00:08.09#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.05:00:08.09#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.05:00:08.09#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.05:00:08.09#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.05:00:08.09$vck44/vblo=1,629.99 2006.145.05:00:08.09#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.05:00:08.09#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.05:00:08.09#ibcon#ireg 17 cls_cnt 0 2006.145.05:00:08.09#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.05:00:08.09#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.05:00:08.09#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.05:00:08.11#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.05:00:08.15#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.05:00:08.15#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.05:00:08.15#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.05:00:08.15#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.05:00:08.15$vck44/vb=1,3 2006.145.05:00:08.15#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.05:00:08.15#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.05:00:08.15#ibcon#ireg 11 cls_cnt 2 2006.145.05:00:08.15#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.05:00:08.15#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.05:00:08.15#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.05:00:08.17#ibcon#[27=AT01-03\r\n] 2006.145.05:00:08.20#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.05:00:08.20#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.05:00:08.20#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.05:00:08.20#ibcon#ireg 7 cls_cnt 0 2006.145.05:00:08.20#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.05:00:08.32#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.05:00:08.32#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.05:00:08.34#ibcon#[27=USB\r\n] 2006.145.05:00:08.37#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.05:00:08.37#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.05:00:08.37#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.05:00:08.37#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.05:00:08.37$vck44/vblo=2,634.99 2006.145.05:00:08.37#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.05:00:08.37#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.05:00:08.37#ibcon#ireg 17 cls_cnt 0 2006.145.05:00:08.37#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.05:00:08.37#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.05:00:08.37#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.05:00:08.39#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.05:00:08.43#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.05:00:08.43#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.05:00:08.43#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.05:00:08.43#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.05:00:08.43$vck44/vb=2,4 2006.145.05:00:08.43#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.05:00:08.43#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.05:00:08.43#ibcon#ireg 11 cls_cnt 2 2006.145.05:00:08.43#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.05:00:08.49#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.05:00:08.49#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.05:00:08.51#ibcon#[27=AT02-04\r\n] 2006.145.05:00:08.54#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.05:00:08.54#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.05:00:08.54#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.05:00:08.54#ibcon#ireg 7 cls_cnt 0 2006.145.05:00:08.54#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.05:00:08.66#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.05:00:08.66#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.05:00:08.68#ibcon#[27=USB\r\n] 2006.145.05:00:08.71#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.05:00:08.71#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.05:00:08.71#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.05:00:08.71#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.05:00:08.71$vck44/vblo=3,649.99 2006.145.05:00:08.71#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.05:00:08.71#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.05:00:08.71#ibcon#ireg 17 cls_cnt 0 2006.145.05:00:08.71#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.05:00:08.71#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.05:00:08.71#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.05:00:08.73#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.05:00:08.77#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.05:00:08.77#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.05:00:08.77#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.05:00:08.77#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.05:00:08.77$vck44/vb=3,4 2006.145.05:00:08.77#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.05:00:08.77#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.05:00:08.77#ibcon#ireg 11 cls_cnt 2 2006.145.05:00:08.77#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.05:00:08.83#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.05:00:08.83#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.05:00:08.85#ibcon#[27=AT03-04\r\n] 2006.145.05:00:08.88#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.05:00:08.88#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.05:00:08.88#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.05:00:08.88#ibcon#ireg 7 cls_cnt 0 2006.145.05:00:08.88#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.05:00:09.00#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.05:00:09.00#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.05:00:09.02#ibcon#[27=USB\r\n] 2006.145.05:00:09.05#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.05:00:09.05#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.05:00:09.05#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.05:00:09.05#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.05:00:09.05$vck44/vblo=4,679.99 2006.145.05:00:09.05#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.05:00:09.05#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.05:00:09.05#ibcon#ireg 17 cls_cnt 0 2006.145.05:00:09.05#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.05:00:09.05#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.05:00:09.05#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.05:00:09.07#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.05:00:09.11#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.05:00:09.11#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.05:00:09.11#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.05:00:09.11#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.05:00:09.11$vck44/vb=4,4 2006.145.05:00:09.11#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.05:00:09.11#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.05:00:09.11#ibcon#ireg 11 cls_cnt 2 2006.145.05:00:09.11#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.05:00:09.17#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.05:00:09.17#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.05:00:09.19#ibcon#[27=AT04-04\r\n] 2006.145.05:00:09.22#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.05:00:09.22#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.05:00:09.22#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.05:00:09.22#ibcon#ireg 7 cls_cnt 0 2006.145.05:00:09.22#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.05:00:09.34#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.05:00:09.34#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.05:00:09.36#ibcon#[27=USB\r\n] 2006.145.05:00:09.39#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.05:00:09.39#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.05:00:09.39#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.05:00:09.39#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.05:00:09.39$vck44/vblo=5,709.99 2006.145.05:00:09.39#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.05:00:09.39#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.05:00:09.39#ibcon#ireg 17 cls_cnt 0 2006.145.05:00:09.39#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.05:00:09.39#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.05:00:09.39#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.05:00:09.41#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.05:00:09.45#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.05:00:09.45#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.05:00:09.45#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.05:00:09.45#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.05:00:09.45$vck44/vb=5,4 2006.145.05:00:09.45#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.05:00:09.45#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.05:00:09.45#ibcon#ireg 11 cls_cnt 2 2006.145.05:00:09.45#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.05:00:09.51#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.05:00:09.51#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.05:00:09.53#ibcon#[27=AT05-04\r\n] 2006.145.05:00:09.56#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.05:00:09.56#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.05:00:09.56#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.05:00:09.56#ibcon#ireg 7 cls_cnt 0 2006.145.05:00:09.56#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.05:00:09.68#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.05:00:09.68#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.05:00:09.70#ibcon#[27=USB\r\n] 2006.145.05:00:09.73#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.05:00:09.73#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.05:00:09.73#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.05:00:09.73#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.05:00:09.73$vck44/vblo=6,719.99 2006.145.05:00:09.73#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.05:00:09.73#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.05:00:09.73#ibcon#ireg 17 cls_cnt 0 2006.145.05:00:09.73#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.05:00:09.73#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.05:00:09.73#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.05:00:09.75#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.05:00:09.79#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.05:00:09.79#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.05:00:09.79#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.05:00:09.79#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.05:00:09.79$vck44/vb=6,4 2006.145.05:00:09.79#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.05:00:09.79#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.05:00:09.79#ibcon#ireg 11 cls_cnt 2 2006.145.05:00:09.79#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.05:00:09.85#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.05:00:09.85#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.05:00:09.87#ibcon#[27=AT06-04\r\n] 2006.145.05:00:09.90#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.05:00:09.90#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.05:00:09.90#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.05:00:09.90#ibcon#ireg 7 cls_cnt 0 2006.145.05:00:09.90#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.05:00:10.02#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.05:00:10.02#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.05:00:10.04#ibcon#[27=USB\r\n] 2006.145.05:00:10.07#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.05:00:10.07#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.05:00:10.07#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.05:00:10.07#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.05:00:10.07$vck44/vblo=7,734.99 2006.145.05:00:10.07#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.05:00:10.07#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.05:00:10.07#ibcon#ireg 17 cls_cnt 0 2006.145.05:00:10.07#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.05:00:10.07#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.05:00:10.07#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.05:00:10.09#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.05:00:10.13#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.05:00:10.13#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.05:00:10.13#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.05:00:10.13#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.05:00:10.13$vck44/vb=7,4 2006.145.05:00:10.13#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.05:00:10.13#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.05:00:10.13#ibcon#ireg 11 cls_cnt 2 2006.145.05:00:10.13#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.05:00:10.19#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.05:00:10.19#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.05:00:10.21#ibcon#[27=AT07-04\r\n] 2006.145.05:00:10.24#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.05:00:10.24#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.05:00:10.24#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.05:00:10.24#ibcon#ireg 7 cls_cnt 0 2006.145.05:00:10.24#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.05:00:10.36#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.05:00:10.36#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.05:00:10.38#ibcon#[27=USB\r\n] 2006.145.05:00:10.41#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.05:00:10.41#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.05:00:10.41#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.05:00:10.41#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.05:00:10.41$vck44/vblo=8,744.99 2006.145.05:00:10.41#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.05:00:10.41#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.05:00:10.41#ibcon#ireg 17 cls_cnt 0 2006.145.05:00:10.41#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.05:00:10.41#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.05:00:10.41#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.05:00:10.43#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.05:00:10.47#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.05:00:10.47#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.05:00:10.47#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.05:00:10.47#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.05:00:10.47$vck44/vb=8,4 2006.145.05:00:10.47#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.05:00:10.47#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.05:00:10.47#ibcon#ireg 11 cls_cnt 2 2006.145.05:00:10.47#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.05:00:10.53#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.05:00:10.53#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.05:00:10.55#ibcon#[27=AT08-04\r\n] 2006.145.05:00:10.58#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.05:00:10.58#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.05:00:10.58#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.05:00:10.58#ibcon#ireg 7 cls_cnt 0 2006.145.05:00:10.58#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.05:00:10.70#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.05:00:10.70#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.05:00:10.72#ibcon#[27=USB\r\n] 2006.145.05:00:10.75#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.05:00:10.75#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.05:00:10.75#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.05:00:10.75#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.05:00:10.75$vck44/vabw=wide 2006.145.05:00:10.75#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.05:00:10.75#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.05:00:10.75#ibcon#ireg 8 cls_cnt 0 2006.145.05:00:10.75#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.05:00:10.75#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.05:00:10.75#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.05:00:10.77#ibcon#[25=BW32\r\n] 2006.145.05:00:10.80#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.05:00:10.80#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.05:00:10.80#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.05:00:10.80#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.05:00:10.80$vck44/vbbw=wide 2006.145.05:00:10.80#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.05:00:10.80#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.05:00:10.80#ibcon#ireg 8 cls_cnt 0 2006.145.05:00:10.80#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:00:10.87#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:00:10.87#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:00:10.89#ibcon#[27=BW32\r\n] 2006.145.05:00:10.92#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:00:10.92#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:00:10.92#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.05:00:10.92#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.05:00:10.92$setupk4/ifdk4 2006.145.05:00:10.92$ifdk4/lo= 2006.145.05:00:10.92$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.05:00:10.92$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.05:00:10.92$ifdk4/patch= 2006.145.05:00:10.92$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.05:00:10.92$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.05:00:10.92$setupk4/!*+20s 2006.145.05:00:15.28#abcon#<5=/06 3.7 6.2 20.79 561016.5\r\n> 2006.145.05:00:15.30#abcon#{5=INTERFACE CLEAR} 2006.145.05:00:15.36#abcon#[5=S1D000X0/0*\r\n] 2006.145.05:00:25.38$setupk4/"tpicd 2006.145.05:00:25.38$setupk4/echo=off 2006.145.05:00:25.38$setupk4/xlog=off 2006.145.05:00:25.38:!2006.145.05:08:40 2006.145.05:00:26.14#trakl#Source acquired 2006.145.05:00:27.14#flagr#flagr/antenna,acquired 2006.145.05:08:40.00:preob 2006.145.05:08:40.14/onsource/TRACKING 2006.145.05:08:40.15:!2006.145.05:08:50 2006.145.05:08:50.01:"tape 2006.145.05:08:50.01:"st=record 2006.145.05:08:50.01:data_valid=on 2006.145.05:08:50.02:midob 2006.145.05:08:51.14/onsource/TRACKING 2006.145.05:08:51.15/wx/20.97,1016.4,58 2006.145.05:08:51.28/cable/+6.5409E-03 2006.145.05:08:52.37/va/01,08,usb,yes,29,31 2006.145.05:08:52.37/va/02,07,usb,yes,31,31 2006.145.05:08:52.37/va/03,08,usb,yes,28,29 2006.145.05:08:52.37/va/04,07,usb,yes,31,33 2006.145.05:08:52.37/va/05,04,usb,yes,27,28 2006.145.05:08:52.37/va/06,04,usb,yes,31,31 2006.145.05:08:52.37/va/07,04,usb,yes,31,32 2006.145.05:08:52.37/va/08,04,usb,yes,27,32 2006.145.05:08:52.60/valo/01,524.99,yes,locked 2006.145.05:08:52.60/valo/02,534.99,yes,locked 2006.145.05:08:52.60/valo/03,564.99,yes,locked 2006.145.05:08:52.60/valo/04,624.99,yes,locked 2006.145.05:08:52.60/valo/05,734.99,yes,locked 2006.145.05:08:52.60/valo/06,814.99,yes,locked 2006.145.05:08:52.60/valo/07,864.99,yes,locked 2006.145.05:08:52.60/valo/08,884.99,yes,locked 2006.145.05:08:53.69/vb/01,03,usb,yes,36,33 2006.145.05:08:53.69/vb/02,04,usb,yes,31,31 2006.145.05:08:53.69/vb/03,04,usb,yes,28,31 2006.145.05:08:53.69/vb/04,04,usb,yes,33,32 2006.145.05:08:53.69/vb/05,04,usb,yes,25,28 2006.145.05:08:53.69/vb/06,04,usb,yes,30,26 2006.145.05:08:53.69/vb/07,04,usb,yes,29,29 2006.145.05:08:53.69/vb/08,04,usb,yes,27,30 2006.145.05:08:53.92/vblo/01,629.99,yes,locked 2006.145.05:08:53.92/vblo/02,634.99,yes,locked 2006.145.05:08:53.92/vblo/03,649.99,yes,locked 2006.145.05:08:53.92/vblo/04,679.99,yes,locked 2006.145.05:08:53.92/vblo/05,709.99,yes,locked 2006.145.05:08:53.92/vblo/06,719.99,yes,locked 2006.145.05:08:53.92/vblo/07,734.99,yes,locked 2006.145.05:08:53.92/vblo/08,744.99,yes,locked 2006.145.05:08:54.07/vabw/8 2006.145.05:08:54.22/vbbw/8 2006.145.05:08:54.34/xfe/off,on,16.0 2006.145.05:08:54.73/ifatt/23,28,28,28 2006.145.05:08:55.10/fmout-gps/S +5.1E-08 2006.145.05:08:55.19:!2006.145.05:09:50 2006.145.05:09:50.01:data_valid=off 2006.145.05:09:50.02:"et 2006.145.05:09:50.02:!+3s 2006.145.05:09:53.05:"tape 2006.145.05:09:53.09:postob 2006.145.05:09:53.25/cable/+6.5417E-03 2006.145.05:09:53.26/wx/20.98,1016.4,57 2006.145.05:09:53.32/fmout-gps/S +5.1E-08 2006.145.05:09:53.32:scan_name=145-0511,jd0605,80 2006.145.05:09:53.32:source=0528+134,053056.42,133155.1,2000.0,cw 2006.145.05:09:54.14#flagr#flagr/antenna,new-source 2006.145.05:09:54.15:checkk5 2006.145.05:09:54.67/chk_autoobs//k5ts1/ autoobs is running! 2006.145.05:09:55.40/chk_autoobs//k5ts2/ autoobs is running! 2006.145.05:09:56.03/chk_autoobs//k5ts3/ autoobs is running! 2006.145.05:09:56.49/chk_autoobs//k5ts4/ autoobs is running! 2006.145.05:09:56.99/chk_obsdata//k5ts1/T1450508??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.145.05:09:57.70/chk_obsdata//k5ts2/T1450508??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.145.05:09:58.25/chk_obsdata//k5ts3/T1450508??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.145.05:09:58.79/chk_obsdata//k5ts4/T1450508??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.145.05:09:59.65/k5log//k5ts1_log_newline 2006.145.05:10:00.75/k5log//k5ts2_log_newline 2006.145.05:10:01.82/k5log//k5ts3_log_newline 2006.145.05:10:02.81/k5log//k5ts4_log_newline 2006.145.05:10:02.83/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.05:10:02.83:setupk4=1 2006.145.05:10:02.83$setupk4/echo=on 2006.145.05:10:02.83$setupk4/pcalon 2006.145.05:10:02.83$pcalon/"no phase cal control is implemented here 2006.145.05:10:02.83$setupk4/"tpicd=stop 2006.145.05:10:02.83$setupk4/"rec=synch_on 2006.145.05:10:02.83$setupk4/"rec_mode=128 2006.145.05:10:02.83$setupk4/!* 2006.145.05:10:02.83$setupk4/recpk4 2006.145.05:10:02.83$recpk4/recpatch= 2006.145.05:10:02.84$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.05:10:02.84$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.05:10:02.84$setupk4/vck44 2006.145.05:10:02.84$vck44/valo=1,524.99 2006.145.05:10:02.84#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.05:10:02.84#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.05:10:02.84#ibcon#ireg 17 cls_cnt 0 2006.145.05:10:02.84#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.05:10:02.84#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.05:10:02.84#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.05:10:02.87#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.05:10:02.92#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.05:10:02.92#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.05:10:02.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.05:10:02.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.05:10:02.92$vck44/va=1,8 2006.145.05:10:02.92#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.05:10:02.92#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.05:10:02.92#ibcon#ireg 11 cls_cnt 2 2006.145.05:10:02.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.05:10:02.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.05:10:02.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.05:10:02.94#ibcon#[25=AT01-08\r\n] 2006.145.05:10:02.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.05:10:02.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.05:10:02.97#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.05:10:02.97#ibcon#ireg 7 cls_cnt 0 2006.145.05:10:02.97#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.05:10:03.09#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.05:10:03.09#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.05:10:03.11#ibcon#[25=USB\r\n] 2006.145.05:10:03.14#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.05:10:03.14#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.05:10:03.14#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.05:10:03.14#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.05:10:03.14$vck44/valo=2,534.99 2006.145.05:10:03.14#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.05:10:03.14#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.05:10:03.14#ibcon#ireg 17 cls_cnt 0 2006.145.05:10:03.15#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.05:10:03.15#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.05:10:03.15#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.05:10:03.18#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.05:10:03.21#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.05:10:03.21#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.05:10:03.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.05:10:03.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.05:10:03.21$vck44/va=2,7 2006.145.05:10:03.21#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.05:10:03.21#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.05:10:03.21#ibcon#ireg 11 cls_cnt 2 2006.145.05:10:03.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.05:10:03.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.05:10:03.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.05:10:03.28#ibcon#[25=AT02-07\r\n] 2006.145.05:10:03.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.05:10:03.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.05:10:03.31#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.05:10:03.31#ibcon#ireg 7 cls_cnt 0 2006.145.05:10:03.31#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.05:10:03.43#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.05:10:03.43#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.05:10:03.45#ibcon#[25=USB\r\n] 2006.145.05:10:03.48#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.05:10:03.48#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.05:10:03.48#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.05:10:03.48#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.05:10:03.48$vck44/valo=3,564.99 2006.145.05:10:03.48#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.05:10:03.48#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.05:10:03.48#ibcon#ireg 17 cls_cnt 0 2006.145.05:10:03.48#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:10:03.48#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:10:03.48#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:10:03.50#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.05:10:03.54#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:10:03.54#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:10:03.54#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.05:10:03.54#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.05:10:03.54$vck44/va=3,8 2006.145.05:10:03.54#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.05:10:03.54#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.05:10:03.54#ibcon#ireg 11 cls_cnt 2 2006.145.05:10:03.54#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:10:03.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:10:03.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:10:03.62#ibcon#[25=AT03-08\r\n] 2006.145.05:10:03.65#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:10:03.65#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:10:03.65#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.05:10:03.65#ibcon#ireg 7 cls_cnt 0 2006.145.05:10:03.65#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:10:03.77#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:10:03.77#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:10:03.79#ibcon#[25=USB\r\n] 2006.145.05:10:03.82#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:10:03.82#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:10:03.82#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.05:10:03.82#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.05:10:03.82$vck44/valo=4,624.99 2006.145.05:10:03.82#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.05:10:03.82#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.05:10:03.82#ibcon#ireg 17 cls_cnt 0 2006.145.05:10:03.82#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:10:03.82#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:10:03.82#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:10:03.84#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.05:10:03.88#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:10:03.88#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:10:03.88#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.05:10:03.88#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.05:10:03.88$vck44/va=4,7 2006.145.05:10:03.88#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.05:10:03.88#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.05:10:03.88#ibcon#ireg 11 cls_cnt 2 2006.145.05:10:03.88#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:10:03.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:10:03.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:10:03.96#ibcon#[25=AT04-07\r\n] 2006.145.05:10:03.99#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:10:03.99#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:10:03.99#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.05:10:03.99#ibcon#ireg 7 cls_cnt 0 2006.145.05:10:03.99#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:10:04.11#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:10:04.11#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:10:04.13#ibcon#[25=USB\r\n] 2006.145.05:10:04.16#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:10:04.16#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:10:04.16#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.05:10:04.16#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.05:10:04.16$vck44/valo=5,734.99 2006.145.05:10:04.16#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.05:10:04.16#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.05:10:04.16#ibcon#ireg 17 cls_cnt 0 2006.145.05:10:04.16#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:10:04.16#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:10:04.16#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:10:04.18#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.05:10:04.22#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:10:04.22#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:10:04.22#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.05:10:04.22#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.05:10:04.22$vck44/va=5,4 2006.145.05:10:04.22#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.05:10:04.22#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.05:10:04.22#ibcon#ireg 11 cls_cnt 2 2006.145.05:10:04.22#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:10:04.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:10:04.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:10:04.30#ibcon#[25=AT05-04\r\n] 2006.145.05:10:04.33#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:10:04.33#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:10:04.33#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.05:10:04.33#ibcon#ireg 7 cls_cnt 0 2006.145.05:10:04.33#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:10:04.45#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:10:04.45#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:10:04.47#ibcon#[25=USB\r\n] 2006.145.05:10:04.50#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:10:04.50#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:10:04.50#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.05:10:04.50#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.05:10:04.50$vck44/valo=6,814.99 2006.145.05:10:04.50#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.05:10:04.50#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.05:10:04.50#ibcon#ireg 17 cls_cnt 0 2006.145.05:10:04.50#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.05:10:04.50#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.05:10:04.50#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.05:10:04.52#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.05:10:04.56#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.05:10:04.56#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.05:10:04.56#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.05:10:04.56#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.05:10:04.56$vck44/va=6,4 2006.145.05:10:04.56#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.05:10:04.56#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.05:10:04.56#ibcon#ireg 11 cls_cnt 2 2006.145.05:10:04.56#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.05:10:04.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.05:10:04.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.05:10:04.64#ibcon#[25=AT06-04\r\n] 2006.145.05:10:04.67#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.05:10:04.67#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.05:10:04.67#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.05:10:04.67#ibcon#ireg 7 cls_cnt 0 2006.145.05:10:04.67#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.05:10:04.79#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.05:10:04.79#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.05:10:04.81#ibcon#[25=USB\r\n] 2006.145.05:10:04.84#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.05:10:04.84#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.05:10:04.84#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.05:10:04.84#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.05:10:04.84$vck44/valo=7,864.99 2006.145.05:10:04.84#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.05:10:04.84#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.05:10:04.84#ibcon#ireg 17 cls_cnt 0 2006.145.05:10:04.84#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.05:10:04.84#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.05:10:04.84#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.05:10:04.86#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.05:10:04.90#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.05:10:04.90#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.05:10:04.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.05:10:04.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.05:10:04.90$vck44/va=7,4 2006.145.05:10:04.90#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.05:10:04.90#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.05:10:04.90#ibcon#ireg 11 cls_cnt 2 2006.145.05:10:04.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:10:04.96#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:10:04.96#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:10:04.98#ibcon#[25=AT07-04\r\n] 2006.145.05:10:05.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:10:05.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:10:05.04#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.05:10:05.04#ibcon#ireg 7 cls_cnt 0 2006.145.05:10:05.04#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:10:05.15#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:10:05.15#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:10:05.17#ibcon#[25=USB\r\n] 2006.145.05:10:05.20#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:10:05.20#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:10:05.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.05:10:05.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.05:10:05.20$vck44/valo=8,884.99 2006.145.05:10:05.20#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.05:10:05.20#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.05:10:05.20#ibcon#ireg 17 cls_cnt 0 2006.145.05:10:05.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:10:05.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:10:05.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:10:05.24#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.05:10:05.27#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:10:05.27#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:10:05.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.05:10:05.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.05:10:05.27$vck44/va=8,4 2006.145.05:10:05.27#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.05:10:05.27#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.05:10:05.27#ibcon#ireg 11 cls_cnt 2 2006.145.05:10:05.27#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:10:05.33#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:10:05.33#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:10:05.34#ibcon#[25=AT08-04\r\n] 2006.145.05:10:05.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:10:05.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:10:05.37#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.05:10:05.37#ibcon#ireg 7 cls_cnt 0 2006.145.05:10:05.37#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:10:05.49#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:10:05.49#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:10:05.51#ibcon#[25=USB\r\n] 2006.145.05:10:05.54#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:10:05.54#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:10:05.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.05:10:05.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.05:10:05.54$vck44/vblo=1,629.99 2006.145.05:10:05.54#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.05:10:05.54#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.05:10:05.54#ibcon#ireg 17 cls_cnt 0 2006.145.05:10:05.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:10:05.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:10:05.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:10:05.56#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.05:10:05.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:10:05.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:10:05.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.05:10:05.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.05:10:05.60$vck44/vb=1,3 2006.145.05:10:05.60#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.05:10:05.60#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.05:10:05.60#ibcon#ireg 11 cls_cnt 2 2006.145.05:10:05.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.05:10:05.60#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.05:10:05.60#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.05:10:05.62#ibcon#[27=AT01-03\r\n] 2006.145.05:10:05.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.05:10:05.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.05:10:05.65#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.05:10:05.65#ibcon#ireg 7 cls_cnt 0 2006.145.05:10:05.65#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.05:10:05.77#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.05:10:05.77#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.05:10:05.79#ibcon#[27=USB\r\n] 2006.145.05:10:05.82#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.05:10:05.82#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.05:10:05.82#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.05:10:05.82#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.05:10:05.82$vck44/vblo=2,634.99 2006.145.05:10:05.82#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.05:10:05.82#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.05:10:05.82#ibcon#ireg 17 cls_cnt 0 2006.145.05:10:05.82#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.05:10:05.82#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.05:10:05.82#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.05:10:05.84#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.05:10:05.86#abcon#<5=/05 3.6 7.7 20.99 591016.4\r\n> 2006.145.05:10:05.88#abcon#{5=INTERFACE CLEAR} 2006.145.05:10:05.88#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.05:10:05.88#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.05:10:05.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.05:10:05.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.05:10:05.88$vck44/vb=2,4 2006.145.05:10:05.88#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.05:10:05.88#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.05:10:05.88#ibcon#ireg 11 cls_cnt 2 2006.145.05:10:05.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:10:05.94#abcon#[5=S1D000X0/0*\r\n] 2006.145.05:10:05.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:10:05.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:10:05.96#ibcon#[27=AT02-04\r\n] 2006.145.05:10:05.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:10:05.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:10:05.99#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.05:10:05.99#ibcon#ireg 7 cls_cnt 0 2006.145.05:10:05.99#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:10:06.11#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:10:06.11#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:10:06.13#ibcon#[27=USB\r\n] 2006.145.05:10:06.16#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:10:06.16#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:10:06.16#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.05:10:06.16#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.05:10:06.16$vck44/vblo=3,649.99 2006.145.05:10:06.16#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.05:10:06.16#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.05:10:06.16#ibcon#ireg 17 cls_cnt 0 2006.145.05:10:06.16#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:10:06.16#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:10:06.16#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:10:06.18#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.05:10:06.22#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:10:06.22#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:10:06.22#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.05:10:06.22#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.05:10:06.22$vck44/vb=3,4 2006.145.05:10:06.22#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.05:10:06.22#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.05:10:06.22#ibcon#ireg 11 cls_cnt 2 2006.145.05:10:06.22#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:10:06.28#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:10:06.28#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:10:06.30#ibcon#[27=AT03-04\r\n] 2006.145.05:10:06.33#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:10:06.33#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:10:06.33#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.05:10:06.33#ibcon#ireg 7 cls_cnt 0 2006.145.05:10:06.33#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:10:06.45#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:10:06.45#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:10:06.47#ibcon#[27=USB\r\n] 2006.145.05:10:06.50#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:10:06.50#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:10:06.50#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.05:10:06.50#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.05:10:06.50$vck44/vblo=4,679.99 2006.145.05:10:06.50#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.05:10:06.50#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.05:10:06.50#ibcon#ireg 17 cls_cnt 0 2006.145.05:10:06.50#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:10:06.50#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:10:06.50#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:10:06.52#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.05:10:06.56#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:10:06.56#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:10:06.56#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.05:10:06.56#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.05:10:06.56$vck44/vb=4,4 2006.145.05:10:06.56#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.05:10:06.56#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.05:10:06.56#ibcon#ireg 11 cls_cnt 2 2006.145.05:10:06.56#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:10:06.62#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:10:06.62#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:10:06.64#ibcon#[27=AT04-04\r\n] 2006.145.05:10:06.67#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:10:06.67#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:10:06.67#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.05:10:06.67#ibcon#ireg 7 cls_cnt 0 2006.145.05:10:06.67#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:10:06.79#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:10:06.79#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:10:06.81#ibcon#[27=USB\r\n] 2006.145.05:10:06.84#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:10:06.84#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:10:06.84#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.05:10:06.84#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.05:10:06.84$vck44/vblo=5,709.99 2006.145.05:10:06.84#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.05:10:06.84#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.05:10:06.84#ibcon#ireg 17 cls_cnt 0 2006.145.05:10:06.84#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:10:06.84#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:10:06.84#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:10:06.86#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.05:10:06.90#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:10:06.90#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:10:06.90#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.05:10:06.90#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.05:10:06.90$vck44/vb=5,4 2006.145.05:10:06.90#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.05:10:06.90#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.05:10:06.90#ibcon#ireg 11 cls_cnt 2 2006.145.05:10:06.90#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:10:06.96#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:10:06.96#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:10:06.98#ibcon#[27=AT05-04\r\n] 2006.145.05:10:07.01#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:10:07.01#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:10:07.01#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.05:10:07.01#ibcon#ireg 7 cls_cnt 0 2006.145.05:10:07.01#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:10:07.13#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:10:07.13#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:10:07.15#ibcon#[27=USB\r\n] 2006.145.05:10:07.18#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:10:07.18#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:10:07.18#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.05:10:07.18#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.05:10:07.18$vck44/vblo=6,719.99 2006.145.05:10:07.18#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.05:10:07.18#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.05:10:07.18#ibcon#ireg 17 cls_cnt 0 2006.145.05:10:07.18#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.05:10:07.18#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.05:10:07.18#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.05:10:07.20#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.05:10:07.24#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.05:10:07.24#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.05:10:07.24#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.05:10:07.24#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.05:10:07.24$vck44/vb=6,4 2006.145.05:10:07.24#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.05:10:07.24#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.05:10:07.24#ibcon#ireg 11 cls_cnt 2 2006.145.05:10:07.24#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.05:10:07.30#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.05:10:07.30#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.05:10:07.32#ibcon#[27=AT06-04\r\n] 2006.145.05:10:07.35#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.05:10:07.35#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.05:10:07.35#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.05:10:07.35#ibcon#ireg 7 cls_cnt 0 2006.145.05:10:07.35#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.05:10:07.47#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.05:10:07.47#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.05:10:07.49#ibcon#[27=USB\r\n] 2006.145.05:10:07.52#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.05:10:07.52#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.05:10:07.52#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.05:10:07.52#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.05:10:07.52$vck44/vblo=7,734.99 2006.145.05:10:07.52#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.05:10:07.52#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.05:10:07.52#ibcon#ireg 17 cls_cnt 0 2006.145.05:10:07.52#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.05:10:07.52#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.05:10:07.52#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.05:10:07.54#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.05:10:07.58#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.05:10:07.58#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.05:10:07.58#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.05:10:07.58#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.05:10:07.58$vck44/vb=7,4 2006.145.05:10:07.58#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.05:10:07.58#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.05:10:07.58#ibcon#ireg 11 cls_cnt 2 2006.145.05:10:07.58#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:10:07.64#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:10:07.64#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:10:07.66#ibcon#[27=AT07-04\r\n] 2006.145.05:10:07.69#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:10:07.69#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:10:07.69#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.05:10:07.69#ibcon#ireg 7 cls_cnt 0 2006.145.05:10:07.69#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:10:07.81#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:10:07.81#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:10:07.83#ibcon#[27=USB\r\n] 2006.145.05:10:07.86#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:10:07.86#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:10:07.86#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.05:10:07.86#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.05:10:07.86$vck44/vblo=8,744.99 2006.145.05:10:07.86#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.05:10:07.86#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.05:10:07.86#ibcon#ireg 17 cls_cnt 0 2006.145.05:10:07.86#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:10:07.86#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:10:07.86#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:10:07.88#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.05:10:07.92#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:10:07.92#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:10:07.92#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.05:10:07.92#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.05:10:07.92$vck44/vb=8,4 2006.145.05:10:07.92#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.05:10:07.92#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.05:10:07.92#ibcon#ireg 11 cls_cnt 2 2006.145.05:10:07.92#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:10:07.98#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:10:07.98#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:10:08.00#ibcon#[27=AT08-04\r\n] 2006.145.05:10:08.03#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:10:08.03#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:10:08.03#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.05:10:08.03#ibcon#ireg 7 cls_cnt 0 2006.145.05:10:08.03#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:10:08.15#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:10:08.15#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:10:08.17#ibcon#[27=USB\r\n] 2006.145.05:10:08.20#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:10:08.20#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:10:08.20#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.05:10:08.20#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.05:10:08.20$vck44/vabw=wide 2006.145.05:10:08.20#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.05:10:08.20#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.05:10:08.20#ibcon#ireg 8 cls_cnt 0 2006.145.05:10:08.20#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:10:08.20#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:10:08.20#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:10:08.22#ibcon#[25=BW32\r\n] 2006.145.05:10:08.25#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:10:08.25#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:10:08.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.05:10:08.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.05:10:08.25$vck44/vbbw=wide 2006.145.05:10:08.25#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.05:10:08.25#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.05:10:08.25#ibcon#ireg 8 cls_cnt 0 2006.145.05:10:08.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.05:10:08.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.05:10:08.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.05:10:08.34#ibcon#[27=BW32\r\n] 2006.145.05:10:08.37#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.05:10:08.37#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.05:10:08.37#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.05:10:08.37#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.05:10:08.37$setupk4/ifdk4 2006.145.05:10:08.37$ifdk4/lo= 2006.145.05:10:08.37$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.05:10:08.37$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.05:10:08.37$ifdk4/patch= 2006.145.05:10:08.37$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.05:10:08.38$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.05:10:08.38$setupk4/!*+20s 2006.145.05:10:16.03#abcon#<5=/05 3.6 7.7 20.99 601016.4\r\n> 2006.145.05:10:16.05#abcon#{5=INTERFACE CLEAR} 2006.145.05:10:16.11#abcon#[5=S1D000X0/0*\r\n] 2006.145.05:10:21.13#trakl#Source acquired 2006.145.05:10:22.85$setupk4/"tpicd 2006.145.05:10:22.85$setupk4/echo=off 2006.145.05:10:22.85$setupk4/xlog=off 2006.145.05:10:22.85:!2006.145.05:11:36 2006.145.05:10:23.13#flagr#flagr/antenna,acquired 2006.145.05:11:36.00:preob 2006.145.05:11:36.13/onsource/TRACKING 2006.145.05:11:36.13:!2006.145.05:11:46 2006.145.05:11:46.00:"tape 2006.145.05:11:46.00:"st=record 2006.145.05:11:46.00:data_valid=on 2006.145.05:11:46.00:midob 2006.145.05:11:47.13/onsource/TRACKING 2006.145.05:11:47.13/wx/21.00,1016.3,62 2006.145.05:11:47.21/cable/+6.5432E-03 2006.145.05:11:48.30/va/01,08,usb,yes,28,30 2006.145.05:11:48.30/va/02,07,usb,yes,30,30 2006.145.05:11:48.30/va/03,08,usb,yes,27,28 2006.145.05:11:48.30/va/04,07,usb,yes,31,33 2006.145.05:11:48.30/va/05,04,usb,yes,27,27 2006.145.05:11:48.30/va/06,04,usb,yes,30,30 2006.145.05:11:48.30/va/07,04,usb,yes,31,32 2006.145.05:11:48.30/va/08,04,usb,yes,26,31 2006.145.05:11:48.53/valo/01,524.99,yes,locked 2006.145.05:11:48.53/valo/02,534.99,yes,locked 2006.145.05:11:48.53/valo/03,564.99,yes,locked 2006.145.05:11:48.53/valo/04,624.99,yes,locked 2006.145.05:11:48.53/valo/05,734.99,yes,locked 2006.145.05:11:48.53/valo/06,814.99,yes,locked 2006.145.05:11:48.53/valo/07,864.99,yes,locked 2006.145.05:11:48.53/valo/08,884.99,yes,locked 2006.145.05:11:49.62/vb/01,03,usb,yes,35,33 2006.145.05:11:49.62/vb/02,04,usb,yes,31,31 2006.145.05:11:49.62/vb/03,04,usb,yes,28,31 2006.145.05:11:49.62/vb/04,04,usb,yes,32,31 2006.145.05:11:49.62/vb/05,04,usb,yes,25,27 2006.145.05:11:49.62/vb/06,04,usb,yes,29,26 2006.145.05:11:49.62/vb/07,04,usb,yes,29,29 2006.145.05:11:49.62/vb/08,04,usb,yes,27,30 2006.145.05:11:49.86/vblo/01,629.99,yes,locked 2006.145.05:11:49.86/vblo/02,634.99,yes,locked 2006.145.05:11:49.86/vblo/03,649.99,yes,locked 2006.145.05:11:49.86/vblo/04,679.99,yes,locked 2006.145.05:11:49.86/vblo/05,709.99,yes,locked 2006.145.05:11:49.86/vblo/06,719.99,yes,locked 2006.145.05:11:49.86/vblo/07,734.99,yes,locked 2006.145.05:11:49.86/vblo/08,744.99,yes,locked 2006.145.05:11:50.01/vabw/8 2006.145.05:11:50.16/vbbw/8 2006.145.05:11:50.27/xfe/off,on,14.5 2006.145.05:11:50.67/ifatt/23,28,28,28 2006.145.05:11:51.07/fmout-gps/S +4.9E-08 2006.145.05:11:51.16:!2006.145.05:13:06 2006.145.05:13:06.01:data_valid=off 2006.145.05:13:06.02:"et 2006.145.05:13:06.02:!+3s 2006.145.05:13:09.05:"tape 2006.145.05:13:09.06:postob 2006.145.05:13:09.16/cable/+6.5439E-03 2006.145.05:13:09.17/wx/21.02,1016.3,58 2006.145.05:13:09.22/fmout-gps/S +4.7E-08 2006.145.05:13:09.23:scan_name=145-0516,jd0605,150 2006.145.05:13:09.23:source=3c274,123049.42,122328.0,2000.0,cw 2006.145.05:13:10.14#flagr#flagr/antenna,new-source 2006.145.05:13:10.15:checkk5 2006.145.05:13:11.02/chk_autoobs//k5ts1/ autoobs is running! 2006.145.05:13:11.53/chk_autoobs//k5ts2/ autoobs is running! 2006.145.05:13:12.00/chk_autoobs//k5ts3/ autoobs is running! 2006.145.05:13:12.48/chk_autoobs//k5ts4/ autoobs is running! 2006.145.05:13:12.99/chk_obsdata//k5ts1/T1450511??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.05:13:13.58/chk_obsdata//k5ts2/T1450511??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.05:13:14.22/chk_obsdata//k5ts3/T1450511??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.05:13:14.70/chk_obsdata//k5ts4/T1450511??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.05:13:15.53/k5log//k5ts1_log_newline 2006.145.05:13:16.66/k5log//k5ts2_log_newline 2006.145.05:13:17.47/k5log//k5ts3_log_newline 2006.145.05:13:18.32/k5log//k5ts4_log_newline 2006.145.05:13:18.35/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.05:13:18.35:setupk4=1 2006.145.05:13:18.35$setupk4/echo=on 2006.145.05:13:18.35$setupk4/pcalon 2006.145.05:13:18.35$pcalon/"no phase cal control is implemented here 2006.145.05:13:18.35$setupk4/"tpicd=stop 2006.145.05:13:18.35$setupk4/"rec=synch_on 2006.145.05:13:18.35$setupk4/"rec_mode=128 2006.145.05:13:18.35$setupk4/!* 2006.145.05:13:18.35$setupk4/recpk4 2006.145.05:13:18.35$recpk4/recpatch= 2006.145.05:13:18.36$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.05:13:18.36$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.05:13:18.36$setupk4/vck44 2006.145.05:13:18.36$vck44/valo=1,524.99 2006.145.05:13:18.36#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.05:13:18.36#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.05:13:18.36#ibcon#ireg 17 cls_cnt 0 2006.145.05:13:18.36#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:13:18.36#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:13:18.36#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:13:18.39#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.05:13:18.44#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:13:18.44#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:13:18.44#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.05:13:18.44#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.05:13:18.44$vck44/va=1,8 2006.145.05:13:18.44#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.05:13:18.44#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.05:13:18.44#ibcon#ireg 11 cls_cnt 2 2006.145.05:13:18.44#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:13:18.44#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:13:18.44#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:13:18.46#ibcon#[25=AT01-08\r\n] 2006.145.05:13:18.49#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:13:18.49#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:13:18.49#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.05:13:18.49#ibcon#ireg 7 cls_cnt 0 2006.145.05:13:18.49#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:13:18.62#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:13:18.62#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:13:18.63#ibcon#[25=USB\r\n] 2006.145.05:13:18.66#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:13:18.66#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:13:18.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.05:13:18.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.05:13:18.66$vck44/valo=2,534.99 2006.145.05:13:18.66#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.05:13:18.66#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.05:13:18.66#ibcon#ireg 17 cls_cnt 0 2006.145.05:13:18.66#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:13:18.66#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:13:18.66#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:13:18.69#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.05:13:18.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:13:18.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:13:18.73#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.05:13:18.73#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.05:13:18.73$vck44/va=2,7 2006.145.05:13:18.73#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.05:13:18.73#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.05:13:18.73#ibcon#ireg 11 cls_cnt 2 2006.145.05:13:18.73#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:13:18.79#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:13:18.79#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:13:18.82#ibcon#[25=AT02-07\r\n] 2006.145.05:13:18.84#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:13:18.84#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:13:18.84#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.05:13:18.84#ibcon#ireg 7 cls_cnt 0 2006.145.05:13:18.84#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:13:18.96#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:13:18.96#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:13:18.98#ibcon#[25=USB\r\n] 2006.145.05:13:19.01#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:13:19.01#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:13:19.01#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.05:13:19.01#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.05:13:19.01$vck44/valo=3,564.99 2006.145.05:13:19.01#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.05:13:19.01#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.05:13:19.01#ibcon#ireg 17 cls_cnt 0 2006.145.05:13:19.01#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:13:19.01#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:13:19.01#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:13:19.03#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.05:13:19.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:13:19.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:13:19.07#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.05:13:19.07#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.05:13:19.07$vck44/va=3,8 2006.145.05:13:19.07#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.05:13:19.07#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.05:13:19.07#ibcon#ireg 11 cls_cnt 2 2006.145.05:13:19.07#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:13:19.09#abcon#<5=/04 3.9 7.7 21.03 601016.3\r\n> 2006.145.05:13:19.11#abcon#{5=INTERFACE CLEAR} 2006.145.05:13:19.13#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:13:19.13#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:13:19.15#ibcon#[25=AT03-08\r\n] 2006.145.05:13:19.17#abcon#[5=S1D000X0/0*\r\n] 2006.145.05:13:19.18#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:13:19.18#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:13:19.18#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.05:13:19.18#ibcon#ireg 7 cls_cnt 0 2006.145.05:13:19.18#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:13:19.30#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:13:19.30#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:13:19.32#ibcon#[25=USB\r\n] 2006.145.05:13:19.35#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:13:19.35#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:13:19.35#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.05:13:19.35#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.05:13:19.35$vck44/valo=4,624.99 2006.145.05:13:19.35#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.05:13:19.35#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.05:13:19.35#ibcon#ireg 17 cls_cnt 0 2006.145.05:13:19.35#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:13:19.35#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:13:19.35#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:13:19.37#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.05:13:19.41#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:13:19.41#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:13:19.41#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.05:13:19.41#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.05:13:19.41$vck44/va=4,7 2006.145.05:13:19.41#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.05:13:19.41#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.05:13:19.41#ibcon#ireg 11 cls_cnt 2 2006.145.05:13:19.41#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:13:19.47#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:13:19.47#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:13:19.49#ibcon#[25=AT04-07\r\n] 2006.145.05:13:19.52#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:13:19.52#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:13:19.52#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.05:13:19.52#ibcon#ireg 7 cls_cnt 0 2006.145.05:13:19.52#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:13:19.64#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:13:19.64#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:13:19.66#ibcon#[25=USB\r\n] 2006.145.05:13:19.69#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:13:19.69#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:13:19.69#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.05:13:19.69#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.05:13:19.69$vck44/valo=5,734.99 2006.145.05:13:19.69#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.05:13:19.69#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.05:13:19.69#ibcon#ireg 17 cls_cnt 0 2006.145.05:13:19.69#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:13:19.69#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:13:19.69#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:13:19.71#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.05:13:19.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:13:19.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:13:19.75#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.05:13:19.75#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.05:13:19.75$vck44/va=5,4 2006.145.05:13:19.75#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.05:13:19.75#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.05:13:19.75#ibcon#ireg 11 cls_cnt 2 2006.145.05:13:19.75#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:13:19.81#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:13:19.81#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:13:19.83#ibcon#[25=AT05-04\r\n] 2006.145.05:13:19.86#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:13:19.86#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:13:19.86#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.05:13:19.86#ibcon#ireg 7 cls_cnt 0 2006.145.05:13:19.86#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:13:19.98#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:13:19.98#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:13:20.00#ibcon#[25=USB\r\n] 2006.145.05:13:20.03#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:13:20.03#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:13:20.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.05:13:20.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.05:13:20.03$vck44/valo=6,814.99 2006.145.05:13:20.03#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.05:13:20.03#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.05:13:20.03#ibcon#ireg 17 cls_cnt 0 2006.145.05:13:20.03#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:13:20.03#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:13:20.03#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:13:20.05#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.05:13:20.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:13:20.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:13:20.09#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.05:13:20.09#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.05:13:20.09$vck44/va=6,4 2006.145.05:13:20.09#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.05:13:20.09#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.05:13:20.09#ibcon#ireg 11 cls_cnt 2 2006.145.05:13:20.09#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:13:20.15#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:13:20.15#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:13:20.17#ibcon#[25=AT06-04\r\n] 2006.145.05:13:20.20#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:13:20.20#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:13:20.20#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.05:13:20.20#ibcon#ireg 7 cls_cnt 0 2006.145.05:13:20.20#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:13:20.32#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:13:20.32#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:13:20.36#ibcon#[25=USB\r\n] 2006.145.05:13:20.38#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:13:20.38#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:13:20.38#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.05:13:20.38#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.05:13:20.38$vck44/valo=7,864.99 2006.145.05:13:20.38#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.05:13:20.38#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.05:13:20.38#ibcon#ireg 17 cls_cnt 0 2006.145.05:13:20.38#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:13:20.38#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:13:20.38#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:13:20.40#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.05:13:20.44#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:13:20.44#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:13:20.44#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.05:13:20.44#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.05:13:20.44$vck44/va=7,4 2006.145.05:13:20.45#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.05:13:20.45#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.05:13:20.45#ibcon#ireg 11 cls_cnt 2 2006.145.05:13:20.45#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:13:20.49#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:13:20.49#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:13:20.52#ibcon#[25=AT07-04\r\n] 2006.145.05:13:20.54#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:13:20.54#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:13:20.54#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.05:13:20.54#ibcon#ireg 7 cls_cnt 0 2006.145.05:13:20.54#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:13:20.66#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:13:20.66#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:13:20.68#ibcon#[25=USB\r\n] 2006.145.05:13:20.71#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:13:20.71#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:13:20.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.05:13:20.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.05:13:20.71$vck44/valo=8,884.99 2006.145.05:13:20.71#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.05:13:20.71#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.05:13:20.71#ibcon#ireg 17 cls_cnt 0 2006.145.05:13:20.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:13:20.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:13:20.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:13:20.73#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.05:13:20.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:13:20.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:13:20.77#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.05:13:20.77#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.05:13:20.77$vck44/va=8,4 2006.145.05:13:20.77#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.05:13:20.77#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.05:13:20.77#ibcon#ireg 11 cls_cnt 2 2006.145.05:13:20.77#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:13:20.83#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:13:20.83#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:13:20.85#ibcon#[25=AT08-04\r\n] 2006.145.05:13:20.88#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:13:20.88#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:13:20.88#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.05:13:20.88#ibcon#ireg 7 cls_cnt 0 2006.145.05:13:20.88#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:13:21.00#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:13:21.00#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:13:21.02#ibcon#[25=USB\r\n] 2006.145.05:13:21.05#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:13:21.05#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:13:21.05#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.05:13:21.05#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.05:13:21.05$vck44/vblo=1,629.99 2006.145.05:13:21.05#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.05:13:21.05#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.05:13:21.05#ibcon#ireg 17 cls_cnt 0 2006.145.05:13:21.05#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:13:21.05#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:13:21.05#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:13:21.07#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.05:13:21.11#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:13:21.11#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:13:21.11#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.05:13:21.11#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.05:13:21.11$vck44/vb=1,3 2006.145.05:13:21.11#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.05:13:21.11#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.05:13:21.11#ibcon#ireg 11 cls_cnt 2 2006.145.05:13:21.11#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:13:21.11#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:13:21.11#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:13:21.13#ibcon#[27=AT01-03\r\n] 2006.145.05:13:21.16#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:13:21.16#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:13:21.16#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.05:13:21.16#ibcon#ireg 7 cls_cnt 0 2006.145.05:13:21.16#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:13:21.28#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:13:21.28#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:13:21.30#ibcon#[27=USB\r\n] 2006.145.05:13:21.33#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:13:21.33#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:13:21.33#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.05:13:21.33#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.05:13:21.33$vck44/vblo=2,634.99 2006.145.05:13:21.33#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.05:13:21.33#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.05:13:21.33#ibcon#ireg 17 cls_cnt 0 2006.145.05:13:21.33#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:13:21.33#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:13:21.33#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:13:21.35#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.05:13:21.39#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:13:21.39#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:13:21.39#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.05:13:21.39#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.05:13:21.39$vck44/vb=2,4 2006.145.05:13:21.39#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.05:13:21.39#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.05:13:21.39#ibcon#ireg 11 cls_cnt 2 2006.145.05:13:21.39#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:13:21.45#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:13:21.45#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:13:21.47#ibcon#[27=AT02-04\r\n] 2006.145.05:13:21.50#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:13:21.50#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:13:21.50#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.05:13:21.50#ibcon#ireg 7 cls_cnt 0 2006.145.05:13:21.50#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:13:21.62#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:13:21.62#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:13:21.64#ibcon#[27=USB\r\n] 2006.145.05:13:21.67#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:13:21.67#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:13:21.67#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.05:13:21.67#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.05:13:21.67$vck44/vblo=3,649.99 2006.145.05:13:21.67#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.05:13:21.67#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.05:13:21.67#ibcon#ireg 17 cls_cnt 0 2006.145.05:13:21.67#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:13:21.67#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:13:21.67#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:13:21.69#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.05:13:21.73#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:13:21.73#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:13:21.73#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.05:13:21.73#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.05:13:21.73$vck44/vb=3,4 2006.145.05:13:21.73#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.05:13:21.73#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.05:13:21.73#ibcon#ireg 11 cls_cnt 2 2006.145.05:13:21.73#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.05:13:21.79#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.05:13:21.79#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.05:13:21.81#ibcon#[27=AT03-04\r\n] 2006.145.05:13:21.84#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.05:13:21.84#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.05:13:21.84#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.05:13:21.84#ibcon#ireg 7 cls_cnt 0 2006.145.05:13:21.84#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.05:13:21.96#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.05:13:21.96#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.05:13:21.98#ibcon#[27=USB\r\n] 2006.145.05:13:22.01#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.05:13:22.01#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.05:13:22.01#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.05:13:22.01#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.05:13:22.01$vck44/vblo=4,679.99 2006.145.05:13:22.01#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.05:13:22.01#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.05:13:22.01#ibcon#ireg 17 cls_cnt 0 2006.145.05:13:22.01#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:13:22.01#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:13:22.01#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:13:22.03#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.05:13:22.07#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:13:22.07#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:13:22.07#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.05:13:22.07#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.05:13:22.07$vck44/vb=4,4 2006.145.05:13:22.07#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.05:13:22.07#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.05:13:22.07#ibcon#ireg 11 cls_cnt 2 2006.145.05:13:22.07#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:13:22.13#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:13:22.13#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:13:22.15#ibcon#[27=AT04-04\r\n] 2006.145.05:13:22.18#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:13:22.18#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:13:22.18#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.05:13:22.18#ibcon#ireg 7 cls_cnt 0 2006.145.05:13:22.18#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:13:22.30#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:13:22.30#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:13:22.32#ibcon#[27=USB\r\n] 2006.145.05:13:22.35#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:13:22.35#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:13:22.35#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.05:13:22.35#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.05:13:22.35$vck44/vblo=5,709.99 2006.145.05:13:22.35#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.05:13:22.35#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.05:13:22.35#ibcon#ireg 17 cls_cnt 0 2006.145.05:13:22.35#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:13:22.35#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:13:22.35#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:13:22.37#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.05:13:22.41#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:13:22.41#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:13:22.41#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.05:13:22.41#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.05:13:22.41$vck44/vb=5,4 2006.145.05:13:22.41#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.05:13:22.41#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.05:13:22.41#ibcon#ireg 11 cls_cnt 2 2006.145.05:13:22.41#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:13:22.47#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:13:22.47#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:13:22.49#ibcon#[27=AT05-04\r\n] 2006.145.05:13:22.52#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:13:22.52#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:13:22.52#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.05:13:22.52#ibcon#ireg 7 cls_cnt 0 2006.145.05:13:22.52#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:13:22.64#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:13:22.64#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:13:22.66#ibcon#[27=USB\r\n] 2006.145.05:13:22.69#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:13:22.69#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:13:22.69#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.05:13:22.69#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.05:13:22.69$vck44/vblo=6,719.99 2006.145.05:13:22.69#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.05:13:22.69#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.05:13:22.69#ibcon#ireg 17 cls_cnt 0 2006.145.05:13:22.69#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:13:22.69#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:13:22.69#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:13:22.71#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.05:13:22.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:13:22.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:13:22.75#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.05:13:22.75#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.05:13:22.75$vck44/vb=6,4 2006.145.05:13:22.75#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.05:13:22.75#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.05:13:22.75#ibcon#ireg 11 cls_cnt 2 2006.145.05:13:22.75#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:13:22.81#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:13:22.81#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:13:22.83#ibcon#[27=AT06-04\r\n] 2006.145.05:13:22.86#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:13:22.86#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:13:22.86#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.05:13:22.86#ibcon#ireg 7 cls_cnt 0 2006.145.05:13:22.86#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:13:22.98#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:13:22.98#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:13:23.00#ibcon#[27=USB\r\n] 2006.145.05:13:23.03#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:13:23.03#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:13:23.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.05:13:23.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.05:13:23.03$vck44/vblo=7,734.99 2006.145.05:13:23.03#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.05:13:23.03#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.05:13:23.03#ibcon#ireg 17 cls_cnt 0 2006.145.05:13:23.03#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:13:23.03#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:13:23.03#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:13:23.05#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.05:13:23.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:13:23.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:13:23.09#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.05:13:23.09#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.05:13:23.09$vck44/vb=7,4 2006.145.05:13:23.09#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.05:13:23.09#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.05:13:23.09#ibcon#ireg 11 cls_cnt 2 2006.145.05:13:23.09#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:13:23.15#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:13:23.15#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:13:23.17#ibcon#[27=AT07-04\r\n] 2006.145.05:13:23.20#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:13:23.20#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:13:23.20#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.05:13:23.20#ibcon#ireg 7 cls_cnt 0 2006.145.05:13:23.20#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:13:23.32#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:13:23.32#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:13:23.34#ibcon#[27=USB\r\n] 2006.145.05:13:23.37#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:13:23.37#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:13:23.37#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.05:13:23.37#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.05:13:23.37$vck44/vblo=8,744.99 2006.145.05:13:23.37#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.05:13:23.37#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.05:13:23.37#ibcon#ireg 17 cls_cnt 0 2006.145.05:13:23.37#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:13:23.37#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:13:23.37#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:13:23.39#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.05:13:23.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:13:23.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:13:23.43#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.05:13:23.43#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.05:13:23.43$vck44/vb=8,4 2006.145.05:13:23.43#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.05:13:23.43#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.05:13:23.43#ibcon#ireg 11 cls_cnt 2 2006.145.05:13:23.43#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:13:23.49#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:13:23.49#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:13:23.51#ibcon#[27=AT08-04\r\n] 2006.145.05:13:23.55#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:13:23.55#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:13:23.55#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.05:13:23.55#ibcon#ireg 7 cls_cnt 0 2006.145.05:13:23.55#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:13:23.66#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:13:23.66#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:13:23.68#ibcon#[27=USB\r\n] 2006.145.05:13:23.71#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:13:23.71#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:13:23.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.05:13:23.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.05:13:23.71$vck44/vabw=wide 2006.145.05:13:23.71#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.05:13:23.71#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.05:13:23.71#ibcon#ireg 8 cls_cnt 0 2006.145.05:13:23.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:13:23.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:13:23.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:13:23.73#ibcon#[25=BW32\r\n] 2006.145.05:13:23.76#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:13:23.76#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:13:23.76#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.05:13:23.76#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.05:13:23.76$vck44/vbbw=wide 2006.145.05:13:23.76#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.05:13:23.76#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.05:13:23.76#ibcon#ireg 8 cls_cnt 0 2006.145.05:13:23.76#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.05:13:23.83#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.05:13:23.83#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.05:13:23.85#ibcon#[27=BW32\r\n] 2006.145.05:13:23.88#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.05:13:23.88#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.05:13:23.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.05:13:23.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.05:13:23.88$setupk4/ifdk4 2006.145.05:13:23.88$ifdk4/lo= 2006.145.05:13:23.88$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.05:13:23.88$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.05:13:23.88$ifdk4/patch= 2006.145.05:13:23.88$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.05:13:23.88$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.05:13:23.88$setupk4/!*+20s 2006.145.05:13:29.26#abcon#<5=/04 3.9 7.7 21.03 571016.3\r\n> 2006.145.05:13:29.28#abcon#{5=INTERFACE CLEAR} 2006.145.05:13:29.34#abcon#[5=S1D000X0/0*\r\n] 2006.145.05:13:38.36$setupk4/"tpicd 2006.145.05:13:38.36$setupk4/echo=off 2006.145.05:13:38.36$setupk4/xlog=off 2006.145.05:13:38.36:!2006.145.05:16:29 2006.145.05:14:05.14#trakl#Source acquired 2006.145.05:14:05.14#flagr#flagr/antenna,acquired 2006.145.05:16:18.14#trakl#Off source 2006.145.05:16:18.14?ERROR st -7 Antenna off-source! 2006.145.05:16:18.14#trakl#az 82.252 el 10.498 azerr*cos(el) 0.0187 elerr 0.0046 2006.145.05:16:20.14#flagr#flagr/antenna,off-source 2006.145.05:16:24.14#trakl#Source re-acquired 2006.145.05:16:26.14#flagr#flagr/antenna,re-acquired 2006.145.05:16:29.00:preob 2006.145.05:16:30.14/onsource/TRACKING 2006.145.05:16:30.14:!2006.145.05:16:39 2006.145.05:16:39.00:"tape 2006.145.05:16:39.00:"st=record 2006.145.05:16:39.00:data_valid=on 2006.145.05:16:39.00:midob 2006.145.05:16:39.14/onsource/TRACKING 2006.145.05:16:39.14/wx/21.02,1016.3,59 2006.145.05:16:39.20/cable/+6.5431E-03 2006.145.05:16:40.29/va/01,08,usb,yes,35,37 2006.145.05:16:40.29/va/02,07,usb,yes,37,38 2006.145.05:16:40.29/va/03,08,usb,yes,34,35 2006.145.05:16:40.29/va/04,07,usb,yes,38,40 2006.145.05:16:40.29/va/05,04,usb,yes,33,34 2006.145.05:16:40.29/va/06,04,usb,yes,37,37 2006.145.05:16:40.29/va/07,04,usb,yes,38,39 2006.145.05:16:40.29/va/08,04,usb,yes,32,39 2006.145.05:16:40.52/valo/01,524.99,yes,locked 2006.145.05:16:40.52/valo/02,534.99,yes,locked 2006.145.05:16:40.52/valo/03,564.99,yes,locked 2006.145.05:16:40.52/valo/04,624.99,yes,locked 2006.145.05:16:40.52/valo/05,734.99,yes,locked 2006.145.05:16:40.52/valo/06,814.99,yes,locked 2006.145.05:16:40.52/valo/07,864.99,yes,locked 2006.145.05:16:40.52/valo/08,884.99,yes,locked 2006.145.05:16:41.61/vb/01,03,usb,yes,44,84 2006.145.05:16:41.61/vb/02,04,usb,yes,38,78 2006.145.05:16:41.61/vb/03,04,usb,yes,35,48 2006.145.05:16:41.61/vb/04,04,usb,yes,39,38 2006.145.05:16:41.61/vb/05,04,usb,yes,32,35 2006.145.05:16:41.61/vb/06,04,usb,yes,38,33 2006.145.05:16:41.61/vb/07,04,usb,yes,36,36 2006.145.05:16:41.61/vb/08,04,usb,yes,33,37 2006.145.05:16:41.85/vblo/01,629.99,yes,locked 2006.145.05:16:41.85/vblo/02,634.99,yes,locked 2006.145.05:16:41.85/vblo/03,649.99,yes,locked 2006.145.05:16:41.85/vblo/04,679.99,yes,locked 2006.145.05:16:41.85/vblo/05,709.99,yes,locked 2006.145.05:16:41.85/vblo/06,719.99,yes,locked 2006.145.05:16:41.85/vblo/07,734.99,yes,locked 2006.145.05:16:41.85/vblo/08,744.99,yes,locked 2006.145.05:16:42.00/vabw/8 2006.145.05:16:42.15/vbbw/8 2006.145.05:16:42.24/xfe/off,on,16.0 2006.145.05:16:42.62/ifatt/23,28,28,28 2006.145.05:16:43.07/fmout-gps/S +4.8E-08 2006.145.05:16:43.15:!2006.145.05:19:09 2006.145.05:19:09.00:data_valid=off 2006.145.05:19:09.01:"et 2006.145.05:19:09.01:!+3s 2006.145.05:19:12.02:"tape 2006.145.05:19:12.03:postob 2006.145.05:19:12.18/cable/+6.5419E-03 2006.145.05:19:12.19/wx/21.01,1016.4,60 2006.145.05:19:12.24/fmout-gps/S +4.7E-08 2006.145.05:19:12.24:scan_name=145-0520,jd0605,180 2006.145.05:19:12.24:source=1044+719,104827.62,714335.9,2000.0,cw 2006.145.05:19:13.13#flagr#flagr/antenna,new-source 2006.145.05:19:13.14:checkk5 2006.145.05:19:13.64/chk_autoobs//k5ts1/ autoobs is running! 2006.145.05:19:14.15/chk_autoobs//k5ts2/ autoobs is running! 2006.145.05:19:14.62/chk_autoobs//k5ts3/ autoobs is running! 2006.145.05:19:15.10/chk_autoobs//k5ts4/ autoobs is running! 2006.145.05:19:15.57/chk_obsdata//k5ts1/T1450516??a.dat file size is correct (nominal:600MB, actual:596MB). 2006.145.05:19:16.02/chk_obsdata//k5ts2/T1450516??b.dat file size is correct (nominal:600MB, actual:596MB). 2006.145.05:19:16.84/chk_obsdata//k5ts3/T1450516??c.dat file size is correct (nominal:600MB, actual:596MB). 2006.145.05:19:17.47/chk_obsdata//k5ts4/T1450516??d.dat file size is correct (nominal:600MB, actual:596MB). 2006.145.05:19:18.27/k5log//k5ts1_log_newline 2006.145.05:19:19.29/k5log//k5ts2_log_newline 2006.145.05:19:20.26/k5log//k5ts3_log_newline 2006.145.05:19:21.04/k5log//k5ts4_log_newline 2006.145.05:19:21.10/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.05:19:21.10:setupk4=1 2006.145.05:19:21.10$setupk4/echo=on 2006.145.05:19:21.10$setupk4/pcalon 2006.145.05:19:21.10$pcalon/"no phase cal control is implemented here 2006.145.05:19:21.10$setupk4/"tpicd=stop 2006.145.05:19:21.10$setupk4/"rec=synch_on 2006.145.05:19:21.10$setupk4/"rec_mode=128 2006.145.05:19:21.10$setupk4/!* 2006.145.05:19:21.10$setupk4/recpk4 2006.145.05:19:21.10$recpk4/recpatch= 2006.145.05:19:21.11$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.05:19:21.11$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.05:19:21.11$setupk4/vck44 2006.145.05:19:21.11$vck44/valo=1,524.99 2006.145.05:19:21.11#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.05:19:21.11#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.05:19:21.11#ibcon#ireg 17 cls_cnt 0 2006.145.05:19:21.11#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.05:19:21.11#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.05:19:21.11#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.05:19:21.13#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.05:19:21.18#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.05:19:21.18#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.05:19:21.18#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.05:19:21.18#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.05:19:21.18$vck44/va=1,8 2006.145.05:19:21.18#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.05:19:21.18#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.05:19:21.18#ibcon#ireg 11 cls_cnt 2 2006.145.05:19:21.18#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.05:19:21.18#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.05:19:21.18#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.05:19:21.20#ibcon#[25=AT01-08\r\n] 2006.145.05:19:21.23#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.05:19:21.23#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.05:19:21.23#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.05:19:21.23#ibcon#ireg 7 cls_cnt 0 2006.145.05:19:21.23#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.05:19:21.35#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.05:19:21.35#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.05:19:21.37#ibcon#[25=USB\r\n] 2006.145.05:19:21.40#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.05:19:21.40#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.05:19:21.40#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.05:19:21.40#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.05:19:21.40$vck44/valo=2,534.99 2006.145.05:19:21.40#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.05:19:21.40#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.05:19:21.40#ibcon#ireg 17 cls_cnt 0 2006.145.05:19:21.40#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:19:21.40#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:19:21.40#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:19:21.42#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.05:19:21.46#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:19:21.46#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:19:21.46#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.05:19:21.46#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.05:19:21.46$vck44/va=2,7 2006.145.05:19:21.46#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.05:19:21.46#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.05:19:21.46#ibcon#ireg 11 cls_cnt 2 2006.145.05:19:21.46#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:19:21.52#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:19:21.52#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:19:21.54#ibcon#[25=AT02-07\r\n] 2006.145.05:19:21.57#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:19:21.57#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:19:21.57#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.05:19:21.57#ibcon#ireg 7 cls_cnt 0 2006.145.05:19:21.57#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:19:21.69#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:19:21.69#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:19:21.71#ibcon#[25=USB\r\n] 2006.145.05:19:21.74#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:19:21.74#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:19:21.74#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.05:19:21.74#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.05:19:21.74$vck44/valo=3,564.99 2006.145.05:19:21.74#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.05:19:21.74#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.05:19:21.74#ibcon#ireg 17 cls_cnt 0 2006.145.05:19:21.74#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:19:21.74#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:19:21.74#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:19:21.76#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.05:19:21.80#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:19:21.80#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:19:21.80#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.05:19:21.80#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.05:19:21.80$vck44/va=3,8 2006.145.05:19:21.80#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.05:19:21.80#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.05:19:21.80#ibcon#ireg 11 cls_cnt 2 2006.145.05:19:21.80#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:19:21.86#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:19:21.86#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:19:21.88#ibcon#[25=AT03-08\r\n] 2006.145.05:19:21.91#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:19:21.91#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:19:21.91#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.05:19:21.91#ibcon#ireg 7 cls_cnt 0 2006.145.05:19:21.91#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:19:22.03#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:19:22.03#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:19:22.05#ibcon#[25=USB\r\n] 2006.145.05:19:22.08#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:19:22.08#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:19:22.08#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.05:19:22.08#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.05:19:22.08$vck44/valo=4,624.99 2006.145.05:19:22.08#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.05:19:22.08#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.05:19:22.08#ibcon#ireg 17 cls_cnt 0 2006.145.05:19:22.08#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:19:22.08#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:19:22.08#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:19:22.10#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.05:19:22.14#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:19:22.14#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:19:22.14#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.05:19:22.14#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.05:19:22.14$vck44/va=4,7 2006.145.05:19:22.14#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.05:19:22.14#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.05:19:22.14#ibcon#ireg 11 cls_cnt 2 2006.145.05:19:22.14#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:19:22.20#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:19:22.20#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:19:22.22#ibcon#[25=AT04-07\r\n] 2006.145.05:19:22.25#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:19:22.25#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:19:22.25#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.05:19:22.25#ibcon#ireg 7 cls_cnt 0 2006.145.05:19:22.25#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:19:22.37#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:19:22.37#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:19:22.39#ibcon#[25=USB\r\n] 2006.145.05:19:22.42#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:19:22.42#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:19:22.42#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.05:19:22.42#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.05:19:22.42$vck44/valo=5,734.99 2006.145.05:19:22.42#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.05:19:22.42#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.05:19:22.42#ibcon#ireg 17 cls_cnt 0 2006.145.05:19:22.42#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.05:19:22.42#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.05:19:22.42#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.05:19:22.44#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.05:19:22.48#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.05:19:22.48#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.05:19:22.48#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.05:19:22.48#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.05:19:22.48$vck44/va=5,4 2006.145.05:19:22.48#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.05:19:22.48#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.05:19:22.48#ibcon#ireg 11 cls_cnt 2 2006.145.05:19:22.48#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.05:19:22.54#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.05:19:22.54#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.05:19:22.56#ibcon#[25=AT05-04\r\n] 2006.145.05:19:22.59#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.05:19:22.59#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.05:19:22.59#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.05:19:22.59#ibcon#ireg 7 cls_cnt 0 2006.145.05:19:22.59#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.05:19:22.71#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.05:19:22.71#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.05:19:22.73#ibcon#[25=USB\r\n] 2006.145.05:19:22.76#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.05:19:22.76#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.05:19:22.76#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.05:19:22.76#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.05:19:22.76$vck44/valo=6,814.99 2006.145.05:19:22.76#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.05:19:22.76#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.05:19:22.76#ibcon#ireg 17 cls_cnt 0 2006.145.05:19:22.76#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.05:19:22.76#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.05:19:22.76#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.05:19:22.78#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.05:19:22.82#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.05:19:22.82#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.05:19:22.82#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.05:19:22.82#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.05:19:22.82$vck44/va=6,4 2006.145.05:19:22.82#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.05:19:22.82#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.05:19:22.82#ibcon#ireg 11 cls_cnt 2 2006.145.05:19:22.82#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:19:22.88#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:19:22.88#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:19:22.90#ibcon#[25=AT06-04\r\n] 2006.145.05:19:22.93#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:19:22.93#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:19:22.93#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.05:19:22.93#ibcon#ireg 7 cls_cnt 0 2006.145.05:19:22.93#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:19:23.05#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:19:23.05#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:19:23.07#ibcon#[25=USB\r\n] 2006.145.05:19:23.10#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:19:23.10#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:19:23.10#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.05:19:23.10#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.05:19:23.10$vck44/valo=7,864.99 2006.145.05:19:23.10#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.05:19:23.10#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.05:19:23.10#ibcon#ireg 17 cls_cnt 0 2006.145.05:19:23.10#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:19:23.10#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:19:23.10#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:19:23.12#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.05:19:23.16#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:19:23.16#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:19:23.16#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.05:19:23.16#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.05:19:23.16$vck44/va=7,4 2006.145.05:19:23.16#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.05:19:23.16#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.05:19:23.16#ibcon#ireg 11 cls_cnt 2 2006.145.05:19:23.16#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:19:23.22#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:19:23.22#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:19:23.25#ibcon#[25=AT07-04\r\n] 2006.145.05:19:23.27#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:19:23.27#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:19:23.27#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.05:19:23.27#ibcon#ireg 7 cls_cnt 0 2006.145.05:19:23.27#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:19:23.39#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:19:23.39#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:19:23.41#ibcon#[25=USB\r\n] 2006.145.05:19:23.44#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:19:23.44#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:19:23.44#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.05:19:23.44#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.05:19:23.44$vck44/valo=8,884.99 2006.145.05:19:23.44#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.05:19:23.44#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.05:19:23.44#ibcon#ireg 17 cls_cnt 0 2006.145.05:19:23.44#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:19:23.44#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:19:23.44#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:19:23.46#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.05:19:23.50#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:19:23.50#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:19:23.50#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.05:19:23.50#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.05:19:23.50$vck44/va=8,4 2006.145.05:19:23.50#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.05:19:23.50#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.05:19:23.50#ibcon#ireg 11 cls_cnt 2 2006.145.05:19:23.50#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.05:19:23.56#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.05:19:23.56#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.05:19:23.58#ibcon#[25=AT08-04\r\n] 2006.145.05:19:23.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.05:19:23.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.05:19:23.61#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.05:19:23.61#ibcon#ireg 7 cls_cnt 0 2006.145.05:19:23.61#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.05:19:23.73#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.05:19:23.73#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.05:19:23.75#ibcon#[25=USB\r\n] 2006.145.05:19:23.78#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.05:19:23.78#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.05:19:23.78#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.05:19:23.78#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.05:19:23.78$vck44/vblo=1,629.99 2006.145.05:19:23.78#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.05:19:23.78#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.05:19:23.78#ibcon#ireg 17 cls_cnt 0 2006.145.05:19:23.78#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.05:19:23.78#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.05:19:23.78#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.05:19:23.80#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.05:19:23.84#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.05:19:23.84#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.05:19:23.84#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.05:19:23.84#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.05:19:23.84$vck44/vb=1,3 2006.145.05:19:23.84#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.05:19:23.84#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.05:19:23.84#ibcon#ireg 11 cls_cnt 2 2006.145.05:19:23.84#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.05:19:23.84#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.05:19:23.84#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.05:19:23.86#ibcon#[27=AT01-03\r\n] 2006.145.05:19:23.89#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.05:19:23.89#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.05:19:23.89#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.05:19:23.89#ibcon#ireg 7 cls_cnt 0 2006.145.05:19:23.89#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.05:19:24.01#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.05:19:24.01#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.05:19:24.03#ibcon#[27=USB\r\n] 2006.145.05:19:24.06#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.05:19:24.06#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.05:19:24.06#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.05:19:24.06#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.05:19:24.06$vck44/vblo=2,634.99 2006.145.05:19:24.06#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.05:19:24.06#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.05:19:24.06#ibcon#ireg 17 cls_cnt 0 2006.145.05:19:24.06#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.05:19:24.06#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.05:19:24.06#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.05:19:24.08#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.05:19:24.12#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.05:19:24.12#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.05:19:24.12#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.05:19:24.12#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.05:19:24.12$vck44/vb=2,4 2006.145.05:19:24.12#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.05:19:24.12#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.05:19:24.12#ibcon#ireg 11 cls_cnt 2 2006.145.05:19:24.12#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.05:19:24.18#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.05:19:24.18#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.05:19:24.20#ibcon#[27=AT02-04\r\n] 2006.145.05:19:24.23#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.05:19:24.23#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.05:19:24.23#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.05:19:24.23#ibcon#ireg 7 cls_cnt 0 2006.145.05:19:24.23#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.05:19:24.35#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.05:19:24.35#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.05:19:24.37#ibcon#[27=USB\r\n] 2006.145.05:19:24.40#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.05:19:24.40#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.05:19:24.40#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.05:19:24.40#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.05:19:24.40$vck44/vblo=3,649.99 2006.145.05:19:24.40#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.05:19:24.40#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.05:19:24.40#ibcon#ireg 17 cls_cnt 0 2006.145.05:19:24.40#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:19:24.40#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:19:24.40#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:19:24.42#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.05:19:24.46#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:19:24.46#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:19:24.46#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.05:19:24.46#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.05:19:24.46$vck44/vb=3,4 2006.145.05:19:24.46#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.05:19:24.46#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.05:19:24.46#ibcon#ireg 11 cls_cnt 2 2006.145.05:19:24.46#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:19:24.52#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:19:24.52#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:19:24.54#ibcon#[27=AT03-04\r\n] 2006.145.05:19:24.57#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:19:24.57#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:19:24.57#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.05:19:24.57#ibcon#ireg 7 cls_cnt 0 2006.145.05:19:24.57#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:19:24.69#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:19:24.69#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:19:24.71#ibcon#[27=USB\r\n] 2006.145.05:19:24.74#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:19:24.74#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:19:24.74#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.05:19:24.74#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.05:19:24.74$vck44/vblo=4,679.99 2006.145.05:19:24.74#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.05:19:24.74#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.05:19:24.74#ibcon#ireg 17 cls_cnt 0 2006.145.05:19:24.74#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:19:24.74#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:19:24.74#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:19:24.76#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.05:19:24.80#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:19:24.80#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:19:24.80#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.05:19:24.80#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.05:19:24.80$vck44/vb=4,4 2006.145.05:19:24.80#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.05:19:24.80#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.05:19:24.80#ibcon#ireg 11 cls_cnt 2 2006.145.05:19:24.80#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:19:24.86#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:19:24.86#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:19:24.88#ibcon#[27=AT04-04\r\n] 2006.145.05:19:24.91#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:19:24.91#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:19:24.91#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.05:19:24.91#ibcon#ireg 7 cls_cnt 0 2006.145.05:19:24.91#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:19:25.03#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:19:25.03#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:19:25.05#ibcon#[27=USB\r\n] 2006.145.05:19:25.08#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:19:25.08#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:19:25.08#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.05:19:25.08#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.05:19:25.08$vck44/vblo=5,709.99 2006.145.05:19:25.08#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.05:19:25.08#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.05:19:25.08#ibcon#ireg 17 cls_cnt 0 2006.145.05:19:25.08#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:19:25.08#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:19:25.08#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:19:25.10#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.05:19:25.14#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:19:25.14#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:19:25.14#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.05:19:25.14#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.05:19:25.14$vck44/vb=5,4 2006.145.05:19:25.14#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.05:19:25.14#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.05:19:25.14#ibcon#ireg 11 cls_cnt 2 2006.145.05:19:25.14#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:19:25.20#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:19:25.20#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:19:25.22#ibcon#[27=AT05-04\r\n] 2006.145.05:19:25.25#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:19:25.25#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:19:25.25#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.05:19:25.25#ibcon#ireg 7 cls_cnt 0 2006.145.05:19:25.25#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:19:25.37#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:19:25.37#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:19:25.39#ibcon#[27=USB\r\n] 2006.145.05:19:25.40#abcon#<5=/04 4.0 6.9 21.02 571016.4\r\n> 2006.145.05:19:25.42#abcon#{5=INTERFACE CLEAR} 2006.145.05:19:25.42#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:19:25.42#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:19:25.42#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.05:19:25.42#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.05:19:25.42$vck44/vblo=6,719.99 2006.145.05:19:25.42#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.05:19:25.42#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.05:19:25.42#ibcon#ireg 17 cls_cnt 0 2006.145.05:19:25.42#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:19:25.42#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:19:25.42#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:19:25.44#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.05:19:25.48#abcon#[5=S1D000X0/0*\r\n] 2006.145.05:19:25.48#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:19:25.48#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:19:25.48#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.05:19:25.48#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.05:19:25.48$vck44/vb=6,4 2006.145.05:19:25.48#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.05:19:25.48#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.05:19:25.48#ibcon#ireg 11 cls_cnt 2 2006.145.05:19:25.48#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:19:25.54#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:19:25.54#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:19:25.56#ibcon#[27=AT06-04\r\n] 2006.145.05:19:25.59#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:19:25.59#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:19:25.59#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.05:19:25.59#ibcon#ireg 7 cls_cnt 0 2006.145.05:19:25.59#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:19:25.71#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:19:25.71#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:19:25.73#ibcon#[27=USB\r\n] 2006.145.05:19:25.76#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:19:25.76#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:19:25.76#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.05:19:25.76#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.05:19:25.76$vck44/vblo=7,734.99 2006.145.05:19:25.76#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.05:19:25.76#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.05:19:25.76#ibcon#ireg 17 cls_cnt 0 2006.145.05:19:25.76#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:19:25.76#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:19:25.76#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:19:25.78#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.05:19:25.82#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:19:25.82#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:19:25.82#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.05:19:25.82#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.05:19:25.82$vck44/vb=7,4 2006.145.05:19:25.82#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.05:19:25.82#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.05:19:25.82#ibcon#ireg 11 cls_cnt 2 2006.145.05:19:25.82#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:19:25.88#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:19:25.88#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:19:25.90#ibcon#[27=AT07-04\r\n] 2006.145.05:19:25.93#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:19:25.93#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:19:25.93#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.05:19:25.93#ibcon#ireg 7 cls_cnt 0 2006.145.05:19:25.93#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:19:26.05#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:19:26.05#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:19:26.07#ibcon#[27=USB\r\n] 2006.145.05:19:26.10#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:19:26.10#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:19:26.10#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.05:19:26.10#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.05:19:26.10$vck44/vblo=8,744.99 2006.145.05:19:26.10#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.05:19:26.10#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.05:19:26.10#ibcon#ireg 17 cls_cnt 0 2006.145.05:19:26.10#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:19:26.10#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:19:26.10#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:19:26.12#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.05:19:26.16#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:19:26.16#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:19:26.16#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.05:19:26.16#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.05:19:26.16$vck44/vb=8,4 2006.145.05:19:26.16#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.05:19:26.16#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.05:19:26.16#ibcon#ireg 11 cls_cnt 2 2006.145.05:19:26.16#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.05:19:26.22#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.05:19:26.22#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.05:19:26.24#ibcon#[27=AT08-04\r\n] 2006.145.05:19:26.27#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.05:19:26.27#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.05:19:26.27#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.05:19:26.27#ibcon#ireg 7 cls_cnt 0 2006.145.05:19:26.27#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.05:19:26.39#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.05:19:26.39#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.05:19:26.41#ibcon#[27=USB\r\n] 2006.145.05:19:26.44#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.05:19:26.44#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.05:19:26.44#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.05:19:26.44#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.05:19:26.44$vck44/vabw=wide 2006.145.05:19:26.44#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.05:19:26.44#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.05:19:26.44#ibcon#ireg 8 cls_cnt 0 2006.145.05:19:26.44#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.05:19:26.44#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.05:19:26.44#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.05:19:26.46#ibcon#[25=BW32\r\n] 2006.145.05:19:26.49#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.05:19:26.49#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.05:19:26.49#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.05:19:26.49#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.05:19:26.49$vck44/vbbw=wide 2006.145.05:19:26.49#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.05:19:26.49#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.05:19:26.49#ibcon#ireg 8 cls_cnt 0 2006.145.05:19:26.49#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.05:19:26.56#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.05:19:26.56#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.05:19:26.59#ibcon#[27=BW32\r\n] 2006.145.05:19:26.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.05:19:26.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.05:19:26.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.05:19:26.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.05:19:26.62$setupk4/ifdk4 2006.145.05:19:26.62$ifdk4/lo= 2006.145.05:19:26.62$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.05:19:26.62$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.05:19:26.62$ifdk4/patch= 2006.145.05:19:26.62$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.05:19:26.62$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.05:19:26.62$setupk4/!*+20s 2006.145.05:19:35.57#abcon#<5=/04 4.0 6.9 21.02 601016.3\r\n> 2006.145.05:19:35.59#abcon#{5=INTERFACE CLEAR} 2006.145.05:19:35.65#abcon#[5=S1D000X0/0*\r\n] 2006.145.05:19:41.11$setupk4/"tpicd 2006.145.05:19:41.11$setupk4/echo=off 2006.145.05:19:41.11$setupk4/xlog=off 2006.145.05:19:41.11:!2006.145.05:20:10 2006.145.05:19:42.13#trakl#Source acquired 2006.145.05:19:42.13#flagr#flagr/antenna,acquired 2006.145.05:20:10.00:preob 2006.145.05:20:10.13/onsource/TRACKING 2006.145.05:20:10.13:!2006.145.05:20:20 2006.145.05:20:20.00:"tape 2006.145.05:20:20.00:"st=record 2006.145.05:20:20.00:data_valid=on 2006.145.05:20:20.00:midob 2006.145.05:20:21.13/onsource/TRACKING 2006.145.05:20:21.13/wx/21.01,1016.3,58 2006.145.05:20:21.21/cable/+6.5409E-03 2006.145.05:20:22.30/va/01,08,usb,yes,28,30 2006.145.05:20:22.30/va/02,07,usb,yes,30,31 2006.145.05:20:22.30/va/03,08,usb,yes,27,28 2006.145.05:20:22.30/va/04,07,usb,yes,31,33 2006.145.05:20:22.30/va/05,04,usb,yes,27,27 2006.145.05:20:22.30/va/06,04,usb,yes,30,30 2006.145.05:20:22.30/va/07,04,usb,yes,31,32 2006.145.05:20:22.30/va/08,04,usb,yes,26,32 2006.145.05:20:22.53/valo/01,524.99,yes,locked 2006.145.05:20:22.53/valo/02,534.99,yes,locked 2006.145.05:20:22.53/valo/03,564.99,yes,locked 2006.145.05:20:22.53/valo/04,624.99,yes,locked 2006.145.05:20:22.53/valo/05,734.99,yes,locked 2006.145.05:20:22.53/valo/06,814.99,yes,locked 2006.145.05:20:22.53/valo/07,864.99,yes,locked 2006.145.05:20:22.53/valo/08,884.99,yes,locked 2006.145.05:20:23.62/vb/01,03,usb,yes,36,33 2006.145.05:20:23.62/vb/02,04,usb,yes,31,31 2006.145.05:20:23.62/vb/03,04,usb,yes,28,31 2006.145.05:20:23.62/vb/04,04,usb,yes,33,32 2006.145.05:20:23.62/vb/05,04,usb,yes,25,28 2006.145.05:20:23.62/vb/06,04,usb,yes,30,26 2006.145.05:20:23.62/vb/07,04,usb,yes,29,29 2006.145.05:20:23.62/vb/08,04,usb,yes,27,30 2006.145.05:20:23.85/vblo/01,629.99,yes,locked 2006.145.05:20:23.85/vblo/02,634.99,yes,locked 2006.145.05:20:23.85/vblo/03,649.99,yes,locked 2006.145.05:20:23.85/vblo/04,679.99,yes,locked 2006.145.05:20:23.85/vblo/05,709.99,yes,locked 2006.145.05:20:23.85/vblo/06,719.99,yes,locked 2006.145.05:20:23.85/vblo/07,734.99,yes,locked 2006.145.05:20:23.85/vblo/08,744.99,yes,locked 2006.145.05:20:24.00/vabw/8 2006.145.05:20:24.15/vbbw/8 2006.145.05:20:24.25/xfe/off,on,14.2 2006.145.05:20:24.65/ifatt/23,28,28,28 2006.145.05:20:25.07/fmout-gps/S +4.8E-08 2006.145.05:20:25.15:!2006.145.05:23:20 2006.145.05:23:20.01:data_valid=off 2006.145.05:23:20.02:"et 2006.145.05:23:20.02:!+3s 2006.145.05:23:23.03:"tape 2006.145.05:23:23.03:postob 2006.145.05:23:23.14/cable/+6.5406E-03 2006.145.05:23:23.15/wx/21.00,1016.2,59 2006.145.05:23:23.22/fmout-gps/S +4.9E-08 2006.145.05:23:23.22:scan_name=145-0526,jd0605,490 2006.145.05:23:23.22:source=1418+546,141946.60,542314.8,2000.0,cw 2006.145.05:23:24.14#flagr#flagr/antenna,new-source 2006.145.05:23:24.14:checkk5 2006.145.05:23:24.62/chk_autoobs//k5ts1/ autoobs is running! 2006.145.05:23:25.57/chk_autoobs//k5ts2/ autoobs is running! 2006.145.05:23:26.07/chk_autoobs//k5ts3/ autoobs is running! 2006.145.05:23:26.74/chk_autoobs//k5ts4/ autoobs is running! 2006.145.05:23:27.22/chk_obsdata//k5ts1/T1450520??a.dat file size is correct (nominal:720MB, actual:716MB). 2006.145.05:23:28.42/chk_obsdata//k5ts2/T1450520??b.dat file size is correct (nominal:720MB, actual:716MB). 2006.145.05:23:28.87/chk_obsdata//k5ts3/T1450520??c.dat file size is correct (nominal:720MB, actual:716MB). 2006.145.05:23:29.38/chk_obsdata//k5ts4/T1450520??d.dat file size is correct (nominal:720MB, actual:716MB). 2006.145.05:23:30.37/k5log//k5ts1_log_newline 2006.145.05:23:31.20/k5log//k5ts2_log_newline 2006.145.05:23:31.99/k5log//k5ts3_log_newline 2006.145.05:23:32.94/k5log//k5ts4_log_newline 2006.145.05:23:32.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.05:23:32.97:setupk4=1 2006.145.05:23:32.97$setupk4/echo=on 2006.145.05:23:32.97$setupk4/pcalon 2006.145.05:23:32.97$pcalon/"no phase cal control is implemented here 2006.145.05:23:32.97$setupk4/"tpicd=stop 2006.145.05:23:32.97$setupk4/"rec=synch_on 2006.145.05:23:32.97$setupk4/"rec_mode=128 2006.145.05:23:32.97$setupk4/!* 2006.145.05:23:32.97$setupk4/recpk4 2006.145.05:23:32.97$recpk4/recpatch= 2006.145.05:23:32.98$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.05:23:32.98$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.05:23:32.98$setupk4/vck44 2006.145.05:23:32.98$vck44/valo=1,524.99 2006.145.05:23:32.98#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.05:23:32.98#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.05:23:32.98#ibcon#ireg 17 cls_cnt 0 2006.145.05:23:32.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:23:32.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:23:32.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:23:33.01#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.05:23:33.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:23:33.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:23:33.06#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.05:23:33.06#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.05:23:33.06$vck44/va=1,8 2006.145.05:23:33.06#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.05:23:33.06#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.05:23:33.06#ibcon#ireg 11 cls_cnt 2 2006.145.05:23:33.06#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:23:33.06#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:23:33.06#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:23:33.08#ibcon#[25=AT01-08\r\n] 2006.145.05:23:33.11#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:23:33.11#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:23:33.11#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.05:23:33.11#ibcon#ireg 7 cls_cnt 0 2006.145.05:23:33.11#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:23:33.23#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:23:33.23#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:23:33.25#ibcon#[25=USB\r\n] 2006.145.05:23:33.30#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:23:33.30#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:23:33.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.05:23:33.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.05:23:33.30$vck44/valo=2,534.99 2006.145.05:23:33.30#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.05:23:33.30#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.05:23:33.30#ibcon#ireg 17 cls_cnt 0 2006.145.05:23:33.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:23:33.30#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:23:33.30#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:23:33.32#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.05:23:33.36#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:23:33.36#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:23:33.36#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.05:23:33.36#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.05:23:33.42$vck44/va=2,7 2006.145.05:23:33.42#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.05:23:33.42#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.05:23:33.42#ibcon#ireg 11 cls_cnt 2 2006.145.05:23:33.42#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:23:33.42#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:23:33.42#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:23:33.44#ibcon#[25=AT02-07\r\n] 2006.145.05:23:33.47#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:23:33.47#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:23:33.47#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.05:23:33.47#ibcon#ireg 7 cls_cnt 0 2006.145.05:23:33.47#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:23:33.59#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:23:33.59#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:23:33.61#ibcon#[25=USB\r\n] 2006.145.05:23:33.64#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:23:33.64#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:23:33.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.05:23:33.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.05:23:33.64$vck44/valo=3,564.99 2006.145.05:23:33.64#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.05:23:33.64#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.05:23:33.64#ibcon#ireg 17 cls_cnt 0 2006.145.05:23:33.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:23:33.64#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:23:33.64#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:23:33.66#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.05:23:33.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:23:33.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:23:33.70#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.05:23:33.70#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.05:23:33.70$vck44/va=3,8 2006.145.05:23:33.70#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.05:23:33.70#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.05:23:33.70#ibcon#ireg 11 cls_cnt 2 2006.145.05:23:33.70#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:23:33.76#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:23:33.76#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:23:33.78#ibcon#[25=AT03-08\r\n] 2006.145.05:23:33.81#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:23:33.81#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:23:33.81#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.05:23:33.81#ibcon#ireg 7 cls_cnt 0 2006.145.05:23:33.81#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:23:33.93#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:23:33.93#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:23:33.95#ibcon#[25=USB\r\n] 2006.145.05:23:33.98#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:23:33.98#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:23:33.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.05:23:33.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.05:23:33.98$vck44/valo=4,624.99 2006.145.05:23:33.98#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.05:23:33.98#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.05:23:33.98#ibcon#ireg 17 cls_cnt 0 2006.145.05:23:33.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:23:33.98#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:23:33.98#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:23:34.00#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.05:23:34.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:23:34.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:23:34.04#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.05:23:34.04#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.05:23:34.04$vck44/va=4,7 2006.145.05:23:34.04#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.05:23:34.04#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.05:23:34.04#ibcon#ireg 11 cls_cnt 2 2006.145.05:23:34.04#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:23:34.10#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:23:34.10#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:23:34.12#ibcon#[25=AT04-07\r\n] 2006.145.05:23:34.15#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:23:34.15#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:23:34.15#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.05:23:34.15#ibcon#ireg 7 cls_cnt 0 2006.145.05:23:34.15#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:23:34.27#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:23:34.27#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:23:34.29#ibcon#[25=USB\r\n] 2006.145.05:23:34.32#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:23:34.32#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:23:34.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.05:23:34.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.05:23:34.32$vck44/valo=5,734.99 2006.145.05:23:34.32#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.05:23:34.32#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.05:23:34.32#ibcon#ireg 17 cls_cnt 0 2006.145.05:23:34.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:23:34.32#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:23:34.32#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:23:34.34#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.05:23:34.38#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:23:34.38#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:23:34.38#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.05:23:34.38#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.05:23:34.38$vck44/va=5,4 2006.145.05:23:34.38#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.05:23:34.38#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.05:23:34.38#ibcon#ireg 11 cls_cnt 2 2006.145.05:23:34.38#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.05:23:34.44#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.05:23:34.44#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.05:23:34.46#ibcon#[25=AT05-04\r\n] 2006.145.05:23:34.49#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.05:23:34.49#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.05:23:34.49#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.05:23:34.49#ibcon#ireg 7 cls_cnt 0 2006.145.05:23:34.49#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.05:23:34.61#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.05:23:34.61#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.05:23:34.63#ibcon#[25=USB\r\n] 2006.145.05:23:34.66#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.05:23:34.66#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.05:23:34.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.05:23:34.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.05:23:34.66$vck44/valo=6,814.99 2006.145.05:23:34.66#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.05:23:34.66#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.05:23:34.66#ibcon#ireg 17 cls_cnt 0 2006.145.05:23:34.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:23:34.66#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:23:34.66#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:23:34.68#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.05:23:34.72#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:23:34.72#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:23:34.72#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.05:23:34.72#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.05:23:34.72$vck44/va=6,4 2006.145.05:23:34.72#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.05:23:34.72#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.05:23:34.72#ibcon#ireg 11 cls_cnt 2 2006.145.05:23:34.72#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:23:34.78#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:23:34.78#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:23:34.80#ibcon#[25=AT06-04\r\n] 2006.145.05:23:34.83#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:23:34.83#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:23:34.83#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.05:23:34.83#ibcon#ireg 7 cls_cnt 0 2006.145.05:23:34.83#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:23:34.95#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:23:34.95#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:23:34.97#ibcon#[25=USB\r\n] 2006.145.05:23:35.00#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:23:35.00#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:23:35.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.05:23:35.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.05:23:35.00$vck44/valo=7,864.99 2006.145.05:23:35.00#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.05:23:35.00#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.05:23:35.00#ibcon#ireg 17 cls_cnt 0 2006.145.05:23:35.00#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:23:35.00#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:23:35.00#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:23:35.02#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.05:23:35.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:23:35.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:23:35.06#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.05:23:35.06#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.05:23:35.06$vck44/va=7,4 2006.145.05:23:35.06#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.05:23:35.06#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.05:23:35.06#ibcon#ireg 11 cls_cnt 2 2006.145.05:23:35.06#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:23:35.12#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:23:35.12#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:23:35.14#ibcon#[25=AT07-04\r\n] 2006.145.05:23:35.17#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:23:35.17#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:23:35.17#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.05:23:35.17#ibcon#ireg 7 cls_cnt 0 2006.145.05:23:35.17#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:23:35.29#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:23:35.29#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:23:35.31#ibcon#[25=USB\r\n] 2006.145.05:23:35.34#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:23:35.34#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:23:35.34#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.05:23:35.34#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.05:23:35.34$vck44/valo=8,884.99 2006.145.05:23:35.34#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.05:23:35.34#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.05:23:35.34#ibcon#ireg 17 cls_cnt 0 2006.145.05:23:35.34#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:23:35.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:23:35.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:23:35.36#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.05:23:35.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:23:35.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:23:35.40#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.05:23:35.40#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.05:23:35.40$vck44/va=8,4 2006.145.05:23:35.40#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.05:23:35.40#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.05:23:35.40#ibcon#ireg 11 cls_cnt 2 2006.145.05:23:35.40#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:23:35.46#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:23:35.46#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:23:35.48#ibcon#[25=AT08-04\r\n] 2006.145.05:23:35.51#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:23:35.51#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:23:35.51#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.05:23:35.51#ibcon#ireg 7 cls_cnt 0 2006.145.05:23:35.51#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:23:35.63#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:23:35.63#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:23:35.65#ibcon#[25=USB\r\n] 2006.145.05:23:35.68#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:23:35.68#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:23:35.68#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.05:23:35.68#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.05:23:35.68$vck44/vblo=1,629.99 2006.145.05:23:35.68#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.05:23:35.68#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.05:23:35.68#ibcon#ireg 17 cls_cnt 0 2006.145.05:23:35.68#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:23:35.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:23:35.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:23:35.70#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.05:23:35.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:23:35.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:23:35.74#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.05:23:35.74#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.05:23:35.74$vck44/vb=1,3 2006.145.05:23:35.74#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.05:23:35.74#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.05:23:35.74#ibcon#ireg 11 cls_cnt 2 2006.145.05:23:35.74#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:23:35.74#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:23:35.74#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:23:35.76#ibcon#[27=AT01-03\r\n] 2006.145.05:23:35.79#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:23:35.79#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:23:35.79#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.05:23:35.79#ibcon#ireg 7 cls_cnt 0 2006.145.05:23:35.79#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:23:35.91#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:23:35.91#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:23:35.93#ibcon#[27=USB\r\n] 2006.145.05:23:35.96#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:23:35.96#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:23:35.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.05:23:35.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.05:23:35.96$vck44/vblo=2,634.99 2006.145.05:23:35.96#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.05:23:35.96#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.05:23:35.96#ibcon#ireg 17 cls_cnt 0 2006.145.05:23:35.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:23:35.96#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:23:35.96#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:23:35.98#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.05:23:36.02#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:23:36.02#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:23:36.02#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.05:23:36.02#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.05:23:36.02$vck44/vb=2,4 2006.145.05:23:36.02#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.05:23:36.02#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.05:23:36.02#ibcon#ireg 11 cls_cnt 2 2006.145.05:23:36.02#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:23:36.08#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:23:36.08#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:23:36.10#ibcon#[27=AT02-04\r\n] 2006.145.05:23:36.13#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:23:36.13#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:23:36.13#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.05:23:36.13#ibcon#ireg 7 cls_cnt 0 2006.145.05:23:36.13#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:23:36.25#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:23:36.25#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:23:36.27#ibcon#[27=USB\r\n] 2006.145.05:23:36.30#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:23:36.30#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:23:36.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.05:23:36.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.05:23:36.30$vck44/vblo=3,649.99 2006.145.05:23:36.30#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.05:23:36.30#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.05:23:36.30#ibcon#ireg 17 cls_cnt 0 2006.145.05:23:36.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:23:36.30#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:23:36.30#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:23:36.32#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.05:23:36.36#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:23:36.36#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:23:36.36#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.05:23:36.36#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.05:23:36.36$vck44/vb=3,4 2006.145.05:23:36.36#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.05:23:36.36#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.05:23:36.36#ibcon#ireg 11 cls_cnt 2 2006.145.05:23:36.36#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:23:36.42#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:23:36.42#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:23:36.44#ibcon#[27=AT03-04\r\n] 2006.145.05:23:36.47#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:23:36.47#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:23:36.47#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.05:23:36.47#ibcon#ireg 7 cls_cnt 0 2006.145.05:23:36.47#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:23:36.59#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:23:36.59#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:23:36.61#ibcon#[27=USB\r\n] 2006.145.05:23:36.64#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:23:36.64#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:23:36.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.05:23:36.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.05:23:36.64$vck44/vblo=4,679.99 2006.145.05:23:36.64#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.05:23:36.64#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.05:23:36.64#ibcon#ireg 17 cls_cnt 0 2006.145.05:23:36.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:23:36.64#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:23:36.64#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:23:36.66#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.05:23:36.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:23:36.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:23:36.70#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.05:23:36.70#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.05:23:36.70$vck44/vb=4,4 2006.145.05:23:36.70#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.05:23:36.70#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.05:23:36.70#ibcon#ireg 11 cls_cnt 2 2006.145.05:23:36.70#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:23:36.76#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:23:36.76#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:23:36.78#ibcon#[27=AT04-04\r\n] 2006.145.05:23:36.81#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:23:36.81#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:23:36.81#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.05:23:36.81#ibcon#ireg 7 cls_cnt 0 2006.145.05:23:36.81#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:23:36.93#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:23:36.93#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:23:36.95#ibcon#[27=USB\r\n] 2006.145.05:23:36.98#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:23:36.98#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:23:36.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.05:23:36.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.05:23:36.98$vck44/vblo=5,709.99 2006.145.05:23:36.98#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.05:23:36.98#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.05:23:36.98#ibcon#ireg 17 cls_cnt 0 2006.145.05:23:36.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:23:36.98#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:23:36.98#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:23:37.00#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.05:23:37.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:23:37.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:23:37.04#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.05:23:37.04#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.05:23:37.04$vck44/vb=5,4 2006.145.05:23:37.04#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.05:23:37.04#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.05:23:37.04#ibcon#ireg 11 cls_cnt 2 2006.145.05:23:37.04#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:23:37.10#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:23:37.10#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:23:37.12#ibcon#[27=AT05-04\r\n] 2006.145.05:23:37.15#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:23:37.15#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:23:37.15#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.05:23:37.15#ibcon#ireg 7 cls_cnt 0 2006.145.05:23:37.15#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:23:37.27#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:23:37.27#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:23:37.29#ibcon#[27=USB\r\n] 2006.145.05:23:37.32#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:23:37.32#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:23:37.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.05:23:37.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.05:23:37.32$vck44/vblo=6,719.99 2006.145.05:23:37.32#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.05:23:37.32#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.05:23:37.32#ibcon#ireg 17 cls_cnt 0 2006.145.05:23:37.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:23:37.32#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:23:37.32#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:23:37.34#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.05:23:37.38#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:23:37.38#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:23:37.38#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.05:23:37.38#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.05:23:37.38$vck44/vb=6,4 2006.145.05:23:37.38#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.05:23:37.38#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.05:23:37.38#ibcon#ireg 11 cls_cnt 2 2006.145.05:23:37.38#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.05:23:37.44#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.05:23:37.44#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.05:23:37.46#ibcon#[27=AT06-04\r\n] 2006.145.05:23:37.49#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.05:23:37.49#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.05:23:37.49#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.05:23:37.49#ibcon#ireg 7 cls_cnt 0 2006.145.05:23:37.49#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.05:23:37.61#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.05:23:37.61#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.05:23:37.63#ibcon#[27=USB\r\n] 2006.145.05:23:37.66#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.05:23:37.66#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.05:23:37.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.05:23:37.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.05:23:37.66$vck44/vblo=7,734.99 2006.145.05:23:37.66#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.05:23:37.66#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.05:23:37.66#ibcon#ireg 17 cls_cnt 0 2006.145.05:23:37.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:23:37.66#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:23:37.66#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:23:37.68#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.05:23:37.72#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:23:37.72#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:23:37.72#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.05:23:37.72#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.05:23:37.72$vck44/vb=7,4 2006.145.05:23:37.72#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.05:23:37.72#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.05:23:37.72#ibcon#ireg 11 cls_cnt 2 2006.145.05:23:37.72#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:23:37.78#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:23:37.78#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:23:37.80#ibcon#[27=AT07-04\r\n] 2006.145.05:23:37.83#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:23:37.83#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:23:37.83#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.05:23:37.83#ibcon#ireg 7 cls_cnt 0 2006.145.05:23:37.83#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:23:37.95#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:23:37.95#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:23:37.97#ibcon#[27=USB\r\n] 2006.145.05:23:38.00#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:23:38.00#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:23:38.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.05:23:38.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.05:23:38.00$vck44/vblo=8,744.99 2006.145.05:23:38.00#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.05:23:38.00#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.05:23:38.00#ibcon#ireg 17 cls_cnt 0 2006.145.05:23:38.00#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:23:38.00#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:23:38.00#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:23:38.02#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.05:23:38.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:23:38.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:23:38.06#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.05:23:38.06#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.05:23:38.06$vck44/vb=8,4 2006.145.05:23:38.06#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.05:23:38.06#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.05:23:38.06#ibcon#ireg 11 cls_cnt 2 2006.145.05:23:38.06#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:23:38.12#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:23:38.12#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:23:38.14#ibcon#[27=AT08-04\r\n] 2006.145.05:23:38.17#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:23:38.17#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:23:38.17#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.05:23:38.17#ibcon#ireg 7 cls_cnt 0 2006.145.05:23:38.17#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:23:38.29#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:23:38.29#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:23:38.31#ibcon#[27=USB\r\n] 2006.145.05:23:38.36#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:23:38.36#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:23:38.36#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.05:23:38.36#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.05:23:38.36$vck44/vabw=wide 2006.145.05:23:38.36#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.05:23:38.36#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.05:23:38.36#ibcon#ireg 8 cls_cnt 0 2006.145.05:23:38.36#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:23:38.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:23:38.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:23:38.37#ibcon#[25=BW32\r\n] 2006.145.05:23:38.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:23:38.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:23:38.40#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.05:23:38.40#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.05:23:38.40$vck44/vbbw=wide 2006.145.05:23:38.40#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.05:23:38.40#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.05:23:38.40#ibcon#ireg 8 cls_cnt 0 2006.145.05:23:38.40#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.05:23:38.48#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.05:23:38.48#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.05:23:38.50#ibcon#[27=BW32\r\n] 2006.145.05:23:38.53#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.05:23:38.53#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.05:23:38.53#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.05:23:38.53#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.05:23:38.53$setupk4/ifdk4 2006.145.05:23:38.53$ifdk4/lo= 2006.145.05:23:38.53$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.05:23:38.53$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.05:23:38.53$ifdk4/patch= 2006.145.05:23:38.53$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.05:23:38.53$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.05:23:38.53$setupk4/!*+20s 2006.145.05:23:39.74#abcon#<5=/05 4.0 7.3 21.01 611016.2\r\n> 2006.145.05:23:39.76#abcon#{5=INTERFACE CLEAR} 2006.145.05:23:39.82#abcon#[5=S1D000X0/0*\r\n] 2006.145.05:23:46.14#trakl#Source acquired 2006.145.05:23:47.14#flagr#flagr/antenna,acquired 2006.145.05:23:49.91#abcon#<5=/05 4.0 7.2 21.01 591016.2\r\n> 2006.145.05:23:49.93#abcon#{5=INTERFACE CLEAR} 2006.145.05:23:49.99#abcon#[5=S1D000X0/0*\r\n] 2006.145.05:23:52.98$setupk4/"tpicd 2006.145.05:23:52.98$setupk4/echo=off 2006.145.05:23:52.98$setupk4/xlog=off 2006.145.05:23:52.98:!2006.145.05:26:06 2006.145.05:26:06.00:preob 2006.145.05:26:06.14/onsource/TRACKING 2006.145.05:26:06.14:!2006.145.05:26:16 2006.145.05:26:16.00:"tape 2006.145.05:26:16.00:"st=record 2006.145.05:26:16.00:data_valid=on 2006.145.05:26:16.00:midob 2006.145.05:26:17.14/onsource/TRACKING 2006.145.05:26:17.14/wx/21.02,1016.2,57 2006.145.05:26:17.37/cable/+6.5407E-03 2006.145.05:26:18.46/va/01,08,usb,yes,30,32 2006.145.05:26:18.46/va/02,07,usb,yes,32,33 2006.145.05:26:18.46/va/03,08,usb,yes,29,30 2006.145.05:26:18.46/va/04,07,usb,yes,33,35 2006.145.05:26:18.46/va/05,04,usb,yes,29,29 2006.145.05:26:18.46/va/06,04,usb,yes,33,32 2006.145.05:26:18.46/va/07,04,usb,yes,33,34 2006.145.05:26:18.46/va/08,04,usb,yes,28,34 2006.145.05:26:18.69/valo/01,524.99,yes,locked 2006.145.05:26:18.69/valo/02,534.99,yes,locked 2006.145.05:26:18.69/valo/03,564.99,yes,locked 2006.145.05:26:18.69/valo/04,624.99,yes,locked 2006.145.05:26:18.69/valo/05,734.99,yes,locked 2006.145.05:26:18.69/valo/06,814.99,yes,locked 2006.145.05:26:18.69/valo/07,864.99,yes,locked 2006.145.05:26:18.69/valo/08,884.99,yes,locked 2006.145.05:26:19.78/vb/01,03,usb,yes,37,34 2006.145.05:26:19.78/vb/02,04,usb,yes,32,32 2006.145.05:26:19.78/vb/03,04,usb,yes,29,32 2006.145.05:26:19.78/vb/04,04,usb,yes,34,33 2006.145.05:26:19.78/vb/05,04,usb,yes,26,29 2006.145.05:26:19.78/vb/06,04,usb,yes,31,27 2006.145.05:26:19.78/vb/07,04,usb,yes,30,30 2006.145.05:26:19.78/vb/08,04,usb,yes,28,31 2006.145.05:26:20.01/vblo/01,629.99,yes,locked 2006.145.05:26:20.01/vblo/02,634.99,yes,locked 2006.145.05:26:20.01/vblo/03,649.99,yes,locked 2006.145.05:26:20.01/vblo/04,679.99,yes,locked 2006.145.05:26:20.01/vblo/05,709.99,yes,locked 2006.145.05:26:20.01/vblo/06,719.99,yes,locked 2006.145.05:26:20.01/vblo/07,734.99,yes,locked 2006.145.05:26:20.01/vblo/08,744.99,yes,locked 2006.145.05:26:20.16/vabw/8 2006.145.05:26:20.31/vbbw/8 2006.145.05:26:20.40/xfe/off,on,15.2 2006.145.05:26:20.77/ifatt/23,28,28,28 2006.145.05:26:21.07/fmout-gps/S +4.8E-08 2006.145.05:26:21.11:!2006.145.05:34:26 2006.145.05:30:12.14#trakl#Off source 2006.145.05:30:12.14?ERROR st -7 Antenna off-source! 2006.145.05:30:12.14#trakl#az 35.375 el 18.667 azerr*cos(el) 0.0194 elerr 0.0027 2006.145.05:30:12.14#flagr#flagr/antenna,off-source 2006.145.05:30:19.14#trakl#Source re-acquired 2006.145.05:30:21.14#flagr#flagr/antenna,re-acquired 2006.145.05:34:26.00:data_valid=off 2006.145.05:34:26.00:"et 2006.145.05:34:26.01:!+3s 2006.145.05:34:29.02:"tape 2006.145.05:34:29.02:postob 2006.145.05:34:29.09/cable/+6.5407E-03 2006.145.05:34:29.10/wx/20.97,1016.2,58 2006.145.05:34:30.08/fmout-gps/S +4.8E-08 2006.145.05:34:30.08:scan_name=145-0536,jd0605,50 2006.145.05:34:30.09:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.145.05:34:31.14#flagr#flagr/antenna,new-source 2006.145.05:34:31.14:checkk5 2006.145.05:34:31.63/chk_autoobs//k5ts1/ autoobs is running! 2006.145.05:34:32.07/chk_autoobs//k5ts2/ autoobs is running! 2006.145.05:34:32.57/chk_autoobs//k5ts3/ autoobs is running! 2006.145.05:34:33.04/chk_autoobs//k5ts4/ autoobs is running! 2006.145.05:34:33.49/chk_obsdata//k5ts1/T1450526??a.dat file size is correct (nominal:1960MB, actual:1956MB). 2006.145.05:34:34.17/chk_obsdata//k5ts2/T1450526??b.dat file size is correct (nominal:1960MB, actual:1956MB). 2006.145.05:34:34.68/chk_obsdata//k5ts3/T1450526??c.dat file size is correct (nominal:1960MB, actual:1956MB). 2006.145.05:34:35.14/chk_obsdata//k5ts4/T1450526??d.dat file size is correct (nominal:1960MB, actual:1956MB). 2006.145.05:34:35.99/k5log//k5ts1_log_newline 2006.145.05:34:36.81/k5log//k5ts2_log_newline 2006.145.05:34:37.64/k5log//k5ts3_log_newline 2006.145.05:34:38.54/k5log//k5ts4_log_newline 2006.145.05:34:38.57/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.05:34:38.57:setupk4=1 2006.145.05:34:38.57$setupk4/echo=on 2006.145.05:34:38.57$setupk4/pcalon 2006.145.05:34:38.57$pcalon/"no phase cal control is implemented here 2006.145.05:34:38.57$setupk4/"tpicd=stop 2006.145.05:34:38.57$setupk4/"rec=synch_on 2006.145.05:34:38.57$setupk4/"rec_mode=128 2006.145.05:34:38.57$setupk4/!* 2006.145.05:34:38.57$setupk4/recpk4 2006.145.05:34:38.57$recpk4/recpatch= 2006.145.05:34:38.57$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.05:34:38.57$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.05:34:38.57$setupk4/vck44 2006.145.05:34:38.57$vck44/valo=1,524.99 2006.145.05:34:38.57#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.05:34:38.57#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.05:34:38.57#ibcon#ireg 17 cls_cnt 0 2006.145.05:34:38.57#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.05:34:38.57#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.05:34:38.57#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.05:34:38.61#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.05:34:38.66#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.05:34:38.66#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.05:34:38.66#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.05:34:38.66#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.05:34:38.66$vck44/va=1,8 2006.145.05:34:38.66#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.05:34:38.66#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.05:34:38.66#ibcon#ireg 11 cls_cnt 2 2006.145.05:34:38.66#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.05:34:38.66#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.05:34:38.66#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.05:34:38.68#ibcon#[25=AT01-08\r\n] 2006.145.05:34:38.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.05:34:38.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.05:34:38.71#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.05:34:38.71#ibcon#ireg 7 cls_cnt 0 2006.145.05:34:38.71#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.05:34:38.83#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.05:34:38.83#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.05:34:38.85#ibcon#[25=USB\r\n] 2006.145.05:34:38.88#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.05:34:38.88#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.05:34:38.88#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.05:34:38.88#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.05:34:38.88$vck44/valo=2,534.99 2006.145.05:34:38.88#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.05:34:38.88#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.05:34:38.88#ibcon#ireg 17 cls_cnt 0 2006.145.05:34:38.88#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:34:38.88#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:34:38.88#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:34:38.90#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.05:34:38.94#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:34:38.94#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:34:38.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.05:34:38.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.05:34:38.94$vck44/va=2,7 2006.145.05:34:38.94#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.05:34:38.94#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.05:34:38.94#ibcon#ireg 11 cls_cnt 2 2006.145.05:34:38.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:34:39.00#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:34:39.00#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:34:39.02#ibcon#[25=AT02-07\r\n] 2006.145.05:34:39.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:34:39.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:34:39.05#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.05:34:39.05#ibcon#ireg 7 cls_cnt 0 2006.145.05:34:39.05#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:34:39.17#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:34:39.17#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:34:39.22#ibcon#[25=USB\r\n] 2006.145.05:34:39.25#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:34:39.25#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:34:39.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.05:34:39.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.05:34:39.25$vck44/valo=3,564.99 2006.145.05:34:39.25#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.05:34:39.25#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.05:34:39.25#ibcon#ireg 17 cls_cnt 0 2006.145.05:34:39.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:34:39.25#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:34:39.25#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:34:39.27#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.05:34:39.31#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:34:39.31#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:34:39.31#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.05:34:39.31#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.05:34:39.31$vck44/va=3,8 2006.145.05:34:39.31#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.05:34:39.31#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.05:34:39.31#ibcon#ireg 11 cls_cnt 2 2006.145.05:34:39.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:34:39.37#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:34:39.37#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:34:39.39#ibcon#[25=AT03-08\r\n] 2006.145.05:34:39.42#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:34:39.42#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:34:39.42#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.05:34:39.42#ibcon#ireg 7 cls_cnt 0 2006.145.05:34:39.42#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:34:39.54#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:34:39.54#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:34:39.56#ibcon#[25=USB\r\n] 2006.145.05:34:39.59#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:34:39.59#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:34:39.59#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.05:34:39.59#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.05:34:39.59$vck44/valo=4,624.99 2006.145.05:34:39.59#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.05:34:39.59#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.05:34:39.59#ibcon#ireg 17 cls_cnt 0 2006.145.05:34:39.59#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:34:39.59#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:34:39.59#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:34:39.61#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.05:34:39.65#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:34:39.65#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:34:39.65#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.05:34:39.65#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.05:34:39.65$vck44/va=4,7 2006.145.05:34:39.65#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.05:34:39.65#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.05:34:39.65#ibcon#ireg 11 cls_cnt 2 2006.145.05:34:39.65#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:34:39.71#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:34:39.71#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:34:39.73#ibcon#[25=AT04-07\r\n] 2006.145.05:34:39.76#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:34:39.76#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:34:39.76#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.05:34:39.76#ibcon#ireg 7 cls_cnt 0 2006.145.05:34:39.76#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:34:39.88#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:34:39.88#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:34:39.90#ibcon#[25=USB\r\n] 2006.145.05:34:39.93#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:34:39.93#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:34:39.93#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.05:34:39.93#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.05:34:39.93$vck44/valo=5,734.99 2006.145.05:34:39.93#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.05:34:39.93#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.05:34:39.93#ibcon#ireg 17 cls_cnt 0 2006.145.05:34:39.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.05:34:39.93#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.05:34:39.93#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.05:34:39.95#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.05:34:39.99#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.05:34:39.99#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.05:34:39.99#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.05:34:39.99#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.05:34:39.99$vck44/va=5,4 2006.145.05:34:39.99#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.05:34:39.99#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.05:34:39.99#ibcon#ireg 11 cls_cnt 2 2006.145.05:34:39.99#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.05:34:40.05#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.05:34:40.05#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.05:34:40.07#ibcon#[25=AT05-04\r\n] 2006.145.05:34:40.10#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.05:34:40.10#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.05:34:40.10#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.05:34:40.10#ibcon#ireg 7 cls_cnt 0 2006.145.05:34:40.10#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.05:34:40.22#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.05:34:40.22#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.05:34:40.24#ibcon#[25=USB\r\n] 2006.145.05:34:40.27#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.05:34:40.27#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.05:34:40.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.05:34:40.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.05:34:40.27$vck44/valo=6,814.99 2006.145.05:34:40.27#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.05:34:40.27#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.05:34:40.27#ibcon#ireg 17 cls_cnt 0 2006.145.05:34:40.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.05:34:40.27#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.05:34:40.27#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.05:34:40.29#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.05:34:40.33#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.05:34:40.33#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.05:34:40.33#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.05:34:40.33#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.05:34:40.33$vck44/va=6,4 2006.145.05:34:40.33#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.05:34:40.33#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.05:34:40.33#ibcon#ireg 11 cls_cnt 2 2006.145.05:34:40.33#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:34:40.39#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:34:40.39#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:34:40.41#ibcon#[25=AT06-04\r\n] 2006.145.05:34:40.44#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:34:40.44#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:34:40.44#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.05:34:40.44#ibcon#ireg 7 cls_cnt 0 2006.145.05:34:40.44#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:34:40.56#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:34:40.56#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:34:40.58#ibcon#[25=USB\r\n] 2006.145.05:34:40.61#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:34:40.61#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:34:40.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.05:34:40.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.05:34:40.61$vck44/valo=7,864.99 2006.145.05:34:40.61#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.05:34:40.61#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.05:34:40.61#ibcon#ireg 17 cls_cnt 0 2006.145.05:34:40.61#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:34:40.61#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:34:40.61#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:34:40.63#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.05:34:40.67#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:34:40.67#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:34:40.67#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.05:34:40.67#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.05:34:40.67$vck44/va=7,4 2006.145.05:34:40.67#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.05:34:40.67#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.05:34:40.67#ibcon#ireg 11 cls_cnt 2 2006.145.05:34:40.67#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:34:40.73#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:34:40.73#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:34:40.75#ibcon#[25=AT07-04\r\n] 2006.145.05:34:40.78#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:34:40.78#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:34:40.78#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.05:34:40.78#ibcon#ireg 7 cls_cnt 0 2006.145.05:34:40.78#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:34:40.90#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:34:40.90#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:34:40.92#ibcon#[25=USB\r\n] 2006.145.05:34:40.95#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:34:40.95#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:34:40.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.05:34:40.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.05:34:40.95$vck44/valo=8,884.99 2006.145.05:34:40.95#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.05:34:40.95#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.05:34:40.95#ibcon#ireg 17 cls_cnt 0 2006.145.05:34:40.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:34:40.95#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:34:40.95#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:34:40.97#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.05:34:41.01#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:34:41.01#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:34:41.01#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.05:34:41.01#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.05:34:41.01$vck44/va=8,4 2006.145.05:34:41.01#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.05:34:41.01#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.05:34:41.01#ibcon#ireg 11 cls_cnt 2 2006.145.05:34:41.01#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.05:34:41.02#abcon#<5=/05 4.5 7.2 20.96 561016.2\r\n> 2006.145.05:34:41.04#abcon#{5=INTERFACE CLEAR} 2006.145.05:34:41.07#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.05:34:41.07#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.05:34:41.09#ibcon#[25=AT08-04\r\n] 2006.145.05:34:41.10#abcon#[5=S1D000X0/0*\r\n] 2006.145.05:34:41.12#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.05:34:41.12#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.05:34:41.12#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.05:34:41.12#ibcon#ireg 7 cls_cnt 0 2006.145.05:34:41.12#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.05:34:41.24#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.05:34:41.24#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.05:34:41.26#ibcon#[25=USB\r\n] 2006.145.05:34:41.29#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.05:34:41.29#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.05:34:41.29#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.05:34:41.29#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.05:34:41.29$vck44/vblo=1,629.99 2006.145.05:34:41.29#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.05:34:41.29#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.05:34:41.29#ibcon#ireg 17 cls_cnt 0 2006.145.05:34:41.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.05:34:41.29#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.05:34:41.29#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.05:34:41.31#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.05:34:41.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.05:34:41.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.05:34:41.35#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.05:34:41.35#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.05:34:41.35$vck44/vb=1,3 2006.145.05:34:41.35#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.05:34:41.35#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.05:34:41.35#ibcon#ireg 11 cls_cnt 2 2006.145.05:34:41.35#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.05:34:41.35#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.05:34:41.35#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.05:34:41.37#ibcon#[27=AT01-03\r\n] 2006.145.05:34:41.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.05:34:41.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.05:34:41.40#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.05:34:41.40#ibcon#ireg 7 cls_cnt 0 2006.145.05:34:41.40#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.05:34:41.52#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.05:34:41.52#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.05:34:41.54#ibcon#[27=USB\r\n] 2006.145.05:34:41.57#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.05:34:41.57#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.05:34:41.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.05:34:41.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.05:34:41.57$vck44/vblo=2,634.99 2006.145.05:34:41.57#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.05:34:41.57#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.05:34:41.57#ibcon#ireg 17 cls_cnt 0 2006.145.05:34:41.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:34:41.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:34:41.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:34:41.59#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.05:34:41.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:34:41.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:34:41.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.05:34:41.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.05:34:41.63$vck44/vb=2,4 2006.145.05:34:41.63#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.05:34:41.63#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.05:34:41.63#ibcon#ireg 11 cls_cnt 2 2006.145.05:34:41.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:34:41.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:34:41.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:34:41.71#ibcon#[27=AT02-04\r\n] 2006.145.05:34:41.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:34:41.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:34:41.74#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.05:34:41.74#ibcon#ireg 7 cls_cnt 0 2006.145.05:34:41.74#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:34:41.86#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:34:41.86#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:34:41.88#ibcon#[27=USB\r\n] 2006.145.05:34:41.91#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:34:41.91#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:34:41.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.05:34:41.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.05:34:41.91$vck44/vblo=3,649.99 2006.145.05:34:41.91#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.05:34:41.91#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.05:34:41.91#ibcon#ireg 17 cls_cnt 0 2006.145.05:34:41.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:34:41.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:34:41.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:34:41.93#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.05:34:41.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:34:41.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.05:34:41.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.05:34:41.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.05:34:41.97$vck44/vb=3,4 2006.145.05:34:41.97#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.05:34:41.97#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.05:34:41.97#ibcon#ireg 11 cls_cnt 2 2006.145.05:34:41.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:34:42.03#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:34:42.03#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:34:42.05#ibcon#[27=AT03-04\r\n] 2006.145.05:34:42.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:34:42.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.05:34:42.08#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.05:34:42.08#ibcon#ireg 7 cls_cnt 0 2006.145.05:34:42.08#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:34:42.20#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:34:42.20#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:34:42.22#ibcon#[27=USB\r\n] 2006.145.05:34:42.25#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:34:42.25#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.05:34:42.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.05:34:42.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.05:34:42.25$vck44/vblo=4,679.99 2006.145.05:34:42.25#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.05:34:42.25#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.05:34:42.25#ibcon#ireg 17 cls_cnt 0 2006.145.05:34:42.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:34:42.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:34:42.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:34:42.27#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.05:34:42.31#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:34:42.31#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.05:34:42.31#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.05:34:42.31#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.05:34:42.31$vck44/vb=4,4 2006.145.05:34:42.31#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.05:34:42.31#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.05:34:42.31#ibcon#ireg 11 cls_cnt 2 2006.145.05:34:42.31#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:34:42.37#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:34:42.37#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:34:42.39#ibcon#[27=AT04-04\r\n] 2006.145.05:34:42.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:34:42.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.05:34:42.42#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.05:34:42.42#ibcon#ireg 7 cls_cnt 0 2006.145.05:34:42.42#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:34:42.54#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:34:42.54#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:34:42.56#ibcon#[27=USB\r\n] 2006.145.05:34:42.59#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:34:42.59#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.05:34:42.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.05:34:42.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.05:34:42.59$vck44/vblo=5,709.99 2006.145.05:34:42.59#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.05:34:42.59#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.05:34:42.59#ibcon#ireg 17 cls_cnt 0 2006.145.05:34:42.59#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.05:34:42.59#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.05:34:42.59#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.05:34:42.61#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.05:34:42.65#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.05:34:42.65#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.05:34:42.65#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.05:34:42.65#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.05:34:42.65$vck44/vb=5,4 2006.145.05:34:42.65#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.05:34:42.65#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.05:34:42.65#ibcon#ireg 11 cls_cnt 2 2006.145.05:34:42.65#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.05:34:42.71#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.05:34:42.71#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.05:34:42.73#ibcon#[27=AT05-04\r\n] 2006.145.05:34:42.76#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.05:34:42.76#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.05:34:42.76#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.05:34:42.76#ibcon#ireg 7 cls_cnt 0 2006.145.05:34:42.76#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.05:34:42.88#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.05:34:42.88#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.05:34:42.90#ibcon#[27=USB\r\n] 2006.145.05:34:42.93#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.05:34:42.93#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.05:34:42.93#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.05:34:42.93#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.05:34:42.93$vck44/vblo=6,719.99 2006.145.05:34:42.93#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.05:34:42.93#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.05:34:42.93#ibcon#ireg 17 cls_cnt 0 2006.145.05:34:42.93#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.05:34:42.93#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.05:34:42.93#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.05:34:42.95#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.05:34:42.99#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.05:34:42.99#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.05:34:42.99#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.05:34:42.99#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.05:34:42.99$vck44/vb=6,4 2006.145.05:34:42.99#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.05:34:42.99#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.05:34:42.99#ibcon#ireg 11 cls_cnt 2 2006.145.05:34:42.99#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:34:43.05#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:34:43.05#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:34:43.07#ibcon#[27=AT06-04\r\n] 2006.145.05:34:43.10#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:34:43.10#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.05:34:43.10#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.05:34:43.10#ibcon#ireg 7 cls_cnt 0 2006.145.05:34:43.10#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:34:43.22#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:34:43.22#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:34:43.24#ibcon#[27=USB\r\n] 2006.145.05:34:43.27#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:34:43.27#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.05:34:43.27#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.05:34:43.27#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.05:34:43.27$vck44/vblo=7,734.99 2006.145.05:34:43.27#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.05:34:43.27#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.05:34:43.27#ibcon#ireg 17 cls_cnt 0 2006.145.05:34:43.27#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:34:43.27#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:34:43.27#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:34:43.29#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.05:34:43.33#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:34:43.33#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.05:34:43.33#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.05:34:43.33#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.05:34:43.33$vck44/vb=7,4 2006.145.05:34:43.33#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.05:34:43.33#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.05:34:43.33#ibcon#ireg 11 cls_cnt 2 2006.145.05:34:43.33#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:34:43.39#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:34:43.39#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:34:43.41#ibcon#[27=AT07-04\r\n] 2006.145.05:34:43.44#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:34:43.44#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.05:34:43.44#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.05:34:43.44#ibcon#ireg 7 cls_cnt 0 2006.145.05:34:43.44#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:34:43.56#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:34:43.56#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:34:43.58#ibcon#[27=USB\r\n] 2006.145.05:34:43.61#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:34:43.61#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.05:34:43.61#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.05:34:43.61#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.05:34:43.61$vck44/vblo=8,744.99 2006.145.05:34:43.61#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.05:34:43.61#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.05:34:43.61#ibcon#ireg 17 cls_cnt 0 2006.145.05:34:43.61#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:34:43.61#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:34:43.61#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:34:43.63#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.05:34:43.67#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:34:43.67#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.05:34:43.67#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.05:34:43.67#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.05:34:43.67$vck44/vb=8,4 2006.145.05:34:43.67#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.05:34:43.67#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.05:34:43.67#ibcon#ireg 11 cls_cnt 2 2006.145.05:34:43.67#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.05:34:43.73#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.05:34:43.73#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.05:34:43.75#ibcon#[27=AT08-04\r\n] 2006.145.05:34:43.78#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.05:34:43.78#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.05:34:43.78#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.05:34:43.78#ibcon#ireg 7 cls_cnt 0 2006.145.05:34:43.78#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.05:34:43.90#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.05:34:43.90#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.05:34:43.92#ibcon#[27=USB\r\n] 2006.145.05:34:43.95#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.05:34:43.95#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.05:34:43.95#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.05:34:43.95#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.05:34:43.95$vck44/vabw=wide 2006.145.05:34:43.95#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.05:34:43.95#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.05:34:43.95#ibcon#ireg 8 cls_cnt 0 2006.145.05:34:43.95#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.05:34:43.95#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.05:34:43.95#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.05:34:43.97#ibcon#[25=BW32\r\n] 2006.145.05:34:44.00#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.05:34:44.00#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.05:34:44.00#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.05:34:44.00#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.05:34:44.00$vck44/vbbw=wide 2006.145.05:34:44.00#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.05:34:44.00#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.05:34:44.00#ibcon#ireg 8 cls_cnt 0 2006.145.05:34:44.00#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.05:34:44.07#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.05:34:44.07#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.05:34:44.09#ibcon#[27=BW32\r\n] 2006.145.05:34:44.12#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.05:34:44.12#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.05:34:44.12#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.05:34:44.12#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.05:34:44.12$setupk4/ifdk4 2006.145.05:34:44.12$ifdk4/lo= 2006.145.05:34:44.12$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.05:34:44.12$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.05:34:44.12$ifdk4/patch= 2006.145.05:34:44.12$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.05:34:44.12$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.05:34:44.12$setupk4/!*+20s 2006.145.05:34:51.19#abcon#<5=/05 4.6 7.2 20.96 571016.2\r\n> 2006.145.05:34:51.21#abcon#{5=INTERFACE CLEAR} 2006.145.05:34:51.27#abcon#[5=S1D000X0/0*\r\n] 2006.145.05:34:58.58$setupk4/"tpicd 2006.145.05:34:58.58$setupk4/echo=off 2006.145.05:34:58.58$setupk4/xlog=off 2006.145.05:34:58.58:!2006.145.05:36:42 2006.145.05:35:13.14#trakl#Source acquired 2006.145.05:35:14.13#flagr#flagr/antenna,acquired 2006.145.05:36:42.00:preob 2006.145.05:36:42.13/onsource/TRACKING 2006.145.05:36:42.13:!2006.145.05:36:52 2006.145.05:36:52.00:"tape 2006.145.05:36:52.00:"st=record 2006.145.05:36:52.00:data_valid=on 2006.145.05:36:52.00:midob 2006.145.05:36:53.13/onsource/TRACKING 2006.145.05:36:53.13/wx/20.95,1016.2,56 2006.145.05:36:53.28/cable/+6.5412E-03 2006.145.05:36:54.37/va/01,08,usb,yes,28,30 2006.145.05:36:54.37/va/02,07,usb,yes,30,30 2006.145.05:36:54.37/va/03,08,usb,yes,27,28 2006.145.05:36:54.37/va/04,07,usb,yes,31,32 2006.145.05:36:54.37/va/05,04,usb,yes,27,27 2006.145.05:36:54.37/va/06,04,usb,yes,30,30 2006.145.05:36:54.37/va/07,04,usb,yes,30,32 2006.145.05:36:54.37/va/08,04,usb,yes,26,31 2006.145.05:36:54.60/valo/01,524.99,yes,locked 2006.145.05:36:54.60/valo/02,534.99,yes,locked 2006.145.05:36:54.60/valo/03,564.99,yes,locked 2006.145.05:36:54.60/valo/04,624.99,yes,locked 2006.145.05:36:54.60/valo/05,734.99,yes,locked 2006.145.05:36:54.60/valo/06,814.99,yes,locked 2006.145.05:36:54.60/valo/07,864.99,yes,locked 2006.145.05:36:54.60/valo/08,884.99,yes,locked 2006.145.05:36:55.69/vb/01,03,usb,yes,35,33 2006.145.05:36:55.69/vb/02,04,usb,yes,31,31 2006.145.05:36:55.69/vb/03,04,usb,yes,28,31 2006.145.05:36:55.69/vb/04,04,usb,yes,32,31 2006.145.05:36:55.69/vb/05,04,usb,yes,25,27 2006.145.05:36:55.69/vb/06,04,usb,yes,29,26 2006.145.05:36:55.69/vb/07,04,usb,yes,29,29 2006.145.05:36:55.69/vb/08,04,usb,yes,27,30 2006.145.05:36:55.92/vblo/01,629.99,yes,locked 2006.145.05:36:55.92/vblo/02,634.99,yes,locked 2006.145.05:36:55.92/vblo/03,649.99,yes,locked 2006.145.05:36:55.92/vblo/04,679.99,yes,locked 2006.145.05:36:55.92/vblo/05,709.99,yes,locked 2006.145.05:36:55.92/vblo/06,719.99,yes,locked 2006.145.05:36:55.92/vblo/07,734.99,yes,locked 2006.145.05:36:55.92/vblo/08,744.99,yes,locked 2006.145.05:36:56.07/vabw/8 2006.145.05:36:56.22/vbbw/8 2006.145.05:36:56.31/xfe/off,on,14.2 2006.145.05:36:56.69/ifatt/23,28,28,28 2006.145.05:36:57.08/fmout-gps/S +4.8E-08 2006.145.05:36:57.16:!2006.145.05:37:42 2006.145.05:37:42.00:data_valid=off 2006.145.05:37:42.00:"et 2006.145.05:37:42.00:!+3s 2006.145.05:37:45.02:"tape 2006.145.05:37:45.02:postob 2006.145.05:37:45.14/cable/+6.5404E-03 2006.145.05:37:45.14/wx/20.95,1016.2,57 2006.145.05:37:46.08/fmout-gps/S +4.8E-08 2006.145.05:37:46.08:scan_name=145-0540,jd0605,780 2006.145.05:37:46.08:source=0133+476,013658.59,475129.1,2000.0,ccw 2006.145.05:37:47.14#flagr#flagr/antenna,new-source 2006.145.05:37:47.14:checkk5 2006.145.05:37:47.61/chk_autoobs//k5ts1/ autoobs is running! 2006.145.05:37:48.08/chk_autoobs//k5ts2/ autoobs is running! 2006.145.05:37:48.63/chk_autoobs//k5ts3/ autoobs is running! 2006.145.05:37:49.15/chk_autoobs//k5ts4/ autoobs is running! 2006.145.05:37:49.63/chk_obsdata//k5ts1/T1450536??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.145.05:37:50.08/chk_obsdata//k5ts2/T1450536??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.145.05:37:50.52/chk_obsdata//k5ts3/T1450536??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.145.05:37:51.00/chk_obsdata//k5ts4/T1450536??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.145.05:37:51.80/k5log//k5ts1_log_newline 2006.145.05:37:52.57/k5log//k5ts2_log_newline 2006.145.05:37:53.44/k5log//k5ts3_log_newline 2006.145.05:37:54.24/k5log//k5ts4_log_newline 2006.145.05:37:54.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.05:37:54.26:setupk4=1 2006.145.05:37:54.26$setupk4/echo=on 2006.145.05:37:54.26$setupk4/pcalon 2006.145.05:37:54.26$pcalon/"no phase cal control is implemented here 2006.145.05:37:54.26$setupk4/"tpicd=stop 2006.145.05:37:54.26$setupk4/"rec=synch_on 2006.145.05:37:54.26$setupk4/"rec_mode=128 2006.145.05:37:54.26$setupk4/!* 2006.145.05:37:54.26$setupk4/recpk4 2006.145.05:37:54.26$recpk4/recpatch= 2006.145.05:37:54.27$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.05:37:54.27$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.05:37:54.27$setupk4/vck44 2006.145.05:37:54.27$vck44/valo=1,524.99 2006.145.05:37:54.27#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.05:37:54.27#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.05:37:54.27#ibcon#ireg 17 cls_cnt 0 2006.145.05:37:54.27#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:37:54.27#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:37:54.27#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:37:54.31#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.05:37:54.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:37:54.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:37:54.36#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.05:37:54.36#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.05:37:54.36$vck44/va=1,8 2006.145.05:37:54.36#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.05:37:54.36#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.05:37:54.36#ibcon#ireg 11 cls_cnt 2 2006.145.05:37:54.36#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:37:54.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:37:54.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:37:54.36#abcon#<5=/05 4.4 7.2 20.95 601016.2\r\n> 2006.145.05:37:54.38#ibcon#[25=AT01-08\r\n] 2006.145.05:37:54.38#abcon#{5=INTERFACE CLEAR} 2006.145.05:37:54.41#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:37:54.41#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.05:37:54.41#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.05:37:54.41#ibcon#ireg 7 cls_cnt 0 2006.145.05:37:54.41#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:37:54.44#abcon#[5=S1D000X0/0*\r\n] 2006.145.05:37:54.53#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:37:54.53#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:37:54.55#ibcon#[25=USB\r\n] 2006.145.05:37:54.58#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:37:54.58#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.05:37:54.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.05:37:54.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.05:37:54.58$vck44/valo=2,534.99 2006.145.05:37:54.58#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.05:37:54.58#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.05:37:54.58#ibcon#ireg 17 cls_cnt 0 2006.145.05:37:54.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:37:54.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:37:54.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:37:54.61#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.05:37:54.65#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:37:54.65#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:37:54.65#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.05:37:54.65#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.05:37:54.65$vck44/va=2,7 2006.145.05:37:54.65#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.05:37:54.65#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.05:37:54.65#ibcon#ireg 11 cls_cnt 2 2006.145.05:37:54.65#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:37:54.70#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:37:54.70#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:37:54.72#ibcon#[25=AT02-07\r\n] 2006.145.05:37:54.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:37:54.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:37:54.75#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.05:37:54.75#ibcon#ireg 7 cls_cnt 0 2006.145.05:37:54.75#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:37:54.87#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:37:54.87#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:37:54.89#ibcon#[25=USB\r\n] 2006.145.05:37:54.92#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:37:54.92#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:37:54.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.05:37:54.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.05:37:54.92$vck44/valo=3,564.99 2006.145.05:37:54.92#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.05:37:54.92#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.05:37:54.92#ibcon#ireg 17 cls_cnt 0 2006.145.05:37:54.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:37:54.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:37:54.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:37:54.94#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.05:37:54.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:37:54.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:37:54.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.05:37:54.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.05:37:54.98$vck44/va=3,8 2006.145.05:37:54.98#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.05:37:54.98#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.05:37:54.98#ibcon#ireg 11 cls_cnt 2 2006.145.05:37:54.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:37:55.04#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:37:55.04#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:37:55.06#ibcon#[25=AT03-08\r\n] 2006.145.05:37:55.09#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:37:55.09#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:37:55.09#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.05:37:55.09#ibcon#ireg 7 cls_cnt 0 2006.145.05:37:55.09#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:37:55.21#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:37:55.21#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:37:55.23#ibcon#[25=USB\r\n] 2006.145.05:37:55.26#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:37:55.26#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:37:55.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.05:37:55.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.05:37:55.26$vck44/valo=4,624.99 2006.145.05:37:55.26#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.05:37:55.26#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.05:37:55.26#ibcon#ireg 17 cls_cnt 0 2006.145.05:37:55.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:37:55.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:37:55.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:37:55.28#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.05:37:55.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:37:55.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:37:55.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.05:37:55.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.05:37:55.32$vck44/va=4,7 2006.145.05:37:55.32#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.05:37:55.32#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.05:37:55.32#ibcon#ireg 11 cls_cnt 2 2006.145.05:37:55.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:37:55.38#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:37:55.38#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:37:55.40#ibcon#[25=AT04-07\r\n] 2006.145.05:37:55.43#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:37:55.43#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:37:55.43#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.05:37:55.43#ibcon#ireg 7 cls_cnt 0 2006.145.05:37:55.43#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:37:55.55#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:37:55.55#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:37:55.57#ibcon#[25=USB\r\n] 2006.145.05:37:55.60#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:37:55.60#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:37:55.60#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.05:37:55.60#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.05:37:55.60$vck44/valo=5,734.99 2006.145.05:37:55.60#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.05:37:55.60#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.05:37:55.60#ibcon#ireg 17 cls_cnt 0 2006.145.05:37:55.60#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:37:55.60#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:37:55.60#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:37:55.62#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.05:37:55.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:37:55.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:37:55.66#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.05:37:55.66#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.05:37:55.66$vck44/va=5,4 2006.145.05:37:55.66#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.05:37:55.66#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.05:37:55.66#ibcon#ireg 11 cls_cnt 2 2006.145.05:37:55.66#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:37:55.72#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:37:55.72#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:37:55.74#ibcon#[25=AT05-04\r\n] 2006.145.05:37:55.77#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:37:55.77#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:37:55.77#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.05:37:55.77#ibcon#ireg 7 cls_cnt 0 2006.145.05:37:55.77#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:37:55.89#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:37:55.89#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:37:55.91#ibcon#[25=USB\r\n] 2006.145.05:37:55.94#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:37:55.94#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:37:55.94#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.05:37:55.94#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.05:37:55.94$vck44/valo=6,814.99 2006.145.05:37:55.94#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.05:37:55.94#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.05:37:55.94#ibcon#ireg 17 cls_cnt 0 2006.145.05:37:55.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:37:55.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:37:55.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:37:55.96#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.05:37:56.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:37:56.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:37:56.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.05:37:56.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.05:37:56.00$vck44/va=6,4 2006.145.05:37:56.00#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.05:37:56.00#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.05:37:56.00#ibcon#ireg 11 cls_cnt 2 2006.145.05:37:56.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:37:56.06#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:37:56.06#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:37:56.08#ibcon#[25=AT06-04\r\n] 2006.145.05:37:56.11#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:37:56.11#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:37:56.11#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.05:37:56.11#ibcon#ireg 7 cls_cnt 0 2006.145.05:37:56.11#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:37:56.23#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:37:56.23#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:37:56.25#ibcon#[25=USB\r\n] 2006.145.05:37:56.28#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:37:56.28#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:37:56.28#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.05:37:56.28#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.05:37:56.28$vck44/valo=7,864.99 2006.145.05:37:56.28#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.05:37:56.28#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.05:37:56.28#ibcon#ireg 17 cls_cnt 0 2006.145.05:37:56.28#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:37:56.28#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:37:56.28#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:37:56.30#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.05:37:56.34#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:37:56.34#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:37:56.34#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.05:37:56.34#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.05:37:56.34$vck44/va=7,4 2006.145.05:37:56.34#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.05:37:56.34#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.05:37:56.34#ibcon#ireg 11 cls_cnt 2 2006.145.05:37:56.34#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:37:56.40#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:37:56.40#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:37:56.42#ibcon#[25=AT07-04\r\n] 2006.145.05:37:56.45#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:37:56.45#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:37:56.45#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.05:37:56.45#ibcon#ireg 7 cls_cnt 0 2006.145.05:37:56.45#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:37:56.57#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:37:56.57#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:37:56.59#ibcon#[25=USB\r\n] 2006.145.05:37:56.62#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:37:56.62#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:37:56.62#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.05:37:56.62#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.05:37:56.62$vck44/valo=8,884.99 2006.145.05:37:56.62#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.05:37:56.62#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.05:37:56.62#ibcon#ireg 17 cls_cnt 0 2006.145.05:37:56.62#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:37:56.62#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:37:56.62#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:37:56.64#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.05:37:56.68#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:37:56.68#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:37:56.68#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.05:37:56.68#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.05:37:56.68$vck44/va=8,4 2006.145.05:37:56.68#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.05:37:56.68#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.05:37:56.68#ibcon#ireg 11 cls_cnt 2 2006.145.05:37:56.68#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:37:56.74#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:37:56.74#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:37:56.76#ibcon#[25=AT08-04\r\n] 2006.145.05:37:56.79#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:37:56.79#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:37:56.79#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.05:37:56.79#ibcon#ireg 7 cls_cnt 0 2006.145.05:37:56.79#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:37:56.91#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:37:56.91#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:37:56.93#ibcon#[25=USB\r\n] 2006.145.05:37:56.96#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:37:56.96#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:37:56.96#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.05:37:56.96#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.05:37:56.96$vck44/vblo=1,629.99 2006.145.05:37:56.96#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.05:37:56.96#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.05:37:56.96#ibcon#ireg 17 cls_cnt 0 2006.145.05:37:56.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:37:56.96#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:37:56.96#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:37:56.98#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.05:37:57.02#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:37:57.02#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:37:57.02#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.05:37:57.02#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.05:37:57.02$vck44/vb=1,3 2006.145.05:37:57.02#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.05:37:57.02#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.05:37:57.02#ibcon#ireg 11 cls_cnt 2 2006.145.05:37:57.02#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:37:57.02#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:37:57.02#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:37:57.04#ibcon#[27=AT01-03\r\n] 2006.145.05:37:57.07#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:37:57.07#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:37:57.07#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.05:37:57.07#ibcon#ireg 7 cls_cnt 0 2006.145.05:37:57.07#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:37:57.19#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:37:57.19#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:37:57.21#ibcon#[27=USB\r\n] 2006.145.05:37:57.24#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:37:57.24#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:37:57.24#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.05:37:57.24#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.05:37:57.24$vck44/vblo=2,634.99 2006.145.05:37:57.24#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.05:37:57.24#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.05:37:57.24#ibcon#ireg 17 cls_cnt 0 2006.145.05:37:57.24#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:37:57.24#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:37:57.24#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:37:57.26#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.05:37:57.30#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:37:57.30#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:37:57.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.05:37:57.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.05:37:57.30$vck44/vb=2,4 2006.145.05:37:57.30#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.05:37:57.30#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.05:37:57.30#ibcon#ireg 11 cls_cnt 2 2006.145.05:37:57.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.05:37:57.36#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.05:37:57.36#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.05:37:57.38#ibcon#[27=AT02-04\r\n] 2006.145.05:37:57.41#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.05:37:57.41#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.05:37:57.41#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.05:37:57.41#ibcon#ireg 7 cls_cnt 0 2006.145.05:37:57.41#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.05:37:57.53#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.05:37:57.53#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.05:37:57.55#ibcon#[27=USB\r\n] 2006.145.05:37:57.58#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.05:37:57.58#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.05:37:57.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.05:37:57.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.05:37:57.58$vck44/vblo=3,649.99 2006.145.05:37:57.58#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.05:37:57.58#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.05:37:57.58#ibcon#ireg 17 cls_cnt 0 2006.145.05:37:57.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:37:57.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:37:57.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:37:57.60#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.05:37:57.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:37:57.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:37:57.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.05:37:57.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.05:37:57.64$vck44/vb=3,4 2006.145.05:37:57.64#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.05:37:57.64#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.05:37:57.64#ibcon#ireg 11 cls_cnt 2 2006.145.05:37:57.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:37:57.70#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:37:57.70#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:37:57.72#ibcon#[27=AT03-04\r\n] 2006.145.05:37:57.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:37:57.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:37:57.75#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.05:37:57.75#ibcon#ireg 7 cls_cnt 0 2006.145.05:37:57.75#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:37:57.87#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:37:57.87#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:37:57.89#ibcon#[27=USB\r\n] 2006.145.05:37:57.92#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:37:57.92#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:37:57.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.05:37:57.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.05:37:57.92$vck44/vblo=4,679.99 2006.145.05:37:57.92#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.05:37:57.92#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.05:37:57.92#ibcon#ireg 17 cls_cnt 0 2006.145.05:37:57.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:37:57.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:37:57.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:37:57.94#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.05:37:57.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:37:57.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:37:57.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.05:37:57.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.05:37:57.98$vck44/vb=4,4 2006.145.05:37:57.98#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.05:37:57.98#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.05:37:57.98#ibcon#ireg 11 cls_cnt 2 2006.145.05:37:57.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:37:58.04#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:37:58.04#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:37:58.06#ibcon#[27=AT04-04\r\n] 2006.145.05:37:58.09#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:37:58.09#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:37:58.09#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.05:37:58.09#ibcon#ireg 7 cls_cnt 0 2006.145.05:37:58.09#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:37:58.21#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:37:58.21#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:37:58.23#ibcon#[27=USB\r\n] 2006.145.05:37:58.26#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:37:58.26#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:37:58.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.05:37:58.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.05:37:58.26$vck44/vblo=5,709.99 2006.145.05:37:58.26#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.05:37:58.26#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.05:37:58.26#ibcon#ireg 17 cls_cnt 0 2006.145.05:37:58.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:37:58.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:37:58.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:37:58.28#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.05:37:58.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:37:58.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:37:58.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.05:37:58.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.05:37:58.32$vck44/vb=5,4 2006.145.05:37:58.32#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.05:37:58.32#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.05:37:58.32#ibcon#ireg 11 cls_cnt 2 2006.145.05:37:58.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:37:58.38#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:37:58.38#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:37:58.40#ibcon#[27=AT05-04\r\n] 2006.145.05:37:58.43#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:37:58.43#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:37:58.43#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.05:37:58.43#ibcon#ireg 7 cls_cnt 0 2006.145.05:37:58.43#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:37:58.55#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:37:58.55#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:37:58.57#ibcon#[27=USB\r\n] 2006.145.05:37:58.60#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:37:58.60#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:37:58.60#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.05:37:58.60#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.05:37:58.60$vck44/vblo=6,719.99 2006.145.05:37:58.60#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.05:37:58.60#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.05:37:58.60#ibcon#ireg 17 cls_cnt 0 2006.145.05:37:58.60#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:37:58.60#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:37:58.60#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:37:58.62#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.05:37:58.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:37:58.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:37:58.66#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.05:37:58.66#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.05:37:58.66$vck44/vb=6,4 2006.145.05:37:58.66#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.05:37:58.66#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.05:37:58.66#ibcon#ireg 11 cls_cnt 2 2006.145.05:37:58.66#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:37:58.72#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:37:58.72#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:37:58.74#ibcon#[27=AT06-04\r\n] 2006.145.05:37:58.77#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:37:58.77#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:37:58.77#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.05:37:58.77#ibcon#ireg 7 cls_cnt 0 2006.145.05:37:58.77#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:37:58.89#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:37:58.89#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:37:58.91#ibcon#[27=USB\r\n] 2006.145.05:37:58.94#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:37:58.94#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:37:58.94#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.05:37:58.94#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.05:37:58.94$vck44/vblo=7,734.99 2006.145.05:37:58.94#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.05:37:58.94#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.05:37:58.94#ibcon#ireg 17 cls_cnt 0 2006.145.05:37:58.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:37:58.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:37:58.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:37:58.96#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.05:37:59.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:37:59.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:37:59.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.05:37:59.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.05:37:59.00$vck44/vb=7,4 2006.145.05:37:59.00#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.05:37:59.00#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.05:37:59.00#ibcon#ireg 11 cls_cnt 2 2006.145.05:37:59.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:37:59.06#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:37:59.06#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:37:59.08#ibcon#[27=AT07-04\r\n] 2006.145.05:37:59.11#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:37:59.11#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:37:59.11#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.05:37:59.11#ibcon#ireg 7 cls_cnt 0 2006.145.05:37:59.11#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:37:59.23#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:37:59.23#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:37:59.25#ibcon#[27=USB\r\n] 2006.145.05:37:59.28#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:37:59.28#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:37:59.28#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.05:37:59.28#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.05:37:59.28$vck44/vblo=8,744.99 2006.145.05:37:59.28#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.05:37:59.28#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.05:37:59.28#ibcon#ireg 17 cls_cnt 0 2006.145.05:37:59.28#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:37:59.28#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:37:59.28#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:37:59.30#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.05:37:59.34#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:37:59.34#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:37:59.34#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.05:37:59.34#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.05:37:59.34$vck44/vb=8,4 2006.145.05:37:59.34#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.05:37:59.34#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.05:37:59.34#ibcon#ireg 11 cls_cnt 2 2006.145.05:37:59.34#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:37:59.40#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:37:59.40#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:37:59.42#ibcon#[27=AT08-04\r\n] 2006.145.05:37:59.45#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:37:59.45#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:37:59.45#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.05:37:59.45#ibcon#ireg 7 cls_cnt 0 2006.145.05:37:59.45#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:37:59.57#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:37:59.57#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:37:59.59#ibcon#[27=USB\r\n] 2006.145.05:37:59.62#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:37:59.62#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:37:59.62#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.05:37:59.62#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.05:37:59.62$vck44/vabw=wide 2006.145.05:37:59.62#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.05:37:59.62#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.05:37:59.62#ibcon#ireg 8 cls_cnt 0 2006.145.05:37:59.62#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:37:59.62#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:37:59.62#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:37:59.64#ibcon#[25=BW32\r\n] 2006.145.05:37:59.67#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:37:59.67#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:37:59.67#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.05:37:59.67#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.05:37:59.67$vck44/vbbw=wide 2006.145.05:37:59.67#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.05:37:59.67#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.05:37:59.67#ibcon#ireg 8 cls_cnt 0 2006.145.05:37:59.67#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.05:37:59.74#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.05:37:59.74#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.05:37:59.76#ibcon#[27=BW32\r\n] 2006.145.05:37:59.79#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.05:37:59.79#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.05:37:59.79#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.05:37:59.79#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.05:37:59.79$setupk4/ifdk4 2006.145.05:37:59.79$ifdk4/lo= 2006.145.05:37:59.79$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.05:37:59.79$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.05:37:59.79$ifdk4/patch= 2006.145.05:37:59.79$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.05:37:59.79$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.05:37:59.79$setupk4/!*+20s 2006.145.05:38:04.53#abcon#<5=/05 4.4 7.2 20.95 601016.2\r\n> 2006.145.05:38:04.55#abcon#{5=INTERFACE CLEAR} 2006.145.05:38:04.63#abcon#[5=S1D000X0/0*\r\n] 2006.145.05:38:14.14#trakl#Source acquired 2006.145.05:38:14.27$setupk4/"tpicd 2006.145.05:38:14.27$setupk4/echo=off 2006.145.05:38:14.27$setupk4/xlog=off 2006.145.05:38:14.27:!2006.145.05:39:58 2006.145.05:38:16.14#flagr#flagr/antenna,acquired 2006.145.05:39:58.00:preob 2006.145.05:39:59.14/onsource/TRACKING 2006.145.05:39:59.14:!2006.145.05:40:08 2006.145.05:40:08.00:"tape 2006.145.05:40:08.00:"st=record 2006.145.05:40:08.00:data_valid=on 2006.145.05:40:08.00:midob 2006.145.05:40:08.14/onsource/TRACKING 2006.145.05:40:08.14/wx/20.97,1016.2,57 2006.145.05:40:08.25/cable/+6.5414E-03 2006.145.05:40:09.34/va/01,08,usb,yes,29,31 2006.145.05:40:09.34/va/02,07,usb,yes,31,32 2006.145.05:40:09.34/va/03,08,usb,yes,28,29 2006.145.05:40:09.34/va/04,07,usb,yes,32,34 2006.145.05:40:09.34/va/05,04,usb,yes,28,28 2006.145.05:40:09.34/va/06,04,usb,yes,31,31 2006.145.05:40:09.34/va/07,04,usb,yes,32,33 2006.145.05:40:09.34/va/08,04,usb,yes,27,32 2006.145.05:40:09.57/valo/01,524.99,yes,locked 2006.145.05:40:09.57/valo/02,534.99,yes,locked 2006.145.05:40:09.57/valo/03,564.99,yes,locked 2006.145.05:40:09.57/valo/04,624.99,yes,locked 2006.145.05:40:09.57/valo/05,734.99,yes,locked 2006.145.05:40:09.57/valo/06,814.99,yes,locked 2006.145.05:40:09.57/valo/07,864.99,yes,locked 2006.145.05:40:09.57/valo/08,884.99,yes,locked 2006.145.05:40:10.66/vb/01,03,usb,yes,36,33 2006.145.05:40:10.66/vb/02,04,usb,yes,31,31 2006.145.05:40:10.66/vb/03,04,usb,yes,28,31 2006.145.05:40:10.66/vb/04,04,usb,yes,33,32 2006.145.05:40:10.66/vb/05,04,usb,yes,25,28 2006.145.05:40:10.66/vb/06,04,usb,yes,30,26 2006.145.05:40:10.66/vb/07,04,usb,yes,29,29 2006.145.05:40:10.66/vb/08,04,usb,yes,27,30 2006.145.05:40:10.89/vblo/01,629.99,yes,locked 2006.145.05:40:10.89/vblo/02,634.99,yes,locked 2006.145.05:40:10.89/vblo/03,649.99,yes,locked 2006.145.05:40:10.89/vblo/04,679.99,yes,locked 2006.145.05:40:10.89/vblo/05,709.99,yes,locked 2006.145.05:40:10.89/vblo/06,719.99,yes,locked 2006.145.05:40:10.89/vblo/07,734.99,yes,locked 2006.145.05:40:10.89/vblo/08,744.99,yes,locked 2006.145.05:40:11.04/vabw/8 2006.145.05:40:11.19/vbbw/8 2006.145.05:40:11.28/xfe/off,on,15.2 2006.145.05:40:11.66/ifatt/23,28,28,28 2006.145.05:40:12.08/fmout-gps/S +4.8E-08 2006.145.05:40:12.12:!2006.145.05:53:08 2006.145.05:53:08.00:data_valid=off 2006.145.05:53:08.01:"et 2006.145.05:53:08.01:!+3s 2006.145.05:53:11.03:"tape 2006.145.05:53:11.03:postob 2006.145.05:53:11.16/cable/+6.5426E-03 2006.145.05:53:11.16/wx/20.85,1016.2,58 2006.145.05:53:11.22/fmout-gps/S +4.8E-08 2006.145.05:53:11.22:scan_name=145-0554,jd0605,40 2006.145.05:53:11.22:source=0537-441,053850.36,-440508.9,2000.0,ccw 2006.145.05:53:12.13:checkk5 2006.145.05:53:12.13#flagr#flagr/antenna,new-source 2006.145.05:53:12.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.05:53:13.05/chk_autoobs//k5ts2/ autoobs is running! 2006.145.05:53:13.56/chk_autoobs//k5ts3/ autoobs is running! 2006.145.05:53:14.01/chk_autoobs//k5ts4/ autoobs is running! 2006.145.05:53:14.89/chk_obsdata//k5ts1/T1450540??a.dat file size is correct (nominal:3120MB, actual:3120MB). 2006.145.05:53:15.69/chk_obsdata//k5ts2/T1450540??b.dat file size is correct (nominal:3120MB, actual:3120MB). 2006.145.05:53:16.65/chk_obsdata//k5ts3/T1450540??c.dat file size is correct (nominal:3120MB, actual:3120MB). 2006.145.05:53:17.49/chk_obsdata//k5ts4/T1450540??d.dat file size is correct (nominal:3120MB, actual:3120MB). 2006.145.05:53:18.32/k5log//k5ts1_log_newline 2006.145.05:53:19.37/k5log//k5ts2_log_newline 2006.145.05:53:20.46/k5log//k5ts3_log_newline 2006.145.05:53:21.55/k5log//k5ts4_log_newline 2006.145.05:53:21.57/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.05:53:21.57:setupk4=1 2006.145.05:53:21.57$setupk4/echo=on 2006.145.05:53:21.57$setupk4/pcalon 2006.145.05:53:21.57$pcalon/"no phase cal control is implemented here 2006.145.05:53:21.57$setupk4/"tpicd=stop 2006.145.05:53:21.57$setupk4/"rec=synch_on 2006.145.05:53:21.57$setupk4/"rec_mode=128 2006.145.05:53:21.57$setupk4/!* 2006.145.05:53:21.57$setupk4/recpk4 2006.145.05:53:21.57$recpk4/recpatch= 2006.145.05:53:21.57$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.05:53:21.58$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.05:53:21.58$setupk4/vck44 2006.145.05:53:21.58$vck44/valo=1,524.99 2006.145.05:53:21.58#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.05:53:21.58#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.05:53:21.58#ibcon#ireg 17 cls_cnt 0 2006.145.05:53:21.58#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.05:53:21.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.05:53:21.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.05:53:21.59#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.05:53:21.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.05:53:21.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.05:53:21.64#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.05:53:21.64#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.05:53:21.64$vck44/va=1,8 2006.145.05:53:21.64#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.05:53:21.64#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.05:53:21.64#ibcon#ireg 11 cls_cnt 2 2006.145.05:53:21.64#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.05:53:21.64#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.05:53:21.64#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.05:53:21.66#ibcon#[25=AT01-08\r\n] 2006.145.05:53:21.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.05:53:21.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.05:53:21.69#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.05:53:21.69#ibcon#ireg 7 cls_cnt 0 2006.145.05:53:21.69#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.05:53:21.81#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.05:53:21.81#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.05:53:21.83#ibcon#[25=USB\r\n] 2006.145.05:53:21.86#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.05:53:21.86#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.05:53:21.86#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.05:53:21.86#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.05:53:21.86$vck44/valo=2,534.99 2006.145.05:53:21.86#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.05:53:21.86#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.05:53:21.86#ibcon#ireg 17 cls_cnt 0 2006.145.05:53:21.86#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.05:53:21.86#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.05:53:21.86#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.05:53:21.89#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.05:53:21.93#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.05:53:21.93#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.05:53:21.93#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.05:53:21.93#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.05:53:21.93$vck44/va=2,7 2006.145.05:53:21.93#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.05:53:21.93#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.05:53:21.93#ibcon#ireg 11 cls_cnt 2 2006.145.05:53:21.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.05:53:21.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.05:53:21.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.05:53:22.00#ibcon#[25=AT02-07\r\n] 2006.145.05:53:22.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.05:53:22.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.05:53:22.03#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.05:53:22.03#ibcon#ireg 7 cls_cnt 0 2006.145.05:53:22.03#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.05:53:22.15#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.05:53:22.15#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.05:53:22.17#ibcon#[25=USB\r\n] 2006.145.05:53:22.20#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.05:53:22.20#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.05:53:22.20#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.05:53:22.20#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.05:53:22.20$vck44/valo=3,564.99 2006.145.05:53:22.20#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.05:53:22.20#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.05:53:22.20#ibcon#ireg 17 cls_cnt 0 2006.145.05:53:22.20#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.05:53:22.20#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.05:53:22.20#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.05:53:22.22#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.05:53:22.26#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.05:53:22.26#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.05:53:22.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.05:53:22.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.05:53:22.26$vck44/va=3,8 2006.145.05:53:22.26#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.05:53:22.26#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.05:53:22.26#ibcon#ireg 11 cls_cnt 2 2006.145.05:53:22.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.05:53:22.32#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.05:53:22.32#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.05:53:22.34#ibcon#[25=AT03-08\r\n] 2006.145.05:53:22.37#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.05:53:22.37#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.05:53:22.37#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.05:53:22.37#ibcon#ireg 7 cls_cnt 0 2006.145.05:53:22.37#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.05:53:22.49#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.05:53:22.49#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.05:53:22.51#ibcon#[25=USB\r\n] 2006.145.05:53:22.54#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.05:53:22.54#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.05:53:22.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.05:53:22.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.05:53:22.54$vck44/valo=4,624.99 2006.145.05:53:22.54#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.05:53:22.54#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.05:53:22.54#ibcon#ireg 17 cls_cnt 0 2006.145.05:53:22.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.05:53:22.54#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.05:53:22.54#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.05:53:22.56#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.05:53:22.60#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.05:53:22.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.05:53:22.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.05:53:22.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.05:53:22.60$vck44/va=4,7 2006.145.05:53:22.60#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.05:53:22.60#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.05:53:22.60#ibcon#ireg 11 cls_cnt 2 2006.145.05:53:22.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.05:53:22.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.05:53:22.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.05:53:22.68#ibcon#[25=AT04-07\r\n] 2006.145.05:53:22.71#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.05:53:22.71#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.05:53:22.71#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.05:53:22.71#ibcon#ireg 7 cls_cnt 0 2006.145.05:53:22.71#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.05:53:22.83#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.05:53:22.83#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.05:53:22.85#ibcon#[25=USB\r\n] 2006.145.05:53:22.88#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.05:53:22.88#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.05:53:22.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.05:53:22.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.05:53:22.88$vck44/valo=5,734.99 2006.145.05:53:22.88#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.05:53:22.88#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.05:53:22.88#ibcon#ireg 17 cls_cnt 0 2006.145.05:53:22.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.05:53:22.88#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.05:53:22.88#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.05:53:22.90#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.05:53:22.94#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.05:53:22.94#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.05:53:22.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.05:53:22.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.05:53:22.94$vck44/va=5,4 2006.145.05:53:22.94#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.05:53:22.94#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.05:53:22.94#ibcon#ireg 11 cls_cnt 2 2006.145.05:53:22.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.05:53:23.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.05:53:23.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.05:53:23.02#ibcon#[25=AT05-04\r\n] 2006.145.05:53:23.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.05:53:23.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.05:53:23.05#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.05:53:23.05#ibcon#ireg 7 cls_cnt 0 2006.145.05:53:23.05#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.05:53:23.17#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.05:53:23.17#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.05:53:23.19#ibcon#[25=USB\r\n] 2006.145.05:53:23.22#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.05:53:23.22#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.05:53:23.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.05:53:23.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.05:53:23.22$vck44/valo=6,814.99 2006.145.05:53:23.22#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.05:53:23.22#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.05:53:23.22#ibcon#ireg 17 cls_cnt 0 2006.145.05:53:23.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.05:53:23.22#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.05:53:23.22#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.05:53:23.24#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.05:53:23.28#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.05:53:23.28#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.05:53:23.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.05:53:23.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.05:53:23.28$vck44/va=6,4 2006.145.05:53:23.28#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.05:53:23.28#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.05:53:23.28#ibcon#ireg 11 cls_cnt 2 2006.145.05:53:23.28#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.05:53:23.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.05:53:23.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.05:53:23.36#ibcon#[25=AT06-04\r\n] 2006.145.05:53:23.39#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.05:53:23.39#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.05:53:23.39#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.05:53:23.39#ibcon#ireg 7 cls_cnt 0 2006.145.05:53:23.39#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.05:53:23.51#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.05:53:23.51#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.05:53:23.53#ibcon#[25=USB\r\n] 2006.145.05:53:23.56#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.05:53:23.56#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.05:53:23.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.05:53:23.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.05:53:23.56$vck44/valo=7,864.99 2006.145.05:53:23.56#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.05:53:23.56#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.05:53:23.56#ibcon#ireg 17 cls_cnt 0 2006.145.05:53:23.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.05:53:23.56#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.05:53:23.56#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.05:53:23.58#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.05:53:23.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.05:53:23.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.05:53:23.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.05:53:23.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.05:53:23.62$vck44/va=7,4 2006.145.05:53:23.62#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.05:53:23.62#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.05:53:23.62#ibcon#ireg 11 cls_cnt 2 2006.145.05:53:23.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.05:53:23.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.05:53:23.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.05:53:23.70#ibcon#[25=AT07-04\r\n] 2006.145.05:53:23.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.05:53:23.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.05:53:23.73#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.05:53:23.73#ibcon#ireg 7 cls_cnt 0 2006.145.05:53:23.73#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.05:53:23.85#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.05:53:23.85#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.05:53:23.87#ibcon#[25=USB\r\n] 2006.145.05:53:23.90#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.05:53:23.90#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.05:53:23.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.05:53:23.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.05:53:23.90$vck44/valo=8,884.99 2006.145.05:53:23.90#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.05:53:23.90#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.05:53:23.90#ibcon#ireg 17 cls_cnt 0 2006.145.05:53:23.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.05:53:23.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.05:53:23.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.05:53:23.92#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.05:53:23.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.05:53:23.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.05:53:23.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.05:53:23.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.05:53:23.96$vck44/va=8,4 2006.145.05:53:23.96#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.05:53:23.96#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.05:53:23.96#ibcon#ireg 11 cls_cnt 2 2006.145.05:53:23.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.05:53:24.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.05:53:24.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.05:53:24.04#ibcon#[25=AT08-04\r\n] 2006.145.05:53:24.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.05:53:24.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.05:53:24.07#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.05:53:24.07#ibcon#ireg 7 cls_cnt 0 2006.145.05:53:24.07#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.05:53:24.19#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.05:53:24.19#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.05:53:24.21#ibcon#[25=USB\r\n] 2006.145.05:53:24.24#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.05:53:24.24#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.05:53:24.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.05:53:24.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.05:53:24.24$vck44/vblo=1,629.99 2006.145.05:53:24.24#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.05:53:24.24#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.05:53:24.24#ibcon#ireg 17 cls_cnt 0 2006.145.05:53:24.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.05:53:24.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.05:53:24.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.05:53:24.26#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.05:53:24.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.05:53:24.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.05:53:24.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.05:53:24.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.05:53:24.30$vck44/vb=1,3 2006.145.05:53:24.30#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.05:53:24.30#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.05:53:24.30#ibcon#ireg 11 cls_cnt 2 2006.145.05:53:24.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.05:53:24.30#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.05:53:24.30#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.05:53:24.32#ibcon#[27=AT01-03\r\n] 2006.145.05:53:24.35#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.05:53:24.35#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.05:53:24.35#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.05:53:24.35#ibcon#ireg 7 cls_cnt 0 2006.145.05:53:24.35#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.05:53:24.47#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.05:53:24.47#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.05:53:24.49#ibcon#[27=USB\r\n] 2006.145.05:53:24.52#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.05:53:24.52#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.05:53:24.52#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.05:53:24.52#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.05:53:24.52$vck44/vblo=2,634.99 2006.145.05:53:24.52#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.05:53:24.52#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.05:53:24.52#ibcon#ireg 17 cls_cnt 0 2006.145.05:53:24.52#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.05:53:24.52#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.05:53:24.52#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.05:53:24.54#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.05:53:24.58#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.05:53:24.58#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.05:53:24.58#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.05:53:24.58#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.05:53:24.58$vck44/vb=2,4 2006.145.05:53:24.58#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.05:53:24.58#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.05:53:24.58#ibcon#ireg 11 cls_cnt 2 2006.145.05:53:24.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.05:53:24.64#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.05:53:24.64#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.05:53:24.66#ibcon#[27=AT02-04\r\n] 2006.145.05:53:24.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.05:53:24.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.05:53:24.69#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.05:53:24.69#ibcon#ireg 7 cls_cnt 0 2006.145.05:53:24.69#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.05:53:24.81#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.05:53:24.81#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.05:53:24.83#ibcon#[27=USB\r\n] 2006.145.05:53:24.86#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.05:53:24.86#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.05:53:24.86#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.05:53:24.86#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.05:53:24.86$vck44/vblo=3,649.99 2006.145.05:53:24.86#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.05:53:24.86#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.05:53:24.86#ibcon#ireg 17 cls_cnt 0 2006.145.05:53:24.86#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.05:53:24.86#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.05:53:24.86#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.05:53:24.88#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.05:53:24.92#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.05:53:24.92#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.05:53:24.92#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.05:53:24.92#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.05:53:24.92$vck44/vb=3,4 2006.145.05:53:24.92#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.05:53:24.92#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.05:53:24.92#ibcon#ireg 11 cls_cnt 2 2006.145.05:53:24.92#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.05:53:24.98#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.05:53:24.98#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.05:53:25.00#ibcon#[27=AT03-04\r\n] 2006.145.05:53:25.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.05:53:25.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.05:53:25.05#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.05:53:25.05#ibcon#ireg 7 cls_cnt 0 2006.145.05:53:25.05#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.05:53:25.16#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.05:53:25.16#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.05:53:25.18#ibcon#[27=USB\r\n] 2006.145.05:53:25.21#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.05:53:25.21#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.05:53:25.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.05:53:25.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.05:53:25.21$vck44/vblo=4,679.99 2006.145.05:53:25.21#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.05:53:25.21#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.05:53:25.21#ibcon#ireg 17 cls_cnt 0 2006.145.05:53:25.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.05:53:25.21#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.05:53:25.21#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.05:53:25.23#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.05:53:25.27#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.05:53:25.27#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.05:53:25.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.05:53:25.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.05:53:25.27$vck44/vb=4,4 2006.145.05:53:25.27#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.05:53:25.27#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.05:53:25.27#ibcon#ireg 11 cls_cnt 2 2006.145.05:53:25.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.05:53:25.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.05:53:25.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.05:53:25.35#ibcon#[27=AT04-04\r\n] 2006.145.05:53:25.38#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.05:53:25.38#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.05:53:25.38#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.05:53:25.38#ibcon#ireg 7 cls_cnt 0 2006.145.05:53:25.38#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.05:53:25.50#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.05:53:25.50#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.05:53:25.52#ibcon#[27=USB\r\n] 2006.145.05:53:25.55#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.05:53:25.55#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.05:53:25.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.05:53:25.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.05:53:25.55$vck44/vblo=5,709.99 2006.145.05:53:25.55#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.05:53:25.55#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.05:53:25.55#ibcon#ireg 17 cls_cnt 0 2006.145.05:53:25.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.05:53:25.55#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.05:53:25.55#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.05:53:25.57#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.05:53:25.61#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.05:53:25.61#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.05:53:25.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.05:53:25.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.05:53:25.61$vck44/vb=5,4 2006.145.05:53:25.61#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.05:53:25.61#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.05:53:25.61#ibcon#ireg 11 cls_cnt 2 2006.145.05:53:25.61#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.05:53:25.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.05:53:25.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.05:53:25.69#ibcon#[27=AT05-04\r\n] 2006.145.05:53:25.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.05:53:25.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.05:53:25.72#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.05:53:25.72#ibcon#ireg 7 cls_cnt 0 2006.145.05:53:25.72#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.05:53:25.84#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.05:53:25.84#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.05:53:25.86#ibcon#[27=USB\r\n] 2006.145.05:53:25.89#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.05:53:25.89#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.05:53:25.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.05:53:25.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.05:53:25.89$vck44/vblo=6,719.99 2006.145.05:53:25.89#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.05:53:25.89#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.05:53:25.89#ibcon#ireg 17 cls_cnt 0 2006.145.05:53:25.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.05:53:25.89#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.05:53:25.89#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.05:53:25.91#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.05:53:25.95#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.05:53:25.95#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.05:53:25.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.05:53:25.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.05:53:25.95$vck44/vb=6,4 2006.145.05:53:25.95#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.05:53:25.95#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.05:53:25.95#ibcon#ireg 11 cls_cnt 2 2006.145.05:53:25.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.05:53:26.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.05:53:26.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.05:53:26.03#ibcon#[27=AT06-04\r\n] 2006.145.05:53:26.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.05:53:26.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.05:53:26.06#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.05:53:26.06#ibcon#ireg 7 cls_cnt 0 2006.145.05:53:26.06#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.05:53:26.18#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.05:53:26.18#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.05:53:26.20#ibcon#[27=USB\r\n] 2006.145.05:53:26.23#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.05:53:26.23#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.05:53:26.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.05:53:26.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.05:53:26.23$vck44/vblo=7,734.99 2006.145.05:53:26.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.05:53:26.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.05:53:26.23#ibcon#ireg 17 cls_cnt 0 2006.145.05:53:26.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.05:53:26.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.05:53:26.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.05:53:26.25#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.05:53:26.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.05:53:26.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.05:53:26.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.05:53:26.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.05:53:26.29$vck44/vb=7,4 2006.145.05:53:26.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.05:53:26.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.05:53:26.29#ibcon#ireg 11 cls_cnt 2 2006.145.05:53:26.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.05:53:26.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.05:53:26.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.05:53:26.37#ibcon#[27=AT07-04\r\n] 2006.145.05:53:26.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.05:53:26.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.05:53:26.40#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.05:53:26.40#ibcon#ireg 7 cls_cnt 0 2006.145.05:53:26.40#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.05:53:26.52#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.05:53:26.52#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.05:53:26.54#ibcon#[27=USB\r\n] 2006.145.05:53:26.57#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.05:53:26.57#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.05:53:26.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.05:53:26.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.05:53:26.57$vck44/vblo=8,744.99 2006.145.05:53:26.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.05:53:26.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.05:53:26.57#ibcon#ireg 17 cls_cnt 0 2006.145.05:53:26.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.05:53:26.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.05:53:26.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.05:53:26.59#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.05:53:26.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.05:53:26.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.05:53:26.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.05:53:26.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.05:53:26.63$vck44/vb=8,4 2006.145.05:53:26.63#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.05:53:26.63#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.05:53:26.63#ibcon#ireg 11 cls_cnt 2 2006.145.05:53:26.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.05:53:26.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.05:53:26.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.05:53:26.71#ibcon#[27=AT08-04\r\n] 2006.145.05:53:26.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.05:53:26.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.05:53:26.74#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.05:53:26.74#ibcon#ireg 7 cls_cnt 0 2006.145.05:53:26.74#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.05:53:26.86#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.05:53:26.86#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.05:53:26.88#ibcon#[27=USB\r\n] 2006.145.05:53:26.91#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.05:53:26.91#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.05:53:26.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.05:53:26.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.05:53:26.91$vck44/vabw=wide 2006.145.05:53:26.91#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.05:53:26.91#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.05:53:26.91#ibcon#ireg 8 cls_cnt 0 2006.145.05:53:26.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.05:53:26.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.05:53:26.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.05:53:26.93#ibcon#[25=BW32\r\n] 2006.145.05:53:26.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.05:53:26.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.05:53:26.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.05:53:26.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.05:53:26.96$vck44/vbbw=wide 2006.145.05:53:26.96#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.05:53:26.96#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.05:53:26.96#ibcon#ireg 8 cls_cnt 0 2006.145.05:53:26.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:53:27.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:53:27.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:53:27.05#ibcon#[27=BW32\r\n] 2006.145.05:53:27.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:53:27.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.05:53:27.08#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.05:53:27.08#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.05:53:27.08$setupk4/ifdk4 2006.145.05:53:27.08$ifdk4/lo= 2006.145.05:53:27.08$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.05:53:27.08$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.05:53:27.08$ifdk4/patch= 2006.145.05:53:27.08$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.05:53:27.08$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.05:53:27.08$setupk4/!*+20s 2006.145.05:53:30.34#abcon#<5=/05 4.7 8.1 20.85 591016.1\r\n> 2006.145.05:53:30.36#abcon#{5=INTERFACE CLEAR} 2006.145.05:53:30.42#abcon#[5=S1D000X0/0*\r\n] 2006.145.05:53:40.51#abcon#<5=/05 4.7 8.1 20.85 591016.2\r\n> 2006.145.05:53:40.53#abcon#{5=INTERFACE CLEAR} 2006.145.05:53:40.61#abcon#[5=S1D000X0/0*\r\n] 2006.145.05:53:41.58$setupk4/"tpicd 2006.145.05:53:41.58$setupk4/echo=off 2006.145.05:53:41.58$setupk4/xlog=off 2006.145.05:53:41.58:!2006.145.05:54:00 2006.145.05:53:56.13#trakl#Source acquired 2006.145.05:53:56.13#flagr#flagr/antenna,acquired 2006.145.05:54:00.00:preob 2006.145.05:54:00.13/onsource/TRACKING 2006.145.05:54:00.13:!2006.145.05:54:10 2006.145.05:54:10.00:"tape 2006.145.05:54:10.00:"st=record 2006.145.05:54:10.00:data_valid=on 2006.145.05:54:10.00:midob 2006.145.05:54:11.14/onsource/TRACKING 2006.145.05:54:11.14/wx/20.85,1016.2,60 2006.145.05:54:11.25/cable/+6.5392E-03 2006.145.05:54:12.34/va/01,08,usb,yes,39,42 2006.145.05:54:12.34/va/02,07,usb,yes,41,42 2006.145.05:54:12.34/va/03,08,usb,yes,38,39 2006.145.05:54:12.34/va/04,07,usb,yes,42,45 2006.145.05:54:12.34/va/05,04,usb,yes,37,38 2006.145.05:54:12.34/va/06,04,usb,yes,42,42 2006.145.05:54:12.34/va/07,04,usb,yes,43,44 2006.145.05:54:12.34/va/08,04,usb,yes,37,43 2006.145.05:54:12.57/valo/01,524.99,yes,locked 2006.145.05:54:12.57/valo/02,534.99,yes,locked 2006.145.05:54:12.57/valo/03,564.99,yes,locked 2006.145.05:54:12.57/valo/04,624.99,yes,locked 2006.145.05:54:12.57/valo/05,734.99,yes,locked 2006.145.05:54:12.57/valo/06,814.99,yes,locked 2006.145.05:54:12.57/valo/07,864.99,yes,locked 2006.145.05:54:12.57/valo/08,884.99,yes,locked 2006.145.05:54:13.66/vb/01,03,usb,yes,43,39 2006.145.05:54:13.66/vb/02,04,usb,yes,37,37 2006.145.05:54:13.66/vb/03,04,usb,yes,34,37 2006.145.05:54:13.66/vb/04,04,usb,yes,39,38 2006.145.05:54:13.66/vb/05,04,usb,yes,33,34 2006.145.05:54:13.66/vb/06,04,usb,yes,36,33 2006.145.05:54:13.66/vb/07,04,usb,yes,35,36 2006.145.05:54:13.66/vb/08,04,usb,yes,32,36 2006.145.05:54:13.89/vblo/01,629.99,yes,locked 2006.145.05:54:13.89/vblo/02,634.99,yes,locked 2006.145.05:54:13.89/vblo/03,649.99,yes,locked 2006.145.05:54:13.89/vblo/04,679.99,yes,locked 2006.145.05:54:13.89/vblo/05,709.99,yes,locked 2006.145.05:54:13.89/vblo/06,719.99,yes,locked 2006.145.05:54:13.89/vblo/07,734.99,yes,locked 2006.145.05:54:13.89/vblo/08,744.99,yes,locked 2006.145.05:54:14.04/vabw/8 2006.145.05:54:14.19/vbbw/8 2006.145.05:54:14.28/xfe/off,on,14.2 2006.145.05:54:14.66/ifatt/23,28,28,28 2006.145.05:54:15.07/fmout-gps/S +4.9E-08 2006.145.05:54:15.15:!2006.145.05:54:50 2006.145.05:54:24.14#trakl#Off source 2006.145.05:54:24.14?ERROR st -7 Antenna off-source! 2006.145.05:54:24.14#trakl#az 198.886 el 6.363 azerr*cos(el) 0.0226 elerr -0.0001 2006.145.05:54:24.14#flagr#flagr/antenna,off-source 2006.145.05:54:30.14#trakl#Source re-acquired 2006.145.05:54:30.14#flagr#flagr/antenna,re-acquired 2006.145.05:54:50.01:data_valid=off 2006.145.05:54:50.02:"et 2006.145.05:54:50.02:!+3s 2006.145.05:54:53.03:"tape 2006.145.05:54:53.04:postob 2006.145.05:54:53.25/cable/+6.5398E-03 2006.145.05:54:53.26/wx/20.85,1016.2,58 2006.145.05:54:53.33/fmout-gps/S +5.0E-08 2006.145.05:54:53.33:scan_name=145-0557,jd0605,80 2006.145.05:54:53.33:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.145.05:54:55.14#flagr#flagr/antenna,new-source 2006.145.05:54:55.15:checkk5 2006.145.05:54:55.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.05:54:56.10/chk_autoobs//k5ts2/ autoobs is running! 2006.145.05:54:56.90/chk_autoobs//k5ts3/ autoobs is running! 2006.145.05:54:57.39/chk_autoobs//k5ts4/ autoobs is running! 2006.145.05:54:57.83/chk_obsdata//k5ts1/T1450554??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.05:54:58.32/chk_obsdata//k5ts2/T1450554??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.05:54:58.81/chk_obsdata//k5ts3/T1450554??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.05:54:59.30/chk_obsdata//k5ts4/T1450554??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.05:55:00.55/k5log//k5ts1_log_newline 2006.145.05:55:01.32/k5log//k5ts2_log_newline 2006.145.05:55:02.21/k5log//k5ts3_log_newline 2006.145.05:55:03.07/k5log//k5ts4_log_newline 2006.145.05:55:03.10/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.05:55:03.10:setupk4=1 2006.145.05:55:03.10$setupk4/echo=on 2006.145.05:55:03.10$setupk4/pcalon 2006.145.05:55:03.10$pcalon/"no phase cal control is implemented here 2006.145.05:55:03.10$setupk4/"tpicd=stop 2006.145.05:55:03.10$setupk4/"rec=synch_on 2006.145.05:55:03.10$setupk4/"rec_mode=128 2006.145.05:55:03.10$setupk4/!* 2006.145.05:55:03.10$setupk4/recpk4 2006.145.05:55:03.10$recpk4/recpatch= 2006.145.05:55:03.10$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.05:55:03.10$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.05:55:03.10$setupk4/vck44 2006.145.05:55:03.10$vck44/valo=1,524.99 2006.145.05:55:03.10#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.05:55:03.10#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.05:55:03.10#ibcon#ireg 17 cls_cnt 0 2006.145.05:55:03.10#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:55:03.10#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:55:03.10#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:55:03.14#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.05:55:03.19#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:55:03.19#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:55:03.19#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.05:55:03.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.05:55:03.19$vck44/va=1,8 2006.145.05:55:03.19#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.05:55:03.19#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.05:55:03.19#ibcon#ireg 11 cls_cnt 2 2006.145.05:55:03.19#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:55:03.19#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:55:03.19#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:55:03.21#ibcon#[25=AT01-08\r\n] 2006.145.05:55:03.24#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:55:03.24#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:55:03.24#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.05:55:03.24#ibcon#ireg 7 cls_cnt 0 2006.145.05:55:03.24#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:55:03.36#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:55:03.36#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:55:03.38#ibcon#[25=USB\r\n] 2006.145.05:55:03.41#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:55:03.41#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:55:03.41#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.05:55:03.41#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.05:55:03.41$vck44/valo=2,534.99 2006.145.05:55:03.41#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.05:55:03.41#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.05:55:03.41#ibcon#ireg 17 cls_cnt 0 2006.145.05:55:03.41#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:55:03.41#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:55:03.41#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:55:03.43#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.05:55:03.47#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:55:03.47#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:55:03.47#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.05:55:03.47#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.05:55:03.47$vck44/va=2,7 2006.145.05:55:03.47#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.05:55:03.47#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.05:55:03.47#ibcon#ireg 11 cls_cnt 2 2006.145.05:55:03.47#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:55:03.53#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:55:03.53#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:55:03.55#ibcon#[25=AT02-07\r\n] 2006.145.05:55:03.58#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:55:03.58#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:55:03.58#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.05:55:03.58#ibcon#ireg 7 cls_cnt 0 2006.145.05:55:03.58#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:55:03.70#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:55:03.70#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:55:03.72#ibcon#[25=USB\r\n] 2006.145.05:55:03.75#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:55:03.75#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:55:03.75#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.05:55:03.75#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.05:55:03.75$vck44/valo=3,564.99 2006.145.05:55:03.75#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.05:55:03.75#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.05:55:03.75#ibcon#ireg 17 cls_cnt 0 2006.145.05:55:03.75#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:55:03.75#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:55:03.75#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:55:03.77#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.05:55:03.81#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:55:03.81#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:55:03.81#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.05:55:03.81#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.05:55:03.81$vck44/va=3,8 2006.145.05:55:03.81#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.05:55:03.81#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.05:55:03.81#ibcon#ireg 11 cls_cnt 2 2006.145.05:55:03.81#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:55:03.87#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:55:03.87#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:55:03.89#ibcon#[25=AT03-08\r\n] 2006.145.05:55:03.92#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:55:03.92#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:55:03.92#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.05:55:03.92#ibcon#ireg 7 cls_cnt 0 2006.145.05:55:03.92#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:55:04.04#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:55:04.04#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:55:04.06#ibcon#[25=USB\r\n] 2006.145.05:55:04.09#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:55:04.09#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:55:04.09#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.05:55:04.09#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.05:55:04.09$vck44/valo=4,624.99 2006.145.05:55:04.09#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.05:55:04.09#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.05:55:04.09#ibcon#ireg 17 cls_cnt 0 2006.145.05:55:04.09#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:55:04.09#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:55:04.09#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:55:04.11#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.05:55:04.15#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:55:04.15#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:55:04.15#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.05:55:04.15#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.05:55:04.15$vck44/va=4,7 2006.145.05:55:04.15#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.05:55:04.15#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.05:55:04.15#ibcon#ireg 11 cls_cnt 2 2006.145.05:55:04.15#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:55:04.21#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:55:04.21#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:55:04.23#ibcon#[25=AT04-07\r\n] 2006.145.05:55:04.26#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:55:04.26#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:55:04.26#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.05:55:04.26#ibcon#ireg 7 cls_cnt 0 2006.145.05:55:04.26#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:55:04.38#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:55:04.38#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:55:04.40#ibcon#[25=USB\r\n] 2006.145.05:55:04.45#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:55:04.45#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:55:04.45#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.05:55:04.45#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.05:55:04.45$vck44/valo=5,734.99 2006.145.05:55:04.45#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.05:55:04.45#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.05:55:04.45#ibcon#ireg 17 cls_cnt 0 2006.145.05:55:04.45#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:55:04.45#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:55:04.45#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:55:04.46#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.05:55:04.50#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:55:04.50#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:55:04.50#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.05:55:04.50#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.05:55:04.50$vck44/va=5,4 2006.145.05:55:04.50#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.05:55:04.50#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.05:55:04.50#ibcon#ireg 11 cls_cnt 2 2006.145.05:55:04.50#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:55:04.57#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:55:04.57#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:55:04.59#ibcon#[25=AT05-04\r\n] 2006.145.05:55:04.63#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:55:04.63#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:55:04.63#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.05:55:04.63#ibcon#ireg 7 cls_cnt 0 2006.145.05:55:04.63#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:55:04.74#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:55:04.74#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:55:04.76#ibcon#[25=USB\r\n] 2006.145.05:55:04.79#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:55:04.79#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:55:04.79#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.05:55:04.79#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.05:55:04.79$vck44/valo=6,814.99 2006.145.05:55:04.79#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.05:55:04.79#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.05:55:04.79#ibcon#ireg 17 cls_cnt 0 2006.145.05:55:04.79#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:55:04.79#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:55:04.79#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:55:04.81#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.05:55:04.85#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:55:04.85#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:55:04.85#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.05:55:04.85#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.05:55:04.85$vck44/va=6,4 2006.145.05:55:04.85#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.05:55:04.85#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.05:55:04.85#ibcon#ireg 11 cls_cnt 2 2006.145.05:55:04.85#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:55:04.91#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:55:04.91#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:55:04.93#ibcon#[25=AT06-04\r\n] 2006.145.05:55:04.96#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:55:04.96#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:55:04.96#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.05:55:04.96#ibcon#ireg 7 cls_cnt 0 2006.145.05:55:04.96#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:55:05.08#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:55:05.08#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:55:05.10#ibcon#[25=USB\r\n] 2006.145.05:55:05.13#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:55:05.13#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:55:05.13#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.05:55:05.13#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.05:55:05.13$vck44/valo=7,864.99 2006.145.05:55:05.13#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.05:55:05.13#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.05:55:05.13#ibcon#ireg 17 cls_cnt 0 2006.145.05:55:05.13#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:55:05.13#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:55:05.13#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:55:05.15#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.05:55:05.19#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:55:05.19#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:55:05.19#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.05:55:05.19#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.05:55:05.19$vck44/va=7,4 2006.145.05:55:05.19#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.05:55:05.19#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.05:55:05.19#ibcon#ireg 11 cls_cnt 2 2006.145.05:55:05.19#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:55:05.25#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:55:05.25#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:55:05.27#ibcon#[25=AT07-04\r\n] 2006.145.05:55:05.30#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:55:05.30#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:55:05.30#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.05:55:05.30#ibcon#ireg 7 cls_cnt 0 2006.145.05:55:05.30#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:55:05.42#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:55:05.42#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:55:05.44#ibcon#[25=USB\r\n] 2006.145.05:55:05.47#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:55:05.47#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:55:05.47#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.05:55:05.47#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.05:55:05.47$vck44/valo=8,884.99 2006.145.05:55:05.47#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.05:55:05.47#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.05:55:05.47#ibcon#ireg 17 cls_cnt 0 2006.145.05:55:05.47#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:55:05.47#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:55:05.47#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:55:05.49#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.05:55:05.53#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:55:05.53#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:55:05.53#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.05:55:05.53#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.05:55:05.53$vck44/va=8,4 2006.145.05:55:05.53#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.05:55:05.53#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.05:55:05.53#ibcon#ireg 11 cls_cnt 2 2006.145.05:55:05.53#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.05:55:05.59#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.05:55:05.59#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.05:55:05.61#ibcon#[25=AT08-04\r\n] 2006.145.05:55:05.64#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.05:55:05.64#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.05:55:05.64#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.05:55:05.64#ibcon#ireg 7 cls_cnt 0 2006.145.05:55:05.64#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.05:55:05.76#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.05:55:05.76#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.05:55:05.78#ibcon#[25=USB\r\n] 2006.145.05:55:05.81#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.05:55:05.81#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.05:55:05.81#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.05:55:05.81#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.05:55:05.81$vck44/vblo=1,629.99 2006.145.05:55:05.81#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.05:55:05.81#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.05:55:05.81#ibcon#ireg 17 cls_cnt 0 2006.145.05:55:05.81#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:55:05.81#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:55:05.81#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:55:05.84#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.05:55:05.88#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:55:05.88#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.05:55:05.88#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.05:55:05.88#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.05:55:05.88$vck44/vb=1,3 2006.145.05:55:05.88#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.05:55:05.88#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.05:55:05.88#ibcon#ireg 11 cls_cnt 2 2006.145.05:55:05.88#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:55:05.88#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:55:05.88#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:55:05.90#ibcon#[27=AT01-03\r\n] 2006.145.05:55:05.93#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:55:05.93#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.05:55:05.93#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.05:55:05.93#ibcon#ireg 7 cls_cnt 0 2006.145.05:55:05.93#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:55:06.05#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:55:06.05#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:55:06.07#ibcon#[27=USB\r\n] 2006.145.05:55:06.12#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:55:06.12#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.05:55:06.12#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.05:55:06.12#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.05:55:06.12$vck44/vblo=2,634.99 2006.145.05:55:06.12#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.05:55:06.12#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.05:55:06.12#ibcon#ireg 17 cls_cnt 0 2006.145.05:55:06.12#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:55:06.12#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:55:06.12#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:55:06.13#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.05:55:06.17#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:55:06.17#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.05:55:06.17#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.05:55:06.17#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.05:55:06.17$vck44/vb=2,4 2006.145.05:55:06.17#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.05:55:06.17#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.05:55:06.17#ibcon#ireg 11 cls_cnt 2 2006.145.05:55:06.17#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:55:06.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:55:06.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:55:06.26#ibcon#[27=AT02-04\r\n] 2006.145.05:55:06.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:55:06.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.05:55:06.29#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.05:55:06.29#ibcon#ireg 7 cls_cnt 0 2006.145.05:55:06.29#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:55:06.41#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:55:06.41#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:55:06.43#ibcon#[27=USB\r\n] 2006.145.05:55:06.46#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:55:06.46#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.05:55:06.46#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.05:55:06.46#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.05:55:06.46$vck44/vblo=3,649.99 2006.145.05:55:06.46#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.05:55:06.46#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.05:55:06.46#ibcon#ireg 17 cls_cnt 0 2006.145.05:55:06.46#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:55:06.46#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:55:06.46#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:55:06.48#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.05:55:06.52#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:55:06.52#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.05:55:06.52#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.05:55:06.52#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.05:55:06.52$vck44/vb=3,4 2006.145.05:55:06.52#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.05:55:06.52#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.05:55:06.52#ibcon#ireg 11 cls_cnt 2 2006.145.05:55:06.52#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:55:06.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:55:06.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:55:06.60#ibcon#[27=AT03-04\r\n] 2006.145.05:55:06.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:55:06.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.05:55:06.63#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.05:55:06.63#ibcon#ireg 7 cls_cnt 0 2006.145.05:55:06.63#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:55:06.75#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:55:06.75#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:55:06.77#ibcon#[27=USB\r\n] 2006.145.05:55:06.80#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:55:06.80#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.05:55:06.80#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.05:55:06.80#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.05:55:06.80$vck44/vblo=4,679.99 2006.145.05:55:06.80#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.05:55:06.80#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.05:55:06.80#ibcon#ireg 17 cls_cnt 0 2006.145.05:55:06.80#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:55:06.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:55:06.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:55:06.82#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.05:55:06.86#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:55:06.86#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.05:55:06.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.05:55:06.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.05:55:06.86$vck44/vb=4,4 2006.145.05:55:06.86#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.05:55:06.86#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.05:55:06.86#ibcon#ireg 11 cls_cnt 2 2006.145.05:55:06.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:55:06.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:55:06.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:55:06.94#ibcon#[27=AT04-04\r\n] 2006.145.05:55:06.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:55:06.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.05:55:06.97#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.05:55:06.97#ibcon#ireg 7 cls_cnt 0 2006.145.05:55:06.97#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:55:07.09#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:55:07.09#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:55:07.11#ibcon#[27=USB\r\n] 2006.145.05:55:07.14#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:55:07.14#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.05:55:07.14#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.05:55:07.14#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.05:55:07.14$vck44/vblo=5,709.99 2006.145.05:55:07.14#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.05:55:07.14#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.05:55:07.14#ibcon#ireg 17 cls_cnt 0 2006.145.05:55:07.14#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:55:07.14#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:55:07.14#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:55:07.16#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.05:55:07.20#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:55:07.20#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.05:55:07.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.05:55:07.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.05:55:07.20$vck44/vb=5,4 2006.145.05:55:07.20#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.05:55:07.20#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.05:55:07.20#ibcon#ireg 11 cls_cnt 2 2006.145.05:55:07.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:55:07.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:55:07.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:55:07.28#ibcon#[27=AT05-04\r\n] 2006.145.05:55:07.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:55:07.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.05:55:07.31#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.05:55:07.31#ibcon#ireg 7 cls_cnt 0 2006.145.05:55:07.31#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:55:07.43#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:55:07.43#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:55:07.45#ibcon#[27=USB\r\n] 2006.145.05:55:07.48#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:55:07.48#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.05:55:07.48#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.05:55:07.48#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.05:55:07.48$vck44/vblo=6,719.99 2006.145.05:55:07.48#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.05:55:07.48#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.05:55:07.48#ibcon#ireg 17 cls_cnt 0 2006.145.05:55:07.48#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:55:07.48#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:55:07.48#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:55:07.50#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.05:55:07.54#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:55:07.54#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.05:55:07.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.05:55:07.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.05:55:07.54$vck44/vb=6,4 2006.145.05:55:07.54#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.05:55:07.54#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.05:55:07.54#ibcon#ireg 11 cls_cnt 2 2006.145.05:55:07.54#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:55:07.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:55:07.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:55:07.62#ibcon#[27=AT06-04\r\n] 2006.145.05:55:07.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:55:07.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.05:55:07.65#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.05:55:07.65#ibcon#ireg 7 cls_cnt 0 2006.145.05:55:07.65#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:55:07.77#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:55:07.77#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:55:07.79#ibcon#[27=USB\r\n] 2006.145.05:55:07.82#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:55:07.82#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.05:55:07.82#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.05:55:07.82#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.05:55:07.82$vck44/vblo=7,734.99 2006.145.05:55:07.82#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.05:55:07.82#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.05:55:07.82#ibcon#ireg 17 cls_cnt 0 2006.145.05:55:07.82#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:55:07.82#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:55:07.82#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:55:07.84#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.05:55:07.88#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:55:07.88#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.05:55:07.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.05:55:07.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.05:55:07.88$vck44/vb=7,4 2006.145.05:55:07.88#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.05:55:07.88#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.05:55:07.88#ibcon#ireg 11 cls_cnt 2 2006.145.05:55:07.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:55:07.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:55:07.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:55:07.96#ibcon#[27=AT07-04\r\n] 2006.145.05:55:07.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:55:07.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.05:55:07.99#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.05:55:07.99#ibcon#ireg 7 cls_cnt 0 2006.145.05:55:07.99#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:55:08.11#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:55:08.11#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:55:08.13#ibcon#[27=USB\r\n] 2006.145.05:55:08.16#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:55:08.16#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.05:55:08.16#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.05:55:08.16#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.05:55:08.16$vck44/vblo=8,744.99 2006.145.05:55:08.16#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.05:55:08.16#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.05:55:08.16#ibcon#ireg 17 cls_cnt 0 2006.145.05:55:08.16#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:55:08.16#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:55:08.16#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:55:08.18#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.05:55:08.22#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:55:08.22#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.05:55:08.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.05:55:08.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.05:55:08.22$vck44/vb=8,4 2006.145.05:55:08.22#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.05:55:08.22#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.05:55:08.22#ibcon#ireg 11 cls_cnt 2 2006.145.05:55:08.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:55:08.28#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:55:08.28#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:55:08.30#ibcon#[27=AT08-04\r\n] 2006.145.05:55:08.33#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:55:08.33#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.05:55:08.33#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.05:55:08.33#ibcon#ireg 7 cls_cnt 0 2006.145.05:55:08.33#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:55:08.45#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:55:08.45#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:55:08.47#ibcon#[27=USB\r\n] 2006.145.05:55:08.50#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:55:08.50#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.05:55:08.50#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.05:55:08.50#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.05:55:08.50$vck44/vabw=wide 2006.145.05:55:08.50#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.05:55:08.50#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.05:55:08.50#ibcon#ireg 8 cls_cnt 0 2006.145.05:55:08.50#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:55:08.50#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:55:08.50#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:55:08.52#ibcon#[25=BW32\r\n] 2006.145.05:55:08.55#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:55:08.55#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.05:55:08.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.05:55:08.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.05:55:08.55$vck44/vbbw=wide 2006.145.05:55:08.55#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.05:55:08.55#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.05:55:08.55#ibcon#ireg 8 cls_cnt 0 2006.145.05:55:08.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.05:55:08.62#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.05:55:08.62#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.05:55:08.64#ibcon#[27=BW32\r\n] 2006.145.05:55:08.67#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.05:55:08.67#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.05:55:08.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.05:55:08.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.05:55:08.67$setupk4/ifdk4 2006.145.05:55:08.67$ifdk4/lo= 2006.145.05:55:08.67$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.05:55:08.67$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.05:55:08.67$ifdk4/patch= 2006.145.05:55:08.67$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.05:55:08.67$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.05:55:08.67$setupk4/!*+20s 2006.145.05:55:12.06#abcon#<5=/05 4.6 8.1 20.85 591016.2\r\n> 2006.145.05:55:12.08#abcon#{5=INTERFACE CLEAR} 2006.145.05:55:12.14#abcon#[5=S1D000X0/0*\r\n] 2006.145.05:55:21.14#trakl#Source acquired 2006.145.05:55:22.23#abcon#<5=/05 4.6 8.1 20.85 591016.1\r\n> 2006.145.05:55:22.25#abcon#{5=INTERFACE CLEAR} 2006.145.05:55:22.31#abcon#[5=S1D000X0/0*\r\n] 2006.145.05:55:23.11$setupk4/"tpicd 2006.145.05:55:23.11$setupk4/echo=off 2006.145.05:55:23.11$setupk4/xlog=off 2006.145.05:55:23.11:!2006.145.05:57:26 2006.145.05:55:23.14#flagr#flagr/antenna,acquired 2006.145.05:57:26.00:preob 2006.145.05:57:27.14/onsource/TRACKING 2006.145.05:57:27.14:!2006.145.05:57:36 2006.145.05:57:36.00:"tape 2006.145.05:57:36.00:"st=record 2006.145.05:57:36.00:data_valid=on 2006.145.05:57:36.00:midob 2006.145.05:57:36.14/onsource/TRACKING 2006.145.05:57:36.14/wx/20.84,1016.1,61 2006.145.05:57:36.24/cable/+6.5421E-03 2006.145.05:57:37.33/va/01,08,usb,yes,28,30 2006.145.05:57:37.33/va/02,07,usb,yes,30,31 2006.145.05:57:37.33/va/03,08,usb,yes,27,28 2006.145.05:57:37.33/va/04,07,usb,yes,31,33 2006.145.05:57:37.33/va/05,04,usb,yes,27,28 2006.145.05:57:37.33/va/06,04,usb,yes,30,30 2006.145.05:57:37.33/va/07,04,usb,yes,31,32 2006.145.05:57:37.33/va/08,04,usb,yes,26,32 2006.145.05:57:37.56/valo/01,524.99,yes,locked 2006.145.05:57:37.56/valo/02,534.99,yes,locked 2006.145.05:57:37.56/valo/03,564.99,yes,locked 2006.145.05:57:37.56/valo/04,624.99,yes,locked 2006.145.05:57:37.56/valo/05,734.99,yes,locked 2006.145.05:57:37.56/valo/06,814.99,yes,locked 2006.145.05:57:37.56/valo/07,864.99,yes,locked 2006.145.05:57:37.56/valo/08,884.99,yes,locked 2006.145.05:57:38.65/vb/01,03,usb,yes,35,33 2006.145.05:57:38.65/vb/02,04,usb,yes,31,30 2006.145.05:57:38.65/vb/03,04,usb,yes,28,30 2006.145.05:57:38.65/vb/04,04,usb,yes,32,31 2006.145.05:57:38.65/vb/05,04,usb,yes,25,27 2006.145.05:57:38.65/vb/06,04,usb,yes,29,25 2006.145.05:57:38.65/vb/07,04,usb,yes,28,28 2006.145.05:57:38.65/vb/08,04,usb,yes,26,29 2006.145.05:57:38.88/vblo/01,629.99,yes,locked 2006.145.05:57:38.88/vblo/02,634.99,yes,locked 2006.145.05:57:38.88/vblo/03,649.99,yes,locked 2006.145.05:57:38.88/vblo/04,679.99,yes,locked 2006.145.05:57:38.88/vblo/05,709.99,yes,locked 2006.145.05:57:38.88/vblo/06,719.99,yes,locked 2006.145.05:57:38.88/vblo/07,734.99,yes,locked 2006.145.05:57:38.88/vblo/08,744.99,yes,locked 2006.145.05:57:39.03/vabw/8 2006.145.05:57:39.18/vbbw/8 2006.145.05:57:39.27/xfe/off,on,16.0 2006.145.05:57:39.65/ifatt/23,28,28,28 2006.145.05:57:40.07/fmout-gps/S +5.2E-08 2006.145.05:57:40.11:!2006.145.05:58:56 2006.145.05:58:56.01:data_valid=off 2006.145.05:58:56.02:"et 2006.145.05:58:56.02:!+3s 2006.145.05:58:59.03:"tape 2006.145.05:58:59.03:postob 2006.145.05:58:59.21/cable/+6.5403E-03 2006.145.05:58:59.21/wx/20.83,1016.2,60 2006.145.05:58:59.27/fmout-gps/S +5.3E-08 2006.145.05:58:59.27:scan_name=145-0602,jd0605,110 2006.145.05:58:59.28:source=3c274,123049.42,122328.0,2000.0,ccw 2006.145.05:59:00.14#flagr#flagr/antenna,new-source 2006.145.05:59:00.15:checkk5 2006.145.05:59:00.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.05:59:01.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.05:59:01.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.05:59:01.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.05:59:02.31/chk_obsdata//k5ts1/T1450557??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.05:59:02.76/chk_obsdata//k5ts2/T1450557??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.05:59:03.20/chk_obsdata//k5ts3/T1450557??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.05:59:03.65/chk_obsdata//k5ts4/T1450557??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.05:59:04.40/k5log//k5ts1_log_newline 2006.145.05:59:05.17/k5log//k5ts2_log_newline 2006.145.05:59:05.91/k5log//k5ts3_log_newline 2006.145.05:59:06.65/k5log//k5ts4_log_newline 2006.145.05:59:06.68/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.05:59:06.68:setupk4=1 2006.145.05:59:06.68$setupk4/echo=on 2006.145.05:59:06.68$setupk4/pcalon 2006.145.05:59:06.68$pcalon/"no phase cal control is implemented here 2006.145.05:59:06.68$setupk4/"tpicd=stop 2006.145.05:59:06.68$setupk4/"rec=synch_on 2006.145.05:59:06.68$setupk4/"rec_mode=128 2006.145.05:59:06.68$setupk4/!* 2006.145.05:59:06.68$setupk4/recpk4 2006.145.05:59:06.68$recpk4/recpatch= 2006.145.05:59:06.68$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.05:59:06.68$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.05:59:06.68$setupk4/vck44 2006.145.05:59:06.68$vck44/valo=1,524.99 2006.145.05:59:06.68#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.05:59:06.68#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.05:59:06.68#ibcon#ireg 17 cls_cnt 0 2006.145.05:59:06.68#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.05:59:06.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.05:59:06.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.05:59:06.72#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.05:59:06.77#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.05:59:06.77#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.05:59:06.77#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.05:59:06.77#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.05:59:06.77$vck44/va=1,8 2006.145.05:59:06.77#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.05:59:06.77#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.05:59:06.77#ibcon#ireg 11 cls_cnt 2 2006.145.05:59:06.77#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.05:59:06.77#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.05:59:06.77#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.05:59:06.79#ibcon#[25=AT01-08\r\n] 2006.145.05:59:06.82#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.05:59:06.82#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.05:59:06.82#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.05:59:06.82#ibcon#ireg 7 cls_cnt 0 2006.145.05:59:06.82#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.05:59:06.94#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.05:59:06.94#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.05:59:06.98#ibcon#[25=USB\r\n] 2006.145.05:59:07.00#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.05:59:07.00#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.05:59:07.00#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.05:59:07.00#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.05:59:07.00$vck44/valo=2,534.99 2006.145.05:59:07.00#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.05:59:07.00#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.05:59:07.00#ibcon#ireg 17 cls_cnt 0 2006.145.05:59:07.00#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.05:59:07.00#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.05:59:07.00#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.05:59:07.02#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.05:59:07.06#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.05:59:07.06#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.05:59:07.06#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.05:59:07.06#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.05:59:07.06$vck44/va=2,7 2006.145.05:59:07.06#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.05:59:07.06#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.05:59:07.06#ibcon#ireg 11 cls_cnt 2 2006.145.05:59:07.06#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.05:59:07.12#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.05:59:07.12#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.05:59:07.14#ibcon#[25=AT02-07\r\n] 2006.145.05:59:07.17#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.05:59:07.17#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.05:59:07.17#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.05:59:07.17#ibcon#ireg 7 cls_cnt 0 2006.145.05:59:07.17#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.05:59:07.29#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.05:59:07.29#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.05:59:07.31#ibcon#[25=USB\r\n] 2006.145.05:59:07.34#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.05:59:07.34#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.05:59:07.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.05:59:07.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.05:59:07.34$vck44/valo=3,564.99 2006.145.05:59:07.34#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.05:59:07.34#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.05:59:07.34#ibcon#ireg 17 cls_cnt 0 2006.145.05:59:07.34#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.05:59:07.34#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.05:59:07.34#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.05:59:07.36#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.05:59:07.40#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.05:59:07.40#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.05:59:07.40#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.05:59:07.40#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.05:59:07.40$vck44/va=3,8 2006.145.05:59:07.40#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.05:59:07.40#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.05:59:07.40#ibcon#ireg 11 cls_cnt 2 2006.145.05:59:07.40#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.05:59:07.46#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.05:59:07.46#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.05:59:07.48#ibcon#[25=AT03-08\r\n] 2006.145.05:59:07.51#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.05:59:07.51#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.05:59:07.51#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.05:59:07.51#ibcon#ireg 7 cls_cnt 0 2006.145.05:59:07.51#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.05:59:07.63#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.05:59:07.63#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.05:59:07.65#ibcon#[25=USB\r\n] 2006.145.05:59:07.68#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.05:59:07.68#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.05:59:07.68#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.05:59:07.68#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.05:59:07.68$vck44/valo=4,624.99 2006.145.05:59:07.68#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.05:59:07.68#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.05:59:07.68#ibcon#ireg 17 cls_cnt 0 2006.145.05:59:07.68#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.05:59:07.68#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.05:59:07.68#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.05:59:07.70#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.05:59:07.74#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.05:59:07.74#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.05:59:07.74#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.05:59:07.74#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.05:59:07.74$vck44/va=4,7 2006.145.05:59:07.74#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.05:59:07.74#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.05:59:07.74#ibcon#ireg 11 cls_cnt 2 2006.145.05:59:07.74#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.05:59:07.80#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.05:59:07.80#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.05:59:07.82#ibcon#[25=AT04-07\r\n] 2006.145.05:59:07.85#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.05:59:07.85#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.05:59:07.85#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.05:59:07.85#ibcon#ireg 7 cls_cnt 0 2006.145.05:59:07.85#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.05:59:07.97#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.05:59:07.97#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.05:59:07.99#ibcon#[25=USB\r\n] 2006.145.05:59:08.02#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.05:59:08.02#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.05:59:08.02#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.05:59:08.02#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.05:59:08.02$vck44/valo=5,734.99 2006.145.05:59:08.02#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.05:59:08.02#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.05:59:08.02#ibcon#ireg 17 cls_cnt 0 2006.145.05:59:08.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.05:59:08.02#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.05:59:08.02#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.05:59:08.04#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.05:59:08.08#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.05:59:08.08#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.05:59:08.08#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.05:59:08.08#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.05:59:08.08$vck44/va=5,4 2006.145.05:59:08.08#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.05:59:08.08#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.05:59:08.08#ibcon#ireg 11 cls_cnt 2 2006.145.05:59:08.08#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.05:59:08.14#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.05:59:08.14#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.05:59:08.16#ibcon#[25=AT05-04\r\n] 2006.145.05:59:08.19#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.05:59:08.19#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.05:59:08.19#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.05:59:08.19#ibcon#ireg 7 cls_cnt 0 2006.145.05:59:08.19#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.05:59:08.32#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.05:59:08.32#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.05:59:08.33#ibcon#[25=USB\r\n] 2006.145.05:59:08.36#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.05:59:08.36#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.05:59:08.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.05:59:08.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.05:59:08.36$vck44/valo=6,814.99 2006.145.05:59:08.36#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.05:59:08.36#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.05:59:08.36#ibcon#ireg 17 cls_cnt 0 2006.145.05:59:08.36#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.05:59:08.36#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.05:59:08.36#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.05:59:08.38#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.05:59:08.42#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.05:59:08.42#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.05:59:08.42#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.05:59:08.42#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.05:59:08.42$vck44/va=6,4 2006.145.05:59:08.42#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.05:59:08.42#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.05:59:08.42#ibcon#ireg 11 cls_cnt 2 2006.145.05:59:08.42#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.05:59:08.48#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.05:59:08.48#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.05:59:08.50#ibcon#[25=AT06-04\r\n] 2006.145.05:59:08.53#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.05:59:08.53#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.05:59:08.53#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.05:59:08.53#ibcon#ireg 7 cls_cnt 0 2006.145.05:59:08.53#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.05:59:08.65#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.05:59:08.65#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.05:59:08.67#ibcon#[25=USB\r\n] 2006.145.05:59:08.70#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.05:59:08.70#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.05:59:08.70#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.05:59:08.70#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.05:59:08.70$vck44/valo=7,864.99 2006.145.05:59:08.70#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.05:59:08.70#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.05:59:08.70#ibcon#ireg 17 cls_cnt 0 2006.145.05:59:08.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.05:59:08.70#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.05:59:08.70#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.05:59:08.72#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.05:59:08.76#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.05:59:08.76#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.05:59:08.76#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.05:59:08.76#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.05:59:08.76$vck44/va=7,4 2006.145.05:59:08.76#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.05:59:08.76#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.05:59:08.76#ibcon#ireg 11 cls_cnt 2 2006.145.05:59:08.76#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.05:59:08.82#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.05:59:08.82#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.05:59:08.84#ibcon#[25=AT07-04\r\n] 2006.145.05:59:08.87#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.05:59:08.87#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.05:59:08.87#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.05:59:08.87#ibcon#ireg 7 cls_cnt 0 2006.145.05:59:08.87#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.05:59:08.99#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.05:59:08.99#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.05:59:09.01#ibcon#[25=USB\r\n] 2006.145.05:59:09.04#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.05:59:09.04#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.05:59:09.04#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.05:59:09.04#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.05:59:09.04$vck44/valo=8,884.99 2006.145.05:59:09.04#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.05:59:09.04#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.05:59:09.04#ibcon#ireg 17 cls_cnt 0 2006.145.05:59:09.04#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.05:59:09.04#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.05:59:09.04#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.05:59:09.06#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.05:59:09.10#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.05:59:09.10#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.05:59:09.10#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.05:59:09.10#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.05:59:09.10$vck44/va=8,4 2006.145.05:59:09.10#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.05:59:09.10#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.05:59:09.10#ibcon#ireg 11 cls_cnt 2 2006.145.05:59:09.10#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.05:59:09.16#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.05:59:09.16#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.05:59:09.18#ibcon#[25=AT08-04\r\n] 2006.145.05:59:09.21#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.05:59:09.21#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.05:59:09.21#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.05:59:09.21#ibcon#ireg 7 cls_cnt 0 2006.145.05:59:09.21#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.05:59:09.33#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.05:59:09.33#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.05:59:09.35#ibcon#[25=USB\r\n] 2006.145.05:59:09.38#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.05:59:09.38#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.05:59:09.38#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.05:59:09.38#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.05:59:09.38$vck44/vblo=1,629.99 2006.145.05:59:09.38#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.05:59:09.38#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.05:59:09.38#ibcon#ireg 17 cls_cnt 0 2006.145.05:59:09.38#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.05:59:09.38#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.05:59:09.38#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.05:59:09.40#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.05:59:09.44#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.05:59:09.44#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.05:59:09.44#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.05:59:09.44#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.05:59:09.44$vck44/vb=1,3 2006.145.05:59:09.44#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.05:59:09.44#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.05:59:09.44#ibcon#ireg 11 cls_cnt 2 2006.145.05:59:09.44#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.05:59:09.44#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.05:59:09.44#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.05:59:09.46#ibcon#[27=AT01-03\r\n] 2006.145.05:59:09.49#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.05:59:09.49#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.05:59:09.49#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.05:59:09.49#ibcon#ireg 7 cls_cnt 0 2006.145.05:59:09.49#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.05:59:09.61#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.05:59:09.61#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.05:59:09.63#ibcon#[27=USB\r\n] 2006.145.05:59:09.66#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.05:59:09.66#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.05:59:09.66#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.05:59:09.66#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.05:59:09.66$vck44/vblo=2,634.99 2006.145.05:59:09.66#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.05:59:09.66#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.05:59:09.66#ibcon#ireg 17 cls_cnt 0 2006.145.05:59:09.66#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.05:59:09.66#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.05:59:09.66#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.05:59:09.68#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.05:59:09.72#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.05:59:09.72#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.05:59:09.72#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.05:59:09.72#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.05:59:09.72$vck44/vb=2,4 2006.145.05:59:09.72#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.05:59:09.72#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.05:59:09.72#ibcon#ireg 11 cls_cnt 2 2006.145.05:59:09.72#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.05:59:09.78#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.05:59:09.78#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.05:59:09.80#ibcon#[27=AT02-04\r\n] 2006.145.05:59:09.83#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.05:59:09.83#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.05:59:09.83#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.05:59:09.83#ibcon#ireg 7 cls_cnt 0 2006.145.05:59:09.83#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.05:59:09.95#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.05:59:09.95#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.05:59:09.97#ibcon#[27=USB\r\n] 2006.145.05:59:10.00#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.05:59:10.00#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.05:59:10.00#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.05:59:10.00#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.05:59:10.00$vck44/vblo=3,649.99 2006.145.05:59:10.00#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.05:59:10.00#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.05:59:10.00#ibcon#ireg 17 cls_cnt 0 2006.145.05:59:10.00#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.05:59:10.00#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.05:59:10.00#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.05:59:10.02#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.05:59:10.06#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.05:59:10.06#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.05:59:10.06#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.05:59:10.06#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.05:59:10.06$vck44/vb=3,4 2006.145.05:59:10.06#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.05:59:10.06#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.05:59:10.06#ibcon#ireg 11 cls_cnt 2 2006.145.05:59:10.06#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.05:59:10.12#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.05:59:10.12#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.05:59:10.14#ibcon#[27=AT03-04\r\n] 2006.145.05:59:10.17#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.05:59:10.17#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.05:59:10.17#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.05:59:10.17#ibcon#ireg 7 cls_cnt 0 2006.145.05:59:10.17#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.05:59:10.29#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.05:59:10.29#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.05:59:10.31#ibcon#[27=USB\r\n] 2006.145.05:59:10.34#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.05:59:10.34#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.05:59:10.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.05:59:10.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.05:59:10.34$vck44/vblo=4,679.99 2006.145.05:59:10.34#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.05:59:10.34#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.05:59:10.34#ibcon#ireg 17 cls_cnt 0 2006.145.05:59:10.34#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.05:59:10.34#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.05:59:10.34#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.05:59:10.36#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.05:59:10.40#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.05:59:10.40#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.05:59:10.40#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.05:59:10.40#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.05:59:10.40$vck44/vb=4,4 2006.145.05:59:10.40#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.05:59:10.40#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.05:59:10.40#ibcon#ireg 11 cls_cnt 2 2006.145.05:59:10.40#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.05:59:10.46#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.05:59:10.46#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.05:59:10.48#ibcon#[27=AT04-04\r\n] 2006.145.05:59:10.51#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.05:59:10.51#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.05:59:10.51#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.05:59:10.51#ibcon#ireg 7 cls_cnt 0 2006.145.05:59:10.51#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.05:59:10.63#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.05:59:10.63#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.05:59:10.65#ibcon#[27=USB\r\n] 2006.145.05:59:10.68#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.05:59:10.68#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.05:59:10.68#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.05:59:10.68#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.05:59:10.68$vck44/vblo=5,709.99 2006.145.05:59:10.68#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.05:59:10.68#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.05:59:10.68#ibcon#ireg 17 cls_cnt 0 2006.145.05:59:10.68#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.05:59:10.68#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.05:59:10.68#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.05:59:10.70#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.05:59:10.74#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.05:59:10.74#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.05:59:10.74#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.05:59:10.74#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.05:59:10.74$vck44/vb=5,4 2006.145.05:59:10.74#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.05:59:10.74#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.05:59:10.74#ibcon#ireg 11 cls_cnt 2 2006.145.05:59:10.74#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.05:59:10.80#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.05:59:10.80#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.05:59:10.82#ibcon#[27=AT05-04\r\n] 2006.145.05:59:10.85#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.05:59:10.85#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.05:59:10.85#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.05:59:10.85#ibcon#ireg 7 cls_cnt 0 2006.145.05:59:10.85#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.05:59:10.97#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.05:59:10.97#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.05:59:10.99#ibcon#[27=USB\r\n] 2006.145.05:59:11.02#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.05:59:11.02#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.05:59:11.02#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.05:59:11.02#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.05:59:11.02$vck44/vblo=6,719.99 2006.145.05:59:11.02#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.05:59:11.02#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.05:59:11.02#ibcon#ireg 17 cls_cnt 0 2006.145.05:59:11.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.05:59:11.02#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.05:59:11.02#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.05:59:11.04#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.05:59:11.08#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.05:59:11.08#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.05:59:11.08#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.05:59:11.08#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.05:59:11.08$vck44/vb=6,4 2006.145.05:59:11.08#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.05:59:11.08#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.05:59:11.08#ibcon#ireg 11 cls_cnt 2 2006.145.05:59:11.08#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.05:59:11.14#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.05:59:11.14#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.05:59:11.16#ibcon#[27=AT06-04\r\n] 2006.145.05:59:11.19#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.05:59:11.19#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.05:59:11.19#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.05:59:11.19#ibcon#ireg 7 cls_cnt 0 2006.145.05:59:11.19#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.05:59:11.31#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.05:59:11.31#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.05:59:11.33#ibcon#[27=USB\r\n] 2006.145.05:59:11.36#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.05:59:11.36#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.05:59:11.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.05:59:11.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.05:59:11.36$vck44/vblo=7,734.99 2006.145.05:59:11.36#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.05:59:11.36#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.05:59:11.36#ibcon#ireg 17 cls_cnt 0 2006.145.05:59:11.36#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.05:59:11.36#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.05:59:11.36#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.05:59:11.38#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.05:59:11.42#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.05:59:11.42#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.05:59:11.42#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.05:59:11.42#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.05:59:11.42$vck44/vb=7,4 2006.145.05:59:11.42#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.05:59:11.42#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.05:59:11.42#ibcon#ireg 11 cls_cnt 2 2006.145.05:59:11.42#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.05:59:11.48#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.05:59:11.48#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.05:59:11.50#ibcon#[27=AT07-04\r\n] 2006.145.05:59:11.53#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.05:59:11.53#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.05:59:11.53#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.05:59:11.53#ibcon#ireg 7 cls_cnt 0 2006.145.05:59:11.53#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.05:59:11.65#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.05:59:11.65#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.05:59:11.67#ibcon#[27=USB\r\n] 2006.145.05:59:11.70#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.05:59:11.70#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.05:59:11.70#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.05:59:11.70#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.05:59:11.70$vck44/vblo=8,744.99 2006.145.05:59:11.70#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.05:59:11.70#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.05:59:11.70#ibcon#ireg 17 cls_cnt 0 2006.145.05:59:11.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.05:59:11.70#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.05:59:11.70#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.05:59:11.72#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.05:59:11.76#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.05:59:11.76#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.05:59:11.76#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.05:59:11.76#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.05:59:11.76$vck44/vb=8,4 2006.145.05:59:11.76#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.05:59:11.76#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.05:59:11.76#ibcon#ireg 11 cls_cnt 2 2006.145.05:59:11.76#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.05:59:11.82#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.05:59:11.82#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.05:59:11.84#ibcon#[27=AT08-04\r\n] 2006.145.05:59:11.87#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.05:59:11.87#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.05:59:11.87#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.05:59:11.87#ibcon#ireg 7 cls_cnt 0 2006.145.05:59:11.87#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.05:59:11.99#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.05:59:11.99#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.05:59:12.01#ibcon#[27=USB\r\n] 2006.145.05:59:12.04#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.05:59:12.04#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.05:59:12.04#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.05:59:12.04#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.05:59:12.04$vck44/vabw=wide 2006.145.05:59:12.04#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.05:59:12.04#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.05:59:12.04#ibcon#ireg 8 cls_cnt 0 2006.145.05:59:12.04#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.05:59:12.04#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.05:59:12.04#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.05:59:12.06#ibcon#[25=BW32\r\n] 2006.145.05:59:12.09#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.05:59:12.09#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.05:59:12.09#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.05:59:12.09#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.05:59:12.09$vck44/vbbw=wide 2006.145.05:59:12.09#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.05:59:12.09#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.05:59:12.09#ibcon#ireg 8 cls_cnt 0 2006.145.05:59:12.09#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.05:59:12.16#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.05:59:12.16#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.05:59:12.18#ibcon#[27=BW32\r\n] 2006.145.05:59:12.21#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.05:59:12.21#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.05:59:12.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.05:59:12.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.05:59:12.21$setupk4/ifdk4 2006.145.05:59:12.21$ifdk4/lo= 2006.145.05:59:12.21$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.05:59:12.21$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.05:59:12.21$ifdk4/patch= 2006.145.05:59:12.21$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.05:59:12.21$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.05:59:12.21$setupk4/!*+20s 2006.145.05:59:16.15#abcon#<5=/05 4.4 9.0 20.83 611016.2\r\n> 2006.145.05:59:16.17#abcon#{5=INTERFACE CLEAR} 2006.145.05:59:16.23#abcon#[5=S1D000X0/0*\r\n] 2006.145.05:59:26.32#abcon#<5=/05 4.4 9.0 20.83 621016.2\r\n> 2006.145.05:59:26.34#abcon#{5=INTERFACE CLEAR} 2006.145.05:59:26.40#abcon#[5=S1D000X0/0*\r\n] 2006.145.05:59:26.69$setupk4/"tpicd 2006.145.05:59:26.69$setupk4/echo=off 2006.145.05:59:26.69$setupk4/xlog=off 2006.145.05:59:26.69:!2006.145.06:02:22 2006.145.05:59:56.14#trakl#Source acquired 2006.145.05:59:58.14#flagr#flagr/antenna,acquired 2006.145.06:00:10.14#trakl#Off source 2006.145.06:00:10.14?ERROR st -7 Antenna off-source! 2006.145.06:00:10.14#trakl#az 88.552 el 19.305 azerr*cos(el) 0.0173 elerr -0.0042 2006.145.06:00:10.14#flagr#flagr/antenna,off-source 2006.145.06:00:16.14#trakl#Source re-acquired 2006.145.06:00:16.14#flagr#flagr/antenna,re-acquired 2006.145.06:00:50.13#trakl#Off source 2006.145.06:00:50.13?ERROR st -7 Antenna off-source! 2006.145.06:00:50.13#trakl#az 88.649 el 19.440 azerr*cos(el) 0.0161 elerr -0.0018 2006.145.06:00:52.13#flagr#flagr/antenna,off-source 2006.145.06:00:56.13#trakl#Source re-acquired 2006.145.06:00:58.13#flagr#flagr/antenna,re-acquired 2006.145.06:02:22.00:preob 2006.145.06:02:23.13/onsource/TRACKING 2006.145.06:02:23.13:!2006.145.06:02:32 2006.145.06:02:32.00:"tape 2006.145.06:02:32.00:"st=record 2006.145.06:02:32.00:data_valid=on 2006.145.06:02:32.00:midob 2006.145.06:02:32.14/onsource/TRACKING 2006.145.06:02:32.14/wx/20.84,1016.3,58 2006.145.06:02:32.33/cable/+6.5404E-03 2006.145.06:02:33.42/va/01,08,usb,yes,33,35 2006.145.06:02:33.42/va/02,07,usb,yes,35,36 2006.145.06:02:33.42/va/03,08,usb,yes,32,33 2006.145.06:02:33.42/va/04,07,usb,yes,36,38 2006.145.06:02:33.42/va/05,04,usb,yes,31,32 2006.145.06:02:33.42/va/06,04,usb,yes,35,35 2006.145.06:02:33.42/va/07,04,usb,yes,35,37 2006.145.06:02:33.42/va/08,04,usb,yes,30,36 2006.145.06:02:33.65/valo/01,524.99,yes,locked 2006.145.06:02:33.65/valo/02,534.99,yes,locked 2006.145.06:02:33.65/valo/03,564.99,yes,locked 2006.145.06:02:33.65/valo/04,624.99,yes,locked 2006.145.06:02:33.65/valo/05,734.99,yes,locked 2006.145.06:02:33.65/valo/06,814.99,yes,locked 2006.145.06:02:33.65/valo/07,864.99,yes,locked 2006.145.06:02:33.65/valo/08,884.99,yes,locked 2006.145.06:02:34.74/vb/01,03,usb,yes,46,42 2006.145.06:02:34.74/vb/02,04,usb,yes,40,40 2006.145.06:02:34.74/vb/03,04,usb,yes,36,40 2006.145.06:02:34.74/vb/04,04,usb,yes,41,40 2006.145.06:02:34.74/vb/05,04,usb,yes,32,35 2006.145.06:02:34.74/vb/06,04,usb,yes,38,33 2006.145.06:02:34.74/vb/07,04,usb,yes,37,37 2006.145.06:02:34.74/vb/08,04,usb,yes,34,38 2006.145.06:02:34.98/vblo/01,629.99,yes,locked 2006.145.06:02:34.98/vblo/02,634.99,yes,locked 2006.145.06:02:34.98/vblo/03,649.99,yes,locked 2006.145.06:02:34.98/vblo/04,679.99,yes,locked 2006.145.06:02:34.98/vblo/05,709.99,yes,locked 2006.145.06:02:34.98/vblo/06,719.99,yes,locked 2006.145.06:02:34.98/vblo/07,734.99,yes,locked 2006.145.06:02:34.98/vblo/08,744.99,yes,locked 2006.145.06:02:35.13/vabw/8 2006.145.06:02:35.28/vbbw/8 2006.145.06:02:35.37/xfe/off,on,14.2 2006.145.06:02:35.76/ifatt/23,28,28,28 2006.145.06:02:36.07/fmout-gps/S +5.4E-08 2006.145.06:02:36.11:!2006.145.06:04:22 2006.145.06:04:22.00:data_valid=off 2006.145.06:04:22.00:"et 2006.145.06:04:22.01:!+3s 2006.145.06:04:25.02:"tape 2006.145.06:04:25.02:postob 2006.145.06:04:25.24/cable/+6.5361E-03 2006.145.06:04:25.24/wx/20.82,1016.3,61 2006.145.06:04:25.33/fmout-gps/S +5.4E-08 2006.145.06:04:25.33:scan_name=145-0611,jd0605,60 2006.145.06:04:25.34:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.145.06:04:26.14#flagr#flagr/antenna,new-source 2006.145.06:04:26.14:checkk5 2006.145.06:04:26.57/chk_autoobs//k5ts1/ autoobs is running! 2006.145.06:04:26.99/chk_autoobs//k5ts2/ autoobs is running! 2006.145.06:04:27.42/chk_autoobs//k5ts3/ autoobs is running! 2006.145.06:04:27.86/chk_autoobs//k5ts4/ autoobs is running! 2006.145.06:04:28.29/chk_obsdata//k5ts1/T1450602??a.dat file size is correct (nominal:440MB, actual:436MB). 2006.145.06:04:28.71/chk_obsdata//k5ts2/T1450602??b.dat file size is correct (nominal:440MB, actual:436MB). 2006.145.06:04:29.15/chk_obsdata//k5ts3/T1450602??c.dat file size is correct (nominal:440MB, actual:436MB). 2006.145.06:04:29.59/chk_obsdata//k5ts4/T1450602??d.dat file size is correct (nominal:440MB, actual:436MB). 2006.145.06:04:30.39/k5log//k5ts1_log_newline 2006.145.06:04:31.13/k5log//k5ts2_log_newline 2006.145.06:04:31.87/k5log//k5ts3_log_newline 2006.145.06:04:32.60/k5log//k5ts4_log_newline 2006.145.06:04:32.63/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.06:04:32.63:setupk4=1 2006.145.06:04:32.63$setupk4/echo=on 2006.145.06:04:32.63$setupk4/pcalon 2006.145.06:04:32.63$pcalon/"no phase cal control is implemented here 2006.145.06:04:32.63$setupk4/"tpicd=stop 2006.145.06:04:32.63$setupk4/"rec=synch_on 2006.145.06:04:32.63$setupk4/"rec_mode=128 2006.145.06:04:32.63$setupk4/!* 2006.145.06:04:32.63$setupk4/recpk4 2006.145.06:04:32.63$recpk4/recpatch= 2006.145.06:04:32.64$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.06:04:32.64$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.06:04:32.64$setupk4/vck44 2006.145.06:04:32.64$vck44/valo=1,524.99 2006.145.06:04:32.64#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.06:04:32.64#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.06:04:32.64#ibcon#ireg 17 cls_cnt 0 2006.145.06:04:32.64#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.06:04:32.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.06:04:32.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.06:04:32.67#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.06:04:32.72#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.06:04:32.72#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.06:04:32.72#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.06:04:32.72#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.06:04:32.72$vck44/va=1,8 2006.145.06:04:32.72#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.06:04:32.72#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.06:04:32.72#ibcon#ireg 11 cls_cnt 2 2006.145.06:04:32.72#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.06:04:32.72#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.06:04:32.72#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.06:04:32.74#ibcon#[25=AT01-08\r\n] 2006.145.06:04:32.77#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.06:04:32.77#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.06:04:32.77#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.06:04:32.77#ibcon#ireg 7 cls_cnt 0 2006.145.06:04:32.77#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.06:04:32.89#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.06:04:32.89#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.06:04:32.91#ibcon#[25=USB\r\n] 2006.145.06:04:32.94#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.06:04:32.94#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.06:04:32.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.06:04:32.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.06:04:32.94$vck44/valo=2,534.99 2006.145.06:04:32.94#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.06:04:32.94#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.06:04:32.94#ibcon#ireg 17 cls_cnt 0 2006.145.06:04:32.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.06:04:32.94#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.06:04:32.94#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.06:04:32.97#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.06:04:33.01#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.06:04:33.01#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.06:04:33.01#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.06:04:33.01#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.06:04:33.01$vck44/va=2,7 2006.145.06:04:33.01#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.06:04:33.01#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.06:04:33.01#ibcon#ireg 11 cls_cnt 2 2006.145.06:04:33.01#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.06:04:33.06#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.06:04:33.06#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.06:04:33.08#ibcon#[25=AT02-07\r\n] 2006.145.06:04:33.11#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.06:04:33.11#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.06:04:33.11#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.06:04:33.11#ibcon#ireg 7 cls_cnt 0 2006.145.06:04:33.11#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.06:04:33.23#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.06:04:33.23#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.06:04:33.25#ibcon#[25=USB\r\n] 2006.145.06:04:33.28#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.06:04:33.28#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.06:04:33.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.06:04:33.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.06:04:33.28$vck44/valo=3,564.99 2006.145.06:04:33.28#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.06:04:33.28#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.06:04:33.28#ibcon#ireg 17 cls_cnt 0 2006.145.06:04:33.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.06:04:33.28#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.06:04:33.28#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.06:04:33.30#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.06:04:33.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.06:04:33.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.06:04:33.34#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.06:04:33.34#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.06:04:33.34$vck44/va=3,8 2006.145.06:04:33.34#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.06:04:33.34#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.06:04:33.34#ibcon#ireg 11 cls_cnt 2 2006.145.06:04:33.34#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.06:04:33.40#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.06:04:33.40#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.06:04:33.42#ibcon#[25=AT03-08\r\n] 2006.145.06:04:33.45#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.06:04:33.45#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.06:04:33.45#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.06:04:33.45#ibcon#ireg 7 cls_cnt 0 2006.145.06:04:33.45#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.06:04:33.57#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.06:04:33.57#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.06:04:33.59#ibcon#[25=USB\r\n] 2006.145.06:04:33.62#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.06:04:33.62#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.06:04:33.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.06:04:33.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.06:04:33.62$vck44/valo=4,624.99 2006.145.06:04:33.62#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.06:04:33.62#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.06:04:33.62#ibcon#ireg 17 cls_cnt 0 2006.145.06:04:33.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.06:04:33.62#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.06:04:33.62#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.06:04:33.64#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.06:04:33.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.06:04:33.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.06:04:33.68#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.06:04:33.68#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.06:04:33.68$vck44/va=4,7 2006.145.06:04:33.68#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.06:04:33.68#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.06:04:33.68#ibcon#ireg 11 cls_cnt 2 2006.145.06:04:33.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.06:04:33.74#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.06:04:33.74#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.06:04:33.76#ibcon#[25=AT04-07\r\n] 2006.145.06:04:33.79#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.06:04:33.79#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.06:04:33.79#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.06:04:33.79#ibcon#ireg 7 cls_cnt 0 2006.145.06:04:33.79#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.06:04:33.91#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.06:04:33.91#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.06:04:33.93#ibcon#[25=USB\r\n] 2006.145.06:04:33.96#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.06:04:33.96#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.06:04:33.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.06:04:33.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.06:04:33.96$vck44/valo=5,734.99 2006.145.06:04:33.96#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.06:04:33.96#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.06:04:33.96#ibcon#ireg 17 cls_cnt 0 2006.145.06:04:33.96#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.06:04:33.96#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.06:04:33.96#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.06:04:33.98#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.06:04:34.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.06:04:34.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.06:04:34.02#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.06:04:34.02#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.06:04:34.02$vck44/va=5,4 2006.145.06:04:34.02#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.06:04:34.02#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.06:04:34.02#ibcon#ireg 11 cls_cnt 2 2006.145.06:04:34.02#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.06:04:34.08#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.06:04:34.08#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.06:04:34.10#ibcon#[25=AT05-04\r\n] 2006.145.06:04:34.13#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.06:04:34.13#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.06:04:34.13#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.06:04:34.13#ibcon#ireg 7 cls_cnt 0 2006.145.06:04:34.13#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.06:04:34.25#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.06:04:34.25#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.06:04:34.27#ibcon#[25=USB\r\n] 2006.145.06:04:34.30#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.06:04:34.30#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.06:04:34.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.06:04:34.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.06:04:34.30$vck44/valo=6,814.99 2006.145.06:04:34.30#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.06:04:34.30#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.06:04:34.30#ibcon#ireg 17 cls_cnt 0 2006.145.06:04:34.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.06:04:34.30#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.06:04:34.30#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.06:04:34.32#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.06:04:34.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.06:04:34.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.06:04:34.36#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.06:04:34.36#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.06:04:34.36$vck44/va=6,4 2006.145.06:04:34.36#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.06:04:34.36#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.06:04:34.36#ibcon#ireg 11 cls_cnt 2 2006.145.06:04:34.36#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.06:04:34.42#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.06:04:34.42#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.06:04:34.44#ibcon#[25=AT06-04\r\n] 2006.145.06:04:34.47#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.06:04:34.47#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.06:04:34.47#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.06:04:34.47#ibcon#ireg 7 cls_cnt 0 2006.145.06:04:34.47#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.06:04:34.59#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.06:04:34.59#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.06:04:34.61#ibcon#[25=USB\r\n] 2006.145.06:04:34.64#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.06:04:34.64#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.06:04:34.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.06:04:34.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.06:04:34.64$vck44/valo=7,864.99 2006.145.06:04:34.64#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.06:04:34.64#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.06:04:34.64#ibcon#ireg 17 cls_cnt 0 2006.145.06:04:34.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.06:04:34.64#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.06:04:34.64#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.06:04:34.66#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.06:04:34.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.06:04:34.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.06:04:34.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.06:04:34.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.06:04:34.70$vck44/va=7,4 2006.145.06:04:34.70#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.06:04:34.70#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.06:04:34.70#ibcon#ireg 11 cls_cnt 2 2006.145.06:04:34.70#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.06:04:34.76#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.06:04:34.76#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.06:04:34.78#ibcon#[25=AT07-04\r\n] 2006.145.06:04:34.81#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.06:04:34.81#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.06:04:34.81#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.06:04:34.81#ibcon#ireg 7 cls_cnt 0 2006.145.06:04:34.81#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.06:04:34.93#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.06:04:34.93#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.06:04:34.95#ibcon#[25=USB\r\n] 2006.145.06:04:34.98#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.06:04:34.98#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.06:04:34.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.06:04:34.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.06:04:34.98$vck44/valo=8,884.99 2006.145.06:04:34.98#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.06:04:34.98#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.06:04:34.98#ibcon#ireg 17 cls_cnt 0 2006.145.06:04:34.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.06:04:34.98#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.06:04:34.98#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.06:04:35.00#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.06:04:35.04#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.06:04:35.04#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.06:04:35.04#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.06:04:35.04#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.06:04:35.04$vck44/va=8,4 2006.145.06:04:35.04#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.06:04:35.04#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.06:04:35.04#ibcon#ireg 11 cls_cnt 2 2006.145.06:04:35.04#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.06:04:35.10#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.06:04:35.10#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.06:04:35.12#ibcon#[25=AT08-04\r\n] 2006.145.06:04:35.15#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.06:04:35.15#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.06:04:35.15#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.06:04:35.15#ibcon#ireg 7 cls_cnt 0 2006.145.06:04:35.15#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.06:04:35.27#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.06:04:35.27#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.06:04:35.29#ibcon#[25=USB\r\n] 2006.145.06:04:35.32#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.06:04:35.32#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.06:04:35.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.06:04:35.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.06:04:35.32$vck44/vblo=1,629.99 2006.145.06:04:35.32#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.06:04:35.32#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.06:04:35.32#ibcon#ireg 17 cls_cnt 0 2006.145.06:04:35.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.06:04:35.32#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.06:04:35.32#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.06:04:35.34#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.06:04:35.38#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.06:04:35.38#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.06:04:35.38#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.06:04:35.38#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.06:04:35.38$vck44/vb=1,3 2006.145.06:04:35.38#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.06:04:35.38#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.06:04:35.38#ibcon#ireg 11 cls_cnt 2 2006.145.06:04:35.38#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.06:04:35.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.06:04:35.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.06:04:35.40#ibcon#[27=AT01-03\r\n] 2006.145.06:04:35.43#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.06:04:35.43#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.06:04:35.43#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.06:04:35.43#ibcon#ireg 7 cls_cnt 0 2006.145.06:04:35.43#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.06:04:35.55#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.06:04:35.55#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.06:04:35.57#ibcon#[27=USB\r\n] 2006.145.06:04:35.60#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.06:04:35.60#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.06:04:35.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.06:04:35.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.06:04:35.60$vck44/vblo=2,634.99 2006.145.06:04:35.60#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.06:04:35.60#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.06:04:35.60#ibcon#ireg 17 cls_cnt 0 2006.145.06:04:35.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.06:04:35.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.06:04:35.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.06:04:35.62#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.06:04:35.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.06:04:35.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.06:04:35.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.06:04:35.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.06:04:35.66$vck44/vb=2,4 2006.145.06:04:35.66#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.06:04:35.66#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.06:04:35.66#ibcon#ireg 11 cls_cnt 2 2006.145.06:04:35.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.06:04:35.72#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.06:04:35.72#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.06:04:35.74#ibcon#[27=AT02-04\r\n] 2006.145.06:04:35.77#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.06:04:35.77#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.06:04:35.77#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.06:04:35.77#ibcon#ireg 7 cls_cnt 0 2006.145.06:04:35.77#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.06:04:35.89#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.06:04:35.89#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.06:04:35.91#ibcon#[27=USB\r\n] 2006.145.06:04:35.94#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.06:04:35.94#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.06:04:35.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.06:04:35.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.06:04:35.94$vck44/vblo=3,649.99 2006.145.06:04:35.94#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.06:04:35.94#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.06:04:35.94#ibcon#ireg 17 cls_cnt 0 2006.145.06:04:35.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.06:04:35.94#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.06:04:35.94#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.06:04:35.96#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.06:04:36.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.06:04:36.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.06:04:36.00#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.06:04:36.00#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.06:04:36.00$vck44/vb=3,4 2006.145.06:04:36.00#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.06:04:36.00#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.06:04:36.00#ibcon#ireg 11 cls_cnt 2 2006.145.06:04:36.00#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.06:04:36.06#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.06:04:36.06#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.06:04:36.08#ibcon#[27=AT03-04\r\n] 2006.145.06:04:36.11#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.06:04:36.11#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.06:04:36.11#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.06:04:36.11#ibcon#ireg 7 cls_cnt 0 2006.145.06:04:36.11#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.06:04:36.23#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.06:04:36.23#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.06:04:36.25#ibcon#[27=USB\r\n] 2006.145.06:04:36.28#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.06:04:36.28#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.06:04:36.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.06:04:36.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.06:04:36.28$vck44/vblo=4,679.99 2006.145.06:04:36.28#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.06:04:36.28#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.06:04:36.28#ibcon#ireg 17 cls_cnt 0 2006.145.06:04:36.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.06:04:36.28#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.06:04:36.28#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.06:04:36.30#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.06:04:36.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.06:04:36.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.06:04:36.34#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.06:04:36.34#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.06:04:36.34$vck44/vb=4,4 2006.145.06:04:36.34#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.06:04:36.34#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.06:04:36.34#ibcon#ireg 11 cls_cnt 2 2006.145.06:04:36.34#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.06:04:36.40#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.06:04:36.40#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.06:04:36.42#ibcon#[27=AT04-04\r\n] 2006.145.06:04:36.45#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.06:04:36.45#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.06:04:36.45#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.06:04:36.45#ibcon#ireg 7 cls_cnt 0 2006.145.06:04:36.45#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.06:04:36.59#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.06:04:36.59#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.06:04:36.60#ibcon#[27=USB\r\n] 2006.145.06:04:36.63#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.06:04:36.63#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.06:04:36.63#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.06:04:36.63#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.06:04:36.63$vck44/vblo=5,709.99 2006.145.06:04:36.63#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.06:04:36.63#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.06:04:36.63#ibcon#ireg 17 cls_cnt 0 2006.145.06:04:36.63#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.06:04:36.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.06:04:36.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.06:04:36.65#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.06:04:36.69#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.06:04:36.69#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.06:04:36.69#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.06:04:36.69#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.06:04:36.69$vck44/vb=5,4 2006.145.06:04:36.69#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.06:04:36.69#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.06:04:36.69#ibcon#ireg 11 cls_cnt 2 2006.145.06:04:36.69#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.06:04:36.75#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.06:04:36.75#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.06:04:36.77#ibcon#[27=AT05-04\r\n] 2006.145.06:04:36.80#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.06:04:36.80#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.06:04:36.80#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.06:04:36.80#ibcon#ireg 7 cls_cnt 0 2006.145.06:04:36.80#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.06:04:36.92#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.06:04:36.92#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.06:04:36.94#ibcon#[27=USB\r\n] 2006.145.06:04:36.97#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.06:04:36.97#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.06:04:36.97#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.06:04:36.97#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.06:04:36.97$vck44/vblo=6,719.99 2006.145.06:04:36.97#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.06:04:36.97#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.06:04:36.97#ibcon#ireg 17 cls_cnt 0 2006.145.06:04:36.97#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.06:04:36.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.06:04:36.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.06:04:36.99#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.06:04:37.03#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.06:04:37.03#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.06:04:37.03#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.06:04:37.03#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.06:04:37.03$vck44/vb=6,4 2006.145.06:04:37.03#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.06:04:37.03#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.06:04:37.03#ibcon#ireg 11 cls_cnt 2 2006.145.06:04:37.03#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.06:04:37.09#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.06:04:37.09#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.06:04:37.11#ibcon#[27=AT06-04\r\n] 2006.145.06:04:37.14#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.06:04:37.14#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.06:04:37.14#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.06:04:37.14#ibcon#ireg 7 cls_cnt 0 2006.145.06:04:37.14#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.06:04:37.26#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.06:04:37.26#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.06:04:37.28#ibcon#[27=USB\r\n] 2006.145.06:04:37.31#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.06:04:37.31#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.06:04:37.31#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.06:04:37.31#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.06:04:37.31$vck44/vblo=7,734.99 2006.145.06:04:37.31#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.06:04:37.31#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.06:04:37.31#ibcon#ireg 17 cls_cnt 0 2006.145.06:04:37.31#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.06:04:37.31#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.06:04:37.31#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.06:04:37.33#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.06:04:37.37#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.06:04:37.37#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.06:04:37.37#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.06:04:37.37#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.06:04:37.37$vck44/vb=7,4 2006.145.06:04:37.37#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.06:04:37.37#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.06:04:37.37#ibcon#ireg 11 cls_cnt 2 2006.145.06:04:37.37#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.06:04:37.43#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.06:04:37.43#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.06:04:37.45#ibcon#[27=AT07-04\r\n] 2006.145.06:04:37.48#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.06:04:37.48#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.06:04:37.48#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.06:04:37.48#ibcon#ireg 7 cls_cnt 0 2006.145.06:04:37.48#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.06:04:37.60#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.06:04:37.60#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.06:04:37.62#ibcon#[27=USB\r\n] 2006.145.06:04:37.65#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.06:04:37.65#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.06:04:37.65#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.06:04:37.65#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.06:04:37.65$vck44/vblo=8,744.99 2006.145.06:04:37.65#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.06:04:37.65#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.06:04:37.65#ibcon#ireg 17 cls_cnt 0 2006.145.06:04:37.65#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.06:04:37.65#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.06:04:37.65#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.06:04:37.67#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.06:04:37.71#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.06:04:37.71#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.06:04:37.71#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.06:04:37.71#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.06:04:37.71$vck44/vb=8,4 2006.145.06:04:37.71#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.06:04:37.71#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.06:04:37.71#ibcon#ireg 11 cls_cnt 2 2006.145.06:04:37.71#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.06:04:37.77#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.06:04:37.77#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.06:04:37.79#ibcon#[27=AT08-04\r\n] 2006.145.06:04:37.82#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.06:04:37.82#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.06:04:37.82#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.06:04:37.82#ibcon#ireg 7 cls_cnt 0 2006.145.06:04:37.82#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.06:04:37.94#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.06:04:37.94#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.06:04:37.96#ibcon#[27=USB\r\n] 2006.145.06:04:37.99#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.06:04:37.99#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.06:04:37.99#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.06:04:37.99#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.06:04:37.99$vck44/vabw=wide 2006.145.06:04:37.99#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.06:04:37.99#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.06:04:37.99#ibcon#ireg 8 cls_cnt 0 2006.145.06:04:37.99#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.06:04:37.99#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.06:04:37.99#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.06:04:38.01#ibcon#[25=BW32\r\n] 2006.145.06:04:38.04#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.06:04:38.04#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.06:04:38.04#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.06:04:38.04#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.06:04:38.04$vck44/vbbw=wide 2006.145.06:04:38.04#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.06:04:38.04#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.06:04:38.04#ibcon#ireg 8 cls_cnt 0 2006.145.06:04:38.04#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.06:04:38.11#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.06:04:38.11#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.06:04:38.13#ibcon#[27=BW32\r\n] 2006.145.06:04:38.16#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.06:04:38.16#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.06:04:38.16#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.06:04:38.16#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.06:04:38.16$setupk4/ifdk4 2006.145.06:04:38.16$ifdk4/lo= 2006.145.06:04:38.16$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.06:04:38.16$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.06:04:38.16$ifdk4/patch= 2006.145.06:04:38.16$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.06:04:38.16$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.06:04:38.16$setupk4/!*+20s 2006.145.06:04:41.70#abcon#<5=/05 4.8 9.0 20.82 581016.2\r\n> 2006.145.06:04:41.72#abcon#{5=INTERFACE CLEAR} 2006.145.06:04:41.78#abcon#[5=S1D000X0/0*\r\n] 2006.145.06:04:51.87#abcon#<5=/05 4.9 9.0 20.81 591016.2\r\n> 2006.145.06:04:51.89#abcon#{5=INTERFACE CLEAR} 2006.145.06:04:51.95#abcon#[5=S1D000X0/0*\r\n] 2006.145.06:04:52.64$setupk4/"tpicd 2006.145.06:04:52.64$setupk4/echo=off 2006.145.06:04:52.64$setupk4/xlog=off 2006.145.06:04:52.64:!2006.145.06:11:06 2006.145.06:05:05.14#trakl#Source acquired 2006.145.06:05:06.14#flagr#flagr/antenna,acquired 2006.145.06:09:39.13#trakl#Off source 2006.145.06:09:39.13?ERROR st -7 Antenna off-source! 2006.145.06:09:39.13#trakl#az 183.334 el 42.116 azerr*cos(el) 0.0169 elerr 0.0001 2006.145.06:09:39.13#flagr#flagr/antenna,off-source 2006.145.06:09:45.13#trakl#Source re-acquired 2006.145.06:09:45.13#flagr#flagr/antenna,re-acquired 2006.145.06:11:06.00:preob 2006.145.06:11:07.14/onsource/TRACKING 2006.145.06:11:07.14:!2006.145.06:11:16 2006.145.06:11:16.00:"tape 2006.145.06:11:16.00:"st=record 2006.145.06:11:16.00:data_valid=on 2006.145.06:11:16.00:midob 2006.145.06:11:16.14/onsource/TRACKING 2006.145.06:11:16.14/wx/20.62,1016.3,61 2006.145.06:11:16.32/cable/+6.5406E-03 2006.145.06:11:17.41/va/01,08,usb,yes,28,31 2006.145.06:11:17.41/va/02,07,usb,yes,30,31 2006.145.06:11:17.41/va/03,08,usb,yes,28,29 2006.145.06:11:17.41/va/04,07,usb,yes,31,33 2006.145.06:11:17.41/va/05,04,usb,yes,27,28 2006.145.06:11:17.41/va/06,04,usb,yes,31,31 2006.145.06:11:17.41/va/07,04,usb,yes,31,32 2006.145.06:11:17.41/va/08,04,usb,yes,26,32 2006.145.06:11:17.64/valo/01,524.99,yes,locked 2006.145.06:11:17.64/valo/02,534.99,yes,locked 2006.145.06:11:17.64/valo/03,564.99,yes,locked 2006.145.06:11:17.64/valo/04,624.99,yes,locked 2006.145.06:11:17.64/valo/05,734.99,yes,locked 2006.145.06:11:17.64/valo/06,814.99,yes,locked 2006.145.06:11:17.64/valo/07,864.99,yes,locked 2006.145.06:11:17.64/valo/08,884.99,yes,locked 2006.145.06:11:18.73/vb/01,03,usb,yes,36,33 2006.145.06:11:18.73/vb/02,04,usb,yes,31,31 2006.145.06:11:18.73/vb/03,04,usb,yes,28,31 2006.145.06:11:18.73/vb/04,04,usb,yes,32,31 2006.145.06:11:18.73/vb/05,04,usb,yes,25,28 2006.145.06:11:18.73/vb/06,04,usb,yes,30,26 2006.145.06:11:18.73/vb/07,04,usb,yes,29,29 2006.145.06:11:18.73/vb/08,04,usb,yes,27,30 2006.145.06:11:18.96/vblo/01,629.99,yes,locked 2006.145.06:11:18.96/vblo/02,634.99,yes,locked 2006.145.06:11:18.96/vblo/03,649.99,yes,locked 2006.145.06:11:18.96/vblo/04,679.99,yes,locked 2006.145.06:11:18.96/vblo/05,709.99,yes,locked 2006.145.06:11:18.96/vblo/06,719.99,yes,locked 2006.145.06:11:18.96/vblo/07,734.99,yes,locked 2006.145.06:11:18.96/vblo/08,744.99,yes,locked 2006.145.06:11:19.11/vabw/8 2006.145.06:11:19.26/vbbw/8 2006.145.06:11:19.35/xfe/off,on,14.2 2006.145.06:11:19.73/ifatt/23,28,28,28 2006.145.06:11:20.07/fmout-gps/S +5.5E-08 2006.145.06:11:20.11:!2006.145.06:12:16 2006.145.06:12:16.00:data_valid=off 2006.145.06:12:16.00:"et 2006.145.06:12:16.00:!+3s 2006.145.06:12:19.02:"tape 2006.145.06:12:19.02:postob 2006.145.06:12:19.14/cable/+6.5375E-03 2006.145.06:12:19.14/wx/20.61,1016.3,61 2006.145.06:12:20.08/fmout-gps/S +5.6E-08 2006.145.06:12:20.08:scan_name=145-0614,jd0605,340 2006.145.06:12:20.08:source=cta26,033930.94,-014635.8,2000.0,ccw 2006.145.06:12:20.14#flagr#flagr/antenna,new-source 2006.145.06:12:21.14:checkk5 2006.145.06:12:21.57/chk_autoobs//k5ts1/ autoobs is running! 2006.145.06:12:22.00/chk_autoobs//k5ts2/ autoobs is running! 2006.145.06:12:22.45/chk_autoobs//k5ts3/ autoobs is running! 2006.145.06:12:22.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.06:12:23.32/chk_obsdata//k5ts1/T1450611??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.145.06:12:23.75/chk_obsdata//k5ts2/T1450611??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.145.06:12:24.19/chk_obsdata//k5ts3/T1450611??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.145.06:12:24.63/chk_obsdata//k5ts4/T1450611??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.145.06:12:25.40/k5log//k5ts1_log_newline 2006.145.06:12:26.15/k5log//k5ts2_log_newline 2006.145.06:12:26.89/k5log//k5ts3_log_newline 2006.145.06:12:27.62/k5log//k5ts4_log_newline 2006.145.06:12:27.64/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.06:12:27.64:setupk4=1 2006.145.06:12:27.64$setupk4/echo=on 2006.145.06:12:27.64$setupk4/pcalon 2006.145.06:12:27.64$pcalon/"no phase cal control is implemented here 2006.145.06:12:27.64$setupk4/"tpicd=stop 2006.145.06:12:27.64$setupk4/"rec=synch_on 2006.145.06:12:27.64$setupk4/"rec_mode=128 2006.145.06:12:27.64$setupk4/!* 2006.145.06:12:27.64$setupk4/recpk4 2006.145.06:12:27.64$recpk4/recpatch= 2006.145.06:12:27.64$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.06:12:27.64$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.06:12:27.64$setupk4/vck44 2006.145.06:12:27.64$vck44/valo=1,524.99 2006.145.06:12:27.64#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.06:12:27.64#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.06:12:27.64#ibcon#ireg 17 cls_cnt 0 2006.145.06:12:27.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.06:12:27.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.06:12:27.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.06:12:27.66#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.06:12:27.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.06:12:27.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.06:12:27.71#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.06:12:27.71#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.06:12:27.71$vck44/va=1,8 2006.145.06:12:27.71#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.06:12:27.71#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.06:12:27.71#ibcon#ireg 11 cls_cnt 2 2006.145.06:12:27.71#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.06:12:27.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.06:12:27.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.06:12:27.73#ibcon#[25=AT01-08\r\n] 2006.145.06:12:27.76#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.06:12:27.76#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.06:12:27.76#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.06:12:27.76#ibcon#ireg 7 cls_cnt 0 2006.145.06:12:27.76#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.06:12:27.88#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.06:12:27.88#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.06:12:27.90#ibcon#[25=USB\r\n] 2006.145.06:12:27.95#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.06:12:27.95#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.06:12:27.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.06:12:27.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.06:12:27.95$vck44/valo=2,534.99 2006.145.06:12:27.95#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.06:12:27.95#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.06:12:27.95#ibcon#ireg 17 cls_cnt 0 2006.145.06:12:27.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.06:12:27.95#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.06:12:27.95#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.06:12:27.96#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.06:12:28.00#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.06:12:28.00#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.06:12:28.00#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.06:12:28.00#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.06:12:28.00$vck44/va=2,7 2006.145.06:12:28.00#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.06:12:28.00#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.06:12:28.00#ibcon#ireg 11 cls_cnt 2 2006.145.06:12:28.00#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.06:12:28.07#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.06:12:28.07#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.06:12:28.09#ibcon#[25=AT02-07\r\n] 2006.145.06:12:28.12#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.06:12:28.12#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.06:12:28.12#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.06:12:28.12#ibcon#ireg 7 cls_cnt 0 2006.145.06:12:28.12#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.06:12:28.24#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.06:12:28.24#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.06:12:28.26#ibcon#[25=USB\r\n] 2006.145.06:12:28.29#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.06:12:28.29#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.06:12:28.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.06:12:28.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.06:12:28.29$vck44/valo=3,564.99 2006.145.06:12:28.29#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.06:12:28.29#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.06:12:28.29#ibcon#ireg 17 cls_cnt 0 2006.145.06:12:28.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.06:12:28.29#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.06:12:28.29#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.06:12:28.31#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.06:12:28.35#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.06:12:28.35#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.06:12:28.35#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.06:12:28.35#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.06:12:28.35$vck44/va=3,8 2006.145.06:12:28.35#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.06:12:28.35#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.06:12:28.35#ibcon#ireg 11 cls_cnt 2 2006.145.06:12:28.35#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.06:12:28.41#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.06:12:28.41#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.06:12:28.43#ibcon#[25=AT03-08\r\n] 2006.145.06:12:28.46#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.06:12:28.46#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.06:12:28.46#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.06:12:28.46#ibcon#ireg 7 cls_cnt 0 2006.145.06:12:28.46#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.06:12:28.58#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.06:12:28.58#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.06:12:28.60#ibcon#[25=USB\r\n] 2006.145.06:12:28.63#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.06:12:28.63#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.06:12:28.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.06:12:28.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.06:12:28.63$vck44/valo=4,624.99 2006.145.06:12:28.63#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.06:12:28.63#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.06:12:28.63#ibcon#ireg 17 cls_cnt 0 2006.145.06:12:28.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.06:12:28.63#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.06:12:28.63#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.06:12:28.65#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.06:12:28.69#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.06:12:28.69#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.06:12:28.69#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.06:12:28.69#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.06:12:28.69$vck44/va=4,7 2006.145.06:12:28.69#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.06:12:28.69#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.06:12:28.69#ibcon#ireg 11 cls_cnt 2 2006.145.06:12:28.69#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.06:12:28.75#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.06:12:28.75#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.06:12:28.77#ibcon#[25=AT04-07\r\n] 2006.145.06:12:28.80#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.06:12:28.80#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.06:12:28.80#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.06:12:28.80#ibcon#ireg 7 cls_cnt 0 2006.145.06:12:28.80#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.06:12:28.92#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.06:12:28.92#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.06:12:28.94#ibcon#[25=USB\r\n] 2006.145.06:12:28.97#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.06:12:28.97#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.06:12:28.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.06:12:28.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.06:12:28.97$vck44/valo=5,734.99 2006.145.06:12:28.97#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.06:12:28.97#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.06:12:28.97#ibcon#ireg 17 cls_cnt 0 2006.145.06:12:28.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.06:12:28.97#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.06:12:28.97#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.06:12:28.99#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.06:12:29.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.06:12:29.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.06:12:29.03#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.06:12:29.03#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.06:12:29.03$vck44/va=5,4 2006.145.06:12:29.03#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.06:12:29.03#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.06:12:29.03#ibcon#ireg 11 cls_cnt 2 2006.145.06:12:29.03#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.06:12:29.09#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.06:12:29.09#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.06:12:29.11#ibcon#[25=AT05-04\r\n] 2006.145.06:12:29.14#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.06:12:29.14#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.06:12:29.14#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.06:12:29.14#ibcon#ireg 7 cls_cnt 0 2006.145.06:12:29.14#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.06:12:29.26#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.06:12:29.26#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.06:12:29.28#ibcon#[25=USB\r\n] 2006.145.06:12:29.31#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.06:12:29.31#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.06:12:29.31#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.06:12:29.31#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.06:12:29.31$vck44/valo=6,814.99 2006.145.06:12:29.31#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.06:12:29.31#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.06:12:29.31#ibcon#ireg 17 cls_cnt 0 2006.145.06:12:29.31#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.06:12:29.31#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.06:12:29.31#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.06:12:29.33#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.06:12:29.37#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.06:12:29.37#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.06:12:29.37#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.06:12:29.37#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.06:12:29.37$vck44/va=6,4 2006.145.06:12:29.37#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.06:12:29.37#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.06:12:29.37#ibcon#ireg 11 cls_cnt 2 2006.145.06:12:29.37#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.06:12:29.43#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.06:12:29.43#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.06:12:29.45#ibcon#[25=AT06-04\r\n] 2006.145.06:12:29.48#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.06:12:29.48#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.06:12:29.48#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.06:12:29.48#ibcon#ireg 7 cls_cnt 0 2006.145.06:12:29.48#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.06:12:29.52#abcon#<5=/05 4.9 8.0 20.60 621016.3\r\n> 2006.145.06:12:29.54#abcon#{5=INTERFACE CLEAR} 2006.145.06:12:29.60#abcon#[5=S1D000X0/0*\r\n] 2006.145.06:12:29.60#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.06:12:29.60#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.06:12:29.62#ibcon#[25=USB\r\n] 2006.145.06:12:29.65#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.06:12:29.65#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.06:12:29.65#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.06:12:29.65#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.06:12:29.65$vck44/valo=7,864.99 2006.145.06:12:29.65#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.06:12:29.65#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.06:12:29.65#ibcon#ireg 17 cls_cnt 0 2006.145.06:12:29.65#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.06:12:29.65#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.06:12:29.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.06:12:29.67#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.06:12:29.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.06:12:29.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.06:12:29.71#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.06:12:29.71#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.06:12:29.71$vck44/va=7,4 2006.145.06:12:29.71#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.06:12:29.71#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.06:12:29.71#ibcon#ireg 11 cls_cnt 2 2006.145.06:12:29.71#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.06:12:29.77#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.06:12:29.77#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.06:12:29.79#ibcon#[25=AT07-04\r\n] 2006.145.06:12:29.82#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.06:12:29.82#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.06:12:29.82#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.06:12:29.82#ibcon#ireg 7 cls_cnt 0 2006.145.06:12:29.82#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.06:12:29.94#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.06:12:29.94#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.06:12:29.96#ibcon#[25=USB\r\n] 2006.145.06:12:29.99#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.06:12:29.99#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.06:12:29.99#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.06:12:29.99#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.06:12:29.99$vck44/valo=8,884.99 2006.145.06:12:29.99#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.06:12:29.99#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.06:12:29.99#ibcon#ireg 17 cls_cnt 0 2006.145.06:12:29.99#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.06:12:29.99#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.06:12:29.99#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.06:12:30.01#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.06:12:30.05#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.06:12:30.05#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.06:12:30.05#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.06:12:30.05#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.06:12:30.05$vck44/va=8,4 2006.145.06:12:30.05#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.06:12:30.05#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.06:12:30.05#ibcon#ireg 11 cls_cnt 2 2006.145.06:12:30.05#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.06:12:30.11#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.06:12:30.11#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.06:12:30.13#ibcon#[25=AT08-04\r\n] 2006.145.06:12:30.16#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.06:12:30.16#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.06:12:30.16#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.06:12:30.16#ibcon#ireg 7 cls_cnt 0 2006.145.06:12:30.16#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.06:12:30.28#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.06:12:30.28#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.06:12:30.30#ibcon#[25=USB\r\n] 2006.145.06:12:30.33#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.06:12:30.33#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.06:12:30.33#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.06:12:30.33#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.06:12:30.33$vck44/vblo=1,629.99 2006.145.06:12:30.33#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.06:12:30.33#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.06:12:30.33#ibcon#ireg 17 cls_cnt 0 2006.145.06:12:30.33#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.06:12:30.33#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.06:12:30.33#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.06:12:30.35#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.06:12:30.39#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.06:12:30.39#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.06:12:30.39#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.06:12:30.39#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.06:12:30.39$vck44/vb=1,3 2006.145.06:12:30.39#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.06:12:30.39#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.06:12:30.39#ibcon#ireg 11 cls_cnt 2 2006.145.06:12:30.39#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.06:12:30.39#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.06:12:30.39#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.06:12:30.41#ibcon#[27=AT01-03\r\n] 2006.145.06:12:30.44#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.06:12:30.44#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.06:12:30.44#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.06:12:30.44#ibcon#ireg 7 cls_cnt 0 2006.145.06:12:30.44#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.06:12:30.56#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.06:12:30.56#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.06:12:30.58#ibcon#[27=USB\r\n] 2006.145.06:12:30.61#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.06:12:30.61#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.06:12:30.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.06:12:30.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.06:12:30.61$vck44/vblo=2,634.99 2006.145.06:12:30.61#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.06:12:30.61#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.06:12:30.61#ibcon#ireg 17 cls_cnt 0 2006.145.06:12:30.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.06:12:30.61#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.06:12:30.61#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.06:12:30.63#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.06:12:30.67#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.06:12:30.67#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.06:12:30.67#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.06:12:30.67#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.06:12:30.67$vck44/vb=2,4 2006.145.06:12:30.67#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.06:12:30.67#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.06:12:30.67#ibcon#ireg 11 cls_cnt 2 2006.145.06:12:30.67#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.06:12:30.73#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.06:12:30.73#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.06:12:30.75#ibcon#[27=AT02-04\r\n] 2006.145.06:12:30.78#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.06:12:30.78#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.06:12:30.78#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.06:12:30.78#ibcon#ireg 7 cls_cnt 0 2006.145.06:12:30.78#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.06:12:30.90#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.06:12:30.90#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.06:12:30.92#ibcon#[27=USB\r\n] 2006.145.06:12:30.95#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.06:12:30.95#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.06:12:30.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.06:12:30.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.06:12:30.95$vck44/vblo=3,649.99 2006.145.06:12:30.95#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.06:12:30.95#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.06:12:30.95#ibcon#ireg 17 cls_cnt 0 2006.145.06:12:30.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.06:12:30.95#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.06:12:30.95#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.06:12:30.97#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.06:12:31.01#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.06:12:31.01#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.06:12:31.01#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.06:12:31.01#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.06:12:31.01$vck44/vb=3,4 2006.145.06:12:31.01#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.06:12:31.01#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.06:12:31.01#ibcon#ireg 11 cls_cnt 2 2006.145.06:12:31.01#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.06:12:31.07#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.06:12:31.07#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.06:12:31.09#ibcon#[27=AT03-04\r\n] 2006.145.06:12:31.12#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.06:12:31.12#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.06:12:31.12#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.06:12:31.12#ibcon#ireg 7 cls_cnt 0 2006.145.06:12:31.12#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.06:12:31.24#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.06:12:31.24#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.06:12:31.26#ibcon#[27=USB\r\n] 2006.145.06:12:31.29#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.06:12:31.29#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.06:12:31.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.06:12:31.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.06:12:31.29$vck44/vblo=4,679.99 2006.145.06:12:31.29#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.06:12:31.29#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.06:12:31.29#ibcon#ireg 17 cls_cnt 0 2006.145.06:12:31.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.06:12:31.29#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.06:12:31.29#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.06:12:31.31#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.06:12:31.35#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.06:12:31.35#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.06:12:31.35#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.06:12:31.35#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.06:12:31.35$vck44/vb=4,4 2006.145.06:12:31.35#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.06:12:31.35#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.06:12:31.35#ibcon#ireg 11 cls_cnt 2 2006.145.06:12:31.35#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.06:12:31.41#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.06:12:31.41#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.06:12:31.43#ibcon#[27=AT04-04\r\n] 2006.145.06:12:31.46#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.06:12:31.46#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.06:12:31.46#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.06:12:31.46#ibcon#ireg 7 cls_cnt 0 2006.145.06:12:31.46#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.06:12:31.58#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.06:12:31.58#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.06:12:31.60#ibcon#[27=USB\r\n] 2006.145.06:12:31.63#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.06:12:31.63#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.06:12:31.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.06:12:31.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.06:12:31.63$vck44/vblo=5,709.99 2006.145.06:12:31.63#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.06:12:31.63#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.06:12:31.63#ibcon#ireg 17 cls_cnt 0 2006.145.06:12:31.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.06:12:31.63#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.06:12:31.63#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.06:12:31.65#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.06:12:31.69#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.06:12:31.69#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.06:12:31.69#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.06:12:31.69#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.06:12:31.69$vck44/vb=5,4 2006.145.06:12:31.69#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.06:12:31.69#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.06:12:31.69#ibcon#ireg 11 cls_cnt 2 2006.145.06:12:31.69#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.06:12:31.75#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.06:12:31.75#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.06:12:31.77#ibcon#[27=AT05-04\r\n] 2006.145.06:12:31.80#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.06:12:31.80#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.06:12:31.80#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.06:12:31.80#ibcon#ireg 7 cls_cnt 0 2006.145.06:12:31.80#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.06:12:31.92#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.06:12:31.92#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.06:12:31.94#ibcon#[27=USB\r\n] 2006.145.06:12:31.97#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.06:12:31.97#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.06:12:31.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.06:12:31.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.06:12:31.97$vck44/vblo=6,719.99 2006.145.06:12:31.97#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.06:12:31.97#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.06:12:31.97#ibcon#ireg 17 cls_cnt 0 2006.145.06:12:31.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.06:12:31.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.06:12:31.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.06:12:31.99#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.06:12:32.03#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.06:12:32.03#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.06:12:32.03#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.06:12:32.03#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.06:12:32.03$vck44/vb=6,4 2006.145.06:12:32.03#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.06:12:32.03#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.06:12:32.03#ibcon#ireg 11 cls_cnt 2 2006.145.06:12:32.03#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.06:12:32.09#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.06:12:32.09#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.06:12:32.11#ibcon#[27=AT06-04\r\n] 2006.145.06:12:32.14#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.06:12:32.14#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.06:12:32.14#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.06:12:32.14#ibcon#ireg 7 cls_cnt 0 2006.145.06:12:32.14#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.06:12:32.26#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.06:12:32.26#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.06:12:32.28#ibcon#[27=USB\r\n] 2006.145.06:12:32.31#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.06:12:32.31#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.06:12:32.31#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.06:12:32.31#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.06:12:32.31$vck44/vblo=7,734.99 2006.145.06:12:32.31#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.06:12:32.31#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.06:12:32.31#ibcon#ireg 17 cls_cnt 0 2006.145.06:12:32.31#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.06:12:32.31#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.06:12:32.31#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.06:12:32.33#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.06:12:32.37#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.06:12:32.37#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.06:12:32.37#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.06:12:32.37#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.06:12:32.37$vck44/vb=7,4 2006.145.06:12:32.37#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.06:12:32.37#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.06:12:32.37#ibcon#ireg 11 cls_cnt 2 2006.145.06:12:32.37#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.06:12:32.43#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.06:12:32.43#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.06:12:32.45#ibcon#[27=AT07-04\r\n] 2006.145.06:12:32.48#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.06:12:32.48#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.06:12:32.48#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.06:12:32.48#ibcon#ireg 7 cls_cnt 0 2006.145.06:12:32.48#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.06:12:32.60#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.06:12:32.60#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.06:12:32.62#ibcon#[27=USB\r\n] 2006.145.06:12:32.65#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.06:12:32.65#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.06:12:32.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.06:12:32.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.06:12:32.65$vck44/vblo=8,744.99 2006.145.06:12:32.65#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.06:12:32.65#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.06:12:32.65#ibcon#ireg 17 cls_cnt 0 2006.145.06:12:32.65#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.06:12:32.65#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.06:12:32.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.06:12:32.67#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.06:12:32.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.06:12:32.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.06:12:32.71#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.06:12:32.71#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.06:12:32.71$vck44/vb=8,4 2006.145.06:12:32.71#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.06:12:32.71#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.06:12:32.71#ibcon#ireg 11 cls_cnt 2 2006.145.06:12:32.71#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.06:12:32.77#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.06:12:32.77#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.06:12:32.79#ibcon#[27=AT08-04\r\n] 2006.145.06:12:32.82#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.06:12:32.82#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.06:12:32.82#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.06:12:32.82#ibcon#ireg 7 cls_cnt 0 2006.145.06:12:32.82#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.06:12:32.94#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.06:12:32.94#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.06:12:32.96#ibcon#[27=USB\r\n] 2006.145.06:12:32.99#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.06:12:32.99#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.06:12:32.99#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.06:12:32.99#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.06:12:32.99$vck44/vabw=wide 2006.145.06:12:32.99#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.06:12:32.99#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.06:12:32.99#ibcon#ireg 8 cls_cnt 0 2006.145.06:12:32.99#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.06:12:32.99#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.06:12:32.99#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.06:12:33.02#ibcon#[25=BW32\r\n] 2006.145.06:12:33.05#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.06:12:33.05#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.06:12:33.05#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.06:12:33.05#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.06:12:33.05$vck44/vbbw=wide 2006.145.06:12:33.05#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.06:12:33.05#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.06:12:33.05#ibcon#ireg 8 cls_cnt 0 2006.145.06:12:33.05#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.06:12:33.11#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.06:12:33.11#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.06:12:33.13#ibcon#[27=BW32\r\n] 2006.145.06:12:33.16#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.06:12:33.16#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.06:12:33.16#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.06:12:33.16#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.06:12:33.16$setupk4/ifdk4 2006.145.06:12:33.16$ifdk4/lo= 2006.145.06:12:33.16$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.06:12:33.16$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.06:12:33.16$ifdk4/patch= 2006.145.06:12:33.16$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.06:12:33.16$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.06:12:33.16$setupk4/!*+20s 2006.145.06:12:39.69#abcon#<5=/05 5.0 7.9 20.60 621016.3\r\n> 2006.145.06:12:39.71#abcon#{5=INTERFACE CLEAR} 2006.145.06:12:39.77#abcon#[5=S1D000X0/0*\r\n] 2006.145.06:12:47.65$setupk4/"tpicd 2006.145.06:12:47.65$setupk4/echo=off 2006.145.06:12:47.65$setupk4/xlog=off 2006.145.06:12:47.65:!2006.145.06:14:02 2006.145.06:12:51.14#trakl#Source acquired 2006.145.06:12:53.14#flagr#flagr/antenna,acquired 2006.145.06:14:02.00:preob 2006.145.06:14:03.14/onsource/TRACKING 2006.145.06:14:03.14:!2006.145.06:14:12 2006.145.06:14:12.00:"tape 2006.145.06:14:12.00:"st=record 2006.145.06:14:12.00:data_valid=on 2006.145.06:14:12.00:midob 2006.145.06:14:12.14/onsource/TRACKING 2006.145.06:14:12.14/wx/20.57,1016.3,60 2006.145.06:14:12.21/cable/+6.5395E-03 2006.145.06:14:13.30/va/01,08,usb,yes,30,32 2006.145.06:14:13.30/va/02,07,usb,yes,32,32 2006.145.06:14:13.30/va/03,08,usb,yes,29,30 2006.145.06:14:13.30/va/04,07,usb,yes,33,35 2006.145.06:14:13.30/va/05,04,usb,yes,29,29 2006.145.06:14:13.30/va/06,04,usb,yes,32,32 2006.145.06:14:13.30/va/07,04,usb,yes,32,34 2006.145.06:14:13.30/va/08,04,usb,yes,27,33 2006.145.06:14:13.53/valo/01,524.99,yes,locked 2006.145.06:14:13.53/valo/02,534.99,yes,locked 2006.145.06:14:13.53/valo/03,564.99,yes,locked 2006.145.06:14:13.53/valo/04,624.99,yes,locked 2006.145.06:14:13.53/valo/05,734.99,yes,locked 2006.145.06:14:13.53/valo/06,814.99,yes,locked 2006.145.06:14:13.53/valo/07,864.99,yes,locked 2006.145.06:14:13.53/valo/08,884.99,yes,locked 2006.145.06:14:14.62/vb/01,03,usb,yes,37,34 2006.145.06:14:14.62/vb/02,04,usb,yes,32,32 2006.145.06:14:14.62/vb/03,04,usb,yes,29,32 2006.145.06:14:14.62/vb/04,04,usb,yes,33,32 2006.145.06:14:14.62/vb/05,04,usb,yes,26,28 2006.145.06:14:14.62/vb/06,04,usb,yes,30,27 2006.145.06:14:14.62/vb/07,04,usb,yes,30,30 2006.145.06:14:14.62/vb/08,04,usb,yes,28,31 2006.145.06:14:14.85/vblo/01,629.99,yes,locked 2006.145.06:14:14.85/vblo/02,634.99,yes,locked 2006.145.06:14:14.85/vblo/03,649.99,yes,locked 2006.145.06:14:14.85/vblo/04,679.99,yes,locked 2006.145.06:14:14.85/vblo/05,709.99,yes,locked 2006.145.06:14:14.85/vblo/06,719.99,yes,locked 2006.145.06:14:14.85/vblo/07,734.99,yes,locked 2006.145.06:14:14.85/vblo/08,744.99,yes,locked 2006.145.06:14:15.00/vabw/8 2006.145.06:14:15.15/vbbw/8 2006.145.06:14:15.25/xfe/off,on,15.2 2006.145.06:14:15.65/ifatt/23,28,28,28 2006.145.06:14:16.08/fmout-gps/S +5.6E-08 2006.145.06:14:16.12:!2006.145.06:19:52 2006.145.06:19:52.00:data_valid=off 2006.145.06:19:52.01:"et 2006.145.06:19:52.01:!+3s 2006.145.06:19:55.04:"tape 2006.145.06:19:55.05:postob 2006.145.06:19:55.23/cable/+6.5396E-03 2006.145.06:19:55.24/wx/20.54,1016.4,62 2006.145.06:19:55.33/fmout-gps/S +5.6E-08 2006.145.06:19:55.33:scan_name=145-0627,jd0605,460 2006.145.06:19:55.33:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.145.06:19:57.15#flagr#flagr/antenna,new-source 2006.145.06:19:57.15:checkk5 2006.145.06:19:57.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.06:19:58.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.06:19:58.45/chk_autoobs//k5ts3/ autoobs is running! 2006.145.06:19:58.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.06:19:59.31/chk_obsdata//k5ts1/T1450614??a.dat file size is correct (nominal:1360MB, actual:1356MB). 2006.145.06:19:59.74/chk_obsdata//k5ts2/T1450614??b.dat file size is correct (nominal:1360MB, actual:1356MB). 2006.145.06:20:00.18/chk_obsdata//k5ts3/T1450614??c.dat file size is correct (nominal:1360MB, actual:1356MB). 2006.145.06:20:00.65/chk_obsdata//k5ts4/T1450614??d.dat file size is correct (nominal:1360MB, actual:1356MB). 2006.145.06:20:01.41/k5log//k5ts1_log_newline 2006.145.06:20:02.17/k5log//k5ts2_log_newline 2006.145.06:20:02.91/k5log//k5ts3_log_newline 2006.145.06:20:03.68/k5log//k5ts4_log_newline 2006.145.06:20:03.70/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.06:20:03.70:setupk4=1 2006.145.06:20:03.70$setupk4/echo=on 2006.145.06:20:03.70$setupk4/pcalon 2006.145.06:20:03.70$pcalon/"no phase cal control is implemented here 2006.145.06:20:03.70$setupk4/"tpicd=stop 2006.145.06:20:03.70$setupk4/"rec=synch_on 2006.145.06:20:03.70$setupk4/"rec_mode=128 2006.145.06:20:03.70$setupk4/!* 2006.145.06:20:03.70$setupk4/recpk4 2006.145.06:20:03.70$recpk4/recpatch= 2006.145.06:20:03.71$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.06:20:03.71$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.06:20:03.71$setupk4/vck44 2006.145.06:20:03.71$vck44/valo=1,524.99 2006.145.06:20:03.71#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.06:20:03.71#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.06:20:03.71#ibcon#ireg 17 cls_cnt 0 2006.145.06:20:03.71#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.06:20:03.71#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.06:20:03.71#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.06:20:03.74#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.06:20:03.79#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.06:20:03.79#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.06:20:03.79#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.06:20:03.79#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.06:20:03.79$vck44/va=1,8 2006.145.06:20:03.79#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.06:20:03.79#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.06:20:03.79#ibcon#ireg 11 cls_cnt 2 2006.145.06:20:03.79#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.06:20:03.79#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.06:20:03.79#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.06:20:03.81#ibcon#[25=AT01-08\r\n] 2006.145.06:20:03.84#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.06:20:03.84#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.06:20:03.84#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.06:20:03.84#ibcon#ireg 7 cls_cnt 0 2006.145.06:20:03.84#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.06:20:03.96#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.06:20:03.96#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.06:20:03.98#ibcon#[25=USB\r\n] 2006.145.06:20:04.03#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.06:20:04.03#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.06:20:04.03#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.06:20:04.03#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.06:20:04.03$vck44/valo=2,534.99 2006.145.06:20:04.03#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.06:20:04.03#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.06:20:04.03#ibcon#ireg 17 cls_cnt 0 2006.145.06:20:04.03#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.06:20:04.03#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.06:20:04.03#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.06:20:04.05#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.06:20:04.08#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.06:20:04.08#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.06:20:04.08#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.06:20:04.08#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.06:20:04.08$vck44/va=2,7 2006.145.06:20:04.08#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.06:20:04.08#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.06:20:04.08#ibcon#ireg 11 cls_cnt 2 2006.145.06:20:04.08#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.06:20:04.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.06:20:04.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.06:20:04.17#ibcon#[25=AT02-07\r\n] 2006.145.06:20:04.20#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.06:20:04.20#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.06:20:04.20#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.06:20:04.20#ibcon#ireg 7 cls_cnt 0 2006.145.06:20:04.20#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.06:20:04.32#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.06:20:04.32#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.06:20:04.34#ibcon#[25=USB\r\n] 2006.145.06:20:04.37#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.06:20:04.37#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.06:20:04.37#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.06:20:04.37#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.06:20:04.37$vck44/valo=3,564.99 2006.145.06:20:04.37#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.06:20:04.37#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.06:20:04.37#ibcon#ireg 17 cls_cnt 0 2006.145.06:20:04.37#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.06:20:04.37#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.06:20:04.37#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.06:20:04.39#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.06:20:04.43#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.06:20:04.43#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.06:20:04.43#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.06:20:04.43#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.06:20:04.43$vck44/va=3,8 2006.145.06:20:04.43#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.06:20:04.43#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.06:20:04.43#ibcon#ireg 11 cls_cnt 2 2006.145.06:20:04.43#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.06:20:04.49#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.06:20:04.49#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.06:20:04.51#ibcon#[25=AT03-08\r\n] 2006.145.06:20:04.54#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.06:20:04.54#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.06:20:04.54#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.06:20:04.54#ibcon#ireg 7 cls_cnt 0 2006.145.06:20:04.54#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.06:20:04.66#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.06:20:04.66#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.06:20:04.68#ibcon#[25=USB\r\n] 2006.145.06:20:04.71#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.06:20:04.71#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.06:20:04.71#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.06:20:04.71#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.06:20:04.71$vck44/valo=4,624.99 2006.145.06:20:04.71#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.06:20:04.71#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.06:20:04.71#ibcon#ireg 17 cls_cnt 0 2006.145.06:20:04.71#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.06:20:04.71#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.06:20:04.71#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.06:20:04.73#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.06:20:04.77#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.06:20:04.77#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.06:20:04.77#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.06:20:04.77#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.06:20:04.77$vck44/va=4,7 2006.145.06:20:04.77#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.06:20:04.77#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.06:20:04.77#ibcon#ireg 11 cls_cnt 2 2006.145.06:20:04.77#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.06:20:04.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.06:20:04.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.06:20:04.85#ibcon#[25=AT04-07\r\n] 2006.145.06:20:04.88#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.06:20:04.88#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.06:20:04.88#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.06:20:04.88#ibcon#ireg 7 cls_cnt 0 2006.145.06:20:04.88#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.06:20:05.00#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.06:20:05.00#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.06:20:05.02#ibcon#[25=USB\r\n] 2006.145.06:20:05.05#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.06:20:05.05#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.06:20:05.05#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.06:20:05.05#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.06:20:05.05$vck44/valo=5,734.99 2006.145.06:20:05.05#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.06:20:05.05#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.06:20:05.05#ibcon#ireg 17 cls_cnt 0 2006.145.06:20:05.05#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.06:20:05.05#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.06:20:05.05#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.06:20:05.07#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.06:20:05.11#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.06:20:05.11#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.06:20:05.11#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.06:20:05.11#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.06:20:05.11$vck44/va=5,4 2006.145.06:20:05.11#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.06:20:05.11#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.06:20:05.11#ibcon#ireg 11 cls_cnt 2 2006.145.06:20:05.11#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.06:20:05.17#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.06:20:05.17#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.06:20:05.19#ibcon#[25=AT05-04\r\n] 2006.145.06:20:05.22#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.06:20:05.22#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.06:20:05.22#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.06:20:05.22#ibcon#ireg 7 cls_cnt 0 2006.145.06:20:05.22#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.06:20:05.35#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.06:20:05.35#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.06:20:05.36#ibcon#[25=USB\r\n] 2006.145.06:20:05.39#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.06:20:05.39#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.06:20:05.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.06:20:05.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.06:20:05.39$vck44/valo=6,814.99 2006.145.06:20:05.39#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.06:20:05.39#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.06:20:05.39#ibcon#ireg 17 cls_cnt 0 2006.145.06:20:05.39#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.06:20:05.39#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.06:20:05.39#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.06:20:05.42#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.06:20:05.46#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.06:20:05.46#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.06:20:05.46#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.06:20:05.46#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.06:20:05.46$vck44/va=6,4 2006.145.06:20:05.46#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.06:20:05.46#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.06:20:05.46#ibcon#ireg 11 cls_cnt 2 2006.145.06:20:05.46#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.06:20:05.52#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.06:20:05.52#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.06:20:05.55#ibcon#[25=AT06-04\r\n] 2006.145.06:20:05.57#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.06:20:05.57#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.06:20:05.57#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.06:20:05.57#ibcon#ireg 7 cls_cnt 0 2006.145.06:20:05.57#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.06:20:05.69#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.06:20:05.69#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.06:20:05.71#ibcon#[25=USB\r\n] 2006.145.06:20:05.74#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.06:20:05.74#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.06:20:05.74#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.06:20:05.74#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.06:20:05.74$vck44/valo=7,864.99 2006.145.06:20:05.74#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.06:20:05.74#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.06:20:05.74#ibcon#ireg 17 cls_cnt 0 2006.145.06:20:05.74#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.06:20:05.74#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.06:20:05.74#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.06:20:05.76#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.06:20:05.80#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.06:20:05.80#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.06:20:05.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.06:20:05.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.06:20:05.80$vck44/va=7,4 2006.145.06:20:05.80#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.06:20:05.80#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.06:20:05.80#ibcon#ireg 11 cls_cnt 2 2006.145.06:20:05.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.06:20:05.86#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.06:20:05.86#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.06:20:05.88#ibcon#[25=AT07-04\r\n] 2006.145.06:20:05.91#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.06:20:05.91#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.06:20:05.91#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.06:20:05.91#ibcon#ireg 7 cls_cnt 0 2006.145.06:20:05.91#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.06:20:06.03#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.06:20:06.03#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.06:20:06.05#ibcon#[25=USB\r\n] 2006.145.06:20:06.08#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.06:20:06.08#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.06:20:06.08#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.06:20:06.08#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.06:20:06.08$vck44/valo=8,884.99 2006.145.06:20:06.08#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.06:20:06.08#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.06:20:06.08#ibcon#ireg 17 cls_cnt 0 2006.145.06:20:06.08#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.06:20:06.08#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.06:20:06.08#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.06:20:06.10#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.06:20:06.14#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.06:20:06.14#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.06:20:06.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.06:20:06.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.06:20:06.14$vck44/va=8,4 2006.145.06:20:06.14#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.06:20:06.14#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.06:20:06.14#ibcon#ireg 11 cls_cnt 2 2006.145.06:20:06.14#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.06:20:06.20#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.06:20:06.20#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.06:20:06.22#ibcon#[25=AT08-04\r\n] 2006.145.06:20:06.25#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.06:20:06.25#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.06:20:06.25#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.06:20:06.25#ibcon#ireg 7 cls_cnt 0 2006.145.06:20:06.25#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.06:20:06.37#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.06:20:06.37#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.06:20:06.39#ibcon#[25=USB\r\n] 2006.145.06:20:06.42#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.06:20:06.42#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.06:20:06.42#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.06:20:06.42#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.06:20:06.42$vck44/vblo=1,629.99 2006.145.06:20:06.42#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.06:20:06.42#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.06:20:06.42#ibcon#ireg 17 cls_cnt 0 2006.145.06:20:06.42#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.06:20:06.42#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.06:20:06.42#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.06:20:06.44#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.06:20:06.48#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.06:20:06.48#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.06:20:06.48#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.06:20:06.48#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.06:20:06.48$vck44/vb=1,3 2006.145.06:20:06.48#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.06:20:06.48#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.06:20:06.48#ibcon#ireg 11 cls_cnt 2 2006.145.06:20:06.48#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.06:20:06.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.06:20:06.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.06:20:06.50#ibcon#[27=AT01-03\r\n] 2006.145.06:20:06.53#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.06:20:06.53#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.06:20:06.53#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.06:20:06.53#ibcon#ireg 7 cls_cnt 0 2006.145.06:20:06.53#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.06:20:06.65#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.06:20:06.65#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.06:20:06.67#ibcon#[27=USB\r\n] 2006.145.06:20:06.70#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.06:20:06.70#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.06:20:06.70#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.06:20:06.70#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.06:20:06.70$vck44/vblo=2,634.99 2006.145.06:20:06.70#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.06:20:06.70#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.06:20:06.70#ibcon#ireg 17 cls_cnt 0 2006.145.06:20:06.70#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.06:20:06.70#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.06:20:06.70#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.06:20:06.72#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.06:20:06.76#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.06:20:06.76#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.06:20:06.76#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.06:20:06.76#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.06:20:06.76$vck44/vb=2,4 2006.145.06:20:06.76#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.06:20:06.76#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.06:20:06.76#ibcon#ireg 11 cls_cnt 2 2006.145.06:20:06.76#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.06:20:06.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.06:20:06.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.06:20:06.84#ibcon#[27=AT02-04\r\n] 2006.145.06:20:06.87#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.06:20:06.87#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.06:20:06.87#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.06:20:06.87#ibcon#ireg 7 cls_cnt 0 2006.145.06:20:06.87#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.06:20:06.99#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.06:20:06.99#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.06:20:07.01#ibcon#[27=USB\r\n] 2006.145.06:20:07.04#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.06:20:07.04#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.06:20:07.04#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.06:20:07.04#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.06:20:07.04$vck44/vblo=3,649.99 2006.145.06:20:07.04#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.06:20:07.04#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.06:20:07.04#ibcon#ireg 17 cls_cnt 0 2006.145.06:20:07.04#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.06:20:07.04#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.06:20:07.04#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.06:20:07.06#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.06:20:07.10#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.06:20:07.10#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.06:20:07.10#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.06:20:07.10#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.06:20:07.10$vck44/vb=3,4 2006.145.06:20:07.10#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.06:20:07.10#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.06:20:07.10#ibcon#ireg 11 cls_cnt 2 2006.145.06:20:07.10#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.06:20:07.16#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.06:20:07.16#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.06:20:07.18#ibcon#[27=AT03-04\r\n] 2006.145.06:20:07.21#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.06:20:07.21#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.06:20:07.21#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.06:20:07.21#ibcon#ireg 7 cls_cnt 0 2006.145.06:20:07.21#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.06:20:07.33#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.06:20:07.33#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.06:20:07.35#ibcon#[27=USB\r\n] 2006.145.06:20:07.38#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.06:20:07.38#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.06:20:07.38#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.06:20:07.38#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.06:20:07.38$vck44/vblo=4,679.99 2006.145.06:20:07.38#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.06:20:07.38#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.06:20:07.38#ibcon#ireg 17 cls_cnt 0 2006.145.06:20:07.38#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.06:20:07.38#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.06:20:07.38#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.06:20:07.40#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.06:20:07.44#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.06:20:07.44#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.06:20:07.44#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.06:20:07.44#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.06:20:07.44$vck44/vb=4,4 2006.145.06:20:07.44#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.06:20:07.44#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.06:20:07.44#ibcon#ireg 11 cls_cnt 2 2006.145.06:20:07.44#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.06:20:07.48#abcon#<5=/05 4.7 7.3 20.54 601016.4\r\n> 2006.145.06:20:07.50#abcon#{5=INTERFACE CLEAR} 2006.145.06:20:07.50#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.06:20:07.50#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.06:20:07.52#ibcon#[27=AT04-04\r\n] 2006.145.06:20:07.55#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.06:20:07.55#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.06:20:07.55#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.06:20:07.55#ibcon#ireg 7 cls_cnt 0 2006.145.06:20:07.55#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.06:20:07.56#abcon#[5=S1D000X0/0*\r\n] 2006.145.06:20:07.67#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.06:20:07.67#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.06:20:07.69#ibcon#[27=USB\r\n] 2006.145.06:20:07.72#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.06:20:07.72#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.06:20:07.72#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.06:20:07.72#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.06:20:07.72$vck44/vblo=5,709.99 2006.145.06:20:07.72#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.06:20:07.72#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.06:20:07.72#ibcon#ireg 17 cls_cnt 0 2006.145.06:20:07.72#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.06:20:07.72#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.06:20:07.72#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.06:20:07.74#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.06:20:07.78#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.06:20:07.78#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.06:20:07.78#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.06:20:07.78#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.06:20:07.78$vck44/vb=5,4 2006.145.06:20:07.78#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.06:20:07.78#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.06:20:07.78#ibcon#ireg 11 cls_cnt 2 2006.145.06:20:07.78#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.06:20:07.84#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.06:20:07.84#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.06:20:07.86#ibcon#[27=AT05-04\r\n] 2006.145.06:20:07.89#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.06:20:07.89#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.06:20:07.89#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.06:20:07.89#ibcon#ireg 7 cls_cnt 0 2006.145.06:20:07.89#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.06:20:08.01#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.06:20:08.01#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.06:20:08.03#ibcon#[27=USB\r\n] 2006.145.06:20:08.06#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.06:20:08.06#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.06:20:08.06#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.06:20:08.06#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.06:20:08.06$vck44/vblo=6,719.99 2006.145.06:20:08.06#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.06:20:08.06#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.06:20:08.06#ibcon#ireg 17 cls_cnt 0 2006.145.06:20:08.06#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.06:20:08.06#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.06:20:08.06#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.06:20:08.08#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.06:20:08.12#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.06:20:08.12#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.06:20:08.12#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.06:20:08.12#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.06:20:08.12$vck44/vb=6,4 2006.145.06:20:08.12#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.06:20:08.12#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.06:20:08.12#ibcon#ireg 11 cls_cnt 2 2006.145.06:20:08.12#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.06:20:08.18#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.06:20:08.18#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.06:20:08.20#ibcon#[27=AT06-04\r\n] 2006.145.06:20:08.23#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.06:20:08.23#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.06:20:08.23#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.06:20:08.23#ibcon#ireg 7 cls_cnt 0 2006.145.06:20:08.23#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.06:20:08.35#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.06:20:08.35#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.06:20:08.37#ibcon#[27=USB\r\n] 2006.145.06:20:08.40#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.06:20:08.40#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.06:20:08.40#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.06:20:08.40#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.06:20:08.40$vck44/vblo=7,734.99 2006.145.06:20:08.40#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.06:20:08.40#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.06:20:08.40#ibcon#ireg 17 cls_cnt 0 2006.145.06:20:08.40#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.06:20:08.40#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.06:20:08.40#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.06:20:08.42#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.06:20:08.46#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.06:20:08.46#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.06:20:08.46#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.06:20:08.46#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.06:20:08.46$vck44/vb=7,4 2006.145.06:20:08.46#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.06:20:08.46#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.06:20:08.46#ibcon#ireg 11 cls_cnt 2 2006.145.06:20:08.46#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.06:20:08.52#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.06:20:08.52#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.06:20:08.54#ibcon#[27=AT07-04\r\n] 2006.145.06:20:08.57#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.06:20:08.57#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.06:20:08.57#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.06:20:08.57#ibcon#ireg 7 cls_cnt 0 2006.145.06:20:08.57#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.06:20:08.69#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.06:20:08.69#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.06:20:08.71#ibcon#[27=USB\r\n] 2006.145.06:20:08.74#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.06:20:08.74#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.06:20:08.74#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.06:20:08.74#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.06:20:08.74$vck44/vblo=8,744.99 2006.145.06:20:08.74#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.06:20:08.74#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.06:20:08.74#ibcon#ireg 17 cls_cnt 0 2006.145.06:20:08.74#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.06:20:08.74#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.06:20:08.74#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.06:20:08.76#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.06:20:08.80#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.06:20:08.80#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.06:20:08.80#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.06:20:08.80#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.06:20:08.80$vck44/vb=8,4 2006.145.06:20:08.80#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.06:20:08.80#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.06:20:08.80#ibcon#ireg 11 cls_cnt 2 2006.145.06:20:08.80#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.06:20:08.86#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.06:20:08.86#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.06:20:08.88#ibcon#[27=AT08-04\r\n] 2006.145.06:20:08.91#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.06:20:08.91#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.06:20:08.91#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.06:20:08.91#ibcon#ireg 7 cls_cnt 0 2006.145.06:20:08.91#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.06:20:09.03#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.06:20:09.03#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.06:20:09.05#ibcon#[27=USB\r\n] 2006.145.06:20:09.08#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.06:20:09.08#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.06:20:09.08#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.06:20:09.08#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.06:20:09.08$vck44/vabw=wide 2006.145.06:20:09.08#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.06:20:09.08#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.06:20:09.08#ibcon#ireg 8 cls_cnt 0 2006.145.06:20:09.08#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.06:20:09.08#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.06:20:09.08#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.06:20:09.10#ibcon#[25=BW32\r\n] 2006.145.06:20:09.13#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.06:20:09.13#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.06:20:09.13#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.06:20:09.13#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.06:20:09.13$vck44/vbbw=wide 2006.145.06:20:09.13#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.06:20:09.13#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.06:20:09.13#ibcon#ireg 8 cls_cnt 0 2006.145.06:20:09.13#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.06:20:09.20#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.06:20:09.20#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.06:20:09.22#ibcon#[27=BW32\r\n] 2006.145.06:20:09.25#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.06:20:09.25#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.06:20:09.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.06:20:09.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.06:20:09.25$setupk4/ifdk4 2006.145.06:20:09.25$ifdk4/lo= 2006.145.06:20:09.26$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.06:20:09.26$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.06:20:09.26$ifdk4/patch= 2006.145.06:20:09.26$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.06:20:09.26$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.06:20:09.26$setupk4/!*+20s 2006.145.06:20:17.65#abcon#<5=/05 4.7 7.3 20.54 611016.4\r\n> 2006.145.06:20:17.67#abcon#{5=INTERFACE CLEAR} 2006.145.06:20:17.73#abcon#[5=S1D000X0/0*\r\n] 2006.145.06:20:23.72$setupk4/"tpicd 2006.145.06:20:23.72$setupk4/echo=off 2006.145.06:20:23.72$setupk4/xlog=off 2006.145.06:20:23.72:!2006.145.06:27:42 2006.145.06:20:30.14#trakl#Source acquired 2006.145.06:20:31.14#flagr#flagr/antenna,acquired 2006.145.06:27:42.00:preob 2006.145.06:27:42.14/onsource/TRACKING 2006.145.06:27:42.14:!2006.145.06:27:52 2006.145.06:27:52.00:"tape 2006.145.06:27:52.00:"st=record 2006.145.06:27:52.00:data_valid=on 2006.145.06:27:52.01:midob 2006.145.06:27:53.14/onsource/TRACKING 2006.145.06:27:53.14/wx/20.46,1016.5,62 2006.145.06:27:53.22/cable/+6.5409E-03 2006.145.06:27:54.31/va/01,08,usb,yes,30,32 2006.145.06:27:54.31/va/02,07,usb,yes,32,32 2006.145.06:27:54.31/va/03,08,usb,yes,29,30 2006.145.06:27:54.31/va/04,07,usb,yes,33,34 2006.145.06:27:54.31/va/05,04,usb,yes,28,29 2006.145.06:27:54.31/va/06,04,usb,yes,32,32 2006.145.06:27:54.31/va/07,04,usb,yes,32,34 2006.145.06:27:54.31/va/08,04,usb,yes,27,33 2006.145.06:27:54.54/valo/01,524.99,yes,locked 2006.145.06:27:54.54/valo/02,534.99,yes,locked 2006.145.06:27:54.54/valo/03,564.99,yes,locked 2006.145.06:27:54.54/valo/04,624.99,yes,locked 2006.145.06:27:54.54/valo/05,734.99,yes,locked 2006.145.06:27:54.54/valo/06,814.99,yes,locked 2006.145.06:27:54.54/valo/07,864.99,yes,locked 2006.145.06:27:54.54/valo/08,884.99,yes,locked 2006.145.06:27:55.63/vb/01,03,usb,yes,36,34 2006.145.06:27:55.63/vb/02,04,usb,yes,32,32 2006.145.06:27:55.63/vb/03,04,usb,yes,29,32 2006.145.06:27:55.63/vb/04,04,usb,yes,33,32 2006.145.06:27:55.63/vb/05,04,usb,yes,26,28 2006.145.06:27:55.63/vb/06,04,usb,yes,30,26 2006.145.06:27:55.63/vb/07,04,usb,yes,30,30 2006.145.06:27:55.63/vb/08,04,usb,yes,27,31 2006.145.06:27:55.86/vblo/01,629.99,yes,locked 2006.145.06:27:55.86/vblo/02,634.99,yes,locked 2006.145.06:27:55.86/vblo/03,649.99,yes,locked 2006.145.06:27:55.86/vblo/04,679.99,yes,locked 2006.145.06:27:55.86/vblo/05,709.99,yes,locked 2006.145.06:27:55.86/vblo/06,719.99,yes,locked 2006.145.06:27:55.86/vblo/07,734.99,yes,locked 2006.145.06:27:55.86/vblo/08,744.99,yes,locked 2006.145.06:27:56.01/vabw/8 2006.145.06:27:56.16/vbbw/8 2006.145.06:27:56.36/xfe/off,on,14.7 2006.145.06:27:56.74/ifatt/23,28,28,28 2006.145.06:27:57.07/fmout-gps/S +5.7E-08 2006.145.06:27:57.16:!2006.145.06:35:32 2006.145.06:35:32.00:data_valid=off 2006.145.06:35:32.00:"et 2006.145.06:35:32.01:!+3s 2006.145.06:35:35.02:"tape 2006.145.06:35:35.02:postob 2006.145.06:35:35.20/cable/+6.5409E-03 2006.145.06:35:35.21/wx/20.34,1016.5,62 2006.145.06:35:35.26/fmout-gps/S +5.7E-08 2006.145.06:35:35.26:scan_name=145-0641,jd0605,50 2006.145.06:35:35.27:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.145.06:35:36.13#flagr#flagr/antenna,new-source 2006.145.06:35:36.14:checkk5 2006.145.06:35:36.65/chk_autoobs//k5ts1/ autoobs is running! 2006.145.06:35:37.08/chk_autoobs//k5ts2/ autoobs is running! 2006.145.06:35:37.53/chk_autoobs//k5ts3/ autoobs is running! 2006.145.06:35:37.95/chk_autoobs//k5ts4/ autoobs is running! 2006.145.06:35:38.38/chk_obsdata//k5ts1/T1450627??a.dat file size is correct (nominal:1840MB, actual:1836MB). 2006.145.06:35:38.83/chk_obsdata//k5ts2/T1450627??b.dat file size is correct (nominal:1840MB, actual:1836MB). 2006.145.06:35:39.29/chk_obsdata//k5ts3/T1450627??c.dat file size is correct (nominal:1840MB, actual:1836MB). 2006.145.06:35:39.74/chk_obsdata//k5ts4/T1450627??d.dat file size is correct (nominal:1840MB, actual:1836MB). 2006.145.06:35:40.50/k5log//k5ts1_log_newline 2006.145.06:35:41.22/k5log//k5ts2_log_newline 2006.145.06:35:41.96/k5log//k5ts3_log_newline 2006.145.06:35:42.70/k5log//k5ts4_log_newline 2006.145.06:35:42.72/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.06:35:42.72:setupk4=1 2006.145.06:35:42.72$setupk4/echo=on 2006.145.06:35:42.72$setupk4/pcalon 2006.145.06:35:42.72$pcalon/"no phase cal control is implemented here 2006.145.06:35:42.72$setupk4/"tpicd=stop 2006.145.06:35:42.72$setupk4/"rec=synch_on 2006.145.06:35:42.72$setupk4/"rec_mode=128 2006.145.06:35:42.72$setupk4/!* 2006.145.06:35:42.72$setupk4/recpk4 2006.145.06:35:42.72$recpk4/recpatch= 2006.145.06:35:42.73$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.06:35:42.73$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.06:35:42.73$setupk4/vck44 2006.145.06:35:42.73$vck44/valo=1,524.99 2006.145.06:35:42.73#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.06:35:42.73#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.06:35:42.73#ibcon#ireg 17 cls_cnt 0 2006.145.06:35:42.73#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.06:35:42.73#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.06:35:42.73#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.06:35:42.77#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.06:35:42.81#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.06:35:42.81#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.06:35:42.81#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.06:35:42.81#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.06:35:42.81$vck44/va=1,8 2006.145.06:35:42.81#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.06:35:42.81#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.06:35:42.81#ibcon#ireg 11 cls_cnt 2 2006.145.06:35:42.81#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.06:35:42.81#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.06:35:42.81#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.06:35:42.83#ibcon#[25=AT01-08\r\n] 2006.145.06:35:42.86#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.06:35:42.86#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.06:35:42.86#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.06:35:42.86#ibcon#ireg 7 cls_cnt 0 2006.145.06:35:42.86#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.06:35:43.00#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.06:35:43.00#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.06:35:43.01#ibcon#[25=USB\r\n] 2006.145.06:35:43.04#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.06:35:43.04#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.06:35:43.04#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.06:35:43.04#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.06:35:43.04$vck44/valo=2,534.99 2006.145.06:35:43.04#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.06:35:43.04#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.06:35:43.04#ibcon#ireg 17 cls_cnt 0 2006.145.06:35:43.04#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.06:35:43.04#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.06:35:43.04#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.06:35:43.06#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.06:35:43.10#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.06:35:43.10#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.06:35:43.10#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.06:35:43.10#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.06:35:43.10$vck44/va=2,7 2006.145.06:35:43.10#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.06:35:43.10#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.06:35:43.10#ibcon#ireg 11 cls_cnt 2 2006.145.06:35:43.10#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.06:35:43.16#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.06:35:43.16#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.06:35:43.18#ibcon#[25=AT02-07\r\n] 2006.145.06:35:43.21#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.06:35:43.21#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.06:35:43.21#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.06:35:43.21#ibcon#ireg 7 cls_cnt 0 2006.145.06:35:43.21#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.06:35:43.33#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.06:35:43.33#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.06:35:43.35#ibcon#[25=USB\r\n] 2006.145.06:35:43.38#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.06:35:43.38#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.06:35:43.38#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.06:35:43.38#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.06:35:43.38$vck44/valo=3,564.99 2006.145.06:35:43.38#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.06:35:43.38#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.06:35:43.38#ibcon#ireg 17 cls_cnt 0 2006.145.06:35:43.38#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.06:35:43.38#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.06:35:43.38#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.06:35:43.39#abcon#<5=/05 5.1 8.5 20.33 631016.5\r\n> 2006.145.06:35:43.40#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.06:35:43.41#abcon#{5=INTERFACE CLEAR} 2006.145.06:35:43.44#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.06:35:43.44#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.06:35:43.44#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.06:35:43.44#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.06:35:43.44$vck44/va=3,8 2006.145.06:35:43.44#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.06:35:43.44#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.06:35:43.44#ibcon#ireg 11 cls_cnt 2 2006.145.06:35:43.44#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.06:35:43.47#abcon#[5=S1D000X0/0*\r\n] 2006.145.06:35:43.50#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.06:35:43.50#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.06:35:43.52#ibcon#[25=AT03-08\r\n] 2006.145.06:35:43.55#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.06:35:43.55#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.06:35:43.55#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.06:35:43.55#ibcon#ireg 7 cls_cnt 0 2006.145.06:35:43.55#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.06:35:43.67#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.06:35:43.67#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.06:35:43.69#ibcon#[25=USB\r\n] 2006.145.06:35:43.72#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.06:35:43.72#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.06:35:43.72#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.06:35:43.72#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.06:35:43.72$vck44/valo=4,624.99 2006.145.06:35:43.72#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.06:35:43.72#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.06:35:43.72#ibcon#ireg 17 cls_cnt 0 2006.145.06:35:43.72#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.06:35:43.72#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.06:35:43.72#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.06:35:43.74#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.06:35:43.78#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.06:35:43.78#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.06:35:43.78#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.06:35:43.78#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.06:35:43.78$vck44/va=4,7 2006.145.06:35:43.78#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.06:35:43.78#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.06:35:43.78#ibcon#ireg 11 cls_cnt 2 2006.145.06:35:43.78#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.06:35:43.86#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.06:35:43.86#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.06:35:43.87#ibcon#[25=AT04-07\r\n] 2006.145.06:35:43.90#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.06:35:43.90#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.06:35:43.90#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.06:35:43.90#ibcon#ireg 7 cls_cnt 0 2006.145.06:35:43.90#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.06:35:44.04#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.06:35:44.04#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.06:35:44.05#ibcon#[25=USB\r\n] 2006.145.06:35:44.08#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.06:35:44.08#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.06:35:44.08#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.06:35:44.08#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.06:35:44.08$vck44/valo=5,734.99 2006.145.06:35:44.08#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.06:35:44.08#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.06:35:44.08#ibcon#ireg 17 cls_cnt 0 2006.145.06:35:44.08#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.06:35:44.08#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.06:35:44.08#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.06:35:44.11#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.06:35:44.15#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.06:35:44.15#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.06:35:44.15#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.06:35:44.15#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.06:35:44.15$vck44/va=5,4 2006.145.06:35:44.15#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.06:35:44.15#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.06:35:44.15#ibcon#ireg 11 cls_cnt 2 2006.145.06:35:44.15#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.06:35:44.21#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.06:35:44.21#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.06:35:44.23#ibcon#[25=AT05-04\r\n] 2006.145.06:35:44.26#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.06:35:44.26#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.06:35:44.26#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.06:35:44.26#ibcon#ireg 7 cls_cnt 0 2006.145.06:35:44.26#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.06:35:44.38#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.06:35:44.38#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.06:35:44.40#ibcon#[25=USB\r\n] 2006.145.06:35:44.43#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.06:35:44.43#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.06:35:44.43#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.06:35:44.43#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.06:35:44.43$vck44/valo=6,814.99 2006.145.06:35:44.43#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.06:35:44.43#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.06:35:44.43#ibcon#ireg 17 cls_cnt 0 2006.145.06:35:44.43#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.06:35:44.43#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.06:35:44.43#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.06:35:44.45#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.06:35:44.49#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.06:35:44.49#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.06:35:44.49#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.06:35:44.49#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.06:35:44.49$vck44/va=6,4 2006.145.06:35:44.49#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.06:35:44.49#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.06:35:44.49#ibcon#ireg 11 cls_cnt 2 2006.145.06:35:44.49#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.06:35:44.55#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.06:35:44.55#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.06:35:44.57#ibcon#[25=AT06-04\r\n] 2006.145.06:35:44.60#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.06:35:44.60#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.06:35:44.60#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.06:35:44.60#ibcon#ireg 7 cls_cnt 0 2006.145.06:35:44.60#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.06:35:44.72#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.06:35:44.72#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.06:35:44.74#ibcon#[25=USB\r\n] 2006.145.06:35:44.77#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.06:35:44.77#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.06:35:44.77#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.06:35:44.77#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.06:35:44.77$vck44/valo=7,864.99 2006.145.06:35:44.77#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.06:35:44.77#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.06:35:44.77#ibcon#ireg 17 cls_cnt 0 2006.145.06:35:44.77#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.06:35:44.77#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.06:35:44.77#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.06:35:44.79#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.06:35:44.83#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.06:35:44.83#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.06:35:44.83#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.06:35:44.83#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.06:35:44.83$vck44/va=7,4 2006.145.06:35:44.83#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.06:35:44.83#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.06:35:44.83#ibcon#ireg 11 cls_cnt 2 2006.145.06:35:44.83#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.06:35:44.89#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.06:35:44.89#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.06:35:44.91#ibcon#[25=AT07-04\r\n] 2006.145.06:35:44.94#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.06:35:44.94#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.06:35:44.94#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.06:35:44.94#ibcon#ireg 7 cls_cnt 0 2006.145.06:35:44.94#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.06:35:45.06#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.06:35:45.06#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.06:35:45.08#ibcon#[25=USB\r\n] 2006.145.06:35:45.11#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.06:35:45.11#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.06:35:45.11#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.06:35:45.11#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.06:35:45.11$vck44/valo=8,884.99 2006.145.06:35:45.11#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.06:35:45.11#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.06:35:45.11#ibcon#ireg 17 cls_cnt 0 2006.145.06:35:45.11#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.06:35:45.11#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.06:35:45.11#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.06:35:45.13#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.06:35:45.17#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.06:35:45.17#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.06:35:45.17#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.06:35:45.17#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.06:35:45.17$vck44/va=8,4 2006.145.06:35:45.17#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.06:35:45.17#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.06:35:45.17#ibcon#ireg 11 cls_cnt 2 2006.145.06:35:45.17#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.06:35:45.23#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.06:35:45.23#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.06:35:45.25#ibcon#[25=AT08-04\r\n] 2006.145.06:35:45.28#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.06:35:45.28#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.06:35:45.28#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.06:35:45.28#ibcon#ireg 7 cls_cnt 0 2006.145.06:35:45.28#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.06:35:45.40#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.06:35:45.40#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.06:35:45.42#ibcon#[25=USB\r\n] 2006.145.06:35:45.45#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.06:35:45.45#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.06:35:45.45#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.06:35:45.45#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.06:35:45.45$vck44/vblo=1,629.99 2006.145.06:35:45.45#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.06:35:45.45#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.06:35:45.45#ibcon#ireg 17 cls_cnt 0 2006.145.06:35:45.45#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.06:35:45.45#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.06:35:45.45#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.06:35:45.47#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.06:35:45.51#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.06:35:45.51#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.06:35:45.51#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.06:35:45.51#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.06:35:45.51$vck44/vb=1,3 2006.145.06:35:45.51#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.06:35:45.51#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.06:35:45.51#ibcon#ireg 11 cls_cnt 2 2006.145.06:35:45.51#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.06:35:45.51#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.06:35:45.51#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.06:35:45.53#ibcon#[27=AT01-03\r\n] 2006.145.06:35:45.56#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.06:35:45.56#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.06:35:45.56#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.06:35:45.56#ibcon#ireg 7 cls_cnt 0 2006.145.06:35:45.56#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.06:35:45.68#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.06:35:45.68#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.06:35:45.70#ibcon#[27=USB\r\n] 2006.145.06:35:45.73#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.06:35:45.73#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.06:35:45.73#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.06:35:45.73#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.06:35:45.73$vck44/vblo=2,634.99 2006.145.06:35:45.73#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.06:35:45.73#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.06:35:45.73#ibcon#ireg 17 cls_cnt 0 2006.145.06:35:45.73#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.06:35:45.73#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.06:35:45.73#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.06:35:45.75#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.06:35:45.79#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.06:35:45.79#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.06:35:45.79#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.06:35:45.79#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.06:35:45.79$vck44/vb=2,4 2006.145.06:35:45.79#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.06:35:45.79#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.06:35:45.79#ibcon#ireg 11 cls_cnt 2 2006.145.06:35:45.79#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.06:35:45.85#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.06:35:45.85#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.06:35:45.87#ibcon#[27=AT02-04\r\n] 2006.145.06:35:45.90#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.06:35:45.90#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.06:35:45.90#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.06:35:45.90#ibcon#ireg 7 cls_cnt 0 2006.145.06:35:45.90#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.06:35:46.02#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.06:35:46.02#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.06:35:46.04#ibcon#[27=USB\r\n] 2006.145.06:35:46.07#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.06:35:46.07#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.06:35:46.07#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.06:35:46.07#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.06:35:46.07$vck44/vblo=3,649.99 2006.145.06:35:46.07#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.06:35:46.07#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.06:35:46.07#ibcon#ireg 17 cls_cnt 0 2006.145.06:35:46.07#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.06:35:46.07#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.06:35:46.07#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.06:35:46.09#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.06:35:46.13#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.06:35:46.13#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.06:35:46.13#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.06:35:46.13#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.06:35:46.13$vck44/vb=3,4 2006.145.06:35:46.13#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.06:35:46.13#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.06:35:46.13#ibcon#ireg 11 cls_cnt 2 2006.145.06:35:46.13#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.06:35:46.19#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.06:35:46.19#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.06:35:46.21#ibcon#[27=AT03-04\r\n] 2006.145.06:35:46.24#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.06:35:46.24#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.06:35:46.24#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.06:35:46.24#ibcon#ireg 7 cls_cnt 0 2006.145.06:35:46.24#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.06:35:46.36#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.06:35:46.36#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.06:35:46.38#ibcon#[27=USB\r\n] 2006.145.06:35:46.41#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.06:35:46.41#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.06:35:46.41#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.06:35:46.41#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.06:35:46.41$vck44/vblo=4,679.99 2006.145.06:35:46.41#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.06:35:46.41#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.06:35:46.41#ibcon#ireg 17 cls_cnt 0 2006.145.06:35:46.41#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.06:35:46.41#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.06:35:46.41#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.06:35:46.43#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.06:35:46.47#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.06:35:46.47#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.06:35:46.47#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.06:35:46.47#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.06:35:46.47$vck44/vb=4,4 2006.145.06:35:46.47#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.06:35:46.47#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.06:35:46.47#ibcon#ireg 11 cls_cnt 2 2006.145.06:35:46.47#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.06:35:46.53#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.06:35:46.53#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.06:35:46.55#ibcon#[27=AT04-04\r\n] 2006.145.06:35:46.58#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.06:35:46.58#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.06:35:46.58#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.06:35:46.58#ibcon#ireg 7 cls_cnt 0 2006.145.06:35:46.58#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.06:35:46.70#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.06:35:46.70#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.06:35:46.72#ibcon#[27=USB\r\n] 2006.145.06:35:46.75#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.06:35:46.75#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.06:35:46.75#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.06:35:46.75#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.06:35:46.75$vck44/vblo=5,709.99 2006.145.06:35:46.75#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.06:35:46.75#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.06:35:46.75#ibcon#ireg 17 cls_cnt 0 2006.145.06:35:46.75#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.06:35:46.75#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.06:35:46.75#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.06:35:46.77#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.06:35:46.81#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.06:35:46.81#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.06:35:46.81#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.06:35:46.81#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.06:35:46.81$vck44/vb=5,4 2006.145.06:35:46.81#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.06:35:46.81#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.06:35:46.81#ibcon#ireg 11 cls_cnt 2 2006.145.06:35:46.81#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.06:35:46.87#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.06:35:46.87#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.06:35:46.89#ibcon#[27=AT05-04\r\n] 2006.145.06:35:46.92#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.06:35:46.92#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.06:35:46.92#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.06:35:46.92#ibcon#ireg 7 cls_cnt 0 2006.145.06:35:46.92#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.06:35:47.04#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.06:35:47.04#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.06:35:47.06#ibcon#[27=USB\r\n] 2006.145.06:35:47.09#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.06:35:47.09#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.06:35:47.09#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.06:35:47.09#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.06:35:47.09$vck44/vblo=6,719.99 2006.145.06:35:47.09#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.06:35:47.09#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.06:35:47.09#ibcon#ireg 17 cls_cnt 0 2006.145.06:35:47.09#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.06:35:47.09#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.06:35:47.09#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.06:35:47.11#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.06:35:47.15#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.06:35:47.15#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.06:35:47.15#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.06:35:47.15#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.06:35:47.15$vck44/vb=6,4 2006.145.06:35:47.15#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.06:35:47.15#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.06:35:47.15#ibcon#ireg 11 cls_cnt 2 2006.145.06:35:47.15#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.06:35:47.21#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.06:35:47.21#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.06:35:47.23#ibcon#[27=AT06-04\r\n] 2006.145.06:35:47.26#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.06:35:47.26#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.06:35:47.26#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.06:35:47.26#ibcon#ireg 7 cls_cnt 0 2006.145.06:35:47.26#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.06:35:47.38#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.06:35:47.38#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.06:35:47.40#ibcon#[27=USB\r\n] 2006.145.06:35:47.43#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.06:35:47.43#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.06:35:47.43#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.06:35:47.43#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.06:35:47.43$vck44/vblo=7,734.99 2006.145.06:35:47.43#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.06:35:47.43#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.06:35:47.43#ibcon#ireg 17 cls_cnt 0 2006.145.06:35:47.43#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.06:35:47.43#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.06:35:47.43#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.06:35:47.45#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.06:35:47.49#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.06:35:47.49#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.06:35:47.49#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.06:35:47.49#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.06:35:47.49$vck44/vb=7,4 2006.145.06:35:47.49#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.06:35:47.49#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.06:35:47.49#ibcon#ireg 11 cls_cnt 2 2006.145.06:35:47.49#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.06:35:47.55#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.06:35:47.55#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.06:35:47.57#ibcon#[27=AT07-04\r\n] 2006.145.06:35:47.60#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.06:35:47.60#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.06:35:47.60#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.06:35:47.60#ibcon#ireg 7 cls_cnt 0 2006.145.06:35:47.60#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.06:35:47.72#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.06:35:47.72#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.06:35:47.74#ibcon#[27=USB\r\n] 2006.145.06:35:47.77#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.06:35:47.77#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.06:35:47.77#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.06:35:47.77#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.06:35:47.77$vck44/vblo=8,744.99 2006.145.06:35:47.77#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.06:35:47.77#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.06:35:47.77#ibcon#ireg 17 cls_cnt 0 2006.145.06:35:47.77#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.06:35:47.77#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.06:35:47.77#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.06:35:47.79#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.06:35:47.83#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.06:35:47.83#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.06:35:47.83#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.06:35:47.83#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.06:35:47.83$vck44/vb=8,4 2006.145.06:35:47.83#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.06:35:47.83#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.06:35:47.83#ibcon#ireg 11 cls_cnt 2 2006.145.06:35:47.83#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.06:35:47.89#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.06:35:47.89#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.06:35:47.91#ibcon#[27=AT08-04\r\n] 2006.145.06:35:47.94#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.06:35:47.94#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.06:35:47.94#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.06:35:47.94#ibcon#ireg 7 cls_cnt 0 2006.145.06:35:47.94#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.06:35:48.06#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.06:35:48.06#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.06:35:48.08#ibcon#[27=USB\r\n] 2006.145.06:35:48.11#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.06:35:48.11#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.06:35:48.11#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.06:35:48.11#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.06:35:48.11$vck44/vabw=wide 2006.145.06:35:48.11#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.06:35:48.11#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.06:35:48.11#ibcon#ireg 8 cls_cnt 0 2006.145.06:35:48.11#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.06:35:48.11#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.06:35:48.11#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.06:35:48.13#ibcon#[25=BW32\r\n] 2006.145.06:35:48.16#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.06:35:48.16#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.06:35:48.16#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.06:35:48.16#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.06:35:48.16$vck44/vbbw=wide 2006.145.06:35:48.16#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.06:35:48.16#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.06:35:48.16#ibcon#ireg 8 cls_cnt 0 2006.145.06:35:48.16#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.06:35:48.23#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.06:35:48.23#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.06:35:48.25#ibcon#[27=BW32\r\n] 2006.145.06:35:48.28#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.06:35:48.28#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.06:35:48.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.06:35:48.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.06:35:48.28$setupk4/ifdk4 2006.145.06:35:48.28$ifdk4/lo= 2006.145.06:35:48.28$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.06:35:48.28$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.06:35:48.28$ifdk4/patch= 2006.145.06:35:48.28$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.06:35:48.28$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.06:35:48.28$setupk4/!*+20s 2006.145.06:35:53.56#abcon#<5=/05 5.1 8.5 20.33 611016.6\r\n> 2006.145.06:35:53.58#abcon#{5=INTERFACE CLEAR} 2006.145.06:35:53.64#abcon#[5=S1D000X0/0*\r\n] 2006.145.06:36:00.14#trakl#Source acquired 2006.145.06:36:02.14#flagr#flagr/antenna,acquired 2006.145.06:36:02.73$setupk4/"tpicd 2006.145.06:36:02.73$setupk4/echo=off 2006.145.06:36:02.73$setupk4/xlog=off 2006.145.06:36:02.73:!2006.145.06:41:22 2006.145.06:41:22.00:preob 2006.145.06:41:22.14/onsource/TRACKING 2006.145.06:41:22.14:!2006.145.06:41:32 2006.145.06:41:32.00:"tape 2006.145.06:41:32.00:"st=record 2006.145.06:41:32.00:data_valid=on 2006.145.06:41:32.00:midob 2006.145.06:41:32.14/onsource/TRACKING 2006.145.06:41:32.14/wx/20.10,1016.6,63 2006.145.06:41:32.20/cable/+6.5389E-03 2006.145.06:41:33.29/va/01,08,usb,yes,28,30 2006.145.06:41:33.29/va/02,07,usb,yes,30,30 2006.145.06:41:33.29/va/03,08,usb,yes,27,28 2006.145.06:41:33.29/va/04,07,usb,yes,31,33 2006.145.06:41:33.29/va/05,04,usb,yes,27,27 2006.145.06:41:33.29/va/06,04,usb,yes,30,30 2006.145.06:41:33.29/va/07,04,usb,yes,31,32 2006.145.06:41:33.29/va/08,04,usb,yes,26,31 2006.145.06:41:33.52/valo/01,524.99,yes,locked 2006.145.06:41:33.52/valo/02,534.99,yes,locked 2006.145.06:41:33.52/valo/03,564.99,yes,locked 2006.145.06:41:33.52/valo/04,624.99,yes,locked 2006.145.06:41:33.52/valo/05,734.99,yes,locked 2006.145.06:41:33.52/valo/06,814.99,yes,locked 2006.145.06:41:33.52/valo/07,864.99,yes,locked 2006.145.06:41:33.52/valo/08,884.99,yes,locked 2006.145.06:41:34.61/vb/01,03,usb,yes,35,33 2006.145.06:41:34.61/vb/02,04,usb,yes,31,31 2006.145.06:41:34.61/vb/03,04,usb,yes,28,31 2006.145.06:41:34.61/vb/04,04,usb,yes,32,31 2006.145.06:41:34.61/vb/05,04,usb,yes,25,27 2006.145.06:41:34.61/vb/06,04,usb,yes,29,25 2006.145.06:41:34.61/vb/07,04,usb,yes,28,28 2006.145.06:41:34.61/vb/08,04,usb,yes,26,29 2006.145.06:41:34.84/vblo/01,629.99,yes,locked 2006.145.06:41:34.84/vblo/02,634.99,yes,locked 2006.145.06:41:34.84/vblo/03,649.99,yes,locked 2006.145.06:41:34.84/vblo/04,679.99,yes,locked 2006.145.06:41:34.84/vblo/05,709.99,yes,locked 2006.145.06:41:34.84/vblo/06,719.99,yes,locked 2006.145.06:41:34.84/vblo/07,734.99,yes,locked 2006.145.06:41:34.84/vblo/08,744.99,yes,locked 2006.145.06:41:34.99/vabw/8 2006.145.06:41:35.14/vbbw/8 2006.145.06:41:35.23/xfe/off,on,14.5 2006.145.06:41:35.60/ifatt/23,28,28,28 2006.145.06:41:36.07/fmout-gps/S +5.4E-08 2006.145.06:41:36.11:!2006.145.06:42:22 2006.145.06:42:22.01:data_valid=off 2006.145.06:42:22.01:"et 2006.145.06:42:22.02:!+3s 2006.145.06:42:25.03:"tape 2006.145.06:42:25.03:postob 2006.145.06:42:25.26/cable/+6.5397E-03 2006.145.06:42:25.26/wx/20.07,1016.6,67 2006.145.06:42:25.33/fmout-gps/S +5.3E-08 2006.145.06:42:25.33:scan_name=145-0644,jd0605,80 2006.145.06:42:25.33:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.145.06:42:26.14#flagr#flagr/antenna,new-source 2006.145.06:42:26.14:checkk5 2006.145.06:42:26.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.06:42:27.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.06:42:27.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.06:42:27.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.06:42:28.32/chk_obsdata//k5ts1/T1450641??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.145.06:42:28.78/chk_obsdata//k5ts2/T1450641??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.145.06:42:29.22/chk_obsdata//k5ts3/T1450641??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.145.06:42:29.65/chk_obsdata//k5ts4/T1450641??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.145.06:42:30.40/k5log//k5ts1_log_newline 2006.145.06:42:31.16/k5log//k5ts2_log_newline 2006.145.06:42:31.88/k5log//k5ts3_log_newline 2006.145.06:42:32.63/k5log//k5ts4_log_newline 2006.145.06:42:32.65/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.06:42:32.65:setupk4=1 2006.145.06:42:32.65$setupk4/echo=on 2006.145.06:42:32.65$setupk4/pcalon 2006.145.06:42:32.65$pcalon/"no phase cal control is implemented here 2006.145.06:42:32.65$setupk4/"tpicd=stop 2006.145.06:42:32.65$setupk4/"rec=synch_on 2006.145.06:42:32.65$setupk4/"rec_mode=128 2006.145.06:42:32.65$setupk4/!* 2006.145.06:42:32.66$setupk4/recpk4 2006.145.06:42:32.66$recpk4/recpatch= 2006.145.06:42:32.66$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.06:42:32.66$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.06:42:32.66$setupk4/vck44 2006.145.06:42:32.66$vck44/valo=1,524.99 2006.145.06:42:32.66#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.06:42:32.66#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.06:42:32.66#ibcon#ireg 17 cls_cnt 0 2006.145.06:42:32.66#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.06:42:32.66#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.06:42:32.66#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.06:42:32.70#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.06:42:32.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.06:42:32.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.06:42:32.75#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.06:42:32.75#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.06:42:32.75$vck44/va=1,8 2006.145.06:42:32.75#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.06:42:32.75#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.06:42:32.75#ibcon#ireg 11 cls_cnt 2 2006.145.06:42:32.75#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.06:42:32.75#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.06:42:32.75#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.06:42:32.77#ibcon#[25=AT01-08\r\n] 2006.145.06:42:32.80#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.06:42:32.80#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.06:42:32.80#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.06:42:32.80#ibcon#ireg 7 cls_cnt 0 2006.145.06:42:32.80#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.06:42:32.92#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.06:42:32.92#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.06:42:32.94#ibcon#[25=USB\r\n] 2006.145.06:42:32.99#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.06:42:32.99#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.06:42:32.99#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.06:42:32.99#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.06:42:32.99$vck44/valo=2,534.99 2006.145.06:42:32.99#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.06:42:32.99#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.06:42:32.99#ibcon#ireg 17 cls_cnt 0 2006.145.06:42:32.99#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.06:42:32.99#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.06:42:32.99#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.06:42:33.00#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.06:42:33.04#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.06:42:33.04#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.06:42:33.04#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.06:42:33.04#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.06:42:33.04$vck44/va=2,7 2006.145.06:42:33.04#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.06:42:33.04#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.06:42:33.04#ibcon#ireg 11 cls_cnt 2 2006.145.06:42:33.04#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.06:42:33.11#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.06:42:33.11#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.06:42:33.13#ibcon#[25=AT02-07\r\n] 2006.145.06:42:33.16#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.06:42:33.16#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.06:42:33.16#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.06:42:33.16#ibcon#ireg 7 cls_cnt 0 2006.145.06:42:33.16#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.06:42:33.28#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.06:42:33.28#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.06:42:33.30#ibcon#[25=USB\r\n] 2006.145.06:42:33.33#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.06:42:33.33#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.06:42:33.33#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.06:42:33.33#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.06:42:33.33$vck44/valo=3,564.99 2006.145.06:42:33.33#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.06:42:33.33#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.06:42:33.33#ibcon#ireg 17 cls_cnt 0 2006.145.06:42:33.33#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.06:42:33.33#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.06:42:33.33#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.06:42:33.35#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.06:42:33.39#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.06:42:33.39#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.06:42:33.39#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.06:42:33.39#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.06:42:33.39$vck44/va=3,8 2006.145.06:42:33.39#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.06:42:33.39#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.06:42:33.39#ibcon#ireg 11 cls_cnt 2 2006.145.06:42:33.39#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.06:42:33.45#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.06:42:33.45#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.06:42:33.47#ibcon#[25=AT03-08\r\n] 2006.145.06:42:33.50#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.06:42:33.50#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.06:42:33.50#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.06:42:33.50#ibcon#ireg 7 cls_cnt 0 2006.145.06:42:33.50#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.06:42:33.62#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.06:42:33.62#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.06:42:33.64#ibcon#[25=USB\r\n] 2006.145.06:42:33.67#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.06:42:33.67#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.06:42:33.67#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.06:42:33.67#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.06:42:33.67$vck44/valo=4,624.99 2006.145.06:42:33.67#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.06:42:33.67#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.06:42:33.67#ibcon#ireg 17 cls_cnt 0 2006.145.06:42:33.67#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.06:42:33.67#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.06:42:33.67#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.06:42:33.69#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.06:42:33.73#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.06:42:33.73#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.06:42:33.73#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.06:42:33.73#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.06:42:33.73$vck44/va=4,7 2006.145.06:42:33.73#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.06:42:33.73#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.06:42:33.73#ibcon#ireg 11 cls_cnt 2 2006.145.06:42:33.73#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.06:42:33.79#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.06:42:33.79#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.06:42:33.81#ibcon#[25=AT04-07\r\n] 2006.145.06:42:33.84#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.06:42:33.84#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.06:42:33.84#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.06:42:33.84#ibcon#ireg 7 cls_cnt 0 2006.145.06:42:33.84#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.06:42:33.96#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.06:42:33.96#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.06:42:33.98#ibcon#[25=USB\r\n] 2006.145.06:42:34.01#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.06:42:34.01#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.06:42:34.01#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.06:42:34.01#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.06:42:34.01$vck44/valo=5,734.99 2006.145.06:42:34.01#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.06:42:34.01#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.06:42:34.01#ibcon#ireg 17 cls_cnt 0 2006.145.06:42:34.01#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.06:42:34.01#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.06:42:34.01#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.06:42:34.03#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.06:42:34.07#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.06:42:34.07#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.06:42:34.07#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.06:42:34.07#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.06:42:34.07$vck44/va=5,4 2006.145.06:42:34.07#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.06:42:34.07#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.06:42:34.07#ibcon#ireg 11 cls_cnt 2 2006.145.06:42:34.07#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.06:42:34.13#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.06:42:34.13#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.06:42:34.15#ibcon#[25=AT05-04\r\n] 2006.145.06:42:34.18#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.06:42:34.18#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.06:42:34.18#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.06:42:34.18#ibcon#ireg 7 cls_cnt 0 2006.145.06:42:34.18#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.06:42:34.30#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.06:42:34.30#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.06:42:34.32#ibcon#[25=USB\r\n] 2006.145.06:42:34.35#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.06:42:34.35#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.06:42:34.35#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.06:42:34.35#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.06:42:34.35$vck44/valo=6,814.99 2006.145.06:42:34.35#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.06:42:34.35#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.06:42:34.35#ibcon#ireg 17 cls_cnt 0 2006.145.06:42:34.35#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.06:42:34.35#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.06:42:34.35#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.06:42:34.37#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.06:42:34.41#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.06:42:34.41#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.06:42:34.41#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.06:42:34.41#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.06:42:34.41$vck44/va=6,4 2006.145.06:42:34.41#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.06:42:34.41#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.06:42:34.41#ibcon#ireg 11 cls_cnt 2 2006.145.06:42:34.41#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.06:42:34.47#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.06:42:34.47#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.06:42:34.49#ibcon#[25=AT06-04\r\n] 2006.145.06:42:34.52#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.06:42:34.52#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.06:42:34.52#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.06:42:34.52#ibcon#ireg 7 cls_cnt 0 2006.145.06:42:34.52#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.06:42:34.64#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.06:42:34.64#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.06:42:34.66#ibcon#[25=USB\r\n] 2006.145.06:42:34.69#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.06:42:34.69#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.06:42:34.69#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.06:42:34.69#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.06:42:34.69$vck44/valo=7,864.99 2006.145.06:42:34.69#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.06:42:34.69#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.06:42:34.69#ibcon#ireg 17 cls_cnt 0 2006.145.06:42:34.69#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.06:42:34.69#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.06:42:34.69#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.06:42:34.71#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.06:42:34.75#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.06:42:34.75#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.06:42:34.75#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.06:42:34.75#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.06:42:34.75$vck44/va=7,4 2006.145.06:42:34.75#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.06:42:34.75#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.06:42:34.75#ibcon#ireg 11 cls_cnt 2 2006.145.06:42:34.75#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.06:42:34.81#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.06:42:34.81#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.06:42:34.83#ibcon#[25=AT07-04\r\n] 2006.145.06:42:34.86#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.06:42:34.86#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.06:42:34.86#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.06:42:34.86#ibcon#ireg 7 cls_cnt 0 2006.145.06:42:34.86#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.06:42:34.98#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.06:42:34.98#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.06:42:35.00#ibcon#[25=USB\r\n] 2006.145.06:42:35.03#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.06:42:35.03#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.06:42:35.03#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.06:42:35.03#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.06:42:35.03$vck44/valo=8,884.99 2006.145.06:42:35.03#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.06:42:35.03#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.06:42:35.03#ibcon#ireg 17 cls_cnt 0 2006.145.06:42:35.03#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.06:42:35.03#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.06:42:35.03#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.06:42:35.05#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.06:42:35.09#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.06:42:35.09#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.06:42:35.09#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.06:42:35.09#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.06:42:35.09$vck44/va=8,4 2006.145.06:42:35.09#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.06:42:35.09#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.06:42:35.09#ibcon#ireg 11 cls_cnt 2 2006.145.06:42:35.09#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.06:42:35.15#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.06:42:35.15#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.06:42:35.17#ibcon#[25=AT08-04\r\n] 2006.145.06:42:35.20#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.06:42:35.20#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.06:42:35.20#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.06:42:35.20#ibcon#ireg 7 cls_cnt 0 2006.145.06:42:35.20#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.06:42:35.34#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.06:42:35.34#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.06:42:35.36#ibcon#[25=USB\r\n] 2006.145.06:42:35.39#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.06:42:35.39#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.06:42:35.39#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.06:42:35.39#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.06:42:35.39$vck44/vblo=1,629.99 2006.145.06:42:35.39#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.06:42:35.39#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.06:42:35.39#ibcon#ireg 17 cls_cnt 0 2006.145.06:42:35.39#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.06:42:35.39#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.06:42:35.39#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.06:42:35.41#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.06:42:35.45#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.06:42:35.45#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.06:42:35.45#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.06:42:35.45#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.06:42:35.45$vck44/vb=1,3 2006.145.06:42:35.45#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.06:42:35.45#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.06:42:35.45#ibcon#ireg 11 cls_cnt 2 2006.145.06:42:35.45#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.06:42:35.45#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.06:42:35.45#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.06:42:35.47#ibcon#[27=AT01-03\r\n] 2006.145.06:42:35.50#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.06:42:35.50#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.06:42:35.50#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.06:42:35.50#ibcon#ireg 7 cls_cnt 0 2006.145.06:42:35.50#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.06:42:35.62#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.06:42:35.62#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.06:42:35.64#ibcon#[27=USB\r\n] 2006.145.06:42:35.67#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.06:42:35.67#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.06:42:35.67#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.06:42:35.67#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.06:42:35.67$vck44/vblo=2,634.99 2006.145.06:42:35.67#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.06:42:35.67#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.06:42:35.67#ibcon#ireg 17 cls_cnt 0 2006.145.06:42:35.67#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.06:42:35.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.06:42:35.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.06:42:35.69#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.06:42:35.73#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.06:42:35.73#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.06:42:35.73#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.06:42:35.73#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.06:42:35.73$vck44/vb=2,4 2006.145.06:42:35.73#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.06:42:35.73#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.06:42:35.73#ibcon#ireg 11 cls_cnt 2 2006.145.06:42:35.73#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.06:42:35.79#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.06:42:35.79#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.06:42:35.81#ibcon#[27=AT02-04\r\n] 2006.145.06:42:35.84#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.06:42:35.84#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.06:42:35.84#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.06:42:35.84#ibcon#ireg 7 cls_cnt 0 2006.145.06:42:35.84#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.06:42:35.96#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.06:42:35.96#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.06:42:35.98#ibcon#[27=USB\r\n] 2006.145.06:42:36.01#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.06:42:36.01#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.06:42:36.01#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.06:42:36.01#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.06:42:36.01$vck44/vblo=3,649.99 2006.145.06:42:36.01#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.06:42:36.01#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.06:42:36.01#ibcon#ireg 17 cls_cnt 0 2006.145.06:42:36.01#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.06:42:36.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.06:42:36.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.06:42:36.03#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.06:42:36.07#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.06:42:36.07#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.06:42:36.07#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.06:42:36.07#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.06:42:36.07$vck44/vb=3,4 2006.145.06:42:36.07#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.06:42:36.07#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.06:42:36.07#ibcon#ireg 11 cls_cnt 2 2006.145.06:42:36.07#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.06:42:36.13#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.06:42:36.13#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.06:42:36.15#ibcon#[27=AT03-04\r\n] 2006.145.06:42:36.18#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.06:42:36.18#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.06:42:36.18#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.06:42:36.18#ibcon#ireg 7 cls_cnt 0 2006.145.06:42:36.18#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.06:42:36.30#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.06:42:36.30#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.06:42:36.32#ibcon#[27=USB\r\n] 2006.145.06:42:36.35#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.06:42:36.35#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.06:42:36.35#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.06:42:36.35#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.06:42:36.35$vck44/vblo=4,679.99 2006.145.06:42:36.35#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.06:42:36.35#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.06:42:36.35#ibcon#ireg 17 cls_cnt 0 2006.145.06:42:36.35#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.06:42:36.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.06:42:36.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.06:42:36.37#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.06:42:36.41#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.06:42:36.41#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.06:42:36.41#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.06:42:36.41#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.06:42:36.41$vck44/vb=4,4 2006.145.06:42:36.41#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.06:42:36.41#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.06:42:36.41#ibcon#ireg 11 cls_cnt 2 2006.145.06:42:36.41#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.06:42:36.47#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.06:42:36.47#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.06:42:36.49#ibcon#[27=AT04-04\r\n] 2006.145.06:42:36.52#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.06:42:36.52#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.06:42:36.52#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.06:42:36.52#ibcon#ireg 7 cls_cnt 0 2006.145.06:42:36.52#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.06:42:36.64#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.06:42:36.64#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.06:42:36.66#ibcon#[27=USB\r\n] 2006.145.06:42:36.69#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.06:42:36.69#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.06:42:36.69#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.06:42:36.69#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.06:42:36.69$vck44/vblo=5,709.99 2006.145.06:42:36.69#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.06:42:36.69#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.06:42:36.69#ibcon#ireg 17 cls_cnt 0 2006.145.06:42:36.69#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.06:42:36.69#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.06:42:36.69#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.06:42:36.71#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.06:42:36.75#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.06:42:36.75#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.06:42:36.75#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.06:42:36.75#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.06:42:36.75$vck44/vb=5,4 2006.145.06:42:36.75#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.06:42:36.75#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.06:42:36.75#ibcon#ireg 11 cls_cnt 2 2006.145.06:42:36.75#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.06:42:36.81#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.06:42:36.81#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.06:42:36.83#ibcon#[27=AT05-04\r\n] 2006.145.06:42:36.86#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.06:42:36.86#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.06:42:36.86#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.06:42:36.86#ibcon#ireg 7 cls_cnt 0 2006.145.06:42:36.86#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.06:42:36.98#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.06:42:36.98#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.06:42:37.00#ibcon#[27=USB\r\n] 2006.145.06:42:37.03#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.06:42:37.03#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.06:42:37.03#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.06:42:37.03#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.06:42:37.03$vck44/vblo=6,719.99 2006.145.06:42:37.03#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.06:42:37.03#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.06:42:37.03#ibcon#ireg 17 cls_cnt 0 2006.145.06:42:37.03#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.06:42:37.03#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.06:42:37.03#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.06:42:37.05#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.06:42:37.09#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.06:42:37.09#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.06:42:37.09#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.06:42:37.09#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.06:42:37.09$vck44/vb=6,4 2006.145.06:42:37.09#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.06:42:37.09#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.06:42:37.09#ibcon#ireg 11 cls_cnt 2 2006.145.06:42:37.09#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.06:42:37.15#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.06:42:37.15#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.06:42:37.17#ibcon#[27=AT06-04\r\n] 2006.145.06:42:37.20#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.06:42:37.20#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.06:42:37.20#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.06:42:37.20#ibcon#ireg 7 cls_cnt 0 2006.145.06:42:37.20#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.06:42:37.32#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.06:42:37.32#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.06:42:37.34#ibcon#[27=USB\r\n] 2006.145.06:42:37.37#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.06:42:37.37#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.06:42:37.37#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.06:42:37.37#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.06:42:37.37$vck44/vblo=7,734.99 2006.145.06:42:37.37#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.06:42:37.37#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.06:42:37.37#ibcon#ireg 17 cls_cnt 0 2006.145.06:42:37.37#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.06:42:37.37#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.06:42:37.37#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.06:42:37.39#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.06:42:37.43#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.06:42:37.43#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.06:42:37.43#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.06:42:37.43#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.06:42:37.43$vck44/vb=7,4 2006.145.06:42:37.43#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.06:42:37.43#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.06:42:37.43#ibcon#ireg 11 cls_cnt 2 2006.145.06:42:37.43#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.06:42:37.49#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.06:42:37.49#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.06:42:37.51#ibcon#[27=AT07-04\r\n] 2006.145.06:42:37.54#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.06:42:37.54#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.06:42:37.54#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.06:42:37.54#ibcon#ireg 7 cls_cnt 0 2006.145.06:42:37.54#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.06:42:37.66#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.06:42:37.66#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.06:42:37.68#ibcon#[27=USB\r\n] 2006.145.06:42:37.71#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.06:42:37.71#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.06:42:37.71#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.06:42:37.71#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.06:42:37.71$vck44/vblo=8,744.99 2006.145.06:42:37.71#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.06:42:37.71#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.06:42:37.71#ibcon#ireg 17 cls_cnt 0 2006.145.06:42:37.71#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.06:42:37.71#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.06:42:37.71#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.06:42:37.73#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.06:42:37.77#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.06:42:37.77#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.06:42:37.77#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.06:42:37.77#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.06:42:37.77$vck44/vb=8,4 2006.145.06:42:37.77#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.06:42:37.77#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.06:42:37.77#ibcon#ireg 11 cls_cnt 2 2006.145.06:42:37.77#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.06:42:37.83#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.06:42:37.83#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.06:42:37.85#ibcon#[27=AT08-04\r\n] 2006.145.06:42:37.88#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.06:42:37.88#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.06:42:37.88#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.06:42:37.88#ibcon#ireg 7 cls_cnt 0 2006.145.06:42:37.88#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.06:42:38.00#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.06:42:38.00#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.06:42:38.02#ibcon#[27=USB\r\n] 2006.145.06:42:38.05#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.06:42:38.05#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.06:42:38.05#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.06:42:38.05#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.06:42:38.05$vck44/vabw=wide 2006.145.06:42:38.05#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.06:42:38.05#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.06:42:38.05#ibcon#ireg 8 cls_cnt 0 2006.145.06:42:38.05#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.06:42:38.05#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.06:42:38.05#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.06:42:38.07#ibcon#[25=BW32\r\n] 2006.145.06:42:38.10#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.06:42:38.10#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.06:42:38.10#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.06:42:38.10#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.06:42:38.10$vck44/vbbw=wide 2006.145.06:42:38.10#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.06:42:38.10#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.06:42:38.10#ibcon#ireg 8 cls_cnt 0 2006.145.06:42:38.10#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.06:42:38.17#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.06:42:38.17#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.06:42:38.19#ibcon#[27=BW32\r\n] 2006.145.06:42:38.22#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.06:42:38.22#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.06:42:38.22#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.06:42:38.22#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.06:42:38.22$setupk4/ifdk4 2006.145.06:42:38.22$ifdk4/lo= 2006.145.06:42:38.22$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.06:42:38.22$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.06:42:38.22$ifdk4/patch= 2006.145.06:42:38.22$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.06:42:38.22$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.06:42:38.22$setupk4/!*+20s 2006.145.06:42:40.50#abcon#<5=/05 5.1 8.5 20.06 621016.6\r\n> 2006.145.06:42:40.52#abcon#{5=INTERFACE CLEAR} 2006.145.06:42:40.58#abcon#[5=S1D000X0/0*\r\n] 2006.145.06:42:48.13#trakl#Source acquired 2006.145.06:42:48.13#flagr#flagr/antenna,acquired 2006.145.06:42:50.67#abcon#<5=/05 5.0 8.5 20.06 611016.6\r\n> 2006.145.06:42:50.69#abcon#{5=INTERFACE CLEAR} 2006.145.06:42:50.75#abcon#[5=S1D000X0/0*\r\n] 2006.145.06:42:52.66$setupk4/"tpicd 2006.145.06:42:52.66$setupk4/echo=off 2006.145.06:42:52.66$setupk4/xlog=off 2006.145.06:42:52.66:!2006.145.06:44:38 2006.145.06:44:38.00:preob 2006.145.06:44:38.14/onsource/TRACKING 2006.145.06:44:38.14:!2006.145.06:44:48 2006.145.06:44:48.00:"tape 2006.145.06:44:48.00:"st=record 2006.145.06:44:48.00:data_valid=on 2006.145.06:44:48.00:midob 2006.145.06:44:48.14/onsource/TRACKING 2006.145.06:44:48.14/wx/20.00,1016.6,63 2006.145.06:44:48.30/cable/+6.5398E-03 2006.145.06:44:49.39/va/01,08,usb,yes,28,30 2006.145.06:44:49.39/va/02,07,usb,yes,30,31 2006.145.06:44:49.39/va/03,08,usb,yes,27,28 2006.145.06:44:49.39/va/04,07,usb,yes,31,33 2006.145.06:44:49.39/va/05,04,usb,yes,27,28 2006.145.06:44:49.39/va/06,04,usb,yes,30,30 2006.145.06:44:49.39/va/07,04,usb,yes,31,32 2006.145.06:44:49.39/va/08,04,usb,yes,26,32 2006.145.06:44:49.62/valo/01,524.99,yes,locked 2006.145.06:44:49.62/valo/02,534.99,yes,locked 2006.145.06:44:49.62/valo/03,564.99,yes,locked 2006.145.06:44:49.62/valo/04,624.99,yes,locked 2006.145.06:44:49.62/valo/05,734.99,yes,locked 2006.145.06:44:49.62/valo/06,814.99,yes,locked 2006.145.06:44:49.62/valo/07,864.99,yes,locked 2006.145.06:44:49.62/valo/08,884.99,yes,locked 2006.145.06:44:50.71/vb/01,03,usb,yes,35,33 2006.145.06:44:50.71/vb/02,04,usb,yes,31,31 2006.145.06:44:50.71/vb/03,04,usb,yes,28,31 2006.145.06:44:50.71/vb/04,04,usb,yes,32,31 2006.145.06:44:50.71/vb/05,04,usb,yes,25,27 2006.145.06:44:50.71/vb/06,04,usb,yes,29,26 2006.145.06:44:50.71/vb/07,04,usb,yes,29,29 2006.145.06:44:50.71/vb/08,04,usb,yes,27,30 2006.145.06:44:50.95/vblo/01,629.99,yes,locked 2006.145.06:44:50.95/vblo/02,634.99,yes,locked 2006.145.06:44:50.95/vblo/03,649.99,yes,locked 2006.145.06:44:50.95/vblo/04,679.99,yes,locked 2006.145.06:44:50.95/vblo/05,709.99,yes,locked 2006.145.06:44:50.95/vblo/06,719.99,yes,locked 2006.145.06:44:50.95/vblo/07,734.99,yes,locked 2006.145.06:44:50.95/vblo/08,744.99,yes,locked 2006.145.06:44:51.10/vabw/8 2006.145.06:44:51.25/vbbw/8 2006.145.06:44:51.34/xfe/off,on,15.2 2006.145.06:44:51.72/ifatt/23,28,28,28 2006.145.06:44:52.07/fmout-gps/S +5.4E-08 2006.145.06:44:52.15:!2006.145.06:46:08 2006.145.06:46:08.00:data_valid=off 2006.145.06:46:08.00:"et 2006.145.06:46:08.01:!+3s 2006.145.06:46:11.02:"tape 2006.145.06:46:11.02:postob 2006.145.06:46:11.12/cable/+6.5412E-03 2006.145.06:46:11.12/wx/19.97,1016.6,62 2006.145.06:46:11.20/fmout-gps/S +5.3E-08 2006.145.06:46:11.20:scan_name=145-0649,jd0605,784 2006.145.06:46:11.20:source=0133+476,013658.59,475129.1,2000.0,ccw 2006.145.06:46:12.14#flagr#flagr/antenna,new-source 2006.145.06:46:12.14:checkk5 2006.145.06:46:12.61/chk_autoobs//k5ts1/ autoobs is running! 2006.145.06:46:13.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.06:46:13.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.06:46:13.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.06:46:14.31/chk_obsdata//k5ts1/T1450644??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.145.06:46:14.76/chk_obsdata//k5ts2/T1450644??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.145.06:46:15.21/chk_obsdata//k5ts3/T1450644??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.145.06:46:15.65/chk_obsdata//k5ts4/T1450644??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.145.06:46:16.40/k5log//k5ts1_log_newline 2006.145.06:46:17.14/k5log//k5ts2_log_newline 2006.145.06:46:17.89/k5log//k5ts3_log_newline 2006.145.06:46:18.62/k5log//k5ts4_log_newline 2006.145.06:46:18.64/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.06:46:18.64:setupk4=1 2006.145.06:46:18.64$setupk4/echo=on 2006.145.06:46:18.64$setupk4/pcalon 2006.145.06:46:18.64$pcalon/"no phase cal control is implemented here 2006.145.06:46:18.64$setupk4/"tpicd=stop 2006.145.06:46:18.64$setupk4/"rec=synch_on 2006.145.06:46:18.64$setupk4/"rec_mode=128 2006.145.06:46:18.64$setupk4/!* 2006.145.06:46:18.64$setupk4/recpk4 2006.145.06:46:18.64$recpk4/recpatch= 2006.145.06:46:18.65$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.06:46:18.65$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.06:46:18.65$setupk4/vck44 2006.145.06:46:18.65$vck44/valo=1,524.99 2006.145.06:46:18.65#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.06:46:18.65#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.06:46:18.65#ibcon#ireg 17 cls_cnt 0 2006.145.06:46:18.65#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.06:46:18.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.06:46:18.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.06:46:18.69#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.06:46:18.74#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.06:46:18.74#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.06:46:18.74#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.06:46:18.74#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.06:46:18.74$vck44/va=1,8 2006.145.06:46:18.74#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.06:46:18.74#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.06:46:18.74#ibcon#ireg 11 cls_cnt 2 2006.145.06:46:18.74#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.06:46:18.74#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.06:46:18.74#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.06:46:18.76#ibcon#[25=AT01-08\r\n] 2006.145.06:46:18.79#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.06:46:18.79#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.06:46:18.79#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.06:46:18.79#ibcon#ireg 7 cls_cnt 0 2006.145.06:46:18.79#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.06:46:18.91#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.06:46:18.91#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.06:46:18.93#ibcon#[25=USB\r\n] 2006.145.06:46:18.98#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.06:46:18.98#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.06:46:18.98#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.06:46:18.98#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.06:46:18.98$vck44/valo=2,534.99 2006.145.06:46:18.98#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.06:46:18.98#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.06:46:18.98#ibcon#ireg 17 cls_cnt 0 2006.145.06:46:18.98#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.06:46:18.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.06:46:18.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.06:46:18.99#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.06:46:19.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.06:46:19.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.06:46:19.03#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.06:46:19.03#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.06:46:19.03$vck44/va=2,7 2006.145.06:46:19.03#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.06:46:19.03#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.06:46:19.03#ibcon#ireg 11 cls_cnt 2 2006.145.06:46:19.03#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.06:46:19.10#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.06:46:19.10#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.06:46:19.12#ibcon#[25=AT02-07\r\n] 2006.145.06:46:19.15#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.06:46:19.15#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.06:46:19.15#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.06:46:19.15#ibcon#ireg 7 cls_cnt 0 2006.145.06:46:19.15#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.06:46:19.27#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.06:46:19.27#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.06:46:19.29#ibcon#[25=USB\r\n] 2006.145.06:46:19.32#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.06:46:19.32#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.06:46:19.32#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.06:46:19.32#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.06:46:19.32$vck44/valo=3,564.99 2006.145.06:46:19.32#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.06:46:19.32#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.06:46:19.32#ibcon#ireg 17 cls_cnt 0 2006.145.06:46:19.32#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.06:46:19.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.06:46:19.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.06:46:19.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.06:46:19.38#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.06:46:19.38#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.06:46:19.38#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.06:46:19.38#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.06:46:19.38$vck44/va=3,8 2006.145.06:46:19.38#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.06:46:19.38#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.06:46:19.38#ibcon#ireg 11 cls_cnt 2 2006.145.06:46:19.38#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.06:46:19.44#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.06:46:19.44#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.06:46:19.46#ibcon#[25=AT03-08\r\n] 2006.145.06:46:19.49#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.06:46:19.49#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.06:46:19.49#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.06:46:19.49#ibcon#ireg 7 cls_cnt 0 2006.145.06:46:19.49#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.06:46:19.61#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.06:46:19.61#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.06:46:19.63#ibcon#[25=USB\r\n] 2006.145.06:46:19.66#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.06:46:19.66#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.06:46:19.66#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.06:46:19.66#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.06:46:19.66$vck44/valo=4,624.99 2006.145.06:46:19.66#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.06:46:19.66#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.06:46:19.66#ibcon#ireg 17 cls_cnt 0 2006.145.06:46:19.66#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.06:46:19.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.06:46:19.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.06:46:19.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.06:46:19.72#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.06:46:19.72#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.06:46:19.72#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.06:46:19.72#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.06:46:19.72$vck44/va=4,7 2006.145.06:46:19.72#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.06:46:19.72#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.06:46:19.72#ibcon#ireg 11 cls_cnt 2 2006.145.06:46:19.72#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.06:46:19.78#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.06:46:19.78#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.06:46:19.80#ibcon#[25=AT04-07\r\n] 2006.145.06:46:19.83#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.06:46:19.83#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.06:46:19.83#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.06:46:19.83#ibcon#ireg 7 cls_cnt 0 2006.145.06:46:19.83#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.06:46:19.95#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.06:46:19.95#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.06:46:19.97#ibcon#[25=USB\r\n] 2006.145.06:46:20.00#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.06:46:20.00#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.06:46:20.00#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.06:46:20.00#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.06:46:20.00$vck44/valo=5,734.99 2006.145.06:46:20.00#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.06:46:20.00#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.06:46:20.00#ibcon#ireg 17 cls_cnt 0 2006.145.06:46:20.00#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.06:46:20.00#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.06:46:20.00#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.06:46:20.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.06:46:20.06#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.06:46:20.06#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.06:46:20.06#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.06:46:20.06#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.06:46:20.06$vck44/va=5,4 2006.145.06:46:20.06#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.06:46:20.06#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.06:46:20.06#ibcon#ireg 11 cls_cnt 2 2006.145.06:46:20.06#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.06:46:20.13#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.06:46:20.13#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.06:46:20.15#ibcon#[25=AT05-04\r\n] 2006.145.06:46:20.18#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.06:46:20.18#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.06:46:20.18#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.06:46:20.18#ibcon#ireg 7 cls_cnt 0 2006.145.06:46:20.18#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.06:46:20.30#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.06:46:20.30#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.06:46:20.32#ibcon#[25=USB\r\n] 2006.145.06:46:20.36#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.06:46:20.36#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.06:46:20.37#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.06:46:20.37#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.06:46:20.37$vck44/valo=6,814.99 2006.145.06:46:20.37#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.06:46:20.37#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.06:46:20.37#ibcon#ireg 17 cls_cnt 0 2006.145.06:46:20.37#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.06:46:20.37#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.06:46:20.37#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.06:46:20.38#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.06:46:20.42#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.06:46:20.42#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.06:46:20.42#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.06:46:20.42#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.06:46:20.42$vck44/va=6,4 2006.145.06:46:20.42#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.06:46:20.42#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.06:46:20.42#ibcon#ireg 11 cls_cnt 2 2006.145.06:46:20.42#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.06:46:20.48#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.06:46:20.48#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.06:46:20.50#ibcon#[25=AT06-04\r\n] 2006.145.06:46:20.53#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.06:46:20.53#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.06:46:20.53#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.06:46:20.53#ibcon#ireg 7 cls_cnt 0 2006.145.06:46:20.53#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.06:46:20.65#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.06:46:20.65#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.06:46:20.67#ibcon#[25=USB\r\n] 2006.145.06:46:20.70#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.06:46:20.70#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.06:46:20.70#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.06:46:20.70#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.06:46:20.70$vck44/valo=7,864.99 2006.145.06:46:20.70#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.06:46:20.70#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.06:46:20.70#ibcon#ireg 17 cls_cnt 0 2006.145.06:46:20.70#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.06:46:20.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.06:46:20.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.06:46:20.72#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.06:46:20.76#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.06:46:20.76#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.06:46:20.76#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.06:46:20.76#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.06:46:20.76$vck44/va=7,4 2006.145.06:46:20.76#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.06:46:20.76#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.06:46:20.76#ibcon#ireg 11 cls_cnt 2 2006.145.06:46:20.76#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.06:46:20.82#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.06:46:20.82#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.06:46:20.84#ibcon#[25=AT07-04\r\n] 2006.145.06:46:20.87#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.06:46:20.87#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.06:46:20.87#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.06:46:20.87#ibcon#ireg 7 cls_cnt 0 2006.145.06:46:20.87#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.06:46:20.99#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.06:46:20.99#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.06:46:21.01#ibcon#[25=USB\r\n] 2006.145.06:46:21.04#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.06:46:21.04#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.06:46:21.04#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.06:46:21.04#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.06:46:21.04$vck44/valo=8,884.99 2006.145.06:46:21.04#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.06:46:21.04#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.06:46:21.04#ibcon#ireg 17 cls_cnt 0 2006.145.06:46:21.04#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.06:46:21.04#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.06:46:21.04#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.06:46:21.06#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.06:46:21.10#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.06:46:21.10#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.06:46:21.10#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.06:46:21.10#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.06:46:21.10$vck44/va=8,4 2006.145.06:46:21.10#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.06:46:21.10#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.06:46:21.10#ibcon#ireg 11 cls_cnt 2 2006.145.06:46:21.10#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.06:46:21.16#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.06:46:21.16#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.06:46:21.18#ibcon#[25=AT08-04\r\n] 2006.145.06:46:21.21#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.06:46:21.21#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.06:46:21.21#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.06:46:21.21#ibcon#ireg 7 cls_cnt 0 2006.145.06:46:21.21#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.06:46:21.33#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.06:46:21.33#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.06:46:21.35#ibcon#[25=USB\r\n] 2006.145.06:46:21.38#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.06:46:21.38#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.06:46:21.38#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.06:46:21.38#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.06:46:21.38$vck44/vblo=1,629.99 2006.145.06:46:21.38#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.06:46:21.38#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.06:46:21.38#ibcon#ireg 17 cls_cnt 0 2006.145.06:46:21.38#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.06:46:21.38#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.06:46:21.38#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.06:46:21.40#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.06:46:21.44#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.06:46:21.44#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.06:46:21.44#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.06:46:21.44#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.06:46:21.44$vck44/vb=1,3 2006.145.06:46:21.44#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.06:46:21.44#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.06:46:21.44#ibcon#ireg 11 cls_cnt 2 2006.145.06:46:21.44#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.06:46:21.44#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.06:46:21.44#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.06:46:21.46#ibcon#[27=AT01-03\r\n] 2006.145.06:46:21.49#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.06:46:21.49#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.06:46:21.49#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.06:46:21.49#ibcon#ireg 7 cls_cnt 0 2006.145.06:46:21.49#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.06:46:21.61#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.06:46:21.61#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.06:46:21.63#ibcon#[27=USB\r\n] 2006.145.06:46:21.66#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.06:46:21.66#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.06:46:21.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.06:46:21.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.06:46:21.66$vck44/vblo=2,634.99 2006.145.06:46:21.66#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.06:46:21.66#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.06:46:21.66#ibcon#ireg 17 cls_cnt 0 2006.145.06:46:21.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.06:46:21.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.06:46:21.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.06:46:21.68#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.06:46:21.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.06:46:21.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.06:46:21.72#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.06:46:21.72#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.06:46:21.72$vck44/vb=2,4 2006.145.06:46:21.72#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.06:46:21.72#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.06:46:21.72#ibcon#ireg 11 cls_cnt 2 2006.145.06:46:21.72#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.06:46:21.78#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.06:46:21.78#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.06:46:21.80#ibcon#[27=AT02-04\r\n] 2006.145.06:46:21.83#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.06:46:21.83#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.06:46:21.83#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.06:46:21.83#ibcon#ireg 7 cls_cnt 0 2006.145.06:46:21.83#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.06:46:21.95#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.06:46:21.95#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.06:46:21.97#ibcon#[27=USB\r\n] 2006.145.06:46:22.00#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.06:46:22.00#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.06:46:22.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.06:46:22.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.06:46:22.00$vck44/vblo=3,649.99 2006.145.06:46:22.00#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.06:46:22.00#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.06:46:22.00#ibcon#ireg 17 cls_cnt 0 2006.145.06:46:22.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.06:46:22.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.06:46:22.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.06:46:22.02#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.06:46:22.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.06:46:22.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.06:46:22.06#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.06:46:22.06#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.06:46:22.06$vck44/vb=3,4 2006.145.06:46:22.06#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.06:46:22.06#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.06:46:22.06#ibcon#ireg 11 cls_cnt 2 2006.145.06:46:22.06#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.06:46:22.12#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.06:46:22.12#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.06:46:22.14#ibcon#[27=AT03-04\r\n] 2006.145.06:46:22.17#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.06:46:22.17#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.06:46:22.17#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.06:46:22.17#ibcon#ireg 7 cls_cnt 0 2006.145.06:46:22.17#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.06:46:22.29#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.06:46:22.29#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.06:46:22.31#ibcon#[27=USB\r\n] 2006.145.06:46:22.34#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.06:46:22.34#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.06:46:22.34#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.06:46:22.34#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.06:46:22.34$vck44/vblo=4,679.99 2006.145.06:46:22.34#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.06:46:22.34#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.06:46:22.34#ibcon#ireg 17 cls_cnt 0 2006.145.06:46:22.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.06:46:22.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.06:46:22.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.06:46:22.36#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.06:46:22.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.06:46:22.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.06:46:22.40#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.06:46:22.40#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.06:46:22.40$vck44/vb=4,4 2006.145.06:46:22.40#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.06:46:22.40#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.06:46:22.40#ibcon#ireg 11 cls_cnt 2 2006.145.06:46:22.40#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.06:46:22.46#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.06:46:22.46#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.06:46:22.48#ibcon#[27=AT04-04\r\n] 2006.145.06:46:22.51#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.06:46:22.51#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.06:46:22.51#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.06:46:22.51#ibcon#ireg 7 cls_cnt 0 2006.145.06:46:22.51#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.06:46:22.63#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.06:46:22.63#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.06:46:22.65#ibcon#[27=USB\r\n] 2006.145.06:46:22.68#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.06:46:22.68#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.06:46:22.68#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.06:46:22.68#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.06:46:22.68$vck44/vblo=5,709.99 2006.145.06:46:22.68#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.06:46:22.68#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.06:46:22.68#ibcon#ireg 17 cls_cnt 0 2006.145.06:46:22.68#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.06:46:22.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.06:46:22.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.06:46:22.70#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.06:46:22.74#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.06:46:22.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.06:46:22.74#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.06:46:22.74#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.06:46:22.74$vck44/vb=5,4 2006.145.06:46:22.74#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.06:46:22.74#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.06:46:22.74#ibcon#ireg 11 cls_cnt 2 2006.145.06:46:22.74#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.06:46:22.80#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.06:46:22.80#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.06:46:22.82#ibcon#[27=AT05-04\r\n] 2006.145.06:46:22.85#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.06:46:22.85#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.06:46:22.85#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.06:46:22.85#ibcon#ireg 7 cls_cnt 0 2006.145.06:46:22.85#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.06:46:22.97#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.06:46:22.97#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.06:46:22.99#ibcon#[27=USB\r\n] 2006.145.06:46:23.02#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.06:46:23.02#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.06:46:23.02#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.06:46:23.02#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.06:46:23.02$vck44/vblo=6,719.99 2006.145.06:46:23.02#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.06:46:23.02#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.06:46:23.02#ibcon#ireg 17 cls_cnt 0 2006.145.06:46:23.02#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.06:46:23.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.06:46:23.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.06:46:23.04#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.06:46:23.08#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.06:46:23.08#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.06:46:23.08#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.06:46:23.08#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.06:46:23.08$vck44/vb=6,4 2006.145.06:46:23.08#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.06:46:23.08#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.06:46:23.08#ibcon#ireg 11 cls_cnt 2 2006.145.06:46:23.08#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.06:46:23.14#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.06:46:23.14#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.06:46:23.16#ibcon#[27=AT06-04\r\n] 2006.145.06:46:23.19#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.06:46:23.19#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.06:46:23.19#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.06:46:23.19#ibcon#ireg 7 cls_cnt 0 2006.145.06:46:23.19#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.06:46:23.31#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.06:46:23.31#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.06:46:23.33#ibcon#[27=USB\r\n] 2006.145.06:46:23.36#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.06:46:23.36#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.06:46:23.36#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.06:46:23.36#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.06:46:23.36$vck44/vblo=7,734.99 2006.145.06:46:23.36#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.06:46:23.36#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.06:46:23.36#ibcon#ireg 17 cls_cnt 0 2006.145.06:46:23.36#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.06:46:23.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.06:46:23.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.06:46:23.38#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.06:46:23.42#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.06:46:23.42#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.06:46:23.42#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.06:46:23.42#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.06:46:23.42$vck44/vb=7,4 2006.145.06:46:23.42#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.06:46:23.42#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.06:46:23.42#ibcon#ireg 11 cls_cnt 2 2006.145.06:46:23.42#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.06:46:23.48#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.06:46:23.48#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.06:46:23.50#ibcon#[27=AT07-04\r\n] 2006.145.06:46:23.53#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.06:46:23.53#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.06:46:23.53#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.06:46:23.53#ibcon#ireg 7 cls_cnt 0 2006.145.06:46:23.53#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.06:46:23.65#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.06:46:23.65#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.06:46:23.67#ibcon#[27=USB\r\n] 2006.145.06:46:23.70#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.06:46:23.70#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.06:46:23.70#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.06:46:23.70#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.06:46:23.70$vck44/vblo=8,744.99 2006.145.06:46:23.70#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.06:46:23.70#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.06:46:23.70#ibcon#ireg 17 cls_cnt 0 2006.145.06:46:23.70#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.06:46:23.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.06:46:23.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.06:46:23.72#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.06:46:23.76#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.06:46:23.76#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.06:46:23.76#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.06:46:23.76#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.06:46:23.76$vck44/vb=8,4 2006.145.06:46:23.76#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.06:46:23.76#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.06:46:23.76#ibcon#ireg 11 cls_cnt 2 2006.145.06:46:23.76#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.06:46:23.82#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.06:46:23.82#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.06:46:23.84#ibcon#[27=AT08-04\r\n] 2006.145.06:46:23.87#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.06:46:23.87#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.06:46:23.87#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.06:46:23.87#ibcon#ireg 7 cls_cnt 0 2006.145.06:46:23.87#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.06:46:23.99#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.06:46:23.99#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.06:46:24.01#ibcon#[27=USB\r\n] 2006.145.06:46:24.04#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.06:46:24.04#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.06:46:24.04#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.06:46:24.04#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.06:46:24.04$vck44/vabw=wide 2006.145.06:46:24.04#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.06:46:24.04#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.06:46:24.04#ibcon#ireg 8 cls_cnt 0 2006.145.06:46:24.04#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.06:46:24.04#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.06:46:24.04#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.06:46:24.06#ibcon#[25=BW32\r\n] 2006.145.06:46:24.09#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.06:46:24.09#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.06:46:24.09#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.06:46:24.09#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.06:46:24.09$vck44/vbbw=wide 2006.145.06:46:24.09#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.06:46:24.09#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.06:46:24.09#ibcon#ireg 8 cls_cnt 0 2006.145.06:46:24.09#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.06:46:24.16#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.06:46:24.16#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.06:46:24.18#ibcon#[27=BW32\r\n] 2006.145.06:46:24.21#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.06:46:24.21#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.06:46:24.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.06:46:24.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.06:46:24.21$setupk4/ifdk4 2006.145.06:46:24.21$ifdk4/lo= 2006.145.06:46:24.21$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.06:46:24.21$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.06:46:24.21$ifdk4/patch= 2006.145.06:46:24.21$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.06:46:24.21$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.06:46:24.21$setupk4/!*+20s 2006.145.06:46:24.24#abcon#<5=/05 5.0 7.7 19.96 621016.6\r\n> 2006.145.06:46:24.26#abcon#{5=INTERFACE CLEAR} 2006.145.06:46:24.32#abcon#[5=S1D000X0/0*\r\n] 2006.145.06:46:34.41#abcon#<5=/05 5.0 7.7 19.96 621016.6\r\n> 2006.145.06:46:34.43#abcon#{5=INTERFACE CLEAR} 2006.145.06:46:34.49#abcon#[5=S1D000X0/0*\r\n] 2006.145.06:46:38.65$setupk4/"tpicd 2006.145.06:46:38.65$setupk4/echo=off 2006.145.06:46:38.65$setupk4/xlog=off 2006.145.06:46:38.65:!2006.145.06:49:14 2006.145.06:46:42.14#trakl#Source acquired 2006.145.06:46:43.14#flagr#flagr/antenna,acquired 2006.145.06:49:14.00:preob 2006.145.06:49:14.14/onsource/TRACKING 2006.145.06:49:14.14:!2006.145.06:49:24 2006.145.06:49:24.00:"tape 2006.145.06:49:24.00:"st=record 2006.145.06:49:24.00:data_valid=on 2006.145.06:49:24.00:midob 2006.145.06:49:25.14/onsource/TRACKING 2006.145.06:49:25.14/wx/19.91,1016.6,62 2006.145.06:49:25.25/cable/+6.5393E-03 2006.145.06:49:26.34/va/01,08,usb,yes,30,32 2006.145.06:49:26.34/va/02,07,usb,yes,32,33 2006.145.06:49:26.34/va/03,08,usb,yes,29,30 2006.145.06:49:26.34/va/04,07,usb,yes,33,35 2006.145.06:49:26.34/va/05,04,usb,yes,29,30 2006.145.06:49:26.34/va/06,04,usb,yes,33,32 2006.145.06:49:26.34/va/07,04,usb,yes,33,34 2006.145.06:49:26.34/va/08,04,usb,yes,28,34 2006.145.06:49:26.57/valo/01,524.99,yes,locked 2006.145.06:49:26.57/valo/02,534.99,yes,locked 2006.145.06:49:26.57/valo/03,564.99,yes,locked 2006.145.06:49:26.57/valo/04,624.99,yes,locked 2006.145.06:49:26.57/valo/05,734.99,yes,locked 2006.145.06:49:26.57/valo/06,814.99,yes,locked 2006.145.06:49:26.57/valo/07,864.99,yes,locked 2006.145.06:49:26.57/valo/08,884.99,yes,locked 2006.145.06:49:27.66/vb/01,03,usb,yes,37,35 2006.145.06:49:27.66/vb/02,04,usb,yes,33,32 2006.145.06:49:27.66/vb/03,04,usb,yes,29,32 2006.145.06:49:27.66/vb/04,04,usb,yes,34,33 2006.145.06:49:27.66/vb/05,04,usb,yes,26,29 2006.145.06:49:27.66/vb/06,04,usb,yes,31,27 2006.145.06:49:27.66/vb/07,04,usb,yes,30,30 2006.145.06:49:27.66/vb/08,04,usb,yes,28,31 2006.145.06:49:27.89/vblo/01,629.99,yes,locked 2006.145.06:49:27.89/vblo/02,634.99,yes,locked 2006.145.06:49:27.89/vblo/03,649.99,yes,locked 2006.145.06:49:27.89/vblo/04,679.99,yes,locked 2006.145.06:49:27.89/vblo/05,709.99,yes,locked 2006.145.06:49:27.89/vblo/06,719.99,yes,locked 2006.145.06:49:27.89/vblo/07,734.99,yes,locked 2006.145.06:49:27.89/vblo/08,744.99,yes,locked 2006.145.06:49:28.04/vabw/8 2006.145.06:49:28.19/vbbw/8 2006.145.06:49:28.28/xfe/off,on,14.5 2006.145.06:49:28.65/ifatt/23,28,28,28 2006.145.06:49:29.07/fmout-gps/S +5.3E-08 2006.145.06:49:29.11:!2006.145.07:02:28 2006.145.07:02:28.00:data_valid=off 2006.145.07:02:28.01:"et 2006.145.07:02:28.01:!+3s 2006.145.07:02:31.04:"tape 2006.145.07:02:31.05:postob 2006.145.07:02:31.24/cable/+6.5394E-03 2006.145.07:02:31.25/wx/19.68,1016.9,64 2006.145.07:02:31.33/fmout-gps/S +5.5E-08 2006.145.07:02:31.34:scan_name=145-0708,jd0605,90 2006.145.07:02:31.34:source=3c274,123049.42,122328.0,2000.0,cw 2006.145.07:02:33.14#flagr#flagr/antenna,new-source 2006.145.07:02:33.15:checkk5 2006.145.07:02:33.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.07:02:34.04/chk_autoobs//k5ts2/ autoobs is running! 2006.145.07:02:34.48/chk_autoobs//k5ts3/ autoobs is running! 2006.145.07:02:34.91/chk_autoobs//k5ts4/ autoobs is running! 2006.145.07:02:35.63/chk_obsdata//k5ts1/T1450649??a.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.07:02:36.37/chk_obsdata//k5ts2/T1450649??b.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.07:02:37.10/chk_obsdata//k5ts3/T1450649??c.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.07:02:37.84/chk_obsdata//k5ts4/T1450649??d.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.07:02:38.62/k5log//k5ts1_log_newline 2006.145.07:02:39.35/k5log//k5ts2_log_newline 2006.145.07:02:40.09/k5log//k5ts3_log_newline 2006.145.07:02:40.85/k5log//k5ts4_log_newline 2006.145.07:02:40.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.07:02:40.88:setupk4=1 2006.145.07:02:40.88$setupk4/echo=on 2006.145.07:02:40.88$setupk4/pcalon 2006.145.07:02:40.88$pcalon/"no phase cal control is implemented here 2006.145.07:02:40.88$setupk4/"tpicd=stop 2006.145.07:02:40.88$setupk4/"rec=synch_on 2006.145.07:02:40.88$setupk4/"rec_mode=128 2006.145.07:02:40.88$setupk4/!* 2006.145.07:02:40.88$setupk4/recpk4 2006.145.07:02:40.88$recpk4/recpatch= 2006.145.07:02:40.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.07:02:40.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.07:02:40.88$setupk4/vck44 2006.145.07:02:40.88$vck44/valo=1,524.99 2006.145.07:02:40.88#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.07:02:40.88#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.07:02:40.88#ibcon#ireg 17 cls_cnt 0 2006.145.07:02:40.88#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.07:02:40.88#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.07:02:40.88#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.07:02:40.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.07:02:40.96#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.07:02:40.96#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.07:02:40.96#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.07:02:40.96#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.07:02:40.96$vck44/va=1,8 2006.145.07:02:40.96#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.07:02:40.96#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.07:02:40.96#ibcon#ireg 11 cls_cnt 2 2006.145.07:02:40.96#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.07:02:40.96#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.07:02:40.96#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.07:02:40.98#ibcon#[25=AT01-08\r\n] 2006.145.07:02:41.01#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.07:02:41.01#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.07:02:41.01#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.07:02:41.01#ibcon#ireg 7 cls_cnt 0 2006.145.07:02:41.01#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.07:02:41.14#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.07:02:41.14#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.07:02:41.15#ibcon#[25=USB\r\n] 2006.145.07:02:41.18#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.07:02:41.18#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.07:02:41.18#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.07:02:41.18#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.07:02:41.18$vck44/valo=2,534.99 2006.145.07:02:41.18#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.07:02:41.18#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.07:02:41.18#ibcon#ireg 17 cls_cnt 0 2006.145.07:02:41.18#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.07:02:41.18#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.07:02:41.18#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.07:02:41.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.07:02:41.25#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.07:02:41.25#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.07:02:41.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.07:02:41.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.07:02:41.25$vck44/va=2,7 2006.145.07:02:41.25#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.07:02:41.25#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.07:02:41.25#ibcon#ireg 11 cls_cnt 2 2006.145.07:02:41.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.07:02:41.30#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.07:02:41.30#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.07:02:41.32#ibcon#[25=AT02-07\r\n] 2006.145.07:02:41.35#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.07:02:41.35#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.07:02:41.35#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.07:02:41.35#ibcon#ireg 7 cls_cnt 0 2006.145.07:02:41.35#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.07:02:41.47#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.07:02:41.47#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.07:02:41.49#ibcon#[25=USB\r\n] 2006.145.07:02:41.52#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.07:02:41.52#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.07:02:41.52#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.07:02:41.52#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.07:02:41.52$vck44/valo=3,564.99 2006.145.07:02:41.52#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.07:02:41.52#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.07:02:41.52#ibcon#ireg 17 cls_cnt 0 2006.145.07:02:41.52#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.07:02:41.52#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.07:02:41.52#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.07:02:41.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.07:02:41.58#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.07:02:41.58#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.07:02:41.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.07:02:41.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.07:02:41.58$vck44/va=3,8 2006.145.07:02:41.58#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.07:02:41.58#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.07:02:41.58#ibcon#ireg 11 cls_cnt 2 2006.145.07:02:41.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.07:02:41.64#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.07:02:41.64#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.07:02:41.66#ibcon#[25=AT03-08\r\n] 2006.145.07:02:41.69#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.07:02:41.69#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.07:02:41.69#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.07:02:41.69#ibcon#ireg 7 cls_cnt 0 2006.145.07:02:41.69#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.07:02:41.81#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.07:02:41.81#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.07:02:41.83#ibcon#[25=USB\r\n] 2006.145.07:02:41.86#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.07:02:41.86#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.07:02:41.86#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.07:02:41.86#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.07:02:41.86$vck44/valo=4,624.99 2006.145.07:02:41.86#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.07:02:41.86#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.07:02:41.86#ibcon#ireg 17 cls_cnt 0 2006.145.07:02:41.86#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.07:02:41.86#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.07:02:41.86#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.07:02:41.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.07:02:41.92#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.07:02:41.92#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.07:02:41.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.07:02:41.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.07:02:41.92$vck44/va=4,7 2006.145.07:02:41.92#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.07:02:41.92#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.07:02:41.92#ibcon#ireg 11 cls_cnt 2 2006.145.07:02:41.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.07:02:41.98#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.07:02:41.98#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.07:02:42.00#ibcon#[25=AT04-07\r\n] 2006.145.07:02:42.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.07:02:42.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.07:02:42.03#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.07:02:42.03#ibcon#ireg 7 cls_cnt 0 2006.145.07:02:42.03#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.07:02:42.15#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.07:02:42.15#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.07:02:42.17#ibcon#[25=USB\r\n] 2006.145.07:02:42.20#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.07:02:42.20#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.07:02:42.20#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.07:02:42.20#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.07:02:42.20$vck44/valo=5,734.99 2006.145.07:02:42.20#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.07:02:42.20#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.07:02:42.20#ibcon#ireg 17 cls_cnt 0 2006.145.07:02:42.20#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.07:02:42.20#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.07:02:42.20#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.07:02:42.22#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.07:02:42.26#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.07:02:42.26#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.07:02:42.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.07:02:42.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.07:02:42.27$vck44/va=5,4 2006.145.07:02:42.27#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.07:02:42.27#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.07:02:42.27#ibcon#ireg 11 cls_cnt 2 2006.145.07:02:42.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.07:02:42.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.07:02:42.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.07:02:42.34#ibcon#[25=AT05-04\r\n] 2006.145.07:02:42.37#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.07:02:42.37#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.07:02:42.37#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.07:02:42.37#ibcon#ireg 7 cls_cnt 0 2006.145.07:02:42.37#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.07:02:42.49#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.07:02:42.49#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.07:02:42.51#ibcon#[25=USB\r\n] 2006.145.07:02:42.54#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.07:02:42.54#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.07:02:42.54#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.07:02:42.54#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.07:02:42.54$vck44/valo=6,814.99 2006.145.07:02:42.54#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.07:02:42.54#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.07:02:42.54#ibcon#ireg 17 cls_cnt 0 2006.145.07:02:42.54#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:02:42.54#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:02:42.54#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:02:42.56#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.07:02:42.60#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:02:42.60#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:02:42.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.07:02:42.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.07:02:42.60$vck44/va=6,4 2006.145.07:02:42.60#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.07:02:42.60#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.07:02:42.60#ibcon#ireg 11 cls_cnt 2 2006.145.07:02:42.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.07:02:42.66#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.07:02:42.66#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.07:02:42.68#ibcon#[25=AT06-04\r\n] 2006.145.07:02:42.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.07:02:42.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.07:02:42.71#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.07:02:42.71#ibcon#ireg 7 cls_cnt 0 2006.145.07:02:42.71#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.07:02:42.83#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.07:02:42.83#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.07:02:42.85#ibcon#[25=USB\r\n] 2006.145.07:02:42.88#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.07:02:42.88#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.07:02:42.88#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.07:02:42.88#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.07:02:42.88$vck44/valo=7,864.99 2006.145.07:02:42.88#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.07:02:42.88#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.07:02:42.88#ibcon#ireg 17 cls_cnt 0 2006.145.07:02:42.88#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.07:02:42.88#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.07:02:42.88#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.07:02:42.90#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.07:02:42.94#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.07:02:42.94#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.07:02:42.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.07:02:42.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.07:02:42.94$vck44/va=7,4 2006.145.07:02:42.94#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.07:02:42.94#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.07:02:42.94#ibcon#ireg 11 cls_cnt 2 2006.145.07:02:42.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.07:02:43.00#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.07:02:43.00#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.07:02:43.02#ibcon#[25=AT07-04\r\n] 2006.145.07:02:43.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.07:02:43.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.07:02:43.05#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.07:02:43.05#ibcon#ireg 7 cls_cnt 0 2006.145.07:02:43.05#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.07:02:43.17#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.07:02:43.17#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.07:02:43.19#ibcon#[25=USB\r\n] 2006.145.07:02:43.22#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.07:02:43.22#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.07:02:43.22#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.07:02:43.22#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.07:02:43.22$vck44/valo=8,884.99 2006.145.07:02:43.22#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.07:02:43.22#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.07:02:43.22#ibcon#ireg 17 cls_cnt 0 2006.145.07:02:43.22#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.07:02:43.22#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.07:02:43.22#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.07:02:43.24#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.07:02:43.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.07:02:43.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.07:02:43.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.07:02:43.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.07:02:43.28$vck44/va=8,4 2006.145.07:02:43.28#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.07:02:43.28#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.07:02:43.28#ibcon#ireg 11 cls_cnt 2 2006.145.07:02:43.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.07:02:43.34#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.07:02:43.34#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.07:02:43.36#ibcon#[25=AT08-04\r\n] 2006.145.07:02:43.39#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.07:02:43.39#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.07:02:43.39#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.07:02:43.39#ibcon#ireg 7 cls_cnt 0 2006.145.07:02:43.39#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.07:02:43.51#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.07:02:43.51#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.07:02:43.53#ibcon#[25=USB\r\n] 2006.145.07:02:43.56#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.07:02:43.56#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.07:02:43.56#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.07:02:43.56#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.07:02:43.56$vck44/vblo=1,629.99 2006.145.07:02:43.56#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.07:02:43.56#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.07:02:43.56#ibcon#ireg 17 cls_cnt 0 2006.145.07:02:43.56#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.07:02:43.56#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.07:02:43.56#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.07:02:43.58#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.07:02:43.62#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.07:02:43.62#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.07:02:43.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.07:02:43.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.07:02:43.62$vck44/vb=1,3 2006.145.07:02:43.62#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.07:02:43.62#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.07:02:43.62#ibcon#ireg 11 cls_cnt 2 2006.145.07:02:43.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.07:02:43.62#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.07:02:43.62#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.07:02:43.64#ibcon#[27=AT01-03\r\n] 2006.145.07:02:43.67#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.07:02:43.67#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.07:02:43.67#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.07:02:43.67#ibcon#ireg 7 cls_cnt 0 2006.145.07:02:43.67#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.07:02:43.73#abcon#<5=/05 5.1 8.2 19.67 641016.9\r\n> 2006.145.07:02:43.75#abcon#{5=INTERFACE CLEAR} 2006.145.07:02:43.79#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.07:02:43.79#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.07:02:43.81#ibcon#[27=USB\r\n] 2006.145.07:02:43.81#abcon#[5=S1D000X0/0*\r\n] 2006.145.07:02:43.84#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.07:02:43.84#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.07:02:43.84#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.07:02:43.84#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.07:02:43.84$vck44/vblo=2,634.99 2006.145.07:02:43.84#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.07:02:43.84#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.07:02:43.84#ibcon#ireg 17 cls_cnt 0 2006.145.07:02:43.84#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.07:02:43.84#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.07:02:43.84#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.07:02:43.86#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.07:02:43.90#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.07:02:43.90#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.07:02:43.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.07:02:43.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.07:02:43.90$vck44/vb=2,4 2006.145.07:02:43.90#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.07:02:43.90#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.07:02:43.90#ibcon#ireg 11 cls_cnt 2 2006.145.07:02:43.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.07:02:43.96#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.07:02:43.96#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.07:02:43.98#ibcon#[27=AT02-04\r\n] 2006.145.07:02:44.01#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.07:02:44.01#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.07:02:44.01#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.07:02:44.01#ibcon#ireg 7 cls_cnt 0 2006.145.07:02:44.01#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.07:02:44.13#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.07:02:44.13#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.07:02:44.15#ibcon#[27=USB\r\n] 2006.145.07:02:44.18#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.07:02:44.18#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.07:02:44.18#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.07:02:44.18#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.07:02:44.18$vck44/vblo=3,649.99 2006.145.07:02:44.18#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.07:02:44.18#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.07:02:44.18#ibcon#ireg 17 cls_cnt 0 2006.145.07:02:44.18#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.07:02:44.18#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.07:02:44.18#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.07:02:44.20#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.07:02:44.24#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.07:02:44.24#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.07:02:44.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.07:02:44.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.07:02:44.24$vck44/vb=3,4 2006.145.07:02:44.24#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.07:02:44.24#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.07:02:44.24#ibcon#ireg 11 cls_cnt 2 2006.145.07:02:44.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.07:02:44.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.07:02:44.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.07:02:44.32#ibcon#[27=AT03-04\r\n] 2006.145.07:02:44.35#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.07:02:44.35#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.07:02:44.35#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.07:02:44.35#ibcon#ireg 7 cls_cnt 0 2006.145.07:02:44.35#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.07:02:44.47#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.07:02:44.47#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.07:02:44.49#ibcon#[27=USB\r\n] 2006.145.07:02:44.52#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.07:02:44.52#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.07:02:44.52#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.07:02:44.52#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.07:02:44.52$vck44/vblo=4,679.99 2006.145.07:02:44.52#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.07:02:44.52#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.07:02:44.52#ibcon#ireg 17 cls_cnt 0 2006.145.07:02:44.52#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.07:02:44.52#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.07:02:44.52#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.07:02:44.54#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.07:02:44.58#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.07:02:44.58#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.07:02:44.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.07:02:44.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.07:02:44.58$vck44/vb=4,4 2006.145.07:02:44.58#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.07:02:44.58#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.07:02:44.58#ibcon#ireg 11 cls_cnt 2 2006.145.07:02:44.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.07:02:44.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.07:02:44.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.07:02:44.66#ibcon#[27=AT04-04\r\n] 2006.145.07:02:44.69#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.07:02:44.69#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.07:02:44.69#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.07:02:44.69#ibcon#ireg 7 cls_cnt 0 2006.145.07:02:44.69#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.07:02:44.81#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.07:02:44.81#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.07:02:44.83#ibcon#[27=USB\r\n] 2006.145.07:02:44.86#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.07:02:44.86#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.07:02:44.86#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.07:02:44.86#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.07:02:44.86$vck44/vblo=5,709.99 2006.145.07:02:44.86#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.07:02:44.86#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.07:02:44.86#ibcon#ireg 17 cls_cnt 0 2006.145.07:02:44.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.07:02:44.86#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.07:02:44.86#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.07:02:44.88#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.07:02:44.92#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.07:02:44.92#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.07:02:44.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.07:02:44.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.07:02:44.92$vck44/vb=5,4 2006.145.07:02:44.92#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.07:02:44.92#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.07:02:44.92#ibcon#ireg 11 cls_cnt 2 2006.145.07:02:44.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.07:02:44.98#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.07:02:44.98#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.07:02:45.00#ibcon#[27=AT05-04\r\n] 2006.145.07:02:45.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.07:02:45.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.07:02:45.03#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.07:02:45.03#ibcon#ireg 7 cls_cnt 0 2006.145.07:02:45.03#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.07:02:45.15#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.07:02:45.15#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.07:02:45.17#ibcon#[27=USB\r\n] 2006.145.07:02:45.20#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.07:02:45.20#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.07:02:45.20#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.07:02:45.20#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.07:02:45.20$vck44/vblo=6,719.99 2006.145.07:02:45.20#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.07:02:45.20#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.07:02:45.20#ibcon#ireg 17 cls_cnt 0 2006.145.07:02:45.20#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:02:45.20#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:02:45.20#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:02:45.22#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.07:02:45.26#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:02:45.26#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:02:45.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.07:02:45.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.07:02:45.26$vck44/vb=6,4 2006.145.07:02:45.26#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.07:02:45.26#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.07:02:45.26#ibcon#ireg 11 cls_cnt 2 2006.145.07:02:45.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.07:02:45.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.07:02:45.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.07:02:45.34#ibcon#[27=AT06-04\r\n] 2006.145.07:02:45.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.07:02:45.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.07:02:45.37#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.07:02:45.37#ibcon#ireg 7 cls_cnt 0 2006.145.07:02:45.37#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.07:02:45.49#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.07:02:45.49#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.07:02:45.51#ibcon#[27=USB\r\n] 2006.145.07:02:45.54#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.07:02:45.54#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.07:02:45.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.07:02:45.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.07:02:45.54$vck44/vblo=7,734.99 2006.145.07:02:45.54#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.07:02:45.54#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.07:02:45.54#ibcon#ireg 17 cls_cnt 0 2006.145.07:02:45.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.07:02:45.54#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.07:02:45.54#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.07:02:45.56#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.07:02:45.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.07:02:45.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.07:02:45.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.07:02:45.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.07:02:45.60$vck44/vb=7,4 2006.145.07:02:45.60#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.07:02:45.60#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.07:02:45.60#ibcon#ireg 11 cls_cnt 2 2006.145.07:02:45.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.07:02:45.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.07:02:45.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.07:02:45.68#ibcon#[27=AT07-04\r\n] 2006.145.07:02:45.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.07:02:45.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.07:02:45.71#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.07:02:45.71#ibcon#ireg 7 cls_cnt 0 2006.145.07:02:45.71#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.07:02:45.83#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.07:02:45.83#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.07:02:45.85#ibcon#[27=USB\r\n] 2006.145.07:02:45.88#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.07:02:45.88#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.07:02:45.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.07:02:45.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.07:02:45.88$vck44/vblo=8,744.99 2006.145.07:02:45.88#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.07:02:45.88#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.07:02:45.88#ibcon#ireg 17 cls_cnt 0 2006.145.07:02:45.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.07:02:45.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.07:02:45.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.07:02:45.90#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.07:02:45.94#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.07:02:45.94#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.07:02:45.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.07:02:45.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.07:02:45.94$vck44/vb=8,4 2006.145.07:02:45.94#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.07:02:45.94#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.07:02:45.94#ibcon#ireg 11 cls_cnt 2 2006.145.07:02:45.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.07:02:46.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.07:02:46.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.07:02:46.02#ibcon#[27=AT08-04\r\n] 2006.145.07:02:46.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.07:02:46.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.07:02:46.05#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.07:02:46.05#ibcon#ireg 7 cls_cnt 0 2006.145.07:02:46.05#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.07:02:46.17#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.07:02:46.17#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.07:02:46.19#ibcon#[27=USB\r\n] 2006.145.07:02:46.22#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.07:02:46.22#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.07:02:46.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.07:02:46.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.07:02:46.22$vck44/vabw=wide 2006.145.07:02:46.22#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.07:02:46.22#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.07:02:46.22#ibcon#ireg 8 cls_cnt 0 2006.145.07:02:46.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.07:02:46.22#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.07:02:46.22#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.07:02:46.26#ibcon#[25=BW32\r\n] 2006.145.07:02:46.28#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.07:02:46.28#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.07:02:46.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.07:02:46.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.07:02:46.28$vck44/vbbw=wide 2006.145.07:02:46.28#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.07:02:46.28#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.07:02:46.28#ibcon#ireg 8 cls_cnt 0 2006.145.07:02:46.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:02:46.34#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:02:46.34#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:02:46.36#ibcon#[27=BW32\r\n] 2006.145.07:02:46.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:02:46.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:02:46.39#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.07:02:46.39#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.07:02:46.39$setupk4/ifdk4 2006.145.07:02:46.39$ifdk4/lo= 2006.145.07:02:46.39$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.07:02:46.39$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.07:02:46.39$ifdk4/patch= 2006.145.07:02:46.39$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.07:02:46.39$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.07:02:46.39$setupk4/!*+20s 2006.145.07:02:53.90#abcon#<5=/05 5.0 8.2 19.67 631016.9\r\n> 2006.145.07:02:53.92#abcon#{5=INTERFACE CLEAR} 2006.145.07:02:53.98#abcon#[5=S1D000X0/0*\r\n] 2006.145.07:03:00.89$setupk4/"tpicd 2006.145.07:03:00.89$setupk4/echo=off 2006.145.07:03:00.89$setupk4/xlog=off 2006.145.07:03:00.89:!2006.145.07:08:35 2006.145.07:03:26.14#trakl#Source acquired 2006.145.07:03:28.14#flagr#flagr/antenna,acquired 2006.145.07:08:35.00:preob 2006.145.07:08:35.13/onsource/TRACKING 2006.145.07:08:35.13:!2006.145.07:08:45 2006.145.07:08:45.00:"tape 2006.145.07:08:45.00:"st=record 2006.145.07:08:45.00:data_valid=on 2006.145.07:08:45.00:midob 2006.145.07:08:46.13/onsource/TRACKING 2006.145.07:08:46.13/wx/19.57,1017.0,64 2006.145.07:08:46.29/cable/+6.5382E-03 2006.145.07:08:47.38/va/01,08,usb,yes,31,34 2006.145.07:08:47.38/va/02,07,usb,yes,34,34 2006.145.07:08:47.38/va/03,08,usb,yes,31,32 2006.145.07:08:47.38/va/04,07,usb,yes,35,37 2006.145.07:08:47.38/va/05,04,usb,yes,30,31 2006.145.07:08:47.38/va/06,04,usb,yes,34,34 2006.145.07:08:47.38/va/07,04,usb,yes,34,35 2006.145.07:08:47.38/va/08,04,usb,yes,29,35 2006.145.07:08:47.61/valo/01,524.99,yes,locked 2006.145.07:08:47.61/valo/02,534.99,yes,locked 2006.145.07:08:47.61/valo/03,564.99,yes,locked 2006.145.07:08:47.61/valo/04,624.99,yes,locked 2006.145.07:08:47.61/valo/05,734.99,yes,locked 2006.145.07:08:47.61/valo/06,814.99,yes,locked 2006.145.07:08:47.61/valo/07,864.99,yes,locked 2006.145.07:08:47.61/valo/08,884.99,yes,locked 2006.145.07:08:48.70/vb/01,03,usb,yes,45,41 2006.145.07:08:48.70/vb/02,04,usb,yes,39,39 2006.145.07:08:48.70/vb/03,04,usb,yes,35,39 2006.145.07:08:48.70/vb/04,04,usb,yes,40,39 2006.145.07:08:48.70/vb/05,04,usb,yes,32,35 2006.145.07:08:48.70/vb/06,04,usb,yes,37,33 2006.145.07:08:48.70/vb/07,04,usb,yes,36,36 2006.145.07:08:48.70/vb/08,04,usb,yes,33,37 2006.145.07:08:48.93/vblo/01,629.99,yes,locked 2006.145.07:08:48.93/vblo/02,634.99,yes,locked 2006.145.07:08:48.93/vblo/03,649.99,yes,locked 2006.145.07:08:48.93/vblo/04,679.99,yes,locked 2006.145.07:08:48.93/vblo/05,709.99,yes,locked 2006.145.07:08:48.93/vblo/06,719.99,yes,locked 2006.145.07:08:48.93/vblo/07,734.99,yes,locked 2006.145.07:08:48.93/vblo/08,744.99,yes,locked 2006.145.07:08:49.08/vabw/8 2006.145.07:08:49.23/vbbw/8 2006.145.07:08:49.32/xfe/off,on,15.2 2006.145.07:08:49.71/ifatt/23,28,28,28 2006.145.07:08:50.07/fmout-gps/S +5.5E-08 2006.145.07:08:50.11:!2006.145.07:10:15 2006.145.07:10:15.01:data_valid=off 2006.145.07:10:15.02:"et 2006.145.07:10:15.02:!+3s 2006.145.07:10:18.03:"tape 2006.145.07:10:18.04:postob 2006.145.07:10:18.16/cable/+6.5381E-03 2006.145.07:10:18.17/wx/19.53,1017.0,62 2006.145.07:10:18.23/fmout-gps/S +5.4E-08 2006.145.07:10:18.23:scan_name=145-0715,jd0605,60 2006.145.07:10:18.23:source=0727-115,073019.11,-114112.6,2000.0,cw 2006.145.07:10:19.14#flagr#flagr/antenna,new-source 2006.145.07:10:19.15:checkk5 2006.145.07:10:19.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.07:10:20.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.07:10:20.49/chk_autoobs//k5ts3/ autoobs is running! 2006.145.07:10:20.91/chk_autoobs//k5ts4/ autoobs is running! 2006.145.07:10:21.34/chk_obsdata//k5ts1/T1450708??a.dat file size is correct (nominal:360MB, actual:360MB). 2006.145.07:10:21.79/chk_obsdata//k5ts2/T1450708??b.dat file size is correct (nominal:360MB, actual:360MB). 2006.145.07:10:22.22/chk_obsdata//k5ts3/T1450708??c.dat file size is correct (nominal:360MB, actual:360MB). 2006.145.07:10:22.67/chk_obsdata//k5ts4/T1450708??d.dat file size is correct (nominal:360MB, actual:360MB). 2006.145.07:10:23.41/k5log//k5ts1_log_newline 2006.145.07:10:24.15/k5log//k5ts2_log_newline 2006.145.07:10:24.90/k5log//k5ts3_log_newline 2006.145.07:10:25.64/k5log//k5ts4_log_newline 2006.145.07:10:25.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.07:10:25.67:setupk4=1 2006.145.07:10:25.67$setupk4/echo=on 2006.145.07:10:25.67$setupk4/pcalon 2006.145.07:10:25.67$pcalon/"no phase cal control is implemented here 2006.145.07:10:25.67$setupk4/"tpicd=stop 2006.145.07:10:25.67$setupk4/"rec=synch_on 2006.145.07:10:25.67$setupk4/"rec_mode=128 2006.145.07:10:25.67$setupk4/!* 2006.145.07:10:25.67$setupk4/recpk4 2006.145.07:10:25.67$recpk4/recpatch= 2006.145.07:10:25.67$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.07:10:25.67$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.07:10:25.67$setupk4/vck44 2006.145.07:10:25.67$vck44/valo=1,524.99 2006.145.07:10:25.67#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.07:10:25.67#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.07:10:25.67#ibcon#ireg 17 cls_cnt 0 2006.145.07:10:25.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:10:25.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:10:25.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:10:25.71#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.07:10:25.76#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:10:25.76#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:10:25.76#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.07:10:25.76#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.07:10:25.76$vck44/va=1,8 2006.145.07:10:25.76#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.07:10:25.76#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.07:10:25.76#ibcon#ireg 11 cls_cnt 2 2006.145.07:10:25.76#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:10:25.76#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:10:25.76#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:10:25.78#ibcon#[25=AT01-08\r\n] 2006.145.07:10:25.81#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:10:25.81#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:10:25.81#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.07:10:25.81#ibcon#ireg 7 cls_cnt 0 2006.145.07:10:25.81#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:10:25.93#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:10:25.93#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:10:25.95#ibcon#[25=USB\r\n] 2006.145.07:10:25.98#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:10:25.98#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:10:25.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.07:10:25.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.07:10:25.98$vck44/valo=2,534.99 2006.145.07:10:25.98#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.07:10:25.98#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.07:10:25.98#ibcon#ireg 17 cls_cnt 0 2006.145.07:10:25.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:10:25.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:10:25.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:10:26.01#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.07:10:26.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:10:26.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:10:26.05#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.07:10:26.05#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.07:10:26.05$vck44/va=2,7 2006.145.07:10:26.05#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.07:10:26.05#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.07:10:26.05#ibcon#ireg 11 cls_cnt 2 2006.145.07:10:26.05#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:10:26.10#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:10:26.10#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:10:26.12#ibcon#[25=AT02-07\r\n] 2006.145.07:10:26.15#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:10:26.15#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:10:26.15#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.07:10:26.15#ibcon#ireg 7 cls_cnt 0 2006.145.07:10:26.15#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:10:26.27#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:10:26.27#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:10:26.29#ibcon#[25=USB\r\n] 2006.145.07:10:26.32#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:10:26.32#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:10:26.32#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.07:10:26.32#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.07:10:26.32$vck44/valo=3,564.99 2006.145.07:10:26.32#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.07:10:26.32#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.07:10:26.32#ibcon#ireg 17 cls_cnt 0 2006.145.07:10:26.32#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:10:26.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:10:26.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:10:26.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.07:10:26.38#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:10:26.38#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:10:26.38#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.07:10:26.38#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.07:10:26.38$vck44/va=3,8 2006.145.07:10:26.38#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.07:10:26.38#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.07:10:26.38#ibcon#ireg 11 cls_cnt 2 2006.145.07:10:26.38#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:10:26.44#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:10:26.44#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:10:26.46#ibcon#[25=AT03-08\r\n] 2006.145.07:10:26.49#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:10:26.49#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:10:26.49#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.07:10:26.49#ibcon#ireg 7 cls_cnt 0 2006.145.07:10:26.49#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:10:26.61#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:10:26.61#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:10:26.63#ibcon#[25=USB\r\n] 2006.145.07:10:26.66#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:10:26.66#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:10:26.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.07:10:26.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.07:10:26.66$vck44/valo=4,624.99 2006.145.07:10:26.66#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.07:10:26.66#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.07:10:26.66#ibcon#ireg 17 cls_cnt 0 2006.145.07:10:26.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:10:26.66#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:10:26.66#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:10:26.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.07:10:26.72#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:10:26.72#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:10:26.72#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.07:10:26.72#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.07:10:26.72$vck44/va=4,7 2006.145.07:10:26.72#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.07:10:26.72#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.07:10:26.72#ibcon#ireg 11 cls_cnt 2 2006.145.07:10:26.72#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:10:26.78#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:10:26.78#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:10:26.80#ibcon#[25=AT04-07\r\n] 2006.145.07:10:26.83#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:10:26.83#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:10:26.83#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.07:10:26.83#ibcon#ireg 7 cls_cnt 0 2006.145.07:10:26.83#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:10:26.95#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:10:26.95#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:10:26.97#ibcon#[25=USB\r\n] 2006.145.07:10:27.00#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:10:27.00#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:10:27.00#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.07:10:27.00#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.07:10:27.00$vck44/valo=5,734.99 2006.145.07:10:27.00#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.07:10:27.00#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.07:10:27.00#ibcon#ireg 17 cls_cnt 0 2006.145.07:10:27.00#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:10:27.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:10:27.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:10:27.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.07:10:27.06#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:10:27.06#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:10:27.06#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.07:10:27.06#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.07:10:27.06$vck44/va=5,4 2006.145.07:10:27.06#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.07:10:27.06#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.07:10:27.06#ibcon#ireg 11 cls_cnt 2 2006.145.07:10:27.06#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:10:27.12#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:10:27.12#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:10:27.14#ibcon#[25=AT05-04\r\n] 2006.145.07:10:27.17#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:10:27.17#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:10:27.17#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.07:10:27.17#ibcon#ireg 7 cls_cnt 0 2006.145.07:10:27.17#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:10:27.29#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:10:27.29#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:10:27.31#ibcon#[25=USB\r\n] 2006.145.07:10:27.34#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:10:27.34#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:10:27.34#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.07:10:27.34#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.07:10:27.34$vck44/valo=6,814.99 2006.145.07:10:27.34#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.07:10:27.34#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.07:10:27.34#ibcon#ireg 17 cls_cnt 0 2006.145.07:10:27.34#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:10:27.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:10:27.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:10:27.36#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.07:10:27.40#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:10:27.40#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:10:27.40#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.07:10:27.40#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.07:10:27.40$vck44/va=6,4 2006.145.07:10:27.40#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.07:10:27.40#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.07:10:27.40#ibcon#ireg 11 cls_cnt 2 2006.145.07:10:27.40#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:10:27.46#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:10:27.46#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:10:27.48#ibcon#[25=AT06-04\r\n] 2006.145.07:10:27.51#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:10:27.51#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:10:27.51#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.07:10:27.51#ibcon#ireg 7 cls_cnt 0 2006.145.07:10:27.51#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:10:27.63#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:10:27.63#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:10:27.65#ibcon#[25=USB\r\n] 2006.145.07:10:27.68#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:10:27.68#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:10:27.68#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.07:10:27.68#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.07:10:27.68$vck44/valo=7,864.99 2006.145.07:10:27.68#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.07:10:27.68#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.07:10:27.68#ibcon#ireg 17 cls_cnt 0 2006.145.07:10:27.68#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:10:27.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:10:27.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:10:27.70#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.07:10:27.74#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:10:27.74#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:10:27.74#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.07:10:27.74#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.07:10:27.74$vck44/va=7,4 2006.145.07:10:27.74#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.07:10:27.74#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.07:10:27.74#ibcon#ireg 11 cls_cnt 2 2006.145.07:10:27.74#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:10:27.80#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:10:27.80#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:10:27.82#ibcon#[25=AT07-04\r\n] 2006.145.07:10:27.85#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:10:27.85#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:10:27.85#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.07:10:27.85#ibcon#ireg 7 cls_cnt 0 2006.145.07:10:27.85#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:10:27.97#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:10:27.97#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:10:27.99#ibcon#[25=USB\r\n] 2006.145.07:10:28.02#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:10:28.02#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:10:28.02#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.07:10:28.02#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.07:10:28.02$vck44/valo=8,884.99 2006.145.07:10:28.02#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.07:10:28.02#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.07:10:28.02#ibcon#ireg 17 cls_cnt 0 2006.145.07:10:28.02#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:10:28.02#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:10:28.02#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:10:28.04#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.07:10:28.08#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:10:28.08#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:10:28.08#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.07:10:28.08#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.07:10:28.08$vck44/va=8,4 2006.145.07:10:28.08#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.07:10:28.08#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.07:10:28.08#ibcon#ireg 11 cls_cnt 2 2006.145.07:10:28.08#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:10:28.14#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:10:28.14#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:10:28.16#ibcon#[25=AT08-04\r\n] 2006.145.07:10:28.19#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:10:28.19#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:10:28.19#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.07:10:28.19#ibcon#ireg 7 cls_cnt 0 2006.145.07:10:28.19#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:10:28.31#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:10:28.31#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:10:28.35#ibcon#[25=USB\r\n] 2006.145.07:10:28.37#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:10:28.37#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:10:28.37#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.07:10:28.37#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.07:10:28.37$vck44/vblo=1,629.99 2006.145.07:10:28.37#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.07:10:28.37#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.07:10:28.37#ibcon#ireg 17 cls_cnt 0 2006.145.07:10:28.37#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:10:28.37#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:10:28.37#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:10:28.39#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.07:10:28.43#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:10:28.43#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:10:28.43#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.07:10:28.43#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.07:10:28.43$vck44/vb=1,3 2006.145.07:10:28.43#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.07:10:28.43#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.07:10:28.43#ibcon#ireg 11 cls_cnt 2 2006.145.07:10:28.43#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:10:28.43#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:10:28.43#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:10:28.45#ibcon#[27=AT01-03\r\n] 2006.145.07:10:28.48#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:10:28.48#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:10:28.48#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.07:10:28.48#ibcon#ireg 7 cls_cnt 0 2006.145.07:10:28.48#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:10:28.60#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:10:28.60#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:10:28.62#ibcon#[27=USB\r\n] 2006.145.07:10:28.65#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:10:28.65#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:10:28.65#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.07:10:28.65#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.07:10:28.65$vck44/vblo=2,634.99 2006.145.07:10:28.65#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.07:10:28.65#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.07:10:28.65#ibcon#ireg 17 cls_cnt 0 2006.145.07:10:28.65#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:10:28.65#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:10:28.65#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:10:28.67#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.07:10:28.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:10:28.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:10:28.71#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.07:10:28.71#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.07:10:28.71$vck44/vb=2,4 2006.145.07:10:28.71#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.07:10:28.71#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.07:10:28.71#ibcon#ireg 11 cls_cnt 2 2006.145.07:10:28.71#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:10:28.77#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:10:28.77#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:10:28.79#ibcon#[27=AT02-04\r\n] 2006.145.07:10:28.82#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:10:28.82#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:10:28.82#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.07:10:28.82#ibcon#ireg 7 cls_cnt 0 2006.145.07:10:28.82#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:10:28.94#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:10:28.94#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:10:28.96#ibcon#[27=USB\r\n] 2006.145.07:10:28.99#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:10:28.99#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:10:28.99#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.07:10:28.99#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.07:10:28.99$vck44/vblo=3,649.99 2006.145.07:10:28.99#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.07:10:28.99#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.07:10:28.99#ibcon#ireg 17 cls_cnt 0 2006.145.07:10:28.99#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:10:28.99#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:10:28.99#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:10:29.01#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.07:10:29.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:10:29.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:10:29.05#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.07:10:29.05#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.07:10:29.05$vck44/vb=3,4 2006.145.07:10:29.05#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.07:10:29.05#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.07:10:29.05#ibcon#ireg 11 cls_cnt 2 2006.145.07:10:29.05#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:10:29.11#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:10:29.11#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:10:29.13#ibcon#[27=AT03-04\r\n] 2006.145.07:10:29.16#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:10:29.16#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:10:29.16#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.07:10:29.16#ibcon#ireg 7 cls_cnt 0 2006.145.07:10:29.16#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:10:29.28#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:10:29.28#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:10:29.30#ibcon#[27=USB\r\n] 2006.145.07:10:29.33#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:10:29.33#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:10:29.33#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.07:10:29.33#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.07:10:29.33$vck44/vblo=4,679.99 2006.145.07:10:29.33#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.07:10:29.33#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.07:10:29.33#ibcon#ireg 17 cls_cnt 0 2006.145.07:10:29.33#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:10:29.33#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:10:29.33#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:10:29.35#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.07:10:29.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:10:29.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:10:29.39#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.07:10:29.39#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.07:10:29.39$vck44/vb=4,4 2006.145.07:10:29.39#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.07:10:29.39#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.07:10:29.39#ibcon#ireg 11 cls_cnt 2 2006.145.07:10:29.39#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:10:29.45#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:10:29.45#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:10:29.47#ibcon#[27=AT04-04\r\n] 2006.145.07:10:29.50#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:10:29.50#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:10:29.50#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.07:10:29.50#ibcon#ireg 7 cls_cnt 0 2006.145.07:10:29.50#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:10:29.62#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:10:29.62#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:10:29.64#ibcon#[27=USB\r\n] 2006.145.07:10:29.67#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:10:29.67#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:10:29.67#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.07:10:29.67#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.07:10:29.67$vck44/vblo=5,709.99 2006.145.07:10:29.67#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.07:10:29.67#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.07:10:29.67#ibcon#ireg 17 cls_cnt 0 2006.145.07:10:29.67#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:10:29.67#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:10:29.67#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:10:29.69#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.07:10:29.73#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:10:29.73#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:10:29.73#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.07:10:29.73#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.07:10:29.73$vck44/vb=5,4 2006.145.07:10:29.73#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.07:10:29.73#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.07:10:29.73#ibcon#ireg 11 cls_cnt 2 2006.145.07:10:29.73#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:10:29.79#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:10:29.79#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:10:29.81#ibcon#[27=AT05-04\r\n] 2006.145.07:10:29.84#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:10:29.84#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:10:29.84#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.07:10:29.84#ibcon#ireg 7 cls_cnt 0 2006.145.07:10:29.84#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:10:29.96#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:10:29.96#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:10:29.98#ibcon#[27=USB\r\n] 2006.145.07:10:30.01#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:10:30.01#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:10:30.01#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.07:10:30.01#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.07:10:30.01$vck44/vblo=6,719.99 2006.145.07:10:30.01#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.07:10:30.01#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.07:10:30.01#ibcon#ireg 17 cls_cnt 0 2006.145.07:10:30.01#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:10:30.01#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:10:30.01#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:10:30.03#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.07:10:30.07#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:10:30.07#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:10:30.07#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.07:10:30.07#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.07:10:30.07$vck44/vb=6,4 2006.145.07:10:30.07#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.07:10:30.07#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.07:10:30.07#ibcon#ireg 11 cls_cnt 2 2006.145.07:10:30.07#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:10:30.13#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:10:30.13#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:10:30.15#ibcon#[27=AT06-04\r\n] 2006.145.07:10:30.18#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:10:30.18#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:10:30.18#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.07:10:30.18#ibcon#ireg 7 cls_cnt 0 2006.145.07:10:30.18#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:10:30.30#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:10:30.30#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:10:30.32#ibcon#[27=USB\r\n] 2006.145.07:10:30.35#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:10:30.35#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:10:30.35#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.07:10:30.35#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.07:10:30.35$vck44/vblo=7,734.99 2006.145.07:10:30.35#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.07:10:30.35#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.07:10:30.35#ibcon#ireg 17 cls_cnt 0 2006.145.07:10:30.35#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:10:30.35#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:10:30.35#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:10:30.37#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.07:10:30.41#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:10:30.41#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:10:30.41#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.07:10:30.41#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.07:10:30.41$vck44/vb=7,4 2006.145.07:10:30.41#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.07:10:30.41#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.07:10:30.41#ibcon#ireg 11 cls_cnt 2 2006.145.07:10:30.41#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:10:30.47#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:10:30.47#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:10:30.49#ibcon#[27=AT07-04\r\n] 2006.145.07:10:30.52#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:10:30.52#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:10:30.52#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.07:10:30.52#ibcon#ireg 7 cls_cnt 0 2006.145.07:10:30.52#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:10:30.64#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:10:30.64#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:10:30.66#ibcon#[27=USB\r\n] 2006.145.07:10:30.69#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:10:30.69#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:10:30.69#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.07:10:30.69#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.07:10:30.69$vck44/vblo=8,744.99 2006.145.07:10:30.69#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.07:10:30.69#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.07:10:30.69#ibcon#ireg 17 cls_cnt 0 2006.145.07:10:30.69#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:10:30.69#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:10:30.69#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:10:30.71#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.07:10:30.75#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:10:30.75#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:10:30.75#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.07:10:30.75#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.07:10:30.75$vck44/vb=8,4 2006.145.07:10:30.75#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.07:10:30.75#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.07:10:30.75#ibcon#ireg 11 cls_cnt 2 2006.145.07:10:30.75#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:10:30.81#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:10:30.81#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:10:30.83#ibcon#[27=AT08-04\r\n] 2006.145.07:10:30.86#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:10:30.86#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:10:30.86#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.07:10:30.86#ibcon#ireg 7 cls_cnt 0 2006.145.07:10:30.86#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:10:30.98#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:10:30.98#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:10:31.00#ibcon#[27=USB\r\n] 2006.145.07:10:31.03#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:10:31.03#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:10:31.03#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.07:10:31.03#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.07:10:31.03$vck44/vabw=wide 2006.145.07:10:31.03#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.07:10:31.03#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.07:10:31.03#ibcon#ireg 8 cls_cnt 0 2006.145.07:10:31.03#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:10:31.03#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:10:31.03#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:10:31.05#ibcon#[25=BW32\r\n] 2006.145.07:10:31.08#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:10:31.08#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:10:31.08#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.07:10:31.08#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.07:10:31.08$vck44/vbbw=wide 2006.145.07:10:31.08#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.07:10:31.08#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.07:10:31.08#ibcon#ireg 8 cls_cnt 0 2006.145.07:10:31.08#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.07:10:31.15#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.07:10:31.15#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.07:10:31.17#ibcon#[27=BW32\r\n] 2006.145.07:10:31.20#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.07:10:31.20#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.07:10:31.20#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.07:10:31.20#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.07:10:31.20$setupk4/ifdk4 2006.145.07:10:31.20$ifdk4/lo= 2006.145.07:10:31.20$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.07:10:31.20$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.07:10:31.20$ifdk4/patch= 2006.145.07:10:31.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.07:10:31.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.07:10:31.20$setupk4/!*+20s 2006.145.07:10:34.47#abcon#<5=/05 5.2 8.3 19.52 611017.0\r\n> 2006.145.07:10:34.49#abcon#{5=INTERFACE CLEAR} 2006.145.07:10:34.57#abcon#[5=S1D000X0/0*\r\n] 2006.145.07:10:44.66#abcon#<5=/05 5.2 8.3 19.52 611017.0\r\n> 2006.145.07:10:44.68#abcon#{5=INTERFACE CLEAR} 2006.145.07:10:44.74#abcon#[5=S1D000X0/0*\r\n] 2006.145.07:10:45.68$setupk4/"tpicd 2006.145.07:10:45.68$setupk4/echo=off 2006.145.07:10:45.68$setupk4/xlog=off 2006.145.07:10:45.68:!2006.145.07:14:54 2006.145.07:11:02.14#trakl#Source acquired 2006.145.07:11:03.14#flagr#flagr/antenna,acquired 2006.145.07:14:54.00:preob 2006.145.07:14:55.14/onsource/TRACKING 2006.145.07:14:55.14:!2006.145.07:15:04 2006.145.07:15:04.00:"tape 2006.145.07:15:04.00:"st=record 2006.145.07:15:04.00:data_valid=on 2006.145.07:15:04.00:midob 2006.145.07:15:04.14/onsource/TRACKING 2006.145.07:15:04.14/wx/19.45,1017.1,64 2006.145.07:15:04.20/cable/+6.5420E-03 2006.145.07:15:05.30/va/01,08,usb,yes,29,31 2006.145.07:15:05.30/va/02,07,usb,yes,31,31 2006.145.07:15:05.30/va/03,08,usb,yes,28,29 2006.145.07:15:05.30/va/04,07,usb,yes,32,33 2006.145.07:15:05.30/va/05,04,usb,yes,28,28 2006.145.07:15:05.30/va/06,04,usb,yes,31,31 2006.145.07:15:05.30/va/07,04,usb,yes,31,33 2006.145.07:15:05.30/va/08,04,usb,yes,27,32 2006.145.07:15:05.53/valo/01,524.99,yes,locked 2006.145.07:15:05.53/valo/02,534.99,yes,locked 2006.145.07:15:05.53/valo/03,564.99,yes,locked 2006.145.07:15:05.53/valo/04,624.99,yes,locked 2006.145.07:15:05.53/valo/05,734.99,yes,locked 2006.145.07:15:05.53/valo/06,814.99,yes,locked 2006.145.07:15:05.53/valo/07,864.99,yes,locked 2006.145.07:15:05.53/valo/08,884.99,yes,locked 2006.145.07:15:06.62/vb/01,03,usb,yes,36,33 2006.145.07:15:06.62/vb/02,04,usb,yes,31,31 2006.145.07:15:06.62/vb/03,04,usb,yes,28,31 2006.145.07:15:06.62/vb/04,04,usb,yes,33,32 2006.145.07:15:06.62/vb/05,04,usb,yes,26,28 2006.145.07:15:06.62/vb/06,04,usb,yes,30,26 2006.145.07:15:06.62/vb/07,04,usb,yes,29,29 2006.145.07:15:06.62/vb/08,04,usb,yes,27,30 2006.145.07:15:06.85/vblo/01,629.99,yes,locked 2006.145.07:15:06.85/vblo/02,634.99,yes,locked 2006.145.07:15:06.85/vblo/03,649.99,yes,locked 2006.145.07:15:06.85/vblo/04,679.99,yes,locked 2006.145.07:15:06.85/vblo/05,709.99,yes,locked 2006.145.07:15:06.85/vblo/06,719.99,yes,locked 2006.145.07:15:06.85/vblo/07,734.99,yes,locked 2006.145.07:15:06.85/vblo/08,744.99,yes,locked 2006.145.07:15:07.00/vabw/8 2006.145.07:15:07.15/vbbw/8 2006.145.07:15:07.24/xfe/off,on,15.0 2006.145.07:15:07.61/ifatt/23,28,28,28 2006.145.07:15:08.07/fmout-gps/S +5.4E-08 2006.145.07:15:08.11:!2006.145.07:16:04 2006.145.07:15:57.13#trakl#Off source 2006.145.07:15:57.13?ERROR st -7 Antenna off-source! 2006.145.07:15:57.13#trakl#az 204.370 el 38.872 azerr*cos(el) -0.0055 elerr -0.0180 2006.145.07:15:57.13#flagr#flagr/antenna,off-source 2006.145.07:16:03.13#trakl#Source re-acquired 2006.145.07:16:03.13#flagr#flagr/antenna,re-acquired 2006.145.07:16:04.01:data_valid=off 2006.145.07:16:04.01:"et 2006.145.07:16:04.02:!+3s 2006.145.07:16:07.03:"tape 2006.145.07:16:07.03:postob 2006.145.07:16:07.13/cable/+6.5388E-03 2006.145.07:16:07.14/wx/19.45,1017.1,63 2006.145.07:16:07.22/fmout-gps/S +5.4E-08 2006.145.07:16:07.22:scan_name=145-0718,jd0605,40 2006.145.07:16:07.22:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.145.07:16:08.13#flagr#flagr/antenna,new-source 2006.145.07:16:08.13:checkk5 2006.145.07:16:08.57/chk_autoobs//k5ts1/ autoobs is running! 2006.145.07:16:09.00/chk_autoobs//k5ts2/ autoobs is running! 2006.145.07:16:09.44/chk_autoobs//k5ts3/ autoobs is running! 2006.145.07:16:09.88/chk_autoobs//k5ts4/ autoobs is running! 2006.145.07:16:10.31/chk_obsdata//k5ts1/T1450715??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.145.07:16:10.74/chk_obsdata//k5ts2/T1450715??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.145.07:16:11.17/chk_obsdata//k5ts3/T1450715??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.145.07:16:11.59/chk_obsdata//k5ts4/T1450715??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.145.07:16:12.36/k5log//k5ts1_log_newline 2006.145.07:16:13.10/k5log//k5ts2_log_newline 2006.145.07:16:13.84/k5log//k5ts3_log_newline 2006.145.07:16:14.59/k5log//k5ts4_log_newline 2006.145.07:16:14.62/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.07:16:14.62:setupk4=1 2006.145.07:16:14.62$setupk4/echo=on 2006.145.07:16:14.62$setupk4/pcalon 2006.145.07:16:14.62$pcalon/"no phase cal control is implemented here 2006.145.07:16:14.62$setupk4/"tpicd=stop 2006.145.07:16:14.62$setupk4/"rec=synch_on 2006.145.07:16:14.62$setupk4/"rec_mode=128 2006.145.07:16:14.62$setupk4/!* 2006.145.07:16:14.62$setupk4/recpk4 2006.145.07:16:14.62$recpk4/recpatch= 2006.145.07:16:14.62$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.07:16:14.62$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.07:16:14.62$setupk4/vck44 2006.145.07:16:14.62$vck44/valo=1,524.99 2006.145.07:16:14.62#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.07:16:14.62#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.07:16:14.62#ibcon#ireg 17 cls_cnt 0 2006.145.07:16:14.62#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:16:14.62#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:16:14.62#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:16:14.66#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.07:16:14.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:16:14.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:16:14.71#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.07:16:14.71#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.07:16:14.71$vck44/va=1,8 2006.145.07:16:14.71#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.07:16:14.71#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.07:16:14.71#ibcon#ireg 11 cls_cnt 2 2006.145.07:16:14.71#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:16:14.71#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:16:14.71#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:16:14.73#ibcon#[25=AT01-08\r\n] 2006.145.07:16:14.76#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:16:14.76#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:16:14.76#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.07:16:14.76#ibcon#ireg 7 cls_cnt 0 2006.145.07:16:14.76#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:16:14.88#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:16:14.88#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:16:14.91#ibcon#[25=USB\r\n] 2006.145.07:16:14.94#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:16:14.94#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:16:14.94#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.07:16:14.94#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.07:16:14.94$vck44/valo=2,534.99 2006.145.07:16:14.94#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.07:16:14.94#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.07:16:14.94#ibcon#ireg 17 cls_cnt 0 2006.145.07:16:14.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.07:16:14.94#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.07:16:14.94#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.07:16:14.96#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.07:16:15.00#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.07:16:15.00#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.07:16:15.00#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.07:16:15.00#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.07:16:15.00$vck44/va=2,7 2006.145.07:16:15.00#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.07:16:15.00#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.07:16:15.00#ibcon#ireg 11 cls_cnt 2 2006.145.07:16:15.00#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.07:16:15.06#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.07:16:15.06#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.07:16:15.08#ibcon#[25=AT02-07\r\n] 2006.145.07:16:15.11#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.07:16:15.11#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.07:16:15.11#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.07:16:15.11#ibcon#ireg 7 cls_cnt 0 2006.145.07:16:15.11#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.07:16:15.23#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.07:16:15.23#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.07:16:15.25#ibcon#[25=USB\r\n] 2006.145.07:16:15.28#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.07:16:15.28#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.07:16:15.28#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.07:16:15.28#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.07:16:15.28$vck44/valo=3,564.99 2006.145.07:16:15.28#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.07:16:15.28#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.07:16:15.28#ibcon#ireg 17 cls_cnt 0 2006.145.07:16:15.28#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.07:16:15.28#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.07:16:15.28#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.07:16:15.30#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.07:16:15.34#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.07:16:15.34#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.07:16:15.34#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.07:16:15.34#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.07:16:15.34$vck44/va=3,8 2006.145.07:16:15.34#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.07:16:15.34#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.07:16:15.34#ibcon#ireg 11 cls_cnt 2 2006.145.07:16:15.34#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.07:16:15.40#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.07:16:15.40#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.07:16:15.42#ibcon#[25=AT03-08\r\n] 2006.145.07:16:15.45#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.07:16:15.45#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.07:16:15.45#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.07:16:15.45#ibcon#ireg 7 cls_cnt 0 2006.145.07:16:15.45#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.07:16:15.57#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.07:16:15.57#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.07:16:15.59#ibcon#[25=USB\r\n] 2006.145.07:16:15.62#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.07:16:15.62#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.07:16:15.62#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.07:16:15.62#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.07:16:15.62$vck44/valo=4,624.99 2006.145.07:16:15.62#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.07:16:15.62#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.07:16:15.62#ibcon#ireg 17 cls_cnt 0 2006.145.07:16:15.62#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.07:16:15.62#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.07:16:15.62#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.07:16:15.64#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.07:16:15.68#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.07:16:15.68#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.07:16:15.68#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.07:16:15.68#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.07:16:15.68$vck44/va=4,7 2006.145.07:16:15.68#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.07:16:15.68#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.07:16:15.68#ibcon#ireg 11 cls_cnt 2 2006.145.07:16:15.68#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.07:16:15.74#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.07:16:15.74#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.07:16:15.76#ibcon#[25=AT04-07\r\n] 2006.145.07:16:15.79#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.07:16:15.79#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.07:16:15.79#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.07:16:15.79#ibcon#ireg 7 cls_cnt 0 2006.145.07:16:15.79#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.07:16:15.91#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.07:16:15.91#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.07:16:15.93#ibcon#[25=USB\r\n] 2006.145.07:16:15.96#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.07:16:15.96#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.07:16:15.96#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.07:16:15.96#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.07:16:15.96$vck44/valo=5,734.99 2006.145.07:16:15.96#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.07:16:15.96#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.07:16:15.96#ibcon#ireg 17 cls_cnt 0 2006.145.07:16:15.96#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:16:15.96#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:16:15.96#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:16:15.98#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.07:16:16.02#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:16:16.02#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:16:16.02#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.07:16:16.02#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.07:16:16.02$vck44/va=5,4 2006.145.07:16:16.02#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.07:16:16.02#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.07:16:16.02#ibcon#ireg 11 cls_cnt 2 2006.145.07:16:16.02#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:16:16.08#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:16:16.08#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:16:16.10#ibcon#[25=AT05-04\r\n] 2006.145.07:16:16.13#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:16:16.13#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:16:16.13#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.07:16:16.13#ibcon#ireg 7 cls_cnt 0 2006.145.07:16:16.13#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:16:16.25#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:16:16.25#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:16:16.27#ibcon#[25=USB\r\n] 2006.145.07:16:16.30#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:16:16.30#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:16:16.30#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.07:16:16.30#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.07:16:16.30$vck44/valo=6,814.99 2006.145.07:16:16.30#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.07:16:16.30#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.07:16:16.30#ibcon#ireg 17 cls_cnt 0 2006.145.07:16:16.30#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:16:16.30#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:16:16.30#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:16:16.32#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.07:16:16.36#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:16:16.36#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:16:16.36#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.07:16:16.36#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.07:16:16.36$vck44/va=6,4 2006.145.07:16:16.36#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.07:16:16.36#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.07:16:16.36#ibcon#ireg 11 cls_cnt 2 2006.145.07:16:16.36#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:16:16.42#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:16:16.42#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:16:16.44#ibcon#[25=AT06-04\r\n] 2006.145.07:16:16.47#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:16:16.47#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:16:16.47#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.07:16:16.47#ibcon#ireg 7 cls_cnt 0 2006.145.07:16:16.47#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:16:16.59#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:16:16.59#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:16:16.61#ibcon#[25=USB\r\n] 2006.145.07:16:16.64#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:16:16.64#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:16:16.64#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.07:16:16.64#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.07:16:16.64$vck44/valo=7,864.99 2006.145.07:16:16.64#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.07:16:16.64#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.07:16:16.64#ibcon#ireg 17 cls_cnt 0 2006.145.07:16:16.64#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:16:16.64#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:16:16.64#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:16:16.66#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.07:16:16.70#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:16:16.70#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:16:16.70#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.07:16:16.70#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.07:16:16.70$vck44/va=7,4 2006.145.07:16:16.70#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.07:16:16.70#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.07:16:16.70#ibcon#ireg 11 cls_cnt 2 2006.145.07:16:16.70#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.07:16:16.76#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.07:16:16.76#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.07:16:16.78#ibcon#[25=AT07-04\r\n] 2006.145.07:16:16.81#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.07:16:16.81#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.07:16:16.81#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.07:16:16.81#ibcon#ireg 7 cls_cnt 0 2006.145.07:16:16.81#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.07:16:16.93#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.07:16:16.93#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.07:16:16.95#ibcon#[25=USB\r\n] 2006.145.07:16:16.98#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.07:16:16.98#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.07:16:16.98#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.07:16:16.98#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.07:16:16.98$vck44/valo=8,884.99 2006.145.07:16:16.98#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.07:16:16.98#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.07:16:16.98#ibcon#ireg 17 cls_cnt 0 2006.145.07:16:16.98#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:16:16.98#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:16:16.98#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:16:17.00#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.07:16:17.04#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:16:17.04#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:16:17.04#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.07:16:17.04#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.07:16:17.04$vck44/va=8,4 2006.145.07:16:17.04#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.07:16:17.04#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.07:16:17.04#ibcon#ireg 11 cls_cnt 2 2006.145.07:16:17.04#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.07:16:17.10#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.07:16:17.10#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.07:16:17.12#ibcon#[25=AT08-04\r\n] 2006.145.07:16:17.15#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.07:16:17.15#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.07:16:17.15#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.07:16:17.15#ibcon#ireg 7 cls_cnt 0 2006.145.07:16:17.15#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.07:16:17.27#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.07:16:17.27#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.07:16:17.29#ibcon#[25=USB\r\n] 2006.145.07:16:17.32#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.07:16:17.32#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.07:16:17.32#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.07:16:17.32#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.07:16:17.32$vck44/vblo=1,629.99 2006.145.07:16:17.32#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.07:16:17.32#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.07:16:17.32#ibcon#ireg 17 cls_cnt 0 2006.145.07:16:17.32#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.07:16:17.32#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.07:16:17.32#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.07:16:17.34#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.07:16:17.38#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.07:16:17.38#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.07:16:17.38#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.07:16:17.38#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.07:16:17.38$vck44/vb=1,3 2006.145.07:16:17.38#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.07:16:17.38#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.07:16:17.38#ibcon#ireg 11 cls_cnt 2 2006.145.07:16:17.38#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.07:16:17.38#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.07:16:17.38#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.07:16:17.40#ibcon#[27=AT01-03\r\n] 2006.145.07:16:17.43#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.07:16:17.43#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.07:16:17.43#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.07:16:17.43#ibcon#ireg 7 cls_cnt 0 2006.145.07:16:17.43#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.07:16:17.55#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.07:16:17.55#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.07:16:17.57#ibcon#[27=USB\r\n] 2006.145.07:16:17.60#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.07:16:17.60#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.07:16:17.60#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.07:16:17.60#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.07:16:17.60$vck44/vblo=2,634.99 2006.145.07:16:17.60#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.07:16:17.60#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.07:16:17.60#ibcon#ireg 17 cls_cnt 0 2006.145.07:16:17.60#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:16:17.60#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:16:17.60#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:16:17.62#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.07:16:17.66#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:16:17.66#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:16:17.66#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.07:16:17.66#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.07:16:17.66$vck44/vb=2,4 2006.145.07:16:17.66#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.07:16:17.66#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.07:16:17.66#ibcon#ireg 11 cls_cnt 2 2006.145.07:16:17.66#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:16:17.72#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:16:17.72#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:16:17.74#ibcon#[27=AT02-04\r\n] 2006.145.07:16:17.77#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:16:17.77#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:16:17.77#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.07:16:17.77#ibcon#ireg 7 cls_cnt 0 2006.145.07:16:17.77#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:16:17.89#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:16:17.89#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:16:17.91#ibcon#[27=USB\r\n] 2006.145.07:16:17.94#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:16:17.94#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:16:17.94#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.07:16:17.94#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.07:16:17.94$vck44/vblo=3,649.99 2006.145.07:16:17.94#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.07:16:17.94#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.07:16:17.94#ibcon#ireg 17 cls_cnt 0 2006.145.07:16:17.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.07:16:17.94#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.07:16:17.94#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.07:16:17.96#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.07:16:18.00#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.07:16:18.00#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.07:16:18.00#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.07:16:18.00#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.07:16:18.00$vck44/vb=3,4 2006.145.07:16:18.00#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.07:16:18.00#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.07:16:18.00#ibcon#ireg 11 cls_cnt 2 2006.145.07:16:18.00#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.07:16:18.06#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.07:16:18.06#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.07:16:18.08#ibcon#[27=AT03-04\r\n] 2006.145.07:16:18.11#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.07:16:18.11#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.07:16:18.11#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.07:16:18.11#ibcon#ireg 7 cls_cnt 0 2006.145.07:16:18.11#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.07:16:18.23#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.07:16:18.23#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.07:16:18.25#ibcon#[27=USB\r\n] 2006.145.07:16:18.28#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.07:16:18.28#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.07:16:18.28#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.07:16:18.28#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.07:16:18.28$vck44/vblo=4,679.99 2006.145.07:16:18.28#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.07:16:18.28#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.07:16:18.28#ibcon#ireg 17 cls_cnt 0 2006.145.07:16:18.28#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.07:16:18.28#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.07:16:18.28#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.07:16:18.30#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.07:16:18.34#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.07:16:18.34#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.07:16:18.34#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.07:16:18.34#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.07:16:18.34$vck44/vb=4,4 2006.145.07:16:18.34#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.07:16:18.34#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.07:16:18.34#ibcon#ireg 11 cls_cnt 2 2006.145.07:16:18.34#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.07:16:18.40#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.07:16:18.40#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.07:16:18.42#ibcon#[27=AT04-04\r\n] 2006.145.07:16:18.45#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.07:16:18.45#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.07:16:18.45#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.07:16:18.45#ibcon#ireg 7 cls_cnt 0 2006.145.07:16:18.45#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.07:16:18.57#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.07:16:18.57#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.07:16:18.59#ibcon#[27=USB\r\n] 2006.145.07:16:18.62#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.07:16:18.62#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.07:16:18.62#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.07:16:18.62#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.07:16:18.62$vck44/vblo=5,709.99 2006.145.07:16:18.62#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.07:16:18.62#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.07:16:18.62#ibcon#ireg 17 cls_cnt 0 2006.145.07:16:18.62#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.07:16:18.62#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.07:16:18.62#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.07:16:18.64#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.07:16:18.68#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.07:16:18.68#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.07:16:18.68#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.07:16:18.68#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.07:16:18.68$vck44/vb=5,4 2006.145.07:16:18.68#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.07:16:18.68#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.07:16:18.68#ibcon#ireg 11 cls_cnt 2 2006.145.07:16:18.68#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.07:16:18.74#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.07:16:18.74#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.07:16:18.76#ibcon#[27=AT05-04\r\n] 2006.145.07:16:18.79#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.07:16:18.79#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.07:16:18.79#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.07:16:18.79#ibcon#ireg 7 cls_cnt 0 2006.145.07:16:18.79#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.07:16:18.91#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.07:16:18.91#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.07:16:18.93#ibcon#[27=USB\r\n] 2006.145.07:16:18.96#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.07:16:18.96#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.07:16:18.96#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.07:16:18.96#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.07:16:18.96$vck44/vblo=6,719.99 2006.145.07:16:18.96#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.07:16:18.96#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.07:16:18.96#ibcon#ireg 17 cls_cnt 0 2006.145.07:16:18.96#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:16:18.96#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:16:18.96#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:16:18.98#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.07:16:19.02#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:16:19.02#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:16:19.02#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.07:16:19.02#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.07:16:19.02$vck44/vb=6,4 2006.145.07:16:19.02#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.07:16:19.02#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.07:16:19.02#ibcon#ireg 11 cls_cnt 2 2006.145.07:16:19.02#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:16:19.08#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:16:19.08#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:16:19.10#ibcon#[27=AT06-04\r\n] 2006.145.07:16:19.13#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:16:19.13#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:16:19.13#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.07:16:19.13#ibcon#ireg 7 cls_cnt 0 2006.145.07:16:19.13#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:16:19.25#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:16:19.25#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:16:19.27#ibcon#[27=USB\r\n] 2006.145.07:16:19.30#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:16:19.30#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:16:19.30#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.07:16:19.30#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.07:16:19.30$vck44/vblo=7,734.99 2006.145.07:16:19.30#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.07:16:19.30#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.07:16:19.30#ibcon#ireg 17 cls_cnt 0 2006.145.07:16:19.30#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:16:19.30#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:16:19.30#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:16:19.32#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.07:16:19.36#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:16:19.36#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:16:19.36#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.07:16:19.36#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.07:16:19.36$vck44/vb=7,4 2006.145.07:16:19.36#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.07:16:19.36#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.07:16:19.36#ibcon#ireg 11 cls_cnt 2 2006.145.07:16:19.36#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:16:19.42#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:16:19.42#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:16:19.44#ibcon#[27=AT07-04\r\n] 2006.145.07:16:19.47#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:16:19.47#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:16:19.47#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.07:16:19.47#ibcon#ireg 7 cls_cnt 0 2006.145.07:16:19.47#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:16:19.59#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:16:19.59#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:16:19.61#ibcon#[27=USB\r\n] 2006.145.07:16:19.64#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:16:19.64#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:16:19.64#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.07:16:19.64#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.07:16:19.64$vck44/vblo=8,744.99 2006.145.07:16:19.64#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.07:16:19.64#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.07:16:19.64#ibcon#ireg 17 cls_cnt 0 2006.145.07:16:19.64#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:16:19.64#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:16:19.64#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:16:19.66#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.07:16:19.70#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:16:19.70#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:16:19.70#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.07:16:19.70#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.07:16:19.70$vck44/vb=8,4 2006.145.07:16:19.70#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.07:16:19.70#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.07:16:19.70#ibcon#ireg 11 cls_cnt 2 2006.145.07:16:19.70#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.07:16:19.76#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.07:16:19.76#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.07:16:19.78#ibcon#[27=AT08-04\r\n] 2006.145.07:16:19.81#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.07:16:19.81#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.07:16:19.81#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.07:16:19.81#ibcon#ireg 7 cls_cnt 0 2006.145.07:16:19.81#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.07:16:19.93#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.07:16:19.93#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.07:16:19.95#ibcon#[27=USB\r\n] 2006.145.07:16:19.98#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.07:16:19.98#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.07:16:19.98#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.07:16:19.98#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.07:16:19.98$vck44/vabw=wide 2006.145.07:16:19.98#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.07:16:19.98#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.07:16:19.98#ibcon#ireg 8 cls_cnt 0 2006.145.07:16:19.98#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:16:19.98#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:16:19.98#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:16:20.00#ibcon#[25=BW32\r\n] 2006.145.07:16:20.03#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:16:20.03#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:16:20.03#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.07:16:20.03#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.07:16:20.03$vck44/vbbw=wide 2006.145.07:16:20.03#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.07:16:20.03#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.07:16:20.03#ibcon#ireg 8 cls_cnt 0 2006.145.07:16:20.03#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.07:16:20.10#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.07:16:20.10#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.07:16:20.12#ibcon#[27=BW32\r\n] 2006.145.07:16:20.15#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.07:16:20.15#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.07:16:20.15#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.07:16:20.15#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.07:16:20.15$setupk4/ifdk4 2006.145.07:16:20.15$ifdk4/lo= 2006.145.07:16:20.15$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.07:16:20.15$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.07:16:20.15$ifdk4/patch= 2006.145.07:16:20.15$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.07:16:20.15$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.07:16:20.15$setupk4/!*+20s 2006.145.07:16:20.33#abcon#<5=/04 5.1 8.9 19.45 621017.0\r\n> 2006.145.07:16:20.35#abcon#{5=INTERFACE CLEAR} 2006.145.07:16:20.41#abcon#[5=S1D000X0/0*\r\n] 2006.145.07:16:30.50#abcon#<5=/04 5.2 8.9 19.45 621017.1\r\n> 2006.145.07:16:30.52#abcon#{5=INTERFACE CLEAR} 2006.145.07:16:30.58#abcon#[5=S1D000X0/0*\r\n] 2006.145.07:16:34.63$setupk4/"tpicd 2006.145.07:16:34.63$setupk4/echo=off 2006.145.07:16:34.63$setupk4/xlog=off 2006.145.07:16:34.63:!2006.145.07:17:58 2006.145.07:16:49.13#trakl#Source acquired 2006.145.07:16:49.13#flagr#flagr/antenna,acquired 2006.145.07:17:26.13#trakl#Off source 2006.145.07:17:26.13?ERROR st -7 Antenna off-source! 2006.145.07:17:26.13#trakl#az 110.975 el 6.227 azerr*cos(el) 0.0168 elerr 0.0022 2006.145.07:17:28.13#flagr#flagr/antenna,off-source 2006.145.07:17:32.13#trakl#Source re-acquired 2006.145.07:17:34.13#flagr#flagr/antenna,re-acquired 2006.145.07:17:58.00:preob 2006.145.07:17:59.14/onsource/TRACKING 2006.145.07:17:59.14:!2006.145.07:18:08 2006.145.07:18:08.00:"tape 2006.145.07:18:08.00:"st=record 2006.145.07:18:08.00:data_valid=on 2006.145.07:18:08.00:midob 2006.145.07:18:08.14/onsource/TRACKING 2006.145.07:18:08.14/wx/19.45,1017.1,62 2006.145.07:18:08.33/cable/+6.5401E-03 2006.145.07:18:09.42/va/01,08,usb,yes,36,38 2006.145.07:18:09.42/va/02,07,usb,yes,38,39 2006.145.07:18:09.42/va/03,08,usb,yes,35,36 2006.145.07:18:09.42/va/04,07,usb,yes,40,42 2006.145.07:18:09.42/va/05,04,usb,yes,35,36 2006.145.07:18:09.42/va/06,04,usb,yes,39,39 2006.145.07:18:09.42/va/07,04,usb,yes,39,41 2006.145.07:18:09.42/va/08,04,usb,yes,34,40 2006.145.07:18:09.65/valo/01,524.99,yes,locked 2006.145.07:18:09.65/valo/02,534.99,yes,locked 2006.145.07:18:09.65/valo/03,564.99,yes,locked 2006.145.07:18:09.65/valo/04,624.99,yes,locked 2006.145.07:18:09.65/valo/05,734.99,yes,locked 2006.145.07:18:09.65/valo/06,814.99,yes,locked 2006.145.07:18:09.65/valo/07,864.99,yes,locked 2006.145.07:18:09.65/valo/08,884.99,yes,locked 2006.145.07:18:10.74/vb/01,03,usb,yes,41,38 2006.145.07:18:10.74/vb/02,04,usb,yes,36,35 2006.145.07:18:10.74/vb/03,04,usb,yes,32,36 2006.145.07:18:10.74/vb/04,04,usb,yes,37,36 2006.145.07:18:10.74/vb/05,04,usb,yes,29,32 2006.145.07:18:10.74/vb/06,04,usb,yes,34,30 2006.145.07:18:10.74/vb/07,04,usb,yes,34,34 2006.145.07:18:10.74/vb/08,04,usb,yes,31,35 2006.145.07:18:10.97/vblo/01,629.99,yes,locked 2006.145.07:18:10.97/vblo/02,634.99,yes,locked 2006.145.07:18:10.97/vblo/03,649.99,yes,locked 2006.145.07:18:10.97/vblo/04,679.99,yes,locked 2006.145.07:18:10.97/vblo/05,709.99,yes,locked 2006.145.07:18:10.97/vblo/06,719.99,yes,locked 2006.145.07:18:10.97/vblo/07,734.99,yes,locked 2006.145.07:18:10.97/vblo/08,744.99,yes,locked 2006.145.07:18:11.12/vabw/8 2006.145.07:18:11.27/vbbw/8 2006.145.07:18:11.36/xfe/off,on,15.2 2006.145.07:18:11.73/ifatt/23,28,28,28 2006.145.07:18:12.08/fmout-gps/S +5.5E-08 2006.145.07:18:12.12:!2006.145.07:18:48 2006.145.07:18:34.14#trakl#Off source 2006.145.07:18:34.14?ERROR st -7 Antenna off-source! 2006.145.07:18:34.14#trakl#az 111.151 el 6.436 azerr*cos(el) 0.0056 elerr 0.0161 2006.145.07:18:34.14#flagr#flagr/antenna,off-source 2006.145.07:18:42.14#trakl#Source re-acquired 2006.145.07:18:43.14#flagr#flagr/antenna,re-acquired 2006.145.07:18:48.00:data_valid=off 2006.145.07:18:48.00:"et 2006.145.07:18:48.01:!+3s 2006.145.07:18:51.02:"tape 2006.145.07:18:51.02:postob 2006.145.07:18:51.20/cable/+6.5393E-03 2006.145.07:18:51.20/wx/19.44,1017.2,63 2006.145.07:18:52.08/fmout-gps/S +5.6E-08 2006.145.07:18:52.08:scan_name=145-0719,jd0605,490 2006.145.07:18:52.09:source=oq208,140700.39,282714.7,2000.0,cw 2006.145.07:18:53.14#flagr#flagr/antenna,new-source 2006.145.07:18:53.14:checkk5 2006.145.07:18:53.57/chk_autoobs//k5ts1/ autoobs is running! 2006.145.07:18:53.99/chk_autoobs//k5ts2/ autoobs is running! 2006.145.07:18:54.42/chk_autoobs//k5ts3/ autoobs is running! 2006.145.07:18:54.85/chk_autoobs//k5ts4/ autoobs is running! 2006.145.07:18:55.28/chk_obsdata//k5ts1/T1450718??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.07:18:55.74/chk_obsdata//k5ts2/T1450718??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.07:18:56.19/chk_obsdata//k5ts3/T1450718??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.07:18:56.64/chk_obsdata//k5ts4/T1450718??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.07:18:57.38/k5log//k5ts1_log_newline 2006.145.07:18:58.12/k5log//k5ts2_log_newline 2006.145.07:18:58.85/k5log//k5ts3_log_newline 2006.145.07:18:59.62/k5log//k5ts4_log_newline 2006.145.07:18:59.64/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.07:18:59.64:setupk4=1 2006.145.07:18:59.64$setupk4/echo=on 2006.145.07:18:59.64$setupk4/pcalon 2006.145.07:18:59.64$pcalon/"no phase cal control is implemented here 2006.145.07:18:59.64$setupk4/"tpicd=stop 2006.145.07:18:59.64$setupk4/"rec=synch_on 2006.145.07:18:59.64$setupk4/"rec_mode=128 2006.145.07:18:59.64$setupk4/!* 2006.145.07:18:59.64$setupk4/recpk4 2006.145.07:18:59.64$recpk4/recpatch= 2006.145.07:18:59.64$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.07:18:59.64$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.07:18:59.64$setupk4/vck44 2006.145.07:18:59.64$vck44/valo=1,524.99 2006.145.07:18:59.64#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.07:18:59.64#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.07:18:59.64#ibcon#ireg 17 cls_cnt 0 2006.145.07:18:59.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:18:59.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:18:59.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:18:59.68#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.07:18:59.73#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:18:59.73#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:18:59.73#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.07:18:59.73#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.07:18:59.73$vck44/va=1,8 2006.145.07:18:59.73#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.07:18:59.73#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.07:18:59.73#ibcon#ireg 11 cls_cnt 2 2006.145.07:18:59.73#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:18:59.73#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:18:59.73#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:18:59.75#ibcon#[25=AT01-08\r\n] 2006.145.07:18:59.78#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:18:59.78#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:18:59.78#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.07:18:59.78#ibcon#ireg 7 cls_cnt 0 2006.145.07:18:59.78#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:18:59.91#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:18:59.91#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:18:59.92#ibcon#[25=USB\r\n] 2006.145.07:18:59.95#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:18:59.95#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:18:59.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.07:18:59.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.07:18:59.95$vck44/valo=2,534.99 2006.145.07:18:59.95#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.07:18:59.95#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.07:18:59.95#ibcon#ireg 17 cls_cnt 0 2006.145.07:18:59.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:18:59.95#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:18:59.95#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:18:59.98#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.07:19:00.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:19:00.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:19:00.02#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.07:19:00.02#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.07:19:00.02$vck44/va=2,7 2006.145.07:19:00.02#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.07:19:00.02#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.07:19:00.02#ibcon#ireg 11 cls_cnt 2 2006.145.07:19:00.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:19:00.07#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:19:00.07#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:19:00.09#ibcon#[25=AT02-07\r\n] 2006.145.07:19:00.12#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:19:00.12#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:19:00.12#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.07:19:00.12#ibcon#ireg 7 cls_cnt 0 2006.145.07:19:00.12#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:19:00.24#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:19:00.24#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:19:00.26#ibcon#[25=USB\r\n] 2006.145.07:19:00.29#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:19:00.29#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:19:00.29#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.07:19:00.29#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.07:19:00.29$vck44/valo=3,564.99 2006.145.07:19:00.29#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.07:19:00.29#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.07:19:00.29#ibcon#ireg 17 cls_cnt 0 2006.145.07:19:00.29#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:19:00.29#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:19:00.29#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:19:00.31#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.07:19:00.35#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:19:00.35#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:19:00.35#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.07:19:00.35#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.07:19:00.35$vck44/va=3,8 2006.145.07:19:00.35#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.07:19:00.35#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.07:19:00.35#ibcon#ireg 11 cls_cnt 2 2006.145.07:19:00.35#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:19:00.41#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:19:00.41#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:19:00.43#ibcon#[25=AT03-08\r\n] 2006.145.07:19:00.46#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:19:00.46#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:19:00.46#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.07:19:00.46#ibcon#ireg 7 cls_cnt 0 2006.145.07:19:00.46#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:19:00.58#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:19:00.58#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:19:00.60#ibcon#[25=USB\r\n] 2006.145.07:19:00.63#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:19:00.63#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:19:00.63#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.07:19:00.63#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.07:19:00.63$vck44/valo=4,624.99 2006.145.07:19:00.63#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.07:19:00.63#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.07:19:00.63#ibcon#ireg 17 cls_cnt 0 2006.145.07:19:00.63#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:19:00.63#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:19:00.63#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:19:00.65#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.07:19:00.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:19:00.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:19:00.69#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.07:19:00.69#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.07:19:00.69$vck44/va=4,7 2006.145.07:19:00.69#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.07:19:00.69#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.07:19:00.69#ibcon#ireg 11 cls_cnt 2 2006.145.07:19:00.69#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:19:00.75#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:19:00.75#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:19:00.77#ibcon#[25=AT04-07\r\n] 2006.145.07:19:00.80#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:19:00.80#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:19:00.80#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.07:19:00.80#ibcon#ireg 7 cls_cnt 0 2006.145.07:19:00.80#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:19:00.92#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:19:00.92#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:19:00.94#ibcon#[25=USB\r\n] 2006.145.07:19:00.97#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:19:00.97#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:19:00.97#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.07:19:00.97#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.07:19:00.97$vck44/valo=5,734.99 2006.145.07:19:00.97#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.07:19:00.97#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.07:19:00.97#ibcon#ireg 17 cls_cnt 0 2006.145.07:19:00.97#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:19:00.97#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:19:00.97#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:19:01.01#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.07:19:01.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:19:01.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:19:01.05#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.07:19:01.05#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.07:19:01.05$vck44/va=5,4 2006.145.07:19:01.05#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.07:19:01.05#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.07:19:01.05#ibcon#ireg 11 cls_cnt 2 2006.145.07:19:01.05#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:19:01.09#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:19:01.09#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:19:01.11#ibcon#[25=AT05-04\r\n] 2006.145.07:19:01.14#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:19:01.14#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:19:01.14#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.07:19:01.14#ibcon#ireg 7 cls_cnt 0 2006.145.07:19:01.14#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:19:01.26#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:19:01.26#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:19:01.28#ibcon#[25=USB\r\n] 2006.145.07:19:01.31#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:19:01.31#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:19:01.31#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.07:19:01.31#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.07:19:01.31$vck44/valo=6,814.99 2006.145.07:19:01.31#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.07:19:01.31#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.07:19:01.31#ibcon#ireg 17 cls_cnt 0 2006.145.07:19:01.31#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:19:01.31#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:19:01.31#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:19:01.33#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.07:19:01.37#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:19:01.37#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:19:01.37#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.07:19:01.37#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.07:19:01.37$vck44/va=6,4 2006.145.07:19:01.37#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.07:19:01.37#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.07:19:01.37#ibcon#ireg 11 cls_cnt 2 2006.145.07:19:01.37#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:19:01.43#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:19:01.43#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:19:01.45#ibcon#[25=AT06-04\r\n] 2006.145.07:19:01.48#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:19:01.48#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:19:01.48#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.07:19:01.48#ibcon#ireg 7 cls_cnt 0 2006.145.07:19:01.48#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:19:01.60#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:19:01.60#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:19:01.62#ibcon#[25=USB\r\n] 2006.145.07:19:01.65#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:19:01.65#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:19:01.65#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.07:19:01.65#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.07:19:01.65$vck44/valo=7,864.99 2006.145.07:19:01.65#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.07:19:01.65#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.07:19:01.65#ibcon#ireg 17 cls_cnt 0 2006.145.07:19:01.65#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:19:01.65#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:19:01.65#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:19:01.67#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.07:19:01.71#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:19:01.71#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:19:01.71#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.07:19:01.71#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.07:19:01.71$vck44/va=7,4 2006.145.07:19:01.71#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.07:19:01.71#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.07:19:01.71#ibcon#ireg 11 cls_cnt 2 2006.145.07:19:01.71#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:19:01.77#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:19:01.77#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:19:01.79#ibcon#[25=AT07-04\r\n] 2006.145.07:19:01.82#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:19:01.82#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:19:01.82#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.07:19:01.82#ibcon#ireg 7 cls_cnt 0 2006.145.07:19:01.82#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:19:01.94#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:19:01.94#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:19:01.96#ibcon#[25=USB\r\n] 2006.145.07:19:01.99#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:19:01.99#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:19:01.99#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.07:19:01.99#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.07:19:01.99$vck44/valo=8,884.99 2006.145.07:19:01.99#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.07:19:01.99#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.07:19:01.99#ibcon#ireg 17 cls_cnt 0 2006.145.07:19:01.99#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:19:01.99#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:19:01.99#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:19:02.01#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.07:19:02.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:19:02.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:19:02.05#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.07:19:02.05#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.07:19:02.05$vck44/va=8,4 2006.145.07:19:02.05#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.07:19:02.05#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.07:19:02.05#ibcon#ireg 11 cls_cnt 2 2006.145.07:19:02.05#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:19:02.11#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:19:02.11#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:19:02.13#ibcon#[25=AT08-04\r\n] 2006.145.07:19:02.16#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:19:02.16#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:19:02.16#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.07:19:02.16#ibcon#ireg 7 cls_cnt 0 2006.145.07:19:02.16#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:19:02.28#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:19:02.28#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:19:02.30#ibcon#[25=USB\r\n] 2006.145.07:19:02.33#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:19:02.33#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:19:02.33#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.07:19:02.33#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.07:19:02.33$vck44/vblo=1,629.99 2006.145.07:19:02.33#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.07:19:02.33#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.07:19:02.33#ibcon#ireg 17 cls_cnt 0 2006.145.07:19:02.33#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:19:02.33#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:19:02.33#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:19:02.35#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.07:19:02.39#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:19:02.39#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:19:02.39#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.07:19:02.39#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.07:19:02.39$vck44/vb=1,3 2006.145.07:19:02.39#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.07:19:02.39#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.07:19:02.39#ibcon#ireg 11 cls_cnt 2 2006.145.07:19:02.39#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:19:02.39#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:19:02.39#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:19:02.41#ibcon#[27=AT01-03\r\n] 2006.145.07:19:02.44#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:19:02.44#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:19:02.44#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.07:19:02.44#ibcon#ireg 7 cls_cnt 0 2006.145.07:19:02.44#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:19:02.56#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:19:02.56#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:19:02.58#ibcon#[27=USB\r\n] 2006.145.07:19:02.61#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:19:02.61#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:19:02.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.07:19:02.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.07:19:02.61$vck44/vblo=2,634.99 2006.145.07:19:02.61#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.07:19:02.61#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.07:19:02.61#ibcon#ireg 17 cls_cnt 0 2006.145.07:19:02.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:19:02.61#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:19:02.61#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:19:02.63#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.07:19:02.67#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:19:02.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:19:02.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.07:19:02.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.07:19:02.67$vck44/vb=2,4 2006.145.07:19:02.67#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.07:19:02.67#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.07:19:02.67#ibcon#ireg 11 cls_cnt 2 2006.145.07:19:02.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:19:02.73#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:19:02.73#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:19:02.75#ibcon#[27=AT02-04\r\n] 2006.145.07:19:02.78#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:19:02.78#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:19:02.78#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.07:19:02.78#ibcon#ireg 7 cls_cnt 0 2006.145.07:19:02.78#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:19:02.90#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:19:02.90#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:19:02.92#ibcon#[27=USB\r\n] 2006.145.07:19:02.95#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:19:02.95#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:19:02.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.07:19:02.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.07:19:02.95$vck44/vblo=3,649.99 2006.145.07:19:02.95#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.07:19:02.95#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.07:19:02.95#ibcon#ireg 17 cls_cnt 0 2006.145.07:19:02.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:19:02.95#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:19:02.95#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:19:02.97#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.07:19:03.01#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:19:03.01#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:19:03.01#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.07:19:03.01#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.07:19:03.01$vck44/vb=3,4 2006.145.07:19:03.01#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.07:19:03.01#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.07:19:03.01#ibcon#ireg 11 cls_cnt 2 2006.145.07:19:03.01#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:19:03.05#abcon#<5=/04 5.1 8.9 19.44 631017.2\r\n> 2006.145.07:19:03.07#abcon#{5=INTERFACE CLEAR} 2006.145.07:19:03.07#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:19:03.07#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:19:03.09#ibcon#[27=AT03-04\r\n] 2006.145.07:19:03.12#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:19:03.12#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:19:03.12#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.07:19:03.12#ibcon#ireg 7 cls_cnt 0 2006.145.07:19:03.12#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:19:03.13#abcon#[5=S1D000X0/0*\r\n] 2006.145.07:19:03.24#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:19:03.24#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:19:03.26#ibcon#[27=USB\r\n] 2006.145.07:19:03.29#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:19:03.29#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:19:03.29#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.07:19:03.29#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.07:19:03.29$vck44/vblo=4,679.99 2006.145.07:19:03.29#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.07:19:03.29#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.07:19:03.29#ibcon#ireg 17 cls_cnt 0 2006.145.07:19:03.29#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:19:03.29#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:19:03.29#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:19:03.31#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.07:19:03.35#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:19:03.35#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:19:03.35#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.07:19:03.35#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.07:19:03.35$vck44/vb=4,4 2006.145.07:19:03.35#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.07:19:03.35#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.07:19:03.35#ibcon#ireg 11 cls_cnt 2 2006.145.07:19:03.35#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:19:03.41#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:19:03.41#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:19:03.43#ibcon#[27=AT04-04\r\n] 2006.145.07:19:03.46#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:19:03.46#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:19:03.46#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.07:19:03.46#ibcon#ireg 7 cls_cnt 0 2006.145.07:19:03.46#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:19:03.58#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:19:03.58#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:19:03.60#ibcon#[27=USB\r\n] 2006.145.07:19:03.63#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:19:03.63#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:19:03.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.07:19:03.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.07:19:03.63$vck44/vblo=5,709.99 2006.145.07:19:03.63#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.07:19:03.63#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.07:19:03.63#ibcon#ireg 17 cls_cnt 0 2006.145.07:19:03.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:19:03.63#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:19:03.63#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:19:03.65#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.07:19:03.69#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:19:03.69#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:19:03.69#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.07:19:03.69#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.07:19:03.69$vck44/vb=5,4 2006.145.07:19:03.69#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.07:19:03.69#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.07:19:03.69#ibcon#ireg 11 cls_cnt 2 2006.145.07:19:03.69#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:19:03.75#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:19:03.75#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:19:03.77#ibcon#[27=AT05-04\r\n] 2006.145.07:19:03.80#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:19:03.80#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:19:03.80#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.07:19:03.80#ibcon#ireg 7 cls_cnt 0 2006.145.07:19:03.80#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:19:03.92#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:19:03.92#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:19:03.94#ibcon#[27=USB\r\n] 2006.145.07:19:03.97#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:19:03.97#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:19:03.97#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.07:19:03.97#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.07:19:03.97$vck44/vblo=6,719.99 2006.145.07:19:03.97#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.07:19:03.97#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.07:19:03.97#ibcon#ireg 17 cls_cnt 0 2006.145.07:19:03.97#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:19:03.97#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:19:03.97#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:19:03.99#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.07:19:04.03#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:19:04.03#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:19:04.03#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.07:19:04.03#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.07:19:04.03$vck44/vb=6,4 2006.145.07:19:04.03#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.07:19:04.03#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.07:19:04.03#ibcon#ireg 11 cls_cnt 2 2006.145.07:19:04.03#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:19:04.09#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:19:04.09#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:19:04.11#ibcon#[27=AT06-04\r\n] 2006.145.07:19:04.14#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:19:04.14#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:19:04.14#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.07:19:04.14#ibcon#ireg 7 cls_cnt 0 2006.145.07:19:04.14#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:19:04.26#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:19:04.26#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:19:04.28#ibcon#[27=USB\r\n] 2006.145.07:19:04.31#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:19:04.31#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:19:04.31#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.07:19:04.31#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.07:19:04.31$vck44/vblo=7,734.99 2006.145.07:19:04.31#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.07:19:04.31#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.07:19:04.31#ibcon#ireg 17 cls_cnt 0 2006.145.07:19:04.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:19:04.31#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:19:04.31#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:19:04.33#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.07:19:04.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:19:04.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:19:04.37#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.07:19:04.37#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.07:19:04.37$vck44/vb=7,4 2006.145.07:19:04.37#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.07:19:04.37#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.07:19:04.37#ibcon#ireg 11 cls_cnt 2 2006.145.07:19:04.37#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:19:04.43#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:19:04.43#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:19:04.45#ibcon#[27=AT07-04\r\n] 2006.145.07:19:04.48#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:19:04.48#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:19:04.48#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.07:19:04.48#ibcon#ireg 7 cls_cnt 0 2006.145.07:19:04.48#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:19:04.60#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:19:04.60#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:19:04.62#ibcon#[27=USB\r\n] 2006.145.07:19:04.65#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:19:04.65#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:19:04.65#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.07:19:04.65#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.07:19:04.65$vck44/vblo=8,744.99 2006.145.07:19:04.65#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.07:19:04.65#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.07:19:04.65#ibcon#ireg 17 cls_cnt 0 2006.145.07:19:04.65#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:19:04.65#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:19:04.65#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:19:04.67#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.07:19:04.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:19:04.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:19:04.71#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.07:19:04.71#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.07:19:04.71$vck44/vb=8,4 2006.145.07:19:04.71#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.07:19:04.71#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.07:19:04.71#ibcon#ireg 11 cls_cnt 2 2006.145.07:19:04.71#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:19:04.77#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:19:04.77#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:19:04.79#ibcon#[27=AT08-04\r\n] 2006.145.07:19:04.82#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:19:04.82#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:19:04.82#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.07:19:04.82#ibcon#ireg 7 cls_cnt 0 2006.145.07:19:04.82#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:19:04.94#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:19:04.94#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:19:04.96#ibcon#[27=USB\r\n] 2006.145.07:19:04.99#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:19:04.99#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:19:04.99#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.07:19:04.99#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.07:19:04.99$vck44/vabw=wide 2006.145.07:19:04.99#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.07:19:04.99#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.07:19:04.99#ibcon#ireg 8 cls_cnt 0 2006.145.07:19:04.99#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:19:04.99#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:19:04.99#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:19:05.01#ibcon#[25=BW32\r\n] 2006.145.07:19:05.04#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:19:05.04#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:19:05.04#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.07:19:05.04#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.07:19:05.04$vck44/vbbw=wide 2006.145.07:19:05.04#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.07:19:05.04#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.07:19:05.04#ibcon#ireg 8 cls_cnt 0 2006.145.07:19:05.04#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:19:05.11#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:19:05.11#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:19:05.13#ibcon#[27=BW32\r\n] 2006.145.07:19:05.16#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:19:05.16#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:19:05.16#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.07:19:05.16#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.07:19:05.16$setupk4/ifdk4 2006.145.07:19:05.16$ifdk4/lo= 2006.145.07:19:05.16$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.07:19:05.16$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.07:19:05.16$ifdk4/patch= 2006.145.07:19:05.16$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.07:19:05.16$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.07:19:05.16$setupk4/!*+20s 2006.145.07:19:13.22#abcon#<5=/04 5.2 8.9 19.44 631017.1\r\n> 2006.145.07:19:13.24#abcon#{5=INTERFACE CLEAR} 2006.145.07:19:13.32#abcon#[5=S1D000X0/0*\r\n] 2006.145.07:19:15.14#trakl#Source acquired 2006.145.07:19:15.14#flagr#flagr/antenna,acquired 2006.145.07:19:19.65$setupk4/"tpicd 2006.145.07:19:19.65$setupk4/echo=off 2006.145.07:19:19.65$setupk4/xlog=off 2006.145.07:19:19.65:!2006.145.07:19:16 2006.145.07:19:19.65:preob 2006.145.07:19:20.14/onsource/TRACKING 2006.145.07:19:20.14:!2006.145.07:19:26 2006.145.07:19:26.00:"tape 2006.145.07:19:26.00:"st=record 2006.145.07:19:26.00:data_valid=on 2006.145.07:19:26.00:midob 2006.145.07:19:26.14/onsource/TRACKING 2006.145.07:19:26.14/wx/19.43,1017.1,63 2006.145.07:19:26.36/cable/+6.5369E-03 2006.145.07:19:27.45/va/01,08,usb,yes,29,32 2006.145.07:19:27.45/va/02,07,usb,yes,32,32 2006.145.07:19:27.45/va/03,08,usb,yes,29,30 2006.145.07:19:27.45/va/04,07,usb,yes,32,34 2006.145.07:19:27.45/va/05,04,usb,yes,28,29 2006.145.07:19:27.45/va/06,04,usb,yes,32,32 2006.145.07:19:27.45/va/07,04,usb,yes,32,33 2006.145.07:19:27.45/va/08,04,usb,yes,27,33 2006.145.07:19:27.68/valo/01,524.99,yes,locked 2006.145.07:19:27.68/valo/02,534.99,yes,locked 2006.145.07:19:27.68/valo/03,564.99,yes,locked 2006.145.07:19:27.68/valo/04,624.99,yes,locked 2006.145.07:19:27.68/valo/05,734.99,yes,locked 2006.145.07:19:27.68/valo/06,814.99,yes,locked 2006.145.07:19:27.68/valo/07,864.99,yes,locked 2006.145.07:19:27.68/valo/08,884.99,yes,locked 2006.145.07:19:28.77/vb/01,03,usb,yes,36,34 2006.145.07:19:28.77/vb/02,04,usb,yes,32,32 2006.145.07:19:28.77/vb/03,04,usb,yes,29,32 2006.145.07:19:28.77/vb/04,04,usb,yes,33,32 2006.145.07:19:28.77/vb/05,04,usb,yes,26,28 2006.145.07:19:28.77/vb/06,04,usb,yes,30,26 2006.145.07:19:28.77/vb/07,04,usb,yes,30,30 2006.145.07:19:28.77/vb/08,04,usb,yes,27,31 2006.145.07:19:29.00/vblo/01,629.99,yes,locked 2006.145.07:19:29.00/vblo/02,634.99,yes,locked 2006.145.07:19:29.00/vblo/03,649.99,yes,locked 2006.145.07:19:29.00/vblo/04,679.99,yes,locked 2006.145.07:19:29.00/vblo/05,709.99,yes,locked 2006.145.07:19:29.00/vblo/06,719.99,yes,locked 2006.145.07:19:29.00/vblo/07,734.99,yes,locked 2006.145.07:19:29.00/vblo/08,744.99,yes,locked 2006.145.07:19:29.15/vabw/8 2006.145.07:19:29.30/vbbw/8 2006.145.07:19:29.51/xfe/off,on,14.7 2006.145.07:19:29.88/ifatt/23,28,28,28 2006.145.07:19:30.08/fmout-gps/S +5.5E-08 2006.145.07:19:30.12:!2006.145.07:27:36 2006.145.07:20:15.14#trakl#Off source 2006.145.07:20:15.14?ERROR st -7 Antenna off-source! 2006.145.07:20:15.14#trakl#az 71.705 el 24.616 azerr*cos(el) 0.0162 elerr -0.0002 2006.145.07:20:15.14#flagr#flagr/antenna,off-source 2006.145.07:20:21.14#trakl#Source re-acquired 2006.145.07:20:21.14#flagr#flagr/antenna,re-acquired 2006.145.07:21:48.14#trakl#Off source 2006.145.07:21:48.14?ERROR st -7 Antenna off-source! 2006.145.07:21:48.14#trakl#az 71.889 el 24.914 azerr*cos(el) 0.0165 elerr -0.0010 2006.145.07:21:48.14#flagr#flagr/antenna,off-source 2006.145.07:21:54.14#trakl#Source re-acquired 2006.145.07:21:54.14#flagr#flagr/antenna,re-acquired 2006.145.07:23:52.14#trakl#Off source 2006.145.07:23:52.14?ERROR st -7 Antenna off-source! 2006.145.07:23:52.14#trakl#az 72.133 el 25.312 azerr*cos(el) 0.0187 elerr 0.0064 2006.145.07:23:54.14#flagr#flagr/antenna,off-source 2006.145.07:23:58.14#trakl#Source re-acquired 2006.145.07:24:00.14#flagr#flagr/antenna,re-acquired 2006.145.07:27:36.00:data_valid=off 2006.145.07:27:36.00:"et 2006.145.07:27:36.00:!+3s 2006.145.07:27:39.02:"tape 2006.145.07:27:39.02:postob 2006.145.07:27:39.14/cable/+6.5403E-03 2006.145.07:27:39.14/wx/19.32,1017.1,64 2006.145.07:27:40.08/fmout-gps/S +5.4E-08 2006.145.07:27:40.08:scan_name=145-0728,jd0605,50 2006.145.07:27:40.08:source=3c345,164258.81,394837.0,2000.0,cw 2006.145.07:27:41.14#flagr#flagr/antenna,new-source 2006.145.07:27:41.14:checkk5 2006.145.07:27:41.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.07:27:42.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.07:27:42.48/chk_autoobs//k5ts3/ autoobs is running! 2006.145.07:27:42.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.07:27:43.33/chk_obsdata//k5ts1/T1450719??a.dat file size is correct (nominal:1960MB, actual:1956MB). 2006.145.07:27:43.76/chk_obsdata//k5ts2/T1450719??b.dat file size is correct (nominal:1960MB, actual:1956MB). 2006.145.07:27:44.21/chk_obsdata//k5ts3/T1450719??c.dat file size is correct (nominal:1960MB, actual:1956MB). 2006.145.07:27:44.64/chk_obsdata//k5ts4/T1450719??d.dat file size is correct (nominal:1960MB, actual:1956MB). 2006.145.07:27:45.41/k5log//k5ts1_log_newline 2006.145.07:27:46.16/k5log//k5ts2_log_newline 2006.145.07:27:46.91/k5log//k5ts3_log_newline 2006.145.07:27:47.66/k5log//k5ts4_log_newline 2006.145.07:27:47.68/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.07:27:47.68:setupk4=1 2006.145.07:27:47.68$setupk4/echo=on 2006.145.07:27:47.68$setupk4/pcalon 2006.145.07:27:47.68$pcalon/"no phase cal control is implemented here 2006.145.07:27:47.68$setupk4/"tpicd=stop 2006.145.07:27:47.68$setupk4/"rec=synch_on 2006.145.07:27:47.68$setupk4/"rec_mode=128 2006.145.07:27:47.68$setupk4/!* 2006.145.07:27:47.68$setupk4/recpk4 2006.145.07:27:47.68$recpk4/recpatch= 2006.145.07:27:47.68$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.07:27:47.68$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.07:27:47.68$setupk4/vck44 2006.145.07:27:47.68$vck44/valo=1,524.99 2006.145.07:27:47.68#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.07:27:47.68#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.07:27:47.68#ibcon#ireg 17 cls_cnt 0 2006.145.07:27:47.68#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:27:47.68#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:27:47.68#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:27:47.72#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.07:27:47.77#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:27:47.77#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:27:47.77#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.07:27:47.77#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.07:27:47.77$vck44/va=1,8 2006.145.07:27:47.77#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.07:27:47.77#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.07:27:47.77#ibcon#ireg 11 cls_cnt 2 2006.145.07:27:47.77#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.07:27:47.77#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.07:27:47.77#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.07:27:47.79#ibcon#[25=AT01-08\r\n] 2006.145.07:27:47.82#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.07:27:47.82#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.07:27:47.82#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.07:27:47.82#ibcon#ireg 7 cls_cnt 0 2006.145.07:27:47.82#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.07:27:47.94#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.07:27:47.94#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.07:27:47.96#ibcon#[25=USB\r\n] 2006.145.07:27:47.99#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.07:27:47.99#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.07:27:47.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.07:27:47.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.07:27:47.99$vck44/valo=2,534.99 2006.145.07:27:47.99#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.07:27:47.99#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.07:27:47.99#ibcon#ireg 17 cls_cnt 0 2006.145.07:27:47.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.07:27:47.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.07:27:47.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.07:27:48.02#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.07:27:48.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.07:27:48.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.07:27:48.06#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.07:27:48.06#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.07:27:48.06$vck44/va=2,7 2006.145.07:27:48.06#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.07:27:48.06#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.07:27:48.06#ibcon#ireg 11 cls_cnt 2 2006.145.07:27:48.06#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.07:27:48.11#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.07:27:48.11#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.07:27:48.13#ibcon#[25=AT02-07\r\n] 2006.145.07:27:48.16#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.07:27:48.16#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.07:27:48.16#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.07:27:48.16#ibcon#ireg 7 cls_cnt 0 2006.145.07:27:48.16#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.07:27:48.28#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.07:27:48.28#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.07:27:48.30#ibcon#[25=USB\r\n] 2006.145.07:27:48.33#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.07:27:48.33#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.07:27:48.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.07:27:48.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.07:27:48.33$vck44/valo=3,564.99 2006.145.07:27:48.33#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.07:27:48.33#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.07:27:48.33#ibcon#ireg 17 cls_cnt 0 2006.145.07:27:48.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:27:48.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:27:48.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:27:48.35#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.07:27:48.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:27:48.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:27:48.39#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.07:27:48.39#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.07:27:48.39$vck44/va=3,8 2006.145.07:27:48.39#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.07:27:48.39#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.07:27:48.39#ibcon#ireg 11 cls_cnt 2 2006.145.07:27:48.39#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:27:48.45#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:27:48.45#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:27:48.47#ibcon#[25=AT03-08\r\n] 2006.145.07:27:48.50#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:27:48.50#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:27:48.50#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.07:27:48.50#ibcon#ireg 7 cls_cnt 0 2006.145.07:27:48.50#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:27:48.62#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:27:48.62#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:27:48.64#ibcon#[25=USB\r\n] 2006.145.07:27:48.67#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:27:48.67#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:27:48.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.07:27:48.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.07:27:48.67$vck44/valo=4,624.99 2006.145.07:27:48.67#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.07:27:48.67#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.07:27:48.67#ibcon#ireg 17 cls_cnt 0 2006.145.07:27:48.67#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.07:27:48.67#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.07:27:48.67#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.07:27:48.69#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.07:27:48.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.07:27:48.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.07:27:48.73#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.07:27:48.73#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.07:27:48.73$vck44/va=4,7 2006.145.07:27:48.73#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.07:27:48.73#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.07:27:48.73#ibcon#ireg 11 cls_cnt 2 2006.145.07:27:48.73#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.07:27:48.79#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.07:27:48.79#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.07:27:48.81#ibcon#[25=AT04-07\r\n] 2006.145.07:27:48.84#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.07:27:48.84#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.07:27:48.84#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.07:27:48.84#ibcon#ireg 7 cls_cnt 0 2006.145.07:27:48.84#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.07:27:48.96#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.07:27:48.96#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.07:27:48.98#ibcon#[25=USB\r\n] 2006.145.07:27:49.01#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.07:27:49.01#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.07:27:49.01#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.07:27:49.01#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.07:27:49.01$vck44/valo=5,734.99 2006.145.07:27:49.01#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.07:27:49.01#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.07:27:49.01#ibcon#ireg 17 cls_cnt 0 2006.145.07:27:49.01#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.07:27:49.01#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.07:27:49.01#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.07:27:49.03#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.07:27:49.07#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.07:27:49.07#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.07:27:49.07#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.07:27:49.07#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.07:27:49.07$vck44/va=5,4 2006.145.07:27:49.07#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.07:27:49.07#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.07:27:49.07#ibcon#ireg 11 cls_cnt 2 2006.145.07:27:49.07#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.07:27:49.13#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.07:27:49.13#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.07:27:49.15#ibcon#[25=AT05-04\r\n] 2006.145.07:27:49.18#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.07:27:49.18#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.07:27:49.18#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.07:27:49.18#ibcon#ireg 7 cls_cnt 0 2006.145.07:27:49.18#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.07:27:49.30#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.07:27:49.30#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.07:27:49.32#ibcon#[25=USB\r\n] 2006.145.07:27:49.35#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.07:27:49.35#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.07:27:49.35#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.07:27:49.35#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.07:27:49.35$vck44/valo=6,814.99 2006.145.07:27:49.35#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.07:27:49.35#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.07:27:49.35#ibcon#ireg 17 cls_cnt 0 2006.145.07:27:49.35#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.07:27:49.35#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.07:27:49.35#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.07:27:49.37#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.07:27:49.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.07:27:49.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.07:27:49.41#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.07:27:49.41#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.07:27:49.41$vck44/va=6,4 2006.145.07:27:49.41#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.07:27:49.41#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.07:27:49.41#ibcon#ireg 11 cls_cnt 2 2006.145.07:27:49.41#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.07:27:49.47#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.07:27:49.47#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.07:27:49.49#ibcon#[25=AT06-04\r\n] 2006.145.07:27:49.52#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.07:27:49.52#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.07:27:49.52#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.07:27:49.52#ibcon#ireg 7 cls_cnt 0 2006.145.07:27:49.52#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.07:27:49.64#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.07:27:49.64#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.07:27:49.66#ibcon#[25=USB\r\n] 2006.145.07:27:49.69#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.07:27:49.69#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.07:27:49.69#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.07:27:49.69#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.07:27:49.69$vck44/valo=7,864.99 2006.145.07:27:49.69#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.07:27:49.69#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.07:27:49.69#ibcon#ireg 17 cls_cnt 0 2006.145.07:27:49.69#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:27:49.69#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:27:49.69#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:27:49.71#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.07:27:49.75#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:27:49.75#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:27:49.75#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.07:27:49.75#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.07:27:49.75$vck44/va=7,4 2006.145.07:27:49.75#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.07:27:49.75#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.07:27:49.75#ibcon#ireg 11 cls_cnt 2 2006.145.07:27:49.75#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:27:49.81#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:27:49.81#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:27:49.83#ibcon#[25=AT07-04\r\n] 2006.145.07:27:49.86#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:27:49.86#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:27:49.86#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.07:27:49.86#ibcon#ireg 7 cls_cnt 0 2006.145.07:27:49.86#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:27:49.98#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:27:49.98#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:27:50.00#ibcon#[25=USB\r\n] 2006.145.07:27:50.03#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:27:50.03#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:27:50.03#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.07:27:50.03#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.07:27:50.03$vck44/valo=8,884.99 2006.145.07:27:50.03#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.07:27:50.03#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.07:27:50.03#ibcon#ireg 17 cls_cnt 0 2006.145.07:27:50.03#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:27:50.03#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:27:50.03#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:27:50.05#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.07:27:50.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:27:50.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:27:50.09#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.07:27:50.09#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.07:27:50.09$vck44/va=8,4 2006.145.07:27:50.09#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.07:27:50.09#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.07:27:50.09#ibcon#ireg 11 cls_cnt 2 2006.145.07:27:50.09#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:27:50.15#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:27:50.15#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:27:50.17#ibcon#[25=AT08-04\r\n] 2006.145.07:27:50.20#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:27:50.20#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:27:50.20#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.07:27:50.20#ibcon#ireg 7 cls_cnt 0 2006.145.07:27:50.20#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:27:50.32#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:27:50.32#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:27:50.34#ibcon#[25=USB\r\n] 2006.145.07:27:50.37#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:27:50.37#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:27:50.37#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.07:27:50.37#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.07:27:50.37$vck44/vblo=1,629.99 2006.145.07:27:50.37#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.07:27:50.37#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.07:27:50.37#ibcon#ireg 17 cls_cnt 0 2006.145.07:27:50.37#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:27:50.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:27:50.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:27:50.39#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.07:27:50.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:27:50.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:27:50.43#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.07:27:50.43#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.07:27:50.43$vck44/vb=1,3 2006.145.07:27:50.43#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.07:27:50.43#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.07:27:50.43#ibcon#ireg 11 cls_cnt 2 2006.145.07:27:50.43#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.07:27:50.43#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.07:27:50.43#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.07:27:50.45#ibcon#[27=AT01-03\r\n] 2006.145.07:27:50.48#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.07:27:50.48#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.07:27:50.48#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.07:27:50.48#ibcon#ireg 7 cls_cnt 0 2006.145.07:27:50.48#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.07:27:50.60#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.07:27:50.60#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.07:27:50.62#ibcon#[27=USB\r\n] 2006.145.07:27:50.65#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.07:27:50.65#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.07:27:50.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.07:27:50.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.07:27:50.65$vck44/vblo=2,634.99 2006.145.07:27:50.65#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.07:27:50.65#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.07:27:50.65#ibcon#ireg 17 cls_cnt 0 2006.145.07:27:50.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:27:50.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:27:50.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:27:50.67#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.07:27:50.71#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:27:50.71#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:27:50.71#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.07:27:50.71#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.07:27:50.71$vck44/vb=2,4 2006.145.07:27:50.71#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.07:27:50.71#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.07:27:50.71#ibcon#ireg 11 cls_cnt 2 2006.145.07:27:50.71#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.07:27:50.77#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.07:27:50.77#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.07:27:50.79#ibcon#[27=AT02-04\r\n] 2006.145.07:27:50.82#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.07:27:50.82#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.07:27:50.82#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.07:27:50.82#ibcon#ireg 7 cls_cnt 0 2006.145.07:27:50.82#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.07:27:50.94#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.07:27:50.94#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.07:27:50.96#ibcon#[27=USB\r\n] 2006.145.07:27:50.99#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.07:27:50.99#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.07:27:50.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.07:27:50.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.07:27:50.99$vck44/vblo=3,649.99 2006.145.07:27:50.99#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.07:27:50.99#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.07:27:50.99#ibcon#ireg 17 cls_cnt 0 2006.145.07:27:50.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.07:27:50.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.07:27:50.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.07:27:51.01#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.07:27:51.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.07:27:51.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.07:27:51.05#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.07:27:51.05#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.07:27:51.05$vck44/vb=3,4 2006.145.07:27:51.05#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.07:27:51.05#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.07:27:51.05#ibcon#ireg 11 cls_cnt 2 2006.145.07:27:51.05#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.07:27:51.11#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.07:27:51.11#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.07:27:51.13#ibcon#[27=AT03-04\r\n] 2006.145.07:27:51.16#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.07:27:51.16#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.07:27:51.16#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.07:27:51.16#ibcon#ireg 7 cls_cnt 0 2006.145.07:27:51.16#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.07:27:51.28#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.07:27:51.28#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.07:27:51.30#ibcon#[27=USB\r\n] 2006.145.07:27:51.33#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.07:27:51.33#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.07:27:51.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.07:27:51.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.07:27:51.33$vck44/vblo=4,679.99 2006.145.07:27:51.33#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.07:27:51.33#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.07:27:51.33#ibcon#ireg 17 cls_cnt 0 2006.145.07:27:51.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:27:51.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:27:51.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:27:51.35#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.07:27:51.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:27:51.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:27:51.39#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.07:27:51.39#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.07:27:51.39$vck44/vb=4,4 2006.145.07:27:51.39#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.07:27:51.39#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.07:27:51.39#ibcon#ireg 11 cls_cnt 2 2006.145.07:27:51.39#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:27:51.45#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:27:51.45#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:27:51.47#ibcon#[27=AT04-04\r\n] 2006.145.07:27:51.50#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:27:51.50#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:27:51.50#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.07:27:51.50#ibcon#ireg 7 cls_cnt 0 2006.145.07:27:51.50#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:27:51.62#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:27:51.62#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:27:51.64#ibcon#[27=USB\r\n] 2006.145.07:27:51.67#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:27:51.67#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:27:51.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.07:27:51.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.07:27:51.67$vck44/vblo=5,709.99 2006.145.07:27:51.67#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.07:27:51.67#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.07:27:51.67#ibcon#ireg 17 cls_cnt 0 2006.145.07:27:51.67#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.07:27:51.67#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.07:27:51.67#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.07:27:51.69#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.07:27:51.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.07:27:51.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.07:27:51.73#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.07:27:51.73#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.07:27:51.73$vck44/vb=5,4 2006.145.07:27:51.73#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.07:27:51.73#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.07:27:51.73#ibcon#ireg 11 cls_cnt 2 2006.145.07:27:51.73#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.07:27:51.79#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.07:27:51.79#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.07:27:51.81#ibcon#[27=AT05-04\r\n] 2006.145.07:27:51.84#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.07:27:51.84#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.07:27:51.84#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.07:27:51.84#ibcon#ireg 7 cls_cnt 0 2006.145.07:27:51.84#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.07:27:51.96#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.07:27:51.96#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.07:27:51.98#ibcon#[27=USB\r\n] 2006.145.07:27:52.01#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.07:27:52.01#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.07:27:52.01#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.07:27:52.01#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.07:27:52.01$vck44/vblo=6,719.99 2006.145.07:27:52.01#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.07:27:52.01#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.07:27:52.01#ibcon#ireg 17 cls_cnt 0 2006.145.07:27:52.01#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.07:27:52.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.07:27:52.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.07:27:52.03#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.07:27:52.04#abcon#<5=/04 4.7 7.9 19.32 631017.1\r\n> 2006.145.07:27:52.06#abcon#{5=INTERFACE CLEAR} 2006.145.07:27:52.07#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.07:27:52.07#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.07:27:52.07#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.07:27:52.07#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.07:27:52.07$vck44/vb=6,4 2006.145.07:27:52.07#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.07:27:52.07#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.07:27:52.07#ibcon#ireg 11 cls_cnt 2 2006.145.07:27:52.07#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:27:52.12#abcon#[5=S1D000X0/0*\r\n] 2006.145.07:27:52.13#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:27:52.13#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:27:52.15#ibcon#[27=AT06-04\r\n] 2006.145.07:27:52.18#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:27:52.18#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:27:52.18#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.07:27:52.18#ibcon#ireg 7 cls_cnt 0 2006.145.07:27:52.18#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:27:52.30#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:27:52.30#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:27:52.32#ibcon#[27=USB\r\n] 2006.145.07:27:52.35#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:27:52.35#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:27:52.35#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.07:27:52.35#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.07:27:52.35$vck44/vblo=7,734.99 2006.145.07:27:52.35#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.07:27:52.35#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.07:27:52.35#ibcon#ireg 17 cls_cnt 0 2006.145.07:27:52.35#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:27:52.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:27:52.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:27:52.37#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.07:27:52.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:27:52.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:27:52.41#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.07:27:52.41#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.07:27:52.41$vck44/vb=7,4 2006.145.07:27:52.41#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.07:27:52.41#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.07:27:52.41#ibcon#ireg 11 cls_cnt 2 2006.145.07:27:52.41#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:27:52.47#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:27:52.47#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:27:52.49#ibcon#[27=AT07-04\r\n] 2006.145.07:27:52.52#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:27:52.52#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:27:52.52#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.07:27:52.52#ibcon#ireg 7 cls_cnt 0 2006.145.07:27:52.52#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:27:52.64#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:27:52.64#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:27:52.66#ibcon#[27=USB\r\n] 2006.145.07:27:52.69#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:27:52.69#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:27:52.69#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.07:27:52.69#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.07:27:52.69$vck44/vblo=8,744.99 2006.145.07:27:52.69#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.07:27:52.69#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.07:27:52.69#ibcon#ireg 17 cls_cnt 0 2006.145.07:27:52.69#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:27:52.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:27:52.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:27:52.71#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.07:27:52.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:27:52.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:27:52.75#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.07:27:52.75#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.07:27:52.75$vck44/vb=8,4 2006.145.07:27:52.75#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.07:27:52.75#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.07:27:52.75#ibcon#ireg 11 cls_cnt 2 2006.145.07:27:52.75#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:27:52.81#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:27:52.81#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:27:52.83#ibcon#[27=AT08-04\r\n] 2006.145.07:27:52.86#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:27:52.86#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:27:52.86#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.07:27:52.86#ibcon#ireg 7 cls_cnt 0 2006.145.07:27:52.86#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:27:52.98#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:27:52.98#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:27:53.00#ibcon#[27=USB\r\n] 2006.145.07:27:53.03#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:27:53.03#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:27:53.03#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.07:27:53.03#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.07:27:53.03$vck44/vabw=wide 2006.145.07:27:53.03#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.07:27:53.03#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.07:27:53.03#ibcon#ireg 8 cls_cnt 0 2006.145.07:27:53.03#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:27:53.03#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:27:53.03#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:27:53.05#ibcon#[25=BW32\r\n] 2006.145.07:27:53.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:27:53.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:27:53.08#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.07:27:53.08#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.07:27:53.08$vck44/vbbw=wide 2006.145.07:27:53.08#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.07:27:53.08#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.07:27:53.08#ibcon#ireg 8 cls_cnt 0 2006.145.07:27:53.08#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.07:27:53.15#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.07:27:53.15#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.07:27:53.17#ibcon#[27=BW32\r\n] 2006.145.07:27:53.20#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.07:27:53.20#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.07:27:53.20#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.07:27:53.20#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.07:27:53.20$setupk4/ifdk4 2006.145.07:27:53.20$ifdk4/lo= 2006.145.07:27:53.20$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.07:27:53.20$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.07:27:53.20$ifdk4/patch= 2006.145.07:27:53.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.07:27:53.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.07:27:53.20$setupk4/!*+20s 2006.145.07:28:00.14#trakl#Source acquired 2006.145.07:28:01.14#flagr#flagr/antenna,acquired 2006.145.07:28:02.21#abcon#<5=/04 4.7 7.9 19.32 631017.1\r\n> 2006.145.07:28:02.23#abcon#{5=INTERFACE CLEAR} 2006.145.07:28:02.29#abcon#[5=S1D000X0/0*\r\n] 2006.145.07:28:07.69$setupk4/"tpicd 2006.145.07:28:07.69$setupk4/echo=off 2006.145.07:28:07.69$setupk4/xlog=off 2006.145.07:28:07.69:!2006.145.07:28:08 2006.145.07:28:08.00:preob 2006.145.07:28:08.14/onsource/TRACKING 2006.145.07:28:08.14:!2006.145.07:28:18 2006.145.07:28:18.00:"tape 2006.145.07:28:18.00:"st=record 2006.145.07:28:18.00:data_valid=on 2006.145.07:28:18.00:midob 2006.145.07:28:19.14/onsource/TRACKING 2006.145.07:28:19.14/wx/19.32,1017.1,64 2006.145.07:28:19.29/cable/+6.5391E-03 2006.145.07:28:20.38/va/01,08,usb,yes,36,39 2006.145.07:28:20.38/va/02,07,usb,yes,39,40 2006.145.07:28:20.38/va/03,08,usb,yes,35,37 2006.145.07:28:20.38/va/04,07,usb,yes,40,42 2006.145.07:28:20.38/va/05,04,usb,yes,35,36 2006.145.07:28:20.38/va/06,04,usb,yes,39,39 2006.145.07:28:20.38/va/07,04,usb,yes,40,41 2006.145.07:28:20.38/va/08,04,usb,yes,34,40 2006.145.07:28:20.61/valo/01,524.99,yes,locked 2006.145.07:28:20.61/valo/02,534.99,yes,locked 2006.145.07:28:20.61/valo/03,564.99,yes,locked 2006.145.07:28:20.61/valo/04,624.99,yes,locked 2006.145.07:28:20.61/valo/05,734.99,yes,locked 2006.145.07:28:20.61/valo/06,814.99,yes,locked 2006.145.07:28:20.61/valo/07,864.99,yes,locked 2006.145.07:28:20.61/valo/08,884.99,yes,locked 2006.145.07:28:21.70/vb/01,03,usb,yes,42,39 2006.145.07:28:21.70/vb/02,04,usb,yes,37,36 2006.145.07:28:21.70/vb/03,04,usb,yes,33,37 2006.145.07:28:21.70/vb/04,04,usb,yes,38,37 2006.145.07:28:21.70/vb/05,04,usb,yes,30,33 2006.145.07:28:21.70/vb/06,04,usb,yes,35,31 2006.145.07:28:21.70/vb/07,04,usb,yes,35,35 2006.145.07:28:21.70/vb/08,04,usb,yes,32,36 2006.145.07:28:21.93/vblo/01,629.99,yes,locked 2006.145.07:28:21.93/vblo/02,634.99,yes,locked 2006.145.07:28:21.93/vblo/03,649.99,yes,locked 2006.145.07:28:21.93/vblo/04,679.99,yes,locked 2006.145.07:28:21.93/vblo/05,709.99,yes,locked 2006.145.07:28:21.93/vblo/06,719.99,yes,locked 2006.145.07:28:21.93/vblo/07,734.99,yes,locked 2006.145.07:28:21.93/vblo/08,744.99,yes,locked 2006.145.07:28:22.08/vabw/8 2006.145.07:28:22.23/vbbw/8 2006.145.07:28:22.32/xfe/off,on,14.2 2006.145.07:28:22.71/ifatt/23,28,28,28 2006.145.07:28:23.08/fmout-gps/S +5.5E-08 2006.145.07:28:23.12:!2006.145.07:29:08 2006.145.07:29:08.00:data_valid=off 2006.145.07:29:08.00:"et 2006.145.07:29:08.00:!+3s 2006.145.07:29:11.02:"tape 2006.145.07:29:11.02:postob 2006.145.07:29:11.16/cable/+6.5396E-03 2006.145.07:29:11.16/wx/19.30,1017.1,63 2006.145.07:29:12.08/fmout-gps/S +5.5E-08 2006.145.07:29:12.08:scan_name=145-0733,jd0605,90 2006.145.07:29:12.08:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.145.07:29:13.14#flagr#flagr/antenna,new-source 2006.145.07:29:13.14:checkk5 2006.145.07:29:13.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.07:29:14.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.07:29:14.43/chk_autoobs//k5ts3/ autoobs is running! 2006.145.07:29:14.87/chk_autoobs//k5ts4/ autoobs is running! 2006.145.07:29:15.31/chk_obsdata//k5ts1/T1450728??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.07:29:15.75/chk_obsdata//k5ts2/T1450728??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.07:29:16.21/chk_obsdata//k5ts3/T1450728??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.07:29:16.64/chk_obsdata//k5ts4/T1450728??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.07:29:17.38/k5log//k5ts1_log_newline 2006.145.07:29:18.13/k5log//k5ts2_log_newline 2006.145.07:29:18.87/k5log//k5ts3_log_newline 2006.145.07:29:19.61/k5log//k5ts4_log_newline 2006.145.07:29:19.63/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.07:29:19.63:setupk4=1 2006.145.07:29:19.63$setupk4/echo=on 2006.145.07:29:19.63$setupk4/pcalon 2006.145.07:29:19.63$pcalon/"no phase cal control is implemented here 2006.145.07:29:19.63$setupk4/"tpicd=stop 2006.145.07:29:19.63$setupk4/"rec=synch_on 2006.145.07:29:19.63$setupk4/"rec_mode=128 2006.145.07:29:19.63$setupk4/!* 2006.145.07:29:19.63$setupk4/recpk4 2006.145.07:29:19.63$recpk4/recpatch= 2006.145.07:29:19.64$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.07:29:19.64$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.07:29:19.64$setupk4/vck44 2006.145.07:29:19.64$vck44/valo=1,524.99 2006.145.07:29:19.64#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.07:29:19.64#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.07:29:19.64#ibcon#ireg 17 cls_cnt 0 2006.145.07:29:19.64#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:29:19.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:29:19.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:29:19.67#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.07:29:19.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:29:19.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:29:19.73#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.07:29:19.73#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.07:29:19.73$vck44/va=1,8 2006.145.07:29:19.73#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.07:29:19.73#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.07:29:19.73#ibcon#ireg 11 cls_cnt 2 2006.145.07:29:19.73#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:29:19.73#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:29:19.73#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:29:19.75#ibcon#[25=AT01-08\r\n] 2006.145.07:29:19.78#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:29:19.78#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:29:19.78#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.07:29:19.78#ibcon#ireg 7 cls_cnt 0 2006.145.07:29:19.78#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:29:19.92#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:29:19.92#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:29:19.93#ibcon#[25=USB\r\n] 2006.145.07:29:19.96#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:29:19.96#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:29:19.96#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.07:29:19.96#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.07:29:19.96$vck44/valo=2,534.99 2006.145.07:29:19.96#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.07:29:19.96#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.07:29:19.96#ibcon#ireg 17 cls_cnt 0 2006.145.07:29:19.96#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:29:19.96#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:29:19.96#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:29:19.99#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.07:29:20.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:29:20.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:29:20.03#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.07:29:20.03#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.07:29:20.03$vck44/va=2,7 2006.145.07:29:20.03#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.07:29:20.03#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.07:29:20.03#ibcon#ireg 11 cls_cnt 2 2006.145.07:29:20.03#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:29:20.09#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:29:20.09#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:29:20.11#ibcon#[25=AT02-07\r\n] 2006.145.07:29:20.14#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:29:20.14#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:29:20.14#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.07:29:20.14#ibcon#ireg 7 cls_cnt 0 2006.145.07:29:20.14#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:29:20.26#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:29:20.26#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:29:20.28#ibcon#[25=USB\r\n] 2006.145.07:29:20.31#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:29:20.31#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:29:20.31#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.07:29:20.31#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.07:29:20.31$vck44/valo=3,564.99 2006.145.07:29:20.31#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.07:29:20.31#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.07:29:20.31#ibcon#ireg 17 cls_cnt 0 2006.145.07:29:20.31#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:29:20.31#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:29:20.31#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:29:20.33#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.07:29:20.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:29:20.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:29:20.37#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.07:29:20.37#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.07:29:20.37$vck44/va=3,8 2006.145.07:29:20.37#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.07:29:20.37#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.07:29:20.37#ibcon#ireg 11 cls_cnt 2 2006.145.07:29:20.37#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:29:20.43#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:29:20.43#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:29:20.45#ibcon#[25=AT03-08\r\n] 2006.145.07:29:20.48#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:29:20.48#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:29:20.48#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.07:29:20.48#ibcon#ireg 7 cls_cnt 0 2006.145.07:29:20.48#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:29:20.60#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:29:20.60#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:29:20.62#ibcon#[25=USB\r\n] 2006.145.07:29:20.65#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:29:20.65#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:29:20.65#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.07:29:20.65#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.07:29:20.65$vck44/valo=4,624.99 2006.145.07:29:20.65#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.07:29:20.65#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.07:29:20.65#ibcon#ireg 17 cls_cnt 0 2006.145.07:29:20.65#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:29:20.65#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:29:20.65#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:29:20.67#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.07:29:20.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:29:20.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:29:20.71#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.07:29:20.71#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.07:29:20.71$vck44/va=4,7 2006.145.07:29:20.71#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.07:29:20.71#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.07:29:20.71#ibcon#ireg 11 cls_cnt 2 2006.145.07:29:20.71#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:29:20.77#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:29:20.77#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:29:20.79#ibcon#[25=AT04-07\r\n] 2006.145.07:29:20.82#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:29:20.82#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:29:20.82#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.07:29:20.82#ibcon#ireg 7 cls_cnt 0 2006.145.07:29:20.82#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:29:20.94#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:29:20.94#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:29:20.96#ibcon#[25=USB\r\n] 2006.145.07:29:20.99#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:29:20.99#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:29:20.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.07:29:20.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.07:29:20.99$vck44/valo=5,734.99 2006.145.07:29:20.99#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.07:29:20.99#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.07:29:20.99#ibcon#ireg 17 cls_cnt 0 2006.145.07:29:20.99#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:29:20.99#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:29:20.99#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:29:21.01#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.07:29:21.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:29:21.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:29:21.05#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.07:29:21.05#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.07:29:21.05$vck44/va=5,4 2006.145.07:29:21.05#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.07:29:21.05#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.07:29:21.05#ibcon#ireg 11 cls_cnt 2 2006.145.07:29:21.05#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:29:21.11#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:29:21.11#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:29:21.13#ibcon#[25=AT05-04\r\n] 2006.145.07:29:21.16#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:29:21.16#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:29:21.16#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.07:29:21.16#ibcon#ireg 7 cls_cnt 0 2006.145.07:29:21.16#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:29:21.28#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:29:21.28#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:29:21.30#ibcon#[25=USB\r\n] 2006.145.07:29:21.33#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:29:21.33#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:29:21.33#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.07:29:21.33#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.07:29:21.33$vck44/valo=6,814.99 2006.145.07:29:21.33#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.07:29:21.33#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.07:29:21.33#ibcon#ireg 17 cls_cnt 0 2006.145.07:29:21.33#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:29:21.33#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:29:21.33#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:29:21.36#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.07:29:21.40#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:29:21.40#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:29:21.40#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.07:29:21.40#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.07:29:21.40$vck44/va=6,4 2006.145.07:29:21.40#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.07:29:21.40#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.07:29:21.40#ibcon#ireg 11 cls_cnt 2 2006.145.07:29:21.40#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:29:21.45#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:29:21.45#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:29:21.47#ibcon#[25=AT06-04\r\n] 2006.145.07:29:21.50#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:29:21.50#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:29:21.50#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.07:29:21.50#ibcon#ireg 7 cls_cnt 0 2006.145.07:29:21.50#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:29:21.62#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:29:21.62#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:29:21.64#ibcon#[25=USB\r\n] 2006.145.07:29:21.67#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:29:21.67#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:29:21.67#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.07:29:21.67#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.07:29:21.67$vck44/valo=7,864.99 2006.145.07:29:21.67#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.07:29:21.67#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.07:29:21.67#ibcon#ireg 17 cls_cnt 0 2006.145.07:29:21.67#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:29:21.67#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:29:21.67#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:29:21.69#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.07:29:21.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:29:21.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:29:21.73#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.07:29:21.73#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.07:29:21.73$vck44/va=7,4 2006.145.07:29:21.73#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.07:29:21.73#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.07:29:21.73#ibcon#ireg 11 cls_cnt 2 2006.145.07:29:21.73#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:29:21.79#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:29:21.79#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:29:21.81#ibcon#[25=AT07-04\r\n] 2006.145.07:29:21.84#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:29:21.84#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:29:21.84#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.07:29:21.84#ibcon#ireg 7 cls_cnt 0 2006.145.07:29:21.84#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:29:21.96#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:29:21.96#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:29:21.98#ibcon#[25=USB\r\n] 2006.145.07:29:22.01#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:29:22.01#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:29:22.01#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.07:29:22.01#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.07:29:22.01$vck44/valo=8,884.99 2006.145.07:29:22.01#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.07:29:22.01#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.07:29:22.01#ibcon#ireg 17 cls_cnt 0 2006.145.07:29:22.01#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:29:22.01#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:29:22.01#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:29:22.03#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.07:29:22.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:29:22.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:29:22.07#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.07:29:22.07#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.07:29:22.07$vck44/va=8,4 2006.145.07:29:22.07#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.07:29:22.07#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.07:29:22.07#ibcon#ireg 11 cls_cnt 2 2006.145.07:29:22.07#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:29:22.13#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:29:22.13#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:29:22.15#ibcon#[25=AT08-04\r\n] 2006.145.07:29:22.18#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:29:22.18#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:29:22.18#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.07:29:22.18#ibcon#ireg 7 cls_cnt 0 2006.145.07:29:22.18#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:29:22.30#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:29:22.30#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:29:22.32#ibcon#[25=USB\r\n] 2006.145.07:29:22.35#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:29:22.35#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:29:22.35#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.07:29:22.35#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.07:29:22.35$vck44/vblo=1,629.99 2006.145.07:29:22.35#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.07:29:22.35#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.07:29:22.35#ibcon#ireg 17 cls_cnt 0 2006.145.07:29:22.35#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:29:22.35#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:29:22.35#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:29:22.37#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.07:29:22.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:29:22.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:29:22.41#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.07:29:22.41#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.07:29:22.41$vck44/vb=1,3 2006.145.07:29:22.41#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.07:29:22.41#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.07:29:22.41#ibcon#ireg 11 cls_cnt 2 2006.145.07:29:22.41#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:29:22.41#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:29:22.41#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:29:22.43#ibcon#[27=AT01-03\r\n] 2006.145.07:29:22.46#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:29:22.46#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:29:22.46#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.07:29:22.46#ibcon#ireg 7 cls_cnt 0 2006.145.07:29:22.46#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:29:22.58#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:29:22.58#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:29:22.60#ibcon#[27=USB\r\n] 2006.145.07:29:22.63#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:29:22.63#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:29:22.63#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.07:29:22.63#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.07:29:22.63$vck44/vblo=2,634.99 2006.145.07:29:22.63#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.07:29:22.63#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.07:29:22.63#ibcon#ireg 17 cls_cnt 0 2006.145.07:29:22.63#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:29:22.63#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:29:22.63#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:29:22.66#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.07:29:22.70#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:29:22.70#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:29:22.70#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.07:29:22.70#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.07:29:22.70$vck44/vb=2,4 2006.145.07:29:22.70#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.07:29:22.70#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.07:29:22.70#ibcon#ireg 11 cls_cnt 2 2006.145.07:29:22.70#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:29:22.75#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:29:22.75#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:29:22.77#ibcon#[27=AT02-04\r\n] 2006.145.07:29:22.80#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:29:22.80#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:29:22.80#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.07:29:22.80#ibcon#ireg 7 cls_cnt 0 2006.145.07:29:22.80#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:29:22.92#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:29:22.92#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:29:22.94#ibcon#[27=USB\r\n] 2006.145.07:29:22.97#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:29:22.97#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:29:22.97#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.07:29:22.97#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.07:29:22.97$vck44/vblo=3,649.99 2006.145.07:29:22.97#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.07:29:22.97#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.07:29:22.97#ibcon#ireg 17 cls_cnt 0 2006.145.07:29:22.97#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:29:22.97#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:29:22.97#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:29:22.99#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.07:29:23.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:29:23.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:29:23.03#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.07:29:23.03#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.07:29:23.03$vck44/vb=3,4 2006.145.07:29:23.03#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.07:29:23.03#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.07:29:23.03#ibcon#ireg 11 cls_cnt 2 2006.145.07:29:23.03#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:29:23.09#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:29:23.09#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:29:23.11#ibcon#[27=AT03-04\r\n] 2006.145.07:29:23.14#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:29:23.14#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:29:23.14#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.07:29:23.14#ibcon#ireg 7 cls_cnt 0 2006.145.07:29:23.14#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:29:23.26#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:29:23.26#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:29:23.28#ibcon#[27=USB\r\n] 2006.145.07:29:23.31#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:29:23.31#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:29:23.31#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.07:29:23.31#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.07:29:23.31$vck44/vblo=4,679.99 2006.145.07:29:23.31#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.07:29:23.31#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.07:29:23.31#ibcon#ireg 17 cls_cnt 0 2006.145.07:29:23.31#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:29:23.31#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:29:23.31#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:29:23.33#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.07:29:23.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:29:23.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:29:23.37#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.07:29:23.37#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.07:29:23.37$vck44/vb=4,4 2006.145.07:29:23.37#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.07:29:23.37#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.07:29:23.37#ibcon#ireg 11 cls_cnt 2 2006.145.07:29:23.37#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:29:23.43#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:29:23.43#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:29:23.45#ibcon#[27=AT04-04\r\n] 2006.145.07:29:23.48#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:29:23.48#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:29:23.48#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.07:29:23.48#ibcon#ireg 7 cls_cnt 0 2006.145.07:29:23.48#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:29:23.60#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:29:23.60#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:29:23.62#ibcon#[27=USB\r\n] 2006.145.07:29:23.65#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:29:23.65#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:29:23.65#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.07:29:23.65#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.07:29:23.65$vck44/vblo=5,709.99 2006.145.07:29:23.65#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.07:29:23.65#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.07:29:23.65#ibcon#ireg 17 cls_cnt 0 2006.145.07:29:23.65#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:29:23.65#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:29:23.65#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:29:23.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.07:29:23.72#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:29:23.72#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:29:23.72#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.07:29:23.72#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.07:29:23.72$vck44/vb=5,4 2006.145.07:29:23.72#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.07:29:23.72#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.07:29:23.72#ibcon#ireg 11 cls_cnt 2 2006.145.07:29:23.72#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:29:23.77#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:29:23.77#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:29:23.79#abcon#<5=/04 4.7 7.9 19.30 641017.1\r\n> 2006.145.07:29:23.79#ibcon#[27=AT05-04\r\n] 2006.145.07:29:23.81#abcon#{5=INTERFACE CLEAR} 2006.145.07:29:23.82#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:29:23.82#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:29:23.82#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.07:29:23.82#ibcon#ireg 7 cls_cnt 0 2006.145.07:29:23.82#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:29:23.87#abcon#[5=S1D000X0/0*\r\n] 2006.145.07:29:23.94#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:29:23.94#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:29:23.96#ibcon#[27=USB\r\n] 2006.145.07:29:23.99#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:29:23.99#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:29:23.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.07:29:23.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.07:29:23.99$vck44/vblo=6,719.99 2006.145.07:29:23.99#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.07:29:23.99#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.07:29:23.99#ibcon#ireg 17 cls_cnt 0 2006.145.07:29:23.99#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:29:23.99#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:29:23.99#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:29:24.01#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.07:29:24.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:29:24.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:29:24.05#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.07:29:24.05#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.07:29:24.05$vck44/vb=6,4 2006.145.07:29:24.05#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.07:29:24.05#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.07:29:24.05#ibcon#ireg 11 cls_cnt 2 2006.145.07:29:24.05#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:29:24.11#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:29:24.11#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:29:24.13#ibcon#[27=AT06-04\r\n] 2006.145.07:29:24.16#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:29:24.16#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:29:24.16#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.07:29:24.16#ibcon#ireg 7 cls_cnt 0 2006.145.07:29:24.16#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:29:24.28#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:29:24.28#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:29:24.30#ibcon#[27=USB\r\n] 2006.145.07:29:24.33#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:29:24.33#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:29:24.33#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.07:29:24.33#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.07:29:24.33$vck44/vblo=7,734.99 2006.145.07:29:24.33#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.07:29:24.33#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.07:29:24.33#ibcon#ireg 17 cls_cnt 0 2006.145.07:29:24.33#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:29:24.33#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:29:24.33#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:29:24.35#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.07:29:24.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:29:24.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:29:24.39#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.07:29:24.39#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.07:29:24.39$vck44/vb=7,4 2006.145.07:29:24.39#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.07:29:24.39#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.07:29:24.39#ibcon#ireg 11 cls_cnt 2 2006.145.07:29:24.39#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:29:24.45#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:29:24.45#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:29:24.47#ibcon#[27=AT07-04\r\n] 2006.145.07:29:24.50#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:29:24.50#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:29:24.50#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.07:29:24.50#ibcon#ireg 7 cls_cnt 0 2006.145.07:29:24.50#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:29:24.62#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:29:24.62#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:29:24.64#ibcon#[27=USB\r\n] 2006.145.07:29:24.67#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:29:24.67#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:29:24.67#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.07:29:24.67#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.07:29:24.67$vck44/vblo=8,744.99 2006.145.07:29:24.67#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.07:29:24.67#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.07:29:24.67#ibcon#ireg 17 cls_cnt 0 2006.145.07:29:24.67#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:29:24.67#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:29:24.67#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:29:24.69#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.07:29:24.73#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:29:24.73#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:29:24.73#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.07:29:24.73#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.07:29:24.73$vck44/vb=8,4 2006.145.07:29:24.73#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.07:29:24.73#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.07:29:24.73#ibcon#ireg 11 cls_cnt 2 2006.145.07:29:24.73#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:29:24.79#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:29:24.79#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:29:24.81#ibcon#[27=AT08-04\r\n] 2006.145.07:29:24.84#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:29:24.84#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:29:24.84#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.07:29:24.84#ibcon#ireg 7 cls_cnt 0 2006.145.07:29:24.84#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:29:24.96#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:29:24.96#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:29:24.98#ibcon#[27=USB\r\n] 2006.145.07:29:25.01#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:29:25.01#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:29:25.01#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.07:29:25.01#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.07:29:25.01$vck44/vabw=wide 2006.145.07:29:25.01#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.07:29:25.01#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.07:29:25.01#ibcon#ireg 8 cls_cnt 0 2006.145.07:29:25.01#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:29:25.01#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:29:25.01#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:29:25.03#ibcon#[25=BW32\r\n] 2006.145.07:29:25.06#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:29:25.06#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:29:25.06#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.07:29:25.06#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.07:29:25.06$vck44/vbbw=wide 2006.145.07:29:25.06#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.07:29:25.06#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.07:29:25.06#ibcon#ireg 8 cls_cnt 0 2006.145.07:29:25.06#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.07:29:25.13#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.07:29:25.13#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.07:29:25.15#ibcon#[27=BW32\r\n] 2006.145.07:29:25.18#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.07:29:25.18#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.07:29:25.18#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.07:29:25.18#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.07:29:25.18$setupk4/ifdk4 2006.145.07:29:25.18$ifdk4/lo= 2006.145.07:29:25.18$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.07:29:25.18$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.07:29:25.18$ifdk4/patch= 2006.145.07:29:25.18$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.07:29:25.18$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.07:29:25.18$setupk4/!*+20s 2006.145.07:29:33.96#abcon#<5=/04 4.7 7.9 19.29 651017.1\r\n> 2006.145.07:29:33.98#abcon#{5=INTERFACE CLEAR} 2006.145.07:29:34.06#abcon#[5=S1D000X0/0*\r\n] 2006.145.07:29:39.64$setupk4/"tpicd 2006.145.07:29:39.64$setupk4/echo=off 2006.145.07:29:39.64$setupk4/xlog=off 2006.145.07:29:39.64:!2006.145.07:33:36 2006.145.07:30:07.14#trakl#Source acquired 2006.145.07:30:09.14#flagr#flagr/antenna,acquired 2006.145.07:33:36.02:preob 2006.145.07:33:37.14/onsource/TRACKING 2006.145.07:33:37.14:!2006.145.07:33:46 2006.145.07:33:46.01:"tape 2006.145.07:33:46.02:"st=record 2006.145.07:33:46.02:data_valid=on 2006.145.07:33:46.02:midob 2006.145.07:33:47.14/onsource/TRACKING 2006.145.07:33:47.14/wx/19.23,1017.2,63 2006.145.07:33:47.21/cable/+6.5393E-03 2006.145.07:33:48.30/va/01,08,usb,yes,28,31 2006.145.07:33:48.30/va/02,07,usb,yes,30,31 2006.145.07:33:48.30/va/03,08,usb,yes,28,29 2006.145.07:33:48.30/va/04,07,usb,yes,31,33 2006.145.07:33:48.31/va/05,04,usb,yes,27,28 2006.145.07:33:48.31/va/06,04,usb,yes,31,31 2006.145.07:33:48.31/va/07,04,usb,yes,31,32 2006.145.07:33:48.31/va/08,04,usb,yes,26,32 2006.145.07:33:48.54/valo/01,524.99,yes,locked 2006.145.07:33:48.54/valo/02,534.99,yes,locked 2006.145.07:33:48.54/valo/03,564.99,yes,locked 2006.145.07:33:48.54/valo/04,624.99,yes,locked 2006.145.07:33:48.54/valo/05,734.99,yes,locked 2006.145.07:33:48.54/valo/06,814.99,yes,locked 2006.145.07:33:48.54/valo/07,864.99,yes,locked 2006.145.07:33:48.54/valo/08,884.99,yes,locked 2006.145.07:33:49.62/vb/01,03,usb,yes,36,34 2006.145.07:33:49.63/vb/02,04,usb,yes,31,31 2006.145.07:33:49.63/vb/03,04,usb,yes,28,31 2006.145.07:33:49.63/vb/04,04,usb,yes,33,32 2006.145.07:33:49.63/vb/05,04,usb,yes,25,28 2006.145.07:33:49.63/vb/06,04,usb,yes,30,26 2006.145.07:33:49.63/vb/07,04,usb,yes,30,29 2006.145.07:33:49.63/vb/08,04,usb,yes,27,30 2006.145.07:33:49.86/vblo/01,629.99,yes,locked 2006.145.07:33:49.86/vblo/02,634.99,yes,locked 2006.145.07:33:49.86/vblo/03,649.99,yes,locked 2006.145.07:33:49.86/vblo/04,679.99,yes,locked 2006.145.07:33:49.86/vblo/05,709.99,yes,locked 2006.145.07:33:49.86/vblo/06,719.99,yes,locked 2006.145.07:33:49.86/vblo/07,734.99,yes,locked 2006.145.07:33:49.86/vblo/08,744.99,yes,locked 2006.145.07:33:50.00/vabw/8 2006.145.07:33:50.15/vbbw/8 2006.145.07:33:50.25/xfe/off,on,14.7 2006.145.07:33:50.62/ifatt/23,28,28,28 2006.145.07:33:51.07/fmout-gps/S +5.5E-08 2006.145.07:33:51.12:!2006.145.07:35:16 2006.145.07:35:16.02:data_valid=off 2006.145.07:35:16.02:"et 2006.145.07:35:16.02:!+3s 2006.145.07:35:19.05:"tape 2006.145.07:35:19.06:postob 2006.145.07:35:19.17/cable/+6.5384E-03 2006.145.07:35:19.18/wx/19.19,1017.2,64 2006.145.07:35:19.23/fmout-gps/S +5.4E-08 2006.145.07:35:19.24:scan_name=145-0738,jd0605,50 2006.145.07:35:19.24:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.145.07:35:20.14#flagr#flagr/antenna,new-source 2006.145.07:35:20.14:checkk5 2006.145.07:35:20.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.07:35:21.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.07:35:21.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.07:35:21.88/chk_autoobs//k5ts4/ autoobs is running! 2006.145.07:35:22.31/chk_obsdata//k5ts1/T1450733??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.07:35:22.75/chk_obsdata//k5ts2/T1450733??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.07:35:23.19/chk_obsdata//k5ts3/T1450733??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.07:35:23.64/chk_obsdata//k5ts4/T1450733??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.07:35:24.40/k5log//k5ts1_log_newline 2006.145.07:35:25.13/k5log//k5ts2_log_newline 2006.145.07:35:25.86/k5log//k5ts3_log_newline 2006.145.07:35:26.61/k5log//k5ts4_log_newline 2006.145.07:35:26.63/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.07:35:26.63:setupk4=1 2006.145.07:35:26.63$setupk4/echo=on 2006.145.07:35:26.63$setupk4/pcalon 2006.145.07:35:26.63$pcalon/"no phase cal control is implemented here 2006.145.07:35:26.63$setupk4/"tpicd=stop 2006.145.07:35:26.63$setupk4/"rec=synch_on 2006.145.07:35:26.63$setupk4/"rec_mode=128 2006.145.07:35:26.63$setupk4/!* 2006.145.07:35:26.63$setupk4/recpk4 2006.145.07:35:26.63$recpk4/recpatch= 2006.145.07:35:26.64$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.07:35:26.64$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.07:35:26.64$setupk4/vck44 2006.145.07:35:26.64$vck44/valo=1,524.99 2006.145.07:35:26.64#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.07:35:26.64#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.07:35:26.64#ibcon#ireg 17 cls_cnt 0 2006.145.07:35:26.64#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.07:35:26.64#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.07:35:26.64#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.07:35:26.67#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.07:35:26.72#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.07:35:26.72#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.07:35:26.72#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.07:35:26.72#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.07:35:26.72$vck44/va=1,8 2006.145.07:35:26.72#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.07:35:26.72#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.07:35:26.72#ibcon#ireg 11 cls_cnt 2 2006.145.07:35:26.72#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.07:35:26.72#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.07:35:26.72#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.07:35:26.74#ibcon#[25=AT01-08\r\n] 2006.145.07:35:26.77#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.07:35:26.77#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.07:35:26.77#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.07:35:26.77#ibcon#ireg 7 cls_cnt 0 2006.145.07:35:26.77#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.07:35:26.90#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.07:35:26.90#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.07:35:26.92#ibcon#[25=USB\r\n] 2006.145.07:35:26.94#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.07:35:26.94#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.07:35:26.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.07:35:26.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.07:35:26.94$vck44/valo=2,534.99 2006.145.07:35:26.94#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.07:35:26.94#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.07:35:26.94#ibcon#ireg 17 cls_cnt 0 2006.145.07:35:26.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.07:35:26.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.07:35:26.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.07:35:26.98#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.07:35:27.01#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.07:35:27.01#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.07:35:27.01#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.07:35:27.01#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.07:35:27.01$vck44/va=2,7 2006.145.07:35:27.01#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.07:35:27.01#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.07:35:27.01#ibcon#ireg 11 cls_cnt 2 2006.145.07:35:27.01#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.07:35:27.06#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.07:35:27.06#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.07:35:27.08#ibcon#[25=AT02-07\r\n] 2006.145.07:35:27.11#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.07:35:27.11#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.07:35:27.11#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.07:35:27.11#ibcon#ireg 7 cls_cnt 0 2006.145.07:35:27.11#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.07:35:27.23#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.07:35:27.23#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.07:35:27.25#ibcon#[25=USB\r\n] 2006.145.07:35:27.28#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.07:35:27.28#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.07:35:27.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.07:35:27.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.07:35:27.28$vck44/valo=3,564.99 2006.145.07:35:27.28#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.07:35:27.28#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.07:35:27.28#ibcon#ireg 17 cls_cnt 0 2006.145.07:35:27.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.07:35:27.28#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.07:35:27.28#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.07:35:27.30#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.07:35:27.34#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.07:35:27.34#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.07:35:27.34#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.07:35:27.34#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.07:35:27.34$vck44/va=3,8 2006.145.07:35:27.34#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.07:35:27.34#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.07:35:27.34#ibcon#ireg 11 cls_cnt 2 2006.145.07:35:27.34#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.07:35:27.40#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.07:35:27.40#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.07:35:27.42#ibcon#[25=AT03-08\r\n] 2006.145.07:35:27.45#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.07:35:27.45#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.07:35:27.45#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.07:35:27.45#ibcon#ireg 7 cls_cnt 0 2006.145.07:35:27.45#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.07:35:27.57#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.07:35:27.57#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.07:35:27.59#ibcon#[25=USB\r\n] 2006.145.07:35:27.62#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.07:35:27.62#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.07:35:27.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.07:35:27.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.07:35:27.62$vck44/valo=4,624.99 2006.145.07:35:27.62#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.07:35:27.62#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.07:35:27.62#ibcon#ireg 17 cls_cnt 0 2006.145.07:35:27.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.07:35:27.62#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.07:35:27.63#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.07:35:27.64#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.07:35:27.68#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.07:35:27.68#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.07:35:27.68#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.07:35:27.68#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.07:35:27.68$vck44/va=4,7 2006.145.07:35:27.68#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.07:35:27.68#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.07:35:27.68#ibcon#ireg 11 cls_cnt 2 2006.145.07:35:27.68#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.07:35:27.74#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.07:35:27.74#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.07:35:27.76#ibcon#[25=AT04-07\r\n] 2006.145.07:35:27.79#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.07:35:27.79#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.07:35:27.79#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.07:35:27.79#ibcon#ireg 7 cls_cnt 0 2006.145.07:35:27.79#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.07:35:27.91#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.07:35:27.91#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.07:35:27.93#ibcon#[25=USB\r\n] 2006.145.07:35:27.96#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.07:35:27.96#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.07:35:27.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.07:35:27.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.07:35:27.96$vck44/valo=5,734.99 2006.145.07:35:27.96#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.07:35:27.96#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.07:35:27.96#ibcon#ireg 17 cls_cnt 0 2006.145.07:35:27.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.07:35:27.96#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.07:35:27.96#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.07:35:27.98#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.07:35:28.02#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.07:35:28.02#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.07:35:28.02#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.07:35:28.02#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.07:35:28.02$vck44/va=5,4 2006.145.07:35:28.02#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.07:35:28.02#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.07:35:28.02#ibcon#ireg 11 cls_cnt 2 2006.145.07:35:28.02#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.07:35:28.09#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.07:35:28.09#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.07:35:28.10#ibcon#[25=AT05-04\r\n] 2006.145.07:35:28.13#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.07:35:28.13#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.07:35:28.13#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.07:35:28.13#ibcon#ireg 7 cls_cnt 0 2006.145.07:35:28.13#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.07:35:28.26#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.07:35:28.26#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.07:35:28.27#ibcon#[25=USB\r\n] 2006.145.07:35:28.30#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.07:35:28.31#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.07:35:28.31#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.07:35:28.31#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.07:35:28.31$vck44/valo=6,814.99 2006.145.07:35:28.31#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.07:35:28.31#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.07:35:28.31#ibcon#ireg 17 cls_cnt 0 2006.145.07:35:28.31#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.07:35:28.31#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.07:35:28.31#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.07:35:28.32#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.07:35:28.36#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.07:35:28.36#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.07:35:28.36#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.07:35:28.36#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.07:35:28.36$vck44/va=6,4 2006.145.07:35:28.36#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.07:35:28.36#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.07:35:28.36#ibcon#ireg 11 cls_cnt 2 2006.145.07:35:28.36#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.07:35:28.43#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.07:35:28.43#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.07:35:28.45#ibcon#[25=AT06-04\r\n] 2006.145.07:35:28.48#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.07:35:28.48#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.07:35:28.48#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.07:35:28.48#ibcon#ireg 7 cls_cnt 0 2006.145.07:35:28.48#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.07:35:28.60#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.07:35:28.60#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.07:35:28.62#ibcon#[25=USB\r\n] 2006.145.07:35:28.65#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.07:35:28.65#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.07:35:28.65#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.07:35:28.65#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.07:35:28.65$vck44/valo=7,864.99 2006.145.07:35:28.65#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.07:35:28.65#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.07:35:28.65#ibcon#ireg 17 cls_cnt 0 2006.145.07:35:28.65#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.07:35:28.65#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.07:35:28.65#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.07:35:28.67#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.07:35:28.71#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.07:35:28.71#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.07:35:28.71#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.07:35:28.71#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.07:35:28.71$vck44/va=7,4 2006.145.07:35:28.71#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.07:35:28.71#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.07:35:28.71#ibcon#ireg 11 cls_cnt 2 2006.145.07:35:28.71#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.07:35:28.77#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.07:35:28.77#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.07:35:28.79#ibcon#[25=AT07-04\r\n] 2006.145.07:35:28.82#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.07:35:28.82#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.07:35:28.82#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.07:35:28.82#ibcon#ireg 7 cls_cnt 0 2006.145.07:35:28.82#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.07:35:28.94#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.07:35:28.94#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.07:35:28.96#ibcon#[25=USB\r\n] 2006.145.07:35:28.99#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.07:35:28.99#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.07:35:28.99#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.07:35:28.99#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.07:35:28.99$vck44/valo=8,884.99 2006.145.07:35:28.99#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.07:35:28.99#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.07:35:28.99#ibcon#ireg 17 cls_cnt 0 2006.145.07:35:28.99#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.07:35:28.99#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.07:35:28.99#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.07:35:29.01#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.07:35:29.05#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.07:35:29.05#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.07:35:29.05#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.07:35:29.05#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.07:35:29.05$vck44/va=8,4 2006.145.07:35:29.05#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.07:35:29.05#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.07:35:29.05#ibcon#ireg 11 cls_cnt 2 2006.145.07:35:29.05#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.07:35:29.11#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.07:35:29.11#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.07:35:29.13#ibcon#[25=AT08-04\r\n] 2006.145.07:35:29.16#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.07:35:29.16#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.07:35:29.16#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.07:35:29.16#ibcon#ireg 7 cls_cnt 0 2006.145.07:35:29.16#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.07:35:29.28#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.07:35:29.28#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.07:35:29.31#ibcon#[25=USB\r\n] 2006.145.07:35:29.34#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.07:35:29.34#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.07:35:29.34#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.07:35:29.34#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.07:35:29.34$vck44/vblo=1,629.99 2006.145.07:35:29.34#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.07:35:29.34#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.07:35:29.34#ibcon#ireg 17 cls_cnt 0 2006.145.07:35:29.34#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.07:35:29.34#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.07:35:29.34#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.07:35:29.35#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.07:35:29.40#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.07:35:29.40#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.07:35:29.40#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.07:35:29.40#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.07:35:29.40$vck44/vb=1,3 2006.145.07:35:29.40#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.07:35:29.40#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.07:35:29.40#ibcon#ireg 11 cls_cnt 2 2006.145.07:35:29.40#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.07:35:29.40#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.07:35:29.40#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.07:35:29.42#ibcon#[27=AT01-03\r\n] 2006.145.07:35:29.45#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.07:35:29.45#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.07:35:29.45#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.07:35:29.45#ibcon#ireg 7 cls_cnt 0 2006.145.07:35:29.45#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.07:35:29.57#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.07:35:29.57#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.07:35:29.59#ibcon#[27=USB\r\n] 2006.145.07:35:29.62#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.07:35:29.62#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.07:35:29.62#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.07:35:29.62#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.07:35:29.62$vck44/vblo=2,634.99 2006.145.07:35:29.62#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.07:35:29.62#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.07:35:29.62#ibcon#ireg 17 cls_cnt 0 2006.145.07:35:29.62#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.07:35:29.62#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.07:35:29.62#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.07:35:29.64#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.07:35:29.68#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.07:35:29.68#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.07:35:29.68#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.07:35:29.68#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.07:35:29.68$vck44/vb=2,4 2006.145.07:35:29.68#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.07:35:29.68#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.07:35:29.68#ibcon#ireg 11 cls_cnt 2 2006.145.07:35:29.68#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.07:35:29.74#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.07:35:29.74#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.07:35:29.76#ibcon#[27=AT02-04\r\n] 2006.145.07:35:29.79#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.07:35:29.79#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.07:35:29.79#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.07:35:29.79#ibcon#ireg 7 cls_cnt 0 2006.145.07:35:29.79#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.07:35:29.91#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.07:35:29.91#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.07:35:29.92#abcon#<5=/04 5.1 8.9 19.19 641017.2\r\n> 2006.145.07:35:29.93#ibcon#[27=USB\r\n] 2006.145.07:35:29.94#abcon#{5=INTERFACE CLEAR} 2006.145.07:35:29.96#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.07:35:29.96#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.07:35:29.96#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.07:35:29.96#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.07:35:29.96$vck44/vblo=3,649.99 2006.145.07:35:29.96#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.07:35:29.96#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.07:35:29.96#ibcon#ireg 17 cls_cnt 0 2006.145.07:35:29.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.07:35:29.96#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.07:35:29.96#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.07:35:29.98#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.07:35:30.00#abcon#[5=S1D000X0/0*\r\n] 2006.145.07:35:30.02#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.07:35:30.02#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.07:35:30.02#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.07:35:30.02#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.07:35:30.02$vck44/vb=3,4 2006.145.07:35:30.02#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.07:35:30.02#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.07:35:30.02#ibcon#ireg 11 cls_cnt 2 2006.145.07:35:30.02#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.07:35:30.08#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.07:35:30.08#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.07:35:30.10#ibcon#[27=AT03-04\r\n] 2006.145.07:35:30.13#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.07:35:30.13#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.07:35:30.13#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.07:35:30.13#ibcon#ireg 7 cls_cnt 0 2006.145.07:35:30.13#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.07:35:30.25#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.07:35:30.25#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.07:35:30.27#ibcon#[27=USB\r\n] 2006.145.07:35:30.30#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.07:35:30.30#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.07:35:30.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.07:35:30.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.07:35:30.30$vck44/vblo=4,679.99 2006.145.07:35:30.30#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.07:35:30.30#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.07:35:30.30#ibcon#ireg 17 cls_cnt 0 2006.145.07:35:30.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.07:35:30.30#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.07:35:30.30#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.07:35:30.32#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.07:35:30.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.07:35:30.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.07:35:30.36#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.07:35:30.36#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.07:35:30.36$vck44/vb=4,4 2006.145.07:35:30.36#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.07:35:30.36#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.07:35:30.36#ibcon#ireg 11 cls_cnt 2 2006.145.07:35:30.36#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.07:35:30.42#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.07:35:30.42#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.07:35:30.44#ibcon#[27=AT04-04\r\n] 2006.145.07:35:30.47#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.07:35:30.47#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.07:35:30.47#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.07:35:30.47#ibcon#ireg 7 cls_cnt 0 2006.145.07:35:30.47#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.07:35:30.59#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.07:35:30.59#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.07:35:30.61#ibcon#[27=USB\r\n] 2006.145.07:35:30.64#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.07:35:30.64#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.07:35:30.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.07:35:30.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.07:35:30.64$vck44/vblo=5,709.99 2006.145.07:35:30.64#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.07:35:30.64#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.07:35:30.64#ibcon#ireg 17 cls_cnt 0 2006.145.07:35:30.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.07:35:30.64#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.07:35:30.64#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.07:35:30.66#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.07:35:30.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.07:35:30.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.07:35:30.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.07:35:30.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.07:35:30.70$vck44/vb=5,4 2006.145.07:35:30.70#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.07:35:30.70#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.07:35:30.70#ibcon#ireg 11 cls_cnt 2 2006.145.07:35:30.70#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.07:35:30.76#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.07:35:30.76#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.07:35:30.78#ibcon#[27=AT05-04\r\n] 2006.145.07:35:30.81#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.07:35:30.81#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.07:35:30.81#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.07:35:30.81#ibcon#ireg 7 cls_cnt 0 2006.145.07:35:30.81#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.07:35:30.93#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.07:35:30.93#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.07:35:30.95#ibcon#[27=USB\r\n] 2006.145.07:35:30.98#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.07:35:30.98#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.07:35:30.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.07:35:30.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.07:35:30.98$vck44/vblo=6,719.99 2006.145.07:35:30.98#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.07:35:30.98#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.07:35:30.98#ibcon#ireg 17 cls_cnt 0 2006.145.07:35:30.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.07:35:30.98#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.07:35:30.98#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.07:35:31.00#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.07:35:31.04#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.07:35:31.04#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.07:35:31.04#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.07:35:31.04#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.07:35:31.04$vck44/vb=6,4 2006.145.07:35:31.04#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.07:35:31.04#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.07:35:31.04#ibcon#ireg 11 cls_cnt 2 2006.145.07:35:31.04#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.07:35:31.10#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.07:35:31.10#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.07:35:31.12#ibcon#[27=AT06-04\r\n] 2006.145.07:35:31.15#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.07:35:31.15#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.07:35:31.15#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.07:35:31.15#ibcon#ireg 7 cls_cnt 0 2006.145.07:35:31.15#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.07:35:31.27#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.07:35:31.27#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.07:35:31.29#ibcon#[27=USB\r\n] 2006.145.07:35:31.32#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.07:35:31.32#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.07:35:31.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.07:35:31.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.07:35:31.32$vck44/vblo=7,734.99 2006.145.07:35:31.32#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.07:35:31.32#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.07:35:31.32#ibcon#ireg 17 cls_cnt 0 2006.145.07:35:31.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.07:35:31.32#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.07:35:31.32#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.07:35:31.34#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.07:35:31.38#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.07:35:31.38#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.07:35:31.38#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.07:35:31.38#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.07:35:31.38$vck44/vb=7,4 2006.145.07:35:31.38#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.07:35:31.38#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.07:35:31.38#ibcon#ireg 11 cls_cnt 2 2006.145.07:35:31.38#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.07:35:31.44#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.07:35:31.44#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.07:35:31.46#ibcon#[27=AT07-04\r\n] 2006.145.07:35:31.49#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.07:35:31.49#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.07:35:31.49#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.07:35:31.49#ibcon#ireg 7 cls_cnt 0 2006.145.07:35:31.49#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.07:35:31.61#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.07:35:31.61#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.07:35:31.63#ibcon#[27=USB\r\n] 2006.145.07:35:31.66#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.07:35:31.66#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.07:35:31.66#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.07:35:31.66#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.07:35:31.66$vck44/vblo=8,744.99 2006.145.07:35:31.66#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.07:35:31.66#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.07:35:31.66#ibcon#ireg 17 cls_cnt 0 2006.145.07:35:31.66#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.07:35:31.66#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.07:35:31.66#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.07:35:31.68#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.07:35:31.72#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.07:35:31.72#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.07:35:31.72#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.07:35:31.72#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.07:35:31.72$vck44/vb=8,4 2006.145.07:35:31.72#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.07:35:31.72#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.07:35:31.72#ibcon#ireg 11 cls_cnt 2 2006.145.07:35:31.72#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.07:35:31.78#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.07:35:31.78#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.07:35:31.80#ibcon#[27=AT08-04\r\n] 2006.145.07:35:31.83#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.07:35:31.83#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.07:35:31.83#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.07:35:31.83#ibcon#ireg 7 cls_cnt 0 2006.145.07:35:31.83#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.07:35:31.95#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.07:35:31.95#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.07:35:31.97#ibcon#[27=USB\r\n] 2006.145.07:35:32.00#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.07:35:32.00#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.07:35:32.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.07:35:32.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.07:35:32.00$vck44/vabw=wide 2006.145.07:35:32.00#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.07:35:32.00#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.07:35:32.00#ibcon#ireg 8 cls_cnt 0 2006.145.07:35:32.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.07:35:32.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.07:35:32.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.07:35:32.02#ibcon#[25=BW32\r\n] 2006.145.07:35:32.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.07:35:32.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.07:35:32.05#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.07:35:32.05#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.07:35:32.05$vck44/vbbw=wide 2006.145.07:35:32.05#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.07:35:32.05#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.07:35:32.05#ibcon#ireg 8 cls_cnt 0 2006.145.07:35:32.05#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:35:32.12#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:35:32.12#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:35:32.14#ibcon#[27=BW32\r\n] 2006.145.07:35:32.17#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:35:32.17#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:35:32.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.07:35:32.17#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.07:35:32.17$setupk4/ifdk4 2006.145.07:35:32.17$ifdk4/lo= 2006.145.07:35:32.18$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.07:35:32.18$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.07:35:32.18$ifdk4/patch= 2006.145.07:35:32.18$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.07:35:32.18$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.07:35:32.18$setupk4/!*+20s 2006.145.07:35:39.14#trakl#Source acquired 2006.145.07:35:39.15#flagr#flagr/antenna,acquired 2006.145.07:35:40.09#abcon#<5=/04 5.1 8.9 19.18 641017.2\r\n> 2006.145.07:35:40.11#abcon#{5=INTERFACE CLEAR} 2006.145.07:35:40.17#abcon#[5=S1D000X0/0*\r\n] 2006.145.07:35:46.65$setupk4/"tpicd 2006.145.07:35:46.65$setupk4/echo=off 2006.145.07:35:46.65$setupk4/xlog=off 2006.145.07:35:46.65:!2006.145.07:38:22 2006.145.07:38:22.00:preob 2006.145.07:38:22.14/onsource/TRACKING 2006.145.07:38:22.14:!2006.145.07:38:32 2006.145.07:38:32.00:"tape 2006.145.07:38:32.00:"st=record 2006.145.07:38:32.00:data_valid=on 2006.145.07:38:32.00:midob 2006.145.07:38:33.14/onsource/TRACKING 2006.145.07:38:33.14/wx/19.11,1017.2,65 2006.145.07:38:33.32/cable/+6.5390E-03 2006.145.07:38:34.41/va/01,08,usb,yes,28,30 2006.145.07:38:34.41/va/02,07,usb,yes,30,31 2006.145.07:38:34.41/va/03,08,usb,yes,27,29 2006.145.07:38:34.41/va/04,07,usb,yes,31,33 2006.145.07:38:34.41/va/05,04,usb,yes,27,28 2006.145.07:38:34.41/va/06,04,usb,yes,30,30 2006.145.07:38:34.41/va/07,04,usb,yes,31,32 2006.145.07:38:34.41/va/08,04,usb,yes,26,32 2006.145.07:38:34.64/valo/01,524.99,yes,locked 2006.145.07:38:34.64/valo/02,534.99,yes,locked 2006.145.07:38:34.64/valo/03,564.99,yes,locked 2006.145.07:38:34.64/valo/04,624.99,yes,locked 2006.145.07:38:34.64/valo/05,734.99,yes,locked 2006.145.07:38:34.64/valo/06,814.99,yes,locked 2006.145.07:38:34.64/valo/07,864.99,yes,locked 2006.145.07:38:34.64/valo/08,884.99,yes,locked 2006.145.07:38:35.73/vb/01,03,usb,yes,36,33 2006.145.07:38:35.73/vb/02,04,usb,yes,31,31 2006.145.07:38:35.73/vb/03,04,usb,yes,28,31 2006.145.07:38:35.73/vb/04,04,usb,yes,33,32 2006.145.07:38:35.73/vb/05,04,usb,yes,25,28 2006.145.07:38:35.73/vb/06,04,usb,yes,30,26 2006.145.07:38:35.73/vb/07,04,usb,yes,29,29 2006.145.07:38:35.73/vb/08,04,usb,yes,27,30 2006.145.07:38:35.96/vblo/01,629.99,yes,locked 2006.145.07:38:35.96/vblo/02,634.99,yes,locked 2006.145.07:38:35.96/vblo/03,649.99,yes,locked 2006.145.07:38:35.96/vblo/04,679.99,yes,locked 2006.145.07:38:35.96/vblo/05,709.99,yes,locked 2006.145.07:38:35.96/vblo/06,719.99,yes,locked 2006.145.07:38:35.96/vblo/07,734.99,yes,locked 2006.145.07:38:35.96/vblo/08,744.99,yes,locked 2006.145.07:38:36.11/vabw/8 2006.145.07:38:36.26/vbbw/8 2006.145.07:38:36.35/xfe/off,on,15.5 2006.145.07:38:36.74/ifatt/23,28,28,28 2006.145.07:38:37.07/fmout-gps/S +5.6E-08 2006.145.07:38:37.12:!2006.145.07:39:22 2006.145.07:39:22.01:data_valid=off 2006.145.07:39:22.02:"et 2006.145.07:39:22.02:!+3s 2006.145.07:39:25.05:"tape 2006.145.07:39:25.06:postob 2006.145.07:39:25.14/cable/+6.5414E-03 2006.145.07:39:25.15/wx/19.10,1017.2,66 2006.145.07:39:25.22/fmout-gps/S +5.5E-08 2006.145.07:39:25.23:scan_name=145-0741,jd0605,190 2006.145.07:39:25.23:source=0014+813,001708.47,813508.1,2000.0,neutral 2006.145.07:39:26.14#flagr#flagr/antenna,new-source 2006.145.07:39:26.15:checkk5 2006.145.07:39:26.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.07:39:27.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.07:39:27.45/chk_autoobs//k5ts3/ autoobs is running! 2006.145.07:39:27.87/chk_autoobs//k5ts4/ autoobs is running! 2006.145.07:39:28.30/chk_obsdata//k5ts1/T1450738??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.07:39:28.73/chk_obsdata//k5ts2/T1450738??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.07:39:29.17/chk_obsdata//k5ts3/T1450738??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.07:39:29.60/chk_obsdata//k5ts4/T1450738??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.07:39:30.35/k5log//k5ts1_log_newline 2006.145.07:39:31.09/k5log//k5ts2_log_newline 2006.145.07:39:31.85/k5log//k5ts3_log_newline 2006.145.07:39:32.59/k5log//k5ts4_log_newline 2006.145.07:39:32.61/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.07:39:32.61:setupk4=1 2006.145.07:39:32.61$setupk4/echo=on 2006.145.07:39:32.61$setupk4/pcalon 2006.145.07:39:32.61$pcalon/"no phase cal control is implemented here 2006.145.07:39:32.61$setupk4/"tpicd=stop 2006.145.07:39:32.61$setupk4/"rec=synch_on 2006.145.07:39:32.61$setupk4/"rec_mode=128 2006.145.07:39:32.61$setupk4/!* 2006.145.07:39:32.61$setupk4/recpk4 2006.145.07:39:32.61$recpk4/recpatch= 2006.145.07:39:32.62$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.07:39:32.62$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.07:39:32.62$setupk4/vck44 2006.145.07:39:32.62$vck44/valo=1,524.99 2006.145.07:39:32.62#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.07:39:32.62#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.07:39:32.62#ibcon#ireg 17 cls_cnt 0 2006.145.07:39:32.62#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.07:39:32.62#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.07:39:32.62#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.07:39:32.65#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.07:39:32.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.07:39:32.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.07:39:32.70#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.07:39:32.70#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.07:39:32.70$vck44/va=1,8 2006.145.07:39:32.70#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.07:39:32.70#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.07:39:32.70#ibcon#ireg 11 cls_cnt 2 2006.145.07:39:32.70#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.07:39:32.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.07:39:32.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.07:39:32.72#ibcon#[25=AT01-08\r\n] 2006.145.07:39:32.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.07:39:32.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.07:39:32.75#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.07:39:32.75#ibcon#ireg 7 cls_cnt 0 2006.145.07:39:32.75#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.07:39:32.88#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.07:39:32.88#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.07:39:32.89#ibcon#[25=USB\r\n] 2006.145.07:39:32.92#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.07:39:32.92#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.07:39:32.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.07:39:32.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.07:39:32.92$vck44/valo=2,534.99 2006.145.07:39:32.92#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.07:39:32.92#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.07:39:32.92#ibcon#ireg 17 cls_cnt 0 2006.145.07:39:32.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.07:39:32.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.07:39:32.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.07:39:32.95#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.07:39:32.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.07:39:32.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.07:39:32.99#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.07:39:32.99#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.07:39:32.99$vck44/va=2,7 2006.145.07:39:32.99#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.07:39:32.99#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.07:39:32.99#ibcon#ireg 11 cls_cnt 2 2006.145.07:39:32.99#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.07:39:33.04#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.07:39:33.04#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.07:39:33.06#ibcon#[25=AT02-07\r\n] 2006.145.07:39:33.09#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.07:39:33.09#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.07:39:33.09#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.07:39:33.09#ibcon#ireg 7 cls_cnt 0 2006.145.07:39:33.09#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.07:39:33.21#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.07:39:33.21#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.07:39:33.23#ibcon#[25=USB\r\n] 2006.145.07:39:33.26#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.07:39:33.26#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.07:39:33.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.07:39:33.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.07:39:33.26$vck44/valo=3,564.99 2006.145.07:39:33.26#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.07:39:33.26#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.07:39:33.26#ibcon#ireg 17 cls_cnt 0 2006.145.07:39:33.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.07:39:33.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.07:39:33.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.07:39:33.28#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.07:39:33.32#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.07:39:33.32#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.07:39:33.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.07:39:33.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.07:39:33.32$vck44/va=3,8 2006.145.07:39:33.32#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.07:39:33.32#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.07:39:33.32#ibcon#ireg 11 cls_cnt 2 2006.145.07:39:33.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.07:39:33.38#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.07:39:33.38#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.07:39:33.40#ibcon#[25=AT03-08\r\n] 2006.145.07:39:33.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.07:39:33.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.07:39:33.43#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.07:39:33.43#ibcon#ireg 7 cls_cnt 0 2006.145.07:39:33.43#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.07:39:33.55#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.07:39:33.55#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.07:39:33.57#ibcon#[25=USB\r\n] 2006.145.07:39:33.60#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.07:39:33.60#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.07:39:33.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.07:39:33.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.07:39:33.60$vck44/valo=4,624.99 2006.145.07:39:33.60#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.07:39:33.60#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.07:39:33.60#ibcon#ireg 17 cls_cnt 0 2006.145.07:39:33.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.07:39:33.60#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.07:39:33.60#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.07:39:33.62#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.07:39:33.66#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.07:39:33.66#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.07:39:33.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.07:39:33.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.07:39:33.66$vck44/va=4,7 2006.145.07:39:33.66#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.07:39:33.66#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.07:39:33.66#ibcon#ireg 11 cls_cnt 2 2006.145.07:39:33.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.07:39:33.72#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.07:39:33.72#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.07:39:33.74#ibcon#[25=AT04-07\r\n] 2006.145.07:39:33.77#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.07:39:33.77#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.07:39:33.77#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.07:39:33.77#ibcon#ireg 7 cls_cnt 0 2006.145.07:39:33.77#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.07:39:33.89#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.07:39:33.89#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.07:39:33.91#ibcon#[25=USB\r\n] 2006.145.07:39:33.94#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.07:39:33.94#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.07:39:33.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.07:39:33.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.07:39:33.94$vck44/valo=5,734.99 2006.145.07:39:33.94#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.07:39:33.94#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.07:39:33.94#ibcon#ireg 17 cls_cnt 0 2006.145.07:39:33.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:39:33.94#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:39:33.94#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:39:33.96#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.07:39:34.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:39:34.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:39:34.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.07:39:34.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.07:39:34.00$vck44/va=5,4 2006.145.07:39:34.00#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.07:39:34.00#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.07:39:34.00#ibcon#ireg 11 cls_cnt 2 2006.145.07:39:34.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.07:39:34.06#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.07:39:34.06#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.07:39:34.07#abcon#<5=/04 4.8 8.9 19.10 671017.2\r\n> 2006.145.07:39:34.08#ibcon#[25=AT05-04\r\n] 2006.145.07:39:34.09#abcon#{5=INTERFACE CLEAR} 2006.145.07:39:34.11#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.07:39:34.11#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.07:39:34.11#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.07:39:34.11#ibcon#ireg 7 cls_cnt 0 2006.145.07:39:34.11#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.07:39:34.15#abcon#[5=S1D000X0/0*\r\n] 2006.145.07:39:34.23#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.07:39:34.23#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.07:39:34.25#ibcon#[25=USB\r\n] 2006.145.07:39:34.28#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.07:39:34.28#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.07:39:34.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.07:39:34.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.07:39:34.28$vck44/valo=6,814.99 2006.145.07:39:34.28#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.07:39:34.28#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.07:39:34.28#ibcon#ireg 17 cls_cnt 0 2006.145.07:39:34.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.07:39:34.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.07:39:34.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.07:39:34.30#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.07:39:34.34#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.07:39:34.34#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.07:39:34.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.07:39:34.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.07:39:34.34$vck44/va=6,4 2006.145.07:39:34.34#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.07:39:34.34#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.07:39:34.34#ibcon#ireg 11 cls_cnt 2 2006.145.07:39:34.34#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.07:39:34.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.07:39:34.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.07:39:34.42#ibcon#[25=AT06-04\r\n] 2006.145.07:39:34.45#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.07:39:34.45#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.07:39:34.45#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.07:39:34.45#ibcon#ireg 7 cls_cnt 0 2006.145.07:39:34.45#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.07:39:34.57#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.07:39:34.57#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.07:39:34.59#ibcon#[25=USB\r\n] 2006.145.07:39:34.62#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.07:39:34.62#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.07:39:34.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.07:39:34.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.07:39:34.62$vck44/valo=7,864.99 2006.145.07:39:34.62#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.07:39:34.62#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.07:39:34.62#ibcon#ireg 17 cls_cnt 0 2006.145.07:39:34.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.07:39:34.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.07:39:34.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.07:39:34.64#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.07:39:34.68#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.07:39:34.68#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.07:39:34.68#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.07:39:34.68#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.07:39:34.68$vck44/va=7,4 2006.145.07:39:34.68#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.07:39:34.68#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.07:39:34.68#ibcon#ireg 11 cls_cnt 2 2006.145.07:39:34.68#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.07:39:34.74#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.07:39:34.74#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.07:39:34.76#ibcon#[25=AT07-04\r\n] 2006.145.07:39:34.79#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.07:39:34.79#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.07:39:34.79#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.07:39:34.79#ibcon#ireg 7 cls_cnt 0 2006.145.07:39:34.79#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.07:39:34.91#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.07:39:34.91#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.07:39:34.93#ibcon#[25=USB\r\n] 2006.145.07:39:34.96#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.07:39:34.96#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.07:39:34.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.07:39:34.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.07:39:34.96$vck44/valo=8,884.99 2006.145.07:39:34.96#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.07:39:34.96#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.07:39:34.96#ibcon#ireg 17 cls_cnt 0 2006.145.07:39:34.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.07:39:34.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.07:39:34.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.07:39:34.98#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.07:39:35.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.07:39:35.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.07:39:35.02#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.07:39:35.02#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.07:39:35.02$vck44/va=8,4 2006.145.07:39:35.02#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.07:39:35.02#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.07:39:35.02#ibcon#ireg 11 cls_cnt 2 2006.145.07:39:35.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.07:39:35.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.07:39:35.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.07:39:35.10#ibcon#[25=AT08-04\r\n] 2006.145.07:39:35.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.07:39:35.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.07:39:35.13#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.07:39:35.13#ibcon#ireg 7 cls_cnt 0 2006.145.07:39:35.13#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.07:39:35.25#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.07:39:35.25#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.07:39:35.27#ibcon#[25=USB\r\n] 2006.145.07:39:35.30#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.07:39:35.30#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.07:39:35.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.07:39:35.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.07:39:35.30$vck44/vblo=1,629.99 2006.145.07:39:35.30#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.07:39:35.30#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.07:39:35.30#ibcon#ireg 17 cls_cnt 0 2006.145.07:39:35.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.07:39:35.30#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.07:39:35.30#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.07:39:35.32#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.07:39:35.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.07:39:35.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.07:39:35.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.07:39:35.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.07:39:35.36$vck44/vb=1,3 2006.145.07:39:35.36#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.07:39:35.36#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.07:39:35.36#ibcon#ireg 11 cls_cnt 2 2006.145.07:39:35.36#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.07:39:35.36#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.07:39:35.36#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.07:39:35.38#ibcon#[27=AT01-03\r\n] 2006.145.07:39:35.41#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.07:39:35.41#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.07:39:35.41#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.07:39:35.41#ibcon#ireg 7 cls_cnt 0 2006.145.07:39:35.41#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.07:39:35.53#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.07:39:35.53#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.07:39:35.55#ibcon#[27=USB\r\n] 2006.145.07:39:35.58#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.07:39:35.58#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.07:39:35.58#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.07:39:35.58#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.07:39:35.58$vck44/vblo=2,634.99 2006.145.07:39:35.58#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.07:39:35.58#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.07:39:35.58#ibcon#ireg 17 cls_cnt 0 2006.145.07:39:35.58#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.07:39:35.58#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.07:39:35.58#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.07:39:35.60#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.07:39:35.64#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.07:39:35.64#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.07:39:35.64#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.07:39:35.64#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.07:39:35.64$vck44/vb=2,4 2006.145.07:39:35.64#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.07:39:35.64#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.07:39:35.64#ibcon#ireg 11 cls_cnt 2 2006.145.07:39:35.64#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.07:39:35.70#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.07:39:35.70#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.07:39:35.72#ibcon#[27=AT02-04\r\n] 2006.145.07:39:35.75#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.07:39:35.75#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.07:39:35.75#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.07:39:35.75#ibcon#ireg 7 cls_cnt 0 2006.145.07:39:35.75#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.07:39:35.87#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.07:39:35.87#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.07:39:35.89#ibcon#[27=USB\r\n] 2006.145.07:39:35.92#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.07:39:35.92#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.07:39:35.92#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.07:39:35.92#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.07:39:35.92$vck44/vblo=3,649.99 2006.145.07:39:35.92#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.07:39:35.92#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.07:39:35.92#ibcon#ireg 17 cls_cnt 0 2006.145.07:39:35.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.07:39:35.92#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.07:39:35.92#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.07:39:35.94#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.07:39:35.98#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.07:39:35.98#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.07:39:35.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.07:39:35.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.07:39:35.98$vck44/vb=3,4 2006.145.07:39:35.98#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.07:39:35.98#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.07:39:35.98#ibcon#ireg 11 cls_cnt 2 2006.145.07:39:35.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.07:39:36.04#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.07:39:36.04#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.07:39:36.06#ibcon#[27=AT03-04\r\n] 2006.145.07:39:36.09#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.07:39:36.09#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.07:39:36.09#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.07:39:36.09#ibcon#ireg 7 cls_cnt 0 2006.145.07:39:36.09#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.07:39:36.21#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.07:39:36.21#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.07:39:36.23#ibcon#[27=USB\r\n] 2006.145.07:39:36.26#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.07:39:36.26#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.07:39:36.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.07:39:36.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.07:39:36.26$vck44/vblo=4,679.99 2006.145.07:39:36.26#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.07:39:36.26#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.07:39:36.26#ibcon#ireg 17 cls_cnt 0 2006.145.07:39:36.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.07:39:36.26#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.07:39:36.26#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.07:39:36.28#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.07:39:36.32#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.07:39:36.32#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.07:39:36.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.07:39:36.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.07:39:36.32$vck44/vb=4,4 2006.145.07:39:36.32#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.07:39:36.32#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.07:39:36.32#ibcon#ireg 11 cls_cnt 2 2006.145.07:39:36.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.07:39:36.38#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.07:39:36.38#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.07:39:36.40#ibcon#[27=AT04-04\r\n] 2006.145.07:39:36.43#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.07:39:36.43#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.07:39:36.43#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.07:39:36.43#ibcon#ireg 7 cls_cnt 0 2006.145.07:39:36.43#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.07:39:36.55#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.07:39:36.55#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.07:39:36.57#ibcon#[27=USB\r\n] 2006.145.07:39:36.60#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.07:39:36.60#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.07:39:36.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.07:39:36.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.07:39:36.60$vck44/vblo=5,709.99 2006.145.07:39:36.60#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.07:39:36.60#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.07:39:36.60#ibcon#ireg 17 cls_cnt 0 2006.145.07:39:36.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:39:36.60#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:39:36.60#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:39:36.62#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.07:39:36.66#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:39:36.66#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:39:36.66#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.07:39:36.66#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.07:39:36.66$vck44/vb=5,4 2006.145.07:39:36.66#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.07:39:36.66#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.07:39:36.66#ibcon#ireg 11 cls_cnt 2 2006.145.07:39:36.66#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.07:39:36.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.07:39:36.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.07:39:36.74#ibcon#[27=AT05-04\r\n] 2006.145.07:39:36.77#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.07:39:36.77#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.07:39:36.77#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.07:39:36.77#ibcon#ireg 7 cls_cnt 0 2006.145.07:39:36.77#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.07:39:36.89#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.07:39:36.89#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.07:39:36.91#ibcon#[27=USB\r\n] 2006.145.07:39:36.94#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.07:39:36.94#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.07:39:36.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.07:39:36.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.07:39:36.94$vck44/vblo=6,719.99 2006.145.07:39:36.94#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.07:39:36.94#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.07:39:36.94#ibcon#ireg 17 cls_cnt 0 2006.145.07:39:36.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.07:39:36.94#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.07:39:36.94#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.07:39:36.96#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.07:39:37.00#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.07:39:37.00#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.07:39:37.00#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.07:39:37.00#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.07:39:37.00$vck44/vb=6,4 2006.145.07:39:37.00#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.07:39:37.00#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.07:39:37.00#ibcon#ireg 11 cls_cnt 2 2006.145.07:39:37.00#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.07:39:37.06#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.07:39:37.06#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.07:39:37.08#ibcon#[27=AT06-04\r\n] 2006.145.07:39:37.11#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.07:39:37.11#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.07:39:37.11#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.07:39:37.11#ibcon#ireg 7 cls_cnt 0 2006.145.07:39:37.11#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.07:39:37.23#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.07:39:37.23#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.07:39:37.25#ibcon#[27=USB\r\n] 2006.145.07:39:37.28#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.07:39:37.28#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.07:39:37.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.07:39:37.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.07:39:37.28$vck44/vblo=7,734.99 2006.145.07:39:37.28#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.07:39:37.28#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.07:39:37.28#ibcon#ireg 17 cls_cnt 0 2006.145.07:39:37.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.07:39:37.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.07:39:37.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.07:39:37.30#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.07:39:37.34#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.07:39:37.34#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.07:39:37.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.07:39:37.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.07:39:37.34$vck44/vb=7,4 2006.145.07:39:37.34#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.07:39:37.34#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.07:39:37.34#ibcon#ireg 11 cls_cnt 2 2006.145.07:39:37.34#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.07:39:37.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.07:39:37.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.07:39:37.42#ibcon#[27=AT07-04\r\n] 2006.145.07:39:37.45#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.07:39:37.45#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.07:39:37.45#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.07:39:37.45#ibcon#ireg 7 cls_cnt 0 2006.145.07:39:37.45#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.07:39:37.57#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.07:39:37.57#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.07:39:37.59#ibcon#[27=USB\r\n] 2006.145.07:39:37.62#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.07:39:37.62#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.07:39:37.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.07:39:37.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.07:39:37.62$vck44/vblo=8,744.99 2006.145.07:39:37.62#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.07:39:37.62#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.07:39:37.62#ibcon#ireg 17 cls_cnt 0 2006.145.07:39:37.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.07:39:37.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.07:39:37.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.07:39:37.64#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.07:39:37.68#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.07:39:37.68#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.07:39:37.68#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.07:39:37.68#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.07:39:37.68$vck44/vb=8,4 2006.145.07:39:37.68#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.07:39:37.68#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.07:39:37.68#ibcon#ireg 11 cls_cnt 2 2006.145.07:39:37.68#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.07:39:37.74#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.07:39:37.74#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.07:39:37.76#ibcon#[27=AT08-04\r\n] 2006.145.07:39:37.79#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.07:39:37.79#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.07:39:37.79#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.07:39:37.79#ibcon#ireg 7 cls_cnt 0 2006.145.07:39:37.79#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.07:39:37.91#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.07:39:37.91#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.07:39:37.93#ibcon#[27=USB\r\n] 2006.145.07:39:37.96#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.07:39:37.96#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.07:39:37.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.07:39:37.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.07:39:37.96$vck44/vabw=wide 2006.145.07:39:37.96#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.07:39:37.96#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.07:39:37.96#ibcon#ireg 8 cls_cnt 0 2006.145.07:39:37.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.07:39:37.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.07:39:37.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.07:39:37.98#ibcon#[25=BW32\r\n] 2006.145.07:39:38.01#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.07:39:38.01#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.07:39:38.01#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.07:39:38.01#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.07:39:38.01$vck44/vbbw=wide 2006.145.07:39:38.01#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.07:39:38.01#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.07:39:38.01#ibcon#ireg 8 cls_cnt 0 2006.145.07:39:38.01#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:39:38.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:39:38.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:39:38.10#ibcon#[27=BW32\r\n] 2006.145.07:39:38.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:39:38.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:39:38.13#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.07:39:38.13#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.07:39:38.13$setupk4/ifdk4 2006.145.07:39:38.13$ifdk4/lo= 2006.145.07:39:38.13$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.07:39:38.13$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.07:39:38.13$ifdk4/patch= 2006.145.07:39:38.13$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.07:39:38.13$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.07:39:38.13$setupk4/!*+20s 2006.145.07:39:44.24#abcon#<5=/04 4.7 8.9 19.09 661017.2\r\n> 2006.145.07:39:44.26#abcon#{5=INTERFACE CLEAR} 2006.145.07:39:44.32#abcon#[5=S1D000X0/0*\r\n] 2006.145.07:39:52.62$setupk4/"tpicd 2006.145.07:39:52.62$setupk4/echo=off 2006.145.07:39:52.62$setupk4/xlog=off 2006.145.07:39:52.62:!2006.145.07:41:38 2006.145.07:39:55.14#trakl#Source acquired 2006.145.07:39:57.14#flagr#flagr/antenna,acquired 2006.145.07:41:38.00:preob 2006.145.07:41:38.13/onsource/TRACKING 2006.145.07:41:38.13:!2006.145.07:41:48 2006.145.07:41:48.00:"tape 2006.145.07:41:48.00:"st=record 2006.145.07:41:48.00:data_valid=on 2006.145.07:41:48.00:midob 2006.145.07:41:48.13/onsource/TRACKING 2006.145.07:41:48.13/wx/19.08,1017.2,66 2006.145.07:41:48.29/cable/+6.5411E-03 2006.145.07:41:49.38/va/01,08,usb,yes,29,31 2006.145.07:41:49.38/va/02,07,usb,yes,31,32 2006.145.07:41:49.38/va/03,08,usb,yes,28,29 2006.145.07:41:49.38/va/04,07,usb,yes,32,34 2006.145.07:41:49.38/va/05,04,usb,yes,28,28 2006.145.07:41:49.38/va/06,04,usb,yes,31,31 2006.145.07:41:49.38/va/07,04,usb,yes,32,33 2006.145.07:41:49.38/va/08,04,usb,yes,27,32 2006.145.07:41:49.61/valo/01,524.99,yes,locked 2006.145.07:41:49.61/valo/02,534.99,yes,locked 2006.145.07:41:49.61/valo/03,564.99,yes,locked 2006.145.07:41:49.61/valo/04,624.99,yes,locked 2006.145.07:41:49.61/valo/05,734.99,yes,locked 2006.145.07:41:49.61/valo/06,814.99,yes,locked 2006.145.07:41:49.61/valo/07,864.99,yes,locked 2006.145.07:41:49.61/valo/08,884.99,yes,locked 2006.145.07:41:50.70/vb/01,03,usb,yes,36,34 2006.145.07:41:50.70/vb/02,04,usb,yes,32,31 2006.145.07:41:50.70/vb/03,04,usb,yes,28,31 2006.145.07:41:50.70/vb/04,04,usb,yes,33,32 2006.145.07:41:50.70/vb/05,04,usb,yes,25,28 2006.145.07:41:50.70/vb/06,04,usb,yes,30,26 2006.145.07:41:50.70/vb/07,04,usb,yes,30,29 2006.145.07:41:50.70/vb/08,04,usb,yes,27,30 2006.145.07:41:50.93/vblo/01,629.99,yes,locked 2006.145.07:41:50.93/vblo/02,634.99,yes,locked 2006.145.07:41:50.93/vblo/03,649.99,yes,locked 2006.145.07:41:50.93/vblo/04,679.99,yes,locked 2006.145.07:41:50.93/vblo/05,709.99,yes,locked 2006.145.07:41:50.93/vblo/06,719.99,yes,locked 2006.145.07:41:50.93/vblo/07,734.99,yes,locked 2006.145.07:41:50.93/vblo/08,744.99,yes,locked 2006.145.07:41:51.08/vabw/8 2006.145.07:41:51.23/vbbw/8 2006.145.07:41:51.32/xfe/off,on,14.5 2006.145.07:41:51.70/ifatt/23,28,28,28 2006.145.07:41:52.07/fmout-gps/S +5.5E-08 2006.145.07:41:52.11:!2006.145.07:44:58 2006.145.07:44:58.01:data_valid=off 2006.145.07:44:58.02:"et 2006.145.07:44:58.02:!+3s 2006.145.07:45:01.03:"tape 2006.145.07:45:01.04:postob 2006.145.07:45:01.21/cable/+6.5379E-03 2006.145.07:45:01.22/wx/19.08,1017.3,65 2006.145.07:45:01.30/fmout-gps/S +5.5E-08 2006.145.07:45:01.31:scan_name=145-0755,jd0605,180 2006.145.07:45:01.31:source=1044+719,104827.62,714335.9,2000.0,cw 2006.145.07:45:03.14#flagr#flagr/antenna,new-source 2006.145.07:45:03.15:checkk5 2006.145.07:45:03.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.07:45:04.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.07:45:04.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.07:45:04.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.07:45:05.33/chk_obsdata//k5ts1/T1450741??a.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.07:45:05.76/chk_obsdata//k5ts2/T1450741??b.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.07:45:06.18/chk_obsdata//k5ts3/T1450741??c.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.07:45:06.62/chk_obsdata//k5ts4/T1450741??d.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.07:45:07.40/k5log//k5ts1_log_newline 2006.145.07:45:08.14/k5log//k5ts2_log_newline 2006.145.07:45:08.90/k5log//k5ts3_log_newline 2006.145.07:45:09.66/k5log//k5ts4_log_newline 2006.145.07:45:09.68/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.07:45:09.68:setupk4=1 2006.145.07:45:09.68$setupk4/echo=on 2006.145.07:45:09.68$setupk4/pcalon 2006.145.07:45:09.68$pcalon/"no phase cal control is implemented here 2006.145.07:45:09.68$setupk4/"tpicd=stop 2006.145.07:45:09.68$setupk4/"rec=synch_on 2006.145.07:45:09.68$setupk4/"rec_mode=128 2006.145.07:45:09.68$setupk4/!* 2006.145.07:45:09.68$setupk4/recpk4 2006.145.07:45:09.68$recpk4/recpatch= 2006.145.07:45:09.68$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.07:45:09.68$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.07:45:09.68$setupk4/vck44 2006.145.07:45:09.68$vck44/valo=1,524.99 2006.145.07:45:09.68#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.07:45:09.68#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.07:45:09.68#ibcon#ireg 17 cls_cnt 0 2006.145.07:45:09.68#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:45:09.68#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:45:09.68#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:45:09.72#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.07:45:09.77#abcon#<5=/05 4.2 7.7 19.08 641017.2\r\n> 2006.145.07:45:09.77#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:45:09.77#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:45:09.77#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.07:45:09.77#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.07:45:09.77$vck44/va=1,8 2006.145.07:45:09.77#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.07:45:09.77#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.07:45:09.77#ibcon#ireg 11 cls_cnt 2 2006.145.07:45:09.77#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:45:09.77#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:45:09.77#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:45:09.79#abcon#{5=INTERFACE CLEAR} 2006.145.07:45:09.79#ibcon#[25=AT01-08\r\n] 2006.145.07:45:09.82#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:45:09.82#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:45:09.82#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.07:45:09.82#ibcon#ireg 7 cls_cnt 0 2006.145.07:45:09.82#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:45:09.85#abcon#[5=S1D000X0/0*\r\n] 2006.145.07:45:09.94#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:45:09.94#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:45:09.98#ibcon#[25=USB\r\n] 2006.145.07:45:10.00#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:45:10.00#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:45:10.00#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.07:45:10.00#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.07:45:10.00$vck44/valo=2,534.99 2006.145.07:45:10.00#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.07:45:10.00#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.07:45:10.00#ibcon#ireg 17 cls_cnt 0 2006.145.07:45:10.00#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.07:45:10.00#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.07:45:10.00#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.07:45:10.02#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.07:45:10.07#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.07:45:10.07#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.07:45:10.07#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.07:45:10.07#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.07:45:10.07$vck44/va=2,7 2006.145.07:45:10.07#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.07:45:10.07#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.07:45:10.07#ibcon#ireg 11 cls_cnt 2 2006.145.07:45:10.07#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.07:45:10.11#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.07:45:10.11#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.07:45:10.13#ibcon#[25=AT02-07\r\n] 2006.145.07:45:10.16#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.07:45:10.16#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.07:45:10.16#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.07:45:10.16#ibcon#ireg 7 cls_cnt 0 2006.145.07:45:10.16#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.07:45:10.28#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.07:45:10.28#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.07:45:10.30#ibcon#[25=USB\r\n] 2006.145.07:45:10.33#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.07:45:10.33#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.07:45:10.33#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.07:45:10.33#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.07:45:10.33$vck44/valo=3,564.99 2006.145.07:45:10.33#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.07:45:10.33#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.07:45:10.33#ibcon#ireg 17 cls_cnt 0 2006.145.07:45:10.33#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.07:45:10.33#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.07:45:10.33#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.07:45:10.35#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.07:45:10.39#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.07:45:10.39#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.07:45:10.39#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.07:45:10.39#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.07:45:10.39$vck44/va=3,8 2006.145.07:45:10.39#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.07:45:10.39#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.07:45:10.39#ibcon#ireg 11 cls_cnt 2 2006.145.07:45:10.39#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.07:45:10.45#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.07:45:10.45#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.07:45:10.47#ibcon#[25=AT03-08\r\n] 2006.145.07:45:10.50#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.07:45:10.50#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.07:45:10.50#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.07:45:10.50#ibcon#ireg 7 cls_cnt 0 2006.145.07:45:10.50#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.07:45:10.62#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.07:45:10.62#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.07:45:10.64#ibcon#[25=USB\r\n] 2006.145.07:45:10.67#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.07:45:10.67#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.07:45:10.67#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.07:45:10.67#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.07:45:10.67$vck44/valo=4,624.99 2006.145.07:45:10.67#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.07:45:10.67#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.07:45:10.67#ibcon#ireg 17 cls_cnt 0 2006.145.07:45:10.67#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:45:10.67#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:45:10.67#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:45:10.69#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.07:45:10.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:45:10.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:45:10.73#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.07:45:10.73#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.07:45:10.73$vck44/va=4,7 2006.145.07:45:10.73#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.07:45:10.73#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.07:45:10.73#ibcon#ireg 11 cls_cnt 2 2006.145.07:45:10.73#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:45:10.79#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:45:10.79#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:45:10.81#ibcon#[25=AT04-07\r\n] 2006.145.07:45:10.84#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:45:10.84#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:45:10.84#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.07:45:10.84#ibcon#ireg 7 cls_cnt 0 2006.145.07:45:10.84#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:45:10.96#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:45:10.96#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:45:10.98#ibcon#[25=USB\r\n] 2006.145.07:45:11.01#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:45:11.01#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:45:11.01#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.07:45:11.01#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.07:45:11.01$vck44/valo=5,734.99 2006.145.07:45:11.01#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.07:45:11.01#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.07:45:11.01#ibcon#ireg 17 cls_cnt 0 2006.145.07:45:11.01#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:45:11.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:45:11.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:45:11.03#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.07:45:11.10#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:45:11.10#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:45:11.10#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.07:45:11.10#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.07:45:11.10$vck44/va=5,4 2006.145.07:45:11.10#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.07:45:11.10#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.07:45:11.10#ibcon#ireg 11 cls_cnt 2 2006.145.07:45:11.10#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:45:11.12#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:45:11.12#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:45:11.14#ibcon#[25=AT05-04\r\n] 2006.145.07:45:11.17#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:45:11.17#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:45:11.17#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.07:45:11.17#ibcon#ireg 7 cls_cnt 0 2006.145.07:45:11.17#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:45:11.30#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:45:11.30#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:45:11.31#ibcon#[25=USB\r\n] 2006.145.07:45:11.34#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:45:11.34#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:45:11.34#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.07:45:11.34#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.07:45:11.34$vck44/valo=6,814.99 2006.145.07:45:11.34#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.07:45:11.34#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.07:45:11.34#ibcon#ireg 17 cls_cnt 0 2006.145.07:45:11.34#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:45:11.34#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:45:11.34#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:45:11.37#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.07:45:11.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:45:11.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:45:11.41#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.07:45:11.41#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.07:45:11.41$vck44/va=6,4 2006.145.07:45:11.41#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.07:45:11.41#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.07:45:11.41#ibcon#ireg 11 cls_cnt 2 2006.145.07:45:11.41#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.07:45:11.47#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.07:45:11.47#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.07:45:11.49#ibcon#[25=AT06-04\r\n] 2006.145.07:45:11.52#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.07:45:11.52#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.07:45:11.52#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.07:45:11.52#ibcon#ireg 7 cls_cnt 0 2006.145.07:45:11.52#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.07:45:11.64#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.07:45:11.64#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.07:45:11.66#ibcon#[25=USB\r\n] 2006.145.07:45:11.69#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.07:45:11.69#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.07:45:11.69#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.07:45:11.69#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.07:45:11.69$vck44/valo=7,864.99 2006.145.07:45:11.69#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.07:45:11.69#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.07:45:11.69#ibcon#ireg 17 cls_cnt 0 2006.145.07:45:11.69#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:45:11.69#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:45:11.69#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:45:11.71#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.07:45:11.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:45:11.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:45:11.75#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.07:45:11.75#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.07:45:11.75$vck44/va=7,4 2006.145.07:45:11.75#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.07:45:11.75#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.07:45:11.75#ibcon#ireg 11 cls_cnt 2 2006.145.07:45:11.75#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.07:45:11.81#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.07:45:11.81#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.07:45:11.83#ibcon#[25=AT07-04\r\n] 2006.145.07:45:11.86#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.07:45:11.86#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.07:45:11.86#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.07:45:11.86#ibcon#ireg 7 cls_cnt 0 2006.145.07:45:11.86#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.07:45:11.98#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.07:45:11.98#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.07:45:12.00#ibcon#[25=USB\r\n] 2006.145.07:45:12.03#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.07:45:12.03#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.07:45:12.03#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.07:45:12.03#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.07:45:12.03$vck44/valo=8,884.99 2006.145.07:45:12.03#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.07:45:12.03#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.07:45:12.03#ibcon#ireg 17 cls_cnt 0 2006.145.07:45:12.03#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.07:45:12.03#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.07:45:12.03#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.07:45:12.05#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.07:45:12.09#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.07:45:12.09#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.07:45:12.09#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.07:45:12.09#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.07:45:12.09$vck44/va=8,4 2006.145.07:45:12.09#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.07:45:12.09#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.07:45:12.09#ibcon#ireg 11 cls_cnt 2 2006.145.07:45:12.09#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.07:45:12.15#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.07:45:12.15#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.07:45:12.17#ibcon#[25=AT08-04\r\n] 2006.145.07:45:12.20#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.07:45:12.20#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.07:45:12.20#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.07:45:12.20#ibcon#ireg 7 cls_cnt 0 2006.145.07:45:12.20#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.07:45:12.32#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.07:45:12.32#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.07:45:12.34#ibcon#[25=USB\r\n] 2006.145.07:45:12.37#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.07:45:12.37#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.07:45:12.37#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.07:45:12.37#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.07:45:12.37$vck44/vblo=1,629.99 2006.145.07:45:12.37#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.07:45:12.37#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.07:45:12.37#ibcon#ireg 17 cls_cnt 0 2006.145.07:45:12.37#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:45:12.37#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:45:12.37#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:45:12.39#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.07:45:12.43#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:45:12.43#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.07:45:12.43#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.07:45:12.43#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.07:45:12.43$vck44/vb=1,3 2006.145.07:45:12.43#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.07:45:12.43#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.07:45:12.43#ibcon#ireg 11 cls_cnt 2 2006.145.07:45:12.43#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:45:12.43#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:45:12.43#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:45:12.45#ibcon#[27=AT01-03\r\n] 2006.145.07:45:12.48#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:45:12.48#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.07:45:12.48#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.07:45:12.48#ibcon#ireg 7 cls_cnt 0 2006.145.07:45:12.48#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:45:12.60#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:45:12.60#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:45:12.62#ibcon#[27=USB\r\n] 2006.145.07:45:12.65#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:45:12.65#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.07:45:12.65#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.07:45:12.65#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.07:45:12.65$vck44/vblo=2,634.99 2006.145.07:45:12.65#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.07:45:12.65#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.07:45:12.65#ibcon#ireg 17 cls_cnt 0 2006.145.07:45:12.65#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.07:45:12.65#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.07:45:12.65#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.07:45:12.67#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.07:45:12.71#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.07:45:12.71#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.07:45:12.71#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.07:45:12.71#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.07:45:12.71$vck44/vb=2,4 2006.145.07:45:12.71#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.07:45:12.71#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.07:45:12.71#ibcon#ireg 11 cls_cnt 2 2006.145.07:45:12.71#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.07:45:12.77#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.07:45:12.77#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.07:45:12.79#ibcon#[27=AT02-04\r\n] 2006.145.07:45:12.82#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.07:45:12.82#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.07:45:12.82#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.07:45:12.82#ibcon#ireg 7 cls_cnt 0 2006.145.07:45:12.82#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.07:45:12.94#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.07:45:12.94#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.07:45:12.96#ibcon#[27=USB\r\n] 2006.145.07:45:12.99#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.07:45:12.99#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.07:45:12.99#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.07:45:12.99#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.07:45:12.99$vck44/vblo=3,649.99 2006.145.07:45:12.99#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.07:45:12.99#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.07:45:12.99#ibcon#ireg 17 cls_cnt 0 2006.145.07:45:12.99#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.07:45:12.99#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.07:45:12.99#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.07:45:13.01#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.07:45:13.05#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.07:45:13.05#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.07:45:13.05#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.07:45:13.05#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.07:45:13.05$vck44/vb=3,4 2006.145.07:45:13.05#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.07:45:13.05#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.07:45:13.05#ibcon#ireg 11 cls_cnt 2 2006.145.07:45:13.05#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.07:45:13.11#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.07:45:13.11#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.07:45:13.13#ibcon#[27=AT03-04\r\n] 2006.145.07:45:13.16#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.07:45:13.16#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.07:45:13.16#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.07:45:13.16#ibcon#ireg 7 cls_cnt 0 2006.145.07:45:13.16#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.07:45:13.28#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.07:45:13.28#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.07:45:13.30#ibcon#[27=USB\r\n] 2006.145.07:45:13.33#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.07:45:13.33#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.07:45:13.33#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.07:45:13.33#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.07:45:13.33$vck44/vblo=4,679.99 2006.145.07:45:13.33#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.07:45:13.33#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.07:45:13.33#ibcon#ireg 17 cls_cnt 0 2006.145.07:45:13.33#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.07:45:13.33#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.07:45:13.33#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.07:45:13.35#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.07:45:13.39#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.07:45:13.39#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.07:45:13.39#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.07:45:13.39#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.07:45:13.39$vck44/vb=4,4 2006.145.07:45:13.39#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.07:45:13.39#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.07:45:13.39#ibcon#ireg 11 cls_cnt 2 2006.145.07:45:13.39#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.07:45:13.45#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.07:45:13.45#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.07:45:13.47#ibcon#[27=AT04-04\r\n] 2006.145.07:45:13.50#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.07:45:13.50#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.07:45:13.50#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.07:45:13.50#ibcon#ireg 7 cls_cnt 0 2006.145.07:45:13.50#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.07:45:13.62#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.07:45:13.62#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.07:45:13.64#ibcon#[27=USB\r\n] 2006.145.07:45:13.67#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.07:45:13.67#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.07:45:13.67#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.07:45:13.67#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.07:45:13.67$vck44/vblo=5,709.99 2006.145.07:45:13.67#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.07:45:13.67#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.07:45:13.67#ibcon#ireg 17 cls_cnt 0 2006.145.07:45:13.67#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:45:13.67#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:45:13.67#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:45:13.69#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.07:45:13.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:45:13.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.07:45:13.73#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.07:45:13.73#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.07:45:13.73$vck44/vb=5,4 2006.145.07:45:13.73#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.07:45:13.73#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.07:45:13.73#ibcon#ireg 11 cls_cnt 2 2006.145.07:45:13.73#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:45:13.79#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:45:13.79#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:45:13.81#ibcon#[27=AT05-04\r\n] 2006.145.07:45:13.84#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:45:13.84#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.07:45:13.84#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.07:45:13.84#ibcon#ireg 7 cls_cnt 0 2006.145.07:45:13.84#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:45:13.96#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:45:13.96#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:45:13.98#ibcon#[27=USB\r\n] 2006.145.07:45:14.01#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:45:14.01#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.07:45:14.01#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.07:45:14.01#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.07:45:14.01$vck44/vblo=6,719.99 2006.145.07:45:14.01#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.07:45:14.01#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.07:45:14.01#ibcon#ireg 17 cls_cnt 0 2006.145.07:45:14.01#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:45:14.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:45:14.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:45:14.03#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.07:45:14.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:45:14.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.07:45:14.07#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.07:45:14.07#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.07:45:14.07$vck44/vb=6,4 2006.145.07:45:14.07#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.07:45:14.07#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.07:45:14.07#ibcon#ireg 11 cls_cnt 2 2006.145.07:45:14.07#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:45:14.13#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:45:14.13#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:45:14.15#ibcon#[27=AT06-04\r\n] 2006.145.07:45:14.18#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:45:14.18#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.07:45:14.18#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.07:45:14.18#ibcon#ireg 7 cls_cnt 0 2006.145.07:45:14.18#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:45:14.30#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:45:14.30#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:45:14.32#ibcon#[27=USB\r\n] 2006.145.07:45:14.35#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:45:14.35#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.07:45:14.35#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.07:45:14.35#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.07:45:14.35$vck44/vblo=7,734.99 2006.145.07:45:14.35#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.07:45:14.35#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.07:45:14.35#ibcon#ireg 17 cls_cnt 0 2006.145.07:45:14.35#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:45:14.35#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:45:14.35#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:45:14.37#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.07:45:14.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:45:14.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.07:45:14.41#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.07:45:14.41#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.07:45:14.41$vck44/vb=7,4 2006.145.07:45:14.41#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.07:45:14.41#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.07:45:14.41#ibcon#ireg 11 cls_cnt 2 2006.145.07:45:14.41#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.07:45:14.47#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.07:45:14.47#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.07:45:14.49#ibcon#[27=AT07-04\r\n] 2006.145.07:45:14.52#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.07:45:14.52#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.07:45:14.52#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.07:45:14.52#ibcon#ireg 7 cls_cnt 0 2006.145.07:45:14.52#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.07:45:14.64#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.07:45:14.64#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.07:45:14.66#ibcon#[27=USB\r\n] 2006.145.07:45:14.69#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.07:45:14.69#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.07:45:14.69#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.07:45:14.69#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.07:45:14.69$vck44/vblo=8,744.99 2006.145.07:45:14.69#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.07:45:14.69#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.07:45:14.69#ibcon#ireg 17 cls_cnt 0 2006.145.07:45:14.69#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:45:14.69#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:45:14.69#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:45:14.71#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.07:45:14.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:45:14.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.07:45:14.75#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.07:45:14.75#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.07:45:14.75$vck44/vb=8,4 2006.145.07:45:14.75#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.07:45:14.75#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.07:45:14.75#ibcon#ireg 11 cls_cnt 2 2006.145.07:45:14.75#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.07:45:14.81#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.07:45:14.81#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.07:45:14.83#ibcon#[27=AT08-04\r\n] 2006.145.07:45:14.86#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.07:45:14.86#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.07:45:14.86#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.07:45:14.86#ibcon#ireg 7 cls_cnt 0 2006.145.07:45:14.86#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.07:45:14.98#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.07:45:14.98#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.07:45:15.00#ibcon#[27=USB\r\n] 2006.145.07:45:15.03#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.07:45:15.03#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.07:45:15.03#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.07:45:15.03#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.07:45:15.03$vck44/vabw=wide 2006.145.07:45:15.03#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.07:45:15.03#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.07:45:15.03#ibcon#ireg 8 cls_cnt 0 2006.145.07:45:15.03#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.07:45:15.03#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.07:45:15.03#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.07:45:15.05#ibcon#[25=BW32\r\n] 2006.145.07:45:15.08#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.07:45:15.08#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.07:45:15.08#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.07:45:15.08#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.07:45:15.08$vck44/vbbw=wide 2006.145.07:45:15.08#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.07:45:15.08#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.07:45:15.08#ibcon#ireg 8 cls_cnt 0 2006.145.07:45:15.08#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.07:45:15.15#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.07:45:15.15#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.07:45:15.17#ibcon#[27=BW32\r\n] 2006.145.07:45:15.20#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.07:45:15.20#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.07:45:15.20#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.07:45:15.20#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.07:45:15.20$setupk4/ifdk4 2006.145.07:45:15.20$ifdk4/lo= 2006.145.07:45:15.20$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.07:45:15.20$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.07:45:15.20$ifdk4/patch= 2006.145.07:45:15.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.07:45:15.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.07:45:15.20$setupk4/!*+20s 2006.145.07:45:19.94#abcon#<5=/05 4.1 7.7 19.08 661017.3\r\n> 2006.145.07:45:19.96#abcon#{5=INTERFACE CLEAR} 2006.145.07:45:20.03#abcon#[5=S1D000X0/0*\r\n] 2006.145.07:45:21.14#trakl#Source acquired 2006.145.07:45:22.14#flagr#flagr/antenna,acquired 2006.145.07:45:29.69$setupk4/"tpicd 2006.145.07:45:29.69$setupk4/echo=off 2006.145.07:45:29.69$setupk4/xlog=off 2006.145.07:45:29.69:!2006.145.07:55:18 2006.145.07:55:18.00:preob 2006.145.07:55:18.14/onsource/TRACKING 2006.145.07:55:18.14:!2006.145.07:55:28 2006.145.07:55:28.00:"tape 2006.145.07:55:28.00:"st=record 2006.145.07:55:28.00:data_valid=on 2006.145.07:55:28.00:midob 2006.145.07:55:28.14/onsource/TRACKING 2006.145.07:55:28.14/wx/18.90,1017.3,65 2006.145.07:55:28.25/cable/+6.5375E-03 2006.145.07:55:29.34/va/01,08,usb,yes,28,30 2006.145.07:55:29.34/va/02,07,usb,yes,30,31 2006.145.07:55:29.34/va/03,08,usb,yes,27,28 2006.145.07:55:29.34/va/04,07,usb,yes,31,33 2006.145.07:55:29.34/va/05,04,usb,yes,27,27 2006.145.07:55:29.34/va/06,04,usb,yes,30,30 2006.145.07:55:29.34/va/07,04,usb,yes,30,32 2006.145.07:55:29.34/va/08,04,usb,yes,26,31 2006.145.07:55:29.57/valo/01,524.99,yes,locked 2006.145.07:55:29.57/valo/02,534.99,yes,locked 2006.145.07:55:29.57/valo/03,564.99,yes,locked 2006.145.07:55:29.57/valo/04,624.99,yes,locked 2006.145.07:55:29.57/valo/05,734.99,yes,locked 2006.145.07:55:29.57/valo/06,814.99,yes,locked 2006.145.07:55:29.57/valo/07,864.99,yes,locked 2006.145.07:55:29.57/valo/08,884.99,yes,locked 2006.145.07:55:30.66/vb/01,03,usb,yes,35,33 2006.145.07:55:30.66/vb/02,04,usb,yes,31,31 2006.145.07:55:30.66/vb/03,04,usb,yes,28,31 2006.145.07:55:30.66/vb/04,04,usb,yes,32,31 2006.145.07:55:30.66/vb/05,04,usb,yes,25,27 2006.145.07:55:30.66/vb/06,04,usb,yes,29,25 2006.145.07:55:30.66/vb/07,04,usb,yes,29,29 2006.145.07:55:30.66/vb/08,04,usb,yes,26,30 2006.145.07:55:30.89/vblo/01,629.99,yes,locked 2006.145.07:55:30.89/vblo/02,634.99,yes,locked 2006.145.07:55:30.89/vblo/03,649.99,yes,locked 2006.145.07:55:30.89/vblo/04,679.99,yes,locked 2006.145.07:55:30.89/vblo/05,709.99,yes,locked 2006.145.07:55:30.89/vblo/06,719.99,yes,locked 2006.145.07:55:30.89/vblo/07,734.99,yes,locked 2006.145.07:55:30.89/vblo/08,744.99,yes,locked 2006.145.07:55:31.04/vabw/8 2006.145.07:55:31.19/vbbw/8 2006.145.07:55:31.28/xfe/off,on,16.0 2006.145.07:55:31.65/ifatt/23,28,28,28 2006.145.07:55:32.08/fmout-gps/S +5.8E-08 2006.145.07:55:32.12:!2006.145.07:58:28 2006.145.07:58:28.00:data_valid=off 2006.145.07:58:28.00:"et 2006.145.07:58:28.01:!+3s 2006.145.07:58:31.02:"tape 2006.145.07:58:31.02:postob 2006.145.07:58:31.18/cable/+6.5378E-03 2006.145.07:58:31.18/wx/18.85,1017.2,65 2006.145.07:58:32.08/fmout-gps/S +5.8E-08 2006.145.07:58:32.08:scan_name=145-0759,jd0605,120 2006.145.07:58:32.09:source=1611+343,161341.06,341247.9,2000.0,cw 2006.145.07:58:32.13#flagr#flagr/antenna,new-source 2006.145.07:58:33.13:checkk5 2006.145.07:58:33.54/chk_autoobs//k5ts1/ autoobs is running! 2006.145.07:58:33.97/chk_autoobs//k5ts2/ autoobs is running! 2006.145.07:58:34.40/chk_autoobs//k5ts3/ autoobs is running! 2006.145.07:58:34.85/chk_autoobs//k5ts4/ autoobs is running! 2006.145.07:58:35.29/chk_obsdata//k5ts1/T1450755??a.dat file size is correct (nominal:720MB, actual:720MB). 2006.145.07:58:35.72/chk_obsdata//k5ts2/T1450755??b.dat file size is correct (nominal:720MB, actual:720MB). 2006.145.07:58:36.15/chk_obsdata//k5ts3/T1450755??c.dat file size is correct (nominal:720MB, actual:720MB). 2006.145.07:58:36.57/chk_obsdata//k5ts4/T1450755??d.dat file size is correct (nominal:720MB, actual:720MB). 2006.145.07:58:37.35/k5log//k5ts1_log_newline 2006.145.07:58:38.08/k5log//k5ts2_log_newline 2006.145.07:58:38.79/k5log//k5ts3_log_newline 2006.145.07:58:39.55/k5log//k5ts4_log_newline 2006.145.07:58:39.57/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.07:58:39.57:setupk4=1 2006.145.07:58:39.57$setupk4/echo=on 2006.145.07:58:39.57$setupk4/pcalon 2006.145.07:58:39.57$pcalon/"no phase cal control is implemented here 2006.145.07:58:39.57$setupk4/"tpicd=stop 2006.145.07:58:39.57$setupk4/"rec=synch_on 2006.145.07:58:39.57$setupk4/"rec_mode=128 2006.145.07:58:39.57$setupk4/!* 2006.145.07:58:39.57$setupk4/recpk4 2006.145.07:58:39.57$recpk4/recpatch= 2006.145.07:58:39.58$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.07:58:39.58$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.07:58:39.58$setupk4/vck44 2006.145.07:58:39.58$vck44/valo=1,524.99 2006.145.07:58:39.58#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.07:58:39.58#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.07:58:39.58#ibcon#ireg 17 cls_cnt 0 2006.145.07:58:39.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:58:39.58#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:58:39.58#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:58:39.62#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.07:58:39.66#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:58:39.66#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:58:39.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.07:58:39.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.07:58:39.66$vck44/va=1,8 2006.145.07:58:39.66#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.07:58:39.66#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.07:58:39.66#ibcon#ireg 11 cls_cnt 2 2006.145.07:58:39.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:58:39.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:58:39.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:58:39.68#ibcon#[25=AT01-08\r\n] 2006.145.07:58:39.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:58:39.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:58:39.71#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.07:58:39.71#ibcon#ireg 7 cls_cnt 0 2006.145.07:58:39.71#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:58:39.84#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:58:39.84#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:58:39.85#ibcon#[25=USB\r\n] 2006.145.07:58:39.88#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:58:39.88#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:58:39.88#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.07:58:39.88#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.07:58:39.88$vck44/valo=2,534.99 2006.145.07:58:39.88#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.07:58:39.88#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.07:58:39.88#ibcon#ireg 17 cls_cnt 0 2006.145.07:58:39.88#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:58:39.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:58:39.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:58:39.90#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.07:58:39.94#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:58:39.94#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:58:39.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.07:58:39.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.07:58:39.94$vck44/va=2,7 2006.145.07:58:39.94#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.07:58:39.94#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.07:58:39.94#ibcon#ireg 11 cls_cnt 2 2006.145.07:58:39.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:58:40.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:58:40.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:58:40.02#ibcon#[25=AT02-07\r\n] 2006.145.07:58:40.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:58:40.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:58:40.05#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.07:58:40.05#ibcon#ireg 7 cls_cnt 0 2006.145.07:58:40.05#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:58:40.17#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:58:40.17#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:58:40.19#ibcon#[25=USB\r\n] 2006.145.07:58:40.22#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:58:40.22#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:58:40.22#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.07:58:40.22#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.07:58:40.22$vck44/valo=3,564.99 2006.145.07:58:40.22#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.07:58:40.22#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.07:58:40.22#ibcon#ireg 17 cls_cnt 0 2006.145.07:58:40.22#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:58:40.22#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:58:40.22#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:58:40.24#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.07:58:40.28#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:58:40.28#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:58:40.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.07:58:40.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.07:58:40.28$vck44/va=3,8 2006.145.07:58:40.28#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.07:58:40.28#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.07:58:40.28#ibcon#ireg 11 cls_cnt 2 2006.145.07:58:40.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:58:40.34#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:58:40.34#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:58:40.36#ibcon#[25=AT03-08\r\n] 2006.145.07:58:40.39#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:58:40.39#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:58:40.39#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.07:58:40.39#ibcon#ireg 7 cls_cnt 0 2006.145.07:58:40.39#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:58:40.51#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:58:40.51#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:58:40.53#ibcon#[25=USB\r\n] 2006.145.07:58:40.56#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:58:40.56#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:58:40.56#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.07:58:40.56#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.07:58:40.56$vck44/valo=4,624.99 2006.145.07:58:40.56#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.07:58:40.56#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.07:58:40.56#ibcon#ireg 17 cls_cnt 0 2006.145.07:58:40.56#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:58:40.56#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:58:40.56#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:58:40.58#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.07:58:40.62#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:58:40.62#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:58:40.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.07:58:40.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.07:58:40.62$vck44/va=4,7 2006.145.07:58:40.62#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.07:58:40.62#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.07:58:40.62#ibcon#ireg 11 cls_cnt 2 2006.145.07:58:40.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:58:40.68#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:58:40.68#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:58:40.70#ibcon#[25=AT04-07\r\n] 2006.145.07:58:40.73#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:58:40.73#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:58:40.73#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.07:58:40.73#ibcon#ireg 7 cls_cnt 0 2006.145.07:58:40.73#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:58:40.85#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:58:40.85#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:58:40.87#ibcon#[25=USB\r\n] 2006.145.07:58:40.90#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:58:40.90#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:58:40.90#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.07:58:40.90#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.07:58:40.90$vck44/valo=5,734.99 2006.145.07:58:40.90#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.07:58:40.90#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.07:58:40.90#ibcon#ireg 17 cls_cnt 0 2006.145.07:58:40.90#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:58:40.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:58:40.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:58:40.92#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.07:58:40.96#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:58:40.96#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.07:58:40.96#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.07:58:40.96#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.07:58:40.96$vck44/va=5,4 2006.145.07:58:40.96#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.07:58:40.96#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.07:58:40.96#ibcon#ireg 11 cls_cnt 2 2006.145.07:58:40.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:58:41.02#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:58:41.02#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:58:41.04#ibcon#[25=AT05-04\r\n] 2006.145.07:58:41.07#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:58:41.07#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.07:58:41.07#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.07:58:41.07#ibcon#ireg 7 cls_cnt 0 2006.145.07:58:41.07#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:58:41.19#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:58:41.19#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:58:41.21#ibcon#[25=USB\r\n] 2006.145.07:58:41.24#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:58:41.24#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.07:58:41.24#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.07:58:41.24#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.07:58:41.24$vck44/valo=6,814.99 2006.145.07:58:41.24#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.07:58:41.24#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.07:58:41.24#ibcon#ireg 17 cls_cnt 0 2006.145.07:58:41.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:58:41.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:58:41.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:58:41.26#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.07:58:41.30#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:58:41.30#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:58:41.30#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.07:58:41.30#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.07:58:41.30$vck44/va=6,4 2006.145.07:58:41.30#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.07:58:41.30#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.07:58:41.30#ibcon#ireg 11 cls_cnt 2 2006.145.07:58:41.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:58:41.36#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:58:41.36#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:58:41.38#ibcon#[25=AT06-04\r\n] 2006.145.07:58:41.41#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:58:41.41#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:58:41.41#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.07:58:41.41#ibcon#ireg 7 cls_cnt 0 2006.145.07:58:41.41#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:58:41.53#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:58:41.53#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:58:41.55#ibcon#[25=USB\r\n] 2006.145.07:58:41.58#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:58:41.58#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:58:41.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.07:58:41.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.07:58:41.58$vck44/valo=7,864.99 2006.145.07:58:41.58#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.07:58:41.58#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.07:58:41.58#ibcon#ireg 17 cls_cnt 0 2006.145.07:58:41.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:58:41.58#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:58:41.58#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:58:41.60#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.07:58:41.64#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:58:41.64#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:58:41.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.07:58:41.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.07:58:41.64$vck44/va=7,4 2006.145.07:58:41.64#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.07:58:41.64#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.07:58:41.64#ibcon#ireg 11 cls_cnt 2 2006.145.07:58:41.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:58:41.70#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:58:41.70#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:58:41.72#ibcon#[25=AT07-04\r\n] 2006.145.07:58:41.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:58:41.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:58:41.75#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.07:58:41.75#ibcon#ireg 7 cls_cnt 0 2006.145.07:58:41.75#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:58:41.87#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:58:41.87#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:58:41.90#ibcon#[25=USB\r\n] 2006.145.07:58:41.93#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:58:41.93#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:58:41.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.07:58:41.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.07:58:41.93$vck44/valo=8,884.99 2006.145.07:58:41.93#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.07:58:41.93#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.07:58:41.93#ibcon#ireg 17 cls_cnt 0 2006.145.07:58:41.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:58:41.93#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:58:41.93#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:58:41.95#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.07:58:41.99#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:58:41.99#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:58:41.99#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.07:58:41.99#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.07:58:41.99$vck44/va=8,4 2006.145.07:58:41.99#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.07:58:41.99#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.07:58:41.99#ibcon#ireg 11 cls_cnt 2 2006.145.07:58:41.99#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:58:42.05#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:58:42.05#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:58:42.08#ibcon#[25=AT08-04\r\n] 2006.145.07:58:42.11#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:58:42.11#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:58:42.11#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.07:58:42.11#ibcon#ireg 7 cls_cnt 0 2006.145.07:58:42.11#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:58:42.23#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:58:42.23#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:58:42.25#ibcon#[25=USB\r\n] 2006.145.07:58:42.28#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:58:42.28#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:58:42.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.07:58:42.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.07:58:42.28$vck44/vblo=1,629.99 2006.145.07:58:42.28#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.07:58:42.28#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.07:58:42.28#ibcon#ireg 17 cls_cnt 0 2006.145.07:58:42.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:58:42.28#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:58:42.28#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:58:42.30#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.07:58:42.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:58:42.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:58:42.34#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.07:58:42.34#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.07:58:42.34$vck44/vb=1,3 2006.145.07:58:42.34#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.07:58:42.34#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.07:58:42.34#ibcon#ireg 11 cls_cnt 2 2006.145.07:58:42.34#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:58:42.34#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:58:42.34#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:58:42.36#ibcon#[27=AT01-03\r\n] 2006.145.07:58:42.39#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:58:42.39#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.07:58:42.39#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.07:58:42.39#ibcon#ireg 7 cls_cnt 0 2006.145.07:58:42.39#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:58:42.51#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:58:42.51#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:58:42.53#ibcon#[27=USB\r\n] 2006.145.07:58:42.56#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:58:42.56#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.07:58:42.56#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.07:58:42.56#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.07:58:42.56$vck44/vblo=2,634.99 2006.145.07:58:42.56#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.07:58:42.56#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.07:58:42.56#ibcon#ireg 17 cls_cnt 0 2006.145.07:58:42.56#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:58:42.56#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:58:42.56#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:58:42.58#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.07:58:42.62#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:58:42.62#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.07:58:42.62#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.07:58:42.62#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.07:58:42.62$vck44/vb=2,4 2006.145.07:58:42.62#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.07:58:42.62#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.07:58:42.62#ibcon#ireg 11 cls_cnt 2 2006.145.07:58:42.62#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:58:42.68#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:58:42.68#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:58:42.70#ibcon#[27=AT02-04\r\n] 2006.145.07:58:42.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:58:42.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.07:58:42.73#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.07:58:42.73#ibcon#ireg 7 cls_cnt 0 2006.145.07:58:42.73#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:58:42.85#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:58:42.85#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:58:42.87#ibcon#[27=USB\r\n] 2006.145.07:58:42.90#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:58:42.90#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.07:58:42.90#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.07:58:42.90#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.07:58:42.90$vck44/vblo=3,649.99 2006.145.07:58:42.90#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.07:58:42.90#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.07:58:42.90#ibcon#ireg 17 cls_cnt 0 2006.145.07:58:42.90#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:58:42.90#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:58:42.90#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:58:42.92#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.07:58:42.96#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:58:42.96#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.07:58:42.96#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.07:58:42.96#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.07:58:42.96$vck44/vb=3,4 2006.145.07:58:42.96#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.07:58:42.96#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.07:58:42.96#ibcon#ireg 11 cls_cnt 2 2006.145.07:58:42.96#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:58:43.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:58:43.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:58:43.04#ibcon#[27=AT03-04\r\n] 2006.145.07:58:43.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:58:43.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.07:58:43.07#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.07:58:43.07#ibcon#ireg 7 cls_cnt 0 2006.145.07:58:43.07#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:58:43.19#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:58:43.19#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:58:43.21#ibcon#[27=USB\r\n] 2006.145.07:58:43.24#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:58:43.24#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.07:58:43.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.07:58:43.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.07:58:43.24$vck44/vblo=4,679.99 2006.145.07:58:43.24#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.07:58:43.24#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.07:58:43.24#ibcon#ireg 17 cls_cnt 0 2006.145.07:58:43.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:58:43.24#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:58:43.24#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:58:43.26#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.07:58:43.30#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:58:43.30#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.07:58:43.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.07:58:43.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.07:58:43.30$vck44/vb=4,4 2006.145.07:58:43.30#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.07:58:43.30#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.07:58:43.30#ibcon#ireg 11 cls_cnt 2 2006.145.07:58:43.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:58:43.36#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:58:43.36#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:58:43.38#ibcon#[27=AT04-04\r\n] 2006.145.07:58:43.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:58:43.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.07:58:43.41#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.07:58:43.41#ibcon#ireg 7 cls_cnt 0 2006.145.07:58:43.41#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:58:43.53#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:58:43.53#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:58:43.55#ibcon#[27=USB\r\n] 2006.145.07:58:43.58#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:58:43.58#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.07:58:43.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.07:58:43.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.07:58:43.58$vck44/vblo=5,709.99 2006.145.07:58:43.58#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.07:58:43.58#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.07:58:43.58#ibcon#ireg 17 cls_cnt 0 2006.145.07:58:43.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:58:43.58#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:58:43.58#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:58:43.60#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.07:58:43.64#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:58:43.64#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.07:58:43.64#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.07:58:43.64#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.07:58:43.64$vck44/vb=5,4 2006.145.07:58:43.64#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.07:58:43.64#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.07:58:43.64#ibcon#ireg 11 cls_cnt 2 2006.145.07:58:43.64#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:58:43.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:58:43.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:58:43.72#ibcon#[27=AT05-04\r\n] 2006.145.07:58:43.73#abcon#<5=/04 4.7 8.3 18.84 651017.3\r\n> 2006.145.07:58:43.75#abcon#{5=INTERFACE CLEAR} 2006.145.07:58:43.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:58:43.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.07:58:43.75#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.07:58:43.75#ibcon#ireg 7 cls_cnt 0 2006.145.07:58:43.75#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:58:43.81#abcon#[5=S1D000X0/0*\r\n] 2006.145.07:58:43.87#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:58:43.87#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:58:43.89#ibcon#[27=USB\r\n] 2006.145.07:58:43.92#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:58:43.92#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.07:58:43.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.07:58:43.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.07:58:43.92$vck44/vblo=6,719.99 2006.145.07:58:43.92#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.07:58:43.92#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.07:58:43.92#ibcon#ireg 17 cls_cnt 0 2006.145.07:58:43.92#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:58:43.92#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:58:43.92#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:58:43.94#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.07:58:43.98#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:58:43.98#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.07:58:43.98#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.07:58:43.98#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.07:58:43.98$vck44/vb=6,4 2006.145.07:58:43.98#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.07:58:43.98#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.07:58:43.98#ibcon#ireg 11 cls_cnt 2 2006.145.07:58:43.98#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:58:44.04#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:58:44.04#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:58:44.06#ibcon#[27=AT06-04\r\n] 2006.145.07:58:44.09#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:58:44.09#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.07:58:44.09#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.07:58:44.09#ibcon#ireg 7 cls_cnt 0 2006.145.07:58:44.09#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:58:44.21#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:58:44.21#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:58:44.23#ibcon#[27=USB\r\n] 2006.145.07:58:44.26#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:58:44.26#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.07:58:44.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.07:58:44.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.07:58:44.26$vck44/vblo=7,734.99 2006.145.07:58:44.26#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.07:58:44.26#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.07:58:44.26#ibcon#ireg 17 cls_cnt 0 2006.145.07:58:44.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:58:44.26#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:58:44.26#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:58:44.28#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.07:58:44.32#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:58:44.32#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.07:58:44.32#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.07:58:44.32#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.07:58:44.32$vck44/vb=7,4 2006.145.07:58:44.32#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.07:58:44.32#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.07:58:44.32#ibcon#ireg 11 cls_cnt 2 2006.145.07:58:44.32#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:58:44.38#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:58:44.38#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:58:44.40#ibcon#[27=AT07-04\r\n] 2006.145.07:58:44.43#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:58:44.43#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.07:58:44.43#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.07:58:44.43#ibcon#ireg 7 cls_cnt 0 2006.145.07:58:44.43#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:58:44.55#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:58:44.55#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:58:44.57#ibcon#[27=USB\r\n] 2006.145.07:58:44.60#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:58:44.60#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.07:58:44.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.07:58:44.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.07:58:44.60$vck44/vblo=8,744.99 2006.145.07:58:44.60#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.07:58:44.60#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.07:58:44.60#ibcon#ireg 17 cls_cnt 0 2006.145.07:58:44.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:58:44.60#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:58:44.60#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:58:44.62#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.07:58:44.66#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:58:44.66#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.07:58:44.66#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.07:58:44.66#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.07:58:44.66$vck44/vb=8,4 2006.145.07:58:44.66#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.07:58:44.66#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.07:58:44.66#ibcon#ireg 11 cls_cnt 2 2006.145.07:58:44.66#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:58:44.72#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:58:44.72#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:58:44.74#ibcon#[27=AT08-04\r\n] 2006.145.07:58:44.77#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:58:44.77#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.07:58:44.77#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.07:58:44.77#ibcon#ireg 7 cls_cnt 0 2006.145.07:58:44.77#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:58:44.89#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:58:44.89#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:58:44.91#ibcon#[27=USB\r\n] 2006.145.07:58:44.94#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:58:44.94#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.07:58:44.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.07:58:44.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.07:58:44.94$vck44/vabw=wide 2006.145.07:58:44.94#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.07:58:44.94#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.07:58:44.94#ibcon#ireg 8 cls_cnt 0 2006.145.07:58:44.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:58:44.94#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:58:44.94#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:58:44.96#ibcon#[25=BW32\r\n] 2006.145.07:58:44.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:58:44.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.07:58:44.99#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.07:58:44.99#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.07:58:44.99$vck44/vbbw=wide 2006.145.07:58:44.99#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.07:58:44.99#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.07:58:44.99#ibcon#ireg 8 cls_cnt 0 2006.145.07:58:44.99#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:58:45.06#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:58:45.06#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:58:45.08#ibcon#[27=BW32\r\n] 2006.145.07:58:45.11#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:58:45.11#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.07:58:45.11#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.07:58:45.11#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.07:58:45.11$setupk4/ifdk4 2006.145.07:58:45.11$ifdk4/lo= 2006.145.07:58:45.11$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.07:58:45.11$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.07:58:45.11$ifdk4/patch= 2006.145.07:58:45.11$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.07:58:45.11$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.07:58:45.11$setupk4/!*+20s 2006.145.07:58:53.90#abcon#<5=/04 4.7 8.3 18.84 651017.3\r\n> 2006.145.07:58:53.92#abcon#{5=INTERFACE CLEAR} 2006.145.07:58:53.98#abcon#[5=S1D000X0/0*\r\n] 2006.145.07:58:58.13#trakl#Source acquired 2006.145.07:58:59.13#flagr#flagr/antenna,acquired 2006.145.07:58:59.58$setupk4/"tpicd 2006.145.07:58:59.58$setupk4/echo=off 2006.145.07:58:59.58$setupk4/xlog=off 2006.145.07:58:59.58:!2006.145.07:59:16 2006.145.07:59:16.00:preob 2006.145.07:59:16.13/onsource/TRACKING 2006.145.07:59:16.13:!2006.145.07:59:26 2006.145.07:59:26.00:"tape 2006.145.07:59:26.00:"st=record 2006.145.07:59:26.00:data_valid=on 2006.145.07:59:26.00:midob 2006.145.07:59:26.13/onsource/TRACKING 2006.145.07:59:26.13/wx/18.83,1017.3,65 2006.145.07:59:26.24/cable/+6.5372E-03 2006.145.07:59:27.33/va/01,08,usb,yes,32,35 2006.145.07:59:27.33/va/02,07,usb,yes,35,35 2006.145.07:59:27.33/va/03,08,usb,yes,31,33 2006.145.07:59:27.33/va/04,07,usb,yes,36,38 2006.145.07:59:27.33/va/05,04,usb,yes,31,32 2006.145.07:59:27.33/va/06,04,usb,yes,35,35 2006.145.07:59:27.33/va/07,04,usb,yes,35,37 2006.145.07:59:27.33/va/08,04,usb,yes,30,36 2006.145.07:59:27.56/valo/01,524.99,yes,locked 2006.145.07:59:27.56/valo/02,534.99,yes,locked 2006.145.07:59:27.56/valo/03,564.99,yes,locked 2006.145.07:59:27.56/valo/04,624.99,yes,locked 2006.145.07:59:27.56/valo/05,734.99,yes,locked 2006.145.07:59:27.56/valo/06,814.99,yes,locked 2006.145.07:59:27.56/valo/07,864.99,yes,locked 2006.145.07:59:27.56/valo/08,884.99,yes,locked 2006.145.07:59:28.65/vb/01,03,usb,yes,39,36 2006.145.07:59:28.65/vb/02,04,usb,yes,34,34 2006.145.07:59:28.65/vb/03,04,usb,yes,31,34 2006.145.07:59:28.65/vb/04,04,usb,yes,35,34 2006.145.07:59:28.65/vb/05,04,usb,yes,28,30 2006.145.07:59:28.65/vb/06,04,usb,yes,32,28 2006.145.07:59:28.65/vb/07,04,usb,yes,32,32 2006.145.07:59:28.65/vb/08,04,usb,yes,30,33 2006.145.07:59:28.89/vblo/01,629.99,yes,locked 2006.145.07:59:28.89/vblo/02,634.99,yes,locked 2006.145.07:59:28.89/vblo/03,649.99,yes,locked 2006.145.07:59:28.89/vblo/04,679.99,yes,locked 2006.145.07:59:28.89/vblo/05,709.99,yes,locked 2006.145.07:59:28.89/vblo/06,719.99,yes,locked 2006.145.07:59:28.89/vblo/07,734.99,yes,locked 2006.145.07:59:28.89/vblo/08,744.99,yes,locked 2006.145.07:59:29.04/vabw/8 2006.145.07:59:29.19/vbbw/8 2006.145.07:59:29.34/xfe/off,on,15.2 2006.145.07:59:29.72/ifatt/23,28,28,28 2006.145.07:59:30.07/fmout-gps/S +5.8E-08 2006.145.07:59:30.11:!2006.145.08:01:26 2006.145.07:59:47.14#trakl#Off source 2006.145.07:59:47.14?ERROR st -7 Antenna off-source! 2006.145.07:59:47.14#trakl#az 56.175 el 11.987 azerr*cos(el) 0.0161 elerr -0.0097 2006.145.07:59:49.14#flagr#flagr/antenna,off-source 2006.145.07:59:53.14#trakl#Source re-acquired 2006.145.07:59:55.14#flagr#flagr/antenna,re-acquired 2006.145.08:01:26.00:data_valid=off 2006.145.08:01:26.00:"et 2006.145.08:01:26.01:!+3s 2006.145.08:01:29.02:"tape 2006.145.08:01:29.02:postob 2006.145.08:01:29.14/cable/+6.5400E-03 2006.145.08:01:29.14/wx/18.81,1017.3,67 2006.145.08:01:29.21/fmout-gps/S +5.8E-08 2006.145.08:01:29.21:scan_name=145-0802,jd0605,80 2006.145.08:01:29.21:source=3c274,123049.42,122328.0,2000.0,cw 2006.145.08:01:30.14#trakl#Off source 2006.145.08:01:30.14?ERROR st -7 Antenna off-source! 2006.145.08:01:30.14#trakl#az 56.388 el 12.274 azerr*cos(el) 0.0229 elerr 0.0021 2006.145.08:01:30.14#flagr#flagr/antenna,new-source 2006.145.08:01:30.14:checkk5 2006.145.08:01:30.65/chk_autoobs//k5ts1/ autoobs is running! 2006.145.08:01:31.08/chk_autoobs//k5ts2/ autoobs is running! 2006.145.08:01:31.53/chk_autoobs//k5ts3/ autoobs is running! 2006.145.08:01:31.96/chk_autoobs//k5ts4/ autoobs is running! 2006.145.08:01:32.38/chk_obsdata//k5ts1/T1450759??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.08:01:32.84/chk_obsdata//k5ts2/T1450759??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.08:01:33.29/chk_obsdata//k5ts3/T1450759??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.08:01:33.73/chk_obsdata//k5ts4/T1450759??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.08:01:34.50/k5log//k5ts1_log_newline 2006.145.08:01:35.25/k5log//k5ts2_log_newline 2006.145.08:01:35.99/k5log//k5ts3_log_newline 2006.145.08:01:36.73/k5log//k5ts4_log_newline 2006.145.08:01:36.80/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.08:01:36.80:setupk4=1 2006.145.08:01:36.80$setupk4/echo=on 2006.145.08:01:36.80$setupk4/pcalon 2006.145.08:01:36.80$pcalon/"no phase cal control is implemented here 2006.145.08:01:36.80$setupk4/"tpicd=stop 2006.145.08:01:36.80$setupk4/"rec=synch_on 2006.145.08:01:36.80$setupk4/"rec_mode=128 2006.145.08:01:36.80$setupk4/!* 2006.145.08:01:36.80$setupk4/recpk4 2006.145.08:01:36.80$recpk4/recpatch= 2006.145.08:01:36.80$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.08:01:36.80$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.08:01:36.80$setupk4/vck44 2006.145.08:01:36.80$vck44/valo=1,524.99 2006.145.08:01:36.80#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.08:01:36.80#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.08:01:36.80#ibcon#ireg 17 cls_cnt 0 2006.145.08:01:36.80#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:01:36.80#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:01:36.80#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:01:36.82#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.08:01:36.89#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:01:36.89#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:01:36.89#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.08:01:36.89#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.08:01:36.90$vck44/va=1,8 2006.145.08:01:36.90#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.08:01:36.90#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.08:01:36.90#ibcon#ireg 11 cls_cnt 2 2006.145.08:01:36.90#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:01:36.90#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:01:36.90#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:01:36.91#ibcon#[25=AT01-08\r\n] 2006.145.08:01:36.94#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:01:36.94#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:01:36.94#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.08:01:36.94#ibcon#ireg 7 cls_cnt 0 2006.145.08:01:36.94#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:01:37.08#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:01:37.08#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:01:37.09#ibcon#[25=USB\r\n] 2006.145.08:01:37.12#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:01:37.12#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:01:37.12#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.08:01:37.12#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.08:01:37.12$vck44/valo=2,534.99 2006.145.08:01:37.12#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.08:01:37.12#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.08:01:37.12#ibcon#ireg 17 cls_cnt 0 2006.145.08:01:37.12#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:01:37.12#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:01:37.12#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:01:37.14#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.08:01:37.18#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:01:37.18#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:01:37.18#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.08:01:37.18#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.08:01:37.18$vck44/va=2,7 2006.145.08:01:37.18#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.08:01:37.18#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.08:01:37.18#ibcon#ireg 11 cls_cnt 2 2006.145.08:01:37.18#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:01:37.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:01:37.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:01:37.26#ibcon#[25=AT02-07\r\n] 2006.145.08:01:37.29#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:01:37.29#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:01:37.29#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.08:01:37.29#ibcon#ireg 7 cls_cnt 0 2006.145.08:01:37.29#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:01:37.41#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:01:37.41#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:01:37.43#ibcon#[25=USB\r\n] 2006.145.08:01:37.46#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:01:37.46#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:01:37.46#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.08:01:37.46#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.08:01:37.46$vck44/valo=3,564.99 2006.145.08:01:37.46#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.08:01:37.46#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.08:01:37.46#ibcon#ireg 17 cls_cnt 0 2006.145.08:01:37.46#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:01:37.46#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:01:37.46#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:01:37.48#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.08:01:37.52#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:01:37.52#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:01:37.52#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.08:01:37.52#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.08:01:37.52$vck44/va=3,8 2006.145.08:01:37.52#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.08:01:37.52#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.08:01:37.52#ibcon#ireg 11 cls_cnt 2 2006.145.08:01:37.52#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:01:37.58#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:01:37.58#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:01:37.60#ibcon#[25=AT03-08\r\n] 2006.145.08:01:37.63#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:01:37.63#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:01:37.63#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.08:01:37.63#ibcon#ireg 7 cls_cnt 0 2006.145.08:01:37.63#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:01:37.75#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:01:37.75#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:01:37.77#ibcon#[25=USB\r\n] 2006.145.08:01:37.80#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:01:37.80#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:01:37.80#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.08:01:37.80#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.08:01:37.80$vck44/valo=4,624.99 2006.145.08:01:37.80#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.08:01:37.80#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.08:01:37.80#ibcon#ireg 17 cls_cnt 0 2006.145.08:01:37.80#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:01:37.80#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:01:37.80#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:01:37.82#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.08:01:37.86#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:01:37.86#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:01:37.86#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.08:01:37.86#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.08:01:37.86$vck44/va=4,7 2006.145.08:01:37.86#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.08:01:37.86#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.08:01:37.86#ibcon#ireg 11 cls_cnt 2 2006.145.08:01:37.86#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:01:37.92#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:01:37.92#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:01:37.94#ibcon#[25=AT04-07\r\n] 2006.145.08:01:37.97#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:01:37.97#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:01:37.97#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.08:01:37.97#ibcon#ireg 7 cls_cnt 0 2006.145.08:01:37.97#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:01:38.09#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:01:38.09#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:01:38.12#ibcon#[25=USB\r\n] 2006.145.08:01:38.15#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:01:38.15#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:01:38.15#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.08:01:38.15#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.08:01:38.15$vck44/valo=5,734.99 2006.145.08:01:38.15#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.08:01:38.15#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.08:01:38.15#ibcon#ireg 17 cls_cnt 0 2006.145.08:01:38.15#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:01:38.15#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:01:38.15#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:01:38.17#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.08:01:38.21#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:01:38.21#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:01:38.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.08:01:38.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.08:01:38.21$vck44/va=5,4 2006.145.08:01:38.21#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.08:01:38.21#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.08:01:38.21#ibcon#ireg 11 cls_cnt 2 2006.145.08:01:38.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:01:38.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:01:38.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:01:38.29#ibcon#[25=AT05-04\r\n] 2006.145.08:01:38.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:01:38.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:01:38.32#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.08:01:38.32#ibcon#ireg 7 cls_cnt 0 2006.145.08:01:38.32#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:01:38.44#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:01:38.44#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:01:38.46#ibcon#[25=USB\r\n] 2006.145.08:01:38.49#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:01:38.49#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:01:38.49#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.08:01:38.49#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.08:01:38.49$vck44/valo=6,814.99 2006.145.08:01:38.49#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.08:01:38.49#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.08:01:38.49#ibcon#ireg 17 cls_cnt 0 2006.145.08:01:38.49#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:01:38.49#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:01:38.49#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:01:38.51#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.08:01:38.55#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:01:38.55#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:01:38.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.08:01:38.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.08:01:38.55$vck44/va=6,4 2006.145.08:01:38.55#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.08:01:38.55#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.08:01:38.55#ibcon#ireg 11 cls_cnt 2 2006.145.08:01:38.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.08:01:38.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.08:01:38.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.08:01:38.63#ibcon#[25=AT06-04\r\n] 2006.145.08:01:38.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.08:01:38.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.08:01:38.66#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.08:01:38.66#ibcon#ireg 7 cls_cnt 0 2006.145.08:01:38.66#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.08:01:38.78#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.08:01:38.78#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.08:01:38.80#ibcon#[25=USB\r\n] 2006.145.08:01:38.83#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.08:01:38.83#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.08:01:38.83#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.08:01:38.83#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.08:01:38.83$vck44/valo=7,864.99 2006.145.08:01:38.83#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.08:01:38.83#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.08:01:38.83#ibcon#ireg 17 cls_cnt 0 2006.145.08:01:38.83#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.08:01:38.83#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.08:01:38.83#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.08:01:38.85#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.08:01:38.89#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.08:01:38.89#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.08:01:38.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.08:01:38.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.08:01:38.89$vck44/va=7,4 2006.145.08:01:38.89#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.08:01:38.89#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.08:01:38.89#ibcon#ireg 11 cls_cnt 2 2006.145.08:01:38.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.08:01:38.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.08:01:38.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.08:01:38.97#ibcon#[25=AT07-04\r\n] 2006.145.08:01:39.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.08:01:39.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.08:01:39.00#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.08:01:39.00#ibcon#ireg 7 cls_cnt 0 2006.145.08:01:39.00#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.08:01:39.12#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.08:01:39.12#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.08:01:39.14#ibcon#[25=USB\r\n] 2006.145.08:01:39.17#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.08:01:39.17#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.08:01:39.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.08:01:39.17#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.08:01:39.17$vck44/valo=8,884.99 2006.145.08:01:39.17#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.08:01:39.17#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.08:01:39.17#ibcon#ireg 17 cls_cnt 0 2006.145.08:01:39.17#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.08:01:39.17#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.08:01:39.17#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.08:01:39.19#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.08:01:39.23#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.08:01:39.23#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.08:01:39.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.08:01:39.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.08:01:39.23$vck44/va=8,4 2006.145.08:01:39.23#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.08:01:39.23#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.08:01:39.23#ibcon#ireg 11 cls_cnt 2 2006.145.08:01:39.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.08:01:39.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.08:01:39.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.08:01:39.31#ibcon#[25=AT08-04\r\n] 2006.145.08:01:39.34#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.08:01:39.34#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.08:01:39.34#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.08:01:39.34#ibcon#ireg 7 cls_cnt 0 2006.145.08:01:39.34#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.08:01:39.46#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.08:01:39.46#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.08:01:39.48#ibcon#[25=USB\r\n] 2006.145.08:01:39.51#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.08:01:39.51#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.08:01:39.51#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.08:01:39.51#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.08:01:39.51$vck44/vblo=1,629.99 2006.145.08:01:39.51#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.08:01:39.51#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.08:01:39.51#ibcon#ireg 17 cls_cnt 0 2006.145.08:01:39.51#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.08:01:39.51#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.08:01:39.51#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.08:01:39.53#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.08:01:39.57#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.08:01:39.57#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.08:01:39.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.08:01:39.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.08:01:39.57$vck44/vb=1,3 2006.145.08:01:39.57#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.08:01:39.57#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.08:01:39.57#ibcon#ireg 11 cls_cnt 2 2006.145.08:01:39.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.08:01:39.57#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.08:01:39.57#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.08:01:39.59#ibcon#[27=AT01-03\r\n] 2006.145.08:01:39.62#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.08:01:39.62#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.08:01:39.62#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.08:01:39.62#ibcon#ireg 7 cls_cnt 0 2006.145.08:01:39.62#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.08:01:39.74#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.08:01:39.74#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.08:01:39.76#ibcon#[27=USB\r\n] 2006.145.08:01:39.79#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.08:01:39.79#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.08:01:39.79#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.08:01:39.79#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.08:01:39.79$vck44/vblo=2,634.99 2006.145.08:01:39.79#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.08:01:39.79#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.08:01:39.79#ibcon#ireg 17 cls_cnt 0 2006.145.08:01:39.79#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:01:39.79#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:01:39.79#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:01:39.81#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.08:01:39.85#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:01:39.85#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:01:39.85#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.08:01:39.85#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.08:01:39.85$vck44/vb=2,4 2006.145.08:01:39.85#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.08:01:39.85#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.08:01:39.85#ibcon#ireg 11 cls_cnt 2 2006.145.08:01:39.85#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:01:39.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:01:39.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:01:39.93#ibcon#[27=AT02-04\r\n] 2006.145.08:01:39.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:01:39.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:01:39.96#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.08:01:39.96#ibcon#ireg 7 cls_cnt 0 2006.145.08:01:39.96#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:01:40.08#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:01:40.08#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:01:40.10#ibcon#[27=USB\r\n] 2006.145.08:01:40.13#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:01:40.13#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:01:40.13#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.08:01:40.13#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.08:01:40.13$vck44/vblo=3,649.99 2006.145.08:01:40.13#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.08:01:40.13#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.08:01:40.13#ibcon#ireg 17 cls_cnt 0 2006.145.08:01:40.13#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:01:40.13#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:01:40.13#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:01:40.15#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.08:01:40.19#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:01:40.19#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:01:40.19#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.08:01:40.19#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.08:01:40.19$vck44/vb=3,4 2006.145.08:01:40.19#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.08:01:40.19#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.08:01:40.19#ibcon#ireg 11 cls_cnt 2 2006.145.08:01:40.19#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:01:40.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:01:40.25#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:01:40.27#ibcon#[27=AT03-04\r\n] 2006.145.08:01:40.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:01:40.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:01:40.30#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.08:01:40.30#ibcon#ireg 7 cls_cnt 0 2006.145.08:01:40.30#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:01:40.42#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:01:40.42#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:01:40.44#ibcon#[27=USB\r\n] 2006.145.08:01:40.47#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:01:40.47#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:01:40.47#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.08:01:40.47#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.08:01:40.47$vck44/vblo=4,679.99 2006.145.08:01:40.47#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.08:01:40.47#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.08:01:40.47#ibcon#ireg 17 cls_cnt 0 2006.145.08:01:40.47#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:01:40.47#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:01:40.47#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:01:40.49#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.08:01:40.53#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:01:40.53#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:01:40.53#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.08:01:40.53#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.08:01:40.53$vck44/vb=4,4 2006.145.08:01:40.53#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.08:01:40.53#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.08:01:40.53#ibcon#ireg 11 cls_cnt 2 2006.145.08:01:40.53#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:01:40.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:01:40.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:01:40.61#ibcon#[27=AT04-04\r\n] 2006.145.08:01:40.64#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:01:40.64#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:01:40.64#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.08:01:40.64#ibcon#ireg 7 cls_cnt 0 2006.145.08:01:40.64#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:01:40.76#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:01:40.76#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:01:40.78#ibcon#[27=USB\r\n] 2006.145.08:01:40.81#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:01:40.81#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:01:40.81#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.08:01:40.81#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.08:01:40.81$vck44/vblo=5,709.99 2006.145.08:01:40.81#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.08:01:40.81#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.08:01:40.81#ibcon#ireg 17 cls_cnt 0 2006.145.08:01:40.81#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:01:40.81#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:01:40.81#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:01:40.83#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.08:01:40.87#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:01:40.87#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:01:40.87#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.08:01:40.87#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.08:01:40.87$vck44/vb=5,4 2006.145.08:01:40.87#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.08:01:40.87#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.08:01:40.87#ibcon#ireg 11 cls_cnt 2 2006.145.08:01:40.87#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:01:40.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:01:40.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:01:40.95#ibcon#[27=AT05-04\r\n] 2006.145.08:01:40.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:01:40.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:01:40.98#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.08:01:40.98#ibcon#ireg 7 cls_cnt 0 2006.145.08:01:40.98#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:01:41.10#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:01:41.10#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:01:41.12#ibcon#[27=USB\r\n] 2006.145.08:01:41.15#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:01:41.15#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:01:41.15#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.08:01:41.15#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.08:01:41.15$vck44/vblo=6,719.99 2006.145.08:01:41.15#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.08:01:41.15#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.08:01:41.15#ibcon#ireg 17 cls_cnt 0 2006.145.08:01:41.15#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:01:41.15#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:01:41.15#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:01:41.17#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.08:01:41.21#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:01:41.21#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:01:41.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.08:01:41.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.08:01:41.21$vck44/vb=6,4 2006.145.08:01:41.21#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.08:01:41.21#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.08:01:41.21#ibcon#ireg 11 cls_cnt 2 2006.145.08:01:41.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:01:41.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:01:41.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:01:41.29#ibcon#[27=AT06-04\r\n] 2006.145.08:01:41.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:01:41.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:01:41.32#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.08:01:41.32#ibcon#ireg 7 cls_cnt 0 2006.145.08:01:41.32#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:01:41.44#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:01:41.44#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:01:41.46#ibcon#[27=USB\r\n] 2006.145.08:01:41.49#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:01:41.49#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:01:41.49#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.08:01:41.49#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.08:01:41.49$vck44/vblo=7,734.99 2006.145.08:01:41.49#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.08:01:41.49#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.08:01:41.49#ibcon#ireg 17 cls_cnt 0 2006.145.08:01:41.49#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:01:41.49#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:01:41.49#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:01:41.51#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.08:01:41.55#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:01:41.55#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:01:41.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.08:01:41.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.08:01:41.55$vck44/vb=7,4 2006.145.08:01:41.55#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.08:01:41.55#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.08:01:41.55#ibcon#ireg 11 cls_cnt 2 2006.145.08:01:41.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.08:01:41.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.08:01:41.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.08:01:41.63#ibcon#[27=AT07-04\r\n] 2006.145.08:01:41.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.08:01:41.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.08:01:41.66#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.08:01:41.66#ibcon#ireg 7 cls_cnt 0 2006.145.08:01:41.66#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.08:01:41.78#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.08:01:41.78#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.08:01:41.80#ibcon#[27=USB\r\n] 2006.145.08:01:41.83#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.08:01:41.83#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.08:01:41.83#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.08:01:41.83#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.08:01:41.83$vck44/vblo=8,744.99 2006.145.08:01:41.83#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.08:01:41.83#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.08:01:41.83#ibcon#ireg 17 cls_cnt 0 2006.145.08:01:41.83#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.08:01:41.83#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.08:01:41.83#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.08:01:41.85#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.08:01:41.89#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.08:01:41.89#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.08:01:41.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.08:01:41.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.08:01:41.89$vck44/vb=8,4 2006.145.08:01:41.89#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.08:01:41.89#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.08:01:41.89#ibcon#ireg 11 cls_cnt 2 2006.145.08:01:41.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.08:01:41.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.08:01:41.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.08:01:41.97#ibcon#[27=AT08-04\r\n] 2006.145.08:01:42.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.08:01:42.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.08:01:42.00#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.08:01:42.00#ibcon#ireg 7 cls_cnt 0 2006.145.08:01:42.00#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.08:01:42.12#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.08:01:42.12#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.08:01:42.14#ibcon#[27=USB\r\n] 2006.145.08:01:42.17#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.08:01:42.17#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.08:01:42.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.08:01:42.17#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.08:01:42.17$vck44/vabw=wide 2006.145.08:01:42.17#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.08:01:42.17#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.08:01:42.17#ibcon#ireg 8 cls_cnt 0 2006.145.08:01:42.17#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.08:01:42.17#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.08:01:42.17#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.08:01:42.19#ibcon#[25=BW32\r\n] 2006.145.08:01:42.22#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.08:01:42.22#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.08:01:42.22#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.08:01:42.22#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.08:01:42.22$vck44/vbbw=wide 2006.145.08:01:42.22#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.08:01:42.22#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.08:01:42.22#ibcon#ireg 8 cls_cnt 0 2006.145.08:01:42.22#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.08:01:42.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.08:01:42.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.08:01:42.31#ibcon#[27=BW32\r\n] 2006.145.08:01:42.34#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.08:01:42.34#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.08:01:42.34#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.08:01:42.34#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.08:01:42.34$setupk4/ifdk4 2006.145.08:01:42.34$ifdk4/lo= 2006.145.08:01:42.34$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.08:01:42.34$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.08:01:42.34$ifdk4/patch= 2006.145.08:01:42.34$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.08:01:42.34$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.08:01:42.34$setupk4/!*+20s 2006.145.08:01:46.79#abcon#<5=/04 4.6 8.3 18.81 661017.4\r\n> 2006.145.08:01:46.81#abcon#{5=INTERFACE CLEAR} 2006.145.08:01:46.87#abcon#[5=S1D000X0/0*\r\n] 2006.145.08:01:56.14#trakl#Source acquired 2006.145.08:01:56.14#flagr#flagr/antenna,acquired 2006.145.08:01:56.81$setupk4/"tpicd 2006.145.08:01:56.81$setupk4/echo=off 2006.145.08:01:56.81$setupk4/xlog=off 2006.145.08:01:56.81:!2006.145.08:02:25 2006.145.08:02:25.00:preob 2006.145.08:02:25.14/onsource/TRACKING 2006.145.08:02:25.14:!2006.145.08:02:35 2006.145.08:02:35.00:"tape 2006.145.08:02:35.00:"st=record 2006.145.08:02:35.00:data_valid=on 2006.145.08:02:35.00:midob 2006.145.08:02:35.14/onsource/TRACKING 2006.145.08:02:35.14/wx/18.81,1017.3,64 2006.145.08:02:35.32/cable/+6.5403E-03 2006.145.08:02:36.41/va/01,08,usb,yes,31,33 2006.145.08:02:36.41/va/02,07,usb,yes,33,34 2006.145.08:02:36.41/va/03,08,usb,yes,30,31 2006.145.08:02:36.41/va/04,07,usb,yes,34,36 2006.145.08:02:36.41/va/05,04,usb,yes,30,30 2006.145.08:02:36.41/va/06,04,usb,yes,33,33 2006.145.08:02:36.41/va/07,04,usb,yes,34,35 2006.145.08:02:36.41/va/08,04,usb,yes,29,34 2006.145.08:02:36.64/valo/01,524.99,yes,locked 2006.145.08:02:36.64/valo/02,534.99,yes,locked 2006.145.08:02:36.64/valo/03,564.99,yes,locked 2006.145.08:02:36.64/valo/04,624.99,yes,locked 2006.145.08:02:36.64/valo/05,734.99,yes,locked 2006.145.08:02:36.64/valo/06,814.99,yes,locked 2006.145.08:02:36.64/valo/07,864.99,yes,locked 2006.145.08:02:36.64/valo/08,884.99,yes,locked 2006.145.08:02:37.73/vb/01,03,usb,yes,44,41 2006.145.08:02:37.73/vb/02,04,usb,yes,39,39 2006.145.08:02:37.73/vb/03,04,usb,yes,35,39 2006.145.08:02:37.73/vb/04,04,usb,yes,40,39 2006.145.08:02:37.73/vb/05,04,usb,yes,32,35 2006.145.08:02:37.73/vb/06,04,usb,yes,37,32 2006.145.08:02:37.73/vb/07,04,usb,yes,36,36 2006.145.08:02:37.73/vb/08,04,usb,yes,33,37 2006.145.08:02:37.97/vblo/01,629.99,yes,locked 2006.145.08:02:37.97/vblo/02,634.99,yes,locked 2006.145.08:02:37.97/vblo/03,649.99,yes,locked 2006.145.08:02:37.97/vblo/04,679.99,yes,locked 2006.145.08:02:37.97/vblo/05,709.99,yes,locked 2006.145.08:02:37.97/vblo/06,719.99,yes,locked 2006.145.08:02:37.97/vblo/07,734.99,yes,locked 2006.145.08:02:37.97/vblo/08,744.99,yes,locked 2006.145.08:02:38.12/vabw/8 2006.145.08:02:38.27/vbbw/8 2006.145.08:02:38.36/xfe/off,on,15.0 2006.145.08:02:38.75/ifatt/23,28,28,28 2006.145.08:02:39.08/fmout-gps/S +5.9E-08 2006.145.08:02:39.12:!2006.145.08:03:55 2006.145.08:03:55.00:data_valid=off 2006.145.08:03:55.00:"et 2006.145.08:03:55.00:!+3s 2006.145.08:03:58.02:"tape 2006.145.08:03:58.02:postob 2006.145.08:03:58.24/cable/+6.5403E-03 2006.145.08:03:58.24/wx/18.79,1017.4,65 2006.145.08:03:58.32/fmout-gps/S +5.8E-08 2006.145.08:03:58.32:scan_name=145-0808,jd0605,130 2006.145.08:03:58.33:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.145.08:03:59.14#flagr#flagr/antenna,new-source 2006.145.08:03:59.14:checkk5 2006.145.08:03:59.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.08:04:00.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.08:04:00.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.08:04:00.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.08:04:01.31/chk_obsdata//k5ts1/T1450802??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.08:04:01.76/chk_obsdata//k5ts2/T1450802??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.08:04:02.19/chk_obsdata//k5ts3/T1450802??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.08:04:02.62/chk_obsdata//k5ts4/T1450802??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.08:04:03.39/k5log//k5ts1_log_newline 2006.145.08:04:04.13/k5log//k5ts2_log_newline 2006.145.08:04:04.87/k5log//k5ts3_log_newline 2006.145.08:04:05.61/k5log//k5ts4_log_newline 2006.145.08:04:05.64/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.08:04:05.64:setupk4=1 2006.145.08:04:05.64$setupk4/echo=on 2006.145.08:04:05.64$setupk4/pcalon 2006.145.08:04:05.64$pcalon/"no phase cal control is implemented here 2006.145.08:04:05.64$setupk4/"tpicd=stop 2006.145.08:04:05.64$setupk4/"rec=synch_on 2006.145.08:04:05.64$setupk4/"rec_mode=128 2006.145.08:04:05.64$setupk4/!* 2006.145.08:04:05.64$setupk4/recpk4 2006.145.08:04:05.64$recpk4/recpatch= 2006.145.08:04:05.64$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.08:04:05.64$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.08:04:05.64$setupk4/vck44 2006.145.08:04:05.64$vck44/valo=1,524.99 2006.145.08:04:05.64#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.08:04:05.64#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.08:04:05.64#ibcon#ireg 17 cls_cnt 0 2006.145.08:04:05.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:04:05.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:04:05.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:04:05.68#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.08:04:05.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:04:05.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:04:05.73#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.08:04:05.73#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.08:04:05.73$vck44/va=1,8 2006.145.08:04:05.73#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.08:04:05.73#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.08:04:05.73#ibcon#ireg 11 cls_cnt 2 2006.145.08:04:05.73#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:04:05.73#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:04:05.73#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:04:05.75#ibcon#[25=AT01-08\r\n] 2006.145.08:04:05.78#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:04:05.78#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:04:05.78#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.08:04:05.78#ibcon#ireg 7 cls_cnt 0 2006.145.08:04:05.78#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:04:05.90#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:04:05.90#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:04:05.92#ibcon#[25=USB\r\n] 2006.145.08:04:05.95#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:04:05.95#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:04:05.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.08:04:05.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.08:04:05.95$vck44/valo=2,534.99 2006.145.08:04:05.95#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.08:04:05.95#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.08:04:05.95#ibcon#ireg 17 cls_cnt 0 2006.145.08:04:05.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:04:05.95#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:04:05.95#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:04:05.98#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.08:04:06.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:04:06.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:04:06.02#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.08:04:06.02#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.08:04:06.02$vck44/va=2,7 2006.145.08:04:06.02#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.08:04:06.02#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.08:04:06.02#ibcon#ireg 11 cls_cnt 2 2006.145.08:04:06.02#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:04:06.07#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:04:06.07#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:04:06.09#ibcon#[25=AT02-07\r\n] 2006.145.08:04:06.12#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:04:06.12#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:04:06.12#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.08:04:06.12#ibcon#ireg 7 cls_cnt 0 2006.145.08:04:06.12#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:04:06.24#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:04:06.24#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:04:06.26#ibcon#[25=USB\r\n] 2006.145.08:04:06.29#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:04:06.29#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:04:06.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.08:04:06.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.08:04:06.29$vck44/valo=3,564.99 2006.145.08:04:06.29#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.08:04:06.29#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.08:04:06.29#ibcon#ireg 17 cls_cnt 0 2006.145.08:04:06.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:04:06.29#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:04:06.29#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:04:06.31#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.08:04:06.35#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:04:06.35#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:04:06.35#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.08:04:06.35#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.08:04:06.35$vck44/va=3,8 2006.145.08:04:06.35#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.08:04:06.35#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.08:04:06.35#ibcon#ireg 11 cls_cnt 2 2006.145.08:04:06.35#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:04:06.41#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:04:06.41#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:04:06.43#ibcon#[25=AT03-08\r\n] 2006.145.08:04:06.46#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:04:06.46#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:04:06.46#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.08:04:06.46#ibcon#ireg 7 cls_cnt 0 2006.145.08:04:06.46#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:04:06.58#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:04:06.58#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:04:06.60#ibcon#[25=USB\r\n] 2006.145.08:04:06.63#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:04:06.63#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:04:06.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.08:04:06.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.08:04:06.63$vck44/valo=4,624.99 2006.145.08:04:06.63#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.08:04:06.63#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.08:04:06.63#ibcon#ireg 17 cls_cnt 0 2006.145.08:04:06.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:04:06.63#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:04:06.63#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:04:06.65#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.08:04:06.69#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:04:06.69#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:04:06.69#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.08:04:06.69#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.08:04:06.69$vck44/va=4,7 2006.145.08:04:06.69#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.08:04:06.69#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.08:04:06.69#ibcon#ireg 11 cls_cnt 2 2006.145.08:04:06.69#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:04:06.75#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:04:06.75#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:04:06.77#ibcon#[25=AT04-07\r\n] 2006.145.08:04:06.80#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:04:06.80#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:04:06.80#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.08:04:06.80#ibcon#ireg 7 cls_cnt 0 2006.145.08:04:06.80#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:04:06.92#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:04:06.92#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:04:06.94#ibcon#[25=USB\r\n] 2006.145.08:04:06.97#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:04:06.97#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:04:06.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.08:04:06.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.08:04:06.97$vck44/valo=5,734.99 2006.145.08:04:06.97#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.08:04:06.97#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.08:04:06.97#ibcon#ireg 17 cls_cnt 0 2006.145.08:04:06.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:04:06.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:04:06.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:04:06.99#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.08:04:07.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:04:07.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:04:07.03#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.08:04:07.03#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.08:04:07.03$vck44/va=5,4 2006.145.08:04:07.03#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.08:04:07.03#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.08:04:07.03#ibcon#ireg 11 cls_cnt 2 2006.145.08:04:07.03#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:04:07.09#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:04:07.09#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:04:07.11#ibcon#[25=AT05-04\r\n] 2006.145.08:04:07.14#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:04:07.14#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:04:07.14#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.08:04:07.14#ibcon#ireg 7 cls_cnt 0 2006.145.08:04:07.14#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:04:07.26#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:04:07.26#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:04:07.28#ibcon#[25=USB\r\n] 2006.145.08:04:07.31#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:04:07.31#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:04:07.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.08:04:07.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.08:04:07.31$vck44/valo=6,814.99 2006.145.08:04:07.31#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.08:04:07.31#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.08:04:07.31#ibcon#ireg 17 cls_cnt 0 2006.145.08:04:07.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:04:07.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:04:07.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:04:07.34#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.08:04:07.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:04:07.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:04:07.38#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.08:04:07.38#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.08:04:07.38$vck44/va=6,4 2006.145.08:04:07.38#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.08:04:07.38#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.08:04:07.38#ibcon#ireg 11 cls_cnt 2 2006.145.08:04:07.38#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:04:07.43#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:04:07.43#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:04:07.45#ibcon#[25=AT06-04\r\n] 2006.145.08:04:07.48#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:04:07.48#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:04:07.48#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.08:04:07.48#ibcon#ireg 7 cls_cnt 0 2006.145.08:04:07.48#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:04:07.60#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:04:07.60#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:04:07.62#ibcon#[25=USB\r\n] 2006.145.08:04:07.65#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:04:07.65#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:04:07.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.08:04:07.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.08:04:07.65$vck44/valo=7,864.99 2006.145.08:04:07.65#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.08:04:07.65#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.08:04:07.65#ibcon#ireg 17 cls_cnt 0 2006.145.08:04:07.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:04:07.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:04:07.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:04:07.67#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.08:04:07.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:04:07.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:04:07.71#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.08:04:07.71#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.08:04:07.71$vck44/va=7,4 2006.145.08:04:07.71#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.08:04:07.71#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.08:04:07.71#ibcon#ireg 11 cls_cnt 2 2006.145.08:04:07.71#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:04:07.77#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:04:07.77#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:04:07.79#ibcon#[25=AT07-04\r\n] 2006.145.08:04:07.82#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:04:07.82#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:04:07.82#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.08:04:07.82#ibcon#ireg 7 cls_cnt 0 2006.145.08:04:07.82#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:04:07.94#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:04:07.94#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:04:07.96#ibcon#[25=USB\r\n] 2006.145.08:04:07.99#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:04:07.99#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:04:07.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.08:04:07.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.08:04:07.99$vck44/valo=8,884.99 2006.145.08:04:07.99#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.08:04:07.99#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.08:04:07.99#ibcon#ireg 17 cls_cnt 0 2006.145.08:04:07.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:04:07.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:04:07.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:04:08.01#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.08:04:08.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:04:08.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:04:08.05#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.08:04:08.05#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.08:04:08.05$vck44/va=8,4 2006.145.08:04:08.05#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.08:04:08.05#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.08:04:08.05#ibcon#ireg 11 cls_cnt 2 2006.145.08:04:08.05#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:04:08.11#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:04:08.11#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:04:08.13#ibcon#[25=AT08-04\r\n] 2006.145.08:04:08.16#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:04:08.16#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:04:08.16#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.08:04:08.16#ibcon#ireg 7 cls_cnt 0 2006.145.08:04:08.16#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:04:08.28#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:04:08.28#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:04:08.30#ibcon#[25=USB\r\n] 2006.145.08:04:08.33#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:04:08.33#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:04:08.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.08:04:08.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.08:04:08.33$vck44/vblo=1,629.99 2006.145.08:04:08.33#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.08:04:08.33#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.08:04:08.33#ibcon#ireg 17 cls_cnt 0 2006.145.08:04:08.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:04:08.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:04:08.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:04:08.35#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.08:04:08.40#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:04:08.40#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:04:08.40#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.08:04:08.40#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.08:04:08.40$vck44/vb=1,3 2006.145.08:04:08.40#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.08:04:08.40#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.08:04:08.40#ibcon#ireg 11 cls_cnt 2 2006.145.08:04:08.40#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.08:04:08.40#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.08:04:08.40#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.08:04:08.42#ibcon#[27=AT01-03\r\n] 2006.145.08:04:08.45#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.08:04:08.45#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.08:04:08.45#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.08:04:08.45#ibcon#ireg 7 cls_cnt 0 2006.145.08:04:08.45#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.08:04:08.57#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.08:04:08.57#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.08:04:08.59#ibcon#[27=USB\r\n] 2006.145.08:04:08.62#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.08:04:08.62#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.08:04:08.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.08:04:08.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.08:04:08.62$vck44/vblo=2,634.99 2006.145.08:04:08.62#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.08:04:08.62#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.08:04:08.62#ibcon#ireg 17 cls_cnt 0 2006.145.08:04:08.62#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:04:08.62#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:04:08.62#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:04:08.64#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.08:04:08.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:04:08.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:04:08.68#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.08:04:08.68#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.08:04:08.68$vck44/vb=2,4 2006.145.08:04:08.68#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.08:04:08.68#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.08:04:08.68#ibcon#ireg 11 cls_cnt 2 2006.145.08:04:08.68#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:04:08.74#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:04:08.74#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:04:08.76#ibcon#[27=AT02-04\r\n] 2006.145.08:04:08.79#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:04:08.79#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:04:08.79#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.08:04:08.79#ibcon#ireg 7 cls_cnt 0 2006.145.08:04:08.79#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:04:08.91#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:04:08.91#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:04:08.93#ibcon#[27=USB\r\n] 2006.145.08:04:08.96#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:04:08.96#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:04:08.96#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.08:04:08.96#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.08:04:08.96$vck44/vblo=3,649.99 2006.145.08:04:08.96#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.08:04:08.96#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.08:04:08.96#ibcon#ireg 17 cls_cnt 0 2006.145.08:04:08.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:04:08.96#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:04:08.96#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:04:08.98#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.08:04:09.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:04:09.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:04:09.02#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.08:04:09.02#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.08:04:09.02$vck44/vb=3,4 2006.145.08:04:09.02#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.08:04:09.02#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.08:04:09.02#ibcon#ireg 11 cls_cnt 2 2006.145.08:04:09.02#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:04:09.08#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:04:09.08#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:04:09.10#ibcon#[27=AT03-04\r\n] 2006.145.08:04:09.13#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:04:09.13#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:04:09.13#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.08:04:09.13#ibcon#ireg 7 cls_cnt 0 2006.145.08:04:09.13#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:04:09.17#abcon#<5=/04 4.6 7.5 18.79 651017.4\r\n> 2006.145.08:04:09.19#abcon#{5=INTERFACE CLEAR} 2006.145.08:04:09.25#abcon#[5=S1D000X0/0*\r\n] 2006.145.08:04:09.25#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:04:09.25#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:04:09.27#ibcon#[27=USB\r\n] 2006.145.08:04:09.30#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:04:09.30#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:04:09.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.08:04:09.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.08:04:09.30$vck44/vblo=4,679.99 2006.145.08:04:09.30#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.08:04:09.30#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.08:04:09.30#ibcon#ireg 17 cls_cnt 0 2006.145.08:04:09.30#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:04:09.30#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:04:09.30#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:04:09.32#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.08:04:09.36#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:04:09.36#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:04:09.36#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.08:04:09.36#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.08:04:09.36$vck44/vb=4,4 2006.145.08:04:09.36#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.08:04:09.36#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.08:04:09.36#ibcon#ireg 11 cls_cnt 2 2006.145.08:04:09.36#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:04:09.42#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:04:09.42#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:04:09.44#ibcon#[27=AT04-04\r\n] 2006.145.08:04:09.47#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:04:09.47#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:04:09.47#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.08:04:09.47#ibcon#ireg 7 cls_cnt 0 2006.145.08:04:09.47#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:04:09.59#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:04:09.59#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:04:09.61#ibcon#[27=USB\r\n] 2006.145.08:04:09.64#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:04:09.64#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:04:09.64#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.08:04:09.64#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.08:04:09.64$vck44/vblo=5,709.99 2006.145.08:04:09.64#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.08:04:09.64#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.08:04:09.64#ibcon#ireg 17 cls_cnt 0 2006.145.08:04:09.64#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:04:09.64#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:04:09.64#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:04:09.66#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.08:04:09.70#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:04:09.70#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:04:09.70#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.08:04:09.70#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.08:04:09.70$vck44/vb=5,4 2006.145.08:04:09.70#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.08:04:09.70#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.08:04:09.70#ibcon#ireg 11 cls_cnt 2 2006.145.08:04:09.70#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:04:09.76#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:04:09.76#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:04:09.78#ibcon#[27=AT05-04\r\n] 2006.145.08:04:09.81#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:04:09.81#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:04:09.81#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.08:04:09.81#ibcon#ireg 7 cls_cnt 0 2006.145.08:04:09.81#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:04:09.93#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:04:09.93#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:04:09.95#ibcon#[27=USB\r\n] 2006.145.08:04:09.98#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:04:09.98#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:04:09.98#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.08:04:09.98#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.08:04:09.98$vck44/vblo=6,719.99 2006.145.08:04:09.98#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.08:04:09.98#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.08:04:09.98#ibcon#ireg 17 cls_cnt 0 2006.145.08:04:09.98#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:04:09.98#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:04:09.98#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:04:10.00#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.08:04:10.04#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:04:10.04#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:04:10.04#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.08:04:10.04#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.08:04:10.04$vck44/vb=6,4 2006.145.08:04:10.04#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.08:04:10.04#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.08:04:10.04#ibcon#ireg 11 cls_cnt 2 2006.145.08:04:10.04#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:04:10.10#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:04:10.10#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:04:10.12#ibcon#[27=AT06-04\r\n] 2006.145.08:04:10.15#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:04:10.15#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:04:10.15#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.08:04:10.15#ibcon#ireg 7 cls_cnt 0 2006.145.08:04:10.15#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:04:10.27#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:04:10.27#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:04:10.29#ibcon#[27=USB\r\n] 2006.145.08:04:10.32#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:04:10.32#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:04:10.32#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.08:04:10.32#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.08:04:10.32$vck44/vblo=7,734.99 2006.145.08:04:10.32#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.08:04:10.32#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.08:04:10.32#ibcon#ireg 17 cls_cnt 0 2006.145.08:04:10.32#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:04:10.32#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:04:10.32#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:04:10.34#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.08:04:10.38#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:04:10.38#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:04:10.38#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.08:04:10.38#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.08:04:10.38$vck44/vb=7,4 2006.145.08:04:10.38#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.08:04:10.38#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.08:04:10.38#ibcon#ireg 11 cls_cnt 2 2006.145.08:04:10.38#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:04:10.44#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:04:10.44#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:04:10.46#ibcon#[27=AT07-04\r\n] 2006.145.08:04:10.49#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:04:10.49#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:04:10.49#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.08:04:10.49#ibcon#ireg 7 cls_cnt 0 2006.145.08:04:10.49#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:04:10.61#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:04:10.61#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:04:10.63#ibcon#[27=USB\r\n] 2006.145.08:04:10.66#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:04:10.66#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:04:10.66#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.08:04:10.66#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.08:04:10.66$vck44/vblo=8,744.99 2006.145.08:04:10.66#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.08:04:10.66#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.08:04:10.66#ibcon#ireg 17 cls_cnt 0 2006.145.08:04:10.66#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:04:10.66#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:04:10.66#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:04:10.68#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.08:04:10.72#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:04:10.72#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:04:10.72#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.08:04:10.72#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.08:04:10.72$vck44/vb=8,4 2006.145.08:04:10.72#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.08:04:10.72#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.08:04:10.72#ibcon#ireg 11 cls_cnt 2 2006.145.08:04:10.72#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:04:10.78#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:04:10.78#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:04:10.80#ibcon#[27=AT08-04\r\n] 2006.145.08:04:10.83#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:04:10.83#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:04:10.83#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.08:04:10.83#ibcon#ireg 7 cls_cnt 0 2006.145.08:04:10.83#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:04:10.95#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:04:10.95#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:04:10.97#ibcon#[27=USB\r\n] 2006.145.08:04:11.00#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:04:11.00#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:04:11.00#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.08:04:11.00#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.08:04:11.00$vck44/vabw=wide 2006.145.08:04:11.00#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.08:04:11.00#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.08:04:11.00#ibcon#ireg 8 cls_cnt 0 2006.145.08:04:11.00#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:04:11.00#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:04:11.00#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:04:11.02#ibcon#[25=BW32\r\n] 2006.145.08:04:11.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:04:11.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:04:11.05#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.08:04:11.05#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.08:04:11.05$vck44/vbbw=wide 2006.145.08:04:11.05#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.08:04:11.05#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.08:04:11.05#ibcon#ireg 8 cls_cnt 0 2006.145.08:04:11.05#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:04:11.12#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:04:11.12#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:04:11.14#ibcon#[27=BW32\r\n] 2006.145.08:04:11.17#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:04:11.17#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:04:11.17#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.08:04:11.17#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.08:04:11.17$setupk4/ifdk4 2006.145.08:04:11.17$ifdk4/lo= 2006.145.08:04:11.17$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.08:04:11.17$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.08:04:11.17$ifdk4/patch= 2006.145.08:04:11.17$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.08:04:11.17$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.08:04:11.17$setupk4/!*+20s 2006.145.08:04:19.34#abcon#<5=/04 4.6 7.5 18.78 641017.4\r\n> 2006.145.08:04:19.36#abcon#{5=INTERFACE CLEAR} 2006.145.08:04:19.42#abcon#[5=S1D000X0/0*\r\n] 2006.145.08:04:21.14#trakl#Source acquired 2006.145.08:04:21.14#flagr#flagr/antenna,acquired 2006.145.08:04:22.14#trakl#Off source 2006.145.08:04:22.14?ERROR st -7 Antenna off-source! 2006.145.08:04:22.14#trakl#az 118.656 el 14.759 azerr*cos(el) 0.0177 elerr -0.0068 2006.145.08:04:24.14#flagr#flagr/antenna,off-source 2006.145.08:04:25.65$setupk4/"tpicd 2006.145.08:04:25.65$setupk4/echo=off 2006.145.08:04:25.65$setupk4/xlog=off 2006.145.08:04:25.65:!2006.145.08:07:51 2006.145.08:04:28.14#trakl#Source re-acquired 2006.145.08:04:30.14#flagr#flagr/antenna,re-acquired 2006.145.08:07:51.00:preob 2006.145.08:07:52.13/onsource/TRACKING 2006.145.08:07:52.13:!2006.145.08:08:01 2006.145.08:08:01.00:"tape 2006.145.08:08:01.00:"st=record 2006.145.08:08:01.00:data_valid=on 2006.145.08:08:01.00:midob 2006.145.08:08:01.14/onsource/TRACKING 2006.145.08:08:01.14/wx/18.75,1017.4,65 2006.145.08:08:01.21/cable/+6.5384E-03 2006.145.08:08:02.30/va/01,08,usb,yes,31,33 2006.145.08:08:02.30/va/02,07,usb,yes,33,34 2006.145.08:08:02.30/va/03,08,usb,yes,30,31 2006.145.08:08:02.30/va/04,07,usb,yes,34,36 2006.145.08:08:02.30/va/05,04,usb,yes,30,30 2006.145.08:08:02.30/va/06,04,usb,yes,33,33 2006.145.08:08:02.30/va/07,04,usb,yes,34,35 2006.145.08:08:02.30/va/08,04,usb,yes,29,34 2006.145.08:08:02.53/valo/01,524.99,yes,locked 2006.145.08:08:02.53/valo/02,534.99,yes,locked 2006.145.08:08:02.53/valo/03,564.99,yes,locked 2006.145.08:08:02.53/valo/04,624.99,yes,locked 2006.145.08:08:02.53/valo/05,734.99,yes,locked 2006.145.08:08:02.53/valo/06,814.99,yes,locked 2006.145.08:08:02.53/valo/07,864.99,yes,locked 2006.145.08:08:02.53/valo/08,884.99,yes,locked 2006.145.08:08:03.62/vb/01,03,usb,yes,37,34 2006.145.08:08:03.62/vb/02,04,usb,yes,32,32 2006.145.08:08:03.62/vb/03,04,usb,yes,29,32 2006.145.08:08:03.62/vb/04,04,usb,yes,34,32 2006.145.08:08:03.62/vb/05,04,usb,yes,26,29 2006.145.08:08:03.62/vb/06,04,usb,yes,31,27 2006.145.08:08:03.62/vb/07,04,usb,yes,30,30 2006.145.08:08:03.62/vb/08,04,usb,yes,28,31 2006.145.08:08:03.85/vblo/01,629.99,yes,locked 2006.145.08:08:03.85/vblo/02,634.99,yes,locked 2006.145.08:08:03.85/vblo/03,649.99,yes,locked 2006.145.08:08:03.85/vblo/04,679.99,yes,locked 2006.145.08:08:03.85/vblo/05,709.99,yes,locked 2006.145.08:08:03.85/vblo/06,719.99,yes,locked 2006.145.08:08:03.85/vblo/07,734.99,yes,locked 2006.145.08:08:03.85/vblo/08,744.99,yes,locked 2006.145.08:08:04.00/vabw/8 2006.145.08:08:04.15/vbbw/8 2006.145.08:08:04.24/xfe/off,on,14.5 2006.145.08:08:04.63/ifatt/23,28,28,28 2006.145.08:08:05.08/fmout-gps/S +5.5E-08 2006.145.08:08:05.12:!2006.145.08:10:11 2006.145.08:10:11.00:data_valid=off 2006.145.08:10:11.00:"et 2006.145.08:10:11.00:!+3s 2006.145.08:10:14.02:"tape 2006.145.08:10:14.02:postob 2006.145.08:10:14.10/cable/+6.5404E-03 2006.145.08:10:14.10/wx/18.74,1017.4,64 2006.145.08:10:15.08/fmout-gps/S +5.5E-08 2006.145.08:10:15.08:scan_name=145-0812,jd0605,60 2006.145.08:10:15.08:source=0727-115,073019.11,-114112.6,2000.0,cw 2006.145.08:10:16.14#flagr#flagr/antenna,new-source 2006.145.08:10:16.14:checkk5 2006.145.08:10:16.62/chk_autoobs//k5ts1/ autoobs is running! 2006.145.08:10:17.06/chk_autoobs//k5ts2/ autoobs is running! 2006.145.08:10:17.51/chk_autoobs//k5ts3/ autoobs is running! 2006.145.08:10:17.94/chk_autoobs//k5ts4/ autoobs is running! 2006.145.08:10:18.36/chk_obsdata//k5ts1/T1450808??a.dat file size is correct (nominal:520MB, actual:520MB). 2006.145.08:10:18.80/chk_obsdata//k5ts2/T1450808??b.dat file size is correct (nominal:520MB, actual:520MB). 2006.145.08:10:19.26/chk_obsdata//k5ts3/T1450808??c.dat file size is correct (nominal:520MB, actual:520MB). 2006.145.08:10:19.69/chk_obsdata//k5ts4/T1450808??d.dat file size is correct (nominal:520MB, actual:520MB). 2006.145.08:10:20.44/k5log//k5ts1_log_newline 2006.145.08:10:21.20/k5log//k5ts2_log_newline 2006.145.08:10:21.94/k5log//k5ts3_log_newline 2006.145.08:10:22.68/k5log//k5ts4_log_newline 2006.145.08:10:22.70/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.08:10:22.71:setupk4=1 2006.145.08:10:22.71$setupk4/echo=on 2006.145.08:10:22.71$setupk4/pcalon 2006.145.08:10:22.71$pcalon/"no phase cal control is implemented here 2006.145.08:10:22.71$setupk4/"tpicd=stop 2006.145.08:10:22.71$setupk4/"rec=synch_on 2006.145.08:10:22.71$setupk4/"rec_mode=128 2006.145.08:10:22.71$setupk4/!* 2006.145.08:10:22.71$setupk4/recpk4 2006.145.08:10:22.71$recpk4/recpatch= 2006.145.08:10:22.71$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.08:10:22.71$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.08:10:22.71$setupk4/vck44 2006.145.08:10:22.72$vck44/valo=1,524.99 2006.145.08:10:22.72#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.08:10:22.72#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.08:10:22.72#ibcon#ireg 17 cls_cnt 0 2006.145.08:10:22.72#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.08:10:22.72#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.08:10:22.72#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.08:10:22.75#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.08:10:22.80#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.08:10:22.80#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.08:10:22.80#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.08:10:22.80#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.08:10:22.80$vck44/va=1,8 2006.145.08:10:22.80#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.08:10:22.80#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.08:10:22.80#ibcon#ireg 11 cls_cnt 2 2006.145.08:10:22.80#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.08:10:22.80#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.08:10:22.80#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.08:10:22.82#ibcon#[25=AT01-08\r\n] 2006.145.08:10:22.85#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.08:10:22.85#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.08:10:22.85#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.08:10:22.85#ibcon#ireg 7 cls_cnt 0 2006.145.08:10:22.85#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.08:10:22.96#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.08:10:22.97#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.08:10:22.99#ibcon#[25=USB\r\n] 2006.145.08:10:23.03#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.08:10:23.03#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.08:10:23.03#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.08:10:23.03#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.08:10:23.04$vck44/valo=2,534.99 2006.145.08:10:23.04#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.08:10:23.04#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.08:10:23.04#ibcon#ireg 17 cls_cnt 0 2006.145.08:10:23.04#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.08:10:23.04#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.08:10:23.04#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.08:10:23.06#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.08:10:23.10#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.08:10:23.10#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.08:10:23.10#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.08:10:23.10#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.08:10:23.10$vck44/va=2,7 2006.145.08:10:23.10#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.08:10:23.10#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.08:10:23.10#ibcon#ireg 11 cls_cnt 2 2006.145.08:10:23.10#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.08:10:23.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.08:10:23.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.08:10:23.17#ibcon#[25=AT02-07\r\n] 2006.145.08:10:23.20#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.08:10:23.20#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.08:10:23.20#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.08:10:23.20#ibcon#ireg 7 cls_cnt 0 2006.145.08:10:23.20#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.08:10:23.31#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.08:10:23.32#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.08:10:23.34#ibcon#[25=USB\r\n] 2006.145.08:10:23.37#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.08:10:23.37#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.08:10:23.37#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.08:10:23.37#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.08:10:23.37$vck44/valo=3,564.99 2006.145.08:10:23.37#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.08:10:23.37#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.08:10:23.37#ibcon#ireg 17 cls_cnt 0 2006.145.08:10:23.37#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.08:10:23.37#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.08:10:23.37#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.08:10:23.39#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.08:10:23.43#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.08:10:23.43#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.08:10:23.43#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.08:10:23.43#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.08:10:23.43$vck44/va=3,8 2006.145.08:10:23.43#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.08:10:23.43#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.08:10:23.43#ibcon#ireg 11 cls_cnt 2 2006.145.08:10:23.43#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.08:10:23.48#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.08:10:23.49#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.08:10:23.51#ibcon#[25=AT03-08\r\n] 2006.145.08:10:23.54#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.08:10:23.54#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.08:10:23.54#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.08:10:23.54#ibcon#ireg 7 cls_cnt 0 2006.145.08:10:23.54#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.08:10:23.65#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.08:10:23.66#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.08:10:23.68#ibcon#[25=USB\r\n] 2006.145.08:10:23.71#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.08:10:23.71#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.08:10:23.71#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.08:10:23.71#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.08:10:23.71$vck44/valo=4,624.99 2006.145.08:10:23.71#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.08:10:23.71#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.08:10:23.71#ibcon#ireg 17 cls_cnt 0 2006.145.08:10:23.71#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:10:23.71#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:10:23.71#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:10:23.72#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.08:10:23.77#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:10:23.77#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:10:23.77#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.08:10:23.77#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.08:10:23.77$vck44/va=4,7 2006.145.08:10:23.77#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.08:10:23.77#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.08:10:23.77#ibcon#ireg 11 cls_cnt 2 2006.145.08:10:23.77#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:10:23.82#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:10:23.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:10:23.85#ibcon#[25=AT04-07\r\n] 2006.145.08:10:23.87#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:10:23.88#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:10:23.88#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.08:10:23.88#ibcon#ireg 7 cls_cnt 0 2006.145.08:10:23.88#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:10:23.99#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:10:24.00#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:10:24.02#ibcon#[25=USB\r\n] 2006.145.08:10:24.05#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:10:24.05#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:10:24.05#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.08:10:24.05#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.08:10:24.05$vck44/valo=5,734.99 2006.145.08:10:24.05#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.08:10:24.05#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.08:10:24.05#ibcon#ireg 17 cls_cnt 0 2006.145.08:10:24.05#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:10:24.05#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:10:24.05#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:10:24.07#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.08:10:24.11#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:10:24.11#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:10:24.11#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.08:10:24.11#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.08:10:24.11$vck44/va=5,4 2006.145.08:10:24.11#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.08:10:24.11#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.08:10:24.11#ibcon#ireg 11 cls_cnt 2 2006.145.08:10:24.11#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:10:24.17#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:10:24.17#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:10:24.19#ibcon#[25=AT05-04\r\n] 2006.145.08:10:24.22#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:10:24.22#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:10:24.22#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.08:10:24.22#ibcon#ireg 7 cls_cnt 0 2006.145.08:10:24.22#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:10:24.33#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:10:24.34#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:10:24.36#ibcon#[25=USB\r\n] 2006.145.08:10:24.39#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:10:24.39#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:10:24.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.08:10:24.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.08:10:24.39$vck44/valo=6,814.99 2006.145.08:10:24.39#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.08:10:24.39#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.08:10:24.39#ibcon#ireg 17 cls_cnt 0 2006.145.08:10:24.39#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:10:24.39#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:10:24.39#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:10:24.41#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.08:10:24.45#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:10:24.45#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:10:24.45#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.08:10:24.45#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.08:10:24.45$vck44/va=6,4 2006.145.08:10:24.45#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.08:10:24.45#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.08:10:24.45#ibcon#ireg 11 cls_cnt 2 2006.145.08:10:24.45#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:10:24.50#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:10:24.51#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:10:24.53#ibcon#[25=AT06-04\r\n] 2006.145.08:10:24.55#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:10:24.56#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:10:24.56#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.08:10:24.56#ibcon#ireg 7 cls_cnt 0 2006.145.08:10:24.56#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:10:24.67#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:10:24.68#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:10:24.69#ibcon#[25=USB\r\n] 2006.145.08:10:24.72#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:10:24.73#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:10:24.73#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.08:10:24.73#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.08:10:24.73$vck44/valo=7,864.99 2006.145.08:10:24.73#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.08:10:24.73#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.08:10:24.73#ibcon#ireg 17 cls_cnt 0 2006.145.08:10:24.73#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:10:24.73#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:10:24.73#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:10:24.75#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.08:10:24.79#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:10:24.79#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:10:24.79#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.08:10:24.79#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.08:10:24.79$vck44/va=7,4 2006.145.08:10:24.79#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.08:10:24.79#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.08:10:24.79#ibcon#ireg 11 cls_cnt 2 2006.145.08:10:24.79#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:10:24.84#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:10:24.85#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:10:24.87#ibcon#[25=AT07-04\r\n] 2006.145.08:10:24.90#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:10:24.90#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:10:24.90#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.08:10:24.90#ibcon#ireg 7 cls_cnt 0 2006.145.08:10:24.90#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:10:25.01#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:10:25.02#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:10:25.04#ibcon#[25=USB\r\n] 2006.145.08:10:25.07#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:10:25.07#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:10:25.07#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.08:10:25.07#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.08:10:25.07$vck44/valo=8,884.99 2006.145.08:10:25.07#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.08:10:25.07#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.08:10:25.07#ibcon#ireg 17 cls_cnt 0 2006.145.08:10:25.07#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:10:25.07#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:10:25.07#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:10:25.09#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.08:10:25.13#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:10:25.13#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:10:25.13#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.08:10:25.13#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.08:10:25.13$vck44/va=8,4 2006.145.08:10:25.13#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.08:10:25.13#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.08:10:25.13#ibcon#ireg 11 cls_cnt 2 2006.145.08:10:25.13#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:10:25.18#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:10:25.19#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:10:25.21#ibcon#[25=AT08-04\r\n] 2006.145.08:10:25.24#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:10:25.24#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:10:25.24#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.08:10:25.24#ibcon#ireg 7 cls_cnt 0 2006.145.08:10:25.24#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:10:25.36#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:10:25.36#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:10:25.38#ibcon#[25=USB\r\n] 2006.145.08:10:25.41#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:10:25.41#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:10:25.41#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.08:10:25.41#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.08:10:25.41$vck44/vblo=1,629.99 2006.145.08:10:25.41#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.08:10:25.41#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.08:10:25.41#ibcon#ireg 17 cls_cnt 0 2006.145.08:10:25.41#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:10:25.41#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:10:25.41#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:10:25.43#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.08:10:25.47#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:10:25.47#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:10:25.47#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.08:10:25.47#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.08:10:25.47$vck44/vb=1,3 2006.145.08:10:25.47#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.08:10:25.47#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.08:10:25.47#ibcon#ireg 11 cls_cnt 2 2006.145.08:10:25.47#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.08:10:25.47#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.08:10:25.47#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.08:10:25.49#ibcon#[27=AT01-03\r\n] 2006.145.08:10:25.52#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.08:10:25.52#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.08:10:25.52#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.08:10:25.52#ibcon#ireg 7 cls_cnt 0 2006.145.08:10:25.52#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.08:10:25.64#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.08:10:25.64#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.08:10:25.66#ibcon#[27=USB\r\n] 2006.145.08:10:25.68#abcon#<5=/05 4.7 7.7 18.74 641017.4\r\n> 2006.145.08:10:25.69#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.08:10:25.69#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.08:10:25.69#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.08:10:25.69#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.08:10:25.69$vck44/vblo=2,634.99 2006.145.08:10:25.69#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.08:10:25.69#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.08:10:25.69#ibcon#ireg 17 cls_cnt 0 2006.145.08:10:25.69#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:10:25.69#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:10:25.69#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:10:25.70#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.08:10:25.71#abcon#{5=INTERFACE CLEAR} 2006.145.08:10:25.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:10:25.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:10:25.75#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.08:10:25.75#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.08:10:25.75$vck44/vb=2,4 2006.145.08:10:25.75#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.08:10:25.75#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.08:10:25.75#ibcon#ireg 11 cls_cnt 2 2006.145.08:10:25.75#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.08:10:25.77#abcon#[5=S1D000X0/0*\r\n] 2006.145.08:10:25.80#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.08:10:25.81#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.08:10:25.83#ibcon#[27=AT02-04\r\n] 2006.145.08:10:25.85#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.08:10:25.86#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.08:10:25.86#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.08:10:25.86#ibcon#ireg 7 cls_cnt 0 2006.145.08:10:25.86#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.08:10:25.97#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.08:10:25.98#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.08:10:26.00#ibcon#[27=USB\r\n] 2006.145.08:10:26.03#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.08:10:26.03#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.08:10:26.03#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.08:10:26.03#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.08:10:26.03$vck44/vblo=3,649.99 2006.145.08:10:26.03#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.08:10:26.03#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.08:10:26.03#ibcon#ireg 17 cls_cnt 0 2006.145.08:10:26.03#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.08:10:26.03#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.08:10:26.03#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.08:10:26.05#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.08:10:26.09#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.08:10:26.09#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.08:10:26.09#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.08:10:26.09#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.08:10:26.09$vck44/vb=3,4 2006.145.08:10:26.09#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.08:10:26.09#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.08:10:26.09#ibcon#ireg 11 cls_cnt 2 2006.145.08:10:26.09#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.08:10:26.15#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.08:10:26.15#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.08:10:26.17#ibcon#[27=AT03-04\r\n] 2006.145.08:10:26.20#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.08:10:26.20#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.08:10:26.20#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.08:10:26.20#ibcon#ireg 7 cls_cnt 0 2006.145.08:10:26.20#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.08:10:26.31#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.08:10:26.32#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.08:10:26.34#ibcon#[27=USB\r\n] 2006.145.08:10:26.37#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.08:10:26.37#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.08:10:26.37#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.08:10:26.37#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.08:10:26.37$vck44/vblo=4,679.99 2006.145.08:10:26.37#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.08:10:26.37#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.08:10:26.37#ibcon#ireg 17 cls_cnt 0 2006.145.08:10:26.37#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:10:26.37#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:10:26.37#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:10:26.38#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.08:10:26.43#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:10:26.43#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:10:26.43#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.08:10:26.43#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.08:10:26.43$vck44/vb=4,4 2006.145.08:10:26.43#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.08:10:26.43#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.08:10:26.43#ibcon#ireg 11 cls_cnt 2 2006.145.08:10:26.43#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:10:26.48#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:10:26.49#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:10:26.50#ibcon#[27=AT04-04\r\n] 2006.145.08:10:26.54#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:10:26.54#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:10:26.54#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.08:10:26.54#ibcon#ireg 7 cls_cnt 0 2006.145.08:10:26.54#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:10:26.66#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:10:26.66#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:10:26.68#ibcon#[27=USB\r\n] 2006.145.08:10:26.71#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:10:26.71#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:10:26.71#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.08:10:26.71#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.08:10:26.71$vck44/vblo=5,709.99 2006.145.08:10:26.71#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.08:10:26.71#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.08:10:26.71#ibcon#ireg 17 cls_cnt 0 2006.145.08:10:26.71#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:10:26.71#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:10:26.71#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:10:26.73#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.08:10:26.77#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:10:26.77#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:10:26.77#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.08:10:26.77#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.08:10:26.77$vck44/vb=5,4 2006.145.08:10:26.77#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.08:10:26.77#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.08:10:26.77#ibcon#ireg 11 cls_cnt 2 2006.145.08:10:26.77#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:10:26.82#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:10:26.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:10:26.85#ibcon#[27=AT05-04\r\n] 2006.145.08:10:26.88#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:10:26.88#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:10:26.88#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.08:10:26.88#ibcon#ireg 7 cls_cnt 0 2006.145.08:10:26.88#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:10:26.99#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:10:27.00#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:10:27.02#ibcon#[27=USB\r\n] 2006.145.08:10:27.05#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:10:27.05#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:10:27.05#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.08:10:27.05#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.08:10:27.05$vck44/vblo=6,719.99 2006.145.08:10:27.05#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.08:10:27.05#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.08:10:27.05#ibcon#ireg 17 cls_cnt 0 2006.145.08:10:27.05#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:10:27.05#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:10:27.05#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:10:27.07#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.08:10:27.10#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:10:27.11#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:10:27.11#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.08:10:27.11#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.08:10:27.11$vck44/vb=6,4 2006.145.08:10:27.11#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.08:10:27.11#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.08:10:27.11#ibcon#ireg 11 cls_cnt 2 2006.145.08:10:27.11#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:10:27.16#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:10:27.17#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:10:27.19#ibcon#[27=AT06-04\r\n] 2006.145.08:10:27.22#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:10:27.22#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:10:27.22#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.08:10:27.22#ibcon#ireg 7 cls_cnt 0 2006.145.08:10:27.22#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:10:27.33#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:10:27.34#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:10:27.35#ibcon#[27=USB\r\n] 2006.145.08:10:27.38#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:10:27.39#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:10:27.39#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.08:10:27.39#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.08:10:27.39$vck44/vblo=7,734.99 2006.145.08:10:27.39#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.08:10:27.39#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.08:10:27.39#ibcon#ireg 17 cls_cnt 0 2006.145.08:10:27.39#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:10:27.39#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:10:27.39#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:10:27.41#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.08:10:27.44#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:10:27.45#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:10:27.45#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.08:10:27.45#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.08:10:27.45$vck44/vb=7,4 2006.145.08:10:27.45#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.08:10:27.45#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.08:10:27.45#ibcon#ireg 11 cls_cnt 2 2006.145.08:10:27.45#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:10:27.50#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:10:27.50#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:10:27.52#ibcon#[27=AT07-04\r\n] 2006.145.08:10:27.55#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:10:27.56#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:10:27.56#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.08:10:27.56#ibcon#ireg 7 cls_cnt 0 2006.145.08:10:27.56#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:10:27.67#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:10:27.68#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:10:27.70#ibcon#[27=USB\r\n] 2006.145.08:10:27.73#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:10:27.73#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:10:27.73#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.08:10:27.73#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.08:10:27.73$vck44/vblo=8,744.99 2006.145.08:10:27.73#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.08:10:27.73#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.08:10:27.73#ibcon#ireg 17 cls_cnt 0 2006.145.08:10:27.73#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:10:27.73#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:10:27.73#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:10:27.74#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.08:10:27.79#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:10:27.79#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:10:27.79#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.08:10:27.79#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.08:10:27.79$vck44/vb=8,4 2006.145.08:10:27.79#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.08:10:27.79#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.08:10:27.79#ibcon#ireg 11 cls_cnt 2 2006.145.08:10:27.79#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:10:27.84#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:10:27.84#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:10:27.86#ibcon#[27=AT08-04\r\n] 2006.145.08:10:27.90#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:10:27.90#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:10:27.90#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.08:10:27.90#ibcon#ireg 7 cls_cnt 0 2006.145.08:10:27.90#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:10:28.01#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:10:28.02#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:10:28.04#ibcon#[27=USB\r\n] 2006.145.08:10:28.07#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:10:28.07#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:10:28.07#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.08:10:28.07#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.08:10:28.07$vck44/vabw=wide 2006.145.08:10:28.07#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.08:10:28.07#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.08:10:28.07#ibcon#ireg 8 cls_cnt 0 2006.145.08:10:28.07#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:10:28.07#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:10:28.07#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:10:28.09#ibcon#[25=BW32\r\n] 2006.145.08:10:28.12#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:10:28.12#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:10:28.12#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.08:10:28.12#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.08:10:28.12$vck44/vbbw=wide 2006.145.08:10:28.12#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.08:10:28.12#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.08:10:28.12#ibcon#ireg 8 cls_cnt 0 2006.145.08:10:28.12#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.08:10:28.18#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.08:10:28.19#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.08:10:28.21#ibcon#[27=BW32\r\n] 2006.145.08:10:28.24#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.08:10:28.24#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.08:10:28.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.08:10:28.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.08:10:28.24$setupk4/ifdk4 2006.145.08:10:28.24$ifdk4/lo= 2006.145.08:10:28.24$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.08:10:28.24$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.08:10:28.24$ifdk4/patch= 2006.145.08:10:28.24$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.08:10:28.24$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.08:10:28.24$setupk4/!*+20s 2006.145.08:10:35.85#abcon#<5=/05 4.7 7.7 18.74 641017.4\r\n> 2006.145.08:10:35.87#abcon#{5=INTERFACE CLEAR} 2006.145.08:10:35.93#abcon#[5=S1D000X0/0*\r\n] 2006.145.08:10:42.73$setupk4/"tpicd 2006.145.08:10:42.74$setupk4/echo=off 2006.145.08:10:42.74$setupk4/xlog=off 2006.145.08:10:42.74:!2006.145.08:12:27 2006.145.08:10:56.14#trakl#Source acquired 2006.145.08:10:56.15#flagr#flagr/antenna,acquired 2006.145.08:12:27.02:preob 2006.145.08:12:28.15/onsource/TRACKING 2006.145.08:12:28.15:!2006.145.08:12:37 2006.145.08:12:37.02:"tape 2006.145.08:12:37.02:"st=record 2006.145.08:12:37.02:data_valid=on 2006.145.08:12:37.02:midob 2006.145.08:12:38.15/onsource/TRACKING 2006.145.08:12:38.15/wx/18.72,1017.4,64 2006.145.08:12:38.23/cable/+6.5404E-03 2006.145.08:12:39.32/va/01,08,usb,yes,29,31 2006.145.08:12:39.32/va/02,07,usb,yes,31,32 2006.145.08:12:39.32/va/03,08,usb,yes,28,29 2006.145.08:12:39.32/va/04,07,usb,yes,32,34 2006.145.08:12:39.32/va/05,04,usb,yes,28,28 2006.145.08:12:39.32/va/06,04,usb,yes,31,31 2006.145.08:12:39.32/va/07,04,usb,yes,32,33 2006.145.08:12:39.32/va/08,04,usb,yes,27,32 2006.145.08:12:39.55/valo/01,524.99,yes,locked 2006.145.08:12:39.55/valo/02,534.99,yes,locked 2006.145.08:12:39.55/valo/03,564.99,yes,locked 2006.145.08:12:39.55/valo/04,624.99,yes,locked 2006.145.08:12:39.55/valo/05,734.99,yes,locked 2006.145.08:12:39.55/valo/06,814.99,yes,locked 2006.145.08:12:39.55/valo/07,864.99,yes,locked 2006.145.08:12:39.55/valo/08,884.99,yes,locked 2006.145.08:12:40.64/vb/01,03,usb,yes,36,34 2006.145.08:12:40.64/vb/02,04,usb,yes,32,32 2006.145.08:12:40.64/vb/03,04,usb,yes,29,32 2006.145.08:12:40.64/vb/04,04,usb,yes,33,32 2006.145.08:12:40.64/vb/05,04,usb,yes,25,28 2006.145.08:12:40.64/vb/06,04,usb,yes,30,26 2006.145.08:12:40.64/vb/07,04,usb,yes,30,29 2006.145.08:12:40.64/vb/08,04,usb,yes,27,31 2006.145.08:12:40.87/vblo/01,629.99,yes,locked 2006.145.08:12:40.87/vblo/02,634.99,yes,locked 2006.145.08:12:40.87/vblo/03,649.99,yes,locked 2006.145.08:12:40.87/vblo/04,679.99,yes,locked 2006.145.08:12:40.87/vblo/05,709.99,yes,locked 2006.145.08:12:40.87/vblo/06,719.99,yes,locked 2006.145.08:12:40.87/vblo/07,734.99,yes,locked 2006.145.08:12:40.87/vblo/08,744.99,yes,locked 2006.145.08:12:41.02/vabw/8 2006.145.08:12:41.17/vbbw/8 2006.145.08:12:41.26/xfe/off,on,15.0 2006.145.08:12:41.65/ifatt/23,28,28,28 2006.145.08:12:42.07/fmout-gps/S +5.6E-08 2006.145.08:12:42.12:!2006.145.08:13:37 2006.145.08:13:37.01:data_valid=off 2006.145.08:13:37.02:"et 2006.145.08:13:37.02:!+3s 2006.145.08:13:40.05:"tape 2006.145.08:13:40.06:postob 2006.145.08:13:40.13/cable/+6.5412E-03 2006.145.08:13:40.14/wx/18.72,1017.5,64 2006.145.08:13:40.20/fmout-gps/S +5.5E-08 2006.145.08:13:40.21:scan_name=145-0815,jd0605,540 2006.145.08:13:40.21:source=0059+581,010245.76,582411.1,2000.0,cw 2006.145.08:13:41.14#flagr#flagr/antenna,new-source 2006.145.08:13:41.15:checkk5 2006.145.08:13:41.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.08:13:42.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.08:13:42.44/chk_autoobs//k5ts3/ autoobs is running! 2006.145.08:13:42.88/chk_autoobs//k5ts4/ autoobs is running! 2006.145.08:13:43.31/chk_obsdata//k5ts1/T1450812??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.145.08:13:43.75/chk_obsdata//k5ts2/T1450812??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.145.08:13:44.20/chk_obsdata//k5ts3/T1450812??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.145.08:13:44.64/chk_obsdata//k5ts4/T1450812??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.145.08:13:45.39/k5log//k5ts1_log_newline 2006.145.08:13:46.14/k5log//k5ts2_log_newline 2006.145.08:13:46.89/k5log//k5ts3_log_newline 2006.145.08:13:47.63/k5log//k5ts4_log_newline 2006.145.08:13:47.65/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.08:13:47.65:setupk4=1 2006.145.08:13:47.66$setupk4/echo=on 2006.145.08:13:47.66$setupk4/pcalon 2006.145.08:13:47.66$pcalon/"no phase cal control is implemented here 2006.145.08:13:47.66$setupk4/"tpicd=stop 2006.145.08:13:47.66$setupk4/"rec=synch_on 2006.145.08:13:47.66$setupk4/"rec_mode=128 2006.145.08:13:47.66$setupk4/!* 2006.145.08:13:47.66$setupk4/recpk4 2006.145.08:13:47.66$recpk4/recpatch= 2006.145.08:13:47.66$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.08:13:47.66$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.08:13:47.66$setupk4/vck44 2006.145.08:13:47.66$vck44/valo=1,524.99 2006.145.08:13:47.66#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.08:13:47.66#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.08:13:47.66#ibcon#ireg 17 cls_cnt 0 2006.145.08:13:47.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:13:47.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:13:47.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:13:47.67#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.08:13:47.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:13:47.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:13:47.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.08:13:47.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.08:13:47.72$vck44/va=1,8 2006.145.08:13:47.72#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.08:13:47.72#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.08:13:47.72#ibcon#ireg 11 cls_cnt 2 2006.145.08:13:47.72#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:13:47.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:13:47.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:13:47.74#ibcon#[25=AT01-08\r\n] 2006.145.08:13:47.77#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:13:47.77#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:13:47.77#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.08:13:47.77#ibcon#ireg 7 cls_cnt 0 2006.145.08:13:47.77#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:13:47.89#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:13:47.89#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:13:47.91#ibcon#[25=USB\r\n] 2006.145.08:13:47.96#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:13:47.96#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:13:47.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.08:13:47.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.08:13:47.96$vck44/valo=2,534.99 2006.145.08:13:47.96#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.08:13:47.96#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.08:13:47.96#ibcon#ireg 17 cls_cnt 0 2006.145.08:13:47.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:13:47.96#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:13:47.96#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:13:47.98#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.08:13:48.01#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:13:48.01#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:13:48.01#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.08:13:48.01#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.08:13:48.01$vck44/va=2,7 2006.145.08:13:48.01#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.08:13:48.01#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.08:13:48.01#ibcon#ireg 11 cls_cnt 2 2006.145.08:13:48.01#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:13:48.08#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:13:48.08#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:13:48.10#ibcon#[25=AT02-07\r\n] 2006.145.08:13:48.13#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:13:48.13#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:13:48.13#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.08:13:48.13#ibcon#ireg 7 cls_cnt 0 2006.145.08:13:48.13#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:13:48.25#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:13:48.25#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:13:48.27#ibcon#[25=USB\r\n] 2006.145.08:13:48.30#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:13:48.30#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:13:48.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.08:13:48.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.08:13:48.30$vck44/valo=3,564.99 2006.145.08:13:48.30#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.08:13:48.30#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.08:13:48.30#ibcon#ireg 17 cls_cnt 0 2006.145.08:13:48.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:13:48.30#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:13:48.30#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:13:48.32#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.08:13:48.36#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:13:48.36#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:13:48.36#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.08:13:48.36#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.08:13:48.36$vck44/va=3,8 2006.145.08:13:48.36#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.08:13:48.36#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.08:13:48.36#ibcon#ireg 11 cls_cnt 2 2006.145.08:13:48.36#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:13:48.42#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:13:48.42#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:13:48.44#ibcon#[25=AT03-08\r\n] 2006.145.08:13:48.47#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:13:48.47#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:13:48.47#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.08:13:48.47#ibcon#ireg 7 cls_cnt 0 2006.145.08:13:48.47#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:13:48.59#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:13:48.59#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:13:48.61#ibcon#[25=USB\r\n] 2006.145.08:13:48.64#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:13:48.64#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:13:48.64#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.08:13:48.64#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.08:13:48.64$vck44/valo=4,624.99 2006.145.08:13:48.64#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.08:13:48.64#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.08:13:48.64#ibcon#ireg 17 cls_cnt 0 2006.145.08:13:48.64#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:13:48.64#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:13:48.64#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:13:48.66#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.08:13:48.70#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:13:48.70#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:13:48.70#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.08:13:48.70#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.08:13:48.70$vck44/va=4,7 2006.145.08:13:48.70#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.08:13:48.70#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.08:13:48.70#ibcon#ireg 11 cls_cnt 2 2006.145.08:13:48.70#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:13:48.76#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:13:48.76#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:13:48.78#ibcon#[25=AT04-07\r\n] 2006.145.08:13:48.81#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:13:48.81#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:13:48.81#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.08:13:48.81#ibcon#ireg 7 cls_cnt 0 2006.145.08:13:48.81#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:13:48.93#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:13:48.93#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:13:48.95#ibcon#[25=USB\r\n] 2006.145.08:13:48.98#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:13:48.98#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:13:48.98#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.08:13:48.98#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.08:13:48.98$vck44/valo=5,734.99 2006.145.08:13:48.98#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.08:13:48.98#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.08:13:48.98#ibcon#ireg 17 cls_cnt 0 2006.145.08:13:48.98#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:13:48.98#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:13:48.98#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:13:49.00#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.08:13:49.04#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:13:49.04#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:13:49.04#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.08:13:49.04#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.08:13:49.04$vck44/va=5,4 2006.145.08:13:49.04#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.08:13:49.04#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.08:13:49.04#ibcon#ireg 11 cls_cnt 2 2006.145.08:13:49.04#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:13:49.10#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:13:49.10#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:13:49.12#ibcon#[25=AT05-04\r\n] 2006.145.08:13:49.15#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:13:49.15#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:13:49.15#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.08:13:49.15#ibcon#ireg 7 cls_cnt 0 2006.145.08:13:49.15#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:13:49.17#abcon#<5=/05 4.6 7.9 18.71 641017.5\r\n> 2006.145.08:13:49.19#abcon#{5=INTERFACE CLEAR} 2006.145.08:13:49.25#abcon#[5=S1D000X0/0*\r\n] 2006.145.08:13:49.27#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:13:49.27#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:13:49.31#ibcon#[25=USB\r\n] 2006.145.08:13:49.33#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:13:49.33#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:13:49.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.08:13:49.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.08:13:49.33$vck44/valo=6,814.99 2006.145.08:13:49.33#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.08:13:49.33#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.08:13:49.33#ibcon#ireg 17 cls_cnt 0 2006.145.08:13:49.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:13:49.33#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:13:49.33#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:13:49.35#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.08:13:49.40#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:13:49.40#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:13:49.40#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.08:13:49.40#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.08:13:49.40$vck44/va=6,4 2006.145.08:13:49.40#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.08:13:49.40#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.08:13:49.40#ibcon#ireg 11 cls_cnt 2 2006.145.08:13:49.40#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:13:49.44#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:13:49.44#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:13:49.46#ibcon#[25=AT06-04\r\n] 2006.145.08:13:49.49#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:13:49.49#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:13:49.49#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.08:13:49.49#ibcon#ireg 7 cls_cnt 0 2006.145.08:13:49.49#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:13:49.61#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:13:49.61#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:13:49.63#ibcon#[25=USB\r\n] 2006.145.08:13:49.66#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:13:49.66#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:13:49.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.08:13:49.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.08:13:49.66$vck44/valo=7,864.99 2006.145.08:13:49.66#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.08:13:49.66#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.08:13:49.66#ibcon#ireg 17 cls_cnt 0 2006.145.08:13:49.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:13:49.66#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:13:49.66#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:13:49.68#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.08:13:49.72#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:13:49.72#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:13:49.72#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.08:13:49.72#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.08:13:49.72$vck44/va=7,4 2006.145.08:13:49.72#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.08:13:49.72#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.08:13:49.72#ibcon#ireg 11 cls_cnt 2 2006.145.08:13:49.72#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:13:49.78#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:13:49.78#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:13:49.80#ibcon#[25=AT07-04\r\n] 2006.145.08:13:49.83#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:13:49.83#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:13:49.83#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.08:13:49.83#ibcon#ireg 7 cls_cnt 0 2006.145.08:13:49.83#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:13:49.95#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:13:49.95#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:13:49.97#ibcon#[25=USB\r\n] 2006.145.08:13:50.00#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:13:50.00#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:13:50.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.08:13:50.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.08:13:50.00$vck44/valo=8,884.99 2006.145.08:13:50.00#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.08:13:50.00#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.08:13:50.00#ibcon#ireg 17 cls_cnt 0 2006.145.08:13:50.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:13:50.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:13:50.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:13:50.02#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.08:13:50.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:13:50.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:13:50.06#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.08:13:50.06#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.08:13:50.06$vck44/va=8,4 2006.145.08:13:50.06#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.08:13:50.06#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.08:13:50.06#ibcon#ireg 11 cls_cnt 2 2006.145.08:13:50.06#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:13:50.12#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:13:50.12#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:13:50.14#ibcon#[25=AT08-04\r\n] 2006.145.08:13:50.17#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:13:50.17#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:13:50.17#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.08:13:50.17#ibcon#ireg 7 cls_cnt 0 2006.145.08:13:50.17#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:13:50.29#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:13:50.29#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:13:50.31#ibcon#[25=USB\r\n] 2006.145.08:13:50.34#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:13:50.34#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:13:50.34#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.08:13:50.34#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.08:13:50.34$vck44/vblo=1,629.99 2006.145.08:13:50.34#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.08:13:50.34#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.08:13:50.34#ibcon#ireg 17 cls_cnt 0 2006.145.08:13:50.34#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:13:50.34#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:13:50.34#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:13:50.36#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.08:13:50.40#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:13:50.40#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:13:50.40#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.08:13:50.40#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.08:13:50.40$vck44/vb=1,3 2006.145.08:13:50.40#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.08:13:50.40#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.08:13:50.40#ibcon#ireg 11 cls_cnt 2 2006.145.08:13:50.40#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:13:50.40#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:13:50.40#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:13:50.42#ibcon#[27=AT01-03\r\n] 2006.145.08:13:50.45#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:13:50.45#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:13:50.45#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.08:13:50.45#ibcon#ireg 7 cls_cnt 0 2006.145.08:13:50.45#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:13:50.57#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:13:50.57#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:13:50.59#ibcon#[27=USB\r\n] 2006.145.08:13:50.62#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:13:50.62#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:13:50.62#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.08:13:50.62#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.08:13:50.62$vck44/vblo=2,634.99 2006.145.08:13:50.62#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.08:13:50.62#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.08:13:50.62#ibcon#ireg 17 cls_cnt 0 2006.145.08:13:50.62#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:13:50.62#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:13:50.62#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:13:50.64#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.08:13:50.68#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:13:50.68#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:13:50.68#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.08:13:50.68#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.08:13:50.68$vck44/vb=2,4 2006.145.08:13:50.68#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.08:13:50.68#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.08:13:50.68#ibcon#ireg 11 cls_cnt 2 2006.145.08:13:50.68#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:13:50.74#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:13:50.74#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:13:50.76#ibcon#[27=AT02-04\r\n] 2006.145.08:13:50.79#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:13:50.79#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:13:50.79#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.08:13:50.79#ibcon#ireg 7 cls_cnt 0 2006.145.08:13:50.79#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:13:50.91#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:13:50.91#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:13:50.93#ibcon#[27=USB\r\n] 2006.145.08:13:50.96#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:13:50.96#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:13:50.96#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.08:13:50.96#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.08:13:50.96$vck44/vblo=3,649.99 2006.145.08:13:50.96#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.08:13:50.96#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.08:13:50.96#ibcon#ireg 17 cls_cnt 0 2006.145.08:13:50.96#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:13:50.96#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:13:50.96#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:13:50.98#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.08:13:51.02#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:13:51.02#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:13:51.02#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.08:13:51.02#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.08:13:51.02$vck44/vb=3,4 2006.145.08:13:51.02#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.08:13:51.02#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.08:13:51.02#ibcon#ireg 11 cls_cnt 2 2006.145.08:13:51.02#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:13:51.08#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:13:51.08#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:13:51.10#ibcon#[27=AT03-04\r\n] 2006.145.08:13:51.13#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:13:51.13#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:13:51.13#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.08:13:51.13#ibcon#ireg 7 cls_cnt 0 2006.145.08:13:51.13#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:13:51.25#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:13:51.25#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:13:51.27#ibcon#[27=USB\r\n] 2006.145.08:13:51.30#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:13:51.30#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:13:51.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.08:13:51.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.08:13:51.30$vck44/vblo=4,679.99 2006.145.08:13:51.30#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.08:13:51.30#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.08:13:51.30#ibcon#ireg 17 cls_cnt 0 2006.145.08:13:51.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:13:51.30#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:13:51.30#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:13:51.32#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.08:13:51.36#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:13:51.36#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:13:51.36#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.08:13:51.36#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.08:13:51.36$vck44/vb=4,4 2006.145.08:13:51.36#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.08:13:51.36#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.08:13:51.36#ibcon#ireg 11 cls_cnt 2 2006.145.08:13:51.36#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:13:51.42#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:13:51.42#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:13:51.44#ibcon#[27=AT04-04\r\n] 2006.145.08:13:51.47#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:13:51.47#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:13:51.47#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.08:13:51.47#ibcon#ireg 7 cls_cnt 0 2006.145.08:13:51.47#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:13:51.59#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:13:51.59#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:13:51.61#ibcon#[27=USB\r\n] 2006.145.08:13:51.64#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:13:51.64#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:13:51.64#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.08:13:51.64#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.08:13:51.64$vck44/vblo=5,709.99 2006.145.08:13:51.64#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.08:13:51.64#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.08:13:51.64#ibcon#ireg 17 cls_cnt 0 2006.145.08:13:51.64#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:13:51.64#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:13:51.64#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:13:51.66#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.08:13:51.70#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:13:51.70#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:13:51.70#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.08:13:51.70#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.08:13:51.70$vck44/vb=5,4 2006.145.08:13:51.70#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.08:13:51.70#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.08:13:51.70#ibcon#ireg 11 cls_cnt 2 2006.145.08:13:51.70#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:13:51.76#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:13:51.76#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:13:51.78#ibcon#[27=AT05-04\r\n] 2006.145.08:13:51.81#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:13:51.81#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:13:51.81#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.08:13:51.81#ibcon#ireg 7 cls_cnt 0 2006.145.08:13:51.81#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:13:51.93#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:13:51.93#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:13:51.95#ibcon#[27=USB\r\n] 2006.145.08:13:51.98#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:13:51.98#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:13:51.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.08:13:51.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.08:13:51.98$vck44/vblo=6,719.99 2006.145.08:13:51.98#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.08:13:51.98#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.08:13:51.98#ibcon#ireg 17 cls_cnt 0 2006.145.08:13:51.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:13:51.98#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:13:51.98#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:13:52.00#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.08:13:52.04#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:13:52.04#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:13:52.04#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.08:13:52.04#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.08:13:52.04$vck44/vb=6,4 2006.145.08:13:52.04#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.08:13:52.04#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.08:13:52.04#ibcon#ireg 11 cls_cnt 2 2006.145.08:13:52.04#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.08:13:52.10#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.08:13:52.10#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.08:13:52.12#ibcon#[27=AT06-04\r\n] 2006.145.08:13:52.15#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.08:13:52.15#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.08:13:52.15#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.08:13:52.15#ibcon#ireg 7 cls_cnt 0 2006.145.08:13:52.15#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.08:13:52.27#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.08:13:52.27#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.08:13:52.29#ibcon#[27=USB\r\n] 2006.145.08:13:52.32#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.08:13:52.32#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.08:13:52.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.08:13:52.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.08:13:52.32$vck44/vblo=7,734.99 2006.145.08:13:52.32#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.08:13:52.32#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.08:13:52.32#ibcon#ireg 17 cls_cnt 0 2006.145.08:13:52.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:13:52.32#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:13:52.32#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:13:52.34#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.08:13:52.38#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:13:52.38#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:13:52.38#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.08:13:52.38#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.08:13:52.38$vck44/vb=7,4 2006.145.08:13:52.38#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.08:13:52.38#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.08:13:52.38#ibcon#ireg 11 cls_cnt 2 2006.145.08:13:52.38#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:13:52.44#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:13:52.44#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:13:52.46#ibcon#[27=AT07-04\r\n] 2006.145.08:13:52.49#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:13:52.49#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:13:52.49#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.08:13:52.49#ibcon#ireg 7 cls_cnt 0 2006.145.08:13:52.49#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:13:52.61#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:13:52.61#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:13:52.63#ibcon#[27=USB\r\n] 2006.145.08:13:52.66#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:13:52.66#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:13:52.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.08:13:52.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.08:13:52.66$vck44/vblo=8,744.99 2006.145.08:13:52.66#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.08:13:52.66#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.08:13:52.66#ibcon#ireg 17 cls_cnt 0 2006.145.08:13:52.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:13:52.66#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:13:52.66#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:13:52.68#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.08:13:52.72#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:13:52.72#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:13:52.72#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.08:13:52.72#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.08:13:52.72$vck44/vb=8,4 2006.145.08:13:52.72#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.08:13:52.72#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.08:13:52.72#ibcon#ireg 11 cls_cnt 2 2006.145.08:13:52.72#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:13:52.78#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:13:52.78#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:13:52.80#ibcon#[27=AT08-04\r\n] 2006.145.08:13:52.83#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:13:52.83#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:13:52.83#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.08:13:52.83#ibcon#ireg 7 cls_cnt 0 2006.145.08:13:52.83#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:13:52.95#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:13:52.95#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:13:52.97#ibcon#[27=USB\r\n] 2006.145.08:13:53.00#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:13:53.00#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:13:53.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.08:13:53.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.08:13:53.00$vck44/vabw=wide 2006.145.08:13:53.00#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.08:13:53.00#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.08:13:53.00#ibcon#ireg 8 cls_cnt 0 2006.145.08:13:53.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:13:53.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:13:53.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:13:53.02#ibcon#[25=BW32\r\n] 2006.145.08:13:53.05#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:13:53.05#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:13:53.05#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.08:13:53.05#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.08:13:53.05$vck44/vbbw=wide 2006.145.08:13:53.05#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.08:13:53.05#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.08:13:53.05#ibcon#ireg 8 cls_cnt 0 2006.145.08:13:53.05#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:13:53.12#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:13:53.12#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:13:53.14#ibcon#[27=BW32\r\n] 2006.145.08:13:53.17#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:13:53.17#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:13:53.17#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.08:13:53.17#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.08:13:53.17$setupk4/ifdk4 2006.145.08:13:53.17$ifdk4/lo= 2006.145.08:13:53.17$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.08:13:53.18$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.08:13:53.18$ifdk4/patch= 2006.145.08:13:53.18$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.08:13:53.18$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.08:13:53.18$setupk4/!*+20s 2006.145.08:13:59.34#abcon#<5=/05 4.6 7.9 18.71 631017.5\r\n> 2006.145.08:13:59.36#abcon#{5=INTERFACE CLEAR} 2006.145.08:13:59.42#abcon#[5=S1D000X0/0*\r\n] 2006.145.08:14:07.68$setupk4/"tpicd 2006.145.08:14:07.68$setupk4/echo=off 2006.145.08:14:07.68$setupk4/xlog=off 2006.145.08:14:07.68:!2006.145.08:15:48 2006.145.08:14:27.13#trakl#Source acquired 2006.145.08:14:27.13#flagr#flagr/antenna,acquired 2006.145.08:15:48.00:preob 2006.145.08:15:49.13/onsource/TRACKING 2006.145.08:15:49.13:!2006.145.08:15:58 2006.145.08:15:58.00:"tape 2006.145.08:15:58.00:"st=record 2006.145.08:15:58.00:data_valid=on 2006.145.08:15:58.00:midob 2006.145.08:15:58.13/onsource/TRACKING 2006.145.08:15:58.14/wx/18.68,1017.4,65 2006.145.08:15:58.28/cable/+6.5399E-03 2006.145.08:15:59.37/va/01,08,usb,yes,32,34 2006.145.08:15:59.37/va/02,07,usb,yes,34,35 2006.145.08:15:59.37/va/03,08,usb,yes,31,32 2006.145.08:15:59.37/va/04,07,usb,yes,35,37 2006.145.08:15:59.37/va/05,04,usb,yes,31,31 2006.145.08:15:59.37/va/06,04,usb,yes,34,34 2006.145.08:15:59.37/va/07,04,usb,yes,35,36 2006.145.08:15:59.37/va/08,04,usb,yes,29,35 2006.145.08:15:59.60/valo/01,524.99,yes,locked 2006.145.08:15:59.60/valo/02,534.99,yes,locked 2006.145.08:15:59.60/valo/03,564.99,yes,locked 2006.145.08:15:59.60/valo/04,624.99,yes,locked 2006.145.08:15:59.60/valo/05,734.99,yes,locked 2006.145.08:15:59.60/valo/06,814.99,yes,locked 2006.145.08:15:59.60/valo/07,864.99,yes,locked 2006.145.08:15:59.60/valo/08,884.99,yes,locked 2006.145.08:16:00.69/vb/01,03,usb,yes,38,35 2006.145.08:16:00.69/vb/02,04,usb,yes,33,33 2006.145.08:16:00.69/vb/03,04,usb,yes,30,33 2006.145.08:16:00.69/vb/04,04,usb,yes,34,33 2006.145.08:16:00.69/vb/05,04,usb,yes,27,29 2006.145.08:16:00.69/vb/06,04,usb,yes,32,28 2006.145.08:16:00.69/vb/07,04,usb,yes,31,31 2006.145.08:16:00.69/vb/08,04,usb,yes,29,32 2006.145.08:16:00.92/vblo/01,629.99,yes,locked 2006.145.08:16:00.92/vblo/02,634.99,yes,locked 2006.145.08:16:00.92/vblo/03,649.99,yes,locked 2006.145.08:16:00.92/vblo/04,679.99,yes,locked 2006.145.08:16:00.92/vblo/05,709.99,yes,locked 2006.145.08:16:00.92/vblo/06,719.99,yes,locked 2006.145.08:16:00.92/vblo/07,734.99,yes,locked 2006.145.08:16:00.92/vblo/08,744.99,yes,locked 2006.145.08:16:01.07/vabw/8 2006.145.08:16:01.22/vbbw/8 2006.145.08:16:01.31/xfe/off,on,16.0 2006.145.08:16:01.68/ifatt/23,28,28,28 2006.145.08:16:02.07/fmout-gps/S +5.6E-08 2006.145.08:16:02.12:!2006.145.08:24:58 2006.145.08:24:58.00:data_valid=off 2006.145.08:24:58.01:"et 2006.145.08:24:58.01:!+3s 2006.145.08:25:01.02:"tape 2006.145.08:25:01.02:postob 2006.145.08:25:01.17/cable/+6.5407E-03 2006.145.08:25:01.17/wx/18.57,1017.6,66 2006.145.08:25:01.25/fmout-gps/S +5.5E-08 2006.145.08:25:01.25:scan_name=145-0826,jd0605,90 2006.145.08:25:01.25:source=0528+134,053056.42,133155.1,2000.0,cw 2006.145.08:25:02.14#flagr#flagr/antenna,new-source 2006.145.08:25:02.14:checkk5 2006.145.08:25:02.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.08:25:03.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.08:25:03.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.08:25:03.92/chk_autoobs//k5ts4/ autoobs is running! 2006.145.08:25:04.65/chk_obsdata//k5ts1/T1450815??a.dat file size is correct (nominal:2160MB, actual:2156MB). 2006.145.08:25:05.40/chk_obsdata//k5ts2/T1450815??b.dat file size is correct (nominal:2160MB, actual:2156MB). 2006.145.08:25:06.14/chk_obsdata//k5ts3/T1450815??c.dat file size is correct (nominal:2160MB, actual:2156MB). 2006.145.08:25:06.88/chk_obsdata//k5ts4/T1450815??d.dat file size is correct (nominal:2160MB, actual:2156MB). 2006.145.08:25:07.64/k5log//k5ts1_log_newline 2006.145.08:25:08.37/k5log//k5ts2_log_newline 2006.145.08:25:09.10/k5log//k5ts3_log_newline 2006.145.08:25:09.84/k5log//k5ts4_log_newline 2006.145.08:25:09.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.08:25:09.87:setupk4=1 2006.145.08:25:09.87$setupk4/echo=on 2006.145.08:25:09.87$setupk4/pcalon 2006.145.08:25:09.87$pcalon/"no phase cal control is implemented here 2006.145.08:25:09.87$setupk4/"tpicd=stop 2006.145.08:25:09.87$setupk4/"rec=synch_on 2006.145.08:25:09.87$setupk4/"rec_mode=128 2006.145.08:25:09.87$setupk4/!* 2006.145.08:25:09.87$setupk4/recpk4 2006.145.08:25:09.87$recpk4/recpatch= 2006.145.08:25:09.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.08:25:09.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.08:25:09.87$setupk4/vck44 2006.145.08:25:09.87$vck44/valo=1,524.99 2006.145.08:25:09.87#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.08:25:09.87#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.08:25:09.87#ibcon#ireg 17 cls_cnt 0 2006.145.08:25:09.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.08:25:09.87#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.08:25:09.87#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.08:25:09.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.08:25:09.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.08:25:09.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.08:25:09.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.08:25:09.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.08:25:09.96$vck44/va=1,8 2006.145.08:25:09.96#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.08:25:09.96#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.08:25:09.96#ibcon#ireg 11 cls_cnt 2 2006.145.08:25:09.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.08:25:09.96#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.08:25:09.96#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.08:25:09.98#ibcon#[25=AT01-08\r\n] 2006.145.08:25:10.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.08:25:10.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.08:25:10.01#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.08:25:10.01#ibcon#ireg 7 cls_cnt 0 2006.145.08:25:10.01#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.08:25:10.14#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.08:25:10.14#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.08:25:10.15#ibcon#[25=USB\r\n] 2006.145.08:25:10.18#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.08:25:10.18#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.08:25:10.18#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.08:25:10.18#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.08:25:10.18$vck44/valo=2,534.99 2006.145.08:25:10.18#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.08:25:10.18#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.08:25:10.18#ibcon#ireg 17 cls_cnt 0 2006.145.08:25:10.18#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.08:25:10.18#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.08:25:10.18#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.08:25:10.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.08:25:10.25#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.08:25:10.25#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.08:25:10.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.08:25:10.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.08:25:10.25$vck44/va=2,7 2006.145.08:25:10.25#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.08:25:10.25#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.08:25:10.25#ibcon#ireg 11 cls_cnt 2 2006.145.08:25:10.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.08:25:10.30#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.08:25:10.30#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.08:25:10.32#ibcon#[25=AT02-07\r\n] 2006.145.08:25:10.35#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.08:25:10.35#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.08:25:10.35#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.08:25:10.35#ibcon#ireg 7 cls_cnt 0 2006.145.08:25:10.35#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.08:25:10.47#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.08:25:10.47#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.08:25:10.49#ibcon#[25=USB\r\n] 2006.145.08:25:10.52#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.08:25:10.52#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.08:25:10.52#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.08:25:10.52#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.08:25:10.52$vck44/valo=3,564.99 2006.145.08:25:10.52#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.08:25:10.52#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.08:25:10.52#ibcon#ireg 17 cls_cnt 0 2006.145.08:25:10.52#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.08:25:10.52#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.08:25:10.52#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.08:25:10.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.08:25:10.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.08:25:10.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.08:25:10.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.08:25:10.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.08:25:10.58$vck44/va=3,8 2006.145.08:25:10.58#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.08:25:10.58#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.08:25:10.58#ibcon#ireg 11 cls_cnt 2 2006.145.08:25:10.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.08:25:10.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.08:25:10.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.08:25:10.66#ibcon#[25=AT03-08\r\n] 2006.145.08:25:10.69#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.08:25:10.69#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.08:25:10.69#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.08:25:10.69#ibcon#ireg 7 cls_cnt 0 2006.145.08:25:10.69#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.08:25:10.81#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.08:25:10.81#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.08:25:10.83#ibcon#[25=USB\r\n] 2006.145.08:25:10.86#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.08:25:10.86#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.08:25:10.86#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.08:25:10.86#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.08:25:10.86$vck44/valo=4,624.99 2006.145.08:25:10.86#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.08:25:10.86#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.08:25:10.86#ibcon#ireg 17 cls_cnt 0 2006.145.08:25:10.86#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.08:25:10.86#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.08:25:10.86#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.08:25:10.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.08:25:10.92#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.08:25:10.92#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.08:25:10.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.08:25:10.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.08:25:10.92$vck44/va=4,7 2006.145.08:25:10.92#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.08:25:10.92#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.08:25:10.92#ibcon#ireg 11 cls_cnt 2 2006.145.08:25:10.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.08:25:10.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.08:25:10.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.08:25:11.00#ibcon#[25=AT04-07\r\n] 2006.145.08:25:11.03#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.08:25:11.03#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.08:25:11.03#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.08:25:11.03#ibcon#ireg 7 cls_cnt 0 2006.145.08:25:11.03#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.08:25:11.15#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.08:25:11.15#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.08:25:11.17#ibcon#[25=USB\r\n] 2006.145.08:25:11.19#abcon#<5=/04 4.0 7.6 18.57 661017.6\r\n> 2006.145.08:25:11.20#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.08:25:11.20#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.08:25:11.20#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.08:25:11.20#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.08:25:11.20$vck44/valo=5,734.99 2006.145.08:25:11.20#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.08:25:11.20#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.08:25:11.20#ibcon#ireg 17 cls_cnt 0 2006.145.08:25:11.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:25:11.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:25:11.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:25:11.21#abcon#{5=INTERFACE CLEAR} 2006.145.08:25:11.22#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.08:25:11.26#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:25:11.26#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:25:11.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.08:25:11.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.08:25:11.26$vck44/va=5,4 2006.145.08:25:11.26#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.08:25:11.26#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.08:25:11.26#ibcon#ireg 11 cls_cnt 2 2006.145.08:25:11.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.08:25:11.27#abcon#[5=S1D000X0/0*\r\n] 2006.145.08:25:11.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.08:25:11.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.08:25:11.34#ibcon#[25=AT05-04\r\n] 2006.145.08:25:11.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.08:25:11.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.08:25:11.37#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.08:25:11.37#ibcon#ireg 7 cls_cnt 0 2006.145.08:25:11.37#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.08:25:11.49#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.08:25:11.49#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.08:25:11.51#ibcon#[25=USB\r\n] 2006.145.08:25:11.54#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.08:25:11.54#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.08:25:11.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.08:25:11.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.08:25:11.54$vck44/valo=6,814.99 2006.145.08:25:11.54#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.08:25:11.54#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.08:25:11.54#ibcon#ireg 17 cls_cnt 0 2006.145.08:25:11.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.08:25:11.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.08:25:11.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.08:25:11.56#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.08:25:11.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.08:25:11.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.08:25:11.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.08:25:11.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.08:25:11.60$vck44/va=6,4 2006.145.08:25:11.60#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.08:25:11.60#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.08:25:11.60#ibcon#ireg 11 cls_cnt 2 2006.145.08:25:11.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.08:25:11.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.08:25:11.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.08:25:11.68#ibcon#[25=AT06-04\r\n] 2006.145.08:25:11.71#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.08:25:11.71#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.08:25:11.71#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.08:25:11.71#ibcon#ireg 7 cls_cnt 0 2006.145.08:25:11.71#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.08:25:11.83#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.08:25:11.83#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.08:25:11.85#ibcon#[25=USB\r\n] 2006.145.08:25:11.88#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.08:25:11.88#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.08:25:11.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.08:25:11.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.08:25:11.88$vck44/valo=7,864.99 2006.145.08:25:11.88#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.08:25:11.88#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.08:25:11.88#ibcon#ireg 17 cls_cnt 0 2006.145.08:25:11.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.08:25:11.88#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.08:25:11.88#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.08:25:11.90#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.08:25:11.94#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.08:25:11.94#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.08:25:11.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.08:25:11.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.08:25:11.94$vck44/va=7,4 2006.145.08:25:11.94#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.08:25:11.94#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.08:25:11.94#ibcon#ireg 11 cls_cnt 2 2006.145.08:25:11.94#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.08:25:12.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.08:25:12.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.08:25:12.02#ibcon#[25=AT07-04\r\n] 2006.145.08:25:12.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.08:25:12.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.08:25:12.05#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.08:25:12.05#ibcon#ireg 7 cls_cnt 0 2006.145.08:25:12.05#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.08:25:12.17#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.08:25:12.17#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.08:25:12.19#ibcon#[25=USB\r\n] 2006.145.08:25:12.22#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.08:25:12.22#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.08:25:12.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.08:25:12.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.08:25:12.22$vck44/valo=8,884.99 2006.145.08:25:12.22#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.08:25:12.22#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.08:25:12.22#ibcon#ireg 17 cls_cnt 0 2006.145.08:25:12.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.08:25:12.22#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.08:25:12.22#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.08:25:12.24#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.08:25:12.28#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.08:25:12.28#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.08:25:12.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.08:25:12.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.08:25:12.28$vck44/va=8,4 2006.145.08:25:12.28#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.08:25:12.28#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.08:25:12.28#ibcon#ireg 11 cls_cnt 2 2006.145.08:25:12.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.08:25:12.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.08:25:12.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.08:25:12.36#ibcon#[25=AT08-04\r\n] 2006.145.08:25:12.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.08:25:12.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.08:25:12.39#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.08:25:12.39#ibcon#ireg 7 cls_cnt 0 2006.145.08:25:12.39#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.08:25:12.51#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.08:25:12.51#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.08:25:12.53#ibcon#[25=USB\r\n] 2006.145.08:25:12.56#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.08:25:12.56#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.08:25:12.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.08:25:12.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.08:25:12.56$vck44/vblo=1,629.99 2006.145.08:25:12.56#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.08:25:12.56#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.08:25:12.56#ibcon#ireg 17 cls_cnt 0 2006.145.08:25:12.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.08:25:12.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.08:25:12.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.08:25:12.58#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.08:25:12.62#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.08:25:12.62#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.08:25:12.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.08:25:12.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.08:25:12.62$vck44/vb=1,3 2006.145.08:25:12.62#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.08:25:12.62#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.08:25:12.62#ibcon#ireg 11 cls_cnt 2 2006.145.08:25:12.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.08:25:12.62#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.08:25:12.62#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.08:25:12.64#ibcon#[27=AT01-03\r\n] 2006.145.08:25:12.67#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.08:25:12.67#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.08:25:12.67#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.08:25:12.67#ibcon#ireg 7 cls_cnt 0 2006.145.08:25:12.67#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.08:25:12.79#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.08:25:12.79#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.08:25:12.81#ibcon#[27=USB\r\n] 2006.145.08:25:12.84#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.08:25:12.84#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.08:25:12.84#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.08:25:12.84#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.08:25:12.84$vck44/vblo=2,634.99 2006.145.08:25:12.84#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.08:25:12.84#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.08:25:12.84#ibcon#ireg 17 cls_cnt 0 2006.145.08:25:12.84#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.08:25:12.84#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.08:25:12.84#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.08:25:12.86#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.08:25:12.90#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.08:25:12.90#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.08:25:12.90#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.08:25:12.90#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.08:25:12.90$vck44/vb=2,4 2006.145.08:25:12.90#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.08:25:12.90#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.08:25:12.90#ibcon#ireg 11 cls_cnt 2 2006.145.08:25:12.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.08:25:12.96#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.08:25:12.96#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.08:25:12.98#ibcon#[27=AT02-04\r\n] 2006.145.08:25:13.01#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.08:25:13.01#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.08:25:13.01#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.08:25:13.01#ibcon#ireg 7 cls_cnt 0 2006.145.08:25:13.01#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.08:25:13.13#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.08:25:13.13#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.08:25:13.15#ibcon#[27=USB\r\n] 2006.145.08:25:13.18#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.08:25:13.18#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.08:25:13.18#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.08:25:13.18#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.08:25:13.18$vck44/vblo=3,649.99 2006.145.08:25:13.18#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.08:25:13.18#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.08:25:13.18#ibcon#ireg 17 cls_cnt 0 2006.145.08:25:13.18#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.08:25:13.18#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.08:25:13.18#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.08:25:13.20#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.08:25:13.24#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.08:25:13.24#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.08:25:13.24#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.08:25:13.24#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.08:25:13.24$vck44/vb=3,4 2006.145.08:25:13.24#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.08:25:13.24#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.08:25:13.24#ibcon#ireg 11 cls_cnt 2 2006.145.08:25:13.24#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.08:25:13.30#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.08:25:13.30#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.08:25:13.32#ibcon#[27=AT03-04\r\n] 2006.145.08:25:13.35#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.08:25:13.35#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.08:25:13.35#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.08:25:13.35#ibcon#ireg 7 cls_cnt 0 2006.145.08:25:13.35#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.08:25:13.47#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.08:25:13.47#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.08:25:13.49#ibcon#[27=USB\r\n] 2006.145.08:25:13.52#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.08:25:13.52#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.08:25:13.52#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.08:25:13.52#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.08:25:13.52$vck44/vblo=4,679.99 2006.145.08:25:13.52#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.08:25:13.52#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.08:25:13.52#ibcon#ireg 17 cls_cnt 0 2006.145.08:25:13.52#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.08:25:13.52#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.08:25:13.52#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.08:25:13.54#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.08:25:13.58#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.08:25:13.58#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.08:25:13.58#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.08:25:13.58#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.08:25:13.58$vck44/vb=4,4 2006.145.08:25:13.58#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.08:25:13.58#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.08:25:13.58#ibcon#ireg 11 cls_cnt 2 2006.145.08:25:13.58#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.08:25:13.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.08:25:13.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.08:25:13.66#ibcon#[27=AT04-04\r\n] 2006.145.08:25:13.69#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.08:25:13.69#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.08:25:13.69#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.08:25:13.69#ibcon#ireg 7 cls_cnt 0 2006.145.08:25:13.69#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.08:25:13.81#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.08:25:13.81#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.08:25:13.83#ibcon#[27=USB\r\n] 2006.145.08:25:13.86#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.08:25:13.86#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.08:25:13.86#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.08:25:13.86#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.08:25:13.86$vck44/vblo=5,709.99 2006.145.08:25:13.86#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.08:25:13.86#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.08:25:13.86#ibcon#ireg 17 cls_cnt 0 2006.145.08:25:13.86#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.08:25:13.86#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.08:25:13.86#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.08:25:13.88#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.08:25:13.92#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.08:25:13.92#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.08:25:13.92#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.08:25:13.92#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.08:25:13.92$vck44/vb=5,4 2006.145.08:25:13.92#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.08:25:13.92#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.08:25:13.92#ibcon#ireg 11 cls_cnt 2 2006.145.08:25:13.92#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.08:25:13.98#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.08:25:13.98#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.08:25:14.00#ibcon#[27=AT05-04\r\n] 2006.145.08:25:14.03#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.08:25:14.03#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.08:25:14.03#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.08:25:14.03#ibcon#ireg 7 cls_cnt 0 2006.145.08:25:14.03#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.08:25:14.15#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.08:25:14.15#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.08:25:14.17#ibcon#[27=USB\r\n] 2006.145.08:25:14.20#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.08:25:14.20#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.08:25:14.20#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.08:25:14.20#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.08:25:14.20$vck44/vblo=6,719.99 2006.145.08:25:14.20#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.08:25:14.20#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.08:25:14.20#ibcon#ireg 17 cls_cnt 0 2006.145.08:25:14.20#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.08:25:14.20#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.08:25:14.20#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.08:25:14.22#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.08:25:14.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.08:25:14.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.08:25:14.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.08:25:14.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.08:25:14.26$vck44/vb=6,4 2006.145.08:25:14.26#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.08:25:14.26#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.08:25:14.26#ibcon#ireg 11 cls_cnt 2 2006.145.08:25:14.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.08:25:14.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.08:25:14.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.08:25:14.34#ibcon#[27=AT06-04\r\n] 2006.145.08:25:14.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.08:25:14.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.08:25:14.37#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.08:25:14.37#ibcon#ireg 7 cls_cnt 0 2006.145.08:25:14.37#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.08:25:14.49#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.08:25:14.49#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.08:25:14.51#ibcon#[27=USB\r\n] 2006.145.08:25:14.54#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.08:25:14.54#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.08:25:14.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.08:25:14.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.08:25:14.54$vck44/vblo=7,734.99 2006.145.08:25:14.54#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.08:25:14.54#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.08:25:14.54#ibcon#ireg 17 cls_cnt 0 2006.145.08:25:14.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.08:25:14.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.08:25:14.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.08:25:14.56#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.08:25:14.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.08:25:14.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.08:25:14.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.08:25:14.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.08:25:14.60$vck44/vb=7,4 2006.145.08:25:14.60#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.08:25:14.60#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.08:25:14.60#ibcon#ireg 11 cls_cnt 2 2006.145.08:25:14.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.08:25:14.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.08:25:14.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.08:25:14.68#ibcon#[27=AT07-04\r\n] 2006.145.08:25:14.71#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.08:25:14.71#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.08:25:14.71#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.08:25:14.71#ibcon#ireg 7 cls_cnt 0 2006.145.08:25:14.71#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.08:25:14.83#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.08:25:14.83#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.08:25:14.85#ibcon#[27=USB\r\n] 2006.145.08:25:14.88#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.08:25:14.88#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.08:25:14.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.08:25:14.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.08:25:14.88$vck44/vblo=8,744.99 2006.145.08:25:14.88#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.08:25:14.88#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.08:25:14.88#ibcon#ireg 17 cls_cnt 0 2006.145.08:25:14.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.08:25:14.88#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.08:25:14.88#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.08:25:14.90#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.08:25:14.94#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.08:25:14.94#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.08:25:14.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.08:25:14.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.08:25:14.94$vck44/vb=8,4 2006.145.08:25:14.94#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.08:25:14.94#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.08:25:14.94#ibcon#ireg 11 cls_cnt 2 2006.145.08:25:14.94#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.08:25:15.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.08:25:15.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.08:25:15.02#ibcon#[27=AT08-04\r\n] 2006.145.08:25:15.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.08:25:15.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.08:25:15.05#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.08:25:15.05#ibcon#ireg 7 cls_cnt 0 2006.145.08:25:15.05#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.08:25:15.17#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.08:25:15.17#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.08:25:15.19#ibcon#[27=USB\r\n] 2006.145.08:25:15.22#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.08:25:15.22#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.08:25:15.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.08:25:15.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.08:25:15.22$vck44/vabw=wide 2006.145.08:25:15.22#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.08:25:15.22#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.08:25:15.22#ibcon#ireg 8 cls_cnt 0 2006.145.08:25:15.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.08:25:15.22#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.08:25:15.22#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.08:25:15.25#ibcon#[25=BW32\r\n] 2006.145.08:25:15.28#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.08:25:15.28#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.08:25:15.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.08:25:15.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.08:25:15.28$vck44/vbbw=wide 2006.145.08:25:15.28#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.08:25:15.28#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.08:25:15.28#ibcon#ireg 8 cls_cnt 0 2006.145.08:25:15.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:25:15.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:25:15.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:25:15.36#ibcon#[27=BW32\r\n] 2006.145.08:25:15.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:25:15.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:25:15.39#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.08:25:15.39#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.08:25:15.39$setupk4/ifdk4 2006.145.08:25:15.39$ifdk4/lo= 2006.145.08:25:15.39$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.08:25:15.39$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.08:25:15.39$ifdk4/patch= 2006.145.08:25:15.39$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.08:25:15.39$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.08:25:15.39$setupk4/!*+20s 2006.145.08:25:21.36#abcon#<5=/04 4.0 7.6 18.57 671017.6\r\n> 2006.145.08:25:21.38#abcon#{5=INTERFACE CLEAR} 2006.145.08:25:21.44#abcon#[5=S1D000X0/0*\r\n] 2006.145.08:25:29.88$setupk4/"tpicd 2006.145.08:25:29.88$setupk4/echo=off 2006.145.08:25:29.88$setupk4/xlog=off 2006.145.08:25:29.88:!2006.145.08:26:10 2006.145.08:25:33.14#trakl#Source acquired 2006.145.08:25:34.14#flagr#flagr/antenna,acquired 2006.145.08:26:10.00:preob 2006.145.08:26:11.14/onsource/TRACKING 2006.145.08:26:11.14:!2006.145.08:26:20 2006.145.08:26:20.00:"tape 2006.145.08:26:20.00:"st=record 2006.145.08:26:20.00:data_valid=on 2006.145.08:26:20.00:midob 2006.145.08:26:20.14/onsource/TRACKING 2006.145.08:26:20.14/wx/18.56,1017.6,66 2006.145.08:26:20.28/cable/+6.5417E-03 2006.145.08:26:21.37/va/01,08,usb,yes,29,31 2006.145.08:26:21.37/va/02,07,usb,yes,31,32 2006.145.08:26:21.37/va/03,08,usb,yes,28,30 2006.145.08:26:21.37/va/04,07,usb,yes,32,34 2006.145.08:26:21.37/va/05,04,usb,yes,28,29 2006.145.08:26:21.37/va/06,04,usb,yes,32,31 2006.145.08:26:21.37/va/07,04,usb,yes,32,33 2006.145.08:26:21.37/va/08,04,usb,yes,27,33 2006.145.08:26:21.60/valo/01,524.99,yes,locked 2006.145.08:26:21.60/valo/02,534.99,yes,locked 2006.145.08:26:21.60/valo/03,564.99,yes,locked 2006.145.08:26:21.60/valo/04,624.99,yes,locked 2006.145.08:26:21.60/valo/05,734.99,yes,locked 2006.145.08:26:21.60/valo/06,814.99,yes,locked 2006.145.08:26:21.60/valo/07,864.99,yes,locked 2006.145.08:26:21.60/valo/08,884.99,yes,locked 2006.145.08:26:22.69/vb/01,03,usb,yes,36,33 2006.145.08:26:22.69/vb/02,04,usb,yes,31,31 2006.145.08:26:22.69/vb/03,04,usb,yes,28,31 2006.145.08:26:22.69/vb/04,04,usb,yes,33,32 2006.145.08:26:22.69/vb/05,04,usb,yes,25,28 2006.145.08:26:22.69/vb/06,04,usb,yes,30,26 2006.145.08:26:22.69/vb/07,04,usb,yes,29,29 2006.145.08:26:22.69/vb/08,04,usb,yes,27,30 2006.145.08:26:22.92/vblo/01,629.99,yes,locked 2006.145.08:26:22.92/vblo/02,634.99,yes,locked 2006.145.08:26:22.92/vblo/03,649.99,yes,locked 2006.145.08:26:22.92/vblo/04,679.99,yes,locked 2006.145.08:26:22.92/vblo/05,709.99,yes,locked 2006.145.08:26:22.92/vblo/06,719.99,yes,locked 2006.145.08:26:22.92/vblo/07,734.99,yes,locked 2006.145.08:26:22.92/vblo/08,744.99,yes,locked 2006.145.08:26:23.07/vabw/8 2006.145.08:26:23.22/vbbw/8 2006.145.08:26:23.31/xfe/off,on,14.7 2006.145.08:26:23.69/ifatt/23,28,28,28 2006.145.08:26:24.07/fmout-gps/S +5.3E-08 2006.145.08:26:24.11:!2006.145.08:27:50 2006.145.08:27:50.01:data_valid=off 2006.145.08:27:50.02:"et 2006.145.08:27:50.02:!+3s 2006.145.08:27:53.03:"tape 2006.145.08:27:53.03:postob 2006.145.08:27:53.21/cable/+6.5414E-03 2006.145.08:27:53.21/wx/18.54,1017.6,66 2006.145.08:27:53.29/fmout-gps/S +5.4E-08 2006.145.08:27:53.29:scan_name=145-0832,jd0605,410 2006.145.08:27:53.29:source=1308+326,131028.66,322043.8,2000.0,cw 2006.145.08:27:54.14#flagr#flagr/antenna,new-source 2006.145.08:27:54.14:checkk5 2006.145.08:27:54.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.08:27:55.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.08:27:55.43/chk_autoobs//k5ts3/ autoobs is running! 2006.145.08:27:55.87/chk_autoobs//k5ts4/ autoobs is running! 2006.145.08:27:56.29/chk_obsdata//k5ts1/T1450826??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.08:27:56.73/chk_obsdata//k5ts2/T1450826??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.08:27:57.17/chk_obsdata//k5ts3/T1450826??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.08:27:57.58/chk_obsdata//k5ts4/T1450826??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.08:27:58.34/k5log//k5ts1_log_newline 2006.145.08:27:59.07/k5log//k5ts2_log_newline 2006.145.08:27:59.81/k5log//k5ts3_log_newline 2006.145.08:28:00.55/k5log//k5ts4_log_newline 2006.145.08:28:00.58/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.08:28:00.58:setupk4=1 2006.145.08:28:00.58$setupk4/echo=on 2006.145.08:28:00.58$setupk4/pcalon 2006.145.08:28:00.58$pcalon/"no phase cal control is implemented here 2006.145.08:28:00.58$setupk4/"tpicd=stop 2006.145.08:28:00.58$setupk4/"rec=synch_on 2006.145.08:28:00.58$setupk4/"rec_mode=128 2006.145.08:28:00.58$setupk4/!* 2006.145.08:28:00.58$setupk4/recpk4 2006.145.08:28:00.58$recpk4/recpatch= 2006.145.08:28:00.58$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.08:28:00.58$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.08:28:00.58$setupk4/vck44 2006.145.08:28:00.58$vck44/valo=1,524.99 2006.145.08:28:00.58#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.08:28:00.58#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.08:28:00.58#ibcon#ireg 17 cls_cnt 0 2006.145.08:28:00.58#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.08:28:00.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.08:28:00.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.08:28:00.62#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.08:28:00.67#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.08:28:00.67#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.08:28:00.67#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.08:28:00.67#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.08:28:00.67$vck44/va=1,8 2006.145.08:28:00.67#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.08:28:00.67#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.08:28:00.67#ibcon#ireg 11 cls_cnt 2 2006.145.08:28:00.67#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.08:28:00.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.08:28:00.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.08:28:00.69#ibcon#[25=AT01-08\r\n] 2006.145.08:28:00.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.08:28:00.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.08:28:00.72#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.08:28:00.72#ibcon#ireg 7 cls_cnt 0 2006.145.08:28:00.72#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.08:28:00.84#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.08:28:00.84#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.08:28:00.86#ibcon#[25=USB\r\n] 2006.145.08:28:00.89#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.08:28:00.89#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.08:28:00.89#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.08:28:00.89#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.08:28:00.89$vck44/valo=2,534.99 2006.145.08:28:00.89#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.08:28:00.89#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.08:28:00.89#ibcon#ireg 17 cls_cnt 0 2006.145.08:28:00.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.08:28:00.89#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.08:28:00.89#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.08:28:00.92#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.08:28:00.96#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.08:28:00.96#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.08:28:00.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.08:28:00.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.08:28:00.96$vck44/va=2,7 2006.145.08:28:00.96#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.08:28:00.96#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.08:28:00.96#ibcon#ireg 11 cls_cnt 2 2006.145.08:28:00.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.08:28:01.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.08:28:01.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.08:28:01.03#ibcon#[25=AT02-07\r\n] 2006.145.08:28:01.06#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.08:28:01.06#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.08:28:01.06#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.08:28:01.06#ibcon#ireg 7 cls_cnt 0 2006.145.08:28:01.06#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.08:28:01.18#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.08:28:01.18#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.08:28:01.20#ibcon#[25=USB\r\n] 2006.145.08:28:01.23#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.08:28:01.23#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.08:28:01.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.08:28:01.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.08:28:01.23$vck44/valo=3,564.99 2006.145.08:28:01.23#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.08:28:01.23#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.08:28:01.23#ibcon#ireg 17 cls_cnt 0 2006.145.08:28:01.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.08:28:01.23#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.08:28:01.23#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.08:28:01.25#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.08:28:01.29#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.08:28:01.29#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.08:28:01.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.08:28:01.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.08:28:01.29$vck44/va=3,8 2006.145.08:28:01.29#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.08:28:01.29#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.08:28:01.29#ibcon#ireg 11 cls_cnt 2 2006.145.08:28:01.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.08:28:01.35#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.08:28:01.35#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.08:28:01.37#ibcon#[25=AT03-08\r\n] 2006.145.08:28:01.40#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.08:28:01.40#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.08:28:01.40#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.08:28:01.40#ibcon#ireg 7 cls_cnt 0 2006.145.08:28:01.40#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.08:28:01.52#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.08:28:01.52#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.08:28:01.54#ibcon#[25=USB\r\n] 2006.145.08:28:01.57#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.08:28:01.57#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.08:28:01.57#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.08:28:01.57#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.08:28:01.57$vck44/valo=4,624.99 2006.145.08:28:01.57#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.08:28:01.57#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.08:28:01.57#ibcon#ireg 17 cls_cnt 0 2006.145.08:28:01.57#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:28:01.57#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:28:01.57#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:28:01.59#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.08:28:01.63#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:28:01.63#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:28:01.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.08:28:01.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.08:28:01.63$vck44/va=4,7 2006.145.08:28:01.63#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.08:28:01.63#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.08:28:01.63#ibcon#ireg 11 cls_cnt 2 2006.145.08:28:01.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.08:28:01.69#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.08:28:01.69#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.08:28:01.71#ibcon#[25=AT04-07\r\n] 2006.145.08:28:01.74#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.08:28:01.74#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.08:28:01.74#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.08:28:01.74#ibcon#ireg 7 cls_cnt 0 2006.145.08:28:01.74#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.08:28:01.86#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.08:28:01.86#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.08:28:01.88#ibcon#[25=USB\r\n] 2006.145.08:28:01.91#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.08:28:01.91#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.08:28:01.91#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.08:28:01.91#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.08:28:01.91$vck44/valo=5,734.99 2006.145.08:28:01.91#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.08:28:01.91#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.08:28:01.91#ibcon#ireg 17 cls_cnt 0 2006.145.08:28:01.91#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.08:28:01.91#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.08:28:01.91#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.08:28:01.93#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.08:28:01.97#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.08:28:01.97#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.08:28:01.97#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.08:28:01.97#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.08:28:01.97$vck44/va=5,4 2006.145.08:28:01.97#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.08:28:01.97#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.08:28:01.97#ibcon#ireg 11 cls_cnt 2 2006.145.08:28:01.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.08:28:02.03#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.08:28:02.03#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.08:28:02.05#ibcon#[25=AT05-04\r\n] 2006.145.08:28:02.08#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.08:28:02.08#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.08:28:02.08#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.08:28:02.08#ibcon#ireg 7 cls_cnt 0 2006.145.08:28:02.08#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.08:28:02.20#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.08:28:02.20#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.08:28:02.22#ibcon#[25=USB\r\n] 2006.145.08:28:02.25#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.08:28:02.25#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.08:28:02.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.08:28:02.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.08:28:02.25$vck44/valo=6,814.99 2006.145.08:28:02.25#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.08:28:02.25#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.08:28:02.25#ibcon#ireg 17 cls_cnt 0 2006.145.08:28:02.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.08:28:02.25#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.08:28:02.25#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.08:28:02.27#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.08:28:02.31#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.08:28:02.31#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.08:28:02.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.08:28:02.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.08:28:02.31$vck44/va=6,4 2006.145.08:28:02.31#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.08:28:02.31#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.08:28:02.31#ibcon#ireg 11 cls_cnt 2 2006.145.08:28:02.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.08:28:02.37#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.08:28:02.37#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.08:28:02.39#ibcon#[25=AT06-04\r\n] 2006.145.08:28:02.42#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.08:28:02.42#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.08:28:02.42#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.08:28:02.42#ibcon#ireg 7 cls_cnt 0 2006.145.08:28:02.42#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.08:28:02.54#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.08:28:02.54#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.08:28:02.56#ibcon#[25=USB\r\n] 2006.145.08:28:02.59#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.08:28:02.59#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.08:28:02.59#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.08:28:02.59#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.08:28:02.59$vck44/valo=7,864.99 2006.145.08:28:02.59#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.08:28:02.59#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.08:28:02.59#ibcon#ireg 17 cls_cnt 0 2006.145.08:28:02.59#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:28:02.59#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:28:02.59#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:28:02.61#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.08:28:02.65#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:28:02.65#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:28:02.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.08:28:02.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.08:28:02.65$vck44/va=7,4 2006.145.08:28:02.65#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.08:28:02.65#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.08:28:02.65#ibcon#ireg 11 cls_cnt 2 2006.145.08:28:02.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.08:28:02.71#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.08:28:02.71#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.08:28:02.73#ibcon#[25=AT07-04\r\n] 2006.145.08:28:02.76#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.08:28:02.76#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.08:28:02.76#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.08:28:02.76#ibcon#ireg 7 cls_cnt 0 2006.145.08:28:02.76#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.08:28:02.88#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.08:28:02.88#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.08:28:02.90#ibcon#[25=USB\r\n] 2006.145.08:28:02.93#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.08:28:02.93#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.08:28:02.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.08:28:02.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.08:28:02.93$vck44/valo=8,884.99 2006.145.08:28:02.93#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.08:28:02.93#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.08:28:02.93#ibcon#ireg 17 cls_cnt 0 2006.145.08:28:02.93#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.08:28:02.93#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.08:28:02.93#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.08:28:02.95#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.08:28:02.99#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.08:28:02.99#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.08:28:02.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.08:28:02.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.08:28:02.99$vck44/va=8,4 2006.145.08:28:02.99#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.08:28:02.99#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.08:28:02.99#ibcon#ireg 11 cls_cnt 2 2006.145.08:28:02.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.08:28:03.05#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.08:28:03.05#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.08:28:03.07#ibcon#[25=AT08-04\r\n] 2006.145.08:28:03.10#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.08:28:03.10#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.08:28:03.10#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.08:28:03.10#ibcon#ireg 7 cls_cnt 0 2006.145.08:28:03.10#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.08:28:03.22#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.08:28:03.22#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.08:28:03.24#ibcon#[25=USB\r\n] 2006.145.08:28:03.27#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.08:28:03.27#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.08:28:03.27#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.08:28:03.27#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.08:28:03.27$vck44/vblo=1,629.99 2006.145.08:28:03.27#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.08:28:03.27#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.08:28:03.27#ibcon#ireg 17 cls_cnt 0 2006.145.08:28:03.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.08:28:03.27#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.08:28:03.27#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.08:28:03.29#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.08:28:03.33#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.08:28:03.33#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.08:28:03.33#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.08:28:03.33#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.08:28:03.33$vck44/vb=1,3 2006.145.08:28:03.33#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.08:28:03.33#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.08:28:03.33#ibcon#ireg 11 cls_cnt 2 2006.145.08:28:03.33#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.08:28:03.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.08:28:03.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.08:28:03.35#ibcon#[27=AT01-03\r\n] 2006.145.08:28:03.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.08:28:03.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.08:28:03.38#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.08:28:03.38#ibcon#ireg 7 cls_cnt 0 2006.145.08:28:03.38#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.08:28:03.50#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.08:28:03.50#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.08:28:03.52#ibcon#[27=USB\r\n] 2006.145.08:28:03.55#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.08:28:03.55#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.08:28:03.55#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.08:28:03.55#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.08:28:03.55$vck44/vblo=2,634.99 2006.145.08:28:03.55#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.08:28:03.55#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.08:28:03.55#ibcon#ireg 17 cls_cnt 0 2006.145.08:28:03.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.08:28:03.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.08:28:03.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.08:28:03.57#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.08:28:03.61#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.08:28:03.61#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.08:28:03.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.08:28:03.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.08:28:03.61$vck44/vb=2,4 2006.145.08:28:03.61#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.08:28:03.61#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.08:28:03.61#ibcon#ireg 11 cls_cnt 2 2006.145.08:28:03.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.08:28:03.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.08:28:03.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.08:28:03.69#ibcon#[27=AT02-04\r\n] 2006.145.08:28:03.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.08:28:03.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.08:28:03.72#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.08:28:03.72#ibcon#ireg 7 cls_cnt 0 2006.145.08:28:03.72#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.08:28:03.84#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.08:28:03.84#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.08:28:03.86#ibcon#[27=USB\r\n] 2006.145.08:28:03.89#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.08:28:03.89#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.08:28:03.89#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.08:28:03.89#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.08:28:03.89$vck44/vblo=3,649.99 2006.145.08:28:03.89#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.08:28:03.89#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.08:28:03.89#ibcon#ireg 17 cls_cnt 0 2006.145.08:28:03.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.08:28:03.89#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.08:28:03.89#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.08:28:03.91#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.08:28:03.95#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.08:28:03.95#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.08:28:03.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.08:28:03.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.08:28:03.95$vck44/vb=3,4 2006.145.08:28:03.95#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.08:28:03.95#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.08:28:03.95#ibcon#ireg 11 cls_cnt 2 2006.145.08:28:03.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.08:28:04.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.08:28:04.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.08:28:04.03#ibcon#[27=AT03-04\r\n] 2006.145.08:28:04.06#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.08:28:04.06#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.08:28:04.06#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.08:28:04.06#ibcon#ireg 7 cls_cnt 0 2006.145.08:28:04.06#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.08:28:04.08#abcon#<5=/04 3.9 7.2 18.53 651017.6\r\n> 2006.145.08:28:04.10#abcon#{5=INTERFACE CLEAR} 2006.145.08:28:04.16#abcon#[5=S1D000X0/0*\r\n] 2006.145.08:28:04.18#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.08:28:04.18#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.08:28:04.20#ibcon#[27=USB\r\n] 2006.145.08:28:04.23#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.08:28:04.23#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.08:28:04.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.08:28:04.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.08:28:04.23$vck44/vblo=4,679.99 2006.145.08:28:04.23#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.08:28:04.23#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.08:28:04.23#ibcon#ireg 17 cls_cnt 0 2006.145.08:28:04.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:28:04.23#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:28:04.23#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:28:04.25#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.08:28:04.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:28:04.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:28:04.29#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.08:28:04.29#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.08:28:04.29$vck44/vb=4,4 2006.145.08:28:04.29#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.08:28:04.29#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.08:28:04.29#ibcon#ireg 11 cls_cnt 2 2006.145.08:28:04.29#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.08:28:04.35#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.08:28:04.35#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.08:28:04.37#ibcon#[27=AT04-04\r\n] 2006.145.08:28:04.40#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.08:28:04.40#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.08:28:04.40#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.08:28:04.40#ibcon#ireg 7 cls_cnt 0 2006.145.08:28:04.40#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.08:28:04.52#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.08:28:04.52#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.08:28:04.54#ibcon#[27=USB\r\n] 2006.145.08:28:04.57#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.08:28:04.57#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.08:28:04.57#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.08:28:04.57#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.08:28:04.57$vck44/vblo=5,709.99 2006.145.08:28:04.57#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.08:28:04.57#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.08:28:04.57#ibcon#ireg 17 cls_cnt 0 2006.145.08:28:04.57#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.08:28:04.57#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.08:28:04.57#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.08:28:04.59#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.08:28:04.63#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.08:28:04.63#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.08:28:04.63#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.08:28:04.63#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.08:28:04.63$vck44/vb=5,4 2006.145.08:28:04.63#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.08:28:04.63#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.08:28:04.63#ibcon#ireg 11 cls_cnt 2 2006.145.08:28:04.63#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.08:28:04.69#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.08:28:04.69#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.08:28:04.71#ibcon#[27=AT05-04\r\n] 2006.145.08:28:04.74#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.08:28:04.74#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.08:28:04.74#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.08:28:04.74#ibcon#ireg 7 cls_cnt 0 2006.145.08:28:04.74#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.08:28:04.86#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.08:28:04.86#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.08:28:04.88#ibcon#[27=USB\r\n] 2006.145.08:28:04.91#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.08:28:04.91#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.08:28:04.91#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.08:28:04.91#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.08:28:04.91$vck44/vblo=6,719.99 2006.145.08:28:04.91#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.08:28:04.91#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.08:28:04.91#ibcon#ireg 17 cls_cnt 0 2006.145.08:28:04.91#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.08:28:04.91#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.08:28:04.91#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.08:28:04.93#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.08:28:04.97#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.08:28:04.97#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.08:28:04.97#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.08:28:04.97#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.08:28:04.97$vck44/vb=6,4 2006.145.08:28:04.97#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.08:28:04.97#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.08:28:04.97#ibcon#ireg 11 cls_cnt 2 2006.145.08:28:04.97#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.08:28:05.03#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.08:28:05.03#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.08:28:05.05#ibcon#[27=AT06-04\r\n] 2006.145.08:28:05.08#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.08:28:05.08#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.08:28:05.08#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.08:28:05.08#ibcon#ireg 7 cls_cnt 0 2006.145.08:28:05.08#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.08:28:05.20#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.08:28:05.20#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.08:28:05.22#ibcon#[27=USB\r\n] 2006.145.08:28:05.25#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.08:28:05.25#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.08:28:05.25#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.08:28:05.25#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.08:28:05.25$vck44/vblo=7,734.99 2006.145.08:28:05.25#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.08:28:05.25#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.08:28:05.25#ibcon#ireg 17 cls_cnt 0 2006.145.08:28:05.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:28:05.25#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:28:05.25#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:28:05.27#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.08:28:05.31#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:28:05.31#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:28:05.31#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.08:28:05.31#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.08:28:05.31$vck44/vb=7,4 2006.145.08:28:05.31#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.08:28:05.31#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.08:28:05.31#ibcon#ireg 11 cls_cnt 2 2006.145.08:28:05.31#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.08:28:05.37#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.08:28:05.37#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.08:28:05.39#ibcon#[27=AT07-04\r\n] 2006.145.08:28:05.42#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.08:28:05.42#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.08:28:05.42#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.08:28:05.42#ibcon#ireg 7 cls_cnt 0 2006.145.08:28:05.42#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.08:28:05.54#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.08:28:05.54#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.08:28:05.56#ibcon#[27=USB\r\n] 2006.145.08:28:05.59#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.08:28:05.59#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.08:28:05.59#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.08:28:05.59#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.08:28:05.59$vck44/vblo=8,744.99 2006.145.08:28:05.59#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.08:28:05.59#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.08:28:05.59#ibcon#ireg 17 cls_cnt 0 2006.145.08:28:05.59#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.08:28:05.59#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.08:28:05.59#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.08:28:05.61#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.08:28:05.65#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.08:28:05.65#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.08:28:05.65#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.08:28:05.65#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.08:28:05.65$vck44/vb=8,4 2006.145.08:28:05.65#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.08:28:05.65#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.08:28:05.65#ibcon#ireg 11 cls_cnt 2 2006.145.08:28:05.65#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.08:28:05.71#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.08:28:05.71#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.08:28:05.73#ibcon#[27=AT08-04\r\n] 2006.145.08:28:05.76#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.08:28:05.76#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.08:28:05.76#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.08:28:05.76#ibcon#ireg 7 cls_cnt 0 2006.145.08:28:05.76#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.08:28:05.88#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.08:28:05.88#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.08:28:05.90#ibcon#[27=USB\r\n] 2006.145.08:28:05.93#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.08:28:05.93#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.08:28:05.93#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.08:28:05.93#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.08:28:05.93$vck44/vabw=wide 2006.145.08:28:05.93#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.08:28:05.93#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.08:28:05.93#ibcon#ireg 8 cls_cnt 0 2006.145.08:28:05.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.08:28:05.93#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.08:28:05.93#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.08:28:05.95#ibcon#[25=BW32\r\n] 2006.145.08:28:05.98#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.08:28:05.98#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.08:28:05.98#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.08:28:05.98#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.08:28:05.98$vck44/vbbw=wide 2006.145.08:28:05.98#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.08:28:05.98#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.08:28:05.98#ibcon#ireg 8 cls_cnt 0 2006.145.08:28:05.98#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:28:06.05#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:28:06.05#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:28:06.07#ibcon#[27=BW32\r\n] 2006.145.08:28:06.10#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:28:06.10#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:28:06.10#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.08:28:06.10#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.08:28:06.10$setupk4/ifdk4 2006.145.08:28:06.10$ifdk4/lo= 2006.145.08:28:06.10$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.08:28:06.10$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.08:28:06.10$ifdk4/patch= 2006.145.08:28:06.10$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.08:28:06.10$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.08:28:06.10$setupk4/!*+20s 2006.145.08:28:14.25#abcon#<5=/04 4.0 7.2 18.53 661017.6\r\n> 2006.145.08:28:14.27#abcon#{5=INTERFACE CLEAR} 2006.145.08:28:14.33#abcon#[5=S1D000X0/0*\r\n] 2006.145.08:28:20.59$setupk4/"tpicd 2006.145.08:28:20.59$setupk4/echo=off 2006.145.08:28:20.59$setupk4/xlog=off 2006.145.08:28:20.59:!2006.145.08:32:08 2006.145.08:29:01.14#trakl#Source acquired 2006.145.08:29:02.14#flagr#flagr/antenna,acquired 2006.145.08:32:08.00:preob 2006.145.08:32:09.13/onsource/TRACKING 2006.145.08:32:09.13:!2006.145.08:32:18 2006.145.08:32:18.00:"tape 2006.145.08:32:18.00:"st=record 2006.145.08:32:18.00:data_valid=on 2006.145.08:32:18.00:midob 2006.145.08:32:18.13/onsource/TRACKING 2006.145.08:32:18.13/wx/18.49,1017.7,66 2006.145.08:32:18.29/cable/+6.5400E-03 2006.145.08:32:19.38/va/01,08,usb,yes,28,30 2006.145.08:32:19.38/va/02,07,usb,yes,30,31 2006.145.08:32:19.38/va/03,08,usb,yes,27,28 2006.145.08:32:19.38/va/04,07,usb,yes,31,33 2006.145.08:32:19.38/va/05,04,usb,yes,27,27 2006.145.08:32:19.38/va/06,04,usb,yes,30,30 2006.145.08:32:19.38/va/07,04,usb,yes,31,32 2006.145.08:32:19.38/va/08,04,usb,yes,26,31 2006.145.08:32:19.61/valo/01,524.99,yes,locked 2006.145.08:32:19.61/valo/02,534.99,yes,locked 2006.145.08:32:19.61/valo/03,564.99,yes,locked 2006.145.08:32:19.61/valo/04,624.99,yes,locked 2006.145.08:32:19.61/valo/05,734.99,yes,locked 2006.145.08:32:19.61/valo/06,814.99,yes,locked 2006.145.08:32:19.61/valo/07,864.99,yes,locked 2006.145.08:32:19.61/valo/08,884.99,yes,locked 2006.145.08:32:20.70/vb/01,03,usb,yes,35,33 2006.145.08:32:20.70/vb/02,04,usb,yes,31,31 2006.145.08:32:20.70/vb/03,04,usb,yes,28,31 2006.145.08:32:20.70/vb/04,04,usb,yes,32,31 2006.145.08:32:20.70/vb/05,04,usb,yes,25,27 2006.145.08:32:20.70/vb/06,04,usb,yes,29,26 2006.145.08:32:20.70/vb/07,04,usb,yes,29,29 2006.145.08:32:20.70/vb/08,04,usb,yes,27,30 2006.145.08:32:20.93/vblo/01,629.99,yes,locked 2006.145.08:32:20.93/vblo/02,634.99,yes,locked 2006.145.08:32:20.93/vblo/03,649.99,yes,locked 2006.145.08:32:20.93/vblo/04,679.99,yes,locked 2006.145.08:32:20.93/vblo/05,709.99,yes,locked 2006.145.08:32:20.93/vblo/06,719.99,yes,locked 2006.145.08:32:20.93/vblo/07,734.99,yes,locked 2006.145.08:32:20.93/vblo/08,744.99,yes,locked 2006.145.08:32:21.08/vabw/8 2006.145.08:32:21.23/vbbw/8 2006.145.08:32:21.32/xfe/off,on,14.7 2006.145.08:32:21.71/ifatt/23,28,28,28 2006.145.08:32:22.07/fmout-gps/S +5.2E-08 2006.145.08:32:22.11:!2006.145.08:39:08 2006.145.08:39:08.00:data_valid=off 2006.145.08:39:08.00:"et 2006.145.08:39:08.01:!+3s 2006.145.08:39:11.02:"tape 2006.145.08:39:11.02:postob 2006.145.08:39:11.17/cable/+6.5405E-03 2006.145.08:39:11.17/wx/18.42,1017.7,67 2006.145.08:39:12.08/fmout-gps/S +5.5E-08 2006.145.08:39:12.08:scan_name=145-0845,jd0605,50 2006.145.08:39:12.09:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.145.08:39:13.13#flagr#flagr/antenna,new-source 2006.145.08:39:13.13:checkk5 2006.145.08:39:13.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.08:39:14.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.08:39:14.44/chk_autoobs//k5ts3/ autoobs is running! 2006.145.08:39:14.87/chk_autoobs//k5ts4/ autoobs is running! 2006.145.08:39:15.31/chk_obsdata//k5ts1/T1450832??a.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.145.08:39:15.76/chk_obsdata//k5ts2/T1450832??b.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.145.08:39:16.22/chk_obsdata//k5ts3/T1450832??c.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.145.08:39:16.65/chk_obsdata//k5ts4/T1450832??d.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.145.08:39:17.42/k5log//k5ts1_log_newline 2006.145.08:39:18.18/k5log//k5ts2_log_newline 2006.145.08:39:18.92/k5log//k5ts3_log_newline 2006.145.08:39:19.66/k5log//k5ts4_log_newline 2006.145.08:39:19.69/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.08:39:19.69:setupk4=1 2006.145.08:39:19.69$setupk4/echo=on 2006.145.08:39:19.69$setupk4/pcalon 2006.145.08:39:19.69$pcalon/"no phase cal control is implemented here 2006.145.08:39:19.69$setupk4/"tpicd=stop 2006.145.08:39:19.69$setupk4/"rec=synch_on 2006.145.08:39:19.69$setupk4/"rec_mode=128 2006.145.08:39:19.69$setupk4/!* 2006.145.08:39:19.69$setupk4/recpk4 2006.145.08:39:19.69$recpk4/recpatch= 2006.145.08:39:19.69$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.08:39:19.69$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.08:39:19.69$setupk4/vck44 2006.145.08:39:19.69$vck44/valo=1,524.99 2006.145.08:39:19.69#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.08:39:19.69#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.08:39:19.69#ibcon#ireg 17 cls_cnt 0 2006.145.08:39:19.69#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:39:19.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:39:19.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:39:19.73#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.08:39:19.78#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:39:19.78#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:39:19.78#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.08:39:19.78#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.08:39:19.78$vck44/va=1,8 2006.145.08:39:19.78#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.08:39:19.78#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.08:39:19.78#ibcon#ireg 11 cls_cnt 2 2006.145.08:39:19.78#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.08:39:19.78#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.08:39:19.78#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.08:39:19.80#ibcon#[25=AT01-08\r\n] 2006.145.08:39:19.83#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.08:39:19.83#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.08:39:19.83#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.08:39:19.83#ibcon#ireg 7 cls_cnt 0 2006.145.08:39:19.83#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.08:39:19.95#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.08:39:19.95#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.08:39:19.97#ibcon#[25=USB\r\n] 2006.145.08:39:20.00#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.08:39:20.00#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.08:39:20.00#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.08:39:20.00#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.08:39:20.00$vck44/valo=2,534.99 2006.145.08:39:20.00#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.08:39:20.00#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.08:39:20.00#ibcon#ireg 17 cls_cnt 0 2006.145.08:39:20.00#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:39:20.00#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:39:20.00#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:39:20.03#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.08:39:20.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:39:20.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:39:20.07#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.08:39:20.07#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.08:39:20.07$vck44/va=2,7 2006.145.08:39:20.07#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.08:39:20.07#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.08:39:20.07#ibcon#ireg 11 cls_cnt 2 2006.145.08:39:20.07#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:39:20.12#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:39:20.12#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:39:20.14#ibcon#[25=AT02-07\r\n] 2006.145.08:39:20.17#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:39:20.17#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:39:20.17#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.08:39:20.17#ibcon#ireg 7 cls_cnt 0 2006.145.08:39:20.17#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:39:20.29#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:39:20.29#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:39:20.31#ibcon#[25=USB\r\n] 2006.145.08:39:20.34#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:39:20.34#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:39:20.34#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.08:39:20.34#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.08:39:20.34$vck44/valo=3,564.99 2006.145.08:39:20.34#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.08:39:20.34#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.08:39:20.34#ibcon#ireg 17 cls_cnt 0 2006.145.08:39:20.34#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:39:20.34#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:39:20.34#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:39:20.36#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.08:39:20.40#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:39:20.40#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:39:20.40#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.08:39:20.40#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.08:39:20.40$vck44/va=3,8 2006.145.08:39:20.40#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.08:39:20.40#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.08:39:20.40#ibcon#ireg 11 cls_cnt 2 2006.145.08:39:20.40#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:39:20.46#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:39:20.46#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:39:20.48#ibcon#[25=AT03-08\r\n] 2006.145.08:39:20.51#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:39:20.51#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:39:20.51#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.08:39:20.51#ibcon#ireg 7 cls_cnt 0 2006.145.08:39:20.51#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:39:20.63#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:39:20.63#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:39:20.65#ibcon#[25=USB\r\n] 2006.145.08:39:20.68#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:39:20.68#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:39:20.68#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.08:39:20.68#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.08:39:20.68$vck44/valo=4,624.99 2006.145.08:39:20.68#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.08:39:20.68#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.08:39:20.68#ibcon#ireg 17 cls_cnt 0 2006.145.08:39:20.68#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:39:20.68#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:39:20.68#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:39:20.70#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.08:39:20.74#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:39:20.74#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:39:20.74#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.08:39:20.74#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.08:39:20.74$vck44/va=4,7 2006.145.08:39:20.74#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.08:39:20.74#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.08:39:20.74#ibcon#ireg 11 cls_cnt 2 2006.145.08:39:20.74#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:39:20.80#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:39:20.80#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:39:20.82#ibcon#[25=AT04-07\r\n] 2006.145.08:39:20.85#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:39:20.85#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:39:20.85#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.08:39:20.85#ibcon#ireg 7 cls_cnt 0 2006.145.08:39:20.85#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:39:20.97#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:39:20.97#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:39:20.99#ibcon#[25=USB\r\n] 2006.145.08:39:21.02#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:39:21.02#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:39:21.02#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.08:39:21.02#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.08:39:21.02$vck44/valo=5,734.99 2006.145.08:39:21.02#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.08:39:21.02#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.08:39:21.02#ibcon#ireg 17 cls_cnt 0 2006.145.08:39:21.02#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:39:21.02#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:39:21.02#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:39:21.04#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.08:39:21.08#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:39:21.08#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:39:21.08#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.08:39:21.08#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.08:39:21.08$vck44/va=5,4 2006.145.08:39:21.08#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.08:39:21.08#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.08:39:21.08#ibcon#ireg 11 cls_cnt 2 2006.145.08:39:21.08#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:39:21.14#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:39:21.14#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:39:21.16#ibcon#[25=AT05-04\r\n] 2006.145.08:39:21.20#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:39:21.20#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:39:21.20#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.08:39:21.20#ibcon#ireg 7 cls_cnt 0 2006.145.08:39:21.20#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:39:21.32#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:39:21.32#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:39:21.34#ibcon#[25=USB\r\n] 2006.145.08:39:21.37#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:39:21.37#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:39:21.37#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.08:39:21.37#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.08:39:21.37$vck44/valo=6,814.99 2006.145.08:39:21.37#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.08:39:21.37#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.08:39:21.37#ibcon#ireg 17 cls_cnt 0 2006.145.08:39:21.37#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:39:21.37#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:39:21.37#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:39:21.39#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.08:39:21.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:39:21.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:39:21.43#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.08:39:21.43#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.08:39:21.43$vck44/va=6,4 2006.145.08:39:21.43#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.08:39:21.43#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.08:39:21.43#ibcon#ireg 11 cls_cnt 2 2006.145.08:39:21.43#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:39:21.49#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:39:21.49#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:39:21.51#ibcon#[25=AT06-04\r\n] 2006.145.08:39:21.54#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:39:21.54#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:39:21.54#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.08:39:21.54#ibcon#ireg 7 cls_cnt 0 2006.145.08:39:21.54#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:39:21.66#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:39:21.66#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:39:21.68#ibcon#[25=USB\r\n] 2006.145.08:39:21.71#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:39:21.71#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:39:21.71#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.08:39:21.71#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.08:39:21.71$vck44/valo=7,864.99 2006.145.08:39:21.71#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.08:39:21.71#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.08:39:21.71#ibcon#ireg 17 cls_cnt 0 2006.145.08:39:21.71#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:39:21.71#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:39:21.71#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:39:21.73#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.08:39:21.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:39:21.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:39:21.77#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.08:39:21.77#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.08:39:21.77$vck44/va=7,4 2006.145.08:39:21.77#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.08:39:21.77#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.08:39:21.77#ibcon#ireg 11 cls_cnt 2 2006.145.08:39:21.77#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:39:21.83#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:39:21.83#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:39:21.85#ibcon#[25=AT07-04\r\n] 2006.145.08:39:21.88#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:39:21.88#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:39:21.88#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.08:39:21.88#ibcon#ireg 7 cls_cnt 0 2006.145.08:39:21.88#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:39:22.00#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:39:22.00#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:39:22.02#ibcon#[25=USB\r\n] 2006.145.08:39:22.05#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:39:22.05#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:39:22.05#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.08:39:22.05#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.08:39:22.05$vck44/valo=8,884.99 2006.145.08:39:22.05#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.08:39:22.05#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.08:39:22.05#ibcon#ireg 17 cls_cnt 0 2006.145.08:39:22.05#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:39:22.05#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:39:22.05#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:39:22.07#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.08:39:22.11#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:39:22.11#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:39:22.11#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.08:39:22.11#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.08:39:22.11$vck44/va=8,4 2006.145.08:39:22.11#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.08:39:22.11#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.08:39:22.11#ibcon#ireg 11 cls_cnt 2 2006.145.08:39:22.11#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:39:22.17#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:39:22.17#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:39:22.19#ibcon#[25=AT08-04\r\n] 2006.145.08:39:22.22#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:39:22.22#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:39:22.22#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.08:39:22.22#ibcon#ireg 7 cls_cnt 0 2006.145.08:39:22.22#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:39:22.34#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:39:22.34#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:39:22.36#ibcon#[25=USB\r\n] 2006.145.08:39:22.39#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:39:22.39#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:39:22.39#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.08:39:22.39#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.08:39:22.39$vck44/vblo=1,629.99 2006.145.08:39:22.39#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.08:39:22.39#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.08:39:22.39#ibcon#ireg 17 cls_cnt 0 2006.145.08:39:22.39#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:39:22.39#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:39:22.39#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:39:22.41#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.08:39:22.45#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:39:22.45#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:39:22.45#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.08:39:22.45#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.08:39:22.45$vck44/vb=1,3 2006.145.08:39:22.45#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.08:39:22.45#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.08:39:22.45#ibcon#ireg 11 cls_cnt 2 2006.145.08:39:22.45#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:39:22.45#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:39:22.45#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:39:22.47#ibcon#[27=AT01-03\r\n] 2006.145.08:39:22.50#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:39:22.50#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:39:22.50#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.08:39:22.50#ibcon#ireg 7 cls_cnt 0 2006.145.08:39:22.50#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:39:22.62#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:39:22.62#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:39:22.64#ibcon#[27=USB\r\n] 2006.145.08:39:22.67#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:39:22.67#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:39:22.67#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.08:39:22.67#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.08:39:22.67$vck44/vblo=2,634.99 2006.145.08:39:22.67#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.08:39:22.67#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.08:39:22.67#ibcon#ireg 17 cls_cnt 0 2006.145.08:39:22.67#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:39:22.67#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:39:22.67#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:39:22.69#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.08:39:22.73#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:39:22.73#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:39:22.73#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.08:39:22.73#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.08:39:22.73$vck44/vb=2,4 2006.145.08:39:22.73#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.08:39:22.73#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.08:39:22.73#ibcon#ireg 11 cls_cnt 2 2006.145.08:39:22.73#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.08:39:22.79#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.08:39:22.79#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.08:39:22.81#ibcon#[27=AT02-04\r\n] 2006.145.08:39:22.84#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.08:39:22.84#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.08:39:22.84#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.08:39:22.84#ibcon#ireg 7 cls_cnt 0 2006.145.08:39:22.84#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.08:39:22.96#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.08:39:22.96#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.08:39:22.98#ibcon#[27=USB\r\n] 2006.145.08:39:23.01#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.08:39:23.01#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.08:39:23.01#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.08:39:23.01#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.08:39:23.01$vck44/vblo=3,649.99 2006.145.08:39:23.01#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.08:39:23.01#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.08:39:23.01#ibcon#ireg 17 cls_cnt 0 2006.145.08:39:23.01#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:39:23.01#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:39:23.01#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:39:23.03#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.08:39:23.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:39:23.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:39:23.07#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.08:39:23.07#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.08:39:23.07$vck44/vb=3,4 2006.145.08:39:23.07#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.08:39:23.07#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.08:39:23.07#ibcon#ireg 11 cls_cnt 2 2006.145.08:39:23.07#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:39:23.13#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:39:23.13#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:39:23.15#ibcon#[27=AT03-04\r\n] 2006.145.08:39:23.18#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:39:23.18#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:39:23.18#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.08:39:23.18#ibcon#ireg 7 cls_cnt 0 2006.145.08:39:23.18#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:39:23.30#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:39:23.30#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:39:23.32#ibcon#[27=USB\r\n] 2006.145.08:39:23.35#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:39:23.35#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:39:23.35#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.08:39:23.35#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.08:39:23.35$vck44/vblo=4,679.99 2006.145.08:39:23.35#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.08:39:23.35#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.08:39:23.35#ibcon#ireg 17 cls_cnt 0 2006.145.08:39:23.35#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:39:23.35#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:39:23.35#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:39:23.37#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.08:39:23.41#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:39:23.41#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:39:23.41#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.08:39:23.41#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.08:39:23.41$vck44/vb=4,4 2006.145.08:39:23.41#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.08:39:23.41#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.08:39:23.41#ibcon#ireg 11 cls_cnt 2 2006.145.08:39:23.41#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:39:23.47#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:39:23.47#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:39:23.49#ibcon#[27=AT04-04\r\n] 2006.145.08:39:23.52#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:39:23.52#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:39:23.52#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.08:39:23.52#ibcon#ireg 7 cls_cnt 0 2006.145.08:39:23.52#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:39:23.64#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:39:23.64#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:39:23.66#ibcon#[27=USB\r\n] 2006.145.08:39:23.69#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:39:23.69#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:39:23.69#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.08:39:23.69#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.08:39:23.69$vck44/vblo=5,709.99 2006.145.08:39:23.69#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.08:39:23.69#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.08:39:23.69#ibcon#ireg 17 cls_cnt 0 2006.145.08:39:23.69#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:39:23.69#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:39:23.69#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:39:23.71#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.08:39:23.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:39:23.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:39:23.75#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.08:39:23.75#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.08:39:23.75$vck44/vb=5,4 2006.145.08:39:23.75#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.08:39:23.75#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.08:39:23.75#ibcon#ireg 11 cls_cnt 2 2006.145.08:39:23.75#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:39:23.81#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:39:23.81#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:39:23.83#ibcon#[27=AT05-04\r\n] 2006.145.08:39:23.86#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:39:23.86#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:39:23.86#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.08:39:23.86#ibcon#ireg 7 cls_cnt 0 2006.145.08:39:23.86#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:39:23.98#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:39:23.98#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:39:24.00#ibcon#[27=USB\r\n] 2006.145.08:39:24.03#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:39:24.03#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:39:24.03#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.08:39:24.03#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.08:39:24.03$vck44/vblo=6,719.99 2006.145.08:39:24.03#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.08:39:24.03#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.08:39:24.03#ibcon#ireg 17 cls_cnt 0 2006.145.08:39:24.03#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:39:24.03#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:39:24.03#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:39:24.05#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.08:39:24.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:39:24.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:39:24.09#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.08:39:24.09#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.08:39:24.09$vck44/vb=6,4 2006.145.08:39:24.09#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.08:39:24.09#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.08:39:24.09#ibcon#ireg 11 cls_cnt 2 2006.145.08:39:24.09#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:39:24.15#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:39:24.15#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:39:24.17#ibcon#[27=AT06-04\r\n] 2006.145.08:39:24.20#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:39:24.20#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:39:24.20#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.08:39:24.20#ibcon#ireg 7 cls_cnt 0 2006.145.08:39:24.20#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:39:24.32#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:39:24.32#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:39:24.34#ibcon#[27=USB\r\n] 2006.145.08:39:24.37#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:39:24.37#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:39:24.37#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.08:39:24.37#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.08:39:24.37$vck44/vblo=7,734.99 2006.145.08:39:24.37#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.08:39:24.37#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.08:39:24.37#ibcon#ireg 17 cls_cnt 0 2006.145.08:39:24.37#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:39:24.37#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:39:24.37#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:39:24.39#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.08:39:24.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:39:24.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:39:24.43#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.08:39:24.43#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.08:39:24.43$vck44/vb=7,4 2006.145.08:39:24.43#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.08:39:24.43#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.08:39:24.43#ibcon#ireg 11 cls_cnt 2 2006.145.08:39:24.43#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:39:24.49#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:39:24.49#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:39:24.51#ibcon#[27=AT07-04\r\n] 2006.145.08:39:24.54#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:39:24.54#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:39:24.54#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.08:39:24.54#ibcon#ireg 7 cls_cnt 0 2006.145.08:39:24.54#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:39:24.66#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:39:24.66#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:39:24.68#ibcon#[27=USB\r\n] 2006.145.08:39:24.71#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:39:24.71#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:39:24.71#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.08:39:24.71#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.08:39:24.71$vck44/vblo=8,744.99 2006.145.08:39:24.71#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.08:39:24.71#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.08:39:24.71#ibcon#ireg 17 cls_cnt 0 2006.145.08:39:24.71#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:39:24.71#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:39:24.71#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:39:24.73#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.08:39:24.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:39:24.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:39:24.77#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.08:39:24.77#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.08:39:24.77$vck44/vb=8,4 2006.145.08:39:24.77#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.08:39:24.77#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.08:39:24.77#ibcon#ireg 11 cls_cnt 2 2006.145.08:39:24.77#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:39:24.83#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:39:24.83#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:39:24.85#ibcon#[27=AT08-04\r\n] 2006.145.08:39:24.88#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:39:24.88#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:39:24.88#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.08:39:24.88#ibcon#ireg 7 cls_cnt 0 2006.145.08:39:24.88#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:39:25.00#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:39:25.00#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:39:25.02#ibcon#[27=USB\r\n] 2006.145.08:39:25.05#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:39:25.05#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:39:25.05#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.08:39:25.05#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.08:39:25.05$vck44/vabw=wide 2006.145.08:39:25.05#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.08:39:25.05#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.08:39:25.05#ibcon#ireg 8 cls_cnt 0 2006.145.08:39:25.05#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:39:25.05#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:39:25.05#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:39:25.07#ibcon#[25=BW32\r\n] 2006.145.08:39:25.10#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:39:25.10#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:39:25.10#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.08:39:25.10#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.08:39:25.10$vck44/vbbw=wide 2006.145.08:39:25.10#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.08:39:25.10#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.08:39:25.10#ibcon#ireg 8 cls_cnt 0 2006.145.08:39:25.10#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.08:39:25.17#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.08:39:25.17#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.08:39:25.19#ibcon#[27=BW32\r\n] 2006.145.08:39:25.22#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.08:39:25.22#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.08:39:25.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.08:39:25.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.08:39:25.22$setupk4/ifdk4 2006.145.08:39:25.22$ifdk4/lo= 2006.145.08:39:25.22$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.08:39:25.22$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.08:39:25.22$ifdk4/patch= 2006.145.08:39:25.22$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.08:39:25.22$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.08:39:25.22$setupk4/!*+20s 2006.145.08:39:28.33#abcon#<5=/05 4.1 6.8 18.42 661017.7\r\n> 2006.145.08:39:28.35#abcon#{5=INTERFACE CLEAR} 2006.145.08:39:28.41#abcon#[5=S1D000X0/0*\r\n] 2006.145.08:39:38.50#abcon#<5=/05 4.1 6.8 18.42 661017.7\r\n> 2006.145.08:39:38.52#abcon#{5=INTERFACE CLEAR} 2006.145.08:39:38.58#abcon#[5=S1D000X0/0*\r\n] 2006.145.08:39:39.70$setupk4/"tpicd 2006.145.08:39:39.70$setupk4/echo=off 2006.145.08:39:39.70$setupk4/xlog=off 2006.145.08:39:39.70:!2006.145.08:44:55 2006.145.08:40:10.13#trakl#Source acquired 2006.145.08:40:11.13#flagr#flagr/antenna,acquired 2006.145.08:44:55.00:preob 2006.145.08:44:55.14/onsource/TRACKING 2006.145.08:44:55.14:!2006.145.08:45:05 2006.145.08:45:05.00:"tape 2006.145.08:45:05.00:"st=record 2006.145.08:45:05.00:data_valid=on 2006.145.08:45:05.00:midob 2006.145.08:45:05.14/onsource/TRACKING 2006.145.08:45:05.14/wx/18.37,1017.7,67 2006.145.08:45:05.26/cable/+6.5411E-03 2006.145.08:45:06.35/va/01,08,usb,yes,28,31 2006.145.08:45:06.35/va/02,07,usb,yes,30,31 2006.145.08:45:06.35/va/03,08,usb,yes,28,29 2006.145.08:45:06.35/va/04,07,usb,yes,31,33 2006.145.08:45:06.35/va/05,04,usb,yes,27,28 2006.145.08:45:06.35/va/06,04,usb,yes,31,31 2006.145.08:45:06.35/va/07,04,usb,yes,31,32 2006.145.08:45:06.35/va/08,04,usb,yes,26,32 2006.145.08:45:06.58/valo/01,524.99,yes,locked 2006.145.08:45:06.58/valo/02,534.99,yes,locked 2006.145.08:45:06.58/valo/03,564.99,yes,locked 2006.145.08:45:06.58/valo/04,624.99,yes,locked 2006.145.08:45:06.58/valo/05,734.99,yes,locked 2006.145.08:45:06.58/valo/06,814.99,yes,locked 2006.145.08:45:06.58/valo/07,864.99,yes,locked 2006.145.08:45:06.58/valo/08,884.99,yes,locked 2006.145.08:45:07.67/vb/01,03,usb,yes,36,34 2006.145.08:45:07.67/vb/02,04,usb,yes,32,31 2006.145.08:45:07.67/vb/03,04,usb,yes,29,31 2006.145.08:45:07.67/vb/04,04,usb,yes,33,32 2006.145.08:45:07.67/vb/05,04,usb,yes,25,28 2006.145.08:45:07.67/vb/06,04,usb,yes,30,26 2006.145.08:45:07.67/vb/07,04,usb,yes,30,29 2006.145.08:45:07.67/vb/08,04,usb,yes,27,30 2006.145.08:45:07.90/vblo/01,629.99,yes,locked 2006.145.08:45:07.90/vblo/02,634.99,yes,locked 2006.145.08:45:07.90/vblo/03,649.99,yes,locked 2006.145.08:45:07.90/vblo/04,679.99,yes,locked 2006.145.08:45:07.90/vblo/05,709.99,yes,locked 2006.145.08:45:07.90/vblo/06,719.99,yes,locked 2006.145.08:45:07.90/vblo/07,734.99,yes,locked 2006.145.08:45:07.90/vblo/08,744.99,yes,locked 2006.145.08:45:08.05/vabw/8 2006.145.08:45:08.20/vbbw/8 2006.145.08:45:08.29/xfe/off,on,15.2 2006.145.08:45:08.66/ifatt/23,28,28,28 2006.145.08:45:09.08/fmout-gps/S +5.4E-08 2006.145.08:45:09.12:!2006.145.08:45:55 2006.145.08:45:55.00:data_valid=off 2006.145.08:45:55.00:"et 2006.145.08:45:55.00:!+3s 2006.145.08:45:58.02:"tape 2006.145.08:45:58.02:postob 2006.145.08:45:58.20/cable/+6.5405E-03 2006.145.08:45:58.20/wx/18.36,1017.7,66 2006.145.08:45:59.08/fmout-gps/S +5.3E-08 2006.145.08:45:59.08:scan_name=145-0848,jd0605,40 2006.145.08:45:59.08:source=3c345,164258.81,394837.0,2000.0,cw 2006.145.08:46:00.14#flagr#flagr/antenna,new-source 2006.145.08:46:00.14:checkk5 2006.145.08:46:00.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.08:46:01.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.08:46:01.45/chk_autoobs//k5ts3/ autoobs is running! 2006.145.08:46:01.88/chk_autoobs//k5ts4/ autoobs is running! 2006.145.08:46:02.30/chk_obsdata//k5ts1/T1450845??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.08:46:02.76/chk_obsdata//k5ts2/T1450845??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.08:46:03.21/chk_obsdata//k5ts3/T1450845??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.08:46:03.63/chk_obsdata//k5ts4/T1450845??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.08:46:04.39/k5log//k5ts1_log_newline 2006.145.08:46:05.14/k5log//k5ts2_log_newline 2006.145.08:46:05.89/k5log//k5ts3_log_newline 2006.145.08:46:06.63/k5log//k5ts4_log_newline 2006.145.08:46:06.65/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.08:46:06.65:setupk4=1 2006.145.08:46:06.65$setupk4/echo=on 2006.145.08:46:06.65$setupk4/pcalon 2006.145.08:46:06.65$pcalon/"no phase cal control is implemented here 2006.145.08:46:06.65$setupk4/"tpicd=stop 2006.145.08:46:06.65$setupk4/"rec=synch_on 2006.145.08:46:06.65$setupk4/"rec_mode=128 2006.145.08:46:06.65$setupk4/!* 2006.145.08:46:06.65$setupk4/recpk4 2006.145.08:46:06.65$recpk4/recpatch= 2006.145.08:46:06.66$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.08:46:06.66$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.08:46:06.66$setupk4/vck44 2006.145.08:46:06.66$vck44/valo=1,524.99 2006.145.08:46:06.66#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.08:46:06.66#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.08:46:06.66#ibcon#ireg 17 cls_cnt 0 2006.145.08:46:06.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.08:46:06.66#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.08:46:06.66#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.08:46:06.69#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.08:46:06.74#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.08:46:06.74#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.08:46:06.74#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.08:46:06.74#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.08:46:06.74$vck44/va=1,8 2006.145.08:46:06.74#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.08:46:06.74#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.08:46:06.74#ibcon#ireg 11 cls_cnt 2 2006.145.08:46:06.74#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.08:46:06.74#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.08:46:06.74#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.08:46:06.76#ibcon#[25=AT01-08\r\n] 2006.145.08:46:06.79#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.08:46:06.79#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.08:46:06.79#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.08:46:06.79#ibcon#ireg 7 cls_cnt 0 2006.145.08:46:06.79#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.08:46:06.91#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.08:46:06.91#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.08:46:06.93#ibcon#[25=USB\r\n] 2006.145.08:46:06.96#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.08:46:06.96#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.08:46:06.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.08:46:06.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.08:46:06.96$vck44/valo=2,534.99 2006.145.08:46:06.96#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.08:46:06.96#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.08:46:06.96#ibcon#ireg 17 cls_cnt 0 2006.145.08:46:06.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.08:46:06.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.08:46:06.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.08:46:06.99#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.08:46:07.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.08:46:07.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.08:46:07.04#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.08:46:07.04#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.08:46:07.04$vck44/va=2,7 2006.145.08:46:07.04#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.08:46:07.04#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.08:46:07.04#ibcon#ireg 11 cls_cnt 2 2006.145.08:46:07.04#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.08:46:07.08#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.08:46:07.08#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.08:46:07.10#ibcon#[25=AT02-07\r\n] 2006.145.08:46:07.13#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.08:46:07.13#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.08:46:07.13#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.08:46:07.13#ibcon#ireg 7 cls_cnt 0 2006.145.08:46:07.13#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.08:46:07.25#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.08:46:07.25#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.08:46:07.27#ibcon#[25=USB\r\n] 2006.145.08:46:07.30#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.08:46:07.30#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.08:46:07.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.08:46:07.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.08:46:07.30$vck44/valo=3,564.99 2006.145.08:46:07.30#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.08:46:07.30#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.08:46:07.30#ibcon#ireg 17 cls_cnt 0 2006.145.08:46:07.30#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:46:07.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:46:07.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:46:07.32#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.08:46:07.36#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:46:07.36#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:46:07.36#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.08:46:07.36#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.08:46:07.36$vck44/va=3,8 2006.145.08:46:07.36#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.08:46:07.36#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.08:46:07.36#ibcon#ireg 11 cls_cnt 2 2006.145.08:46:07.36#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.08:46:07.42#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.08:46:07.42#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.08:46:07.44#ibcon#[25=AT03-08\r\n] 2006.145.08:46:07.47#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.08:46:07.47#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.08:46:07.47#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.08:46:07.47#ibcon#ireg 7 cls_cnt 0 2006.145.08:46:07.47#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.08:46:07.59#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.08:46:07.59#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.08:46:07.61#ibcon#[25=USB\r\n] 2006.145.08:46:07.64#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.08:46:07.64#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.08:46:07.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.08:46:07.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.08:46:07.64$vck44/valo=4,624.99 2006.145.08:46:07.64#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.08:46:07.64#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.08:46:07.64#ibcon#ireg 17 cls_cnt 0 2006.145.08:46:07.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.08:46:07.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.08:46:07.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.08:46:07.66#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.08:46:07.70#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.08:46:07.70#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.08:46:07.70#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.08:46:07.70#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.08:46:07.70$vck44/va=4,7 2006.145.08:46:07.70#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.08:46:07.70#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.08:46:07.70#ibcon#ireg 11 cls_cnt 2 2006.145.08:46:07.70#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.08:46:07.76#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.08:46:07.76#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.08:46:07.78#ibcon#[25=AT04-07\r\n] 2006.145.08:46:07.79#abcon#<5=/05 4.4 7.0 18.36 671017.7\r\n> 2006.145.08:46:07.81#abcon#{5=INTERFACE CLEAR} 2006.145.08:46:07.81#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.08:46:07.81#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.08:46:07.81#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.08:46:07.81#ibcon#ireg 7 cls_cnt 0 2006.145.08:46:07.81#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.08:46:07.87#abcon#[5=S1D000X0/0*\r\n] 2006.145.08:46:07.93#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.08:46:07.93#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.08:46:07.95#ibcon#[25=USB\r\n] 2006.145.08:46:07.98#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.08:46:07.98#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.08:46:07.98#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.08:46:07.98#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.08:46:07.98$vck44/valo=5,734.99 2006.145.08:46:07.98#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.08:46:07.98#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.08:46:07.98#ibcon#ireg 17 cls_cnt 0 2006.145.08:46:07.98#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.08:46:07.98#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.08:46:07.98#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.08:46:08.00#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.08:46:08.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.08:46:08.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.08:46:08.04#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.08:46:08.04#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.08:46:08.04$vck44/va=5,4 2006.145.08:46:08.04#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.08:46:08.04#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.08:46:08.04#ibcon#ireg 11 cls_cnt 2 2006.145.08:46:08.04#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.08:46:08.10#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.08:46:08.10#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.08:46:08.12#ibcon#[25=AT05-04\r\n] 2006.145.08:46:08.16#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.08:46:08.16#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.08:46:08.16#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.08:46:08.16#ibcon#ireg 7 cls_cnt 0 2006.145.08:46:08.16#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.08:46:08.28#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.08:46:08.28#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.08:46:08.30#ibcon#[25=USB\r\n] 2006.145.08:46:08.33#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.08:46:08.33#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.08:46:08.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.08:46:08.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.08:46:08.33$vck44/valo=6,814.99 2006.145.08:46:08.33#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.08:46:08.33#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.08:46:08.33#ibcon#ireg 17 cls_cnt 0 2006.145.08:46:08.33#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.08:46:08.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.08:46:08.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.08:46:08.35#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.08:46:08.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.08:46:08.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.08:46:08.39#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.08:46:08.39#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.08:46:08.39$vck44/va=6,4 2006.145.08:46:08.39#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.08:46:08.39#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.08:46:08.39#ibcon#ireg 11 cls_cnt 2 2006.145.08:46:08.39#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.08:46:08.45#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.08:46:08.45#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.08:46:08.47#ibcon#[25=AT06-04\r\n] 2006.145.08:46:08.50#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.08:46:08.50#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.08:46:08.50#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.08:46:08.50#ibcon#ireg 7 cls_cnt 0 2006.145.08:46:08.50#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.08:46:08.62#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.08:46:08.62#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.08:46:08.64#ibcon#[25=USB\r\n] 2006.145.08:46:08.67#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.08:46:08.67#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.08:46:08.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.08:46:08.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.08:46:08.67$vck44/valo=7,864.99 2006.145.08:46:08.67#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.08:46:08.67#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.08:46:08.67#ibcon#ireg 17 cls_cnt 0 2006.145.08:46:08.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.08:46:08.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.08:46:08.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.08:46:08.69#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.08:46:08.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.08:46:08.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.08:46:08.73#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.08:46:08.73#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.08:46:08.73$vck44/va=7,4 2006.145.08:46:08.73#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.08:46:08.73#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.08:46:08.73#ibcon#ireg 11 cls_cnt 2 2006.145.08:46:08.73#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.08:46:08.79#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.08:46:08.79#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.08:46:08.81#ibcon#[25=AT07-04\r\n] 2006.145.08:46:08.84#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.08:46:08.84#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.08:46:08.84#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.08:46:08.84#ibcon#ireg 7 cls_cnt 0 2006.145.08:46:08.84#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.08:46:08.96#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.08:46:08.96#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.08:46:08.98#ibcon#[25=USB\r\n] 2006.145.08:46:09.01#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.08:46:09.01#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.08:46:09.01#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.08:46:09.01#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.08:46:09.01$vck44/valo=8,884.99 2006.145.08:46:09.01#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.08:46:09.01#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.08:46:09.01#ibcon#ireg 17 cls_cnt 0 2006.145.08:46:09.01#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:46:09.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:46:09.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:46:09.03#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.08:46:09.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:46:09.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:46:09.07#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.08:46:09.07#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.08:46:09.07$vck44/va=8,4 2006.145.08:46:09.07#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.08:46:09.07#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.08:46:09.07#ibcon#ireg 11 cls_cnt 2 2006.145.08:46:09.07#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.08:46:09.13#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.08:46:09.13#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.08:46:09.15#ibcon#[25=AT08-04\r\n] 2006.145.08:46:09.18#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.08:46:09.18#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.08:46:09.18#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.08:46:09.18#ibcon#ireg 7 cls_cnt 0 2006.145.08:46:09.18#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.08:46:09.31#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.08:46:09.31#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.08:46:09.33#ibcon#[25=USB\r\n] 2006.145.08:46:09.36#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.08:46:09.36#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.08:46:09.36#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.08:46:09.36#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.08:46:09.36$vck44/vblo=1,629.99 2006.145.08:46:09.36#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.08:46:09.36#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.08:46:09.36#ibcon#ireg 17 cls_cnt 0 2006.145.08:46:09.36#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.08:46:09.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.08:46:09.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.08:46:09.39#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.08:46:09.43#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.08:46:09.43#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.08:46:09.43#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.08:46:09.43#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.08:46:09.43$vck44/vb=1,3 2006.145.08:46:09.43#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.08:46:09.43#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.08:46:09.43#ibcon#ireg 11 cls_cnt 2 2006.145.08:46:09.43#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.08:46:09.43#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.08:46:09.43#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.08:46:09.45#ibcon#[27=AT01-03\r\n] 2006.145.08:46:09.48#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.08:46:09.48#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.08:46:09.48#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.08:46:09.48#ibcon#ireg 7 cls_cnt 0 2006.145.08:46:09.48#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.08:46:09.60#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.08:46:09.60#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.08:46:09.62#ibcon#[27=USB\r\n] 2006.145.08:46:09.65#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.08:46:09.65#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.08:46:09.65#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.08:46:09.65#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.08:46:09.65$vck44/vblo=2,634.99 2006.145.08:46:09.65#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.08:46:09.65#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.08:46:09.65#ibcon#ireg 17 cls_cnt 0 2006.145.08:46:09.65#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.08:46:09.65#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.08:46:09.65#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.08:46:09.67#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.08:46:09.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.08:46:09.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.08:46:09.71#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.08:46:09.71#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.08:46:09.71$vck44/vb=2,4 2006.145.08:46:09.71#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.08:46:09.71#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.08:46:09.71#ibcon#ireg 11 cls_cnt 2 2006.145.08:46:09.71#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.08:46:09.77#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.08:46:09.77#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.08:46:09.79#ibcon#[27=AT02-04\r\n] 2006.145.08:46:09.82#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.08:46:09.82#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.08:46:09.82#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.08:46:09.82#ibcon#ireg 7 cls_cnt 0 2006.145.08:46:09.82#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.08:46:09.94#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.08:46:09.94#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.08:46:09.96#ibcon#[27=USB\r\n] 2006.145.08:46:09.99#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.08:46:09.99#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.08:46:09.99#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.08:46:09.99#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.08:46:09.99$vck44/vblo=3,649.99 2006.145.08:46:09.99#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.08:46:09.99#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.08:46:09.99#ibcon#ireg 17 cls_cnt 0 2006.145.08:46:09.99#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:46:09.99#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:46:09.99#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:46:10.01#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.08:46:10.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:46:10.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.08:46:10.05#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.08:46:10.05#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.08:46:10.05$vck44/vb=3,4 2006.145.08:46:10.05#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.08:46:10.05#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.08:46:10.05#ibcon#ireg 11 cls_cnt 2 2006.145.08:46:10.05#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.08:46:10.11#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.08:46:10.11#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.08:46:10.13#ibcon#[27=AT03-04\r\n] 2006.145.08:46:10.16#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.08:46:10.16#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.08:46:10.16#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.08:46:10.16#ibcon#ireg 7 cls_cnt 0 2006.145.08:46:10.16#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.08:46:10.28#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.08:46:10.28#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.08:46:10.30#ibcon#[27=USB\r\n] 2006.145.08:46:10.33#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.08:46:10.33#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.08:46:10.33#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.08:46:10.33#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.08:46:10.33$vck44/vblo=4,679.99 2006.145.08:46:10.33#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.08:46:10.33#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.08:46:10.33#ibcon#ireg 17 cls_cnt 0 2006.145.08:46:10.33#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.08:46:10.33#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.08:46:10.33#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.08:46:10.35#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.08:46:10.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.08:46:10.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.08:46:10.39#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.08:46:10.39#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.08:46:10.39$vck44/vb=4,4 2006.145.08:46:10.39#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.08:46:10.39#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.08:46:10.39#ibcon#ireg 11 cls_cnt 2 2006.145.08:46:10.39#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.08:46:10.46#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.08:46:10.46#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.08:46:10.48#ibcon#[27=AT04-04\r\n] 2006.145.08:46:10.51#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.08:46:10.51#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.08:46:10.51#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.08:46:10.51#ibcon#ireg 7 cls_cnt 0 2006.145.08:46:10.51#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.08:46:10.63#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.08:46:10.63#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.08:46:10.65#ibcon#[27=USB\r\n] 2006.145.08:46:10.68#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.08:46:10.68#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.08:46:10.68#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.08:46:10.68#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.08:46:10.68$vck44/vblo=5,709.99 2006.145.08:46:10.68#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.08:46:10.68#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.08:46:10.68#ibcon#ireg 17 cls_cnt 0 2006.145.08:46:10.68#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.08:46:10.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.08:46:10.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.08:46:10.70#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.08:46:10.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.08:46:10.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.08:46:10.74#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.08:46:10.74#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.08:46:10.74$vck44/vb=5,4 2006.145.08:46:10.74#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.08:46:10.74#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.08:46:10.74#ibcon#ireg 11 cls_cnt 2 2006.145.08:46:10.74#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.08:46:10.80#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.08:46:10.80#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.08:46:10.82#ibcon#[27=AT05-04\r\n] 2006.145.08:46:10.85#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.08:46:10.85#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.08:46:10.85#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.08:46:10.85#ibcon#ireg 7 cls_cnt 0 2006.145.08:46:10.85#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.08:46:10.97#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.08:46:10.97#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.08:46:10.99#ibcon#[27=USB\r\n] 2006.145.08:46:11.02#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.08:46:11.02#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.08:46:11.02#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.08:46:11.02#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.08:46:11.02$vck44/vblo=6,719.99 2006.145.08:46:11.02#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.08:46:11.02#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.08:46:11.02#ibcon#ireg 17 cls_cnt 0 2006.145.08:46:11.02#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.08:46:11.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.08:46:11.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.08:46:11.04#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.08:46:11.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.08:46:11.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.08:46:11.08#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.08:46:11.08#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.08:46:11.08$vck44/vb=6,4 2006.145.08:46:11.08#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.08:46:11.08#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.08:46:11.08#ibcon#ireg 11 cls_cnt 2 2006.145.08:46:11.08#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.08:46:11.14#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.08:46:11.14#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.08:46:11.16#ibcon#[27=AT06-04\r\n] 2006.145.08:46:11.19#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.08:46:11.19#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.08:46:11.19#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.08:46:11.19#ibcon#ireg 7 cls_cnt 0 2006.145.08:46:11.19#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.08:46:11.31#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.08:46:11.31#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.08:46:11.33#ibcon#[27=USB\r\n] 2006.145.08:46:11.36#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.08:46:11.36#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.08:46:11.36#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.08:46:11.36#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.08:46:11.36$vck44/vblo=7,734.99 2006.145.08:46:11.36#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.08:46:11.36#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.08:46:11.36#ibcon#ireg 17 cls_cnt 0 2006.145.08:46:11.36#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.08:46:11.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.08:46:11.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.08:46:11.38#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.08:46:11.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.08:46:11.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.08:46:11.42#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.08:46:11.42#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.08:46:11.42$vck44/vb=7,4 2006.145.08:46:11.42#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.08:46:11.42#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.08:46:11.42#ibcon#ireg 11 cls_cnt 2 2006.145.08:46:11.42#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.08:46:11.48#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.08:46:11.48#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.08:46:11.50#ibcon#[27=AT07-04\r\n] 2006.145.08:46:11.53#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.08:46:11.53#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.08:46:11.53#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.08:46:11.53#ibcon#ireg 7 cls_cnt 0 2006.145.08:46:11.53#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.08:46:11.65#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.08:46:11.65#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.08:46:11.67#ibcon#[27=USB\r\n] 2006.145.08:46:11.70#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.08:46:11.70#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.08:46:11.70#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.08:46:11.70#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.08:46:11.70$vck44/vblo=8,744.99 2006.145.08:46:11.70#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.08:46:11.70#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.08:46:11.70#ibcon#ireg 17 cls_cnt 0 2006.145.08:46:11.70#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.08:46:11.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.08:46:11.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.08:46:11.72#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.08:46:11.76#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.08:46:11.76#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.08:46:11.76#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.08:46:11.76#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.08:46:11.76$vck44/vb=8,4 2006.145.08:46:11.76#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.08:46:11.76#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.08:46:11.76#ibcon#ireg 11 cls_cnt 2 2006.145.08:46:11.76#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.08:46:11.82#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.08:46:11.82#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.08:46:11.84#ibcon#[27=AT08-04\r\n] 2006.145.08:46:11.87#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.08:46:11.87#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.08:46:11.87#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.08:46:11.87#ibcon#ireg 7 cls_cnt 0 2006.145.08:46:11.87#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.08:46:11.99#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.08:46:11.99#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.08:46:12.01#ibcon#[27=USB\r\n] 2006.145.08:46:12.04#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.08:46:12.04#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.08:46:12.04#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.08:46:12.04#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.08:46:12.04$vck44/vabw=wide 2006.145.08:46:12.04#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.08:46:12.04#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.08:46:12.04#ibcon#ireg 8 cls_cnt 0 2006.145.08:46:12.04#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:46:12.04#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:46:12.04#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:46:12.06#ibcon#[25=BW32\r\n] 2006.145.08:46:12.09#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:46:12.09#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:46:12.09#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.08:46:12.09#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.08:46:12.09$vck44/vbbw=wide 2006.145.08:46:12.09#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.08:46:12.09#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.08:46:12.09#ibcon#ireg 8 cls_cnt 0 2006.145.08:46:12.09#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:46:12.16#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:46:12.16#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:46:12.18#ibcon#[27=BW32\r\n] 2006.145.08:46:12.21#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:46:12.21#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:46:12.21#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.08:46:12.21#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.08:46:12.21$setupk4/ifdk4 2006.145.08:46:12.21$ifdk4/lo= 2006.145.08:46:12.21$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.08:46:12.21$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.08:46:12.21$ifdk4/patch= 2006.145.08:46:12.21$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.08:46:12.21$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.08:46:12.21$setupk4/!*+20s 2006.145.08:46:17.96#abcon#<5=/05 4.4 7.0 18.36 661017.7\r\n> 2006.145.08:46:17.98#abcon#{5=INTERFACE CLEAR} 2006.145.08:46:18.05#abcon#[5=S1D000X0/0*\r\n] 2006.145.08:46:26.66$setupk4/"tpicd 2006.145.08:46:26.66$setupk4/echo=off 2006.145.08:46:26.66$setupk4/xlog=off 2006.145.08:46:26.66:!2006.145.08:48:33 2006.145.08:46:46.14#trakl#Source acquired 2006.145.08:46:47.14#flagr#flagr/antenna,acquired 2006.145.08:48:33.02:preob 2006.145.08:48:34.14/onsource/TRACKING 2006.145.08:48:34.14:!2006.145.08:48:43 2006.145.08:48:43.01:"tape 2006.145.08:48:43.02:"st=record 2006.145.08:48:43.02:data_valid=on 2006.145.08:48:43.02:midob 2006.145.08:48:44.14/onsource/TRACKING 2006.145.08:48:44.14/wx/18.35,1017.7,68 2006.145.08:48:44.26/cable/+6.5396E-03 2006.145.08:48:45.34/va/01,08,usb,yes,30,33 2006.145.08:48:45.35/va/02,07,usb,yes,33,33 2006.145.08:48:45.35/va/03,08,usb,yes,30,31 2006.145.08:48:45.35/va/04,07,usb,yes,34,35 2006.145.08:48:45.35/va/05,04,usb,yes,29,30 2006.145.08:48:45.35/va/06,04,usb,yes,33,33 2006.145.08:48:45.35/va/07,04,usb,yes,33,35 2006.145.08:48:45.35/va/08,04,usb,yes,28,34 2006.145.08:48:45.58/valo/01,524.99,yes,locked 2006.145.08:48:45.58/valo/02,534.99,yes,locked 2006.145.08:48:45.58/valo/03,564.99,yes,locked 2006.145.08:48:45.58/valo/04,624.99,yes,locked 2006.145.08:48:45.58/valo/05,734.99,yes,locked 2006.145.08:48:45.58/valo/06,814.99,yes,locked 2006.145.08:48:45.58/valo/07,864.99,yes,locked 2006.145.08:48:45.58/valo/08,884.99,yes,locked 2006.145.08:48:46.66/vb/01,03,usb,yes,37,35 2006.145.08:48:46.67/vb/02,04,usb,yes,33,33 2006.145.08:48:46.67/vb/03,04,usb,yes,30,33 2006.145.08:48:46.67/vb/04,04,usb,yes,34,33 2006.145.08:48:46.67/vb/05,04,usb,yes,26,29 2006.145.08:48:46.67/vb/06,04,usb,yes,31,27 2006.145.08:48:46.67/vb/07,04,usb,yes,31,31 2006.145.08:48:46.67/vb/08,04,usb,yes,28,32 2006.145.08:48:46.91/vblo/01,629.99,yes,locked 2006.145.08:48:46.91/vblo/02,634.99,yes,locked 2006.145.08:48:46.91/vblo/03,649.99,yes,locked 2006.145.08:48:46.91/vblo/04,679.99,yes,locked 2006.145.08:48:46.91/vblo/05,709.99,yes,locked 2006.145.08:48:46.91/vblo/06,719.99,yes,locked 2006.145.08:48:46.91/vblo/07,734.99,yes,locked 2006.145.08:48:46.91/vblo/08,744.99,yes,locked 2006.145.08:48:47.05/vabw/8 2006.145.08:48:47.20/vbbw/8 2006.145.08:48:47.32/xfe/off,on,14.7 2006.145.08:48:47.69/ifatt/23,28,28,28 2006.145.08:48:48.07/fmout-gps/S +5.4E-08 2006.145.08:48:48.12:!2006.145.08:49:23 2006.145.08:49:23.02:data_valid=off 2006.145.08:49:23.02:"et 2006.145.08:49:23.02:!+3s 2006.145.08:49:26.05:"tape 2006.145.08:49:26.06:postob 2006.145.08:49:26.17/cable/+6.5393E-03 2006.145.08:49:26.18/wx/18.35,1017.7,67 2006.145.08:49:26.23/fmout-gps/S +5.3E-08 2006.145.08:49:26.24:scan_name=145-0851,jd0605,110 2006.145.08:49:26.24:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.145.08:49:27.13#flagr#flagr/antenna,new-source 2006.145.08:49:27.13:checkk5 2006.145.08:49:27.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.08:49:28.00/chk_autoobs//k5ts2/ autoobs is running! 2006.145.08:49:28.43/chk_autoobs//k5ts3/ autoobs is running! 2006.145.08:49:28.86/chk_autoobs//k5ts4/ autoobs is running! 2006.145.08:49:29.29/chk_obsdata//k5ts1/T1450848??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.08:49:29.73/chk_obsdata//k5ts2/T1450848??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.08:49:30.15/chk_obsdata//k5ts3/T1450848??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.08:49:30.58/chk_obsdata//k5ts4/T1450848??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.08:49:31.35/k5log//k5ts1_log_newline 2006.145.08:49:32.09/k5log//k5ts2_log_newline 2006.145.08:49:32.85/k5log//k5ts3_log_newline 2006.145.08:49:33.60/k5log//k5ts4_log_newline 2006.145.08:49:33.62/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.08:49:33.62:setupk4=1 2006.145.08:49:33.62$setupk4/echo=on 2006.145.08:49:33.62$setupk4/pcalon 2006.145.08:49:33.62$pcalon/"no phase cal control is implemented here 2006.145.08:49:33.62$setupk4/"tpicd=stop 2006.145.08:49:33.62$setupk4/"rec=synch_on 2006.145.08:49:33.62$setupk4/"rec_mode=128 2006.145.08:49:33.62$setupk4/!* 2006.145.08:49:33.62$setupk4/recpk4 2006.145.08:49:33.62$recpk4/recpatch= 2006.145.08:49:33.63$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.08:49:33.63$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.08:49:33.63$setupk4/vck44 2006.145.08:49:33.63$vck44/valo=1,524.99 2006.145.08:49:33.63#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.08:49:33.63#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.08:49:33.63#ibcon#ireg 17 cls_cnt 0 2006.145.08:49:33.63#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.08:49:33.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.08:49:33.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.08:49:33.66#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.08:49:33.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.08:49:33.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.08:49:33.71#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.08:49:33.71#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.08:49:33.72$vck44/va=1,8 2006.145.08:49:33.72#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.08:49:33.72#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.08:49:33.72#ibcon#ireg 11 cls_cnt 2 2006.145.08:49:33.72#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.08:49:33.72#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.08:49:33.72#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.08:49:33.73#ibcon#[25=AT01-08\r\n] 2006.145.08:49:33.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.08:49:33.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.08:49:33.76#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.08:49:33.76#ibcon#ireg 7 cls_cnt 0 2006.145.08:49:33.76#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.08:49:33.88#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.08:49:33.88#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.08:49:33.90#ibcon#[25=USB\r\n] 2006.145.08:49:33.93#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.08:49:33.93#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.08:49:33.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.08:49:33.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.08:49:33.93$vck44/valo=2,534.99 2006.145.08:49:33.94#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.08:49:33.94#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.08:49:33.94#ibcon#ireg 17 cls_cnt 0 2006.145.08:49:33.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:49:33.94#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:49:33.94#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:49:33.97#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.08:49:34.01#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:49:34.01#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:49:34.01#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.08:49:34.01#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.08:49:34.01$vck44/va=2,7 2006.145.08:49:34.01#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.08:49:34.01#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.08:49:34.01#ibcon#ireg 11 cls_cnt 2 2006.145.08:49:34.01#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:49:34.04#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:49:34.04#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:49:34.06#ibcon#[25=AT02-07\r\n] 2006.145.08:49:34.09#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:49:34.09#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:49:34.09#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.08:49:34.09#ibcon#ireg 7 cls_cnt 0 2006.145.08:49:34.10#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:49:34.20#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:49:34.20#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:49:34.22#ibcon#[25=USB\r\n] 2006.145.08:49:34.25#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:49:34.25#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:49:34.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.08:49:34.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.08:49:34.25$vck44/valo=3,564.99 2006.145.08:49:34.26#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.08:49:34.26#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.08:49:34.26#ibcon#ireg 17 cls_cnt 0 2006.145.08:49:34.26#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:49:34.26#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:49:34.26#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:49:34.27#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.08:49:34.31#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:49:34.31#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:49:34.31#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.08:49:34.31#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.08:49:34.32$vck44/va=3,8 2006.145.08:49:34.32#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.08:49:34.32#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.08:49:34.32#ibcon#ireg 11 cls_cnt 2 2006.145.08:49:34.32#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:49:34.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:49:34.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:49:34.38#ibcon#[25=AT03-08\r\n] 2006.145.08:49:34.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:49:34.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:49:34.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.08:49:34.41#ibcon#ireg 7 cls_cnt 0 2006.145.08:49:34.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:49:34.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:49:34.53#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:49:34.55#ibcon#[25=USB\r\n] 2006.145.08:49:34.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:49:34.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:49:34.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.08:49:34.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.08:49:34.58$vck44/valo=4,624.99 2006.145.08:49:34.59#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.08:49:34.59#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.08:49:34.59#ibcon#ireg 17 cls_cnt 0 2006.145.08:49:34.59#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:49:34.59#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:49:34.59#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:49:34.60#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.08:49:34.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:49:34.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:49:34.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.08:49:34.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.08:49:34.64$vck44/va=4,7 2006.145.08:49:34.65#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.08:49:34.65#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.08:49:34.65#ibcon#ireg 11 cls_cnt 2 2006.145.08:49:34.65#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:49:34.69#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:49:34.69#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:49:34.71#ibcon#[25=AT04-07\r\n] 2006.145.08:49:34.74#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:49:34.74#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:49:34.74#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.08:49:34.74#ibcon#ireg 7 cls_cnt 0 2006.145.08:49:34.74#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:49:34.86#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:49:34.86#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:49:34.88#ibcon#[25=USB\r\n] 2006.145.08:49:34.91#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:49:34.91#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:49:34.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.08:49:34.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.08:49:34.92$vck44/valo=5,734.99 2006.145.08:49:34.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.08:49:34.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.08:49:34.92#ibcon#ireg 17 cls_cnt 0 2006.145.08:49:34.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:49:34.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:49:34.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:49:34.93#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.08:49:34.97#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:49:34.97#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:49:34.97#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.08:49:34.97#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.08:49:34.97$vck44/va=5,4 2006.145.08:49:34.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.08:49:34.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.08:49:34.98#ibcon#ireg 11 cls_cnt 2 2006.145.08:49:34.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:49:35.02#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:49:35.02#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:49:35.04#ibcon#[25=AT05-04\r\n] 2006.145.08:49:35.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:49:35.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:49:35.07#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.08:49:35.07#ibcon#ireg 7 cls_cnt 0 2006.145.08:49:35.07#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:49:35.19#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:49:35.19#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:49:35.23#ibcon#[25=USB\r\n] 2006.145.08:49:35.25#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:49:35.25#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:49:35.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.08:49:35.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.08:49:35.25$vck44/valo=6,814.99 2006.145.08:49:35.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.08:49:35.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.08:49:35.26#ibcon#ireg 17 cls_cnt 0 2006.145.08:49:35.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:49:35.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:49:35.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:49:35.27#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.08:49:35.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:49:35.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:49:35.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.08:49:35.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.08:49:35.32$vck44/va=6,4 2006.145.08:49:35.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.08:49:35.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.08:49:35.32#ibcon#ireg 11 cls_cnt 2 2006.145.08:49:35.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:49:35.36#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:49:35.36#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:49:35.38#ibcon#[25=AT06-04\r\n] 2006.145.08:49:35.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:49:35.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:49:35.41#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.08:49:35.41#ibcon#ireg 7 cls_cnt 0 2006.145.08:49:35.41#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:49:35.53#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:49:35.53#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:49:35.55#ibcon#[25=USB\r\n] 2006.145.08:49:35.58#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:49:35.58#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:49:35.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.08:49:35.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.08:49:35.58$vck44/valo=7,864.99 2006.145.08:49:35.59#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.08:49:35.59#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.08:49:35.59#ibcon#ireg 17 cls_cnt 0 2006.145.08:49:35.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:49:35.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:49:35.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:49:35.60#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.08:49:35.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:49:35.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:49:35.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.08:49:35.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.08:49:35.64$vck44/va=7,4 2006.145.08:49:35.65#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.08:49:35.65#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.08:49:35.65#ibcon#ireg 11 cls_cnt 2 2006.145.08:49:35.65#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.08:49:35.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.08:49:35.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.08:49:35.71#ibcon#[25=AT07-04\r\n] 2006.145.08:49:35.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.08:49:35.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.08:49:35.74#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.08:49:35.74#ibcon#ireg 7 cls_cnt 0 2006.145.08:49:35.74#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.08:49:35.86#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.08:49:35.86#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.08:49:35.88#ibcon#[25=USB\r\n] 2006.145.08:49:35.91#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.08:49:35.91#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.08:49:35.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.08:49:35.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.08:49:35.92$vck44/valo=8,884.99 2006.145.08:49:35.92#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.08:49:35.92#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.08:49:35.92#ibcon#ireg 17 cls_cnt 0 2006.145.08:49:35.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.08:49:35.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.08:49:35.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.08:49:35.93#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.08:49:35.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.08:49:35.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.08:49:35.97#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.08:49:35.97#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.08:49:35.97$vck44/va=8,4 2006.145.08:49:35.98#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.08:49:35.98#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.08:49:35.98#ibcon#ireg 11 cls_cnt 2 2006.145.08:49:35.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.08:49:36.02#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.08:49:36.02#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.08:49:36.04#ibcon#[25=AT08-04\r\n] 2006.145.08:49:36.07#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.08:49:36.07#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.08:49:36.07#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.08:49:36.07#ibcon#ireg 7 cls_cnt 0 2006.145.08:49:36.07#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.08:49:36.19#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.08:49:36.19#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.08:49:36.21#ibcon#[25=USB\r\n] 2006.145.08:49:36.24#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.08:49:36.24#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.08:49:36.24#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.08:49:36.24#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.08:49:36.24$vck44/vblo=1,629.99 2006.145.08:49:36.25#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.08:49:36.25#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.08:49:36.25#ibcon#ireg 17 cls_cnt 0 2006.145.08:49:36.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.08:49:36.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.08:49:36.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.08:49:36.26#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.08:49:36.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.08:49:36.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.08:49:36.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.08:49:36.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.08:49:36.30$vck44/vb=1,3 2006.145.08:49:36.31#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.08:49:36.31#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.08:49:36.31#ibcon#ireg 11 cls_cnt 2 2006.145.08:49:36.31#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.08:49:36.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.08:49:36.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.08:49:36.34#ibcon#[27=AT01-03\r\n] 2006.145.08:49:36.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.08:49:36.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.08:49:36.37#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.08:49:36.37#ibcon#ireg 7 cls_cnt 0 2006.145.08:49:36.37#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.08:49:36.49#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.08:49:36.49#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.08:49:36.51#ibcon#[27=USB\r\n] 2006.145.08:49:36.54#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.08:49:36.54#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.08:49:36.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.08:49:36.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.08:49:36.54$vck44/vblo=2,634.99 2006.145.08:49:36.55#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.08:49:36.55#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.08:49:36.55#ibcon#ireg 17 cls_cnt 0 2006.145.08:49:36.55#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.08:49:36.55#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.08:49:36.55#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.08:49:36.58#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.08:49:36.61#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.08:49:36.61#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.08:49:36.61#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.08:49:36.61#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.08:49:36.61$vck44/vb=2,4 2006.145.08:49:36.62#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.08:49:36.62#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.08:49:36.62#ibcon#ireg 11 cls_cnt 2 2006.145.08:49:36.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.08:49:36.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.08:49:36.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.08:49:36.67#ibcon#[27=AT02-04\r\n] 2006.145.08:49:36.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.08:49:36.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.08:49:36.70#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.08:49:36.70#ibcon#ireg 7 cls_cnt 0 2006.145.08:49:36.70#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.08:49:36.82#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.08:49:36.82#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.08:49:36.84#ibcon#[27=USB\r\n] 2006.145.08:49:36.87#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.08:49:36.87#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.08:49:36.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.08:49:36.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.08:49:36.87$vck44/vblo=3,649.99 2006.145.08:49:36.88#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.08:49:36.88#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.08:49:36.88#ibcon#ireg 17 cls_cnt 0 2006.145.08:49:36.88#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:49:36.88#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:49:36.88#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:49:36.89#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.08:49:36.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:49:36.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.08:49:36.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.08:49:36.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.08:49:36.93$vck44/vb=3,4 2006.145.08:49:36.94#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.08:49:36.94#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.08:49:36.94#ibcon#ireg 11 cls_cnt 2 2006.145.08:49:36.94#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:49:36.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:49:36.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:49:37.00#ibcon#[27=AT03-04\r\n] 2006.145.08:49:37.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:49:37.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.08:49:37.03#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.08:49:37.03#ibcon#ireg 7 cls_cnt 0 2006.145.08:49:37.03#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:49:37.15#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:49:37.15#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:49:37.17#ibcon#[27=USB\r\n] 2006.145.08:49:37.20#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:49:37.20#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.08:49:37.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.08:49:37.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.08:49:37.20$vck44/vblo=4,679.99 2006.145.08:49:37.21#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.08:49:37.21#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.08:49:37.21#ibcon#ireg 17 cls_cnt 0 2006.145.08:49:37.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:49:37.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:49:37.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:49:37.22#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.08:49:37.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:49:37.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.08:49:37.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.08:49:37.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.08:49:37.26$vck44/vb=4,4 2006.145.08:49:37.27#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.08:49:37.27#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.08:49:37.27#ibcon#ireg 11 cls_cnt 2 2006.145.08:49:37.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:49:37.31#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:49:37.31#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:49:37.33#ibcon#[27=AT04-04\r\n] 2006.145.08:49:37.36#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:49:37.36#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.08:49:37.36#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.08:49:37.36#ibcon#ireg 7 cls_cnt 0 2006.145.08:49:37.36#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:49:37.48#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:49:37.48#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:49:37.50#ibcon#[27=USB\r\n] 2006.145.08:49:37.53#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:49:37.53#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.08:49:37.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.08:49:37.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.08:49:37.53$vck44/vblo=5,709.99 2006.145.08:49:37.54#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.08:49:37.54#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.08:49:37.54#ibcon#ireg 17 cls_cnt 0 2006.145.08:49:37.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:49:37.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:49:37.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:49:37.55#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.08:49:37.59#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:49:37.59#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.08:49:37.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.08:49:37.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.08:49:37.60$vck44/vb=5,4 2006.145.08:49:37.60#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.08:49:37.60#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.08:49:37.60#ibcon#ireg 11 cls_cnt 2 2006.145.08:49:37.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:49:37.64#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:49:37.64#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:49:37.66#ibcon#[27=AT05-04\r\n] 2006.145.08:49:37.69#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:49:37.69#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.08:49:37.69#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.08:49:37.69#ibcon#ireg 7 cls_cnt 0 2006.145.08:49:37.69#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:49:37.81#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:49:37.81#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:49:37.83#ibcon#[27=USB\r\n] 2006.145.08:49:37.86#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:49:37.86#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.08:49:37.86#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.08:49:37.86#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.08:49:37.86$vck44/vblo=6,719.99 2006.145.08:49:37.87#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.08:49:37.87#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.08:49:37.87#ibcon#ireg 17 cls_cnt 0 2006.145.08:49:37.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:49:37.87#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:49:37.87#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:49:37.88#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.08:49:37.92#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:49:37.92#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:49:37.92#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.08:49:37.92#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.08:49:37.92$vck44/vb=6,4 2006.145.08:49:37.93#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.08:49:37.93#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.08:49:37.93#ibcon#ireg 11 cls_cnt 2 2006.145.08:49:37.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:49:37.97#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:49:37.97#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:49:37.99#ibcon#[27=AT06-04\r\n] 2006.145.08:49:38.02#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:49:38.02#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.08:49:38.02#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.08:49:38.02#ibcon#ireg 7 cls_cnt 0 2006.145.08:49:38.02#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:49:38.14#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:49:38.14#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:49:38.16#ibcon#[27=USB\r\n] 2006.145.08:49:38.19#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:49:38.19#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.08:49:38.19#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.08:49:38.19#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.08:49:38.19$vck44/vblo=7,734.99 2006.145.08:49:38.20#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.08:49:38.20#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.08:49:38.20#ibcon#ireg 17 cls_cnt 0 2006.145.08:49:38.20#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:49:38.20#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:49:38.20#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:49:38.21#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.08:49:38.25#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:49:38.25#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.08:49:38.25#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.08:49:38.25#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.08:49:38.25$vck44/vb=7,4 2006.145.08:49:38.26#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.08:49:38.26#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.08:49:38.26#ibcon#ireg 11 cls_cnt 2 2006.145.08:49:38.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:49:38.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:49:38.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:49:38.32#ibcon#[27=AT07-04\r\n] 2006.145.08:49:38.35#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:49:38.35#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.08:49:38.35#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.08:49:38.35#ibcon#ireg 7 cls_cnt 0 2006.145.08:49:38.35#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:49:38.47#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:49:38.47#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:49:38.49#ibcon#[27=USB\r\n] 2006.145.08:49:38.52#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:49:38.52#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.08:49:38.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.08:49:38.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.08:49:38.52$vck44/vblo=8,744.99 2006.145.08:49:38.53#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.08:49:38.53#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.08:49:38.53#ibcon#ireg 17 cls_cnt 0 2006.145.08:49:38.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:49:38.53#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:49:38.53#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:49:38.54#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.08:49:38.58#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:49:38.58#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.08:49:38.58#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.08:49:38.58#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.08:49:38.58$vck44/vb=8,4 2006.145.08:49:38.59#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.08:49:38.59#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.08:49:38.59#ibcon#ireg 11 cls_cnt 2 2006.145.08:49:38.59#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.08:49:38.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.08:49:38.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.08:49:38.65#ibcon#[27=AT08-04\r\n] 2006.145.08:49:38.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.08:49:38.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.08:49:38.68#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.08:49:38.68#ibcon#ireg 7 cls_cnt 0 2006.145.08:49:38.68#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.08:49:38.80#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.08:49:38.80#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.08:49:38.82#ibcon#[27=USB\r\n] 2006.145.08:49:38.85#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.08:49:38.85#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.08:49:38.85#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.08:49:38.85#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.08:49:38.86$vck44/vabw=wide 2006.145.08:49:38.86#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.08:49:38.86#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.08:49:38.86#ibcon#ireg 8 cls_cnt 0 2006.145.08:49:38.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.08:49:38.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.08:49:38.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.08:49:38.87#ibcon#[25=BW32\r\n] 2006.145.08:49:38.90#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.08:49:38.90#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.08:49:38.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.08:49:38.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.08:49:38.90$vck44/vbbw=wide 2006.145.08:49:38.91#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.08:49:38.91#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.08:49:38.91#ibcon#ireg 8 cls_cnt 0 2006.145.08:49:38.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.08:49:38.96#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.08:49:38.96#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.08:49:38.98#ibcon#[27=BW32\r\n] 2006.145.08:49:39.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.08:49:39.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.08:49:39.01#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.08:49:39.01#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.08:49:39.02$setupk4/ifdk4 2006.145.08:49:39.02$ifdk4/lo= 2006.145.08:49:39.02$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.08:49:39.02$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.08:49:39.02$ifdk4/patch= 2006.145.08:49:39.02$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.08:49:39.02$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.08:49:39.02$setupk4/!*+20s 2006.145.08:49:41.54#abcon#<5=/05 4.3 7.1 18.35 661017.8\r\n> 2006.145.08:49:41.56#abcon#{5=INTERFACE CLEAR} 2006.145.08:49:41.63#abcon#[5=S1D000X0/0*\r\n] 2006.145.08:49:51.71#abcon#<5=/05 4.3 7.1 18.35 661017.8\r\n> 2006.145.08:49:51.73#abcon#{5=INTERFACE CLEAR} 2006.145.08:49:51.79#abcon#[5=S1D000X0/0*\r\n] 2006.145.08:49:53.64$setupk4/"tpicd 2006.145.08:49:53.64$setupk4/echo=off 2006.145.08:49:53.64$setupk4/xlog=off 2006.145.08:49:53.65:!2006.145.08:51:29 2006.145.08:49:59.14#trakl#Source acquired 2006.145.08:50:01.15#flagr#flagr/antenna,acquired 2006.145.08:51:29.01:preob 2006.145.08:51:30.14/onsource/TRACKING 2006.145.08:51:30.15:!2006.145.08:51:39 2006.145.08:51:39.01:"tape 2006.145.08:51:39.01:"st=record 2006.145.08:51:39.01:data_valid=on 2006.145.08:51:39.02:midob 2006.145.08:51:40.14/onsource/TRACKING 2006.145.08:51:40.15/wx/18.34,1017.8,65 2006.145.08:51:40.22/cable/+6.5427E-03 2006.145.08:51:41.31/va/01,08,usb,yes,29,32 2006.145.08:51:41.31/va/02,07,usb,yes,32,32 2006.145.08:51:41.31/va/03,08,usb,yes,29,30 2006.145.08:51:41.31/va/04,07,usb,yes,33,34 2006.145.08:51:41.31/va/05,04,usb,yes,28,29 2006.145.08:51:41.31/va/06,04,usb,yes,32,32 2006.145.08:51:41.31/va/07,04,usb,yes,32,34 2006.145.08:51:41.31/va/08,04,usb,yes,27,33 2006.145.08:51:41.54/valo/01,524.99,yes,locked 2006.145.08:51:41.54/valo/02,534.99,yes,locked 2006.145.08:51:41.54/valo/03,564.99,yes,locked 2006.145.08:51:41.54/valo/04,624.99,yes,locked 2006.145.08:51:41.54/valo/05,734.99,yes,locked 2006.145.08:51:41.54/valo/06,814.99,yes,locked 2006.145.08:51:41.54/valo/07,864.99,yes,locked 2006.145.08:51:41.54/valo/08,884.99,yes,locked 2006.145.08:51:42.63/vb/01,03,usb,yes,36,34 2006.145.08:51:42.63/vb/02,04,usb,yes,32,32 2006.145.08:51:42.63/vb/03,04,usb,yes,29,32 2006.145.08:51:42.63/vb/04,04,usb,yes,33,32 2006.145.08:51:42.63/vb/05,04,usb,yes,26,28 2006.145.08:51:42.63/vb/06,04,usb,yes,30,26 2006.145.08:51:42.63/vb/07,04,usb,yes,30,30 2006.145.08:51:42.63/vb/08,04,usb,yes,28,31 2006.145.08:51:42.86/vblo/01,629.99,yes,locked 2006.145.08:51:42.86/vblo/02,634.99,yes,locked 2006.145.08:51:42.86/vblo/03,649.99,yes,locked 2006.145.08:51:42.86/vblo/04,679.99,yes,locked 2006.145.08:51:42.86/vblo/05,709.99,yes,locked 2006.145.08:51:42.86/vblo/06,719.99,yes,locked 2006.145.08:51:42.86/vblo/07,734.99,yes,locked 2006.145.08:51:42.86/vblo/08,744.99,yes,locked 2006.145.08:51:43.01/vabw/8 2006.145.08:51:43.16/vbbw/8 2006.145.08:51:43.31/xfe/off,on,15.0 2006.145.08:51:43.70/ifatt/23,28,28,28 2006.145.08:51:44.07/fmout-gps/S +5.3E-08 2006.145.08:51:44.12:!2006.145.08:53:29 2006.145.08:53:29.01:data_valid=off 2006.145.08:53:29.02:"et 2006.145.08:53:29.02:!+3s 2006.145.08:53:32.05:"tape 2006.145.08:53:32.09:postob 2006.145.08:53:32.29/cable/+6.5399E-03 2006.145.08:53:32.30/wx/18.32,1017.8,66 2006.145.08:53:32.38/fmout-gps/S +5.2E-08 2006.145.08:53:32.39:scan_name=145-0855,jd0605,80 2006.145.08:53:32.39:source=3c274,123049.42,122328.0,2000.0,cw 2006.145.08:53:34.14#flagr#flagr/antenna,new-source 2006.145.08:53:34.15:checkk5 2006.145.08:53:34.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.08:53:35.04/chk_autoobs//k5ts2/ autoobs is running! 2006.145.08:53:35.48/chk_autoobs//k5ts3/ autoobs is running! 2006.145.08:53:35.91/chk_autoobs//k5ts4/ autoobs is running! 2006.145.08:53:36.33/chk_obsdata//k5ts1/T1450851??a.dat file size is correct (nominal:440MB, actual:436MB). 2006.145.08:53:36.76/chk_obsdata//k5ts2/T1450851??b.dat file size is correct (nominal:440MB, actual:436MB). 2006.145.08:53:37.21/chk_obsdata//k5ts3/T1450851??c.dat file size is correct (nominal:440MB, actual:436MB). 2006.145.08:53:37.64/chk_obsdata//k5ts4/T1450851??d.dat file size is correct (nominal:440MB, actual:436MB). 2006.145.08:53:38.39/k5log//k5ts1_log_newline 2006.145.08:53:39.15/k5log//k5ts2_log_newline 2006.145.08:53:39.89/k5log//k5ts3_log_newline 2006.145.08:53:40.63/k5log//k5ts4_log_newline 2006.145.08:53:40.65/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.08:53:40.65:setupk4=1 2006.145.08:53:40.65$setupk4/echo=on 2006.145.08:53:40.65$setupk4/pcalon 2006.145.08:53:40.65$pcalon/"no phase cal control is implemented here 2006.145.08:53:40.65$setupk4/"tpicd=stop 2006.145.08:53:40.65$setupk4/"rec=synch_on 2006.145.08:53:40.65$setupk4/"rec_mode=128 2006.145.08:53:40.65$setupk4/!* 2006.145.08:53:40.65$setupk4/recpk4 2006.145.08:53:40.65$recpk4/recpatch= 2006.145.08:53:40.66$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.08:53:40.66$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.08:53:40.66$setupk4/vck44 2006.145.08:53:40.66$vck44/valo=1,524.99 2006.145.08:53:40.66#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.08:53:40.66#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.08:53:40.66#ibcon#ireg 17 cls_cnt 0 2006.145.08:53:40.66#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:53:40.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:53:40.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:53:40.70#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.08:53:40.74#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:53:40.74#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:53:40.74#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.08:53:40.74#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.08:53:40.74$vck44/va=1,8 2006.145.08:53:40.74#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.08:53:40.74#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.08:53:40.74#ibcon#ireg 11 cls_cnt 2 2006.145.08:53:40.74#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:53:40.74#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:53:40.74#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:53:40.76#ibcon#[25=AT01-08\r\n] 2006.145.08:53:40.79#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:53:40.79#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:53:40.79#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.08:53:40.79#ibcon#ireg 7 cls_cnt 0 2006.145.08:53:40.79#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:53:40.91#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:53:40.91#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:53:40.93#ibcon#[25=USB\r\n] 2006.145.08:53:40.96#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:53:40.96#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:53:40.96#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.08:53:40.96#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.08:53:40.96$vck44/valo=2,534.99 2006.145.08:53:40.96#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.08:53:40.96#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.08:53:40.96#ibcon#ireg 17 cls_cnt 0 2006.145.08:53:40.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:53:40.96#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:53:40.96#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:53:41.00#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.08:53:41.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:53:41.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:53:41.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.08:53:41.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.08:53:41.03$vck44/va=2,7 2006.145.08:53:41.03#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.08:53:41.03#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.08:53:41.03#ibcon#ireg 11 cls_cnt 2 2006.145.08:53:41.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:53:41.09#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:53:41.09#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:53:41.10#ibcon#[25=AT02-07\r\n] 2006.145.08:53:41.13#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:53:41.13#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:53:41.13#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.08:53:41.13#ibcon#ireg 7 cls_cnt 0 2006.145.08:53:41.13#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:53:41.25#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:53:41.25#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:53:41.27#ibcon#[25=USB\r\n] 2006.145.08:53:41.30#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:53:41.30#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:53:41.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.08:53:41.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.08:53:41.30$vck44/valo=3,564.99 2006.145.08:53:41.30#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.08:53:41.30#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.08:53:41.30#ibcon#ireg 17 cls_cnt 0 2006.145.08:53:41.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:53:41.30#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:53:41.30#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:53:41.32#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.08:53:41.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:53:41.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:53:41.36#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.08:53:41.36#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.08:53:41.36$vck44/va=3,8 2006.145.08:53:41.36#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.08:53:41.36#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.08:53:41.36#ibcon#ireg 11 cls_cnt 2 2006.145.08:53:41.36#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:53:41.42#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:53:41.42#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:53:41.44#ibcon#[25=AT03-08\r\n] 2006.145.08:53:41.47#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:53:41.47#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:53:41.47#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.08:53:41.47#ibcon#ireg 7 cls_cnt 0 2006.145.08:53:41.47#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:53:41.59#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:53:41.59#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:53:41.61#ibcon#[25=USB\r\n] 2006.145.08:53:41.64#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:53:41.64#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:53:41.64#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.08:53:41.64#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.08:53:41.64$vck44/valo=4,624.99 2006.145.08:53:41.64#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.08:53:41.64#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.08:53:41.64#ibcon#ireg 17 cls_cnt 0 2006.145.08:53:41.64#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:53:41.64#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:53:41.64#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:53:41.66#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.08:53:41.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:53:41.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:53:41.70#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.08:53:41.70#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.08:53:41.70$vck44/va=4,7 2006.145.08:53:41.70#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.08:53:41.70#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.08:53:41.70#ibcon#ireg 11 cls_cnt 2 2006.145.08:53:41.70#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:53:41.76#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:53:41.76#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:53:41.78#ibcon#[25=AT04-07\r\n] 2006.145.08:53:41.81#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:53:41.81#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:53:41.81#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.08:53:41.81#ibcon#ireg 7 cls_cnt 0 2006.145.08:53:41.81#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:53:41.93#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:53:41.93#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:53:41.95#ibcon#[25=USB\r\n] 2006.145.08:53:41.98#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:53:41.98#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:53:41.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.08:53:41.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.08:53:41.98$vck44/valo=5,734.99 2006.145.08:53:41.98#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.08:53:41.98#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.08:53:41.98#ibcon#ireg 17 cls_cnt 0 2006.145.08:53:41.98#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:53:41.98#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:53:41.98#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:53:42.00#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.08:53:42.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:53:42.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:53:42.04#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.08:53:42.04#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.08:53:42.04$vck44/va=5,4 2006.145.08:53:42.04#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.08:53:42.04#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.08:53:42.04#ibcon#ireg 11 cls_cnt 2 2006.145.08:53:42.04#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:53:42.10#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:53:42.10#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:53:42.12#ibcon#[25=AT05-04\r\n] 2006.145.08:53:42.15#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:53:42.15#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:53:42.15#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.08:53:42.15#ibcon#ireg 7 cls_cnt 0 2006.145.08:53:42.15#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:53:42.27#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:53:42.27#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:53:42.29#ibcon#[25=USB\r\n] 2006.145.08:53:42.32#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:53:42.32#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:53:42.32#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.08:53:42.32#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.08:53:42.32$vck44/valo=6,814.99 2006.145.08:53:42.32#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.08:53:42.32#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.08:53:42.32#ibcon#ireg 17 cls_cnt 0 2006.145.08:53:42.32#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:53:42.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:53:42.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:53:42.36#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.08:53:42.39#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:53:42.39#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:53:42.39#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.08:53:42.39#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.08:53:42.39$vck44/va=6,4 2006.145.08:53:42.39#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.08:53:42.39#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.08:53:42.39#ibcon#ireg 11 cls_cnt 2 2006.145.08:53:42.39#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:53:42.44#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:53:42.44#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:53:42.46#ibcon#[25=AT06-04\r\n] 2006.145.08:53:42.49#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:53:42.49#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:53:42.49#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.08:53:42.49#ibcon#ireg 7 cls_cnt 0 2006.145.08:53:42.49#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:53:42.61#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:53:42.61#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:53:42.63#ibcon#[25=USB\r\n] 2006.145.08:53:42.66#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:53:42.66#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:53:42.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.08:53:42.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.08:53:42.66$vck44/valo=7,864.99 2006.145.08:53:42.66#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.08:53:42.66#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.08:53:42.66#ibcon#ireg 17 cls_cnt 0 2006.145.08:53:42.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:53:42.66#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:53:42.66#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:53:42.68#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.08:53:42.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:53:42.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:53:42.72#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.08:53:42.72#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.08:53:42.72$vck44/va=7,4 2006.145.08:53:42.72#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.08:53:42.72#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.08:53:42.72#ibcon#ireg 11 cls_cnt 2 2006.145.08:53:42.72#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:53:42.78#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:53:42.78#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:53:42.80#ibcon#[25=AT07-04\r\n] 2006.145.08:53:42.83#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:53:42.83#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:53:42.83#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.08:53:42.83#ibcon#ireg 7 cls_cnt 0 2006.145.08:53:42.83#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:53:42.95#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:53:42.95#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:53:42.97#ibcon#[25=USB\r\n] 2006.145.08:53:43.00#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:53:43.00#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:53:43.00#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.08:53:43.00#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.08:53:43.00$vck44/valo=8,884.99 2006.145.08:53:43.00#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.08:53:43.00#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.08:53:43.00#ibcon#ireg 17 cls_cnt 0 2006.145.08:53:43.00#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:53:43.00#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:53:43.00#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:53:43.02#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.08:53:43.06#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:53:43.06#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.08:53:43.06#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.08:53:43.06#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.08:53:43.06$vck44/va=8,4 2006.145.08:53:43.06#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.08:53:43.06#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.08:53:43.06#ibcon#ireg 11 cls_cnt 2 2006.145.08:53:43.06#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:53:43.12#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:53:43.12#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:53:43.14#ibcon#[25=AT08-04\r\n] 2006.145.08:53:43.17#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:53:43.17#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.08:53:43.17#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.08:53:43.17#ibcon#ireg 7 cls_cnt 0 2006.145.08:53:43.17#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:53:43.29#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:53:43.29#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:53:43.31#ibcon#[25=USB\r\n] 2006.145.08:53:43.34#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:53:43.34#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.08:53:43.34#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.08:53:43.34#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.08:53:43.34$vck44/vblo=1,629.99 2006.145.08:53:43.34#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.08:53:43.34#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.08:53:43.34#ibcon#ireg 17 cls_cnt 0 2006.145.08:53:43.34#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:53:43.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:53:43.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:53:43.36#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.08:53:43.42#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:53:43.42#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:53:43.42#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.08:53:43.42#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.08:53:43.42$vck44/vb=1,3 2006.145.08:53:43.42#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.08:53:43.42#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.08:53:43.42#ibcon#ireg 11 cls_cnt 2 2006.145.08:53:43.42#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.08:53:43.42#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.08:53:43.42#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.08:53:43.44#ibcon#[27=AT01-03\r\n] 2006.145.08:53:43.47#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.08:53:43.47#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.08:53:43.47#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.08:53:43.47#ibcon#ireg 7 cls_cnt 0 2006.145.08:53:43.47#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.08:53:43.59#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.08:53:43.59#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.08:53:43.61#ibcon#[27=USB\r\n] 2006.145.08:53:43.64#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.08:53:43.64#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.08:53:43.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.08:53:43.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.08:53:43.64$vck44/vblo=2,634.99 2006.145.08:53:43.64#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.08:53:43.64#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.08:53:43.64#ibcon#ireg 17 cls_cnt 0 2006.145.08:53:43.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:53:43.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:53:43.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:53:43.68#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.08:53:43.71#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:53:43.71#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.08:53:43.71#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.08:53:43.71#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.08:53:43.71$vck44/vb=2,4 2006.145.08:53:43.71#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.08:53:43.71#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.08:53:43.71#ibcon#ireg 11 cls_cnt 2 2006.145.08:53:43.71#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:53:43.76#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:53:43.76#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:53:43.78#ibcon#[27=AT02-04\r\n] 2006.145.08:53:43.81#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:53:43.81#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.08:53:43.81#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.08:53:43.81#ibcon#ireg 7 cls_cnt 0 2006.145.08:53:43.81#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:53:43.93#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:53:43.93#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:53:43.95#ibcon#[27=USB\r\n] 2006.145.08:53:43.98#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:53:43.98#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.08:53:43.98#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.08:53:43.98#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.08:53:43.98$vck44/vblo=3,649.99 2006.145.08:53:43.98#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.08:53:43.98#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.08:53:43.98#ibcon#ireg 17 cls_cnt 0 2006.145.08:53:43.98#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:53:43.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:53:43.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:53:44.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.08:53:44.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:53:44.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.08:53:44.04#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.08:53:44.04#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.08:53:44.04$vck44/vb=3,4 2006.145.08:53:44.04#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.08:53:44.04#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.08:53:44.04#ibcon#ireg 11 cls_cnt 2 2006.145.08:53:44.04#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:53:44.10#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:53:44.10#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:53:44.12#ibcon#[27=AT03-04\r\n] 2006.145.08:53:44.15#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:53:44.15#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.08:53:44.15#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.08:53:44.15#ibcon#ireg 7 cls_cnt 0 2006.145.08:53:44.15#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:53:44.27#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:53:44.27#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:53:44.29#ibcon#[27=USB\r\n] 2006.145.08:53:44.32#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:53:44.32#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.08:53:44.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.08:53:44.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.08:53:44.32$vck44/vblo=4,679.99 2006.145.08:53:44.32#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.08:53:44.32#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.08:53:44.32#ibcon#ireg 17 cls_cnt 0 2006.145.08:53:44.32#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:53:44.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:53:44.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:53:44.34#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.08:53:44.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:53:44.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.08:53:44.38#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.08:53:44.38#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.08:53:44.38$vck44/vb=4,4 2006.145.08:53:44.38#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.08:53:44.38#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.08:53:44.38#ibcon#ireg 11 cls_cnt 2 2006.145.08:53:44.38#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:53:44.44#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:53:44.44#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:53:44.46#ibcon#[27=AT04-04\r\n] 2006.145.08:53:44.49#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:53:44.49#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.08:53:44.49#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.08:53:44.49#ibcon#ireg 7 cls_cnt 0 2006.145.08:53:44.49#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:53:44.61#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:53:44.61#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:53:44.63#ibcon#[27=USB\r\n] 2006.145.08:53:44.66#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:53:44.66#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.08:53:44.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.08:53:44.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.08:53:44.66$vck44/vblo=5,709.99 2006.145.08:53:44.66#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.08:53:44.66#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.08:53:44.66#ibcon#ireg 17 cls_cnt 0 2006.145.08:53:44.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:53:44.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:53:44.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:53:44.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.08:53:44.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:53:44.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.08:53:44.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.08:53:44.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.08:53:44.72$vck44/vb=5,4 2006.145.08:53:44.72#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.08:53:44.72#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.08:53:44.72#ibcon#ireg 11 cls_cnt 2 2006.145.08:53:44.72#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:53:44.78#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:53:44.78#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:53:44.80#ibcon#[27=AT05-04\r\n] 2006.145.08:53:44.83#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:53:44.83#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.08:53:44.83#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.08:53:44.83#ibcon#ireg 7 cls_cnt 0 2006.145.08:53:44.83#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:53:44.95#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:53:44.95#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:53:44.97#ibcon#[27=USB\r\n] 2006.145.08:53:45.00#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:53:45.00#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.08:53:45.00#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.08:53:45.00#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.08:53:45.00$vck44/vblo=6,719.99 2006.145.08:53:45.00#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.08:53:45.00#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.08:53:45.00#ibcon#ireg 17 cls_cnt 0 2006.145.08:53:45.00#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:53:45.00#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:53:45.00#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:53:45.02#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.08:53:45.06#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:53:45.06#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.08:53:45.06#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.08:53:45.06#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.08:53:45.06$vck44/vb=6,4 2006.145.08:53:45.06#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.08:53:45.06#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.08:53:45.06#ibcon#ireg 11 cls_cnt 2 2006.145.08:53:45.06#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:53:45.12#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:53:45.12#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:53:45.14#ibcon#[27=AT06-04\r\n] 2006.145.08:53:45.17#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:53:45.17#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.08:53:45.17#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.08:53:45.17#ibcon#ireg 7 cls_cnt 0 2006.145.08:53:45.17#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:53:45.29#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:53:45.29#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:53:45.31#ibcon#[27=USB\r\n] 2006.145.08:53:45.34#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:53:45.34#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.08:53:45.34#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.08:53:45.34#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.08:53:45.34$vck44/vblo=7,734.99 2006.145.08:53:45.34#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.08:53:45.34#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.08:53:45.34#ibcon#ireg 17 cls_cnt 0 2006.145.08:53:45.34#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:53:45.34#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:53:45.34#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:53:45.36#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.08:53:45.40#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:53:45.40#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.08:53:45.40#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.08:53:45.40#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.08:53:45.40$vck44/vb=7,4 2006.145.08:53:45.40#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.08:53:45.40#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.08:53:45.40#ibcon#ireg 11 cls_cnt 2 2006.145.08:53:45.40#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:53:45.46#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:53:45.46#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:53:45.48#ibcon#[27=AT07-04\r\n] 2006.145.08:53:45.51#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:53:45.51#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.08:53:45.51#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.08:53:45.51#ibcon#ireg 7 cls_cnt 0 2006.145.08:53:45.51#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:53:45.63#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:53:45.63#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:53:45.65#ibcon#[27=USB\r\n] 2006.145.08:53:45.68#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:53:45.68#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.08:53:45.68#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.08:53:45.68#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.08:53:45.68$vck44/vblo=8,744.99 2006.145.08:53:45.68#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.08:53:45.68#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.08:53:45.68#ibcon#ireg 17 cls_cnt 0 2006.145.08:53:45.68#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:53:45.68#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:53:45.68#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:53:45.70#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.08:53:45.74#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:53:45.74#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.08:53:45.74#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.08:53:45.74#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.08:53:45.74$vck44/vb=8,4 2006.145.08:53:45.74#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.08:53:45.74#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.08:53:45.74#ibcon#ireg 11 cls_cnt 2 2006.145.08:53:45.74#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:53:45.79#abcon#<5=/05 4.7 7.5 18.31 661017.9\r\n> 2006.145.08:53:45.80#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:53:45.80#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:53:45.81#abcon#{5=INTERFACE CLEAR} 2006.145.08:53:45.82#ibcon#[27=AT08-04\r\n] 2006.145.08:53:45.85#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:53:45.85#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.08:53:45.85#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.08:53:45.85#ibcon#ireg 7 cls_cnt 0 2006.145.08:53:45.85#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:53:45.87#abcon#[5=S1D000X0/0*\r\n] 2006.145.08:53:45.97#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:53:45.97#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:53:45.99#ibcon#[27=USB\r\n] 2006.145.08:53:46.02#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:53:46.02#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.08:53:46.02#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.08:53:46.02#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.08:53:46.02$vck44/vabw=wide 2006.145.08:53:46.02#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.08:53:46.02#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.08:53:46.02#ibcon#ireg 8 cls_cnt 0 2006.145.08:53:46.02#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:53:46.02#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:53:46.02#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:53:46.04#ibcon#[25=BW32\r\n] 2006.145.08:53:46.07#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:53:46.07#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.08:53:46.07#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.08:53:46.07#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.08:53:46.07$vck44/vbbw=wide 2006.145.08:53:46.07#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.08:53:46.07#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.08:53:46.07#ibcon#ireg 8 cls_cnt 0 2006.145.08:53:46.07#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:53:46.14#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:53:46.14#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:53:46.16#ibcon#[27=BW32\r\n] 2006.145.08:53:46.19#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:53:46.19#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:53:46.19#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.08:53:46.19#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.08:53:46.19$setupk4/ifdk4 2006.145.08:53:46.19$ifdk4/lo= 2006.145.08:53:46.19$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.08:53:46.19$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.08:53:46.19$ifdk4/patch= 2006.145.08:53:46.19$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.08:53:46.19$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.08:53:46.20$setupk4/!*+20s 2006.145.08:53:55.14#trakl#Source acquired 2006.145.08:53:55.96#abcon#<5=/05 4.7 7.6 18.31 661017.8\r\n> 2006.145.08:53:55.98#abcon#{5=INTERFACE CLEAR} 2006.145.08:53:56.04#abcon#[5=S1D000X0/0*\r\n] 2006.145.08:53:56.15#flagr#flagr/antenna,acquired 2006.145.08:54:00.67$setupk4/"tpicd 2006.145.08:54:00.67$setupk4/echo=off 2006.145.08:54:00.67$setupk4/xlog=off 2006.145.08:54:00.67:!2006.145.08:54:55 2006.145.08:54:55.00:preob 2006.145.08:54:55.14/onsource/TRACKING 2006.145.08:54:55.14:!2006.145.08:55:05 2006.145.08:55:05.00:"tape 2006.145.08:55:05.00:"st=record 2006.145.08:55:05.00:data_valid=on 2006.145.08:55:05.00:midob 2006.145.08:55:05.14/onsource/TRACKING 2006.145.08:55:05.14/wx/18.30,1017.9,67 2006.145.08:55:05.25/cable/+6.5408E-03 2006.145.08:55:06.34/va/01,08,usb,yes,31,33 2006.145.08:55:06.34/va/02,07,usb,yes,33,34 2006.145.08:55:06.34/va/03,08,usb,yes,30,31 2006.145.08:55:06.34/va/04,07,usb,yes,34,36 2006.145.08:55:06.34/va/05,04,usb,yes,30,30 2006.145.08:55:06.34/va/06,04,usb,yes,33,33 2006.145.08:55:06.34/va/07,04,usb,yes,33,35 2006.145.08:55:06.34/va/08,04,usb,yes,28,34 2006.145.08:55:06.57/valo/01,524.99,yes,locked 2006.145.08:55:06.57/valo/02,534.99,yes,locked 2006.145.08:55:06.57/valo/03,564.99,yes,locked 2006.145.08:55:06.57/valo/04,624.99,yes,locked 2006.145.08:55:06.57/valo/05,734.99,yes,locked 2006.145.08:55:06.57/valo/06,814.99,yes,locked 2006.145.08:55:06.57/valo/07,864.99,yes,locked 2006.145.08:55:06.57/valo/08,884.99,yes,locked 2006.145.08:55:07.66/vb/01,03,usb,yes,44,41 2006.145.08:55:07.66/vb/02,04,usb,yes,39,38 2006.145.08:55:07.66/vb/03,04,usb,yes,35,39 2006.145.08:55:07.66/vb/04,04,usb,yes,40,39 2006.145.08:55:07.66/vb/05,04,usb,yes,31,34 2006.145.08:55:07.66/vb/06,04,usb,yes,36,32 2006.145.08:55:07.66/vb/07,04,usb,yes,36,36 2006.145.08:55:07.66/vb/08,04,usb,yes,33,37 2006.145.08:55:07.89/vblo/01,629.99,yes,locked 2006.145.08:55:07.89/vblo/02,634.99,yes,locked 2006.145.08:55:07.89/vblo/03,649.99,yes,locked 2006.145.08:55:07.89/vblo/04,679.99,yes,locked 2006.145.08:55:07.89/vblo/05,709.99,yes,locked 2006.145.08:55:07.89/vblo/06,719.99,yes,locked 2006.145.08:55:07.89/vblo/07,734.99,yes,locked 2006.145.08:55:07.89/vblo/08,744.99,yes,locked 2006.145.08:55:08.04/vabw/8 2006.145.08:55:08.19/vbbw/8 2006.145.08:55:08.28/xfe/off,on,15.0 2006.145.08:55:08.65/ifatt/23,28,28,28 2006.145.08:55:09.07/fmout-gps/S +5.1E-08 2006.145.08:55:09.11:!2006.145.08:56:25 2006.145.08:56:25.01:data_valid=off 2006.145.08:56:25.02:"et 2006.145.08:56:25.02:!+3s 2006.145.08:56:28.05:"tape 2006.145.08:56:28.06:postob 2006.145.08:56:28.20/cable/+6.5436E-03 2006.145.08:56:28.21/wx/18.29,1017.8,67 2006.145.08:56:28.29/fmout-gps/S +5.1E-08 2006.145.08:56:28.29:scan_name=145-0903,jd0605,90 2006.145.08:56:28.29:source=1611+343,161341.06,341247.9,2000.0,cw 2006.145.08:56:29.13#flagr#flagr/antenna,new-source 2006.145.08:56:29.14:checkk5 2006.145.08:56:29.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.08:56:30.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.08:56:30.54/chk_autoobs//k5ts3/ autoobs is running! 2006.145.08:56:30.97/chk_autoobs//k5ts4/ autoobs is running! 2006.145.08:56:31.40/chk_obsdata//k5ts1/T1450855??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.08:56:31.84/chk_obsdata//k5ts2/T1450855??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.08:56:32.27/chk_obsdata//k5ts3/T1450855??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.08:56:32.70/chk_obsdata//k5ts4/T1450855??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.08:56:33.48/k5log//k5ts1_log_newline 2006.145.08:56:34.23/k5log//k5ts2_log_newline 2006.145.08:56:34.97/k5log//k5ts3_log_newline 2006.145.08:56:35.70/k5log//k5ts4_log_newline 2006.145.08:56:35.72/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.08:56:35.72:setupk4=1 2006.145.08:56:35.72$setupk4/echo=on 2006.145.08:56:35.72$setupk4/pcalon 2006.145.08:56:35.72$pcalon/"no phase cal control is implemented here 2006.145.08:56:35.72$setupk4/"tpicd=stop 2006.145.08:56:35.72$setupk4/"rec=synch_on 2006.145.08:56:35.72$setupk4/"rec_mode=128 2006.145.08:56:35.72$setupk4/!* 2006.145.08:56:35.72$setupk4/recpk4 2006.145.08:56:35.72$recpk4/recpatch= 2006.145.08:56:35.73$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.08:56:35.73$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.08:56:35.73$setupk4/vck44 2006.145.08:56:35.73$vck44/valo=1,524.99 2006.145.08:56:35.73#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.08:56:35.73#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.08:56:35.73#ibcon#ireg 17 cls_cnt 0 2006.145.08:56:35.73#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.08:56:35.73#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.08:56:35.73#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.08:56:35.77#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.08:56:35.81#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.08:56:35.81#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.08:56:35.81#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.08:56:35.81#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.08:56:35.81$vck44/va=1,8 2006.145.08:56:35.81#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.08:56:35.81#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.08:56:35.81#ibcon#ireg 11 cls_cnt 2 2006.145.08:56:35.81#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.08:56:35.81#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.08:56:35.81#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.08:56:35.83#ibcon#[25=AT01-08\r\n] 2006.145.08:56:35.86#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.08:56:35.86#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.08:56:35.86#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.08:56:35.86#ibcon#ireg 7 cls_cnt 0 2006.145.08:56:35.86#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.08:56:35.98#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.08:56:35.98#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.08:56:36.00#ibcon#[25=USB\r\n] 2006.145.08:56:36.03#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.08:56:36.03#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.08:56:36.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.08:56:36.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.08:56:36.03$vck44/valo=2,534.99 2006.145.08:56:36.03#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.08:56:36.03#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.08:56:36.03#ibcon#ireg 17 cls_cnt 0 2006.145.08:56:36.03#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.08:56:36.03#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.08:56:36.03#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.08:56:36.07#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.08:56:36.10#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.08:56:36.10#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.08:56:36.10#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.08:56:36.10#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.08:56:36.10$vck44/va=2,7 2006.145.08:56:36.10#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.08:56:36.10#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.08:56:36.10#ibcon#ireg 11 cls_cnt 2 2006.145.08:56:36.10#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.08:56:36.16#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.08:56:36.16#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.08:56:36.17#ibcon#[25=AT02-07\r\n] 2006.145.08:56:36.20#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.08:56:36.20#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.08:56:36.20#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.08:56:36.20#ibcon#ireg 7 cls_cnt 0 2006.145.08:56:36.20#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.08:56:36.32#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.08:56:36.32#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.08:56:36.34#ibcon#[25=USB\r\n] 2006.145.08:56:36.37#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.08:56:36.37#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.08:56:36.37#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.08:56:36.37#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.08:56:36.37$vck44/valo=3,564.99 2006.145.08:56:36.37#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.08:56:36.37#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.08:56:36.37#ibcon#ireg 17 cls_cnt 0 2006.145.08:56:36.37#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.08:56:36.37#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.08:56:36.37#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.08:56:36.39#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.08:56:36.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.08:56:36.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.08:56:36.43#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.08:56:36.43#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.08:56:36.43$vck44/va=3,8 2006.145.08:56:36.43#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.08:56:36.43#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.08:56:36.43#ibcon#ireg 11 cls_cnt 2 2006.145.08:56:36.43#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.08:56:36.49#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.08:56:36.49#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.08:56:36.51#ibcon#[25=AT03-08\r\n] 2006.145.08:56:36.54#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.08:56:36.54#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.08:56:36.54#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.08:56:36.54#ibcon#ireg 7 cls_cnt 0 2006.145.08:56:36.54#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.08:56:36.66#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.08:56:36.66#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.08:56:36.68#ibcon#[25=USB\r\n] 2006.145.08:56:36.71#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.08:56:36.71#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.08:56:36.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.08:56:36.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.08:56:36.71$vck44/valo=4,624.99 2006.145.08:56:36.71#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.08:56:36.71#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.08:56:36.71#ibcon#ireg 17 cls_cnt 0 2006.145.08:56:36.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.08:56:36.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.08:56:36.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.08:56:36.73#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.08:56:36.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.08:56:36.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.08:56:36.77#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.08:56:36.77#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.08:56:36.77$vck44/va=4,7 2006.145.08:56:36.77#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.08:56:36.77#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.08:56:36.77#ibcon#ireg 11 cls_cnt 2 2006.145.08:56:36.77#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.08:56:36.83#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.08:56:36.83#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.08:56:36.85#ibcon#[25=AT04-07\r\n] 2006.145.08:56:36.88#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.08:56:36.88#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.08:56:36.88#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.08:56:36.88#ibcon#ireg 7 cls_cnt 0 2006.145.08:56:36.88#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.08:56:37.00#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.08:56:37.00#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.08:56:37.02#ibcon#[25=USB\r\n] 2006.145.08:56:37.05#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.08:56:37.05#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.08:56:37.05#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.08:56:37.05#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.08:56:37.05$vck44/valo=5,734.99 2006.145.08:56:37.05#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.08:56:37.05#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.08:56:37.05#ibcon#ireg 17 cls_cnt 0 2006.145.08:56:37.05#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.08:56:37.05#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.08:56:37.05#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.08:56:37.07#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.08:56:37.11#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.08:56:37.11#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.08:56:37.11#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.08:56:37.11#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.08:56:37.11$vck44/va=5,4 2006.145.08:56:37.11#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.08:56:37.11#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.08:56:37.11#ibcon#ireg 11 cls_cnt 2 2006.145.08:56:37.11#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.08:56:37.17#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.08:56:37.17#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.08:56:37.20#ibcon#[25=AT05-04\r\n] 2006.145.08:56:37.22#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.08:56:37.22#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.08:56:37.22#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.08:56:37.22#ibcon#ireg 7 cls_cnt 0 2006.145.08:56:37.22#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.08:56:37.34#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.08:56:37.34#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.08:56:37.36#ibcon#[25=USB\r\n] 2006.145.08:56:37.39#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.08:56:37.39#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.08:56:37.39#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.08:56:37.39#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.08:56:37.39$vck44/valo=6,814.99 2006.145.08:56:37.39#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.08:56:37.39#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.08:56:37.39#ibcon#ireg 17 cls_cnt 0 2006.145.08:56:37.39#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.08:56:37.39#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.08:56:37.39#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.08:56:37.41#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.08:56:37.45#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.08:56:37.45#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.08:56:37.45#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.08:56:37.45#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.08:56:37.45$vck44/va=6,4 2006.145.08:56:37.45#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.08:56:37.45#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.08:56:37.45#ibcon#ireg 11 cls_cnt 2 2006.145.08:56:37.45#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.08:56:37.51#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.08:56:37.51#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.08:56:37.53#ibcon#[25=AT06-04\r\n] 2006.145.08:56:37.56#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.08:56:37.56#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.08:56:37.56#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.08:56:37.56#ibcon#ireg 7 cls_cnt 0 2006.145.08:56:37.56#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.08:56:37.68#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.08:56:37.68#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.08:56:37.70#ibcon#[25=USB\r\n] 2006.145.08:56:37.73#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.08:56:37.73#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.08:56:37.73#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.08:56:37.73#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.08:56:37.73$vck44/valo=7,864.99 2006.145.08:56:37.73#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.08:56:37.73#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.08:56:37.73#ibcon#ireg 17 cls_cnt 0 2006.145.08:56:37.73#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.08:56:37.73#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.08:56:37.73#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.08:56:37.75#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.08:56:37.79#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.08:56:37.79#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.08:56:37.79#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.08:56:37.79#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.08:56:37.79$vck44/va=7,4 2006.145.08:56:37.79#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.08:56:37.79#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.08:56:37.79#ibcon#ireg 11 cls_cnt 2 2006.145.08:56:37.79#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.08:56:37.85#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.08:56:37.85#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.08:56:37.87#ibcon#[25=AT07-04\r\n] 2006.145.08:56:37.90#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.08:56:37.90#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.08:56:37.90#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.08:56:37.90#ibcon#ireg 7 cls_cnt 0 2006.145.08:56:37.90#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.08:56:38.02#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.08:56:38.02#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.08:56:38.04#ibcon#[25=USB\r\n] 2006.145.08:56:38.07#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.08:56:38.07#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.08:56:38.07#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.08:56:38.07#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.08:56:38.07$vck44/valo=8,884.99 2006.145.08:56:38.07#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.08:56:38.07#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.08:56:38.07#ibcon#ireg 17 cls_cnt 0 2006.145.08:56:38.07#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.08:56:38.07#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.08:56:38.07#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.08:56:38.09#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.08:56:38.13#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.08:56:38.13#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.08:56:38.13#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.08:56:38.13#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.08:56:38.13$vck44/va=8,4 2006.145.08:56:38.13#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.08:56:38.13#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.08:56:38.13#ibcon#ireg 11 cls_cnt 2 2006.145.08:56:38.13#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.08:56:38.19#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.08:56:38.19#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.08:56:38.21#ibcon#[25=AT08-04\r\n] 2006.145.08:56:38.24#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.08:56:38.24#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.08:56:38.24#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.08:56:38.24#ibcon#ireg 7 cls_cnt 0 2006.145.08:56:38.24#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.08:56:38.36#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.08:56:38.36#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.08:56:38.40#ibcon#[25=USB\r\n] 2006.145.08:56:38.43#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.08:56:38.43#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.08:56:38.43#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.08:56:38.43#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.08:56:38.43$vck44/vblo=1,629.99 2006.145.08:56:38.43#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.08:56:38.43#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.08:56:38.43#ibcon#ireg 17 cls_cnt 0 2006.145.08:56:38.43#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.08:56:38.43#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.08:56:38.43#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.08:56:38.45#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.08:56:38.49#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.08:56:38.49#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.08:56:38.49#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.08:56:38.49#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.08:56:38.49$vck44/vb=1,3 2006.145.08:56:38.49#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.08:56:38.49#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.08:56:38.49#ibcon#ireg 11 cls_cnt 2 2006.145.08:56:38.49#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.08:56:38.49#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.08:56:38.49#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.08:56:38.51#ibcon#[27=AT01-03\r\n] 2006.145.08:56:38.54#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.08:56:38.54#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.08:56:38.54#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.08:56:38.54#ibcon#ireg 7 cls_cnt 0 2006.145.08:56:38.54#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.08:56:38.66#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.08:56:38.66#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.08:56:38.68#ibcon#[27=USB\r\n] 2006.145.08:56:38.68#abcon#<5=/05 4.8 7.6 18.28 671017.9\r\n> 2006.145.08:56:38.70#abcon#{5=INTERFACE CLEAR} 2006.145.08:56:38.71#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.08:56:38.71#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.08:56:38.71#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.08:56:38.71#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.08:56:38.71$vck44/vblo=2,634.99 2006.145.08:56:38.71#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.08:56:38.71#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.08:56:38.71#ibcon#ireg 17 cls_cnt 0 2006.145.08:56:38.71#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:56:38.71#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:56:38.71#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:56:38.73#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.08:56:38.76#abcon#[5=S1D000X0/0*\r\n] 2006.145.08:56:38.77#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:56:38.77#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.08:56:38.77#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.08:56:38.77#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.08:56:38.77$vck44/vb=2,4 2006.145.08:56:38.77#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.08:56:38.77#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.08:56:38.77#ibcon#ireg 11 cls_cnt 2 2006.145.08:56:38.77#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.08:56:38.83#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.08:56:38.83#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.08:56:38.85#ibcon#[27=AT02-04\r\n] 2006.145.08:56:38.88#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.08:56:38.88#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.08:56:38.88#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.08:56:38.88#ibcon#ireg 7 cls_cnt 0 2006.145.08:56:38.88#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.08:56:39.00#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.08:56:39.00#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.08:56:39.02#ibcon#[27=USB\r\n] 2006.145.08:56:39.05#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.08:56:39.05#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.08:56:39.05#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.08:56:39.05#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.08:56:39.05$vck44/vblo=3,649.99 2006.145.08:56:39.05#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.08:56:39.05#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.08:56:39.05#ibcon#ireg 17 cls_cnt 0 2006.145.08:56:39.05#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.08:56:39.05#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.08:56:39.05#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.08:56:39.07#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.08:56:39.11#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.08:56:39.11#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.08:56:39.11#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.08:56:39.11#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.08:56:39.11$vck44/vb=3,4 2006.145.08:56:39.11#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.08:56:39.11#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.08:56:39.11#ibcon#ireg 11 cls_cnt 2 2006.145.08:56:39.11#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.08:56:39.17#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.08:56:39.17#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.08:56:39.19#ibcon#[27=AT03-04\r\n] 2006.145.08:56:39.22#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.08:56:39.22#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.08:56:39.22#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.08:56:39.22#ibcon#ireg 7 cls_cnt 0 2006.145.08:56:39.22#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.08:56:39.34#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.08:56:39.34#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.08:56:39.36#ibcon#[27=USB\r\n] 2006.145.08:56:39.39#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.08:56:39.39#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.08:56:39.39#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.08:56:39.39#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.08:56:39.39$vck44/vblo=4,679.99 2006.145.08:56:39.39#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.08:56:39.39#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.08:56:39.39#ibcon#ireg 17 cls_cnt 0 2006.145.08:56:39.39#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.08:56:39.39#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.08:56:39.39#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.08:56:39.41#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.08:56:39.45#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.08:56:39.45#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.08:56:39.45#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.08:56:39.45#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.08:56:39.45$vck44/vb=4,4 2006.145.08:56:39.45#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.08:56:39.45#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.08:56:39.45#ibcon#ireg 11 cls_cnt 2 2006.145.08:56:39.45#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.08:56:39.51#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.08:56:39.51#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.08:56:39.53#ibcon#[27=AT04-04\r\n] 2006.145.08:56:39.56#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.08:56:39.56#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.08:56:39.56#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.08:56:39.56#ibcon#ireg 7 cls_cnt 0 2006.145.08:56:39.56#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.08:56:39.68#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.08:56:39.68#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.08:56:39.70#ibcon#[27=USB\r\n] 2006.145.08:56:39.73#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.08:56:39.73#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.08:56:39.73#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.08:56:39.73#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.08:56:39.73$vck44/vblo=5,709.99 2006.145.08:56:39.73#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.08:56:39.73#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.08:56:39.73#ibcon#ireg 17 cls_cnt 0 2006.145.08:56:39.73#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.08:56:39.73#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.08:56:39.73#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.08:56:39.75#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.08:56:39.79#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.08:56:39.79#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.08:56:39.79#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.08:56:39.79#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.08:56:39.79$vck44/vb=5,4 2006.145.08:56:39.79#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.08:56:39.79#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.08:56:39.79#ibcon#ireg 11 cls_cnt 2 2006.145.08:56:39.79#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.08:56:39.85#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.08:56:39.85#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.08:56:39.87#ibcon#[27=AT05-04\r\n] 2006.145.08:56:39.90#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.08:56:39.90#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.08:56:39.90#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.08:56:39.90#ibcon#ireg 7 cls_cnt 0 2006.145.08:56:39.90#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.08:56:40.02#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.08:56:40.02#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.08:56:40.04#ibcon#[27=USB\r\n] 2006.145.08:56:40.07#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.08:56:40.07#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.08:56:40.07#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.08:56:40.07#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.08:56:40.07$vck44/vblo=6,719.99 2006.145.08:56:40.07#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.08:56:40.07#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.08:56:40.07#ibcon#ireg 17 cls_cnt 0 2006.145.08:56:40.07#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.08:56:40.07#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.08:56:40.07#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.08:56:40.09#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.08:56:40.13#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.08:56:40.13#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.08:56:40.13#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.08:56:40.13#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.08:56:40.13$vck44/vb=6,4 2006.145.08:56:40.13#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.08:56:40.13#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.08:56:40.13#ibcon#ireg 11 cls_cnt 2 2006.145.08:56:40.13#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.08:56:40.19#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.08:56:40.19#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.08:56:40.21#ibcon#[27=AT06-04\r\n] 2006.145.08:56:40.24#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.08:56:40.24#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.08:56:40.24#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.08:56:40.24#ibcon#ireg 7 cls_cnt 0 2006.145.08:56:40.24#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.08:56:40.36#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.08:56:40.36#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.08:56:40.38#ibcon#[27=USB\r\n] 2006.145.08:56:40.41#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.08:56:40.41#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.08:56:40.41#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.08:56:40.41#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.08:56:40.41$vck44/vblo=7,734.99 2006.145.08:56:40.41#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.08:56:40.41#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.08:56:40.41#ibcon#ireg 17 cls_cnt 0 2006.145.08:56:40.41#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.08:56:40.41#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.08:56:40.41#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.08:56:40.43#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.08:56:40.47#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.08:56:40.47#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.08:56:40.47#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.08:56:40.47#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.08:56:40.47$vck44/vb=7,4 2006.145.08:56:40.47#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.08:56:40.47#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.08:56:40.47#ibcon#ireg 11 cls_cnt 2 2006.145.08:56:40.47#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.08:56:40.53#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.08:56:40.53#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.08:56:40.55#ibcon#[27=AT07-04\r\n] 2006.145.08:56:40.58#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.08:56:40.58#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.08:56:40.58#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.08:56:40.58#ibcon#ireg 7 cls_cnt 0 2006.145.08:56:40.58#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.08:56:40.70#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.08:56:40.70#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.08:56:40.72#ibcon#[27=USB\r\n] 2006.145.08:56:40.75#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.08:56:40.75#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.08:56:40.75#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.08:56:40.75#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.08:56:40.75$vck44/vblo=8,744.99 2006.145.08:56:40.75#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.08:56:40.75#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.08:56:40.75#ibcon#ireg 17 cls_cnt 0 2006.145.08:56:40.75#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.08:56:40.75#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.08:56:40.75#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.08:56:40.77#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.08:56:40.81#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.08:56:40.81#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.08:56:40.81#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.08:56:40.81#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.08:56:40.81$vck44/vb=8,4 2006.145.08:56:40.81#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.08:56:40.81#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.08:56:40.81#ibcon#ireg 11 cls_cnt 2 2006.145.08:56:40.81#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.08:56:40.87#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.08:56:40.87#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.08:56:40.89#ibcon#[27=AT08-04\r\n] 2006.145.08:56:40.92#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.08:56:40.92#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.08:56:40.92#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.08:56:40.92#ibcon#ireg 7 cls_cnt 0 2006.145.08:56:40.92#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.08:56:41.04#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.08:56:41.04#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.08:56:41.06#ibcon#[27=USB\r\n] 2006.145.08:56:41.09#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.08:56:41.09#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.08:56:41.09#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.08:56:41.09#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.08:56:41.09$vck44/vabw=wide 2006.145.08:56:41.09#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.08:56:41.09#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.08:56:41.09#ibcon#ireg 8 cls_cnt 0 2006.145.08:56:41.09#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.08:56:41.09#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.08:56:41.09#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.08:56:41.11#ibcon#[25=BW32\r\n] 2006.145.08:56:41.14#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.08:56:41.14#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.08:56:41.14#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.08:56:41.14#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.08:56:41.14$vck44/vbbw=wide 2006.145.08:56:41.14#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.08:56:41.14#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.08:56:41.14#ibcon#ireg 8 cls_cnt 0 2006.145.08:56:41.14#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:56:41.21#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:56:41.21#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:56:41.23#ibcon#[27=BW32\r\n] 2006.145.08:56:41.26#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:56:41.26#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.08:56:41.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.08:56:41.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.08:56:41.26$setupk4/ifdk4 2006.145.08:56:41.26$ifdk4/lo= 2006.145.08:56:41.26$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.08:56:41.26$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.08:56:41.26$ifdk4/patch= 2006.145.08:56:41.26$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.08:56:41.26$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.08:56:41.26$setupk4/!*+20s 2006.145.08:56:48.85#abcon#<5=/05 4.8 7.6 18.28 661017.9\r\n> 2006.145.08:56:48.87#abcon#{5=INTERFACE CLEAR} 2006.145.08:56:48.95#abcon#[5=S1D000X0/0*\r\n] 2006.145.08:56:55.73$setupk4/"tpicd 2006.145.08:56:55.73$setupk4/echo=off 2006.145.08:56:55.73$setupk4/xlog=off 2006.145.08:56:55.73:!2006.145.09:03:31 2006.145.08:56:57.13#trakl#Source acquired 2006.145.08:56:57.13#flagr#flagr/antenna,acquired 2006.145.09:00:31.14#trakl#Off source 2006.145.09:00:31.14?ERROR st -7 Antenna off-source! 2006.145.09:00:31.14#trakl#az 63.243 el 22.570 azerr*cos(el) 0.0222 elerr 0.0016 2006.145.09:00:33.14#flagr#flagr/antenna,off-source 2006.145.09:00:37.14#trakl#Source re-acquired 2006.145.09:00:39.14#flagr#flagr/antenna,re-acquired 2006.145.09:01:37.14#trakl#Off source 2006.145.09:01:37.14?ERROR st -7 Antenna off-source! 2006.145.09:01:37.14#trakl#az 63.364 el 22.769 azerr*cos(el) 0.0189 elerr -0.0001 2006.145.09:01:39.14#flagr#flagr/antenna,off-source 2006.145.09:01:43.14#trakl#Source re-acquired 2006.145.09:01:45.14#flagr#flagr/antenna,re-acquired 2006.145.09:03:31.00:preob 2006.145.09:03:31.14/onsource/TRACKING 2006.145.09:03:31.14:!2006.145.09:03:41 2006.145.09:03:41.00:"tape 2006.145.09:03:41.00:"st=record 2006.145.09:03:41.00:data_valid=on 2006.145.09:03:41.00:midob 2006.145.09:03:42.14/onsource/TRACKING 2006.145.09:03:42.14/wx/18.21,1018.0,67 2006.145.09:03:42.29/cable/+6.5411E-03 2006.145.09:03:43.38/va/01,08,usb,yes,30,32 2006.145.09:03:43.38/va/02,07,usb,yes,32,32 2006.145.09:03:43.38/va/03,08,usb,yes,29,30 2006.145.09:03:43.38/va/04,07,usb,yes,33,35 2006.145.09:03:43.38/va/05,04,usb,yes,29,29 2006.145.09:03:43.38/va/06,04,usb,yes,32,32 2006.145.09:03:43.38/va/07,04,usb,yes,32,34 2006.145.09:03:43.38/va/08,04,usb,yes,28,33 2006.145.09:03:43.61/valo/01,524.99,yes,locked 2006.145.09:03:43.61/valo/02,534.99,yes,locked 2006.145.09:03:43.61/valo/03,564.99,yes,locked 2006.145.09:03:43.61/valo/04,624.99,yes,locked 2006.145.09:03:43.61/valo/05,734.99,yes,locked 2006.145.09:03:43.61/valo/06,814.99,yes,locked 2006.145.09:03:43.61/valo/07,864.99,yes,locked 2006.145.09:03:43.61/valo/08,884.99,yes,locked 2006.145.09:03:44.70/vb/01,03,usb,yes,37,34 2006.145.09:03:44.70/vb/02,04,usb,yes,32,32 2006.145.09:03:44.70/vb/03,04,usb,yes,29,32 2006.145.09:03:44.70/vb/04,04,usb,yes,33,32 2006.145.09:03:44.70/vb/05,04,usb,yes,26,28 2006.145.09:03:44.70/vb/06,04,usb,yes,30,27 2006.145.09:03:44.70/vb/07,04,usb,yes,30,30 2006.145.09:03:44.70/vb/08,04,usb,yes,28,31 2006.145.09:03:44.94/vblo/01,629.99,yes,locked 2006.145.09:03:44.94/vblo/02,634.99,yes,locked 2006.145.09:03:44.94/vblo/03,649.99,yes,locked 2006.145.09:03:44.94/vblo/04,679.99,yes,locked 2006.145.09:03:44.94/vblo/05,709.99,yes,locked 2006.145.09:03:44.94/vblo/06,719.99,yes,locked 2006.145.09:03:44.94/vblo/07,734.99,yes,locked 2006.145.09:03:44.94/vblo/08,744.99,yes,locked 2006.145.09:03:45.09/vabw/8 2006.145.09:03:45.24/vbbw/8 2006.145.09:03:45.40/xfe/off,on,15.2 2006.145.09:03:45.77/ifatt/23,28,28,28 2006.145.09:03:46.07/fmout-gps/S +4.9E-08 2006.145.09:03:46.15:!2006.145.09:05:11 2006.145.09:04:48.13#trakl#Off source 2006.145.09:04:48.13?ERROR st -7 Antenna off-source! 2006.145.09:04:48.13#trakl#az 63.711 el 23.345 azerr*cos(el) 0.0173 elerr -0.0033 2006.145.09:04:49.13#flagr#flagr/antenna,off-source 2006.145.09:04:54.13#trakl#Source re-acquired 2006.145.09:04:55.13#flagr#flagr/antenna,re-acquired 2006.145.09:05:11.01:data_valid=off 2006.145.09:05:11.02:"et 2006.145.09:05:11.02:!+3s 2006.145.09:05:14.03:"tape 2006.145.09:05:14.03:postob 2006.145.09:05:14.12/cable/+6.5410E-03 2006.145.09:05:14.13/wx/18.20,1018.1,66 2006.145.09:05:14.19/fmout-gps/S +4.9E-08 2006.145.09:05:14.19:scan_name=145-0915,jd0605,410 2006.145.09:05:14.19:source=1418+546,141946.60,542314.8,2000.0,cw 2006.145.09:05:15.13#flagr#flagr/antenna,new-source 2006.145.09:05:15.14:checkk5 2006.145.09:05:15.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.09:05:16.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.09:05:16.45/chk_autoobs//k5ts3/ autoobs is running! 2006.145.09:05:16.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.09:05:17.34/chk_obsdata//k5ts1/T1450903??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.09:05:17.78/chk_obsdata//k5ts2/T1450903??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.09:05:18.23/chk_obsdata//k5ts3/T1450903??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.09:05:18.67/chk_obsdata//k5ts4/T1450903??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.09:05:19.44/k5log//k5ts1_log_newline 2006.145.09:05:20.18/k5log//k5ts2_log_newline 2006.145.09:05:20.92/k5log//k5ts3_log_newline 2006.145.09:05:21.67/k5log//k5ts4_log_newline 2006.145.09:05:21.69/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.09:05:21.69:setupk4=1 2006.145.09:05:21.69$setupk4/echo=on 2006.145.09:05:21.69$setupk4/pcalon 2006.145.09:05:21.69$pcalon/"no phase cal control is implemented here 2006.145.09:05:21.69$setupk4/"tpicd=stop 2006.145.09:05:21.69$setupk4/"rec=synch_on 2006.145.09:05:21.69$setupk4/"rec_mode=128 2006.145.09:05:21.69$setupk4/!* 2006.145.09:05:21.69$setupk4/recpk4 2006.145.09:05:21.69$recpk4/recpatch= 2006.145.09:05:21.69$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.09:05:21.69$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.09:05:21.69$setupk4/vck44 2006.145.09:05:21.69$vck44/valo=1,524.99 2006.145.09:05:21.70#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.09:05:21.70#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.09:05:21.70#ibcon#ireg 17 cls_cnt 0 2006.145.09:05:21.70#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.09:05:21.70#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.09:05:21.70#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.09:05:21.74#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.09:05:21.78#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.09:05:21.78#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.09:05:21.78#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.09:05:21.78#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.09:05:21.78$vck44/va=1,8 2006.145.09:05:21.78#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.09:05:21.78#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.09:05:21.78#ibcon#ireg 11 cls_cnt 2 2006.145.09:05:21.78#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.09:05:21.78#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.09:05:21.78#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.09:05:21.80#ibcon#[25=AT01-08\r\n] 2006.145.09:05:21.83#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.09:05:21.83#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.09:05:21.83#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.09:05:21.83#ibcon#ireg 7 cls_cnt 0 2006.145.09:05:21.83#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.09:05:21.96#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.09:05:21.96#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.09:05:21.97#ibcon#[25=USB\r\n] 2006.145.09:05:22.00#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.09:05:22.00#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.09:05:22.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.09:05:22.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.09:05:22.00$vck44/valo=2,534.99 2006.145.09:05:22.00#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.09:05:22.00#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.09:05:22.00#ibcon#ireg 17 cls_cnt 0 2006.145.09:05:22.00#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.09:05:22.00#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.09:05:22.00#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.09:05:22.03#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.09:05:22.07#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.09:05:22.07#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.09:05:22.07#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.09:05:22.07#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.09:05:22.07$vck44/va=2,7 2006.145.09:05:22.07#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.09:05:22.07#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.09:05:22.07#ibcon#ireg 11 cls_cnt 2 2006.145.09:05:22.07#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.09:05:22.12#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.09:05:22.12#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.09:05:22.14#ibcon#[25=AT02-07\r\n] 2006.145.09:05:22.17#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.09:05:22.17#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.09:05:22.17#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.09:05:22.17#ibcon#ireg 7 cls_cnt 0 2006.145.09:05:22.17#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.09:05:22.29#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.09:05:22.29#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.09:05:22.31#ibcon#[25=USB\r\n] 2006.145.09:05:22.34#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.09:05:22.34#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.09:05:22.34#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.09:05:22.34#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.09:05:22.34$vck44/valo=3,564.99 2006.145.09:05:22.34#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.09:05:22.34#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.09:05:22.34#ibcon#ireg 17 cls_cnt 0 2006.145.09:05:22.34#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.09:05:22.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.09:05:22.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.09:05:22.36#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.09:05:22.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.09:05:22.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.09:05:22.40#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.09:05:22.40#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.09:05:22.40$vck44/va=3,8 2006.145.09:05:22.40#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.09:05:22.40#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.09:05:22.40#ibcon#ireg 11 cls_cnt 2 2006.145.09:05:22.40#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.09:05:22.46#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.09:05:22.46#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.09:05:22.48#ibcon#[25=AT03-08\r\n] 2006.145.09:05:22.51#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.09:05:22.51#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.09:05:22.51#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.09:05:22.51#ibcon#ireg 7 cls_cnt 0 2006.145.09:05:22.51#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.09:05:22.63#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.09:05:22.63#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.09:05:22.65#ibcon#[25=USB\r\n] 2006.145.09:05:22.68#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.09:05:22.68#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.09:05:22.68#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.09:05:22.68#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.09:05:22.68$vck44/valo=4,624.99 2006.145.09:05:22.68#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.09:05:22.68#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.09:05:22.68#ibcon#ireg 17 cls_cnt 0 2006.145.09:05:22.68#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.09:05:22.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.09:05:22.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.09:05:22.70#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.09:05:22.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.09:05:22.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.09:05:22.74#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.09:05:22.74#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.09:05:22.74$vck44/va=4,7 2006.145.09:05:22.74#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.09:05:22.74#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.09:05:22.74#ibcon#ireg 11 cls_cnt 2 2006.145.09:05:22.74#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.09:05:22.80#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.09:05:22.80#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.09:05:22.82#ibcon#[25=AT04-07\r\n] 2006.145.09:05:22.85#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.09:05:22.85#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.09:05:22.85#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.09:05:22.85#ibcon#ireg 7 cls_cnt 0 2006.145.09:05:22.85#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.09:05:22.97#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.09:05:22.97#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.09:05:22.99#ibcon#[25=USB\r\n] 2006.145.09:05:23.02#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.09:05:23.02#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.09:05:23.02#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.09:05:23.02#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.09:05:23.02$vck44/valo=5,734.99 2006.145.09:05:23.02#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.09:05:23.02#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.09:05:23.02#ibcon#ireg 17 cls_cnt 0 2006.145.09:05:23.02#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.09:05:23.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.09:05:23.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.09:05:23.04#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.09:05:23.08#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.09:05:23.08#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.09:05:23.08#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.09:05:23.08#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.09:05:23.08$vck44/va=5,4 2006.145.09:05:23.08#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.09:05:23.08#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.09:05:23.08#ibcon#ireg 11 cls_cnt 2 2006.145.09:05:23.08#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.09:05:23.14#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.09:05:23.14#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.09:05:23.16#ibcon#[25=AT05-04\r\n] 2006.145.09:05:23.19#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.09:05:23.19#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.09:05:23.19#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.09:05:23.19#ibcon#ireg 7 cls_cnt 0 2006.145.09:05:23.19#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.09:05:23.31#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.09:05:23.31#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.09:05:23.33#ibcon#[25=USB\r\n] 2006.145.09:05:23.36#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.09:05:23.36#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.09:05:23.36#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.09:05:23.36#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.09:05:23.36$vck44/valo=6,814.99 2006.145.09:05:23.36#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.09:05:23.36#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.09:05:23.36#ibcon#ireg 17 cls_cnt 0 2006.145.09:05:23.36#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.09:05:23.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.09:05:23.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.09:05:23.38#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.09:05:23.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.09:05:23.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.09:05:23.42#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.09:05:23.42#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.09:05:23.42$vck44/va=6,4 2006.145.09:05:23.42#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.09:05:23.42#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.09:05:23.42#ibcon#ireg 11 cls_cnt 2 2006.145.09:05:23.42#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.09:05:23.48#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.09:05:23.48#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.09:05:23.50#ibcon#[25=AT06-04\r\n] 2006.145.09:05:23.53#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.09:05:23.53#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.09:05:23.53#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.09:05:23.53#ibcon#ireg 7 cls_cnt 0 2006.145.09:05:23.53#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.09:05:23.65#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.09:05:23.65#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.09:05:23.67#ibcon#[25=USB\r\n] 2006.145.09:05:23.70#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.09:05:23.70#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.09:05:23.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.09:05:23.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.09:05:23.70$vck44/valo=7,864.99 2006.145.09:05:23.70#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.09:05:23.70#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.09:05:23.70#ibcon#ireg 17 cls_cnt 0 2006.145.09:05:23.70#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.09:05:23.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.09:05:23.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.09:05:23.72#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.09:05:23.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.09:05:23.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.09:05:23.76#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.09:05:23.76#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.09:05:23.76$vck44/va=7,4 2006.145.09:05:23.76#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.09:05:23.76#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.09:05:23.76#ibcon#ireg 11 cls_cnt 2 2006.145.09:05:23.76#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.09:05:23.82#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.09:05:23.82#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.09:05:23.84#ibcon#[25=AT07-04\r\n] 2006.145.09:05:23.87#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.09:05:23.87#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.09:05:23.87#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.09:05:23.87#ibcon#ireg 7 cls_cnt 0 2006.145.09:05:23.87#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.09:05:23.99#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.09:05:23.99#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.09:05:24.01#ibcon#[25=USB\r\n] 2006.145.09:05:24.04#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.09:05:24.04#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.09:05:24.04#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.09:05:24.04#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.09:05:24.04$vck44/valo=8,884.99 2006.145.09:05:24.04#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.09:05:24.04#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.09:05:24.04#ibcon#ireg 17 cls_cnt 0 2006.145.09:05:24.04#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.09:05:24.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.09:05:24.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.09:05:24.06#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.09:05:24.10#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.09:05:24.10#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.09:05:24.10#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.09:05:24.10#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.09:05:24.10$vck44/va=8,4 2006.145.09:05:24.10#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.09:05:24.10#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.09:05:24.10#ibcon#ireg 11 cls_cnt 2 2006.145.09:05:24.10#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.09:05:24.16#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.09:05:24.16#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.09:05:24.18#ibcon#[25=AT08-04\r\n] 2006.145.09:05:24.21#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.09:05:24.21#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.09:05:24.21#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.09:05:24.21#ibcon#ireg 7 cls_cnt 0 2006.145.09:05:24.21#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.09:05:24.33#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.09:05:24.33#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.09:05:24.35#ibcon#[25=USB\r\n] 2006.145.09:05:24.38#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.09:05:24.38#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.09:05:24.38#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.09:05:24.38#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.09:05:24.38$vck44/vblo=1,629.99 2006.145.09:05:24.38#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.09:05:24.38#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.09:05:24.38#ibcon#ireg 17 cls_cnt 0 2006.145.09:05:24.38#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.09:05:24.38#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.09:05:24.38#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.09:05:24.41#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.09:05:24.45#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.09:05:24.45#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.09:05:24.45#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.09:05:24.45#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.09:05:24.45$vck44/vb=1,3 2006.145.09:05:24.45#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.09:05:24.45#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.09:05:24.45#ibcon#ireg 11 cls_cnt 2 2006.145.09:05:24.45#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.09:05:24.45#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.09:05:24.45#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.09:05:24.47#ibcon#[27=AT01-03\r\n] 2006.145.09:05:24.50#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.09:05:24.50#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.09:05:24.50#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.09:05:24.50#ibcon#ireg 7 cls_cnt 0 2006.145.09:05:24.50#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.09:05:24.62#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.09:05:24.62#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.09:05:24.64#ibcon#[27=USB\r\n] 2006.145.09:05:24.67#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.09:05:24.67#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.09:05:24.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.09:05:24.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.09:05:24.67$vck44/vblo=2,634.99 2006.145.09:05:24.67#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.09:05:24.67#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.09:05:24.67#ibcon#ireg 17 cls_cnt 0 2006.145.09:05:24.67#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.09:05:24.67#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.09:05:24.67#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.09:05:24.69#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.09:05:24.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.09:05:24.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.09:05:24.73#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.09:05:24.73#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.09:05:24.73$vck44/vb=2,4 2006.145.09:05:24.73#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.09:05:24.73#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.09:05:24.73#ibcon#ireg 11 cls_cnt 2 2006.145.09:05:24.73#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.09:05:24.79#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.09:05:24.79#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.09:05:24.81#ibcon#[27=AT02-04\r\n] 2006.145.09:05:24.84#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.09:05:24.84#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.09:05:24.84#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.09:05:24.84#ibcon#ireg 7 cls_cnt 0 2006.145.09:05:24.84#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.09:05:24.96#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.09:05:24.96#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.09:05:24.98#ibcon#[27=USB\r\n] 2006.145.09:05:25.01#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.09:05:25.01#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.09:05:25.01#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.09:05:25.01#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.09:05:25.01$vck44/vblo=3,649.99 2006.145.09:05:25.01#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.09:05:25.01#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.09:05:25.01#ibcon#ireg 17 cls_cnt 0 2006.145.09:05:25.01#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.09:05:25.01#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.09:05:25.01#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.09:05:25.03#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.09:05:25.07#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.09:05:25.07#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.09:05:25.07#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.09:05:25.07#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.09:05:25.07$vck44/vb=3,4 2006.145.09:05:25.07#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.09:05:25.07#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.09:05:25.07#ibcon#ireg 11 cls_cnt 2 2006.145.09:05:25.07#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.09:05:25.13#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.09:05:25.13#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.09:05:25.15#ibcon#[27=AT03-04\r\n] 2006.145.09:05:25.18#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.09:05:25.18#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.09:05:25.18#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.09:05:25.18#ibcon#ireg 7 cls_cnt 0 2006.145.09:05:25.18#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.09:05:25.30#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.09:05:25.30#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.09:05:25.32#ibcon#[27=USB\r\n] 2006.145.09:05:25.35#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.09:05:25.35#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.09:05:25.35#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.09:05:25.35#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.09:05:25.35$vck44/vblo=4,679.99 2006.145.09:05:25.35#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.09:05:25.35#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.09:05:25.35#ibcon#ireg 17 cls_cnt 0 2006.145.09:05:25.35#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.09:05:25.35#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.09:05:25.35#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.09:05:25.37#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.09:05:25.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.09:05:25.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.09:05:25.41#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.09:05:25.41#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.09:05:25.41$vck44/vb=4,4 2006.145.09:05:25.41#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.09:05:25.41#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.09:05:25.41#ibcon#ireg 11 cls_cnt 2 2006.145.09:05:25.41#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.09:05:25.47#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.09:05:25.47#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.09:05:25.49#ibcon#[27=AT04-04\r\n] 2006.145.09:05:25.52#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.09:05:25.52#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.09:05:25.52#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.09:05:25.52#ibcon#ireg 7 cls_cnt 0 2006.145.09:05:25.52#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.09:05:25.64#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.09:05:25.64#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.09:05:25.66#ibcon#[27=USB\r\n] 2006.145.09:05:25.69#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.09:05:25.69#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.09:05:25.69#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.09:05:25.69#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.09:05:25.69$vck44/vblo=5,709.99 2006.145.09:05:25.69#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.09:05:25.69#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.09:05:25.69#ibcon#ireg 17 cls_cnt 0 2006.145.09:05:25.69#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.09:05:25.69#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.09:05:25.69#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.09:05:25.71#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.09:05:25.75#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.09:05:25.75#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.09:05:25.75#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.09:05:25.75#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.09:05:25.75$vck44/vb=5,4 2006.145.09:05:25.75#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.09:05:25.75#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.09:05:25.75#ibcon#ireg 11 cls_cnt 2 2006.145.09:05:25.75#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.09:05:25.81#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.09:05:25.81#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.09:05:25.83#ibcon#[27=AT05-04\r\n] 2006.145.09:05:25.86#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.09:05:25.86#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.09:05:25.86#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.09:05:25.86#ibcon#ireg 7 cls_cnt 0 2006.145.09:05:25.86#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.09:05:25.98#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.09:05:25.98#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.09:05:26.00#ibcon#[27=USB\r\n] 2006.145.09:05:26.03#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.09:05:26.03#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.09:05:26.03#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.09:05:26.03#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.09:05:26.03$vck44/vblo=6,719.99 2006.145.09:05:26.03#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.09:05:26.03#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.09:05:26.03#ibcon#ireg 17 cls_cnt 0 2006.145.09:05:26.03#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.09:05:26.03#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.09:05:26.03#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.09:05:26.05#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.09:05:26.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.09:05:26.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.09:05:26.09#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.09:05:26.09#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.09:05:26.09$vck44/vb=6,4 2006.145.09:05:26.09#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.09:05:26.09#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.09:05:26.09#ibcon#ireg 11 cls_cnt 2 2006.145.09:05:26.09#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.09:05:26.15#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.09:05:26.15#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.09:05:26.17#ibcon#[27=AT06-04\r\n] 2006.145.09:05:26.20#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.09:05:26.20#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.09:05:26.20#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.09:05:26.20#ibcon#ireg 7 cls_cnt 0 2006.145.09:05:26.20#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.09:05:26.32#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.09:05:26.32#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.09:05:26.34#ibcon#[27=USB\r\n] 2006.145.09:05:26.37#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.09:05:26.37#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.09:05:26.37#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.09:05:26.37#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.09:05:26.37$vck44/vblo=7,734.99 2006.145.09:05:26.37#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.09:05:26.37#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.09:05:26.37#ibcon#ireg 17 cls_cnt 0 2006.145.09:05:26.37#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.09:05:26.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.09:05:26.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.09:05:26.39#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.09:05:26.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.09:05:26.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.09:05:26.43#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.09:05:26.43#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.09:05:26.43$vck44/vb=7,4 2006.145.09:05:26.43#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.09:05:26.43#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.09:05:26.43#ibcon#ireg 11 cls_cnt 2 2006.145.09:05:26.43#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.09:05:26.49#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.09:05:26.49#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.09:05:26.51#ibcon#[27=AT07-04\r\n] 2006.145.09:05:26.54#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.09:05:26.54#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.09:05:26.54#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.09:05:26.54#ibcon#ireg 7 cls_cnt 0 2006.145.09:05:26.54#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.09:05:26.66#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.09:05:26.66#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.09:05:26.68#ibcon#[27=USB\r\n] 2006.145.09:05:26.71#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.09:05:26.71#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.09:05:26.71#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.09:05:26.71#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.09:05:26.71$vck44/vblo=8,744.99 2006.145.09:05:26.71#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.09:05:26.71#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.09:05:26.71#ibcon#ireg 17 cls_cnt 0 2006.145.09:05:26.71#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.09:05:26.71#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.09:05:26.71#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.09:05:26.73#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.09:05:26.77#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.09:05:26.77#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.09:05:26.77#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.09:05:26.77#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.09:05:26.77$vck44/vb=8,4 2006.145.09:05:26.77#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.09:05:26.77#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.09:05:26.77#ibcon#ireg 11 cls_cnt 2 2006.145.09:05:26.77#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.09:05:26.83#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.09:05:26.83#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.09:05:26.85#ibcon#[27=AT08-04\r\n] 2006.145.09:05:26.88#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.09:05:26.88#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.09:05:26.88#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.09:05:26.88#ibcon#ireg 7 cls_cnt 0 2006.145.09:05:26.88#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.09:05:27.00#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.09:05:27.00#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.09:05:27.02#ibcon#[27=USB\r\n] 2006.145.09:05:27.05#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.09:05:27.05#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.09:05:27.05#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.09:05:27.05#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.09:05:27.05$vck44/vabw=wide 2006.145.09:05:27.05#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.09:05:27.05#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.09:05:27.05#ibcon#ireg 8 cls_cnt 0 2006.145.09:05:27.05#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.09:05:27.05#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.09:05:27.05#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.09:05:27.07#ibcon#[25=BW32\r\n] 2006.145.09:05:27.10#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.09:05:27.10#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.09:05:27.10#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.09:05:27.10#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.09:05:27.10$vck44/vbbw=wide 2006.145.09:05:27.10#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.09:05:27.10#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.09:05:27.10#ibcon#ireg 8 cls_cnt 0 2006.145.09:05:27.10#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.09:05:27.17#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.09:05:27.17#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.09:05:27.19#ibcon#[27=BW32\r\n] 2006.145.09:05:27.22#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.09:05:27.22#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.09:05:27.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.09:05:27.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.09:05:27.22$setupk4/ifdk4 2006.145.09:05:27.22$ifdk4/lo= 2006.145.09:05:27.22$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.09:05:27.22$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.09:05:27.22$ifdk4/patch= 2006.145.09:05:27.22$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.09:05:27.22$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.09:05:27.22$setupk4/!*+20s 2006.145.09:05:30.66#abcon#<5=/05 4.3 7.7 18.19 661018.0\r\n> 2006.145.09:05:30.68#abcon#{5=INTERFACE CLEAR} 2006.145.09:05:30.74#abcon#[5=S1D000X0/0*\r\n] 2006.145.09:05:34.13#trakl#Source acquired 2006.145.09:05:35.13#flagr#flagr/antenna,acquired 2006.145.09:05:40.83#abcon#<5=/05 4.3 7.7 18.19 661018.0\r\n> 2006.145.09:05:40.85#abcon#{5=INTERFACE CLEAR} 2006.145.09:05:40.91#abcon#[5=S1D000X0/0*\r\n] 2006.145.09:05:41.70$setupk4/"tpicd 2006.145.09:05:41.70$setupk4/echo=off 2006.145.09:05:41.70$setupk4/xlog=off 2006.145.09:05:41.70:!2006.145.09:15:37 2006.145.09:08:34.14#trakl#Off source 2006.145.09:08:34.14?ERROR st -7 Antenna off-source! 2006.145.09:08:34.14#trakl#az 46.058 el 48.492 azerr*cos(el) 0.0017 elerr 0.0164 2006.145.09:08:35.14#flagr#flagr/antenna,off-source 2006.145.09:08:40.14#trakl#Source re-acquired 2006.145.09:08:41.14#flagr#flagr/antenna,re-acquired 2006.145.09:15:37.00:preob 2006.145.09:15:37.14/onsource/TRACKING 2006.145.09:15:37.14:!2006.145.09:15:47 2006.145.09:15:47.00:"tape 2006.145.09:15:47.00:"st=record 2006.145.09:15:47.00:data_valid=on 2006.145.09:15:47.00:midob 2006.145.09:15:47.14/onsource/TRACKING 2006.145.09:15:47.14/wx/18.09,1018.2,67 2006.145.09:15:47.34/cable/+6.5418E-03 2006.145.09:15:48.43/va/01,08,usb,yes,28,30 2006.145.09:15:48.43/va/02,07,usb,yes,30,31 2006.145.09:15:48.43/va/03,08,usb,yes,27,28 2006.145.09:15:48.43/va/04,07,usb,yes,31,32 2006.145.09:15:48.43/va/05,04,usb,yes,27,27 2006.145.09:15:48.43/va/06,04,usb,yes,30,30 2006.145.09:15:48.43/va/07,04,usb,yes,30,32 2006.145.09:15:48.43/va/08,04,usb,yes,26,31 2006.145.09:15:48.66/valo/01,524.99,yes,locked 2006.145.09:15:48.66/valo/02,534.99,yes,locked 2006.145.09:15:48.66/valo/03,564.99,yes,locked 2006.145.09:15:48.66/valo/04,624.99,yes,locked 2006.145.09:15:48.66/valo/05,734.99,yes,locked 2006.145.09:15:48.66/valo/06,814.99,yes,locked 2006.145.09:15:48.66/valo/07,864.99,yes,locked 2006.145.09:15:48.66/valo/08,884.99,yes,locked 2006.145.09:15:49.75/vb/01,03,usb,yes,35,33 2006.145.09:15:49.75/vb/02,04,usb,yes,31,31 2006.145.09:15:49.75/vb/03,04,usb,yes,28,31 2006.145.09:15:49.75/vb/04,04,usb,yes,32,31 2006.145.09:15:49.75/vb/05,04,usb,yes,25,27 2006.145.09:15:49.75/vb/06,04,usb,yes,29,26 2006.145.09:15:49.75/vb/07,04,usb,yes,29,29 2006.145.09:15:49.75/vb/08,04,usb,yes,27,30 2006.145.09:15:49.99/vblo/01,629.99,yes,locked 2006.145.09:15:49.99/vblo/02,634.99,yes,locked 2006.145.09:15:49.99/vblo/03,649.99,yes,locked 2006.145.09:15:49.99/vblo/04,679.99,yes,locked 2006.145.09:15:49.99/vblo/05,709.99,yes,locked 2006.145.09:15:49.99/vblo/06,719.99,yes,locked 2006.145.09:15:49.99/vblo/07,734.99,yes,locked 2006.145.09:15:49.99/vblo/08,744.99,yes,locked 2006.145.09:15:50.14/vabw/8 2006.145.09:15:50.29/vbbw/8 2006.145.09:15:50.38/xfe/off,on,15.2 2006.145.09:15:50.77/ifatt/23,28,28,28 2006.145.09:15:51.07/fmout-gps/S +4.9E-08 2006.145.09:15:51.15:!2006.145.09:22:37 2006.145.09:22:37.00:data_valid=off 2006.145.09:22:37.00:"et 2006.145.09:22:37.00:!+3s 2006.145.09:22:40.02:"tape 2006.145.09:22:40.02:postob 2006.145.09:22:40.09/cable/+6.5427E-03 2006.145.09:22:40.09/wx/18.03,1018.3,66 2006.145.09:22:41.08/fmout-gps/S +4.8E-08 2006.145.09:22:41.08:scan_name=145-0929,jd0605,110 2006.145.09:22:41.08:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.145.09:22:42.13#flagr#flagr/antenna,new-source 2006.145.09:22:42.13:checkk5 2006.145.09:22:42.57/chk_autoobs//k5ts1/ autoobs is running! 2006.145.09:22:43.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.09:22:43.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.09:22:43.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.09:22:44.32/chk_obsdata//k5ts1/T1450915??a.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.145.09:22:44.76/chk_obsdata//k5ts2/T1450915??b.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.145.09:22:45.20/chk_obsdata//k5ts3/T1450915??c.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.145.09:22:45.64/chk_obsdata//k5ts4/T1450915??d.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.145.09:22:46.40/k5log//k5ts1_log_newline 2006.145.09:22:47.15/k5log//k5ts2_log_newline 2006.145.09:22:47.90/k5log//k5ts3_log_newline 2006.145.09:22:48.63/k5log//k5ts4_log_newline 2006.145.09:22:48.65/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.09:22:48.65:setupk4=1 2006.145.09:22:48.65$setupk4/echo=on 2006.145.09:22:48.65$setupk4/pcalon 2006.145.09:22:48.65$pcalon/"no phase cal control is implemented here 2006.145.09:22:48.65$setupk4/"tpicd=stop 2006.145.09:22:48.66$setupk4/"rec=synch_on 2006.145.09:22:48.66$setupk4/"rec_mode=128 2006.145.09:22:48.66$setupk4/!* 2006.145.09:22:48.66$setupk4/recpk4 2006.145.09:22:48.66$recpk4/recpatch= 2006.145.09:22:48.66$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.09:22:48.66$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.09:22:48.66$setupk4/vck44 2006.145.09:22:48.66$vck44/valo=1,524.99 2006.145.09:22:48.66#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.09:22:48.66#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.09:22:48.66#ibcon#ireg 17 cls_cnt 0 2006.145.09:22:48.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.09:22:48.66#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.09:22:48.66#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.09:22:48.70#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.09:22:48.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.09:22:48.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.09:22:48.75#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.09:22:48.75#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.09:22:48.75$vck44/va=1,8 2006.145.09:22:48.75#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.09:22:48.75#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.09:22:48.75#ibcon#ireg 11 cls_cnt 2 2006.145.09:22:48.75#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.09:22:48.75#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.09:22:48.75#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.09:22:48.77#ibcon#[25=AT01-08\r\n] 2006.145.09:22:48.80#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.09:22:48.80#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.09:22:48.80#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.09:22:48.80#ibcon#ireg 7 cls_cnt 0 2006.145.09:22:48.80#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.09:22:48.94#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.09:22:48.94#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.09:22:48.96#ibcon#[25=USB\r\n] 2006.145.09:22:48.99#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.09:22:48.99#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.09:22:48.99#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.09:22:48.99#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.09:22:48.99$vck44/valo=2,534.99 2006.145.09:22:48.99#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.09:22:48.99#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.09:22:48.99#ibcon#ireg 17 cls_cnt 0 2006.145.09:22:48.99#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:22:48.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:22:48.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:22:49.02#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.09:22:49.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:22:49.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:22:49.06#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.09:22:49.06#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.09:22:49.06$vck44/va=2,7 2006.145.09:22:49.06#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.09:22:49.06#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.09:22:49.06#ibcon#ireg 11 cls_cnt 2 2006.145.09:22:49.06#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:22:49.11#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:22:49.11#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:22:49.13#ibcon#[25=AT02-07\r\n] 2006.145.09:22:49.16#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:22:49.16#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:22:49.16#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.09:22:49.16#ibcon#ireg 7 cls_cnt 0 2006.145.09:22:49.16#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:22:49.28#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:22:49.28#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:22:49.30#ibcon#[25=USB\r\n] 2006.145.09:22:49.33#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:22:49.33#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:22:49.33#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.09:22:49.33#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.09:22:49.33$vck44/valo=3,564.99 2006.145.09:22:49.33#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.09:22:49.33#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.09:22:49.33#ibcon#ireg 17 cls_cnt 0 2006.145.09:22:49.33#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:22:49.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:22:49.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:22:49.35#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.09:22:49.39#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:22:49.39#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:22:49.39#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.09:22:49.39#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.09:22:49.39$vck44/va=3,8 2006.145.09:22:49.39#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.09:22:49.39#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.09:22:49.39#ibcon#ireg 11 cls_cnt 2 2006.145.09:22:49.39#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:22:49.45#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:22:49.45#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:22:49.47#ibcon#[25=AT03-08\r\n] 2006.145.09:22:49.50#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:22:49.50#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:22:49.50#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.09:22:49.50#ibcon#ireg 7 cls_cnt 0 2006.145.09:22:49.50#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:22:49.62#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:22:49.62#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:22:49.64#ibcon#[25=USB\r\n] 2006.145.09:22:49.67#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:22:49.67#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:22:49.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.09:22:49.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.09:22:49.67$vck44/valo=4,624.99 2006.145.09:22:49.67#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.09:22:49.67#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.09:22:49.67#ibcon#ireg 17 cls_cnt 0 2006.145.09:22:49.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:22:49.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:22:49.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:22:49.69#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.09:22:49.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:22:49.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:22:49.73#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.09:22:49.73#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.09:22:49.73$vck44/va=4,7 2006.145.09:22:49.73#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.09:22:49.73#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.09:22:49.73#ibcon#ireg 11 cls_cnt 2 2006.145.09:22:49.73#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:22:49.79#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:22:49.79#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:22:49.81#ibcon#[25=AT04-07\r\n] 2006.145.09:22:49.84#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:22:49.84#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:22:49.84#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.09:22:49.84#ibcon#ireg 7 cls_cnt 0 2006.145.09:22:49.84#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:22:49.96#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:22:49.96#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:22:49.98#ibcon#[25=USB\r\n] 2006.145.09:22:50.01#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:22:50.01#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:22:50.01#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.09:22:50.01#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.09:22:50.01$vck44/valo=5,734.99 2006.145.09:22:50.01#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.09:22:50.01#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.09:22:50.01#ibcon#ireg 17 cls_cnt 0 2006.145.09:22:50.01#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:22:50.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:22:50.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:22:50.03#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.09:22:50.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:22:50.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:22:50.07#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.09:22:50.07#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.09:22:50.07$vck44/va=5,4 2006.145.09:22:50.07#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.09:22:50.07#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.09:22:50.07#ibcon#ireg 11 cls_cnt 2 2006.145.09:22:50.07#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.09:22:50.13#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.09:22:50.13#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.09:22:50.15#ibcon#[25=AT05-04\r\n] 2006.145.09:22:50.18#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.09:22:50.18#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.09:22:50.18#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.09:22:50.18#ibcon#ireg 7 cls_cnt 0 2006.145.09:22:50.18#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.09:22:50.30#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.09:22:50.30#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.09:22:50.32#ibcon#[25=USB\r\n] 2006.145.09:22:50.35#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.09:22:50.35#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.09:22:50.35#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.09:22:50.35#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.09:22:50.35$vck44/valo=6,814.99 2006.145.09:22:50.35#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.09:22:50.35#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.09:22:50.35#ibcon#ireg 17 cls_cnt 0 2006.145.09:22:50.35#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:22:50.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:22:50.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:22:50.38#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.09:22:50.42#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:22:50.42#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:22:50.42#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.09:22:50.42#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.09:22:50.42$vck44/va=6,4 2006.145.09:22:50.42#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.09:22:50.42#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.09:22:50.42#ibcon#ireg 11 cls_cnt 2 2006.145.09:22:50.42#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.09:22:50.47#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.09:22:50.47#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.09:22:50.49#ibcon#[25=AT06-04\r\n] 2006.145.09:22:50.52#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.09:22:50.52#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.09:22:50.52#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.09:22:50.52#ibcon#ireg 7 cls_cnt 0 2006.145.09:22:50.52#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.09:22:50.64#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.09:22:50.64#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.09:22:50.66#ibcon#[25=USB\r\n] 2006.145.09:22:50.69#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.09:22:50.69#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.09:22:50.69#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.09:22:50.69#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.09:22:50.69$vck44/valo=7,864.99 2006.145.09:22:50.69#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.09:22:50.69#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.09:22:50.69#ibcon#ireg 17 cls_cnt 0 2006.145.09:22:50.69#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.09:22:50.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.09:22:50.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.09:22:50.71#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.09:22:50.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.09:22:50.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.09:22:50.75#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.09:22:50.75#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.09:22:50.75$vck44/va=7,4 2006.145.09:22:50.75#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.09:22:50.75#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.09:22:50.75#ibcon#ireg 11 cls_cnt 2 2006.145.09:22:50.75#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.09:22:50.81#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.09:22:50.81#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.09:22:50.83#ibcon#[25=AT07-04\r\n] 2006.145.09:22:50.86#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.09:22:50.86#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.09:22:50.86#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.09:22:50.86#ibcon#ireg 7 cls_cnt 0 2006.145.09:22:50.86#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.09:22:50.98#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.09:22:50.98#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.09:22:51.00#ibcon#[25=USB\r\n] 2006.145.09:22:51.03#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.09:22:51.03#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.09:22:51.03#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.09:22:51.03#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.09:22:51.03$vck44/valo=8,884.99 2006.145.09:22:51.03#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.09:22:51.03#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.09:22:51.03#ibcon#ireg 17 cls_cnt 0 2006.145.09:22:51.03#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:22:51.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:22:51.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:22:51.05#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.09:22:51.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:22:51.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:22:51.09#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.09:22:51.09#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.09:22:51.09$vck44/va=8,4 2006.145.09:22:51.09#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.09:22:51.09#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.09:22:51.09#ibcon#ireg 11 cls_cnt 2 2006.145.09:22:51.09#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.09:22:51.15#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.09:22:51.15#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.09:22:51.17#ibcon#[25=AT08-04\r\n] 2006.145.09:22:51.20#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.09:22:51.20#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.09:22:51.20#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.09:22:51.20#ibcon#ireg 7 cls_cnt 0 2006.145.09:22:51.20#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.09:22:51.32#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.09:22:51.32#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.09:22:51.34#ibcon#[25=USB\r\n] 2006.145.09:22:51.37#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.09:22:51.37#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.09:22:51.37#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.09:22:51.37#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.09:22:51.37$vck44/vblo=1,629.99 2006.145.09:22:51.37#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.09:22:51.37#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.09:22:51.37#ibcon#ireg 17 cls_cnt 0 2006.145.09:22:51.37#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.09:22:51.37#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.09:22:51.37#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.09:22:51.39#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.09:22:51.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.09:22:51.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.09:22:51.43#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.09:22:51.43#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.09:22:51.43$vck44/vb=1,3 2006.145.09:22:51.43#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.09:22:51.43#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.09:22:51.43#ibcon#ireg 11 cls_cnt 2 2006.145.09:22:51.43#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.09:22:51.43#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.09:22:51.43#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.09:22:51.45#ibcon#[27=AT01-03\r\n] 2006.145.09:22:51.48#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.09:22:51.48#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.09:22:51.48#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.09:22:51.48#ibcon#ireg 7 cls_cnt 0 2006.145.09:22:51.48#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.09:22:51.60#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.09:22:51.60#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.09:22:51.62#ibcon#[27=USB\r\n] 2006.145.09:22:51.65#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.09:22:51.65#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.09:22:51.65#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.09:22:51.65#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.09:22:51.65$vck44/vblo=2,634.99 2006.145.09:22:51.65#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.09:22:51.65#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.09:22:51.65#ibcon#ireg 17 cls_cnt 0 2006.145.09:22:51.65#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.09:22:51.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.09:22:51.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.09:22:51.67#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.09:22:51.71#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.09:22:51.71#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.09:22:51.71#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.09:22:51.71#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.09:22:51.71$vck44/vb=2,4 2006.145.09:22:51.71#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.09:22:51.71#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.09:22:51.71#ibcon#ireg 11 cls_cnt 2 2006.145.09:22:51.71#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.09:22:51.77#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.09:22:51.77#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.09:22:51.79#ibcon#[27=AT02-04\r\n] 2006.145.09:22:51.82#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.09:22:51.82#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.09:22:51.82#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.09:22:51.82#ibcon#ireg 7 cls_cnt 0 2006.145.09:22:51.82#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.09:22:51.94#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.09:22:51.94#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.09:22:51.96#ibcon#[27=USB\r\n] 2006.145.09:22:51.99#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.09:22:51.99#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.09:22:51.99#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.09:22:51.99#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.09:22:51.99$vck44/vblo=3,649.99 2006.145.09:22:51.99#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.09:22:51.99#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.09:22:51.99#ibcon#ireg 17 cls_cnt 0 2006.145.09:22:51.99#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:22:51.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:22:51.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:22:52.01#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.09:22:52.05#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:22:52.05#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:22:52.05#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.09:22:52.05#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.09:22:52.05$vck44/vb=3,4 2006.145.09:22:52.05#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.09:22:52.05#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.09:22:52.05#ibcon#ireg 11 cls_cnt 2 2006.145.09:22:52.05#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:22:52.11#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:22:52.11#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:22:52.13#ibcon#[27=AT03-04\r\n] 2006.145.09:22:52.16#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:22:52.16#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:22:52.16#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.09:22:52.16#ibcon#ireg 7 cls_cnt 0 2006.145.09:22:52.16#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:22:52.28#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:22:52.28#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:22:52.30#ibcon#[27=USB\r\n] 2006.145.09:22:52.33#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:22:52.33#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:22:52.33#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.09:22:52.33#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.09:22:52.33$vck44/vblo=4,679.99 2006.145.09:22:52.33#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.09:22:52.33#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.09:22:52.33#ibcon#ireg 17 cls_cnt 0 2006.145.09:22:52.33#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:22:52.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:22:52.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:22:52.35#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.09:22:52.39#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:22:52.39#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:22:52.39#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.09:22:52.39#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.09:22:52.39$vck44/vb=4,4 2006.145.09:22:52.39#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.09:22:52.39#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.09:22:52.39#ibcon#ireg 11 cls_cnt 2 2006.145.09:22:52.39#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:22:52.45#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:22:52.45#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:22:52.47#ibcon#[27=AT04-04\r\n] 2006.145.09:22:52.50#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:22:52.50#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:22:52.50#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.09:22:52.50#ibcon#ireg 7 cls_cnt 0 2006.145.09:22:52.50#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:22:52.62#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:22:52.62#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:22:52.64#ibcon#[27=USB\r\n] 2006.145.09:22:52.67#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:22:52.67#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:22:52.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.09:22:52.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.09:22:52.67$vck44/vblo=5,709.99 2006.145.09:22:52.67#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.09:22:52.67#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.09:22:52.67#ibcon#ireg 17 cls_cnt 0 2006.145.09:22:52.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:22:52.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:22:52.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:22:52.69#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.09:22:52.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:22:52.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:22:52.73#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.09:22:52.73#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.09:22:52.73$vck44/vb=5,4 2006.145.09:22:52.73#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.09:22:52.73#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.09:22:52.73#ibcon#ireg 11 cls_cnt 2 2006.145.09:22:52.73#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:22:52.79#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:22:52.79#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:22:52.81#ibcon#[27=AT05-04\r\n] 2006.145.09:22:52.84#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:22:52.84#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:22:52.84#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.09:22:52.84#ibcon#ireg 7 cls_cnt 0 2006.145.09:22:52.84#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:22:52.96#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:22:52.96#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:22:52.98#ibcon#[27=USB\r\n] 2006.145.09:22:53.01#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:22:53.01#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:22:53.01#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.09:22:53.01#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.09:22:53.01$vck44/vblo=6,719.99 2006.145.09:22:53.01#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.09:22:53.01#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.09:22:53.01#ibcon#ireg 17 cls_cnt 0 2006.145.09:22:53.01#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:22:53.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:22:53.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:22:53.03#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.09:22:53.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:22:53.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:22:53.07#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.09:22:53.07#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.09:22:53.07$vck44/vb=6,4 2006.145.09:22:53.07#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.09:22:53.07#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.09:22:53.07#ibcon#ireg 11 cls_cnt 2 2006.145.09:22:53.07#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.09:22:53.13#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.09:22:53.13#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.09:22:53.15#ibcon#[27=AT06-04\r\n] 2006.145.09:22:53.18#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.09:22:53.18#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.09:22:53.18#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.09:22:53.18#ibcon#ireg 7 cls_cnt 0 2006.145.09:22:53.18#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.09:22:53.30#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.09:22:53.30#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.09:22:53.32#ibcon#[27=USB\r\n] 2006.145.09:22:53.35#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.09:22:53.35#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.09:22:53.35#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.09:22:53.35#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.09:22:53.35$vck44/vblo=7,734.99 2006.145.09:22:53.35#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.09:22:53.35#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.09:22:53.35#ibcon#ireg 17 cls_cnt 0 2006.145.09:22:53.35#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:22:53.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:22:53.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:22:53.38#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.09:22:53.42#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:22:53.42#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:22:53.42#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.09:22:53.42#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.09:22:53.42$vck44/vb=7,4 2006.145.09:22:53.42#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.09:22:53.42#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.09:22:53.42#ibcon#ireg 11 cls_cnt 2 2006.145.09:22:53.42#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.09:22:53.47#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.09:22:53.47#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.09:22:53.49#ibcon#[27=AT07-04\r\n] 2006.145.09:22:53.52#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.09:22:53.52#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.09:22:53.52#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.09:22:53.52#ibcon#ireg 7 cls_cnt 0 2006.145.09:22:53.52#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.09:22:53.64#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.09:22:53.64#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.09:22:53.66#ibcon#[27=USB\r\n] 2006.145.09:22:53.69#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.09:22:53.69#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.09:22:53.69#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.09:22:53.69#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.09:22:53.69$vck44/vblo=8,744.99 2006.145.09:22:53.69#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.09:22:53.69#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.09:22:53.69#ibcon#ireg 17 cls_cnt 0 2006.145.09:22:53.69#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.09:22:53.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.09:22:53.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.09:22:53.71#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.09:22:53.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.09:22:53.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.09:22:53.75#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.09:22:53.75#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.09:22:53.75$vck44/vb=8,4 2006.145.09:22:53.75#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.09:22:53.75#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.09:22:53.75#ibcon#ireg 11 cls_cnt 2 2006.145.09:22:53.75#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.09:22:53.81#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.09:22:53.81#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.09:22:53.83#ibcon#[27=AT08-04\r\n] 2006.145.09:22:53.86#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.09:22:53.86#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.09:22:53.86#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.09:22:53.86#ibcon#ireg 7 cls_cnt 0 2006.145.09:22:53.86#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.09:22:53.98#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.09:22:53.98#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.09:22:54.00#ibcon#[27=USB\r\n] 2006.145.09:22:54.03#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.09:22:54.03#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.09:22:54.03#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.09:22:54.03#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.09:22:54.03$vck44/vabw=wide 2006.145.09:22:54.03#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.09:22:54.03#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.09:22:54.03#ibcon#ireg 8 cls_cnt 0 2006.145.09:22:54.03#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:22:54.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:22:54.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:22:54.05#ibcon#[25=BW32\r\n] 2006.145.09:22:54.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:22:54.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:22:54.08#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.09:22:54.08#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.09:22:54.08$vck44/vbbw=wide 2006.145.09:22:54.08#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.09:22:54.08#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.09:22:54.08#ibcon#ireg 8 cls_cnt 0 2006.145.09:22:54.08#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.09:22:54.15#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.09:22:54.15#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.09:22:54.17#ibcon#[27=BW32\r\n] 2006.145.09:22:54.20#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.09:22:54.20#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.09:22:54.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.09:22:54.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.09:22:54.20$setupk4/ifdk4 2006.145.09:22:54.20$ifdk4/lo= 2006.145.09:22:54.20$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.09:22:54.20$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.09:22:54.20$ifdk4/patch= 2006.145.09:22:54.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.09:22:54.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.09:22:54.20$setupk4/!*+20s 2006.145.09:22:58.32#abcon#<5=/05 4.4 7.6 18.03 671018.3\r\n> 2006.145.09:22:58.34#abcon#{5=INTERFACE CLEAR} 2006.145.09:22:58.40#abcon#[5=S1D000X0/0*\r\n] 2006.145.09:23:08.49#abcon#<5=/05 4.4 7.6 18.03 671018.3\r\n> 2006.145.09:23:08.51#abcon#{5=INTERFACE CLEAR} 2006.145.09:23:08.59#abcon#[5=S1D000X0/0*\r\n] 2006.145.09:23:08.67$setupk4/"tpicd 2006.145.09:23:08.67$setupk4/echo=off 2006.145.09:23:08.67$setupk4/xlog=off 2006.145.09:23:08.67:!2006.145.09:29:35 2006.145.09:23:31.14#trakl#Source acquired 2006.145.09:23:32.14#flagr#flagr/antenna,acquired 2006.145.09:29:35.00:preob 2006.145.09:29:36.14/onsource/TRACKING 2006.145.09:29:36.14:!2006.145.09:29:45 2006.145.09:29:45.00:"tape 2006.145.09:29:45.00:"st=record 2006.145.09:29:45.00:data_valid=on 2006.145.09:29:45.00:midob 2006.145.09:29:45.13/onsource/TRACKING 2006.145.09:29:45.14/wx/17.98,1018.5,66 2006.145.09:29:45.19/cable/+6.5421E-03 2006.145.09:29:46.28/va/01,08,usb,yes,31,34 2006.145.09:29:46.28/va/02,07,usb,yes,34,34 2006.145.09:29:46.28/va/03,08,usb,yes,31,32 2006.145.09:29:46.28/va/04,07,usb,yes,35,36 2006.145.09:29:46.28/va/05,04,usb,yes,30,31 2006.145.09:29:46.28/va/06,04,usb,yes,34,34 2006.145.09:29:46.28/va/07,04,usb,yes,34,35 2006.145.09:29:46.28/va/08,04,usb,yes,29,35 2006.145.09:29:46.51/valo/01,524.99,yes,locked 2006.145.09:29:46.51/valo/02,534.99,yes,locked 2006.145.09:29:46.51/valo/03,564.99,yes,locked 2006.145.09:29:46.51/valo/04,624.99,yes,locked 2006.145.09:29:46.51/valo/05,734.99,yes,locked 2006.145.09:29:46.51/valo/06,814.99,yes,locked 2006.145.09:29:46.51/valo/07,864.99,yes,locked 2006.145.09:29:46.51/valo/08,884.99,yes,locked 2006.145.09:29:47.60/vb/01,03,usb,yes,36,33 2006.145.09:29:47.60/vb/02,04,usb,yes,31,31 2006.145.09:29:47.60/vb/03,04,usb,yes,28,31 2006.145.09:29:47.60/vb/04,04,usb,yes,32,31 2006.145.09:29:47.60/vb/05,04,usb,yes,25,28 2006.145.09:29:47.60/vb/06,04,usb,yes,29,26 2006.145.09:29:47.60/vb/07,04,usb,yes,29,29 2006.145.09:29:47.60/vb/08,04,usb,yes,27,30 2006.145.09:29:47.83/vblo/01,629.99,yes,locked 2006.145.09:29:47.83/vblo/02,634.99,yes,locked 2006.145.09:29:47.83/vblo/03,649.99,yes,locked 2006.145.09:29:47.83/vblo/04,679.99,yes,locked 2006.145.09:29:47.83/vblo/05,709.99,yes,locked 2006.145.09:29:47.83/vblo/06,719.99,yes,locked 2006.145.09:29:47.83/vblo/07,734.99,yes,locked 2006.145.09:29:47.83/vblo/08,744.99,yes,locked 2006.145.09:29:47.98/vabw/8 2006.145.09:29:48.13/vbbw/8 2006.145.09:29:48.24/xfe/off,on,15.5 2006.145.09:29:48.62/ifatt/23,28,28,28 2006.145.09:29:49.07/fmout-gps/S +4.9E-08 2006.145.09:29:49.12:!2006.145.09:31:35 2006.145.09:31:35.01:data_valid=off 2006.145.09:31:35.02:"et 2006.145.09:31:35.02:!+3s 2006.145.09:31:38.05:"tape 2006.145.09:31:38.06:postob 2006.145.09:31:38.28/cable/+6.5406E-03 2006.145.09:31:38.29/wx/17.96,1018.5,66 2006.145.09:31:38.34/fmout-gps/S +4.8E-08 2006.145.09:31:38.35:scan_name=145-0937,jd0605,70 2006.145.09:31:38.35:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.145.09:31:39.14#flagr#flagr/antenna,new-source 2006.145.09:31:39.15:checkk5 2006.145.09:31:39.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.09:31:40.07/chk_autoobs//k5ts2/ autoobs is running! 2006.145.09:31:40.52/chk_autoobs//k5ts3/ autoobs is running! 2006.145.09:31:40.95/chk_autoobs//k5ts4/ autoobs is running! 2006.145.09:31:41.38/chk_obsdata//k5ts1/T1450929??a.dat file size is correct (nominal:440MB, actual:436MB). 2006.145.09:31:41.82/chk_obsdata//k5ts2/T1450929??b.dat file size is correct (nominal:440MB, actual:436MB). 2006.145.09:31:42.26/chk_obsdata//k5ts3/T1450929??c.dat file size is correct (nominal:440MB, actual:436MB). 2006.145.09:31:42.69/chk_obsdata//k5ts4/T1450929??d.dat file size is correct (nominal:440MB, actual:436MB). 2006.145.09:31:43.46/k5log//k5ts1_log_newline 2006.145.09:31:44.20/k5log//k5ts2_log_newline 2006.145.09:31:44.94/k5log//k5ts3_log_newline 2006.145.09:31:45.68/k5log//k5ts4_log_newline 2006.145.09:31:45.70/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.09:31:45.70:setupk4=1 2006.145.09:31:45.71$setupk4/echo=on 2006.145.09:31:45.71$setupk4/pcalon 2006.145.09:31:45.71$pcalon/"no phase cal control is implemented here 2006.145.09:31:45.71$setupk4/"tpicd=stop 2006.145.09:31:45.71$setupk4/"rec=synch_on 2006.145.09:31:45.71$setupk4/"rec_mode=128 2006.145.09:31:45.71$setupk4/!* 2006.145.09:31:45.71$setupk4/recpk4 2006.145.09:31:45.71$recpk4/recpatch= 2006.145.09:31:45.71$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.09:31:45.71$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.09:31:45.71$setupk4/vck44 2006.145.09:31:45.71$vck44/valo=1,524.99 2006.145.09:31:45.71#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.09:31:45.71#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.09:31:45.71#ibcon#ireg 17 cls_cnt 0 2006.145.09:31:45.71#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.09:31:45.71#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.09:31:45.71#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.09:31:45.72#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.09:31:45.77#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.09:31:45.77#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.09:31:45.77#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.09:31:45.77#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.09:31:45.77$vck44/va=1,8 2006.145.09:31:45.77#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.09:31:45.77#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.09:31:45.77#ibcon#ireg 11 cls_cnt 2 2006.145.09:31:45.77#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.09:31:45.77#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.09:31:45.77#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.09:31:45.79#ibcon#[25=AT01-08\r\n] 2006.145.09:31:45.82#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.09:31:45.82#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.09:31:45.82#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.09:31:45.82#ibcon#ireg 7 cls_cnt 0 2006.145.09:31:45.82#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.09:31:45.94#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.09:31:45.94#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.09:31:45.96#ibcon#[25=USB\r\n] 2006.145.09:31:45.99#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.09:31:45.99#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.09:31:45.99#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.09:31:45.99#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.09:31:45.99$vck44/valo=2,534.99 2006.145.09:31:45.99#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.09:31:45.99#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.09:31:45.99#ibcon#ireg 17 cls_cnt 0 2006.145.09:31:45.99#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.09:31:45.99#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.09:31:45.99#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.09:31:46.03#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.09:31:46.06#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.09:31:46.06#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.09:31:46.06#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.09:31:46.06#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.09:31:46.06$vck44/va=2,7 2006.145.09:31:46.06#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.09:31:46.06#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.09:31:46.06#ibcon#ireg 11 cls_cnt 2 2006.145.09:31:46.06#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.09:31:46.12#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.09:31:46.12#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.09:31:46.13#ibcon#[25=AT02-07\r\n] 2006.145.09:31:46.16#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.09:31:46.16#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.09:31:46.16#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.09:31:46.16#ibcon#ireg 7 cls_cnt 0 2006.145.09:31:46.16#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.09:31:46.28#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.09:31:46.28#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.09:31:46.30#ibcon#[25=USB\r\n] 2006.145.09:31:46.33#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.09:31:46.33#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.09:31:46.33#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.09:31:46.33#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.09:31:46.33$vck44/valo=3,564.99 2006.145.09:31:46.33#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.09:31:46.33#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.09:31:46.33#ibcon#ireg 17 cls_cnt 0 2006.145.09:31:46.33#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.09:31:46.33#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.09:31:46.33#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.09:31:46.35#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.09:31:46.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.09:31:46.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.09:31:46.39#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.09:31:46.39#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.09:31:46.39$vck44/va=3,8 2006.145.09:31:46.39#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.09:31:46.39#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.09:31:46.39#ibcon#ireg 11 cls_cnt 2 2006.145.09:31:46.39#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.09:31:46.45#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.09:31:46.45#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.09:31:46.47#ibcon#[25=AT03-08\r\n] 2006.145.09:31:46.50#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.09:31:46.50#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.09:31:46.50#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.09:31:46.50#ibcon#ireg 7 cls_cnt 0 2006.145.09:31:46.50#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.09:31:46.62#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.09:31:46.62#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.09:31:46.64#ibcon#[25=USB\r\n] 2006.145.09:31:46.67#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.09:31:46.67#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.09:31:46.67#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.09:31:46.67#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.09:31:46.67$vck44/valo=4,624.99 2006.145.09:31:46.67#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.09:31:46.67#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.09:31:46.67#ibcon#ireg 17 cls_cnt 0 2006.145.09:31:46.67#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.09:31:46.67#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.09:31:46.67#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.09:31:46.69#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.09:31:46.73#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.09:31:46.73#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.09:31:46.73#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.09:31:46.73#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.09:31:46.73$vck44/va=4,7 2006.145.09:31:46.73#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.09:31:46.73#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.09:31:46.73#ibcon#ireg 11 cls_cnt 2 2006.145.09:31:46.73#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.09:31:46.79#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.09:31:46.79#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.09:31:46.81#ibcon#[25=AT04-07\r\n] 2006.145.09:31:46.84#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.09:31:46.84#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.09:31:46.84#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.09:31:46.84#ibcon#ireg 7 cls_cnt 0 2006.145.09:31:46.84#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.09:31:46.96#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.09:31:46.96#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.09:31:46.98#ibcon#[25=USB\r\n] 2006.145.09:31:47.01#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.09:31:47.01#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.09:31:47.01#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.09:31:47.01#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.09:31:47.01$vck44/valo=5,734.99 2006.145.09:31:47.01#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.09:31:47.01#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.09:31:47.01#ibcon#ireg 17 cls_cnt 0 2006.145.09:31:47.01#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.09:31:47.01#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.09:31:47.01#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.09:31:47.03#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.09:31:47.07#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.09:31:47.07#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.09:31:47.07#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.09:31:47.07#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.09:31:47.07$vck44/va=5,4 2006.145.09:31:47.07#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.09:31:47.07#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.09:31:47.07#ibcon#ireg 11 cls_cnt 2 2006.145.09:31:47.07#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.09:31:47.13#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.09:31:47.13#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.09:31:47.15#ibcon#[25=AT05-04\r\n] 2006.145.09:31:47.18#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.09:31:47.18#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.09:31:47.18#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.09:31:47.18#ibcon#ireg 7 cls_cnt 0 2006.145.09:31:47.18#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.09:31:47.30#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.09:31:47.30#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.09:31:47.32#ibcon#[25=USB\r\n] 2006.145.09:31:47.37#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.09:31:47.37#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.09:31:47.37#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.09:31:47.37#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.09:31:47.37$vck44/valo=6,814.99 2006.145.09:31:47.37#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.09:31:47.37#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.09:31:47.37#ibcon#ireg 17 cls_cnt 0 2006.145.09:31:47.37#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.09:31:47.37#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.09:31:47.37#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.09:31:47.38#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.09:31:47.42#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.09:31:47.42#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.09:31:47.42#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.09:31:47.42#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.09:31:47.42$vck44/va=6,4 2006.145.09:31:47.42#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.09:31:47.42#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.09:31:47.42#ibcon#ireg 11 cls_cnt 2 2006.145.09:31:47.42#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.09:31:47.49#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.09:31:47.49#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.09:31:47.51#ibcon#[25=AT06-04\r\n] 2006.145.09:31:47.54#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.09:31:47.54#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.09:31:47.54#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.09:31:47.54#ibcon#ireg 7 cls_cnt 0 2006.145.09:31:47.54#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.09:31:47.66#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.09:31:47.66#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.09:31:47.68#ibcon#[25=USB\r\n] 2006.145.09:31:47.71#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.09:31:47.71#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.09:31:47.71#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.09:31:47.71#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.09:31:47.71$vck44/valo=7,864.99 2006.145.09:31:47.71#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.09:31:47.71#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.09:31:47.71#ibcon#ireg 17 cls_cnt 0 2006.145.09:31:47.71#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.09:31:47.71#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.09:31:47.71#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.09:31:47.73#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.09:31:47.77#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.09:31:47.77#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.09:31:47.77#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.09:31:47.77#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.09:31:47.77$vck44/va=7,4 2006.145.09:31:47.77#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.09:31:47.77#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.09:31:47.77#ibcon#ireg 11 cls_cnt 2 2006.145.09:31:47.77#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.09:31:47.83#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.09:31:47.83#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.09:31:47.85#ibcon#[25=AT07-04\r\n] 2006.145.09:31:47.88#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.09:31:47.88#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.09:31:47.88#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.09:31:47.88#ibcon#ireg 7 cls_cnt 0 2006.145.09:31:47.88#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.09:31:48.00#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.09:31:48.00#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.09:31:48.02#ibcon#[25=USB\r\n] 2006.145.09:31:48.05#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.09:31:48.05#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.09:31:48.05#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.09:31:48.05#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.09:31:48.05$vck44/valo=8,884.99 2006.145.09:31:48.05#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.09:31:48.05#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.09:31:48.05#ibcon#ireg 17 cls_cnt 0 2006.145.09:31:48.05#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.09:31:48.05#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.09:31:48.05#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.09:31:48.07#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.09:31:48.11#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.09:31:48.11#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.09:31:48.11#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.09:31:48.11#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.09:31:48.11$vck44/va=8,4 2006.145.09:31:48.11#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.09:31:48.11#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.09:31:48.11#ibcon#ireg 11 cls_cnt 2 2006.145.09:31:48.11#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.09:31:48.17#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.09:31:48.17#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.09:31:48.19#ibcon#[25=AT08-04\r\n] 2006.145.09:31:48.22#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.09:31:48.22#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.09:31:48.22#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.09:31:48.22#ibcon#ireg 7 cls_cnt 0 2006.145.09:31:48.22#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.09:31:48.34#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.09:31:48.34#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.09:31:48.36#ibcon#[25=USB\r\n] 2006.145.09:31:48.39#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.09:31:48.39#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.09:31:48.39#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.09:31:48.39#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.09:31:48.39$vck44/vblo=1,629.99 2006.145.09:31:48.39#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.09:31:48.39#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.09:31:48.39#ibcon#ireg 17 cls_cnt 0 2006.145.09:31:48.39#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.09:31:48.39#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.09:31:48.39#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.09:31:48.42#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.09:31:48.45#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.09:31:48.45#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.09:31:48.45#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.09:31:48.45#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.09:31:48.45$vck44/vb=1,3 2006.145.09:31:48.45#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.09:31:48.45#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.09:31:48.45#ibcon#ireg 11 cls_cnt 2 2006.145.09:31:48.45#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.09:31:48.45#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.09:31:48.45#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.09:31:48.47#ibcon#[27=AT01-03\r\n] 2006.145.09:31:48.50#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.09:31:48.50#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.09:31:48.50#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.09:31:48.50#ibcon#ireg 7 cls_cnt 0 2006.145.09:31:48.50#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.09:31:48.62#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.09:31:48.62#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.09:31:48.64#ibcon#[27=USB\r\n] 2006.145.09:31:48.67#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.09:31:48.67#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.09:31:48.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.09:31:48.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.09:31:48.67$vck44/vblo=2,634.99 2006.145.09:31:48.67#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.09:31:48.67#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.09:31:48.67#ibcon#ireg 17 cls_cnt 0 2006.145.09:31:48.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.09:31:48.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.09:31:48.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.09:31:48.69#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.09:31:48.73#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.09:31:48.73#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.09:31:48.73#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.09:31:48.73#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.09:31:48.73$vck44/vb=2,4 2006.145.09:31:48.73#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.09:31:48.73#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.09:31:48.73#ibcon#ireg 11 cls_cnt 2 2006.145.09:31:48.73#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.09:31:48.79#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.09:31:48.79#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.09:31:48.81#ibcon#[27=AT02-04\r\n] 2006.145.09:31:48.84#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.09:31:48.84#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.09:31:48.84#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.09:31:48.84#ibcon#ireg 7 cls_cnt 0 2006.145.09:31:48.84#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.09:31:48.96#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.09:31:48.96#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.09:31:48.98#ibcon#[27=USB\r\n] 2006.145.09:31:49.01#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.09:31:49.01#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.09:31:49.01#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.09:31:49.01#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.09:31:49.01$vck44/vblo=3,649.99 2006.145.09:31:49.01#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.09:31:49.01#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.09:31:49.01#ibcon#ireg 17 cls_cnt 0 2006.145.09:31:49.01#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.09:31:49.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.09:31:49.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.09:31:49.03#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.09:31:49.07#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.09:31:49.07#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.09:31:49.07#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.09:31:49.07#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.09:31:49.07$vck44/vb=3,4 2006.145.09:31:49.07#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.09:31:49.07#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.09:31:49.07#ibcon#ireg 11 cls_cnt 2 2006.145.09:31:49.07#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.09:31:49.13#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.09:31:49.13#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.09:31:49.15#ibcon#[27=AT03-04\r\n] 2006.145.09:31:49.18#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.09:31:49.18#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.09:31:49.18#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.09:31:49.18#ibcon#ireg 7 cls_cnt 0 2006.145.09:31:49.18#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.09:31:49.30#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.09:31:49.30#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.09:31:49.32#ibcon#[27=USB\r\n] 2006.145.09:31:49.35#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.09:31:49.35#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.09:31:49.35#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.09:31:49.35#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.09:31:49.35$vck44/vblo=4,679.99 2006.145.09:31:49.35#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.09:31:49.35#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.09:31:49.35#ibcon#ireg 17 cls_cnt 0 2006.145.09:31:49.35#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.09:31:49.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.09:31:49.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.09:31:49.37#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.09:31:49.41#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.09:31:49.41#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.09:31:49.41#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.09:31:49.41#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.09:31:49.41$vck44/vb=4,4 2006.145.09:31:49.41#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.09:31:49.41#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.09:31:49.41#ibcon#ireg 11 cls_cnt 2 2006.145.09:31:49.41#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.09:31:49.47#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.09:31:49.47#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.09:31:49.49#ibcon#[27=AT04-04\r\n] 2006.145.09:31:49.52#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.09:31:49.52#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.09:31:49.52#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.09:31:49.52#ibcon#ireg 7 cls_cnt 0 2006.145.09:31:49.52#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.09:31:49.64#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.09:31:49.64#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.09:31:49.66#ibcon#[27=USB\r\n] 2006.145.09:31:49.69#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.09:31:49.69#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.09:31:49.69#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.09:31:49.69#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.09:31:49.69$vck44/vblo=5,709.99 2006.145.09:31:49.69#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.09:31:49.69#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.09:31:49.69#ibcon#ireg 17 cls_cnt 0 2006.145.09:31:49.69#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.09:31:49.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.09:31:49.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.09:31:49.71#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.09:31:49.75#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.09:31:49.75#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.09:31:49.75#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.09:31:49.75#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.09:31:49.75$vck44/vb=5,4 2006.145.09:31:49.75#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.09:31:49.75#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.09:31:49.75#ibcon#ireg 11 cls_cnt 2 2006.145.09:31:49.75#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.09:31:49.81#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.09:31:49.81#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.09:31:49.83#ibcon#[27=AT05-04\r\n] 2006.145.09:31:49.86#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.09:31:49.86#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.09:31:49.86#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.09:31:49.86#ibcon#ireg 7 cls_cnt 0 2006.145.09:31:49.86#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.09:31:49.98#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.09:31:49.98#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.09:31:50.00#ibcon#[27=USB\r\n] 2006.145.09:31:50.03#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.09:31:50.03#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.09:31:50.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.09:31:50.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.09:31:50.03$vck44/vblo=6,719.99 2006.145.09:31:50.03#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.09:31:50.03#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.09:31:50.03#ibcon#ireg 17 cls_cnt 0 2006.145.09:31:50.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.09:31:50.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.09:31:50.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.09:31:50.05#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.09:31:50.09#abcon#<5=/05 3.8 6.9 17.95 651018.5\r\n> 2006.145.09:31:50.09#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.09:31:50.09#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.09:31:50.09#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.09:31:50.09#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.09:31:50.09$vck44/vb=6,4 2006.145.09:31:50.09#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.09:31:50.09#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.09:31:50.09#ibcon#ireg 11 cls_cnt 2 2006.145.09:31:50.09#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.09:31:50.11#abcon#{5=INTERFACE CLEAR} 2006.145.09:31:50.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.09:31:50.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.09:31:50.17#ibcon#[27=AT06-04\r\n] 2006.145.09:31:50.17#abcon#[5=S1D000X0/0*\r\n] 2006.145.09:31:50.20#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.09:31:50.20#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.09:31:50.20#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.09:31:50.20#ibcon#ireg 7 cls_cnt 0 2006.145.09:31:50.20#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.09:31:50.32#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.09:31:50.32#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.09:31:50.34#ibcon#[27=USB\r\n] 2006.145.09:31:50.37#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.09:31:50.37#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.09:31:50.37#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.09:31:50.37#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.09:31:50.37$vck44/vblo=7,734.99 2006.145.09:31:50.37#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.09:31:50.37#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.09:31:50.37#ibcon#ireg 17 cls_cnt 0 2006.145.09:31:50.37#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.09:31:50.37#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.09:31:50.37#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.09:31:50.39#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.09:31:50.43#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.09:31:50.43#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.09:31:50.43#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.09:31:50.43#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.09:31:50.43$vck44/vb=7,4 2006.145.09:31:50.43#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.09:31:50.43#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.09:31:50.43#ibcon#ireg 11 cls_cnt 2 2006.145.09:31:50.43#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.09:31:50.49#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.09:31:50.49#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.09:31:50.51#ibcon#[27=AT07-04\r\n] 2006.145.09:31:50.54#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.09:31:50.54#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.09:31:50.54#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.09:31:50.54#ibcon#ireg 7 cls_cnt 0 2006.145.09:31:50.54#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.09:31:50.66#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.09:31:50.66#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.09:31:50.68#ibcon#[27=USB\r\n] 2006.145.09:31:50.71#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.09:31:50.71#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.09:31:50.71#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.09:31:50.71#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.09:31:50.71$vck44/vblo=8,744.99 2006.145.09:31:50.71#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.09:31:50.71#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.09:31:50.71#ibcon#ireg 17 cls_cnt 0 2006.145.09:31:50.71#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.09:31:50.71#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.09:31:50.71#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.09:31:50.73#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.09:31:50.77#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.09:31:50.77#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.09:31:50.77#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.09:31:50.77#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.09:31:50.77$vck44/vb=8,4 2006.145.09:31:50.77#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.09:31:50.77#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.09:31:50.77#ibcon#ireg 11 cls_cnt 2 2006.145.09:31:50.77#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.09:31:50.83#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.09:31:50.83#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.09:31:50.85#ibcon#[27=AT08-04\r\n] 2006.145.09:31:50.88#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.09:31:50.88#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.09:31:50.88#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.09:31:50.88#ibcon#ireg 7 cls_cnt 0 2006.145.09:31:50.88#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.09:31:51.00#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.09:31:51.00#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.09:31:51.02#ibcon#[27=USB\r\n] 2006.145.09:31:51.05#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.09:31:51.05#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.09:31:51.05#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.09:31:51.05#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.09:31:51.05$vck44/vabw=wide 2006.145.09:31:51.05#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.09:31:51.05#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.09:31:51.05#ibcon#ireg 8 cls_cnt 0 2006.145.09:31:51.05#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.09:31:51.05#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.09:31:51.05#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.09:31:51.07#ibcon#[25=BW32\r\n] 2006.145.09:31:51.10#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.09:31:51.10#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.09:31:51.10#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.09:31:51.10#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.09:31:51.10$vck44/vbbw=wide 2006.145.09:31:51.10#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.09:31:51.10#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.09:31:51.10#ibcon#ireg 8 cls_cnt 0 2006.145.09:31:51.10#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:31:51.17#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:31:51.17#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:31:51.19#ibcon#[27=BW32\r\n] 2006.145.09:31:51.22#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:31:51.22#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:31:51.22#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.09:31:51.22#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.09:31:51.22$setupk4/ifdk4 2006.145.09:31:51.22$ifdk4/lo= 2006.145.09:31:51.22$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.09:31:51.22$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.09:31:51.22$ifdk4/patch= 2006.145.09:31:51.22$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.09:31:51.22$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.09:31:51.23$setupk4/!*+20s 2006.145.09:32:01.14#trakl#Source acquired 2006.145.09:32:01.14#flagr#flagr/antenna,acquired 2006.145.09:32:05.73$setupk4/"tpicd 2006.145.09:32:05.73$setupk4/echo=off 2006.145.09:32:05.73$setupk4/xlog=off 2006.145.09:32:05.73:!2006.145.09:36:51 2006.145.09:36:51.00:preob 2006.145.09:36:51.14/onsource/TRACKING 2006.145.09:36:51.14:!2006.145.09:37:01 2006.145.09:37:01.00:"tape 2006.145.09:37:01.00:"st=record 2006.145.09:37:01.00:data_valid=on 2006.145.09:37:01.00:midob 2006.145.09:37:01.14/onsource/TRACKING 2006.145.09:37:01.14/wx/17.90,1018.7,67 2006.145.09:37:01.32/cable/+6.5437E-03 2006.145.09:37:02.41/va/01,08,usb,yes,30,32 2006.145.09:37:02.41/va/02,07,usb,yes,32,33 2006.145.09:37:02.41/va/03,08,usb,yes,29,30 2006.145.09:37:02.41/va/04,07,usb,yes,33,35 2006.145.09:37:02.41/va/05,04,usb,yes,29,30 2006.145.09:37:02.41/va/06,04,usb,yes,32,32 2006.145.09:37:02.41/va/07,04,usb,yes,33,34 2006.145.09:37:02.41/va/08,04,usb,yes,28,34 2006.145.09:37:02.64/valo/01,524.99,yes,locked 2006.145.09:37:02.64/valo/02,534.99,yes,locked 2006.145.09:37:02.64/valo/03,564.99,yes,locked 2006.145.09:37:02.64/valo/04,624.99,yes,locked 2006.145.09:37:02.64/valo/05,734.99,yes,locked 2006.145.09:37:02.64/valo/06,814.99,yes,locked 2006.145.09:37:02.64/valo/07,864.99,yes,locked 2006.145.09:37:02.64/valo/08,884.99,yes,locked 2006.145.09:37:03.73/vb/01,03,usb,yes,37,34 2006.145.09:37:03.73/vb/02,04,usb,yes,32,32 2006.145.09:37:03.73/vb/03,04,usb,yes,29,32 2006.145.09:37:03.73/vb/04,04,usb,yes,34,33 2006.145.09:37:03.73/vb/05,04,usb,yes,26,29 2006.145.09:37:03.73/vb/06,04,usb,yes,31,27 2006.145.09:37:03.73/vb/07,04,usb,yes,30,30 2006.145.09:37:03.73/vb/08,04,usb,yes,28,31 2006.145.09:37:03.96/vblo/01,629.99,yes,locked 2006.145.09:37:03.96/vblo/02,634.99,yes,locked 2006.145.09:37:03.96/vblo/03,649.99,yes,locked 2006.145.09:37:03.96/vblo/04,679.99,yes,locked 2006.145.09:37:03.96/vblo/05,709.99,yes,locked 2006.145.09:37:03.96/vblo/06,719.99,yes,locked 2006.145.09:37:03.96/vblo/07,734.99,yes,locked 2006.145.09:37:03.96/vblo/08,744.99,yes,locked 2006.145.09:37:04.11/vabw/8 2006.145.09:37:04.26/vbbw/8 2006.145.09:37:04.35/xfe/off,on,15.2 2006.145.09:37:04.73/ifatt/23,28,28,28 2006.145.09:37:05.07/fmout-gps/S +4.9E-08 2006.145.09:37:05.11:!2006.145.09:38:11 2006.145.09:38:11.01:data_valid=off 2006.145.09:38:11.02:"et 2006.145.09:38:11.02:!+3s 2006.145.09:38:14.03:"tape 2006.145.09:38:14.04:postob 2006.145.09:38:14.10/cable/+6.5434E-03 2006.145.09:38:14.11/wx/17.89,1018.6,66 2006.145.09:38:14.18/fmout-gps/S +5.0E-08 2006.145.09:38:14.18:scan_name=145-0940,jd0605,100 2006.145.09:38:14.19:source=1334-127,133739.78,-125724.7,2000.0,ccw 2006.145.09:38:16.13#flagr#flagr/antenna,new-source 2006.145.09:38:16.14:checkk5 2006.145.09:38:16.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.09:38:17.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.09:38:17.43/chk_autoobs//k5ts3/ autoobs is running! 2006.145.09:38:17.87/chk_autoobs//k5ts4/ autoobs is running! 2006.145.09:38:18.30/chk_obsdata//k5ts1/T1450937??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.09:38:18.73/chk_obsdata//k5ts2/T1450937??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.09:38:19.16/chk_obsdata//k5ts3/T1450937??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.09:38:19.60/chk_obsdata//k5ts4/T1450937??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.09:38:20.35/k5log//k5ts1_log_newline 2006.145.09:38:21.10/k5log//k5ts2_log_newline 2006.145.09:38:21.83/k5log//k5ts3_log_newline 2006.145.09:38:22.60/k5log//k5ts4_log_newline 2006.145.09:38:22.63/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.09:38:22.63:setupk4=1 2006.145.09:38:22.63$setupk4/echo=on 2006.145.09:38:22.63$setupk4/pcalon 2006.145.09:38:22.63$pcalon/"no phase cal control is implemented here 2006.145.09:38:22.63$setupk4/"tpicd=stop 2006.145.09:38:22.63$setupk4/"rec=synch_on 2006.145.09:38:22.63$setupk4/"rec_mode=128 2006.145.09:38:22.63$setupk4/!* 2006.145.09:38:22.63$setupk4/recpk4 2006.145.09:38:22.63$recpk4/recpatch= 2006.145.09:38:22.63$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.09:38:22.63$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.09:38:22.63$setupk4/vck44 2006.145.09:38:22.63$vck44/valo=1,524.99 2006.145.09:38:22.63#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.09:38:22.63#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.09:38:22.63#ibcon#ireg 17 cls_cnt 0 2006.145.09:38:22.63#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:38:22.63#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:38:22.63#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:38:22.67#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.09:38:22.72#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:38:22.72#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:38:22.72#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.09:38:22.72#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.09:38:22.72$vck44/va=1,8 2006.145.09:38:22.72#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.09:38:22.72#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.09:38:22.72#ibcon#ireg 11 cls_cnt 2 2006.145.09:38:22.72#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.09:38:22.72#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.09:38:22.72#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.09:38:22.74#ibcon#[25=AT01-08\r\n] 2006.145.09:38:22.77#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.09:38:22.77#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.09:38:22.77#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.09:38:22.77#ibcon#ireg 7 cls_cnt 0 2006.145.09:38:22.77#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.09:38:22.89#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.09:38:22.89#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.09:38:22.91#ibcon#[25=USB\r\n] 2006.145.09:38:22.94#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.09:38:22.94#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.09:38:22.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.09:38:22.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.09:38:22.94$vck44/valo=2,534.99 2006.145.09:38:22.94#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.09:38:22.94#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.09:38:22.94#ibcon#ireg 17 cls_cnt 0 2006.145.09:38:22.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.09:38:22.94#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.09:38:22.94#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.09:38:22.98#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.09:38:23.01#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.09:38:23.01#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.09:38:23.01#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.09:38:23.01#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.09:38:23.01$vck44/va=2,7 2006.145.09:38:23.01#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.09:38:23.01#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.09:38:23.01#ibcon#ireg 11 cls_cnt 2 2006.145.09:38:23.01#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.09:38:23.06#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.09:38:23.06#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.09:38:23.08#ibcon#[25=AT02-07\r\n] 2006.145.09:38:23.11#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.09:38:23.11#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.09:38:23.11#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.09:38:23.11#ibcon#ireg 7 cls_cnt 0 2006.145.09:38:23.11#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.09:38:23.23#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.09:38:23.23#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.09:38:23.25#ibcon#[25=USB\r\n] 2006.145.09:38:23.28#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.09:38:23.28#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.09:38:23.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.09:38:23.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.09:38:23.28$vck44/valo=3,564.99 2006.145.09:38:23.28#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.09:38:23.28#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.09:38:23.28#ibcon#ireg 17 cls_cnt 0 2006.145.09:38:23.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.09:38:23.28#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.09:38:23.28#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.09:38:23.30#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.09:38:23.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.09:38:23.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.09:38:23.34#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.09:38:23.34#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.09:38:23.34$vck44/va=3,8 2006.145.09:38:23.34#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.09:38:23.34#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.09:38:23.34#ibcon#ireg 11 cls_cnt 2 2006.145.09:38:23.34#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.09:38:23.40#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.09:38:23.40#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.09:38:23.42#ibcon#[25=AT03-08\r\n] 2006.145.09:38:23.45#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.09:38:23.45#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.09:38:23.45#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.09:38:23.45#ibcon#ireg 7 cls_cnt 0 2006.145.09:38:23.45#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.09:38:23.57#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.09:38:23.57#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.09:38:23.59#ibcon#[25=USB\r\n] 2006.145.09:38:23.62#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.09:38:23.62#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.09:38:23.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.09:38:23.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.09:38:23.62$vck44/valo=4,624.99 2006.145.09:38:23.62#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.09:38:23.62#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.09:38:23.62#ibcon#ireg 17 cls_cnt 0 2006.145.09:38:23.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:38:23.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:38:23.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:38:23.64#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.09:38:23.68#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:38:23.68#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:38:23.68#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.09:38:23.68#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.09:38:23.68$vck44/va=4,7 2006.145.09:38:23.68#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.09:38:23.68#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.09:38:23.68#ibcon#ireg 11 cls_cnt 2 2006.145.09:38:23.68#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:38:23.74#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:38:23.74#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:38:23.76#ibcon#[25=AT04-07\r\n] 2006.145.09:38:23.79#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:38:23.79#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:38:23.79#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.09:38:23.79#ibcon#ireg 7 cls_cnt 0 2006.145.09:38:23.79#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:38:23.91#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:38:23.91#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:38:23.93#ibcon#[25=USB\r\n] 2006.145.09:38:23.96#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:38:23.96#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:38:23.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.09:38:23.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.09:38:23.96$vck44/valo=5,734.99 2006.145.09:38:23.96#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.09:38:23.96#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.09:38:23.96#ibcon#ireg 17 cls_cnt 0 2006.145.09:38:23.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:38:23.96#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:38:23.96#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:38:23.98#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.09:38:24.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:38:24.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:38:24.02#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.09:38:24.02#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.09:38:24.02$vck44/va=5,4 2006.145.09:38:24.02#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.09:38:24.02#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.09:38:24.02#ibcon#ireg 11 cls_cnt 2 2006.145.09:38:24.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:38:24.08#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:38:24.08#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:38:24.10#ibcon#[25=AT05-04\r\n] 2006.145.09:38:24.14#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:38:24.14#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:38:24.14#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.09:38:24.14#ibcon#ireg 7 cls_cnt 0 2006.145.09:38:24.14#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:38:24.25#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:38:24.25#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:38:24.27#ibcon#[25=USB\r\n] 2006.145.09:38:24.30#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:38:24.30#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:38:24.30#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.09:38:24.30#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.09:38:24.30$vck44/valo=6,814.99 2006.145.09:38:24.30#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.09:38:24.30#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.09:38:24.30#ibcon#ireg 17 cls_cnt 0 2006.145.09:38:24.30#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:38:24.30#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:38:24.30#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:38:24.33#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.09:38:24.37#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:38:24.37#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:38:24.37#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.09:38:24.37#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.09:38:24.37$vck44/va=6,4 2006.145.09:38:24.37#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.09:38:24.37#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.09:38:24.37#ibcon#ireg 11 cls_cnt 2 2006.145.09:38:24.37#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:38:24.42#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:38:24.42#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:38:24.44#ibcon#[25=AT06-04\r\n] 2006.145.09:38:24.47#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:38:24.47#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:38:24.47#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.09:38:24.47#ibcon#ireg 7 cls_cnt 0 2006.145.09:38:24.47#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:38:24.59#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:38:24.59#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:38:24.61#ibcon#[25=USB\r\n] 2006.145.09:38:24.64#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:38:24.64#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:38:24.64#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.09:38:24.64#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.09:38:24.64$vck44/valo=7,864.99 2006.145.09:38:24.64#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.09:38:24.64#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.09:38:24.64#ibcon#ireg 17 cls_cnt 0 2006.145.09:38:24.64#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:38:24.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:38:24.64#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:38:24.66#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.09:38:24.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:38:24.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:38:24.70#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.09:38:24.70#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.09:38:24.70$vck44/va=7,4 2006.145.09:38:24.70#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.09:38:24.70#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.09:38:24.70#ibcon#ireg 11 cls_cnt 2 2006.145.09:38:24.70#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.09:38:24.76#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.09:38:24.76#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.09:38:24.78#ibcon#[25=AT07-04\r\n] 2006.145.09:38:24.81#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.09:38:24.81#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.09:38:24.81#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.09:38:24.81#ibcon#ireg 7 cls_cnt 0 2006.145.09:38:24.81#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.09:38:24.93#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.09:38:24.93#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.09:38:24.95#ibcon#[25=USB\r\n] 2006.145.09:38:24.98#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.09:38:24.98#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.09:38:24.98#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.09:38:24.98#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.09:38:24.98$vck44/valo=8,884.99 2006.145.09:38:24.98#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.09:38:24.98#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.09:38:24.98#ibcon#ireg 17 cls_cnt 0 2006.145.09:38:24.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:38:24.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:38:24.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:38:25.00#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.09:38:25.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:38:25.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:38:25.04#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.09:38:25.04#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.09:38:25.04$vck44/va=8,4 2006.145.09:38:25.04#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.09:38:25.04#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.09:38:25.04#ibcon#ireg 11 cls_cnt 2 2006.145.09:38:25.04#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.09:38:25.10#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.09:38:25.10#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.09:38:25.12#ibcon#[25=AT08-04\r\n] 2006.145.09:38:25.15#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.09:38:25.15#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.09:38:25.15#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.09:38:25.15#ibcon#ireg 7 cls_cnt 0 2006.145.09:38:25.15#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.09:38:25.27#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.09:38:25.27#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.09:38:25.29#ibcon#[25=USB\r\n] 2006.145.09:38:25.32#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.09:38:25.32#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.09:38:25.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.09:38:25.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.09:38:25.32$vck44/vblo=1,629.99 2006.145.09:38:25.32#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.09:38:25.32#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.09:38:25.32#ibcon#ireg 17 cls_cnt 0 2006.145.09:38:25.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.09:38:25.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.09:38:25.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.09:38:25.34#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.09:38:25.39#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.09:38:25.39#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.09:38:25.39#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.09:38:25.39#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.09:38:25.39$vck44/vb=1,3 2006.145.09:38:25.39#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.09:38:25.39#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.09:38:25.39#ibcon#ireg 11 cls_cnt 2 2006.145.09:38:25.39#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.09:38:25.39#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.09:38:25.39#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.09:38:25.41#ibcon#[27=AT01-03\r\n] 2006.145.09:38:25.44#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.09:38:25.44#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.09:38:25.44#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.09:38:25.44#ibcon#ireg 7 cls_cnt 0 2006.145.09:38:25.44#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.09:38:25.56#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.09:38:25.56#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.09:38:25.58#ibcon#[27=USB\r\n] 2006.145.09:38:25.61#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.09:38:25.61#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.09:38:25.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.09:38:25.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.09:38:25.61$vck44/vblo=2,634.99 2006.145.09:38:25.61#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.09:38:25.61#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.09:38:25.61#ibcon#ireg 17 cls_cnt 0 2006.145.09:38:25.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:38:25.61#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:38:25.61#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:38:25.63#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.09:38:25.67#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:38:25.67#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:38:25.67#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.09:38:25.67#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.09:38:25.67$vck44/vb=2,4 2006.145.09:38:25.67#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.09:38:25.67#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.09:38:25.67#ibcon#ireg 11 cls_cnt 2 2006.145.09:38:25.67#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.09:38:25.73#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.09:38:25.73#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.09:38:25.75#ibcon#[27=AT02-04\r\n] 2006.145.09:38:25.78#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.09:38:25.78#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.09:38:25.78#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.09:38:25.78#ibcon#ireg 7 cls_cnt 0 2006.145.09:38:25.78#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.09:38:25.90#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.09:38:25.90#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.09:38:25.92#ibcon#[27=USB\r\n] 2006.145.09:38:25.95#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.09:38:25.95#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.09:38:25.95#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.09:38:25.95#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.09:38:25.95$vck44/vblo=3,649.99 2006.145.09:38:25.95#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.09:38:25.95#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.09:38:25.95#ibcon#ireg 17 cls_cnt 0 2006.145.09:38:25.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.09:38:25.95#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.09:38:25.95#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.09:38:25.97#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.09:38:26.01#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.09:38:26.01#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.09:38:26.01#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.09:38:26.01#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.09:38:26.01$vck44/vb=3,4 2006.145.09:38:26.01#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.09:38:26.01#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.09:38:26.01#ibcon#ireg 11 cls_cnt 2 2006.145.09:38:26.01#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.09:38:26.07#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.09:38:26.07#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.09:38:26.09#ibcon#[27=AT03-04\r\n] 2006.145.09:38:26.12#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.09:38:26.12#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.09:38:26.12#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.09:38:26.12#ibcon#ireg 7 cls_cnt 0 2006.145.09:38:26.12#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.09:38:26.24#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.09:38:26.24#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.09:38:26.26#ibcon#[27=USB\r\n] 2006.145.09:38:26.29#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.09:38:26.29#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.09:38:26.29#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.09:38:26.29#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.09:38:26.29$vck44/vblo=4,679.99 2006.145.09:38:26.29#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.09:38:26.29#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.09:38:26.29#ibcon#ireg 17 cls_cnt 0 2006.145.09:38:26.29#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.09:38:26.29#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.09:38:26.29#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.09:38:26.31#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.09:38:26.35#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.09:38:26.35#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.09:38:26.35#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.09:38:26.35#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.09:38:26.35$vck44/vb=4,4 2006.145.09:38:26.35#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.09:38:26.35#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.09:38:26.35#ibcon#ireg 11 cls_cnt 2 2006.145.09:38:26.35#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.09:38:26.41#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.09:38:26.41#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.09:38:26.43#ibcon#[27=AT04-04\r\n] 2006.145.09:38:26.46#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.09:38:26.46#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.09:38:26.46#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.09:38:26.46#ibcon#ireg 7 cls_cnt 0 2006.145.09:38:26.46#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.09:38:26.58#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.09:38:26.58#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.09:38:26.60#ibcon#[27=USB\r\n] 2006.145.09:38:26.63#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.09:38:26.63#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.09:38:26.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.09:38:26.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.09:38:26.63$vck44/vblo=5,709.99 2006.145.09:38:26.63#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.09:38:26.63#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.09:38:26.63#ibcon#ireg 17 cls_cnt 0 2006.145.09:38:26.63#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:38:26.63#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:38:26.63#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:38:26.65#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.09:38:26.69#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:38:26.69#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:38:26.69#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.09:38:26.69#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.09:38:26.69$vck44/vb=5,4 2006.145.09:38:26.69#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.09:38:26.69#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.09:38:26.69#ibcon#ireg 11 cls_cnt 2 2006.145.09:38:26.69#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:38:26.75#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:38:26.75#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:38:26.77#ibcon#[27=AT05-04\r\n] 2006.145.09:38:26.80#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:38:26.80#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:38:26.80#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.09:38:26.80#ibcon#ireg 7 cls_cnt 0 2006.145.09:38:26.80#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:38:26.92#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:38:26.92#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:38:26.94#ibcon#[27=USB\r\n] 2006.145.09:38:26.97#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:38:26.97#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:38:26.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.09:38:26.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.09:38:26.97$vck44/vblo=6,719.99 2006.145.09:38:26.97#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.09:38:26.97#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.09:38:26.97#ibcon#ireg 17 cls_cnt 0 2006.145.09:38:26.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:38:26.97#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:38:26.97#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:38:26.99#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.09:38:27.03#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:38:27.03#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:38:27.03#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.09:38:27.03#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.09:38:27.03$vck44/vb=6,4 2006.145.09:38:27.03#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.09:38:27.03#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.09:38:27.03#ibcon#ireg 11 cls_cnt 2 2006.145.09:38:27.03#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:38:27.09#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:38:27.09#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:38:27.11#ibcon#[27=AT06-04\r\n] 2006.145.09:38:27.14#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:38:27.14#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:38:27.14#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.09:38:27.14#ibcon#ireg 7 cls_cnt 0 2006.145.09:38:27.14#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:38:27.26#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:38:27.26#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:38:27.28#ibcon#[27=USB\r\n] 2006.145.09:38:27.31#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:38:27.31#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:38:27.31#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.09:38:27.31#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.09:38:27.31$vck44/vblo=7,734.99 2006.145.09:38:27.31#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.09:38:27.31#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.09:38:27.31#ibcon#ireg 17 cls_cnt 0 2006.145.09:38:27.31#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:38:27.31#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:38:27.31#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:38:27.33#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.09:38:27.37#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:38:27.37#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:38:27.37#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.09:38:27.37#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.09:38:27.37$vck44/vb=7,4 2006.145.09:38:27.37#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.09:38:27.37#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.09:38:27.37#ibcon#ireg 11 cls_cnt 2 2006.145.09:38:27.37#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:38:27.43#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:38:27.43#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:38:27.45#ibcon#[27=AT07-04\r\n] 2006.145.09:38:27.48#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:38:27.48#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:38:27.48#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.09:38:27.48#ibcon#ireg 7 cls_cnt 0 2006.145.09:38:27.48#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:38:27.60#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:38:27.60#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:38:27.62#ibcon#[27=USB\r\n] 2006.145.09:38:27.65#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:38:27.65#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:38:27.65#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.09:38:27.65#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.09:38:27.65$vck44/vblo=8,744.99 2006.145.09:38:27.65#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.09:38:27.65#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.09:38:27.65#ibcon#ireg 17 cls_cnt 0 2006.145.09:38:27.65#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:38:27.65#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:38:27.65#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:38:27.67#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.09:38:27.71#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:38:27.71#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:38:27.71#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.09:38:27.71#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.09:38:27.71$vck44/vb=8,4 2006.145.09:38:27.71#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.09:38:27.71#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.09:38:27.71#ibcon#ireg 11 cls_cnt 2 2006.145.09:38:27.71#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.09:38:27.77#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.09:38:27.77#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.09:38:27.79#ibcon#[27=AT08-04\r\n] 2006.145.09:38:27.82#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.09:38:27.82#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.09:38:27.82#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.09:38:27.82#ibcon#ireg 7 cls_cnt 0 2006.145.09:38:27.82#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.09:38:27.94#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.09:38:27.94#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.09:38:27.96#ibcon#[27=USB\r\n] 2006.145.09:38:27.99#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.09:38:27.99#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.09:38:27.99#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.09:38:27.99#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.09:38:27.99$vck44/vabw=wide 2006.145.09:38:27.99#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.09:38:27.99#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.09:38:27.99#ibcon#ireg 8 cls_cnt 0 2006.145.09:38:27.99#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:38:27.99#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:38:27.99#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:38:28.01#ibcon#[25=BW32\r\n] 2006.145.09:38:28.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:38:28.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:38:28.04#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.09:38:28.04#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.09:38:28.04$vck44/vbbw=wide 2006.145.09:38:28.04#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.09:38:28.04#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.09:38:28.04#ibcon#ireg 8 cls_cnt 0 2006.145.09:38:28.04#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.09:38:28.11#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.09:38:28.11#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.09:38:28.13#ibcon#[27=BW32\r\n] 2006.145.09:38:28.16#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.09:38:28.16#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.09:38:28.16#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.09:38:28.16#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.09:38:28.16$setupk4/ifdk4 2006.145.09:38:28.16$ifdk4/lo= 2006.145.09:38:28.16$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.09:38:28.16$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.09:38:28.16$ifdk4/patch= 2006.145.09:38:28.16$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.09:38:28.16$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.09:38:28.16$setupk4/!*+20s 2006.145.09:38:29.55#abcon#<5=/05 3.6 6.8 17.89 661018.7\r\n> 2006.145.09:38:29.57#abcon#{5=INTERFACE CLEAR} 2006.145.09:38:29.63#abcon#[5=S1D000X0/0*\r\n] 2006.145.09:38:39.72#abcon#<5=/05 3.6 6.8 17.89 671018.6\r\n> 2006.145.09:38:39.74#abcon#{5=INTERFACE CLEAR} 2006.145.09:38:39.80#abcon#[5=S1D000X0/0*\r\n] 2006.145.09:38:42.64$setupk4/"tpicd 2006.145.09:38:42.64$setupk4/echo=off 2006.145.09:38:42.64$setupk4/xlog=off 2006.145.09:38:42.64:!2006.145.09:40:27 2006.145.09:38:59.13#trakl#Source acquired 2006.145.09:38:59.13#flagr#flagr/antenna,acquired 2006.145.09:40:27.00:preob 2006.145.09:40:27.14/onsource/TRACKING 2006.145.09:40:27.14:!2006.145.09:40:37 2006.145.09:40:37.00:"tape 2006.145.09:40:37.00:"st=record 2006.145.09:40:37.00:data_valid=on 2006.145.09:40:37.00:midob 2006.145.09:40:38.14/onsource/TRACKING 2006.145.09:40:38.14/wx/17.87,1018.7,67 2006.145.09:40:38.24/cable/+6.5443E-03 2006.145.09:40:39.33/va/01,08,usb,yes,29,31 2006.145.09:40:39.33/va/02,07,usb,yes,31,32 2006.145.09:40:39.33/va/03,08,usb,yes,28,29 2006.145.09:40:39.33/va/04,07,usb,yes,32,34 2006.145.09:40:39.33/va/05,04,usb,yes,28,28 2006.145.09:40:39.33/va/06,04,usb,yes,31,31 2006.145.09:40:39.33/va/07,04,usb,yes,31,33 2006.145.09:40:39.33/va/08,04,usb,yes,27,32 2006.145.09:40:39.56/valo/01,524.99,yes,locked 2006.145.09:40:39.56/valo/02,534.99,yes,locked 2006.145.09:40:39.56/valo/03,564.99,yes,locked 2006.145.09:40:39.56/valo/04,624.99,yes,locked 2006.145.09:40:39.56/valo/05,734.99,yes,locked 2006.145.09:40:39.56/valo/06,814.99,yes,locked 2006.145.09:40:39.56/valo/07,864.99,yes,locked 2006.145.09:40:39.56/valo/08,884.99,yes,locked 2006.145.09:40:40.65/vb/01,03,usb,yes,36,34 2006.145.09:40:40.65/vb/02,04,usb,yes,32,31 2006.145.09:40:40.65/vb/03,04,usb,yes,29,31 2006.145.09:40:40.65/vb/04,04,usb,yes,33,32 2006.145.09:40:40.65/vb/05,04,usb,yes,25,28 2006.145.09:40:40.65/vb/06,04,usb,yes,30,26 2006.145.09:40:40.65/vb/07,04,usb,yes,30,29 2006.145.09:40:40.65/vb/08,04,usb,yes,27,31 2006.145.09:40:40.89/vblo/01,629.99,yes,locked 2006.145.09:40:40.89/vblo/02,634.99,yes,locked 2006.145.09:40:40.89/vblo/03,649.99,yes,locked 2006.145.09:40:40.89/vblo/04,679.99,yes,locked 2006.145.09:40:40.89/vblo/05,709.99,yes,locked 2006.145.09:40:40.89/vblo/06,719.99,yes,locked 2006.145.09:40:40.89/vblo/07,734.99,yes,locked 2006.145.09:40:40.89/vblo/08,744.99,yes,locked 2006.145.09:40:41.04/vabw/8 2006.145.09:40:41.19/vbbw/8 2006.145.09:40:41.28/xfe/off,on,14.5 2006.145.09:40:41.65/ifatt/23,28,28,28 2006.145.09:40:42.07/fmout-gps/S +5.1E-08 2006.145.09:40:42.11:!2006.145.09:42:17 2006.145.09:42:17.01:data_valid=off 2006.145.09:42:17.02:"et 2006.145.09:42:17.02:!+3s 2006.145.09:42:20.03:"tape 2006.145.09:42:20.03:postob 2006.145.09:42:20.10/cable/+6.5417E-03 2006.145.09:42:20.11/wx/17.85,1018.7,66 2006.145.09:42:20.18/fmout-gps/S +5.0E-08 2006.145.09:42:20.18:scan_name=145-0943,jd0605,80 2006.145.09:42:20.19:source=3c274,123049.42,122328.0,2000.0,ccw 2006.145.09:42:22.14#flagr#flagr/antenna,new-source 2006.145.09:42:22.14:checkk5 2006.145.09:42:22.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.09:42:23.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.09:42:23.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.09:42:23.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.09:42:24.31/chk_obsdata//k5ts1/T1450940??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.09:42:24.76/chk_obsdata//k5ts2/T1450940??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.09:42:25.21/chk_obsdata//k5ts3/T1450940??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.09:42:25.65/chk_obsdata//k5ts4/T1450940??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.09:42:26.41/k5log//k5ts1_log_newline 2006.145.09:42:27.14/k5log//k5ts2_log_newline 2006.145.09:42:27.88/k5log//k5ts3_log_newline 2006.145.09:42:28.62/k5log//k5ts4_log_newline 2006.145.09:42:28.65/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.09:42:28.65:setupk4=1 2006.145.09:42:28.65$setupk4/echo=on 2006.145.09:42:28.65$setupk4/pcalon 2006.145.09:42:28.65$pcalon/"no phase cal control is implemented here 2006.145.09:42:28.65$setupk4/"tpicd=stop 2006.145.09:42:28.65$setupk4/"rec=synch_on 2006.145.09:42:28.65$setupk4/"rec_mode=128 2006.145.09:42:28.65$setupk4/!* 2006.145.09:42:28.65$setupk4/recpk4 2006.145.09:42:28.65$recpk4/recpatch= 2006.145.09:42:28.65$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.09:42:28.65$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.09:42:28.65$setupk4/vck44 2006.145.09:42:28.65$vck44/valo=1,524.99 2006.145.09:42:28.65#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.09:42:28.65#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.09:42:28.65#ibcon#ireg 17 cls_cnt 0 2006.145.09:42:28.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.09:42:28.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.09:42:28.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.09:42:28.69#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.09:42:28.74#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.09:42:28.74#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.09:42:28.74#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.09:42:28.74#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.09:42:28.74$vck44/va=1,8 2006.145.09:42:28.74#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.09:42:28.74#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.09:42:28.74#ibcon#ireg 11 cls_cnt 2 2006.145.09:42:28.74#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.09:42:28.74#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.09:42:28.74#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.09:42:28.76#ibcon#[25=AT01-08\r\n] 2006.145.09:42:28.79#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.09:42:28.79#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.09:42:28.79#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.09:42:28.79#ibcon#ireg 7 cls_cnt 0 2006.145.09:42:28.79#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.09:42:28.91#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.09:42:28.91#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.09:42:28.93#ibcon#[25=USB\r\n] 2006.145.09:42:28.96#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.09:42:28.96#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.09:42:28.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.09:42:28.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.09:42:28.96$vck44/valo=2,534.99 2006.145.09:42:28.96#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.09:42:28.96#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.09:42:28.96#ibcon#ireg 17 cls_cnt 0 2006.145.09:42:28.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.09:42:28.96#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.09:42:28.96#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.09:42:28.99#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.09:42:29.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.09:42:29.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.09:42:29.03#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.09:42:29.03#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.09:42:29.03$vck44/va=2,7 2006.145.09:42:29.03#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.09:42:29.03#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.09:42:29.03#ibcon#ireg 11 cls_cnt 2 2006.145.09:42:29.03#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.09:42:29.08#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.09:42:29.08#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.09:42:29.10#ibcon#[25=AT02-07\r\n] 2006.145.09:42:29.13#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.09:42:29.13#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.09:42:29.13#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.09:42:29.13#ibcon#ireg 7 cls_cnt 0 2006.145.09:42:29.13#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.09:42:29.25#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.09:42:29.25#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.09:42:29.27#ibcon#[25=USB\r\n] 2006.145.09:42:29.30#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.09:42:29.30#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.09:42:29.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.09:42:29.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.09:42:29.30$vck44/valo=3,564.99 2006.145.09:42:29.30#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.09:42:29.30#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.09:42:29.30#ibcon#ireg 17 cls_cnt 0 2006.145.09:42:29.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.09:42:29.30#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.09:42:29.30#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.09:42:29.32#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.09:42:29.36#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.09:42:29.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.09:42:29.36#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.09:42:29.36#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.09:42:29.36$vck44/va=3,8 2006.145.09:42:29.36#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.09:42:29.36#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.09:42:29.36#ibcon#ireg 11 cls_cnt 2 2006.145.09:42:29.36#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.09:42:29.42#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.09:42:29.42#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.09:42:29.44#ibcon#[25=AT03-08\r\n] 2006.145.09:42:29.47#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.09:42:29.47#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.09:42:29.47#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.09:42:29.47#ibcon#ireg 7 cls_cnt 0 2006.145.09:42:29.47#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.09:42:29.59#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.09:42:29.59#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.09:42:29.61#ibcon#[25=USB\r\n] 2006.145.09:42:29.64#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.09:42:29.64#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.09:42:29.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.09:42:29.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.09:42:29.64$vck44/valo=4,624.99 2006.145.09:42:29.64#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.09:42:29.64#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.09:42:29.64#ibcon#ireg 17 cls_cnt 0 2006.145.09:42:29.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.09:42:29.64#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.09:42:29.64#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.09:42:29.66#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.09:42:29.70#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.09:42:29.70#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.09:42:29.70#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.09:42:29.70#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.09:42:29.70$vck44/va=4,7 2006.145.09:42:29.70#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.09:42:29.70#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.09:42:29.70#ibcon#ireg 11 cls_cnt 2 2006.145.09:42:29.70#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.09:42:29.76#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.09:42:29.76#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.09:42:29.78#ibcon#[25=AT04-07\r\n] 2006.145.09:42:29.81#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.09:42:29.81#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.09:42:29.81#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.09:42:29.81#ibcon#ireg 7 cls_cnt 0 2006.145.09:42:29.81#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.09:42:29.93#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.09:42:29.93#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.09:42:29.95#ibcon#[25=USB\r\n] 2006.145.09:42:29.98#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.09:42:29.98#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.09:42:29.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.09:42:29.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.09:42:29.98$vck44/valo=5,734.99 2006.145.09:42:29.98#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.09:42:29.98#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.09:42:29.98#ibcon#ireg 17 cls_cnt 0 2006.145.09:42:29.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.09:42:29.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.09:42:29.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.09:42:30.00#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.09:42:30.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.09:42:30.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.09:42:30.04#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.09:42:30.04#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.09:42:30.04$vck44/va=5,4 2006.145.09:42:30.04#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.09:42:30.04#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.09:42:30.04#ibcon#ireg 11 cls_cnt 2 2006.145.09:42:30.04#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.09:42:30.10#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.09:42:30.10#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.09:42:30.12#ibcon#[25=AT05-04\r\n] 2006.145.09:42:30.15#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.09:42:30.15#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.09:42:30.15#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.09:42:30.15#ibcon#ireg 7 cls_cnt 0 2006.145.09:42:30.15#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.09:42:30.28#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.09:42:30.28#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.09:42:30.29#ibcon#[25=USB\r\n] 2006.145.09:42:30.32#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.09:42:30.32#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.09:42:30.32#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.09:42:30.32#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.09:42:30.32$vck44/valo=6,814.99 2006.145.09:42:30.32#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.09:42:30.32#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.09:42:30.32#ibcon#ireg 17 cls_cnt 0 2006.145.09:42:30.32#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.09:42:30.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.09:42:30.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.09:42:30.35#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.09:42:30.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.09:42:30.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.09:42:30.39#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.09:42:30.39#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.09:42:30.39$vck44/va=6,4 2006.145.09:42:30.39#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.09:42:30.39#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.09:42:30.39#ibcon#ireg 11 cls_cnt 2 2006.145.09:42:30.39#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.09:42:30.44#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.09:42:30.44#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.09:42:30.46#ibcon#[25=AT06-04\r\n] 2006.145.09:42:30.49#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.09:42:30.49#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.09:42:30.49#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.09:42:30.49#ibcon#ireg 7 cls_cnt 0 2006.145.09:42:30.49#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.09:42:30.61#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.09:42:30.61#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.09:42:30.63#ibcon#[25=USB\r\n] 2006.145.09:42:30.66#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.09:42:30.66#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.09:42:30.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.09:42:30.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.09:42:30.66$vck44/valo=7,864.99 2006.145.09:42:30.66#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.09:42:30.66#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.09:42:30.66#ibcon#ireg 17 cls_cnt 0 2006.145.09:42:30.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.09:42:30.66#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.09:42:30.66#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.09:42:30.68#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.09:42:30.72#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.09:42:30.72#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.09:42:30.72#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.09:42:30.72#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.09:42:30.72$vck44/va=7,4 2006.145.09:42:30.72#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.09:42:30.72#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.09:42:30.72#ibcon#ireg 11 cls_cnt 2 2006.145.09:42:30.72#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.09:42:30.78#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.09:42:30.78#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.09:42:30.80#ibcon#[25=AT07-04\r\n] 2006.145.09:42:30.83#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.09:42:30.83#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.09:42:30.83#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.09:42:30.83#ibcon#ireg 7 cls_cnt 0 2006.145.09:42:30.83#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.09:42:30.95#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.09:42:30.95#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.09:42:30.97#ibcon#[25=USB\r\n] 2006.145.09:42:31.00#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.09:42:31.00#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.09:42:31.00#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.09:42:31.00#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.09:42:31.00$vck44/valo=8,884.99 2006.145.09:42:31.00#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.09:42:31.00#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.09:42:31.00#ibcon#ireg 17 cls_cnt 0 2006.145.09:42:31.00#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.09:42:31.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.09:42:31.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.09:42:31.02#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.09:42:31.06#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.09:42:31.06#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.09:42:31.06#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.09:42:31.06#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.09:42:31.06$vck44/va=8,4 2006.145.09:42:31.06#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.09:42:31.06#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.09:42:31.06#ibcon#ireg 11 cls_cnt 2 2006.145.09:42:31.06#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.09:42:31.12#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.09:42:31.12#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.09:42:31.14#ibcon#[25=AT08-04\r\n] 2006.145.09:42:31.17#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.09:42:31.17#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.09:42:31.17#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.09:42:31.17#ibcon#ireg 7 cls_cnt 0 2006.145.09:42:31.17#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.09:42:31.29#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.09:42:31.29#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.09:42:31.31#ibcon#[25=USB\r\n] 2006.145.09:42:31.34#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.09:42:31.34#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.09:42:31.34#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.09:42:31.34#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.09:42:31.34$vck44/vblo=1,629.99 2006.145.09:42:31.34#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.09:42:31.34#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.09:42:31.34#ibcon#ireg 17 cls_cnt 0 2006.145.09:42:31.34#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.09:42:31.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.09:42:31.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.09:42:31.36#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.09:42:31.40#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.09:42:31.40#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.09:42:31.40#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.09:42:31.40#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.09:42:31.40$vck44/vb=1,3 2006.145.09:42:31.40#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.09:42:31.40#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.09:42:31.40#ibcon#ireg 11 cls_cnt 2 2006.145.09:42:31.40#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.09:42:31.40#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.09:42:31.40#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.09:42:31.42#ibcon#[27=AT01-03\r\n] 2006.145.09:42:31.45#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.09:42:31.45#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.09:42:31.45#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.09:42:31.45#ibcon#ireg 7 cls_cnt 0 2006.145.09:42:31.45#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.09:42:31.57#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.09:42:31.57#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.09:42:31.59#ibcon#[27=USB\r\n] 2006.145.09:42:31.62#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.09:42:31.62#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.09:42:31.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.09:42:31.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.09:42:31.62$vck44/vblo=2,634.99 2006.145.09:42:31.62#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.09:42:31.62#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.09:42:31.62#ibcon#ireg 17 cls_cnt 0 2006.145.09:42:31.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.09:42:31.62#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.09:42:31.62#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.09:42:31.64#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.09:42:31.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.09:42:31.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.09:42:31.68#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.09:42:31.68#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.09:42:31.68$vck44/vb=2,4 2006.145.09:42:31.68#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.09:42:31.68#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.09:42:31.68#ibcon#ireg 11 cls_cnt 2 2006.145.09:42:31.68#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.09:42:31.74#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.09:42:31.74#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.09:42:31.76#ibcon#[27=AT02-04\r\n] 2006.145.09:42:31.79#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.09:42:31.79#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.09:42:31.79#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.09:42:31.79#ibcon#ireg 7 cls_cnt 0 2006.145.09:42:31.79#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.09:42:31.91#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.09:42:31.91#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.09:42:31.93#ibcon#[27=USB\r\n] 2006.145.09:42:31.96#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.09:42:31.96#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.09:42:31.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.09:42:31.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.09:42:31.96$vck44/vblo=3,649.99 2006.145.09:42:31.96#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.09:42:31.96#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.09:42:31.96#ibcon#ireg 17 cls_cnt 0 2006.145.09:42:31.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.09:42:31.96#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.09:42:31.96#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.09:42:31.98#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.09:42:32.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.09:42:32.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.09:42:32.02#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.09:42:32.02#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.09:42:32.02$vck44/vb=3,4 2006.145.09:42:32.02#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.09:42:32.02#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.09:42:32.02#ibcon#ireg 11 cls_cnt 2 2006.145.09:42:32.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.09:42:32.08#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.09:42:32.08#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.09:42:32.10#ibcon#[27=AT03-04\r\n] 2006.145.09:42:32.13#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.09:42:32.13#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.09:42:32.13#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.09:42:32.13#ibcon#ireg 7 cls_cnt 0 2006.145.09:42:32.13#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.09:42:32.25#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.09:42:32.25#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.09:42:32.27#ibcon#[27=USB\r\n] 2006.145.09:42:32.30#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.09:42:32.30#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.09:42:32.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.09:42:32.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.09:42:32.30$vck44/vblo=4,679.99 2006.145.09:42:32.30#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.09:42:32.30#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.09:42:32.30#ibcon#ireg 17 cls_cnt 0 2006.145.09:42:32.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.09:42:32.30#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.09:42:32.30#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.09:42:32.32#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.09:42:32.36#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.09:42:32.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.09:42:32.36#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.09:42:32.36#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.09:42:32.36$vck44/vb=4,4 2006.145.09:42:32.36#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.09:42:32.36#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.09:42:32.36#ibcon#ireg 11 cls_cnt 2 2006.145.09:42:32.36#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.09:42:32.42#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.09:42:32.42#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.09:42:32.44#ibcon#[27=AT04-04\r\n] 2006.145.09:42:32.47#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.09:42:32.47#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.09:42:32.47#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.09:42:32.47#ibcon#ireg 7 cls_cnt 0 2006.145.09:42:32.47#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.09:42:32.61#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.09:42:32.62#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.09:42:32.63#ibcon#[27=USB\r\n] 2006.145.09:42:32.66#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.09:42:32.66#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.09:42:32.66#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.09:42:32.66#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.09:42:32.66$vck44/vblo=5,709.99 2006.145.09:42:32.66#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.09:42:32.66#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.09:42:32.66#ibcon#ireg 17 cls_cnt 0 2006.145.09:42:32.66#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.09:42:32.66#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.09:42:32.66#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.09:42:32.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.09:42:32.72#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.09:42:32.72#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.09:42:32.72#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.09:42:32.72#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.09:42:32.72$vck44/vb=5,4 2006.145.09:42:32.72#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.09:42:32.72#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.09:42:32.72#ibcon#ireg 11 cls_cnt 2 2006.145.09:42:32.72#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.09:42:32.78#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.09:42:32.78#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.09:42:32.80#ibcon#[27=AT05-04\r\n] 2006.145.09:42:32.83#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.09:42:32.83#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.09:42:32.83#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.09:42:32.83#ibcon#ireg 7 cls_cnt 0 2006.145.09:42:32.83#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.09:42:32.95#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.09:42:32.95#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.09:42:32.97#ibcon#[27=USB\r\n] 2006.145.09:42:33.00#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.09:42:33.00#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.09:42:33.00#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.09:42:33.00#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.09:42:33.00$vck44/vblo=6,719.99 2006.145.09:42:33.00#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.09:42:33.00#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.09:42:33.00#ibcon#ireg 17 cls_cnt 0 2006.145.09:42:33.00#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.09:42:33.00#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.09:42:33.00#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.09:42:33.02#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.09:42:33.06#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.09:42:33.06#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.09:42:33.06#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.09:42:33.06#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.09:42:33.06$vck44/vb=6,4 2006.145.09:42:33.06#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.09:42:33.06#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.09:42:33.06#ibcon#ireg 11 cls_cnt 2 2006.145.09:42:33.06#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.09:42:33.12#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.09:42:33.12#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.09:42:33.14#ibcon#[27=AT06-04\r\n] 2006.145.09:42:33.17#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.09:42:33.17#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.09:42:33.17#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.09:42:33.17#ibcon#ireg 7 cls_cnt 0 2006.145.09:42:33.17#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.09:42:33.29#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.09:42:33.29#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.09:42:33.31#ibcon#[27=USB\r\n] 2006.145.09:42:33.34#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.09:42:33.34#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.09:42:33.34#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.09:42:33.34#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.09:42:33.34$vck44/vblo=7,734.99 2006.145.09:42:33.34#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.09:42:33.34#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.09:42:33.34#ibcon#ireg 17 cls_cnt 0 2006.145.09:42:33.34#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.09:42:33.34#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.09:42:33.34#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.09:42:33.36#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.09:42:33.40#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.09:42:33.40#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.09:42:33.40#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.09:42:33.40#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.09:42:33.40$vck44/vb=7,4 2006.145.09:42:33.40#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.09:42:33.40#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.09:42:33.40#ibcon#ireg 11 cls_cnt 2 2006.145.09:42:33.40#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.09:42:33.46#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.09:42:33.46#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.09:42:33.48#ibcon#[27=AT07-04\r\n] 2006.145.09:42:33.51#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.09:42:33.51#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.09:42:33.51#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.09:42:33.51#ibcon#ireg 7 cls_cnt 0 2006.145.09:42:33.51#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.09:42:33.63#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.09:42:33.63#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.09:42:33.65#ibcon#[27=USB\r\n] 2006.145.09:42:33.68#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.09:42:33.68#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.09:42:33.68#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.09:42:33.68#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.09:42:33.68$vck44/vblo=8,744.99 2006.145.09:42:33.68#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.09:42:33.68#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.09:42:33.68#ibcon#ireg 17 cls_cnt 0 2006.145.09:42:33.68#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.09:42:33.68#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.09:42:33.68#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.09:42:33.70#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.09:42:33.74#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.09:42:33.74#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.09:42:33.74#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.09:42:33.74#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.09:42:33.74$vck44/vb=8,4 2006.145.09:42:33.74#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.09:42:33.74#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.09:42:33.74#ibcon#ireg 11 cls_cnt 2 2006.145.09:42:33.74#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.09:42:33.80#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.09:42:33.80#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.09:42:33.82#ibcon#[27=AT08-04\r\n] 2006.145.09:42:33.85#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.09:42:33.85#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.09:42:33.85#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.09:42:33.85#ibcon#ireg 7 cls_cnt 0 2006.145.09:42:33.85#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.09:42:33.97#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.09:42:33.97#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.09:42:33.99#ibcon#[27=USB\r\n] 2006.145.09:42:34.02#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.09:42:34.02#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.09:42:34.02#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.09:42:34.02#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.09:42:34.02$vck44/vabw=wide 2006.145.09:42:34.02#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.09:42:34.02#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.09:42:34.02#ibcon#ireg 8 cls_cnt 0 2006.145.09:42:34.02#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.09:42:34.02#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.09:42:34.02#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.09:42:34.04#ibcon#[25=BW32\r\n] 2006.145.09:42:34.07#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.09:42:34.07#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.09:42:34.07#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.09:42:34.07#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.09:42:34.07$vck44/vbbw=wide 2006.145.09:42:34.07#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.09:42:34.07#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.09:42:34.07#ibcon#ireg 8 cls_cnt 0 2006.145.09:42:34.07#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:42:34.14#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:42:34.14#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:42:34.16#ibcon#[27=BW32\r\n] 2006.145.09:42:34.19#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:42:34.19#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:42:34.19#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.09:42:34.19#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.09:42:34.19$setupk4/ifdk4 2006.145.09:42:34.19$ifdk4/lo= 2006.145.09:42:34.19$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.09:42:34.19$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.09:42:34.19$ifdk4/patch= 2006.145.09:42:34.19$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.09:42:34.19$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.09:42:34.19$setupk4/!*+20s 2006.145.09:42:36.46#abcon#<5=/05 3.5 5.5 17.85 661018.7\r\n> 2006.145.09:42:36.48#abcon#{5=INTERFACE CLEAR} 2006.145.09:42:36.54#abcon#[5=S1D000X0/0*\r\n] 2006.145.09:42:42.14#trakl#Source acquired 2006.145.09:42:44.14#flagr#flagr/antenna,acquired 2006.145.09:42:46.63#abcon#<5=/05 3.5 5.5 17.84 671018.7\r\n> 2006.145.09:42:46.65#abcon#{5=INTERFACE CLEAR} 2006.145.09:42:46.71#abcon#[5=S1D000X0/0*\r\n] 2006.145.09:42:48.66$setupk4/"tpicd 2006.145.09:42:48.66$setupk4/echo=off 2006.145.09:42:48.66$setupk4/xlog=off 2006.145.09:42:48.66:!2006.145.09:43:43 2006.145.09:43:43.00:preob 2006.145.09:43:43.14/onsource/TRACKING 2006.145.09:43:43.14:!2006.145.09:43:53 2006.145.09:43:53.00:"tape 2006.145.09:43:53.00:"st=record 2006.145.09:43:53.00:data_valid=on 2006.145.09:43:53.00:midob 2006.145.09:43:53.14/onsource/TRACKING 2006.145.09:43:53.14/wx/17.83,1018.7,67 2006.145.09:43:53.25/cable/+6.5439E-03 2006.145.09:43:54.34/va/01,08,usb,yes,31,33 2006.145.09:43:54.34/va/02,07,usb,yes,33,34 2006.145.09:43:54.34/va/03,08,usb,yes,30,31 2006.145.09:43:54.34/va/04,07,usb,yes,34,36 2006.145.09:43:54.34/va/05,04,usb,yes,29,30 2006.145.09:43:54.34/va/06,04,usb,yes,33,33 2006.145.09:43:54.34/va/07,04,usb,yes,33,35 2006.145.09:43:54.34/va/08,04,usb,yes,28,34 2006.145.09:43:54.57/valo/01,524.99,yes,locked 2006.145.09:43:54.57/valo/02,534.99,yes,locked 2006.145.09:43:54.57/valo/03,564.99,yes,locked 2006.145.09:43:54.57/valo/04,624.99,yes,locked 2006.145.09:43:54.57/valo/05,734.99,yes,locked 2006.145.09:43:54.57/valo/06,814.99,yes,locked 2006.145.09:43:54.57/valo/07,864.99,yes,locked 2006.145.09:43:54.57/valo/08,884.99,yes,locked 2006.145.09:43:55.66/vb/01,03,usb,yes,44,41 2006.145.09:43:55.66/vb/02,04,usb,yes,39,38 2006.145.09:43:55.66/vb/03,04,usb,yes,35,39 2006.145.09:43:55.66/vb/04,04,usb,yes,40,39 2006.145.09:43:55.66/vb/05,04,usb,yes,31,34 2006.145.09:43:55.66/vb/06,04,usb,yes,36,32 2006.145.09:43:55.66/vb/07,04,usb,yes,36,36 2006.145.09:43:55.66/vb/08,04,usb,yes,33,37 2006.145.09:43:55.89/vblo/01,629.99,yes,locked 2006.145.09:43:55.89/vblo/02,634.99,yes,locked 2006.145.09:43:55.89/vblo/03,649.99,yes,locked 2006.145.09:43:55.89/vblo/04,679.99,yes,locked 2006.145.09:43:55.89/vblo/05,709.99,yes,locked 2006.145.09:43:55.89/vblo/06,719.99,yes,locked 2006.145.09:43:55.89/vblo/07,734.99,yes,locked 2006.145.09:43:55.89/vblo/08,744.99,yes,locked 2006.145.09:43:56.04/vabw/8 2006.145.09:43:56.19/vbbw/8 2006.145.09:43:56.28/xfe/off,on,14.0 2006.145.09:43:56.65/ifatt/23,28,28,28 2006.145.09:43:57.07/fmout-gps/S +5.1E-08 2006.145.09:43:57.11:!2006.145.09:45:13 2006.145.09:45:13.01:data_valid=off 2006.145.09:45:13.01:"et 2006.145.09:45:13.02:!+3s 2006.145.09:45:16.03:"tape 2006.145.09:45:16.03:postob 2006.145.09:45:16.20/cable/+6.5443E-03 2006.145.09:45:16.20/wx/17.82,1018.7,67 2006.145.09:45:16.29/fmout-gps/S +5.1E-08 2006.145.09:45:16.29:scan_name=145-0952,jd0605,50 2006.145.09:45:16.29:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.145.09:45:17.14#flagr#flagr/antenna,new-source 2006.145.09:45:17.15:checkk5 2006.145.09:45:17.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.09:45:18.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.09:45:18.45/chk_autoobs//k5ts3/ autoobs is running! 2006.145.09:45:18.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.09:45:19.31/chk_obsdata//k5ts1/T1450943??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.09:45:19.74/chk_obsdata//k5ts2/T1450943??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.09:45:20.17/chk_obsdata//k5ts3/T1450943??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.09:45:20.60/chk_obsdata//k5ts4/T1450943??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.09:45:21.35/k5log//k5ts1_log_newline 2006.145.09:45:22.09/k5log//k5ts2_log_newline 2006.145.09:45:22.83/k5log//k5ts3_log_newline 2006.145.09:45:23.58/k5log//k5ts4_log_newline 2006.145.09:45:23.61/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.09:45:23.61:setupk4=1 2006.145.09:45:23.61$setupk4/echo=on 2006.145.09:45:23.61$setupk4/pcalon 2006.145.09:45:23.61$pcalon/"no phase cal control is implemented here 2006.145.09:45:23.61$setupk4/"tpicd=stop 2006.145.09:45:23.61$setupk4/"rec=synch_on 2006.145.09:45:23.61$setupk4/"rec_mode=128 2006.145.09:45:23.61$setupk4/!* 2006.145.09:45:23.61$setupk4/recpk4 2006.145.09:45:23.61$recpk4/recpatch= 2006.145.09:45:23.61$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.09:45:23.61$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.09:45:23.61$setupk4/vck44 2006.145.09:45:23.61$vck44/valo=1,524.99 2006.145.09:45:23.61#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.09:45:23.61#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.09:45:23.61#ibcon#ireg 17 cls_cnt 0 2006.145.09:45:23.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.09:45:23.61#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.09:45:23.61#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.09:45:23.65#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.09:45:23.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.09:45:23.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.09:45:23.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.09:45:23.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.09:45:23.70$vck44/va=1,8 2006.145.09:45:23.70#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.09:45:23.70#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.09:45:23.70#ibcon#ireg 11 cls_cnt 2 2006.145.09:45:23.70#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.09:45:23.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.09:45:23.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.09:45:23.72#ibcon#[25=AT01-08\r\n] 2006.145.09:45:23.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.09:45:23.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.09:45:23.75#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.09:45:23.75#ibcon#ireg 7 cls_cnt 0 2006.145.09:45:23.75#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.09:45:23.87#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.09:45:23.87#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.09:45:23.89#ibcon#[25=USB\r\n] 2006.145.09:45:23.92#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.09:45:23.92#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.09:45:23.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.09:45:23.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.09:45:23.92$vck44/valo=2,534.99 2006.145.09:45:23.92#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.09:45:23.92#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.09:45:23.92#ibcon#ireg 17 cls_cnt 0 2006.145.09:45:23.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.09:45:23.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.09:45:23.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.09:45:23.95#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.09:45:23.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.09:45:23.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.09:45:23.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.09:45:23.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.09:45:23.99$vck44/va=2,7 2006.145.09:45:23.99#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.09:45:23.99#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.09:45:23.99#ibcon#ireg 11 cls_cnt 2 2006.145.09:45:23.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.09:45:24.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.09:45:24.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.09:45:24.06#ibcon#[25=AT02-07\r\n] 2006.145.09:45:24.09#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.09:45:24.09#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.09:45:24.09#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.09:45:24.09#ibcon#ireg 7 cls_cnt 0 2006.145.09:45:24.09#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.09:45:24.21#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.09:45:24.21#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.09:45:24.23#ibcon#[25=USB\r\n] 2006.145.09:45:24.26#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.09:45:24.26#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.09:45:24.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.09:45:24.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.09:45:24.26$vck44/valo=3,564.99 2006.145.09:45:24.26#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.09:45:24.26#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.09:45:24.26#ibcon#ireg 17 cls_cnt 0 2006.145.09:45:24.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.09:45:24.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.09:45:24.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.09:45:24.28#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.09:45:24.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.09:45:24.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.09:45:24.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.09:45:24.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.09:45:24.32$vck44/va=3,8 2006.145.09:45:24.32#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.09:45:24.32#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.09:45:24.32#ibcon#ireg 11 cls_cnt 2 2006.145.09:45:24.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.09:45:24.38#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.09:45:24.38#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.09:45:24.40#ibcon#[25=AT03-08\r\n] 2006.145.09:45:24.43#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.09:45:24.43#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.09:45:24.43#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.09:45:24.43#ibcon#ireg 7 cls_cnt 0 2006.145.09:45:24.43#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.09:45:24.55#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.09:45:24.55#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.09:45:24.57#ibcon#[25=USB\r\n] 2006.145.09:45:24.60#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.09:45:24.60#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.09:45:24.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.09:45:24.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.09:45:24.60$vck44/valo=4,624.99 2006.145.09:45:24.60#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.09:45:24.60#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.09:45:24.60#ibcon#ireg 17 cls_cnt 0 2006.145.09:45:24.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.09:45:24.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.09:45:24.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.09:45:24.62#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.09:45:24.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.09:45:24.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.09:45:24.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.09:45:24.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.09:45:24.66$vck44/va=4,7 2006.145.09:45:24.66#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.09:45:24.66#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.09:45:24.66#ibcon#ireg 11 cls_cnt 2 2006.145.09:45:24.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.09:45:24.72#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.09:45:24.72#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.09:45:24.74#ibcon#[25=AT04-07\r\n] 2006.145.09:45:24.77#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.09:45:24.77#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.09:45:24.77#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.09:45:24.77#ibcon#ireg 7 cls_cnt 0 2006.145.09:45:24.77#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.09:45:24.89#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.09:45:24.89#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.09:45:24.91#ibcon#[25=USB\r\n] 2006.145.09:45:24.94#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.09:45:24.94#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.09:45:24.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.09:45:24.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.09:45:24.94$vck44/valo=5,734.99 2006.145.09:45:24.94#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.09:45:24.94#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.09:45:24.94#ibcon#ireg 17 cls_cnt 0 2006.145.09:45:24.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.09:45:24.94#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.09:45:24.94#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.09:45:24.96#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.09:45:25.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.09:45:25.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.09:45:25.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.09:45:25.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.09:45:25.00$vck44/va=5,4 2006.145.09:45:25.00#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.09:45:25.00#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.09:45:25.00#ibcon#ireg 11 cls_cnt 2 2006.145.09:45:25.00#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.09:45:25.06#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.09:45:25.06#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.09:45:25.08#ibcon#[25=AT05-04\r\n] 2006.145.09:45:25.11#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.09:45:25.11#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.09:45:25.11#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.09:45:25.11#ibcon#ireg 7 cls_cnt 0 2006.145.09:45:25.11#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.09:45:25.25#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.09:45:25.25#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.09:45:25.26#ibcon#[25=USB\r\n] 2006.145.09:45:25.29#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.09:45:25.29#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.09:45:25.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.09:45:25.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.09:45:25.29$vck44/valo=6,814.99 2006.145.09:45:25.29#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.09:45:25.29#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.09:45:25.29#ibcon#ireg 17 cls_cnt 0 2006.145.09:45:25.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.09:45:25.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.09:45:25.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.09:45:25.32#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.09:45:25.36#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.09:45:25.36#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.09:45:25.36#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.09:45:25.36#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.09:45:25.36$vck44/va=6,4 2006.145.09:45:25.36#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.09:45:25.36#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.09:45:25.36#ibcon#ireg 11 cls_cnt 2 2006.145.09:45:25.36#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.09:45:25.41#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.09:45:25.41#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.09:45:25.43#ibcon#[25=AT06-04\r\n] 2006.145.09:45:25.46#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.09:45:25.46#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.09:45:25.46#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.09:45:25.46#ibcon#ireg 7 cls_cnt 0 2006.145.09:45:25.46#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.09:45:25.58#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.09:45:25.58#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.09:45:25.60#ibcon#[25=USB\r\n] 2006.145.09:45:25.63#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.09:45:25.63#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.09:45:25.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.09:45:25.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.09:45:25.63$vck44/valo=7,864.99 2006.145.09:45:25.63#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.09:45:25.63#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.09:45:25.63#ibcon#ireg 17 cls_cnt 0 2006.145.09:45:25.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.09:45:25.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.09:45:25.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.09:45:25.65#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.09:45:25.69#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.09:45:25.69#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.09:45:25.69#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.09:45:25.69#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.09:45:25.69$vck44/va=7,4 2006.145.09:45:25.69#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.09:45:25.69#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.09:45:25.69#ibcon#ireg 11 cls_cnt 2 2006.145.09:45:25.69#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.09:45:25.75#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.09:45:25.75#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.09:45:25.77#ibcon#[25=AT07-04\r\n] 2006.145.09:45:25.80#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.09:45:25.80#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.09:45:25.80#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.09:45:25.80#ibcon#ireg 7 cls_cnt 0 2006.145.09:45:25.80#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.09:45:25.92#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.09:45:25.92#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.09:45:25.94#ibcon#[25=USB\r\n] 2006.145.09:45:25.97#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.09:45:25.97#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.09:45:25.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.09:45:25.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.09:45:25.97$vck44/valo=8,884.99 2006.145.09:45:25.97#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.09:45:25.97#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.09:45:25.97#ibcon#ireg 17 cls_cnt 0 2006.145.09:45:25.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.09:45:25.97#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.09:45:25.97#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.09:45:25.99#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.09:45:26.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.09:45:26.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.09:45:26.03#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.09:45:26.03#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.09:45:26.03$vck44/va=8,4 2006.145.09:45:26.03#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.09:45:26.03#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.09:45:26.03#ibcon#ireg 11 cls_cnt 2 2006.145.09:45:26.03#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.09:45:26.09#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.09:45:26.09#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.09:45:26.11#ibcon#[25=AT08-04\r\n] 2006.145.09:45:26.14#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.09:45:26.14#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.09:45:26.14#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.09:45:26.14#ibcon#ireg 7 cls_cnt 0 2006.145.09:45:26.14#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.09:45:26.26#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.09:45:26.26#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.09:45:26.28#ibcon#[25=USB\r\n] 2006.145.09:45:26.31#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.09:45:26.31#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.09:45:26.31#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.09:45:26.31#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.09:45:26.31$vck44/vblo=1,629.99 2006.145.09:45:26.31#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.09:45:26.31#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.09:45:26.31#ibcon#ireg 17 cls_cnt 0 2006.145.09:45:26.31#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.09:45:26.31#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.09:45:26.31#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.09:45:26.33#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.09:45:26.37#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.09:45:26.37#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.09:45:26.37#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.09:45:26.37#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.09:45:26.37$vck44/vb=1,3 2006.145.09:45:26.37#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.09:45:26.37#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.09:45:26.37#ibcon#ireg 11 cls_cnt 2 2006.145.09:45:26.37#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.09:45:26.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.09:45:26.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.09:45:26.39#ibcon#[27=AT01-03\r\n] 2006.145.09:45:26.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.09:45:26.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.09:45:26.42#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.09:45:26.42#ibcon#ireg 7 cls_cnt 0 2006.145.09:45:26.42#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.09:45:26.54#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.09:45:26.54#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.09:45:26.56#ibcon#[27=USB\r\n] 2006.145.09:45:26.59#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.09:45:26.59#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.09:45:26.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.09:45:26.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.09:45:26.59$vck44/vblo=2,634.99 2006.145.09:45:26.59#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.09:45:26.59#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.09:45:26.59#ibcon#ireg 17 cls_cnt 0 2006.145.09:45:26.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.09:45:26.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.09:45:26.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.09:45:26.61#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.09:45:26.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.09:45:26.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.09:45:26.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.09:45:26.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.09:45:26.65$vck44/vb=2,4 2006.145.09:45:26.65#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.09:45:26.65#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.09:45:26.65#ibcon#ireg 11 cls_cnt 2 2006.145.09:45:26.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.09:45:26.71#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.09:45:26.71#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.09:45:26.73#ibcon#[27=AT02-04\r\n] 2006.145.09:45:26.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.09:45:26.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.09:45:26.76#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.09:45:26.76#ibcon#ireg 7 cls_cnt 0 2006.145.09:45:26.76#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.09:45:26.88#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.09:45:26.88#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.09:45:26.90#ibcon#[27=USB\r\n] 2006.145.09:45:26.93#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.09:45:26.93#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.09:45:26.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.09:45:26.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.09:45:26.93$vck44/vblo=3,649.99 2006.145.09:45:26.93#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.09:45:26.93#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.09:45:26.93#ibcon#ireg 17 cls_cnt 0 2006.145.09:45:26.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.09:45:26.93#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.09:45:26.93#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.09:45:26.95#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.09:45:26.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.09:45:26.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.09:45:26.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.09:45:26.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.09:45:26.99$vck44/vb=3,4 2006.145.09:45:26.99#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.09:45:26.99#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.09:45:26.99#ibcon#ireg 11 cls_cnt 2 2006.145.09:45:26.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.09:45:27.05#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.09:45:27.05#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.09:45:27.07#ibcon#[27=AT03-04\r\n] 2006.145.09:45:27.10#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.09:45:27.10#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.09:45:27.10#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.09:45:27.10#ibcon#ireg 7 cls_cnt 0 2006.145.09:45:27.10#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.09:45:27.22#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.09:45:27.22#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.09:45:27.24#ibcon#[27=USB\r\n] 2006.145.09:45:27.27#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.09:45:27.27#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.09:45:27.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.09:45:27.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.09:45:27.27$vck44/vblo=4,679.99 2006.145.09:45:27.27#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.09:45:27.27#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.09:45:27.27#ibcon#ireg 17 cls_cnt 0 2006.145.09:45:27.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.09:45:27.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.09:45:27.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.09:45:27.29#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.09:45:27.33#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.09:45:27.33#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.09:45:27.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.09:45:27.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.09:45:27.33$vck44/vb=4,4 2006.145.09:45:27.33#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.09:45:27.33#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.09:45:27.33#ibcon#ireg 11 cls_cnt 2 2006.145.09:45:27.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.09:45:27.39#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.09:45:27.39#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.09:45:27.41#ibcon#[27=AT04-04\r\n] 2006.145.09:45:27.44#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.09:45:27.44#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.09:45:27.44#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.09:45:27.44#ibcon#ireg 7 cls_cnt 0 2006.145.09:45:27.44#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.09:45:27.56#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.09:45:27.56#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.09:45:27.58#ibcon#[27=USB\r\n] 2006.145.09:45:27.61#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.09:45:27.61#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.09:45:27.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.09:45:27.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.09:45:27.61$vck44/vblo=5,709.99 2006.145.09:45:27.61#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.09:45:27.61#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.09:45:27.61#ibcon#ireg 17 cls_cnt 0 2006.145.09:45:27.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.09:45:27.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.09:45:27.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.09:45:27.63#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.09:45:27.67#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.09:45:27.67#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.09:45:27.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.09:45:27.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.09:45:27.67$vck44/vb=5,4 2006.145.09:45:27.67#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.09:45:27.67#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.09:45:27.67#ibcon#ireg 11 cls_cnt 2 2006.145.09:45:27.67#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.09:45:27.73#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.09:45:27.73#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.09:45:27.75#ibcon#[27=AT05-04\r\n] 2006.145.09:45:27.78#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.09:45:27.78#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.09:45:27.78#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.09:45:27.78#ibcon#ireg 7 cls_cnt 0 2006.145.09:45:27.78#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.09:45:27.90#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.09:45:27.90#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.09:45:27.92#ibcon#[27=USB\r\n] 2006.145.09:45:27.95#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.09:45:27.95#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.09:45:27.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.09:45:27.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.09:45:27.95$vck44/vblo=6,719.99 2006.145.09:45:27.95#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.09:45:27.95#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.09:45:27.95#ibcon#ireg 17 cls_cnt 0 2006.145.09:45:27.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.09:45:27.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.09:45:27.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.09:45:27.97#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.09:45:28.01#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.09:45:28.01#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.09:45:28.01#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.09:45:28.01#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.09:45:28.01$vck44/vb=6,4 2006.145.09:45:28.01#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.09:45:28.01#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.09:45:28.01#ibcon#ireg 11 cls_cnt 2 2006.145.09:45:28.01#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.09:45:28.07#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.09:45:28.07#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.09:45:28.09#ibcon#[27=AT06-04\r\n] 2006.145.09:45:28.12#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.09:45:28.12#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.09:45:28.12#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.09:45:28.12#ibcon#ireg 7 cls_cnt 0 2006.145.09:45:28.12#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.09:45:28.24#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.09:45:28.24#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.09:45:28.26#ibcon#[27=USB\r\n] 2006.145.09:45:28.29#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.09:45:28.29#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.09:45:28.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.09:45:28.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.09:45:28.29$vck44/vblo=7,734.99 2006.145.09:45:28.29#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.09:45:28.29#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.09:45:28.29#ibcon#ireg 17 cls_cnt 0 2006.145.09:45:28.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.09:45:28.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.09:45:28.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.09:45:28.31#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.09:45:28.35#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.09:45:28.35#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.09:45:28.35#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.09:45:28.35#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.09:45:28.35$vck44/vb=7,4 2006.145.09:45:28.35#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.09:45:28.35#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.09:45:28.35#ibcon#ireg 11 cls_cnt 2 2006.145.09:45:28.35#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.09:45:28.41#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.09:45:28.41#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.09:45:28.43#ibcon#[27=AT07-04\r\n] 2006.145.09:45:28.46#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.09:45:28.46#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.09:45:28.46#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.09:45:28.46#ibcon#ireg 7 cls_cnt 0 2006.145.09:45:28.46#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.09:45:28.58#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.09:45:28.58#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.09:45:28.60#ibcon#[27=USB\r\n] 2006.145.09:45:28.63#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.09:45:28.63#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.09:45:28.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.09:45:28.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.09:45:28.63$vck44/vblo=8,744.99 2006.145.09:45:28.63#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.09:45:28.63#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.09:45:28.63#ibcon#ireg 17 cls_cnt 0 2006.145.09:45:28.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.09:45:28.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.09:45:28.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.09:45:28.65#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.09:45:28.69#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.09:45:28.69#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.09:45:28.69#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.09:45:28.69#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.09:45:28.69$vck44/vb=8,4 2006.145.09:45:28.69#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.09:45:28.69#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.09:45:28.69#ibcon#ireg 11 cls_cnt 2 2006.145.09:45:28.69#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.09:45:28.75#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.09:45:28.75#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.09:45:28.77#ibcon#[27=AT08-04\r\n] 2006.145.09:45:28.80#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.09:45:28.80#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.09:45:28.80#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.09:45:28.80#ibcon#ireg 7 cls_cnt 0 2006.145.09:45:28.80#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.09:45:28.92#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.09:45:28.92#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.09:45:28.94#ibcon#[27=USB\r\n] 2006.145.09:45:28.97#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.09:45:28.97#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.09:45:28.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.09:45:28.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.09:45:28.97$vck44/vabw=wide 2006.145.09:45:28.97#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.09:45:28.97#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.09:45:28.97#ibcon#ireg 8 cls_cnt 0 2006.145.09:45:28.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.09:45:28.97#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.09:45:28.97#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.09:45:28.99#ibcon#[25=BW32\r\n] 2006.145.09:45:29.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.09:45:29.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.09:45:29.02#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.09:45:29.02#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.09:45:29.02$vck44/vbbw=wide 2006.145.09:45:29.02#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.09:45:29.02#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.09:45:29.02#ibcon#ireg 8 cls_cnt 0 2006.145.09:45:29.02#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.09:45:29.09#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.09:45:29.09#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.09:45:29.11#ibcon#[27=BW32\r\n] 2006.145.09:45:29.14#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.09:45:29.14#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.09:45:29.14#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.09:45:29.14#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.09:45:29.14$setupk4/ifdk4 2006.145.09:45:29.14$ifdk4/lo= 2006.145.09:45:29.14$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.09:45:29.14$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.09:45:29.14$ifdk4/patch= 2006.145.09:45:29.14$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.09:45:29.14$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.09:45:29.14$setupk4/!*+20s 2006.145.09:45:29.35#abcon#<5=/05 3.3 5.4 17.82 671018.7\r\n> 2006.145.09:45:29.37#abcon#{5=INTERFACE CLEAR} 2006.145.09:45:29.43#abcon#[5=S1D000X0/0*\r\n] 2006.145.09:45:39.52#abcon#<5=/05 3.4 5.4 17.82 671018.7\r\n> 2006.145.09:45:39.54#abcon#{5=INTERFACE CLEAR} 2006.145.09:45:39.60#abcon#[5=S1D000X0/0*\r\n] 2006.145.09:45:43.62$setupk4/"tpicd 2006.145.09:45:43.62$setupk4/echo=off 2006.145.09:45:43.62$setupk4/xlog=off 2006.145.09:45:43.62:!2006.145.09:52:33 2006.145.09:46:16.14#trakl#Source acquired 2006.145.09:46:18.14#flagr#flagr/antenna,acquired 2006.145.09:52:33.00:preob 2006.145.09:52:34.14/onsource/TRACKING 2006.145.09:52:34.14:!2006.145.09:52:43 2006.145.09:52:43.00:"tape 2006.145.09:52:43.00:"st=record 2006.145.09:52:43.00:data_valid=on 2006.145.09:52:43.00:midob 2006.145.09:52:43.14/onsource/TRACKING 2006.145.09:52:43.14/wx/17.72,1018.7,66 2006.145.09:52:43.29/cable/+6.5441E-03 2006.145.09:52:44.38/va/01,08,usb,yes,29,31 2006.145.09:52:44.38/va/02,07,usb,yes,31,32 2006.145.09:52:44.38/va/03,08,usb,yes,28,30 2006.145.09:52:44.38/va/04,07,usb,yes,32,34 2006.145.09:52:44.38/va/05,04,usb,yes,28,29 2006.145.09:52:44.38/va/06,04,usb,yes,32,32 2006.145.09:52:44.38/va/07,04,usb,yes,32,33 2006.145.09:52:44.38/va/08,04,usb,yes,27,33 2006.145.09:52:44.61/valo/01,524.99,yes,locked 2006.145.09:52:44.61/valo/02,534.99,yes,locked 2006.145.09:52:44.61/valo/03,564.99,yes,locked 2006.145.09:52:44.61/valo/04,624.99,yes,locked 2006.145.09:52:44.61/valo/05,734.99,yes,locked 2006.145.09:52:44.61/valo/06,814.99,yes,locked 2006.145.09:52:44.61/valo/07,864.99,yes,locked 2006.145.09:52:44.61/valo/08,884.99,yes,locked 2006.145.09:52:45.70/vb/01,03,usb,yes,36,34 2006.145.09:52:45.70/vb/02,04,usb,yes,32,31 2006.145.09:52:45.70/vb/03,04,usb,yes,28,31 2006.145.09:52:45.70/vb/04,04,usb,yes,33,32 2006.145.09:52:45.70/vb/05,04,usb,yes,26,28 2006.145.09:52:45.70/vb/06,04,usb,yes,30,26 2006.145.09:52:45.70/vb/07,04,usb,yes,29,29 2006.145.09:52:45.70/vb/08,04,usb,yes,27,30 2006.145.09:52:45.93/vblo/01,629.99,yes,locked 2006.145.09:52:45.93/vblo/02,634.99,yes,locked 2006.145.09:52:45.93/vblo/03,649.99,yes,locked 2006.145.09:52:45.93/vblo/04,679.99,yes,locked 2006.145.09:52:45.93/vblo/05,709.99,yes,locked 2006.145.09:52:45.93/vblo/06,719.99,yes,locked 2006.145.09:52:45.93/vblo/07,734.99,yes,locked 2006.145.09:52:45.93/vblo/08,744.99,yes,locked 2006.145.09:52:46.08/vabw/8 2006.145.09:52:46.23/vbbw/8 2006.145.09:52:46.32/xfe/off,on,15.0 2006.145.09:52:46.70/ifatt/23,28,28,28 2006.145.09:52:47.07/fmout-gps/S +4.8E-08 2006.145.09:52:47.11:!2006.145.09:53:33 2006.145.09:53:33.00:data_valid=off 2006.145.09:53:33.00:"et 2006.145.09:53:33.01:!+3s 2006.145.09:53:36.02:"tape 2006.145.09:53:36.02:postob 2006.145.09:53:36.13/cable/+6.5427E-03 2006.145.09:53:36.13/wx/17.70,1018.8,66 2006.145.09:53:36.22/fmout-gps/S +4.9E-08 2006.145.09:53:36.22:scan_name=145-0956,jd0605,180 2006.145.09:53:36.22:source=1044+719,104827.62,714335.9,2000.0,neutral 2006.145.09:53:37.14#flagr#flagr/antenna,new-source 2006.145.09:53:37.14:checkk5 2006.145.09:53:37.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.09:53:38.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.09:53:38.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.09:53:38.91/chk_autoobs//k5ts4/ autoobs is running! 2006.145.09:53:39.34/chk_obsdata//k5ts1/T1450952??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.09:53:39.79/chk_obsdata//k5ts2/T1450952??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.09:53:40.23/chk_obsdata//k5ts3/T1450952??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.09:53:40.67/chk_obsdata//k5ts4/T1450952??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.09:53:41.43/k5log//k5ts1_log_newline 2006.145.09:53:42.17/k5log//k5ts2_log_newline 2006.145.09:53:42.90/k5log//k5ts3_log_newline 2006.145.09:53:43.64/k5log//k5ts4_log_newline 2006.145.09:53:43.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.09:53:43.67:setupk4=1 2006.145.09:53:43.67$setupk4/echo=on 2006.145.09:53:43.67$setupk4/pcalon 2006.145.09:53:43.67$pcalon/"no phase cal control is implemented here 2006.145.09:53:43.67$setupk4/"tpicd=stop 2006.145.09:53:43.67$setupk4/"rec=synch_on 2006.145.09:53:43.67$setupk4/"rec_mode=128 2006.145.09:53:43.67$setupk4/!* 2006.145.09:53:43.67$setupk4/recpk4 2006.145.09:53:43.67$recpk4/recpatch= 2006.145.09:53:43.67$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.09:53:43.67$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.09:53:43.67$setupk4/vck44 2006.145.09:53:43.67$vck44/valo=1,524.99 2006.145.09:53:43.67#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.09:53:43.67#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.09:53:43.67#ibcon#ireg 17 cls_cnt 0 2006.145.09:53:43.67#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:53:43.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:53:43.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:53:43.71#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.09:53:43.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:53:43.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:53:43.76#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.09:53:43.76#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.09:53:43.76$vck44/va=1,8 2006.145.09:53:43.76#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.09:53:43.76#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.09:53:43.76#ibcon#ireg 11 cls_cnt 2 2006.145.09:53:43.76#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.09:53:43.76#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.09:53:43.76#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.09:53:43.78#ibcon#[25=AT01-08\r\n] 2006.145.09:53:43.81#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.09:53:43.81#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.09:53:43.81#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.09:53:43.81#ibcon#ireg 7 cls_cnt 0 2006.145.09:53:43.81#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.09:53:43.93#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.09:53:43.93#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.09:53:43.95#ibcon#[25=USB\r\n] 2006.145.09:53:43.98#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.09:53:43.98#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.09:53:43.98#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.09:53:43.98#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.09:53:43.98$vck44/valo=2,534.99 2006.145.09:53:43.98#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.09:53:43.98#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.09:53:43.98#ibcon#ireg 17 cls_cnt 0 2006.145.09:53:43.98#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.09:53:43.98#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.09:53:43.98#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.09:53:44.01#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.09:53:44.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.09:53:44.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.09:53:44.05#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.09:53:44.05#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.09:53:44.05$vck44/va=2,7 2006.145.09:53:44.05#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.09:53:44.05#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.09:53:44.05#ibcon#ireg 11 cls_cnt 2 2006.145.09:53:44.05#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.09:53:44.10#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.09:53:44.10#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.09:53:44.12#ibcon#[25=AT02-07\r\n] 2006.145.09:53:44.15#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.09:53:44.15#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.09:53:44.15#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.09:53:44.15#ibcon#ireg 7 cls_cnt 0 2006.145.09:53:44.15#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.09:53:44.27#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.09:53:44.27#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.09:53:44.29#ibcon#[25=USB\r\n] 2006.145.09:53:44.32#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.09:53:44.32#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.09:53:44.32#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.09:53:44.32#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.09:53:44.32$vck44/valo=3,564.99 2006.145.09:53:44.32#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.09:53:44.32#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.09:53:44.32#ibcon#ireg 17 cls_cnt 0 2006.145.09:53:44.32#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:53:44.32#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:53:44.32#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:53:44.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.09:53:44.38#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:53:44.38#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:53:44.38#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.09:53:44.38#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.09:53:44.38$vck44/va=3,8 2006.145.09:53:44.38#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.09:53:44.38#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.09:53:44.38#ibcon#ireg 11 cls_cnt 2 2006.145.09:53:44.38#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.09:53:44.44#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.09:53:44.44#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.09:53:44.46#ibcon#[25=AT03-08\r\n] 2006.145.09:53:44.49#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.09:53:44.49#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.09:53:44.49#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.09:53:44.49#ibcon#ireg 7 cls_cnt 0 2006.145.09:53:44.49#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.09:53:44.61#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.09:53:44.61#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.09:53:44.63#ibcon#[25=USB\r\n] 2006.145.09:53:44.66#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.09:53:44.66#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.09:53:44.66#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.09:53:44.66#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.09:53:44.66$vck44/valo=4,624.99 2006.145.09:53:44.66#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.09:53:44.66#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.09:53:44.66#ibcon#ireg 17 cls_cnt 0 2006.145.09:53:44.66#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.09:53:44.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.09:53:44.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.09:53:44.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.09:53:44.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.09:53:44.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.09:53:44.72#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.09:53:44.72#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.09:53:44.72$vck44/va=4,7 2006.145.09:53:44.72#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.09:53:44.72#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.09:53:44.72#ibcon#ireg 11 cls_cnt 2 2006.145.09:53:44.72#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.09:53:44.78#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.09:53:44.78#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.09:53:44.80#ibcon#[25=AT04-07\r\n] 2006.145.09:53:44.83#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.09:53:44.83#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.09:53:44.83#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.09:53:44.83#ibcon#ireg 7 cls_cnt 0 2006.145.09:53:44.83#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.09:53:44.95#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.09:53:44.95#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.09:53:44.97#ibcon#[25=USB\r\n] 2006.145.09:53:45.00#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.09:53:45.00#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.09:53:45.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.09:53:45.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.09:53:45.00$vck44/valo=5,734.99 2006.145.09:53:45.00#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.09:53:45.00#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.09:53:45.00#ibcon#ireg 17 cls_cnt 0 2006.145.09:53:45.00#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.09:53:45.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.09:53:45.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.09:53:45.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.09:53:45.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.09:53:45.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.09:53:45.06#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.09:53:45.06#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.09:53:45.06$vck44/va=5,4 2006.145.09:53:45.06#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.09:53:45.06#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.09:53:45.06#ibcon#ireg 11 cls_cnt 2 2006.145.09:53:45.06#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.09:53:45.12#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.09:53:45.12#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.09:53:45.14#ibcon#[25=AT05-04\r\n] 2006.145.09:53:45.17#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.09:53:45.17#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.09:53:45.17#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.09:53:45.17#ibcon#ireg 7 cls_cnt 0 2006.145.09:53:45.17#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.09:53:45.29#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.09:53:45.29#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.09:53:45.31#ibcon#[25=USB\r\n] 2006.145.09:53:45.34#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.09:53:45.34#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.09:53:45.34#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.09:53:45.34#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.09:53:45.34$vck44/valo=6,814.99 2006.145.09:53:45.34#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.09:53:45.34#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.09:53:45.34#ibcon#ireg 17 cls_cnt 0 2006.145.09:53:45.34#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:53:45.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:53:45.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:53:45.37#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.09:53:45.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:53:45.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:53:45.41#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.09:53:45.41#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.09:53:45.41$vck44/va=6,4 2006.145.09:53:45.41#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.09:53:45.41#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.09:53:45.41#ibcon#ireg 11 cls_cnt 2 2006.145.09:53:45.41#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:53:45.46#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:53:45.46#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:53:45.48#ibcon#[25=AT06-04\r\n] 2006.145.09:53:45.51#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:53:45.51#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:53:45.51#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.09:53:45.51#ibcon#ireg 7 cls_cnt 0 2006.145.09:53:45.51#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:53:45.63#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:53:45.63#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:53:45.65#ibcon#[25=USB\r\n] 2006.145.09:53:45.68#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:53:45.68#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:53:45.68#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.09:53:45.68#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.09:53:45.68$vck44/valo=7,864.99 2006.145.09:53:45.68#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.09:53:45.68#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.09:53:45.68#ibcon#ireg 17 cls_cnt 0 2006.145.09:53:45.68#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:53:45.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:53:45.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:53:45.70#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.09:53:45.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:53:45.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:53:45.74#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.09:53:45.74#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.09:53:45.74$vck44/va=7,4 2006.145.09:53:45.74#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.09:53:45.74#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.09:53:45.74#ibcon#ireg 11 cls_cnt 2 2006.145.09:53:45.74#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:53:45.80#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:53:45.80#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:53:45.82#ibcon#[25=AT07-04\r\n] 2006.145.09:53:45.85#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:53:45.85#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:53:45.85#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.09:53:45.85#ibcon#ireg 7 cls_cnt 0 2006.145.09:53:45.85#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:53:45.97#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:53:45.97#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:53:45.99#ibcon#[25=USB\r\n] 2006.145.09:53:46.02#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:53:46.02#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:53:46.02#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.09:53:46.02#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.09:53:46.02$vck44/valo=8,884.99 2006.145.09:53:46.02#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.09:53:46.02#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.09:53:46.02#ibcon#ireg 17 cls_cnt 0 2006.145.09:53:46.02#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:53:46.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:53:46.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:53:46.04#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.09:53:46.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:53:46.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:53:46.08#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.09:53:46.08#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.09:53:46.08$vck44/va=8,4 2006.145.09:53:46.08#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.09:53:46.08#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.09:53:46.08#ibcon#ireg 11 cls_cnt 2 2006.145.09:53:46.08#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:53:46.14#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:53:46.14#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:53:46.16#ibcon#[25=AT08-04\r\n] 2006.145.09:53:46.19#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:53:46.19#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:53:46.19#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.09:53:46.19#ibcon#ireg 7 cls_cnt 0 2006.145.09:53:46.19#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:53:46.31#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:53:46.31#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:53:46.33#ibcon#[25=USB\r\n] 2006.145.09:53:46.36#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:53:46.36#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:53:46.36#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.09:53:46.36#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.09:53:46.36$vck44/vblo=1,629.99 2006.145.09:53:46.36#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.09:53:46.36#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.09:53:46.36#ibcon#ireg 17 cls_cnt 0 2006.145.09:53:46.36#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:53:46.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:53:46.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:53:46.38#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.09:53:46.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:53:46.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:53:46.42#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.09:53:46.42#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.09:53:46.42$vck44/vb=1,3 2006.145.09:53:46.42#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.09:53:46.42#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.09:53:46.42#ibcon#ireg 11 cls_cnt 2 2006.145.09:53:46.42#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.09:53:46.42#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.09:53:46.42#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.09:53:46.44#ibcon#[27=AT01-03\r\n] 2006.145.09:53:46.47#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.09:53:46.47#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.09:53:46.47#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.09:53:46.47#ibcon#ireg 7 cls_cnt 0 2006.145.09:53:46.47#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.09:53:46.59#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.09:53:46.59#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.09:53:46.61#ibcon#[27=USB\r\n] 2006.145.09:53:46.64#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.09:53:46.64#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.09:53:46.64#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.09:53:46.64#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.09:53:46.64$vck44/vblo=2,634.99 2006.145.09:53:46.64#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.09:53:46.64#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.09:53:46.64#ibcon#ireg 17 cls_cnt 0 2006.145.09:53:46.64#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:53:46.64#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:53:46.64#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:53:46.66#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.09:53:46.70#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:53:46.70#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.09:53:46.70#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.09:53:46.70#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.09:53:46.70$vck44/vb=2,4 2006.145.09:53:46.70#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.09:53:46.70#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.09:53:46.70#ibcon#ireg 11 cls_cnt 2 2006.145.09:53:46.70#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.09:53:46.76#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.09:53:46.76#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.09:53:46.78#ibcon#[27=AT02-04\r\n] 2006.145.09:53:46.81#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.09:53:46.81#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.09:53:46.81#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.09:53:46.81#ibcon#ireg 7 cls_cnt 0 2006.145.09:53:46.81#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.09:53:46.93#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.09:53:46.93#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.09:53:46.95#ibcon#[27=USB\r\n] 2006.145.09:53:46.98#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.09:53:46.98#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.09:53:46.98#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.09:53:46.98#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.09:53:46.98$vck44/vblo=3,649.99 2006.145.09:53:46.98#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.09:53:46.98#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.09:53:46.98#ibcon#ireg 17 cls_cnt 0 2006.145.09:53:46.98#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.09:53:46.98#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.09:53:46.98#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.09:53:47.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.09:53:47.04#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.09:53:47.04#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.09:53:47.04#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.09:53:47.04#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.09:53:47.04$vck44/vb=3,4 2006.145.09:53:47.04#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.09:53:47.04#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.09:53:47.04#ibcon#ireg 11 cls_cnt 2 2006.145.09:53:47.04#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.09:53:47.10#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.09:53:47.10#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.09:53:47.12#ibcon#[27=AT03-04\r\n] 2006.145.09:53:47.15#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.09:53:47.15#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.09:53:47.15#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.09:53:47.15#ibcon#ireg 7 cls_cnt 0 2006.145.09:53:47.15#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.09:53:47.27#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.09:53:47.27#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.09:53:47.29#ibcon#[27=USB\r\n] 2006.145.09:53:47.32#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.09:53:47.32#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.09:53:47.32#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.09:53:47.32#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.09:53:47.32$vck44/vblo=4,679.99 2006.145.09:53:47.32#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.09:53:47.32#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.09:53:47.32#ibcon#ireg 17 cls_cnt 0 2006.145.09:53:47.32#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:53:47.32#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:53:47.32#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:53:47.34#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.09:53:47.38#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:53:47.38#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.09:53:47.38#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.09:53:47.38#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.09:53:47.38$vck44/vb=4,4 2006.145.09:53:47.38#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.09:53:47.38#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.09:53:47.38#ibcon#ireg 11 cls_cnt 2 2006.145.09:53:47.38#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.09:53:47.44#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.09:53:47.44#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.09:53:47.46#ibcon#[27=AT04-04\r\n] 2006.145.09:53:47.49#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.09:53:47.49#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.09:53:47.49#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.09:53:47.49#ibcon#ireg 7 cls_cnt 0 2006.145.09:53:47.49#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.09:53:47.61#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.09:53:47.61#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.09:53:47.63#ibcon#[27=USB\r\n] 2006.145.09:53:47.66#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.09:53:47.66#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.09:53:47.66#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.09:53:47.66#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.09:53:47.66$vck44/vblo=5,709.99 2006.145.09:53:47.66#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.09:53:47.66#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.09:53:47.66#ibcon#ireg 17 cls_cnt 0 2006.145.09:53:47.66#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.09:53:47.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.09:53:47.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.09:53:47.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.09:53:47.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.09:53:47.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.09:53:47.72#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.09:53:47.72#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.09:53:47.72$vck44/vb=5,4 2006.145.09:53:47.72#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.09:53:47.72#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.09:53:47.72#ibcon#ireg 11 cls_cnt 2 2006.145.09:53:47.72#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.09:53:47.78#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.09:53:47.78#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.09:53:47.80#ibcon#[27=AT05-04\r\n] 2006.145.09:53:47.82#abcon#<5=/05 3.3 5.4 17.69 671018.8\r\n> 2006.145.09:53:47.83#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.09:53:47.83#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.09:53:47.83#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.09:53:47.83#ibcon#ireg 7 cls_cnt 0 2006.145.09:53:47.83#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.09:53:47.84#abcon#{5=INTERFACE CLEAR} 2006.145.09:53:47.90#abcon#[5=S1D000X0/0*\r\n] 2006.145.09:53:47.95#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.09:53:47.95#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.09:53:47.97#ibcon#[27=USB\r\n] 2006.145.09:53:48.00#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.09:53:48.00#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.09:53:48.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.09:53:48.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.09:53:48.00$vck44/vblo=6,719.99 2006.145.09:53:48.00#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.09:53:48.00#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.09:53:48.00#ibcon#ireg 17 cls_cnt 0 2006.145.09:53:48.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:53:48.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:53:48.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:53:48.02#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.09:53:48.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:53:48.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.09:53:48.06#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.09:53:48.06#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.09:53:48.06$vck44/vb=6,4 2006.145.09:53:48.06#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.09:53:48.06#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.09:53:48.06#ibcon#ireg 11 cls_cnt 2 2006.145.09:53:48.06#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:53:48.12#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:53:48.12#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:53:48.14#ibcon#[27=AT06-04\r\n] 2006.145.09:53:48.17#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:53:48.17#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.09:53:48.17#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.09:53:48.17#ibcon#ireg 7 cls_cnt 0 2006.145.09:53:48.17#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:53:48.29#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:53:48.29#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:53:48.31#ibcon#[27=USB\r\n] 2006.145.09:53:48.34#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:53:48.34#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.09:53:48.34#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.09:53:48.34#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.09:53:48.34$vck44/vblo=7,734.99 2006.145.09:53:48.34#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.09:53:48.34#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.09:53:48.34#ibcon#ireg 17 cls_cnt 0 2006.145.09:53:48.34#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:53:48.34#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:53:48.34#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:53:48.36#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.09:53:48.40#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:53:48.40#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.09:53:48.40#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.09:53:48.40#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.09:53:48.40$vck44/vb=7,4 2006.145.09:53:48.40#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.09:53:48.40#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.09:53:48.40#ibcon#ireg 11 cls_cnt 2 2006.145.09:53:48.40#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:53:48.46#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:53:48.46#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:53:48.48#ibcon#[27=AT07-04\r\n] 2006.145.09:53:48.51#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:53:48.51#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.09:53:48.51#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.09:53:48.51#ibcon#ireg 7 cls_cnt 0 2006.145.09:53:48.51#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:53:48.63#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:53:48.63#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:53:48.65#ibcon#[27=USB\r\n] 2006.145.09:53:48.68#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:53:48.68#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.09:53:48.68#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.09:53:48.68#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.09:53:48.68$vck44/vblo=8,744.99 2006.145.09:53:48.68#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.09:53:48.68#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.09:53:48.68#ibcon#ireg 17 cls_cnt 0 2006.145.09:53:48.68#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:53:48.68#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:53:48.68#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:53:48.70#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.09:53:48.74#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:53:48.74#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.09:53:48.74#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.09:53:48.74#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.09:53:48.74$vck44/vb=8,4 2006.145.09:53:48.74#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.09:53:48.74#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.09:53:48.74#ibcon#ireg 11 cls_cnt 2 2006.145.09:53:48.74#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:53:48.80#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:53:48.80#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:53:48.82#ibcon#[27=AT08-04\r\n] 2006.145.09:53:48.85#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:53:48.85#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:53:48.85#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.09:53:48.85#ibcon#ireg 7 cls_cnt 0 2006.145.09:53:48.85#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:53:48.97#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:53:48.97#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:53:48.99#ibcon#[27=USB\r\n] 2006.145.09:53:49.02#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:53:49.02#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:53:49.02#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.09:53:49.02#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.09:53:49.02$vck44/vabw=wide 2006.145.09:53:49.02#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.09:53:49.02#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.09:53:49.02#ibcon#ireg 8 cls_cnt 0 2006.145.09:53:49.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:53:49.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:53:49.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:53:49.04#ibcon#[25=BW32\r\n] 2006.145.09:53:49.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:53:49.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.09:53:49.07#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.09:53:49.07#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.09:53:49.07$vck44/vbbw=wide 2006.145.09:53:49.07#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.09:53:49.07#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.09:53:49.07#ibcon#ireg 8 cls_cnt 0 2006.145.09:53:49.07#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.09:53:49.14#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.09:53:49.14#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.09:53:49.16#ibcon#[27=BW32\r\n] 2006.145.09:53:49.19#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.09:53:49.19#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.09:53:49.19#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.09:53:49.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.09:53:49.19$setupk4/ifdk4 2006.145.09:53:49.19$ifdk4/lo= 2006.145.09:53:49.19$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.09:53:49.19$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.09:53:49.19$ifdk4/patch= 2006.145.09:53:49.19$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.09:53:49.19$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.09:53:49.19$setupk4/!*+20s 2006.145.09:53:57.99#abcon#<5=/05 3.3 5.4 17.69 661018.8\r\n> 2006.145.09:53:58.01#abcon#{5=INTERFACE CLEAR} 2006.145.09:53:58.09#abcon#[5=S1D000X0/0*\r\n] 2006.145.09:54:03.14#trakl#Source acquired 2006.145.09:54:03.68$setupk4/"tpicd 2006.145.09:54:03.68$setupk4/echo=off 2006.145.09:54:03.68$setupk4/xlog=off 2006.145.09:54:03.68:!2006.145.09:56:29 2006.145.09:54:05.14#flagr#flagr/antenna,acquired 2006.145.09:56:29.00:preob 2006.145.09:56:30.13/onsource/TRACKING 2006.145.09:56:30.13:!2006.145.09:56:39 2006.145.09:56:39.00:"tape 2006.145.09:56:39.00:"st=record 2006.145.09:56:39.00:data_valid=on 2006.145.09:56:39.00:midob 2006.145.09:56:39.13/onsource/TRACKING 2006.145.09:56:39.13/wx/17.66,1018.8,67 2006.145.09:56:39.24/cable/+6.5431E-03 2006.145.09:56:40.33/va/01,08,usb,yes,28,30 2006.145.09:56:40.33/va/02,07,usb,yes,30,31 2006.145.09:56:40.33/va/03,08,usb,yes,27,28 2006.145.09:56:40.33/va/04,07,usb,yes,31,32 2006.145.09:56:40.33/va/05,04,usb,yes,27,27 2006.145.09:56:40.33/va/06,04,usb,yes,30,30 2006.145.09:56:40.33/va/07,04,usb,yes,30,32 2006.145.09:56:40.33/va/08,04,usb,yes,26,31 2006.145.09:56:40.56/valo/01,524.99,yes,locked 2006.145.09:56:40.56/valo/02,534.99,yes,locked 2006.145.09:56:40.56/valo/03,564.99,yes,locked 2006.145.09:56:40.56/valo/04,624.99,yes,locked 2006.145.09:56:40.56/valo/05,734.99,yes,locked 2006.145.09:56:40.56/valo/06,814.99,yes,locked 2006.145.09:56:40.56/valo/07,864.99,yes,locked 2006.145.09:56:40.56/valo/08,884.99,yes,locked 2006.145.09:56:41.65/vb/01,03,usb,yes,35,33 2006.145.09:56:41.65/vb/02,04,usb,yes,31,31 2006.145.09:56:41.65/vb/03,04,usb,yes,28,30 2006.145.09:56:41.65/vb/04,04,usb,yes,32,31 2006.145.09:56:41.65/vb/05,04,usb,yes,25,27 2006.145.09:56:41.65/vb/06,04,usb,yes,29,25 2006.145.09:56:41.65/vb/07,04,usb,yes,29,28 2006.145.09:56:41.65/vb/08,04,usb,yes,26,29 2006.145.09:56:41.88/vblo/01,629.99,yes,locked 2006.145.09:56:41.88/vblo/02,634.99,yes,locked 2006.145.09:56:41.88/vblo/03,649.99,yes,locked 2006.145.09:56:41.88/vblo/04,679.99,yes,locked 2006.145.09:56:41.88/vblo/05,709.99,yes,locked 2006.145.09:56:41.88/vblo/06,719.99,yes,locked 2006.145.09:56:41.88/vblo/07,734.99,yes,locked 2006.145.09:56:41.88/vblo/08,744.99,yes,locked 2006.145.09:56:42.03/vabw/8 2006.145.09:56:42.18/vbbw/8 2006.145.09:56:42.27/xfe/off,on,14.7 2006.145.09:56:42.64/ifatt/23,28,28,28 2006.145.09:56:43.08/fmout-gps/S +4.8E-08 2006.145.09:56:43.12:!2006.145.09:59:39 2006.145.09:59:39.00:data_valid=off 2006.145.09:59:39.00:"et 2006.145.09:59:39.00:!+3s 2006.145.09:59:42.02:"tape 2006.145.09:59:42.02:postob 2006.145.09:59:42.17/cable/+6.5437E-03 2006.145.09:59:42.17/wx/17.62,1018.9,67 2006.145.09:59:43.08/fmout-gps/S +4.8E-08 2006.145.09:59:43.08:scan_name=145-1002,jd0605,80 2006.145.09:59:43.08:source=1611+343,161341.06,341247.9,2000.0,cw 2006.145.09:59:43.14#flagr#flagr/antenna,new-source 2006.145.09:59:44.14:checkk5 2006.145.09:59:44.57/chk_autoobs//k5ts1/ autoobs is running! 2006.145.09:59:44.99/chk_autoobs//k5ts2/ autoobs is running! 2006.145.09:59:45.43/chk_autoobs//k5ts3/ autoobs is running! 2006.145.09:59:45.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.09:59:46.30/chk_obsdata//k5ts1/T1450956??a.dat file size is correct (nominal:720MB, actual:720MB). 2006.145.09:59:46.72/chk_obsdata//k5ts2/T1450956??b.dat file size is correct (nominal:720MB, actual:720MB). 2006.145.09:59:47.16/chk_obsdata//k5ts3/T1450956??c.dat file size is correct (nominal:720MB, actual:720MB). 2006.145.09:59:47.59/chk_obsdata//k5ts4/T1450956??d.dat file size is correct (nominal:720MB, actual:720MB). 2006.145.09:59:48.35/k5log//k5ts1_log_newline 2006.145.09:59:49.10/k5log//k5ts2_log_newline 2006.145.09:59:50.90/k5log//k5ts3_log_newline 2006.145.09:59:51.63/k5log//k5ts4_log_newline 2006.145.09:59:51.66/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.09:59:51.66:setupk4=1 2006.145.09:59:51.66$setupk4/echo=on 2006.145.09:59:51.66$setupk4/pcalon 2006.145.09:59:51.66$pcalon/"no phase cal control is implemented here 2006.145.09:59:51.66$setupk4/"tpicd=stop 2006.145.09:59:51.66$setupk4/"rec=synch_on 2006.145.09:59:51.66$setupk4/"rec_mode=128 2006.145.09:59:51.66$setupk4/!* 2006.145.09:59:51.66$setupk4/recpk4 2006.145.09:59:51.66$recpk4/recpatch= 2006.145.09:59:51.66$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.09:59:51.66$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.09:59:51.66$setupk4/vck44 2006.145.09:59:51.66$vck44/valo=1,524.99 2006.145.09:59:51.66#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.09:59:51.66#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.09:59:51.66#ibcon#ireg 17 cls_cnt 0 2006.145.09:59:51.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.09:59:51.66#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.09:59:51.66#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.09:59:51.68#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.09:59:51.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.09:59:51.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.09:59:51.73#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.09:59:51.73#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.09:59:51.73$vck44/va=1,8 2006.145.09:59:51.73#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.09:59:51.73#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.09:59:51.73#ibcon#ireg 11 cls_cnt 2 2006.145.09:59:51.73#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.09:59:51.73#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.09:59:51.73#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.09:59:51.75#ibcon#[25=AT01-08\r\n] 2006.145.09:59:51.78#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.09:59:51.78#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.09:59:51.78#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.09:59:51.78#ibcon#ireg 7 cls_cnt 0 2006.145.09:59:51.78#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.09:59:51.90#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.09:59:51.90#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.09:59:51.92#ibcon#[25=USB\r\n] 2006.145.09:59:51.96#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.09:59:51.96#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.09:59:51.96#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.09:59:51.96#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.09:59:51.97$vck44/valo=2,534.99 2006.145.09:59:51.97#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.09:59:51.97#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.09:59:51.97#ibcon#ireg 17 cls_cnt 0 2006.145.09:59:51.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.09:59:51.97#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.09:59:51.97#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.09:59:51.98#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.09:59:52.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.09:59:52.02#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.09:59:52.02#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.09:59:52.02#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.09:59:52.02$vck44/va=2,7 2006.145.09:59:52.02#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.09:59:52.02#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.09:59:52.02#ibcon#ireg 11 cls_cnt 2 2006.145.09:59:52.02#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.09:59:52.08#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.09:59:52.08#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.09:59:52.10#ibcon#[25=AT02-07\r\n] 2006.145.09:59:52.13#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.09:59:52.13#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.09:59:52.13#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.09:59:52.13#ibcon#ireg 7 cls_cnt 0 2006.145.09:59:52.13#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.09:59:52.25#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.09:59:52.25#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.09:59:52.27#ibcon#[25=USB\r\n] 2006.145.09:59:52.30#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.09:59:52.30#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.09:59:52.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.09:59:52.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.09:59:52.30$vck44/valo=3,564.99 2006.145.09:59:52.30#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.09:59:52.30#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.09:59:52.30#ibcon#ireg 17 cls_cnt 0 2006.145.09:59:52.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.09:59:52.30#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.09:59:52.30#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.09:59:52.32#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.09:59:52.36#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.09:59:52.36#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.09:59:52.36#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.09:59:52.36#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.09:59:52.36$vck44/va=3,8 2006.145.09:59:52.36#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.09:59:52.36#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.09:59:52.36#ibcon#ireg 11 cls_cnt 2 2006.145.09:59:52.36#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.09:59:52.42#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.09:59:52.42#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.09:59:52.44#ibcon#[25=AT03-08\r\n] 2006.145.09:59:52.47#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.09:59:52.47#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.09:59:52.47#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.09:59:52.47#ibcon#ireg 7 cls_cnt 0 2006.145.09:59:52.47#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.09:59:52.59#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.09:59:52.59#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.09:59:52.61#ibcon#[25=USB\r\n] 2006.145.09:59:52.64#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.09:59:52.64#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.09:59:52.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.09:59:52.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.09:59:52.64$vck44/valo=4,624.99 2006.145.09:59:52.64#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.09:59:52.64#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.09:59:52.64#ibcon#ireg 17 cls_cnt 0 2006.145.09:59:52.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.09:59:52.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.09:59:52.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.09:59:52.66#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.09:59:52.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.09:59:52.70#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.09:59:52.70#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.09:59:52.70#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.09:59:52.70$vck44/va=4,7 2006.145.09:59:52.70#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.09:59:52.70#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.09:59:52.70#ibcon#ireg 11 cls_cnt 2 2006.145.09:59:52.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.09:59:52.76#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.09:59:52.76#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.09:59:52.78#ibcon#[25=AT04-07\r\n] 2006.145.09:59:52.81#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.09:59:52.81#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.09:59:52.81#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.09:59:52.81#ibcon#ireg 7 cls_cnt 0 2006.145.09:59:52.81#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.09:59:52.93#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.09:59:52.93#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.09:59:52.95#ibcon#[25=USB\r\n] 2006.145.09:59:52.98#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.09:59:52.98#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.09:59:52.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.09:59:52.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.09:59:52.98$vck44/valo=5,734.99 2006.145.09:59:52.98#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.09:59:52.98#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.09:59:52.98#ibcon#ireg 17 cls_cnt 0 2006.145.09:59:52.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.09:59:52.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.09:59:52.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.09:59:53.00#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.09:59:53.04#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.09:59:53.04#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.09:59:53.04#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.09:59:53.04#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.09:59:53.04$vck44/va=5,4 2006.145.09:59:53.04#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.09:59:53.04#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.09:59:53.04#ibcon#ireg 11 cls_cnt 2 2006.145.09:59:53.04#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.09:59:53.10#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.09:59:53.10#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.09:59:53.12#ibcon#[25=AT05-04\r\n] 2006.145.09:59:53.15#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.09:59:53.15#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.09:59:53.15#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.09:59:53.15#ibcon#ireg 7 cls_cnt 0 2006.145.09:59:53.15#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.09:59:53.27#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.09:59:53.27#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.09:59:53.29#ibcon#[25=USB\r\n] 2006.145.09:59:53.32#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.09:59:53.32#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.09:59:53.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.09:59:53.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.09:59:53.32$vck44/valo=6,814.99 2006.145.09:59:53.32#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.09:59:53.32#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.09:59:53.32#ibcon#ireg 17 cls_cnt 0 2006.145.09:59:53.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.09:59:53.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.09:59:53.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.09:59:53.34#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.09:59:53.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.09:59:53.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.09:59:53.38#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.09:59:53.38#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.09:59:53.38$vck44/va=6,4 2006.145.09:59:53.38#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.09:59:53.38#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.09:59:53.38#ibcon#ireg 11 cls_cnt 2 2006.145.09:59:53.38#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.09:59:53.44#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.09:59:53.44#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.09:59:53.46#ibcon#[25=AT06-04\r\n] 2006.145.09:59:53.49#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.09:59:53.49#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.09:59:53.49#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.09:59:53.49#ibcon#ireg 7 cls_cnt 0 2006.145.09:59:53.49#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.09:59:53.61#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.09:59:53.61#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.09:59:53.63#ibcon#[25=USB\r\n] 2006.145.09:59:53.66#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.09:59:53.66#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.09:59:53.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.09:59:53.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.09:59:53.66$vck44/valo=7,864.99 2006.145.09:59:53.66#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.09:59:53.66#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.09:59:53.66#ibcon#ireg 17 cls_cnt 0 2006.145.09:59:53.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.09:59:53.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.09:59:53.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.09:59:53.68#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.09:59:53.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.09:59:53.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.09:59:53.72#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.09:59:53.72#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.09:59:53.72$vck44/va=7,4 2006.145.09:59:53.72#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.09:59:53.72#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.09:59:53.72#ibcon#ireg 11 cls_cnt 2 2006.145.09:59:53.72#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.09:59:53.78#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.09:59:53.78#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.09:59:53.80#ibcon#[25=AT07-04\r\n] 2006.145.09:59:53.83#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.09:59:53.83#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.09:59:53.83#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.09:59:53.83#ibcon#ireg 7 cls_cnt 0 2006.145.09:59:53.83#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.09:59:53.95#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.09:59:53.95#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.09:59:53.97#ibcon#[25=USB\r\n] 2006.145.09:59:54.00#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.09:59:54.00#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.09:59:54.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.09:59:54.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.09:59:54.00$vck44/valo=8,884.99 2006.145.09:59:54.00#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.09:59:54.00#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.09:59:54.00#ibcon#ireg 17 cls_cnt 0 2006.145.09:59:54.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.09:59:54.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.09:59:54.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.09:59:54.02#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.09:59:54.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.09:59:54.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.09:59:54.06#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.09:59:54.06#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.09:59:54.06$vck44/va=8,4 2006.145.09:59:54.06#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.09:59:54.06#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.09:59:54.06#ibcon#ireg 11 cls_cnt 2 2006.145.09:59:54.06#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:59:54.07#abcon#<5=/05 3.1 5.3 17.61 671018.9\r\n> 2006.145.09:59:54.09#abcon#{5=INTERFACE CLEAR} 2006.145.09:59:54.12#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:59:54.12#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:59:54.14#ibcon#[25=AT08-04\r\n] 2006.145.09:59:54.15#abcon#[5=S1D000X0/0*\r\n] 2006.145.09:59:54.17#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:59:54.17#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.09:59:54.17#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.09:59:54.17#ibcon#ireg 7 cls_cnt 0 2006.145.09:59:54.17#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:59:54.29#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:59:54.29#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:59:54.33#ibcon#[25=USB\r\n] 2006.145.09:59:54.36#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:59:54.36#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.09:59:54.36#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.09:59:54.36#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.09:59:54.36$vck44/vblo=1,629.99 2006.145.09:59:54.36#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.09:59:54.36#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.09:59:54.36#ibcon#ireg 17 cls_cnt 0 2006.145.09:59:54.36#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.09:59:54.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.09:59:54.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.09:59:54.38#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.09:59:54.42#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.09:59:54.42#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.09:59:54.42#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.09:59:54.42#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.09:59:54.42$vck44/vb=1,3 2006.145.09:59:54.42#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.09:59:54.42#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.09:59:54.42#ibcon#ireg 11 cls_cnt 2 2006.145.09:59:54.42#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.09:59:54.42#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.09:59:54.42#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.09:59:54.44#ibcon#[27=AT01-03\r\n] 2006.145.09:59:54.47#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.09:59:54.47#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.09:59:54.47#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.09:59:54.47#ibcon#ireg 7 cls_cnt 0 2006.145.09:59:54.47#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.09:59:54.59#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.09:59:54.59#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.09:59:54.61#ibcon#[27=USB\r\n] 2006.145.09:59:54.64#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.09:59:54.64#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.09:59:54.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.09:59:54.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.09:59:54.64$vck44/vblo=2,634.99 2006.145.09:59:54.64#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.09:59:54.64#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.09:59:54.64#ibcon#ireg 17 cls_cnt 0 2006.145.09:59:54.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.09:59:54.64#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.09:59:54.64#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.09:59:54.66#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.09:59:54.70#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.09:59:54.70#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.09:59:54.70#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.09:59:54.70#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.09:59:54.70$vck44/vb=2,4 2006.145.09:59:54.70#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.09:59:54.70#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.09:59:54.70#ibcon#ireg 11 cls_cnt 2 2006.145.09:59:54.70#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.09:59:54.76#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.09:59:54.76#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.09:59:54.78#ibcon#[27=AT02-04\r\n] 2006.145.09:59:54.81#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.09:59:54.81#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.09:59:54.81#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.09:59:54.81#ibcon#ireg 7 cls_cnt 0 2006.145.09:59:54.81#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.09:59:54.93#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.09:59:54.93#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.09:59:54.95#ibcon#[27=USB\r\n] 2006.145.09:59:54.98#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.09:59:54.98#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.09:59:54.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.09:59:54.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.09:59:54.98$vck44/vblo=3,649.99 2006.145.09:59:54.98#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.09:59:54.98#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.09:59:54.98#ibcon#ireg 17 cls_cnt 0 2006.145.09:59:54.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.09:59:54.98#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.09:59:54.98#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.09:59:55.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.09:59:55.04#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.09:59:55.04#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.09:59:55.04#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.09:59:55.04#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.09:59:55.04$vck44/vb=3,4 2006.145.09:59:55.04#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.09:59:55.04#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.09:59:55.04#ibcon#ireg 11 cls_cnt 2 2006.145.09:59:55.04#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.09:59:55.10#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.09:59:55.10#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.09:59:55.12#ibcon#[27=AT03-04\r\n] 2006.145.09:59:55.15#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.09:59:55.15#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.09:59:55.15#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.09:59:55.15#ibcon#ireg 7 cls_cnt 0 2006.145.09:59:55.15#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.09:59:55.27#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.09:59:55.27#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.09:59:55.29#ibcon#[27=USB\r\n] 2006.145.09:59:55.32#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.09:59:55.32#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.09:59:55.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.09:59:55.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.09:59:55.32$vck44/vblo=4,679.99 2006.145.09:59:55.32#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.09:59:55.32#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.09:59:55.32#ibcon#ireg 17 cls_cnt 0 2006.145.09:59:55.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.09:59:55.32#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.09:59:55.32#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.09:59:55.34#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.09:59:55.38#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.09:59:55.38#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.09:59:55.38#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.09:59:55.38#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.09:59:55.38$vck44/vb=4,4 2006.145.09:59:55.38#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.09:59:55.38#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.09:59:55.38#ibcon#ireg 11 cls_cnt 2 2006.145.09:59:55.38#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.09:59:55.44#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.09:59:55.44#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.09:59:55.46#ibcon#[27=AT04-04\r\n] 2006.145.09:59:55.49#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.09:59:55.49#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.09:59:55.49#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.09:59:55.49#ibcon#ireg 7 cls_cnt 0 2006.145.09:59:55.49#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.09:59:55.61#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.09:59:55.61#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.09:59:55.63#ibcon#[27=USB\r\n] 2006.145.09:59:55.66#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.09:59:55.66#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.09:59:55.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.09:59:55.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.09:59:55.66$vck44/vblo=5,709.99 2006.145.09:59:55.66#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.09:59:55.66#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.09:59:55.66#ibcon#ireg 17 cls_cnt 0 2006.145.09:59:55.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.09:59:55.66#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.09:59:55.66#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.09:59:55.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.09:59:55.72#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.09:59:55.72#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.09:59:55.72#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.09:59:55.72#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.09:59:55.72$vck44/vb=5,4 2006.145.09:59:55.72#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.09:59:55.72#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.09:59:55.72#ibcon#ireg 11 cls_cnt 2 2006.145.09:59:55.72#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.09:59:55.78#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.09:59:55.78#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.09:59:55.80#ibcon#[27=AT05-04\r\n] 2006.145.09:59:55.83#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.09:59:55.83#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.09:59:55.83#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.09:59:55.83#ibcon#ireg 7 cls_cnt 0 2006.145.09:59:55.83#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.09:59:55.95#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.09:59:55.95#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.09:59:55.97#ibcon#[27=USB\r\n] 2006.145.09:59:56.00#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.09:59:56.00#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.09:59:56.00#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.09:59:56.00#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.09:59:56.00$vck44/vblo=6,719.99 2006.145.09:59:56.00#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.09:59:56.00#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.09:59:56.00#ibcon#ireg 17 cls_cnt 0 2006.145.09:59:56.00#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.09:59:56.00#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.09:59:56.00#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.09:59:56.02#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.09:59:56.06#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.09:59:56.06#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.09:59:56.06#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.09:59:56.06#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.09:59:56.06$vck44/vb=6,4 2006.145.09:59:56.06#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.09:59:56.06#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.09:59:56.06#ibcon#ireg 11 cls_cnt 2 2006.145.09:59:56.06#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.09:59:56.12#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.09:59:56.12#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.09:59:56.14#ibcon#[27=AT06-04\r\n] 2006.145.09:59:56.17#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.09:59:56.17#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.09:59:56.17#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.09:59:56.17#ibcon#ireg 7 cls_cnt 0 2006.145.09:59:56.17#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.09:59:56.29#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.09:59:56.29#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.09:59:56.31#ibcon#[27=USB\r\n] 2006.145.09:59:56.34#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.09:59:56.34#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.09:59:56.34#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.09:59:56.34#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.09:59:56.34$vck44/vblo=7,734.99 2006.145.09:59:56.34#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.09:59:56.34#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.09:59:56.34#ibcon#ireg 17 cls_cnt 0 2006.145.09:59:56.34#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.09:59:56.34#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.09:59:56.34#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.09:59:56.36#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.09:59:56.40#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.09:59:56.40#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.09:59:56.40#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.09:59:56.40#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.09:59:56.40$vck44/vb=7,4 2006.145.09:59:56.40#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.09:59:56.40#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.09:59:56.40#ibcon#ireg 11 cls_cnt 2 2006.145.09:59:56.40#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.09:59:56.46#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.09:59:56.46#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.09:59:56.48#ibcon#[27=AT07-04\r\n] 2006.145.09:59:56.51#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.09:59:56.51#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.09:59:56.51#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.09:59:56.51#ibcon#ireg 7 cls_cnt 0 2006.145.09:59:56.51#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.09:59:56.63#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.09:59:56.63#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.09:59:56.65#ibcon#[27=USB\r\n] 2006.145.09:59:56.68#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.09:59:56.68#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.09:59:56.68#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.09:59:56.68#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.09:59:56.68$vck44/vblo=8,744.99 2006.145.09:59:56.68#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.09:59:56.68#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.09:59:56.68#ibcon#ireg 17 cls_cnt 0 2006.145.09:59:56.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.09:59:56.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.09:59:56.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.09:59:56.70#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.09:59:56.74#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.09:59:56.74#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.09:59:56.74#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.09:59:56.74#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.09:59:56.74$vck44/vb=8,4 2006.145.09:59:56.74#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.09:59:56.74#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.09:59:56.74#ibcon#ireg 11 cls_cnt 2 2006.145.09:59:56.74#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.09:59:56.80#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.09:59:56.80#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.09:59:56.82#ibcon#[27=AT08-04\r\n] 2006.145.09:59:56.85#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.09:59:56.85#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.09:59:56.85#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.09:59:56.85#ibcon#ireg 7 cls_cnt 0 2006.145.09:59:56.85#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.09:59:56.97#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.09:59:56.97#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.09:59:56.99#ibcon#[27=USB\r\n] 2006.145.09:59:57.02#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.09:59:57.02#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.09:59:57.02#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.09:59:57.02#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.09:59:57.02$vck44/vabw=wide 2006.145.09:59:57.02#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.09:59:57.02#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.09:59:57.02#ibcon#ireg 8 cls_cnt 0 2006.145.09:59:57.02#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.09:59:57.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.09:59:57.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.09:59:57.04#ibcon#[25=BW32\r\n] 2006.145.09:59:57.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.09:59:57.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.09:59:57.07#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.09:59:57.07#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.09:59:57.07$vck44/vbbw=wide 2006.145.09:59:57.07#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.09:59:57.07#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.09:59:57.07#ibcon#ireg 8 cls_cnt 0 2006.145.09:59:57.07#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.09:59:57.14#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.09:59:57.14#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.09:59:57.16#ibcon#[27=BW32\r\n] 2006.145.09:59:57.19#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.09:59:57.19#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.09:59:57.19#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.09:59:57.19#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.09:59:57.19$setupk4/ifdk4 2006.145.09:59:57.19$ifdk4/lo= 2006.145.09:59:57.19$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.09:59:57.19$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.09:59:57.19$ifdk4/patch= 2006.145.09:59:57.19$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.09:59:57.19$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.09:59:57.19$setupk4/!*+20s 2006.145.10:00:04.24#abcon#<5=/05 3.1 5.3 17.61 671018.9\r\n> 2006.145.10:00:04.26#abcon#{5=INTERFACE CLEAR} 2006.145.10:00:04.32#abcon#[5=S1D000X0/0*\r\n] 2006.145.10:00:11.67$setupk4/"tpicd 2006.145.10:00:11.67$setupk4/echo=off 2006.145.10:00:11.67$setupk4/xlog=off 2006.145.10:00:11.67:!2006.145.10:02:15 2006.145.10:00:17.14#trakl#Source acquired 2006.145.10:00:19.14#flagr#flagr/antenna,acquired 2006.145.10:02:15.00:preob 2006.145.10:02:15.14/onsource/TRACKING 2006.145.10:02:15.14:!2006.145.10:02:25 2006.145.10:02:25.00:"tape 2006.145.10:02:25.00:"st=record 2006.145.10:02:25.00:data_valid=on 2006.145.10:02:25.00:midob 2006.145.10:02:25.14/onsource/TRACKING 2006.145.10:02:25.14/wx/17.59,1018.9,67 2006.145.10:02:25.26/cable/+6.5443E-03 2006.145.10:02:26.35/va/01,08,usb,yes,29,31 2006.145.10:02:26.35/va/02,07,usb,yes,31,32 2006.145.10:02:26.35/va/03,08,usb,yes,28,29 2006.145.10:02:26.35/va/04,07,usb,yes,32,34 2006.145.10:02:26.35/va/05,04,usb,yes,28,28 2006.145.10:02:26.35/va/06,04,usb,yes,31,31 2006.145.10:02:26.35/va/07,04,usb,yes,32,33 2006.145.10:02:26.35/va/08,04,usb,yes,27,32 2006.145.10:02:26.58/valo/01,524.99,yes,locked 2006.145.10:02:26.58/valo/02,534.99,yes,locked 2006.145.10:02:26.58/valo/03,564.99,yes,locked 2006.145.10:02:26.58/valo/04,624.99,yes,locked 2006.145.10:02:26.58/valo/05,734.99,yes,locked 2006.145.10:02:26.58/valo/06,814.99,yes,locked 2006.145.10:02:26.58/valo/07,864.99,yes,locked 2006.145.10:02:26.58/valo/08,884.99,yes,locked 2006.145.10:02:27.67/vb/01,03,usb,yes,36,33 2006.145.10:02:27.67/vb/02,04,usb,yes,31,31 2006.145.10:02:27.67/vb/03,04,usb,yes,28,31 2006.145.10:02:27.67/vb/04,04,usb,yes,33,32 2006.145.10:02:27.67/vb/05,04,usb,yes,25,28 2006.145.10:02:27.67/vb/06,04,usb,yes,30,26 2006.145.10:02:27.67/vb/07,04,usb,yes,29,29 2006.145.10:02:27.67/vb/08,04,usb,yes,27,30 2006.145.10:02:27.90/vblo/01,629.99,yes,locked 2006.145.10:02:27.90/vblo/02,634.99,yes,locked 2006.145.10:02:27.90/vblo/03,649.99,yes,locked 2006.145.10:02:27.90/vblo/04,679.99,yes,locked 2006.145.10:02:27.90/vblo/05,709.99,yes,locked 2006.145.10:02:27.90/vblo/06,719.99,yes,locked 2006.145.10:02:27.90/vblo/07,734.99,yes,locked 2006.145.10:02:27.90/vblo/08,744.99,yes,locked 2006.145.10:02:28.05/vabw/8 2006.145.10:02:28.20/vbbw/8 2006.145.10:02:28.29/xfe/off,on,14.5 2006.145.10:02:28.67/ifatt/23,28,28,28 2006.145.10:02:29.07/fmout-gps/S +4.9E-08 2006.145.10:02:29.11:!2006.145.10:03:45 2006.145.10:03:45.00:data_valid=off 2006.145.10:03:45.00:"et 2006.145.10:03:45.00:!+3s 2006.145.10:03:48.02:"tape 2006.145.10:03:48.02:postob 2006.145.10:03:48.21/cable/+6.5429E-03 2006.145.10:03:48.21/wx/17.57,1018.9,66 2006.145.10:03:49.08/fmout-gps/S +4.8E-08 2006.145.10:03:49.08:scan_name=145-1005,jd0605,720 2006.145.10:03:49.08:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.145.10:03:50.13#flagr#flagr/antenna,new-source 2006.145.10:03:50.13:checkk5 2006.145.10:03:50.57/chk_autoobs//k5ts1/ autoobs is running! 2006.145.10:03:51.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.10:03:51.45/chk_autoobs//k5ts3/ autoobs is running! 2006.145.10:03:51.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.10:03:52.33/chk_obsdata//k5ts1/T1451002??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.10:03:52.78/chk_obsdata//k5ts2/T1451002??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.10:03:53.21/chk_obsdata//k5ts3/T1451002??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.10:03:53.64/chk_obsdata//k5ts4/T1451002??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.10:03:54.40/k5log//k5ts1_log_newline 2006.145.10:03:55.15/k5log//k5ts2_log_newline 2006.145.10:03:55.88/k5log//k5ts3_log_newline 2006.145.10:03:56.62/k5log//k5ts4_log_newline 2006.145.10:03:56.64/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.10:03:56.64:setupk4=1 2006.145.10:03:56.64$setupk4/echo=on 2006.145.10:03:56.64$setupk4/pcalon 2006.145.10:03:56.64$pcalon/"no phase cal control is implemented here 2006.145.10:03:56.64$setupk4/"tpicd=stop 2006.145.10:03:56.64$setupk4/"rec=synch_on 2006.145.10:03:56.64$setupk4/"rec_mode=128 2006.145.10:03:56.64$setupk4/!* 2006.145.10:03:56.64$setupk4/recpk4 2006.145.10:03:56.64$recpk4/recpatch= 2006.145.10:03:56.65$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.10:03:56.65$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.10:03:56.65$setupk4/vck44 2006.145.10:03:56.65$vck44/valo=1,524.99 2006.145.10:03:56.65#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.10:03:56.65#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.10:03:56.65#ibcon#ireg 17 cls_cnt 0 2006.145.10:03:56.65#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.10:03:56.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.10:03:56.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.10:03:56.69#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.10:03:56.74#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.10:03:56.74#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.10:03:56.74#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.10:03:56.74#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.10:03:56.74$vck44/va=1,8 2006.145.10:03:56.74#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.10:03:56.74#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.10:03:56.74#ibcon#ireg 11 cls_cnt 2 2006.145.10:03:56.74#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.10:03:56.74#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.10:03:56.74#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.10:03:56.76#ibcon#[25=AT01-08\r\n] 2006.145.10:03:56.79#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.10:03:56.79#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.10:03:56.79#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.10:03:56.79#ibcon#ireg 7 cls_cnt 0 2006.145.10:03:56.79#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.10:03:56.90#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.10:03:56.91#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.10:03:56.93#ibcon#[25=USB\r\n] 2006.145.10:03:56.96#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.10:03:56.96#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.10:03:56.96#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.10:03:56.96#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.10:03:56.96$vck44/valo=2,534.99 2006.145.10:03:56.96#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.10:03:56.96#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.10:03:56.96#ibcon#ireg 17 cls_cnt 0 2006.145.10:03:56.96#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.10:03:56.96#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.10:03:56.96#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.10:03:56.99#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.10:03:57.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.10:03:57.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.10:03:57.03#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.10:03:57.03#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.10:03:57.03$vck44/va=2,7 2006.145.10:03:57.03#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.10:03:57.03#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.10:03:57.03#ibcon#ireg 11 cls_cnt 2 2006.145.10:03:57.03#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.10:03:57.07#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.10:03:57.08#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.10:03:57.10#ibcon#[25=AT02-07\r\n] 2006.145.10:03:57.13#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.10:03:57.13#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.10:03:57.13#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.10:03:57.13#ibcon#ireg 7 cls_cnt 0 2006.145.10:03:57.13#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.10:03:57.24#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.10:03:57.25#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.10:03:57.27#ibcon#[25=USB\r\n] 2006.145.10:03:57.30#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.10:03:57.30#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.10:03:57.30#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.10:03:57.30#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.10:03:57.30$vck44/valo=3,564.99 2006.145.10:03:57.30#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.10:03:57.30#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.10:03:57.30#ibcon#ireg 17 cls_cnt 0 2006.145.10:03:57.30#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.10:03:57.30#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.10:03:57.30#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.10:03:57.32#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.10:03:57.36#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.10:03:57.36#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.10:03:57.36#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.10:03:57.36#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.10:03:57.36$vck44/va=3,8 2006.145.10:03:57.36#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.10:03:57.36#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.10:03:57.36#ibcon#ireg 11 cls_cnt 2 2006.145.10:03:57.36#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.10:03:57.41#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.10:03:57.42#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.10:03:57.44#ibcon#[25=AT03-08\r\n] 2006.145.10:03:57.47#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.10:03:57.47#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.10:03:57.47#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.10:03:57.47#ibcon#ireg 7 cls_cnt 0 2006.145.10:03:57.47#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.10:03:57.58#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.10:03:57.59#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.10:03:57.61#ibcon#[25=USB\r\n] 2006.145.10:03:57.64#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.10:03:57.64#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.10:03:57.64#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.10:03:57.64#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.10:03:57.64$vck44/valo=4,624.99 2006.145.10:03:57.64#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.10:03:57.64#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.10:03:57.64#ibcon#ireg 17 cls_cnt 0 2006.145.10:03:57.64#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.10:03:57.64#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.10:03:57.64#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.10:03:57.66#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.10:03:57.70#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.10:03:57.70#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.10:03:57.70#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.10:03:57.70#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.10:03:57.70$vck44/va=4,7 2006.145.10:03:57.70#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.10:03:57.70#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.10:03:57.70#ibcon#ireg 11 cls_cnt 2 2006.145.10:03:57.70#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.10:03:57.75#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.10:03:57.76#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.10:03:57.77#ibcon#[25=AT04-07\r\n] 2006.145.10:03:57.81#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.10:03:57.81#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.10:03:57.81#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.10:03:57.81#ibcon#ireg 7 cls_cnt 0 2006.145.10:03:57.81#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.10:03:57.92#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.10:03:57.93#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.10:03:57.94#ibcon#[25=USB\r\n] 2006.145.10:03:57.98#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.10:03:57.98#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.10:03:57.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.10:03:57.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.10:03:57.98$vck44/valo=5,734.99 2006.145.10:03:57.98#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.10:03:57.98#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.10:03:57.98#ibcon#ireg 17 cls_cnt 0 2006.145.10:03:57.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.10:03:57.98#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.10:03:57.98#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.10:03:58.00#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.10:03:58.04#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.10:03:58.04#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.10:03:58.04#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.10:03:58.04#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.10:03:58.04$vck44/va=5,4 2006.145.10:03:58.04#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.10:03:58.04#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.10:03:58.04#ibcon#ireg 11 cls_cnt 2 2006.145.10:03:58.04#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.10:03:58.09#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.10:03:58.10#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.10:03:58.12#ibcon#[25=AT05-04\r\n] 2006.145.10:03:58.15#abcon#<5=/05 2.9 5.1 17.57 661018.9\r\n> 2006.145.10:03:58.15#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.10:03:58.15#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.10:03:58.15#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.10:03:58.15#ibcon#ireg 7 cls_cnt 0 2006.145.10:03:58.15#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.10:03:58.17#abcon#{5=INTERFACE CLEAR} 2006.145.10:03:58.23#abcon#[5=S1D000X0/0*\r\n] 2006.145.10:03:58.27#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.10:03:58.27#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.10:03:58.29#ibcon#[25=USB\r\n] 2006.145.10:03:58.32#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.10:03:58.32#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.10:03:58.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.10:03:58.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.10:03:58.32$vck44/valo=6,814.99 2006.145.10:03:58.32#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.10:03:58.32#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.10:03:58.32#ibcon#ireg 17 cls_cnt 0 2006.145.10:03:58.32#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:03:58.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:03:58.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:03:58.35#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.10:03:58.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:03:58.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:03:58.39#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.10:03:58.39#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.10:03:58.39$vck44/va=6,4 2006.145.10:03:58.39#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.10:03:58.39#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.10:03:58.39#ibcon#ireg 11 cls_cnt 2 2006.145.10:03:58.39#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.10:03:58.43#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.10:03:58.44#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.10:03:58.45#ibcon#[25=AT06-04\r\n] 2006.145.10:03:58.49#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.10:03:58.49#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.10:03:58.49#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.10:03:58.49#ibcon#ireg 7 cls_cnt 0 2006.145.10:03:58.49#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.10:03:58.60#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.10:03:58.61#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.10:03:58.63#ibcon#[25=USB\r\n] 2006.145.10:03:58.66#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.10:03:58.66#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.10:03:58.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.10:03:58.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.10:03:58.66$vck44/valo=7,864.99 2006.145.10:03:58.66#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.10:03:58.66#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.10:03:58.66#ibcon#ireg 17 cls_cnt 0 2006.145.10:03:58.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.10:03:58.66#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.10:03:58.66#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.10:03:58.68#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.10:03:58.72#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.10:03:58.72#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.10:03:58.72#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.10:03:58.72#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.10:03:58.72$vck44/va=7,4 2006.145.10:03:58.72#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.10:03:58.72#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.10:03:58.72#ibcon#ireg 11 cls_cnt 2 2006.145.10:03:58.72#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.10:03:58.77#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.10:03:58.78#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.10:03:58.80#ibcon#[25=AT07-04\r\n] 2006.145.10:03:58.83#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.10:03:58.83#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.10:03:58.83#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.10:03:58.83#ibcon#ireg 7 cls_cnt 0 2006.145.10:03:58.83#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.10:03:58.94#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.10:03:58.95#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.10:03:58.97#ibcon#[25=USB\r\n] 2006.145.10:03:59.00#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.10:03:59.00#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.10:03:59.00#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.10:03:59.00#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.10:03:59.00$vck44/valo=8,884.99 2006.145.10:03:59.00#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.10:03:59.00#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.10:03:59.00#ibcon#ireg 17 cls_cnt 0 2006.145.10:03:59.00#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.10:03:59.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.10:03:59.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.10:03:59.02#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.10:03:59.06#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.10:03:59.06#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.10:03:59.06#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.10:03:59.06#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.10:03:59.06$vck44/va=8,4 2006.145.10:03:59.06#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.10:03:59.06#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.10:03:59.06#ibcon#ireg 11 cls_cnt 2 2006.145.10:03:59.06#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.10:03:59.11#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.10:03:59.12#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.10:03:59.14#ibcon#[25=AT08-04\r\n] 2006.145.10:03:59.16#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.10:03:59.17#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.10:03:59.17#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.10:03:59.17#ibcon#ireg 7 cls_cnt 0 2006.145.10:03:59.17#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.10:03:59.28#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.10:03:59.29#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.10:03:59.30#ibcon#[25=USB\r\n] 2006.145.10:03:59.34#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.10:03:59.34#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.10:03:59.34#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.10:03:59.34#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.10:03:59.34$vck44/vblo=1,629.99 2006.145.10:03:59.34#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.10:03:59.34#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.10:03:59.34#ibcon#ireg 17 cls_cnt 0 2006.145.10:03:59.34#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.10:03:59.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.10:03:59.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.10:03:59.35#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.10:03:59.40#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.10:03:59.40#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.10:03:59.40#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.10:03:59.40#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.10:03:59.40$vck44/vb=1,3 2006.145.10:03:59.40#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.10:03:59.40#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.10:03:59.40#ibcon#ireg 11 cls_cnt 2 2006.145.10:03:59.40#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.10:03:59.40#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.10:03:59.40#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.10:03:59.42#ibcon#[27=AT01-03\r\n] 2006.145.10:03:59.45#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.10:03:59.45#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.10:03:59.45#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.10:03:59.45#ibcon#ireg 7 cls_cnt 0 2006.145.10:03:59.45#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.10:03:59.56#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.10:03:59.57#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.10:03:59.59#ibcon#[27=USB\r\n] 2006.145.10:03:59.62#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.10:03:59.62#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.10:03:59.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.10:03:59.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.10:03:59.62$vck44/vblo=2,634.99 2006.145.10:03:59.62#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.10:03:59.62#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.10:03:59.62#ibcon#ireg 17 cls_cnt 0 2006.145.10:03:59.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.10:03:59.62#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.10:03:59.62#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.10:03:59.64#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.10:03:59.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.10:03:59.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.10:03:59.68#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.10:03:59.68#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.10:03:59.68$vck44/vb=2,4 2006.145.10:03:59.68#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.10:03:59.68#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.10:03:59.68#ibcon#ireg 11 cls_cnt 2 2006.145.10:03:59.68#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.10:03:59.73#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.10:03:59.74#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.10:03:59.76#ibcon#[27=AT02-04\r\n] 2006.145.10:03:59.79#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.10:03:59.79#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.10:03:59.79#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.10:03:59.79#ibcon#ireg 7 cls_cnt 0 2006.145.10:03:59.79#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.10:03:59.90#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.10:03:59.91#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.10:03:59.93#ibcon#[27=USB\r\n] 2006.145.10:03:59.95#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.10:03:59.96#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.10:03:59.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.10:03:59.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.10:03:59.96$vck44/vblo=3,649.99 2006.145.10:03:59.96#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.10:03:59.96#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.10:03:59.96#ibcon#ireg 17 cls_cnt 0 2006.145.10:03:59.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.10:03:59.96#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.10:03:59.96#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.10:03:59.98#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.10:04:00.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.10:04:00.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.10:04:00.02#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.10:04:00.02#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.10:04:00.02$vck44/vb=3,4 2006.145.10:04:00.02#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.10:04:00.02#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.10:04:00.02#ibcon#ireg 11 cls_cnt 2 2006.145.10:04:00.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.10:04:00.07#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.10:04:00.08#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.10:04:00.09#ibcon#[27=AT03-04\r\n] 2006.145.10:04:00.13#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.10:04:00.13#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.10:04:00.13#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.10:04:00.13#ibcon#ireg 7 cls_cnt 0 2006.145.10:04:00.13#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.10:04:00.24#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.10:04:00.25#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.10:04:00.26#ibcon#[27=USB\r\n] 2006.145.10:04:00.30#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.10:04:00.30#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.10:04:00.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.10:04:00.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.10:04:00.30$vck44/vblo=4,679.99 2006.145.10:04:00.30#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.10:04:00.30#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.10:04:00.30#ibcon#ireg 17 cls_cnt 0 2006.145.10:04:00.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.10:04:00.30#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.10:04:00.30#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.10:04:00.32#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.10:04:00.35#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.10:04:00.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.10:04:00.36#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.10:04:00.36#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.10:04:00.36$vck44/vb=4,4 2006.145.10:04:00.36#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.10:04:00.36#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.10:04:00.36#ibcon#ireg 11 cls_cnt 2 2006.145.10:04:00.36#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.10:04:00.41#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.10:04:00.42#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.10:04:00.43#ibcon#[27=AT04-04\r\n] 2006.145.10:04:00.46#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.10:04:00.47#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.10:04:00.47#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.10:04:00.47#ibcon#ireg 7 cls_cnt 0 2006.145.10:04:00.47#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.10:04:00.58#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.10:04:00.59#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.10:04:00.60#ibcon#[27=USB\r\n] 2006.145.10:04:00.64#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.10:04:00.64#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.10:04:00.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.10:04:00.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.10:04:00.64$vck44/vblo=5,709.99 2006.145.10:04:00.64#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.10:04:00.64#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.10:04:00.64#ibcon#ireg 17 cls_cnt 0 2006.145.10:04:00.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.10:04:00.64#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.10:04:00.64#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.10:04:00.66#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.10:04:00.70#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.10:04:00.70#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.10:04:00.70#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.10:04:00.70#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.10:04:00.70$vck44/vb=5,4 2006.145.10:04:00.70#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.10:04:00.70#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.10:04:00.70#ibcon#ireg 11 cls_cnt 2 2006.145.10:04:00.70#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.10:04:00.75#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.10:04:00.76#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.10:04:00.78#ibcon#[27=AT05-04\r\n] 2006.145.10:04:00.81#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.10:04:00.81#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.10:04:00.81#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.10:04:00.81#ibcon#ireg 7 cls_cnt 0 2006.145.10:04:00.81#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.10:04:00.92#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.10:04:00.93#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.10:04:00.95#ibcon#[27=USB\r\n] 2006.145.10:04:00.98#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.10:04:00.98#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.10:04:00.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.10:04:00.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.10:04:00.98$vck44/vblo=6,719.99 2006.145.10:04:00.98#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.10:04:00.98#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.10:04:00.98#ibcon#ireg 17 cls_cnt 0 2006.145.10:04:00.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.10:04:00.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.10:04:00.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.10:04:01.00#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.10:04:01.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.10:04:01.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.10:04:01.04#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.10:04:01.04#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.10:04:01.04$vck44/vb=6,4 2006.145.10:04:01.04#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.10:04:01.04#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.10:04:01.04#ibcon#ireg 11 cls_cnt 2 2006.145.10:04:01.04#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.10:04:01.09#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.10:04:01.10#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.10:04:01.11#ibcon#[27=AT06-04\r\n] 2006.145.10:04:01.15#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.10:04:01.15#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.10:04:01.15#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.10:04:01.15#ibcon#ireg 7 cls_cnt 0 2006.145.10:04:01.15#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.10:04:01.26#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.10:04:01.27#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.10:04:01.28#ibcon#[27=USB\r\n] 2006.145.10:04:01.31#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.10:04:01.32#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.10:04:01.32#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.10:04:01.32#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.10:04:01.32$vck44/vblo=7,734.99 2006.145.10:04:01.32#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.10:04:01.32#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.10:04:01.32#ibcon#ireg 17 cls_cnt 0 2006.145.10:04:01.32#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:04:01.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:04:01.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:04:01.33#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.10:04:01.37#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:04:01.38#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:04:01.38#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.10:04:01.38#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.10:04:01.38$vck44/vb=7,4 2006.145.10:04:01.38#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.10:04:01.38#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.10:04:01.38#ibcon#ireg 11 cls_cnt 2 2006.145.10:04:01.38#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.10:04:01.43#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.10:04:01.44#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.10:04:01.45#ibcon#[27=AT07-04\r\n] 2006.145.10:04:01.48#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.10:04:01.49#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.10:04:01.49#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.10:04:01.49#ibcon#ireg 7 cls_cnt 0 2006.145.10:04:01.49#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.10:04:01.60#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.10:04:01.60#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.10:04:01.63#ibcon#[27=USB\r\n] 2006.145.10:04:01.66#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.10:04:01.66#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.10:04:01.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.10:04:01.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.10:04:01.66$vck44/vblo=8,744.99 2006.145.10:04:01.66#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.10:04:01.66#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.10:04:01.66#ibcon#ireg 17 cls_cnt 0 2006.145.10:04:01.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.10:04:01.66#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.10:04:01.66#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.10:04:01.68#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.10:04:01.71#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.10:04:01.72#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.10:04:01.72#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.10:04:01.72#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.10:04:01.72$vck44/vb=8,4 2006.145.10:04:01.72#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.10:04:01.72#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.10:04:01.72#ibcon#ireg 11 cls_cnt 2 2006.145.10:04:01.72#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.10:04:01.77#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.10:04:01.77#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.10:04:01.79#ibcon#[27=AT08-04\r\n] 2006.145.10:04:01.83#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.10:04:01.83#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.10:04:01.83#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.10:04:01.83#ibcon#ireg 7 cls_cnt 0 2006.145.10:04:01.83#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.10:04:01.94#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.10:04:01.95#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.10:04:01.97#ibcon#[27=USB\r\n] 2006.145.10:04:02.00#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.10:04:02.00#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.10:04:02.00#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.10:04:02.00#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.10:04:02.00$vck44/vabw=wide 2006.145.10:04:02.00#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.10:04:02.00#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.10:04:02.00#ibcon#ireg 8 cls_cnt 0 2006.145.10:04:02.00#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.10:04:02.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.10:04:02.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.10:04:02.02#ibcon#[25=BW32\r\n] 2006.145.10:04:02.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.10:04:02.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.10:04:02.05#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.10:04:02.05#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.10:04:02.05$vck44/vbbw=wide 2006.145.10:04:02.05#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.10:04:02.05#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.10:04:02.05#ibcon#ireg 8 cls_cnt 0 2006.145.10:04:02.05#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.10:04:02.11#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.10:04:02.12#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.10:04:02.14#ibcon#[27=BW32\r\n] 2006.145.10:04:02.17#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.10:04:02.17#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.10:04:02.17#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.10:04:02.17#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.10:04:02.17$setupk4/ifdk4 2006.145.10:04:02.17$ifdk4/lo= 2006.145.10:04:02.17$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.10:04:02.17$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.10:04:02.17$ifdk4/patch= 2006.145.10:04:02.17$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.10:04:02.17$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.10:04:02.17$setupk4/!*+20s 2006.145.10:04:08.31#abcon#<5=/05 2.9 5.0 17.56 661018.9\r\n> 2006.145.10:04:08.33#abcon#{5=INTERFACE CLEAR} 2006.145.10:04:08.42#abcon#[5=S1D000X0/0*\r\n] 2006.145.10:04:16.66$setupk4/"tpicd 2006.145.10:04:16.67$setupk4/echo=off 2006.145.10:04:16.67$setupk4/xlog=off 2006.145.10:04:16.67:!2006.145.10:05:12 2006.145.10:04:27.13#trakl#Source acquired 2006.145.10:04:28.14#flagr#flagr/antenna,acquired 2006.145.10:05:12.02:preob 2006.145.10:05:13.14/onsource/TRACKING 2006.145.10:05:13.14:!2006.145.10:05:22 2006.145.10:05:22.02:"tape 2006.145.10:05:22.02:"st=record 2006.145.10:05:22.02:data_valid=on 2006.145.10:05:22.02:midob 2006.145.10:05:23.15/onsource/TRACKING 2006.145.10:05:23.15/wx/17.55,1018.9,66 2006.145.10:05:23.20/cable/+6.5437E-03 2006.145.10:05:24.29/va/01,08,usb,yes,36,39 2006.145.10:05:24.29/va/02,07,usb,yes,39,39 2006.145.10:05:24.29/va/03,08,usb,yes,35,37 2006.145.10:05:24.29/va/04,07,usb,yes,40,42 2006.145.10:05:24.29/va/05,04,usb,yes,35,36 2006.145.10:05:24.29/va/06,04,usb,yes,39,39 2006.145.10:05:24.29/va/07,04,usb,yes,40,41 2006.145.10:05:24.29/va/08,04,usb,yes,34,40 2006.145.10:05:24.52/valo/01,524.99,yes,locked 2006.145.10:05:24.52/valo/02,534.99,yes,locked 2006.145.10:05:24.52/valo/03,564.99,yes,locked 2006.145.10:05:24.52/valo/04,624.99,yes,locked 2006.145.10:05:24.52/valo/05,734.99,yes,locked 2006.145.10:05:24.52/valo/06,814.99,yes,locked 2006.145.10:05:24.52/valo/07,864.99,yes,locked 2006.145.10:05:24.52/valo/08,884.99,yes,locked 2006.145.10:05:25.61/vb/01,03,usb,yes,41,39 2006.145.10:05:25.61/vb/02,04,usb,yes,36,36 2006.145.10:05:25.61/vb/03,04,usb,yes,33,36 2006.145.10:05:25.61/vb/04,04,usb,yes,37,36 2006.145.10:05:25.61/vb/05,04,usb,yes,29,32 2006.145.10:05:25.61/vb/06,04,usb,yes,35,30 2006.145.10:05:25.61/vb/07,04,usb,yes,34,34 2006.145.10:05:25.61/vb/08,04,usb,yes,31,35 2006.145.10:05:25.84/vblo/01,629.99,yes,locked 2006.145.10:05:25.84/vblo/02,634.99,yes,locked 2006.145.10:05:25.84/vblo/03,649.99,yes,locked 2006.145.10:05:25.84/vblo/04,679.99,yes,locked 2006.145.10:05:25.84/vblo/05,709.99,yes,locked 2006.145.10:05:25.84/vblo/06,719.99,yes,locked 2006.145.10:05:25.84/vblo/07,734.99,yes,locked 2006.145.10:05:25.84/vblo/08,744.99,yes,locked 2006.145.10:05:25.99/vabw/8 2006.145.10:05:26.14/vbbw/8 2006.145.10:05:26.23/xfe/off,on,14.2 2006.145.10:05:26.61/ifatt/23,28,28,28 2006.145.10:05:27.07/fmout-gps/S +4.7E-08 2006.145.10:05:27.12:!2006.145.10:17:22 2006.145.10:17:22.00:data_valid=off 2006.145.10:17:22.01:"et 2006.145.10:17:22.01:!+3s 2006.145.10:17:25.02:"tape 2006.145.10:17:25.03:postob 2006.145.10:17:25.12/cable/+6.5445E-03 2006.145.10:17:25.13/wx/17.44,1019.1,68 2006.145.10:17:25.21/fmout-gps/S +5.1E-08 2006.145.10:17:25.21:scan_name=145-1019,jd0605,400 2006.145.10:17:25.21:source=1308+326,131028.66,322043.8,2000.0,cw 2006.145.10:17:26.14#flagr#flagr/antenna,new-source 2006.145.10:17:26.15:checkk5 2006.145.10:17:26.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.10:17:27.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.10:17:27.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.10:17:27.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.10:17:28.63/chk_obsdata//k5ts1/T1451005??a.dat file size is correct (nominal:2880MB, actual:2876MB). 2006.145.10:17:29.37/chk_obsdata//k5ts2/T1451005??b.dat file size is correct (nominal:2880MB, actual:2876MB). 2006.145.10:17:30.11/chk_obsdata//k5ts3/T1451005??c.dat file size is correct (nominal:2880MB, actual:2876MB). 2006.145.10:17:30.86/chk_obsdata//k5ts4/T1451005??d.dat file size is correct (nominal:2880MB, actual:2876MB). 2006.145.10:17:31.62/k5log//k5ts1_log_newline 2006.145.10:17:32.36/k5log//k5ts2_log_newline 2006.145.10:17:33.10/k5log//k5ts3_log_newline 2006.145.10:17:33.83/k5log//k5ts4_log_newline 2006.145.10:17:33.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.10:17:33.85:setupk4=1 2006.145.10:17:33.85$setupk4/echo=on 2006.145.10:17:33.85$setupk4/pcalon 2006.145.10:17:33.85$pcalon/"no phase cal control is implemented here 2006.145.10:17:33.85$setupk4/"tpicd=stop 2006.145.10:17:33.85$setupk4/"rec=synch_on 2006.145.10:17:33.85$setupk4/"rec_mode=128 2006.145.10:17:33.85$setupk4/!* 2006.145.10:17:33.85$setupk4/recpk4 2006.145.10:17:33.85$recpk4/recpatch= 2006.145.10:17:33.85$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.10:17:33.86$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.10:17:33.86$setupk4/vck44 2006.145.10:17:33.86$vck44/valo=1,524.99 2006.145.10:17:33.86#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.10:17:33.86#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.10:17:33.86#ibcon#ireg 17 cls_cnt 0 2006.145.10:17:33.86#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.10:17:33.86#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.10:17:33.86#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.10:17:33.90#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.10:17:33.94#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.10:17:33.94#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.10:17:33.94#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.10:17:33.94#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.10:17:33.94$vck44/va=1,8 2006.145.10:17:33.94#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.10:17:33.94#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.10:17:33.94#ibcon#ireg 11 cls_cnt 2 2006.145.10:17:33.94#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.10:17:33.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.10:17:33.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.10:17:33.96#ibcon#[25=AT01-08\r\n] 2006.145.10:17:33.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.10:17:33.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.10:17:33.99#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.10:17:33.99#ibcon#ireg 7 cls_cnt 0 2006.145.10:17:33.99#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.10:17:34.11#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.10:17:34.11#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.10:17:34.13#ibcon#[25=USB\r\n] 2006.145.10:17:34.16#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.10:17:34.16#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.10:17:34.16#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.10:17:34.16#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.10:17:34.16$vck44/valo=2,534.99 2006.145.10:17:34.16#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.10:17:34.16#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.10:17:34.16#ibcon#ireg 17 cls_cnt 0 2006.145.10:17:34.16#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.10:17:34.16#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.10:17:34.16#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.10:17:34.18#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.10:17:34.22#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.10:17:34.22#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.10:17:34.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.10:17:34.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.10:17:34.22$vck44/va=2,7 2006.145.10:17:34.22#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.10:17:34.22#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.10:17:34.22#ibcon#ireg 11 cls_cnt 2 2006.145.10:17:34.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.10:17:34.28#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.10:17:34.28#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.10:17:34.30#ibcon#[25=AT02-07\r\n] 2006.145.10:17:34.33#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.10:17:34.33#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.10:17:34.33#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.10:17:34.33#ibcon#ireg 7 cls_cnt 0 2006.145.10:17:34.33#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.10:17:34.45#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.10:17:34.45#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.10:17:34.47#ibcon#[25=USB\r\n] 2006.145.10:17:34.50#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.10:17:34.50#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.10:17:34.50#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.10:17:34.50#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.10:17:34.50$vck44/valo=3,564.99 2006.145.10:17:34.50#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.10:17:34.50#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.10:17:34.50#ibcon#ireg 17 cls_cnt 0 2006.145.10:17:34.50#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.10:17:34.50#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.10:17:34.50#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.10:17:34.52#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.10:17:34.56#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.10:17:34.56#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.10:17:34.56#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.10:17:34.56#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.10:17:34.56$vck44/va=3,8 2006.145.10:17:34.56#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.10:17:34.56#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.10:17:34.56#ibcon#ireg 11 cls_cnt 2 2006.145.10:17:34.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.10:17:34.62#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.10:17:34.62#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.10:17:34.64#ibcon#[25=AT03-08\r\n] 2006.145.10:17:34.67#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.10:17:34.67#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.10:17:34.67#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.10:17:34.67#ibcon#ireg 7 cls_cnt 0 2006.145.10:17:34.67#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.10:17:34.79#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.10:17:34.79#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.10:17:34.81#ibcon#[25=USB\r\n] 2006.145.10:17:34.84#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.10:17:34.84#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.10:17:34.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.10:17:34.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.10:17:34.84$vck44/valo=4,624.99 2006.145.10:17:34.84#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.10:17:34.84#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.10:17:34.84#ibcon#ireg 17 cls_cnt 0 2006.145.10:17:34.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.10:17:34.84#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.10:17:34.84#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.10:17:34.86#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.10:17:34.90#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.10:17:34.90#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.10:17:34.90#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.10:17:34.90#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.10:17:34.90$vck44/va=4,7 2006.145.10:17:34.90#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.10:17:34.90#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.10:17:34.90#ibcon#ireg 11 cls_cnt 2 2006.145.10:17:34.90#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.10:17:34.96#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.10:17:34.96#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.10:17:34.98#ibcon#[25=AT04-07\r\n] 2006.145.10:17:35.01#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.10:17:35.01#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.10:17:35.01#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.10:17:35.01#ibcon#ireg 7 cls_cnt 0 2006.145.10:17:35.01#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.10:17:35.13#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.10:17:35.13#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.10:17:35.15#ibcon#[25=USB\r\n] 2006.145.10:17:35.18#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.10:17:35.18#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.10:17:35.18#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.10:17:35.18#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.10:17:35.18$vck44/valo=5,734.99 2006.145.10:17:35.18#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.10:17:35.18#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.10:17:35.18#ibcon#ireg 17 cls_cnt 0 2006.145.10:17:35.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.10:17:35.18#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.10:17:35.18#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.10:17:35.20#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.10:17:35.25#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.10:17:35.25#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.10:17:35.25#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.10:17:35.25#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.10:17:35.25$vck44/va=5,4 2006.145.10:17:35.25#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.10:17:35.25#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.10:17:35.25#ibcon#ireg 11 cls_cnt 2 2006.145.10:17:35.25#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.10:17:35.29#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.10:17:35.29#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.10:17:35.31#ibcon#[25=AT05-04\r\n] 2006.145.10:17:35.34#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.10:17:35.34#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.10:17:35.34#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.10:17:35.34#ibcon#ireg 7 cls_cnt 0 2006.145.10:17:35.34#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.10:17:35.46#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.10:17:35.46#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.10:17:35.48#ibcon#[25=USB\r\n] 2006.145.10:17:35.51#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.10:17:35.51#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.10:17:35.51#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.10:17:35.51#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.10:17:35.51$vck44/valo=6,814.99 2006.145.10:17:35.51#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.10:17:35.51#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.10:17:35.51#ibcon#ireg 17 cls_cnt 0 2006.145.10:17:35.51#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.10:17:35.51#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.10:17:35.51#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.10:17:35.53#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.10:17:35.57#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.10:17:35.57#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.10:17:35.57#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.10:17:35.57#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.10:17:35.57$vck44/va=6,4 2006.145.10:17:35.57#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.10:17:35.57#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.10:17:35.57#ibcon#ireg 11 cls_cnt 2 2006.145.10:17:35.57#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.10:17:35.63#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.10:17:35.63#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.10:17:35.65#ibcon#[25=AT06-04\r\n] 2006.145.10:17:35.68#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.10:17:35.68#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.10:17:35.68#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.10:17:35.68#ibcon#ireg 7 cls_cnt 0 2006.145.10:17:35.68#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.10:17:35.80#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.10:17:35.80#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.10:17:35.82#ibcon#[25=USB\r\n] 2006.145.10:17:35.85#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.10:17:35.85#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.10:17:35.85#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.10:17:35.85#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.10:17:35.85$vck44/valo=7,864.99 2006.145.10:17:35.85#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.10:17:35.85#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.10:17:35.85#ibcon#ireg 17 cls_cnt 0 2006.145.10:17:35.85#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.10:17:35.85#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.10:17:35.85#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.10:17:35.87#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.10:17:35.91#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.10:17:35.91#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.10:17:35.91#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.10:17:35.91#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.10:17:35.91$vck44/va=7,4 2006.145.10:17:35.91#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.10:17:35.91#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.10:17:35.91#ibcon#ireg 11 cls_cnt 2 2006.145.10:17:35.91#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.10:17:35.97#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.10:17:35.97#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.10:17:35.99#ibcon#[25=AT07-04\r\n] 2006.145.10:17:36.02#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.10:17:36.02#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.10:17:36.02#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.10:17:36.02#ibcon#ireg 7 cls_cnt 0 2006.145.10:17:36.02#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.10:17:36.14#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.10:17:36.14#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.10:17:36.16#ibcon#[25=USB\r\n] 2006.145.10:17:36.19#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.10:17:36.19#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.10:17:36.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.10:17:36.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.10:17:36.19$vck44/valo=8,884.99 2006.145.10:17:36.19#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.10:17:36.19#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.10:17:36.19#ibcon#ireg 17 cls_cnt 0 2006.145.10:17:36.19#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.10:17:36.19#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.10:17:36.19#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.10:17:36.21#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.10:17:36.25#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.10:17:36.25#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.10:17:36.25#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.10:17:36.25#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.10:17:36.25$vck44/va=8,4 2006.145.10:17:36.25#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.10:17:36.25#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.10:17:36.25#ibcon#ireg 11 cls_cnt 2 2006.145.10:17:36.25#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.10:17:36.31#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.10:17:36.31#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.10:17:36.33#ibcon#[25=AT08-04\r\n] 2006.145.10:17:36.36#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.10:17:36.36#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.10:17:36.36#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.10:17:36.36#ibcon#ireg 7 cls_cnt 0 2006.145.10:17:36.36#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.10:17:36.49#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.10:17:36.49#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.10:17:36.50#ibcon#[25=USB\r\n] 2006.145.10:17:36.53#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.10:17:36.53#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.10:17:36.53#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.10:17:36.53#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.10:17:36.53$vck44/vblo=1,629.99 2006.145.10:17:36.53#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.10:17:36.53#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.10:17:36.53#ibcon#ireg 17 cls_cnt 0 2006.145.10:17:36.53#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.10:17:36.53#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.10:17:36.53#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.10:17:36.56#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.10:17:36.60#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.10:17:36.60#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.10:17:36.60#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.10:17:36.60#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.10:17:36.60$vck44/vb=1,3 2006.145.10:17:36.60#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.10:17:36.60#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.10:17:36.60#ibcon#ireg 11 cls_cnt 2 2006.145.10:17:36.60#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.10:17:36.60#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.10:17:36.60#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.10:17:36.62#ibcon#[27=AT01-03\r\n] 2006.145.10:17:36.65#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.10:17:36.65#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.10:17:36.65#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.10:17:36.65#ibcon#ireg 7 cls_cnt 0 2006.145.10:17:36.65#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.10:17:36.77#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.10:17:36.77#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.10:17:36.79#ibcon#[27=USB\r\n] 2006.145.10:17:36.82#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.10:17:36.82#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.10:17:36.82#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.10:17:36.82#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.10:17:36.82$vck44/vblo=2,634.99 2006.145.10:17:36.82#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.10:17:36.82#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.10:17:36.82#ibcon#ireg 17 cls_cnt 0 2006.145.10:17:36.82#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.10:17:36.82#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.10:17:36.82#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.10:17:36.84#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.10:17:36.88#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.10:17:36.88#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.10:17:36.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.10:17:36.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.10:17:36.88$vck44/vb=2,4 2006.145.10:17:36.88#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.10:17:36.88#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.10:17:36.88#ibcon#ireg 11 cls_cnt 2 2006.145.10:17:36.88#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.10:17:36.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.10:17:36.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.10:17:36.96#ibcon#[27=AT02-04\r\n] 2006.145.10:17:36.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.10:17:36.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.10:17:36.99#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.10:17:36.99#ibcon#ireg 7 cls_cnt 0 2006.145.10:17:36.99#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.10:17:37.11#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.10:17:37.11#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.10:17:37.13#ibcon#[27=USB\r\n] 2006.145.10:17:37.16#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.10:17:37.16#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.10:17:37.16#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.10:17:37.16#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.10:17:37.16$vck44/vblo=3,649.99 2006.145.10:17:37.16#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.10:17:37.16#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.10:17:37.16#ibcon#ireg 17 cls_cnt 0 2006.145.10:17:37.16#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.10:17:37.16#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.10:17:37.16#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.10:17:37.18#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.10:17:37.22#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.10:17:37.22#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.10:17:37.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.10:17:37.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.10:17:37.22$vck44/vb=3,4 2006.145.10:17:37.22#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.10:17:37.22#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.10:17:37.22#ibcon#ireg 11 cls_cnt 2 2006.145.10:17:37.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.10:17:37.28#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.10:17:37.28#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.10:17:37.30#ibcon#[27=AT03-04\r\n] 2006.145.10:17:37.33#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.10:17:37.33#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.10:17:37.33#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.10:17:37.33#ibcon#ireg 7 cls_cnt 0 2006.145.10:17:37.33#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.10:17:37.45#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.10:17:37.45#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.10:17:37.47#ibcon#[27=USB\r\n] 2006.145.10:17:37.50#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.10:17:37.50#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.10:17:37.50#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.10:17:37.50#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.10:17:37.50$vck44/vblo=4,679.99 2006.145.10:17:37.50#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.10:17:37.50#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.10:17:37.50#ibcon#ireg 17 cls_cnt 0 2006.145.10:17:37.50#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.10:17:37.50#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.10:17:37.50#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.10:17:37.52#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.10:17:37.56#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.10:17:37.56#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.10:17:37.56#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.10:17:37.56#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.10:17:37.56$vck44/vb=4,4 2006.145.10:17:37.56#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.10:17:37.56#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.10:17:37.56#ibcon#ireg 11 cls_cnt 2 2006.145.10:17:37.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.10:17:37.62#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.10:17:37.62#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.10:17:37.64#ibcon#[27=AT04-04\r\n] 2006.145.10:17:37.67#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.10:17:37.67#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.10:17:37.67#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.10:17:37.67#ibcon#ireg 7 cls_cnt 0 2006.145.10:17:37.67#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.10:17:37.79#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.10:17:37.79#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.10:17:37.81#ibcon#[27=USB\r\n] 2006.145.10:17:37.84#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.10:17:37.84#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.10:17:37.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.10:17:37.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.10:17:37.84$vck44/vblo=5,709.99 2006.145.10:17:37.84#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.10:17:37.84#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.10:17:37.84#ibcon#ireg 17 cls_cnt 0 2006.145.10:17:37.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.10:17:37.84#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.10:17:37.84#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.10:17:37.86#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.10:17:37.90#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.10:17:37.90#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.10:17:37.90#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.10:17:37.90#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.10:17:37.90$vck44/vb=5,4 2006.145.10:17:37.90#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.10:17:37.90#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.10:17:37.90#ibcon#ireg 11 cls_cnt 2 2006.145.10:17:37.90#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.10:17:37.96#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.10:17:37.96#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.10:17:37.98#ibcon#[27=AT05-04\r\n] 2006.145.10:17:38.01#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.10:17:38.01#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.10:17:38.01#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.10:17:38.01#ibcon#ireg 7 cls_cnt 0 2006.145.10:17:38.01#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.10:17:38.13#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.10:17:38.13#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.10:17:38.15#ibcon#[27=USB\r\n] 2006.145.10:17:38.18#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.10:17:38.18#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.10:17:38.18#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.10:17:38.18#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.10:17:38.18$vck44/vblo=6,719.99 2006.145.10:17:38.18#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.10:17:38.18#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.10:17:38.18#ibcon#ireg 17 cls_cnt 0 2006.145.10:17:38.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.10:17:38.18#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.10:17:38.18#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.10:17:38.20#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.10:17:38.24#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.10:17:38.24#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.10:17:38.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.10:17:38.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.10:17:38.24$vck44/vb=6,4 2006.145.10:17:38.24#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.10:17:38.24#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.10:17:38.24#ibcon#ireg 11 cls_cnt 2 2006.145.10:17:38.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.10:17:38.30#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.10:17:38.30#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.10:17:38.32#ibcon#[27=AT06-04\r\n] 2006.145.10:17:38.35#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.10:17:38.35#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.10:17:38.35#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.10:17:38.35#ibcon#ireg 7 cls_cnt 0 2006.145.10:17:38.35#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.10:17:38.47#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.10:17:38.47#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.10:17:38.49#ibcon#[27=USB\r\n] 2006.145.10:17:38.52#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.10:17:38.52#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.10:17:38.52#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.10:17:38.52#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.10:17:38.52$vck44/vblo=7,734.99 2006.145.10:17:38.52#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.10:17:38.52#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.10:17:38.52#ibcon#ireg 17 cls_cnt 0 2006.145.10:17:38.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.10:17:38.52#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.10:17:38.52#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.10:17:38.54#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.10:17:38.58#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.10:17:38.58#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.10:17:38.58#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.10:17:38.58#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.10:17:38.58$vck44/vb=7,4 2006.145.10:17:38.58#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.10:17:38.58#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.10:17:38.58#ibcon#ireg 11 cls_cnt 2 2006.145.10:17:38.58#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.10:17:38.64#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.10:17:38.64#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.10:17:38.66#ibcon#[27=AT07-04\r\n] 2006.145.10:17:38.69#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.10:17:38.69#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.10:17:38.69#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.10:17:38.69#ibcon#ireg 7 cls_cnt 0 2006.145.10:17:38.69#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.10:17:38.81#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.10:17:38.81#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.10:17:38.83#ibcon#[27=USB\r\n] 2006.145.10:17:38.86#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.10:17:38.86#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.10:17:38.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.10:17:38.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.10:17:38.86$vck44/vblo=8,744.99 2006.145.10:17:38.86#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.10:17:38.86#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.10:17:38.86#ibcon#ireg 17 cls_cnt 0 2006.145.10:17:38.86#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.10:17:38.86#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.10:17:38.86#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.10:17:38.88#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.10:17:38.92#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.10:17:38.92#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.10:17:38.92#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.10:17:38.92#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.10:17:38.92$vck44/vb=8,4 2006.145.10:17:38.92#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.10:17:38.92#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.10:17:38.92#ibcon#ireg 11 cls_cnt 2 2006.145.10:17:38.92#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.10:17:38.98#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.10:17:38.98#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.10:17:39.00#ibcon#[27=AT08-04\r\n] 2006.145.10:17:39.03#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.10:17:39.03#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.10:17:39.03#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.10:17:39.03#ibcon#ireg 7 cls_cnt 0 2006.145.10:17:39.03#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.10:17:39.15#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.10:17:39.15#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.10:17:39.17#ibcon#[27=USB\r\n] 2006.145.10:17:39.20#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.10:17:39.20#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.10:17:39.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.10:17:39.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.10:17:39.20$vck44/vabw=wide 2006.145.10:17:39.20#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.10:17:39.20#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.10:17:39.20#ibcon#ireg 8 cls_cnt 0 2006.145.10:17:39.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.10:17:39.20#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.10:17:39.20#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.10:17:39.22#ibcon#[25=BW32\r\n] 2006.145.10:17:39.25#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.10:17:39.25#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.10:17:39.25#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.10:17:39.25#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.10:17:39.25$vck44/vbbw=wide 2006.145.10:17:39.25#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.10:17:39.25#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.10:17:39.25#ibcon#ireg 8 cls_cnt 0 2006.145.10:17:39.25#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.10:17:39.32#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.10:17:39.32#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.10:17:39.34#ibcon#[27=BW32\r\n] 2006.145.10:17:39.37#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.10:17:39.37#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.10:17:39.37#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.10:17:39.37#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.10:17:39.37$setupk4/ifdk4 2006.145.10:17:39.37$ifdk4/lo= 2006.145.10:17:39.37$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.10:17:39.37$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.10:17:39.37$ifdk4/patch= 2006.145.10:17:39.37$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.10:17:39.37$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.10:17:39.37$setupk4/!*+20s 2006.145.10:17:42.19#abcon#<5=/05 2.0 3.5 17.44 681019.1\r\n> 2006.145.10:17:42.21#abcon#{5=INTERFACE CLEAR} 2006.145.10:17:42.27#abcon#[5=S1D000X0/0*\r\n] 2006.145.10:17:52.38#abcon#<5=/05 2.0 3.5 17.43 681019.1\r\n> 2006.145.10:17:52.40#abcon#{5=INTERFACE CLEAR} 2006.145.10:17:52.46#abcon#[5=S1D000X0/0*\r\n] 2006.145.10:17:53.86$setupk4/"tpicd 2006.145.10:17:53.86$setupk4/echo=off 2006.145.10:17:53.86$setupk4/xlog=off 2006.145.10:17:53.86:!2006.145.10:19:34 2006.145.10:18:08.14#trakl#Source acquired 2006.145.10:18:09.14#flagr#flagr/antenna,acquired 2006.145.10:19:34.00:preob 2006.145.10:19:34.14/onsource/TRACKING 2006.145.10:19:34.14:!2006.145.10:19:44 2006.145.10:19:44.00:"tape 2006.145.10:19:44.00:"st=record 2006.145.10:19:44.00:data_valid=on 2006.145.10:19:44.00:midob 2006.145.10:19:45.14/onsource/TRACKING 2006.145.10:19:45.14/wx/17.42,1019.2,66 2006.145.10:19:45.25/cable/+6.5420E-03 2006.145.10:19:46.34/va/01,08,usb,yes,28,30 2006.145.10:19:46.34/va/02,07,usb,yes,30,30 2006.145.10:19:46.34/va/03,08,usb,yes,27,28 2006.145.10:19:46.34/va/04,07,usb,yes,31,32 2006.145.10:19:46.34/va/05,04,usb,yes,27,27 2006.145.10:19:46.34/va/06,04,usb,yes,30,30 2006.145.10:19:46.34/va/07,04,usb,yes,30,31 2006.145.10:19:46.34/va/08,04,usb,yes,26,31 2006.145.10:19:46.57/valo/01,524.99,yes,locked 2006.145.10:19:46.57/valo/02,534.99,yes,locked 2006.145.10:19:46.57/valo/03,564.99,yes,locked 2006.145.10:19:46.57/valo/04,624.99,yes,locked 2006.145.10:19:46.57/valo/05,734.99,yes,locked 2006.145.10:19:46.57/valo/06,814.99,yes,locked 2006.145.10:19:46.57/valo/07,864.99,yes,locked 2006.145.10:19:46.57/valo/08,884.99,yes,locked 2006.145.10:19:47.66/vb/01,03,usb,yes,35,33 2006.145.10:19:47.66/vb/02,04,usb,yes,31,31 2006.145.10:19:47.66/vb/03,04,usb,yes,28,30 2006.145.10:19:47.66/vb/04,04,usb,yes,32,31 2006.145.10:19:47.66/vb/05,04,usb,yes,25,27 2006.145.10:19:47.66/vb/06,04,usb,yes,29,25 2006.145.10:19:47.66/vb/07,04,usb,yes,29,28 2006.145.10:19:47.66/vb/08,04,usb,yes,26,29 2006.145.10:19:47.90/vblo/01,629.99,yes,locked 2006.145.10:19:47.90/vblo/02,634.99,yes,locked 2006.145.10:19:47.90/vblo/03,649.99,yes,locked 2006.145.10:19:47.90/vblo/04,679.99,yes,locked 2006.145.10:19:47.90/vblo/05,709.99,yes,locked 2006.145.10:19:47.90/vblo/06,719.99,yes,locked 2006.145.10:19:47.90/vblo/07,734.99,yes,locked 2006.145.10:19:47.90/vblo/08,744.99,yes,locked 2006.145.10:19:48.05/vabw/8 2006.145.10:19:48.20/vbbw/8 2006.145.10:19:48.29/xfe/off,on,15.2 2006.145.10:19:48.67/ifatt/23,28,28,28 2006.145.10:19:49.07/fmout-gps/S +5.0E-08 2006.145.10:19:49.11:!2006.145.10:26:24 2006.145.10:26:24.00:data_valid=off 2006.145.10:26:24.00:"et 2006.145.10:26:24.01:!+3s 2006.145.10:26:27.02:"tape 2006.145.10:26:27.02:postob 2006.145.10:26:27.10/cable/+6.5457E-03 2006.145.10:26:27.10/wx/17.40,1019.3,65 2006.145.10:26:27.18/fmout-gps/S +5.1E-08 2006.145.10:26:27.18:scan_name=145-1032,jd0605,100 2006.145.10:26:27.19:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.145.10:26:29.14#flagr#flagr/antenna,new-source 2006.145.10:26:29.14:checkk5 2006.145.10:26:29.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.10:26:30.04/chk_autoobs//k5ts2/ autoobs is running! 2006.145.10:26:30.48/chk_autoobs//k5ts3/ autoobs is running! 2006.145.10:26:30.92/chk_autoobs//k5ts4/ autoobs is running! 2006.145.10:26:31.33/chk_obsdata//k5ts1/T1451019??a.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.145.10:26:31.85/chk_obsdata//k5ts2/T1451019??b.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.145.10:26:32.29/chk_obsdata//k5ts3/T1451019??c.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.145.10:26:32.72/chk_obsdata//k5ts4/T1451019??d.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.145.10:26:33.49/k5log//k5ts1_log_newline 2006.145.10:26:34.23/k5log//k5ts2_log_newline 2006.145.10:26:34.98/k5log//k5ts3_log_newline 2006.145.10:26:35.71/k5log//k5ts4_log_newline 2006.145.10:26:35.73/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.10:26:35.73:setupk4=1 2006.145.10:26:35.73$setupk4/echo=on 2006.145.10:26:35.73$setupk4/pcalon 2006.145.10:26:35.73$pcalon/"no phase cal control is implemented here 2006.145.10:26:35.73$setupk4/"tpicd=stop 2006.145.10:26:35.73$setupk4/"rec=synch_on 2006.145.10:26:35.73$setupk4/"rec_mode=128 2006.145.10:26:35.73$setupk4/!* 2006.145.10:26:35.73$setupk4/recpk4 2006.145.10:26:35.73$recpk4/recpatch= 2006.145.10:26:35.73$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.10:26:35.73$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.10:26:35.73$setupk4/vck44 2006.145.10:26:35.73$vck44/valo=1,524.99 2006.145.10:26:35.74#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.10:26:35.74#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.10:26:35.74#ibcon#ireg 17 cls_cnt 0 2006.145.10:26:35.74#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.10:26:35.74#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.10:26:35.74#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.10:26:35.75#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.10:26:35.80#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.10:26:35.80#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.10:26:35.80#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.10:26:35.80#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.10:26:35.80$vck44/va=1,8 2006.145.10:26:35.80#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.10:26:35.80#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.10:26:35.80#ibcon#ireg 11 cls_cnt 2 2006.145.10:26:35.80#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.10:26:35.80#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.10:26:35.80#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.10:26:35.82#ibcon#[25=AT01-08\r\n] 2006.145.10:26:35.85#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.10:26:35.85#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.10:26:35.85#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.10:26:35.85#ibcon#ireg 7 cls_cnt 0 2006.145.10:26:35.85#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.10:26:35.97#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.10:26:35.97#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.10:26:35.99#ibcon#[25=USB\r\n] 2006.145.10:26:36.04#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.10:26:36.04#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.10:26:36.04#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.10:26:36.04#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.10:26:36.04$vck44/valo=2,534.99 2006.145.10:26:36.04#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.10:26:36.04#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.10:26:36.04#ibcon#ireg 17 cls_cnt 0 2006.145.10:26:36.04#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.10:26:36.04#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.10:26:36.04#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.10:26:36.06#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.10:26:36.10#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.10:26:36.10#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.10:26:36.10#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.10:26:36.10#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.10:26:36.10$vck44/va=2,7 2006.145.10:26:36.10#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.10:26:36.10#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.10:26:36.10#ibcon#ireg 11 cls_cnt 2 2006.145.10:26:36.10#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.10:26:36.16#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.10:26:36.16#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.10:26:36.18#ibcon#[25=AT02-07\r\n] 2006.145.10:26:36.21#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.10:26:36.21#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.10:26:36.21#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.10:26:36.21#ibcon#ireg 7 cls_cnt 0 2006.145.10:26:36.21#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.10:26:36.33#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.10:26:36.33#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.10:26:36.35#ibcon#[25=USB\r\n] 2006.145.10:26:36.38#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.10:26:36.38#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.10:26:36.38#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.10:26:36.38#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.10:26:36.38$vck44/valo=3,564.99 2006.145.10:26:36.38#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.10:26:36.38#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.10:26:36.38#ibcon#ireg 17 cls_cnt 0 2006.145.10:26:36.38#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.10:26:36.38#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.10:26:36.38#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.10:26:36.40#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.10:26:36.44#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.10:26:36.44#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.10:26:36.44#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.10:26:36.44#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.10:26:36.44$vck44/va=3,8 2006.145.10:26:36.44#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.10:26:36.44#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.10:26:36.44#ibcon#ireg 11 cls_cnt 2 2006.145.10:26:36.44#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.10:26:36.50#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.10:26:36.50#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.10:26:36.52#ibcon#[25=AT03-08\r\n] 2006.145.10:26:36.55#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.10:26:36.55#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.10:26:36.55#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.10:26:36.55#ibcon#ireg 7 cls_cnt 0 2006.145.10:26:36.55#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.10:26:36.67#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.10:26:36.67#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.10:26:36.69#ibcon#[25=USB\r\n] 2006.145.10:26:36.72#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.10:26:36.72#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.10:26:36.72#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.10:26:36.72#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.10:26:36.72$vck44/valo=4,624.99 2006.145.10:26:36.72#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.10:26:36.72#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.10:26:36.72#ibcon#ireg 17 cls_cnt 0 2006.145.10:26:36.72#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.10:26:36.72#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.10:26:36.72#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.10:26:36.74#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.10:26:36.78#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.10:26:36.78#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.10:26:36.78#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.10:26:36.78#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.10:26:36.78$vck44/va=4,7 2006.145.10:26:36.78#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.10:26:36.78#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.10:26:36.78#ibcon#ireg 11 cls_cnt 2 2006.145.10:26:36.78#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.10:26:36.84#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.10:26:36.84#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.10:26:36.86#ibcon#[25=AT04-07\r\n] 2006.145.10:26:36.89#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.10:26:36.89#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.10:26:36.89#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.10:26:36.89#ibcon#ireg 7 cls_cnt 0 2006.145.10:26:36.89#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.10:26:37.01#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.10:26:37.01#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.10:26:37.03#ibcon#[25=USB\r\n] 2006.145.10:26:37.06#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.10:26:37.06#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.10:26:37.06#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.10:26:37.06#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.10:26:37.06$vck44/valo=5,734.99 2006.145.10:26:37.06#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.10:26:37.06#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.10:26:37.06#ibcon#ireg 17 cls_cnt 0 2006.145.10:26:37.06#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.10:26:37.06#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.10:26:37.06#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.10:26:37.08#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.10:26:37.12#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.10:26:37.12#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.10:26:37.12#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.10:26:37.12#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.10:26:37.12$vck44/va=5,4 2006.145.10:26:37.12#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.10:26:37.12#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.10:26:37.12#ibcon#ireg 11 cls_cnt 2 2006.145.10:26:37.12#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.10:26:37.18#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.10:26:37.18#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.10:26:37.20#ibcon#[25=AT05-04\r\n] 2006.145.10:26:37.23#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.10:26:37.23#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.10:26:37.23#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.10:26:37.23#ibcon#ireg 7 cls_cnt 0 2006.145.10:26:37.23#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.10:26:37.37#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.10:26:37.37#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.10:26:37.38#ibcon#[25=USB\r\n] 2006.145.10:26:37.41#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.10:26:37.41#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.10:26:37.41#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.10:26:37.41#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.10:26:37.41$vck44/valo=6,814.99 2006.145.10:26:37.41#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.10:26:37.41#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.10:26:37.41#ibcon#ireg 17 cls_cnt 0 2006.145.10:26:37.41#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.10:26:37.41#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.10:26:37.41#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.10:26:37.44#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.10:26:37.48#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.10:26:37.48#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.10:26:37.48#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.10:26:37.48#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.10:26:37.48$vck44/va=6,4 2006.145.10:26:37.48#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.10:26:37.48#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.10:26:37.48#ibcon#ireg 11 cls_cnt 2 2006.145.10:26:37.48#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.10:26:37.53#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.10:26:37.53#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.10:26:37.55#ibcon#[25=AT06-04\r\n] 2006.145.10:26:37.58#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.10:26:37.58#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.10:26:37.58#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.10:26:37.58#ibcon#ireg 7 cls_cnt 0 2006.145.10:26:37.58#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.10:26:37.70#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.10:26:37.70#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.10:26:37.72#ibcon#[25=USB\r\n] 2006.145.10:26:37.75#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.10:26:37.75#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.10:26:37.75#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.10:26:37.75#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.10:26:37.75$vck44/valo=7,864.99 2006.145.10:26:37.75#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.10:26:37.75#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.10:26:37.75#ibcon#ireg 17 cls_cnt 0 2006.145.10:26:37.75#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.10:26:37.75#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.10:26:37.75#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.10:26:37.77#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.10:26:37.81#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.10:26:37.81#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.10:26:37.81#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.10:26:37.81#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.10:26:37.81$vck44/va=7,4 2006.145.10:26:37.81#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.10:26:37.81#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.10:26:37.81#ibcon#ireg 11 cls_cnt 2 2006.145.10:26:37.81#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.10:26:37.87#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.10:26:37.87#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.10:26:37.89#ibcon#[25=AT07-04\r\n] 2006.145.10:26:37.92#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.10:26:37.92#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.10:26:37.92#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.10:26:37.92#ibcon#ireg 7 cls_cnt 0 2006.145.10:26:37.92#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.10:26:38.04#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.10:26:38.04#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.10:26:38.06#ibcon#[25=USB\r\n] 2006.145.10:26:38.09#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.10:26:38.09#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.10:26:38.09#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.10:26:38.09#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.10:26:38.09$vck44/valo=8,884.99 2006.145.10:26:38.09#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.10:26:38.09#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.10:26:38.09#ibcon#ireg 17 cls_cnt 0 2006.145.10:26:38.09#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.10:26:38.09#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.10:26:38.09#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.10:26:38.11#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.10:26:38.15#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.10:26:38.15#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.10:26:38.15#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.10:26:38.15#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.10:26:38.15$vck44/va=8,4 2006.145.10:26:38.15#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.10:26:38.15#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.10:26:38.15#ibcon#ireg 11 cls_cnt 2 2006.145.10:26:38.15#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.10:26:38.21#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.10:26:38.21#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.10:26:38.23#ibcon#[25=AT08-04\r\n] 2006.145.10:26:38.26#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.10:26:38.26#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.10:26:38.26#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.10:26:38.26#ibcon#ireg 7 cls_cnt 0 2006.145.10:26:38.26#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.10:26:38.38#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.10:26:38.38#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.10:26:38.40#ibcon#[25=USB\r\n] 2006.145.10:26:38.43#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.10:26:38.43#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.10:26:38.43#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.10:26:38.43#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.10:26:38.43$vck44/vblo=1,629.99 2006.145.10:26:38.43#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.10:26:38.43#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.10:26:38.43#ibcon#ireg 17 cls_cnt 0 2006.145.10:26:38.43#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.10:26:38.43#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.10:26:38.43#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.10:26:38.45#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.10:26:38.49#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.10:26:38.49#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.10:26:38.49#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.10:26:38.49#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.10:26:38.49$vck44/vb=1,3 2006.145.10:26:38.49#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.10:26:38.49#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.10:26:38.49#ibcon#ireg 11 cls_cnt 2 2006.145.10:26:38.49#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.10:26:38.49#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.10:26:38.49#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.10:26:38.51#ibcon#[27=AT01-03\r\n] 2006.145.10:26:38.54#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.10:26:38.54#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.10:26:38.54#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.10:26:38.54#ibcon#ireg 7 cls_cnt 0 2006.145.10:26:38.54#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.10:26:38.66#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.10:26:38.66#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.10:26:38.68#ibcon#[27=USB\r\n] 2006.145.10:26:38.71#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.10:26:38.71#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.10:26:38.71#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.10:26:38.71#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.10:26:38.71$vck44/vblo=2,634.99 2006.145.10:26:38.71#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.10:26:38.71#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.10:26:38.71#ibcon#ireg 17 cls_cnt 0 2006.145.10:26:38.71#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.10:26:38.71#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.10:26:38.71#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.10:26:38.73#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.10:26:38.77#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.10:26:38.77#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.10:26:38.77#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.10:26:38.77#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.10:26:38.77$vck44/vb=2,4 2006.145.10:26:38.77#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.10:26:38.77#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.10:26:38.77#ibcon#ireg 11 cls_cnt 2 2006.145.10:26:38.77#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.10:26:38.83#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.10:26:38.83#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.10:26:38.85#ibcon#[27=AT02-04\r\n] 2006.145.10:26:38.88#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.10:26:38.88#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.10:26:38.88#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.10:26:38.88#ibcon#ireg 7 cls_cnt 0 2006.145.10:26:38.88#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.10:26:39.00#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.10:26:39.00#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.10:26:39.02#ibcon#[27=USB\r\n] 2006.145.10:26:39.05#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.10:26:39.05#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.10:26:39.05#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.10:26:39.05#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.10:26:39.05$vck44/vblo=3,649.99 2006.145.10:26:39.05#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.10:26:39.05#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.10:26:39.05#ibcon#ireg 17 cls_cnt 0 2006.145.10:26:39.05#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.10:26:39.05#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.10:26:39.05#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.10:26:39.07#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.10:26:39.11#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.10:26:39.11#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.10:26:39.11#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.10:26:39.11#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.10:26:39.11$vck44/vb=3,4 2006.145.10:26:39.11#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.10:26:39.11#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.10:26:39.11#ibcon#ireg 11 cls_cnt 2 2006.145.10:26:39.11#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.10:26:39.17#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.10:26:39.17#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.10:26:39.19#ibcon#[27=AT03-04\r\n] 2006.145.10:26:39.22#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.10:26:39.22#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.10:26:39.22#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.10:26:39.22#ibcon#ireg 7 cls_cnt 0 2006.145.10:26:39.22#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.10:26:39.34#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.10:26:39.34#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.10:26:39.36#ibcon#[27=USB\r\n] 2006.145.10:26:39.39#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.10:26:39.39#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.10:26:39.39#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.10:26:39.39#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.10:26:39.39$vck44/vblo=4,679.99 2006.145.10:26:39.39#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.10:26:39.39#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.10:26:39.39#ibcon#ireg 17 cls_cnt 0 2006.145.10:26:39.39#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.10:26:39.39#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.10:26:39.39#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.10:26:39.41#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.10:26:39.45#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.10:26:39.45#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.10:26:39.45#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.10:26:39.45#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.10:26:39.45$vck44/vb=4,4 2006.145.10:26:39.45#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.10:26:39.45#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.10:26:39.45#ibcon#ireg 11 cls_cnt 2 2006.145.10:26:39.45#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.10:26:39.51#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.10:26:39.51#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.10:26:39.53#ibcon#[27=AT04-04\r\n] 2006.145.10:26:39.56#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.10:26:39.56#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.10:26:39.56#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.10:26:39.56#ibcon#ireg 7 cls_cnt 0 2006.145.10:26:39.56#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.10:26:39.68#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.10:26:39.68#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.10:26:39.70#ibcon#[27=USB\r\n] 2006.145.10:26:39.73#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.10:26:39.73#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.10:26:39.73#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.10:26:39.73#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.10:26:39.73$vck44/vblo=5,709.99 2006.145.10:26:39.73#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.10:26:39.73#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.10:26:39.73#ibcon#ireg 17 cls_cnt 0 2006.145.10:26:39.73#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.10:26:39.73#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.10:26:39.73#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.10:26:39.75#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.10:26:39.79#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.10:26:39.79#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.10:26:39.79#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.10:26:39.79#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.10:26:39.79$vck44/vb=5,4 2006.145.10:26:39.79#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.10:26:39.79#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.10:26:39.79#ibcon#ireg 11 cls_cnt 2 2006.145.10:26:39.79#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.10:26:39.85#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.10:26:39.85#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.10:26:39.87#ibcon#[27=AT05-04\r\n] 2006.145.10:26:39.90#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.10:26:39.90#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.10:26:39.90#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.10:26:39.90#ibcon#ireg 7 cls_cnt 0 2006.145.10:26:39.90#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.10:26:40.02#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.10:26:40.02#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.10:26:40.04#ibcon#[27=USB\r\n] 2006.145.10:26:40.07#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.10:26:40.07#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.10:26:40.07#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.10:26:40.07#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.10:26:40.07$vck44/vblo=6,719.99 2006.145.10:26:40.07#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.10:26:40.07#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.10:26:40.07#ibcon#ireg 17 cls_cnt 0 2006.145.10:26:40.07#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.10:26:40.07#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.10:26:40.07#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.10:26:40.09#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.10:26:40.13#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.10:26:40.13#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.10:26:40.13#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.10:26:40.13#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.10:26:40.13$vck44/vb=6,4 2006.145.10:26:40.13#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.10:26:40.13#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.10:26:40.13#ibcon#ireg 11 cls_cnt 2 2006.145.10:26:40.13#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.10:26:40.19#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.10:26:40.19#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.10:26:40.21#ibcon#[27=AT06-04\r\n] 2006.145.10:26:40.24#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.10:26:40.24#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.10:26:40.24#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.10:26:40.24#ibcon#ireg 7 cls_cnt 0 2006.145.10:26:40.24#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.10:26:40.36#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.10:26:40.36#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.10:26:40.38#ibcon#[27=USB\r\n] 2006.145.10:26:40.41#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.10:26:40.41#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.10:26:40.41#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.10:26:40.41#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.10:26:40.41$vck44/vblo=7,734.99 2006.145.10:26:40.41#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.10:26:40.41#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.10:26:40.41#ibcon#ireg 17 cls_cnt 0 2006.145.10:26:40.41#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.10:26:40.41#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.10:26:40.41#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.10:26:40.43#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.10:26:40.47#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.10:26:40.47#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.10:26:40.47#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.10:26:40.47#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.10:26:40.47$vck44/vb=7,4 2006.145.10:26:40.47#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.10:26:40.47#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.10:26:40.47#ibcon#ireg 11 cls_cnt 2 2006.145.10:26:40.47#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.10:26:40.53#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.10:26:40.53#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.10:26:40.55#ibcon#[27=AT07-04\r\n] 2006.145.10:26:40.58#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.10:26:40.58#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.10:26:40.58#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.10:26:40.58#ibcon#ireg 7 cls_cnt 0 2006.145.10:26:40.58#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.10:26:40.70#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.10:26:40.70#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.10:26:40.72#ibcon#[27=USB\r\n] 2006.145.10:26:40.75#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.10:26:40.75#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.10:26:40.75#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.10:26:40.75#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.10:26:40.75$vck44/vblo=8,744.99 2006.145.10:26:40.75#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.10:26:40.75#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.10:26:40.75#ibcon#ireg 17 cls_cnt 0 2006.145.10:26:40.75#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.10:26:40.75#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.10:26:40.75#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.10:26:40.77#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.10:26:40.81#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.10:26:40.81#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.10:26:40.81#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.10:26:40.81#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.10:26:40.81$vck44/vb=8,4 2006.145.10:26:40.81#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.10:26:40.81#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.10:26:40.81#ibcon#ireg 11 cls_cnt 2 2006.145.10:26:40.81#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.10:26:40.87#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.10:26:40.87#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.10:26:40.89#ibcon#[27=AT08-04\r\n] 2006.145.10:26:40.92#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.10:26:40.92#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.10:26:40.92#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.10:26:40.92#ibcon#ireg 7 cls_cnt 0 2006.145.10:26:40.92#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.10:26:41.04#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.10:26:41.04#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.10:26:41.06#ibcon#[27=USB\r\n] 2006.145.10:26:41.09#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.10:26:41.09#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.10:26:41.09#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.10:26:41.09#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.10:26:41.09$vck44/vabw=wide 2006.145.10:26:41.09#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.10:26:41.09#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.10:26:41.09#ibcon#ireg 8 cls_cnt 0 2006.145.10:26:41.09#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.10:26:41.09#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.10:26:41.09#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.10:26:41.11#ibcon#[25=BW32\r\n] 2006.145.10:26:41.14#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.10:26:41.14#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.10:26:41.14#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.10:26:41.14#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.10:26:41.14$vck44/vbbw=wide 2006.145.10:26:41.14#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.10:26:41.14#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.10:26:41.14#ibcon#ireg 8 cls_cnt 0 2006.145.10:26:41.14#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:26:41.21#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:26:41.21#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:26:41.23#ibcon#[27=BW32\r\n] 2006.145.10:26:41.26#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:26:41.26#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:26:41.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.10:26:41.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.10:26:41.26$setupk4/ifdk4 2006.145.10:26:41.26$ifdk4/lo= 2006.145.10:26:41.26$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.10:26:41.26$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.10:26:41.26$ifdk4/patch= 2006.145.10:26:41.26$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.10:26:41.26$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.10:26:41.26$setupk4/!*+20s 2006.145.10:26:41.52#abcon#<5=/06 2.7 5.4 17.40 641019.2\r\n> 2006.145.10:26:41.54#abcon#{5=INTERFACE CLEAR} 2006.145.10:26:41.60#abcon#[5=S1D000X0/0*\r\n] 2006.145.10:26:51.69#abcon#<5=/06 2.8 5.4 17.39 641019.2\r\n> 2006.145.10:26:51.71#abcon#{5=INTERFACE CLEAR} 2006.145.10:26:51.77#abcon#[5=S1D000X0/0*\r\n] 2006.145.10:26:54.14#trakl#Source acquired 2006.145.10:26:54.14#flagr#flagr/antenna,acquired 2006.145.10:26:55.74$setupk4/"tpicd 2006.145.10:26:55.74$setupk4/echo=off 2006.145.10:26:55.74$setupk4/xlog=off 2006.145.10:26:55.74:!2006.145.10:32:03 2006.145.10:32:03.00:preob 2006.145.10:32:04.14/onsource/TRACKING 2006.145.10:32:04.14:!2006.145.10:32:13 2006.145.10:32:13.00:"tape 2006.145.10:32:13.00:"st=record 2006.145.10:32:13.00:data_valid=on 2006.145.10:32:13.00:midob 2006.145.10:32:13.14/onsource/TRACKING 2006.145.10:32:13.14/wx/17.34,1019.3,65 2006.145.10:32:13.36/cable/+6.5446E-03 2006.145.10:32:14.45/va/01,08,usb,yes,29,31 2006.145.10:32:14.45/va/02,07,usb,yes,31,31 2006.145.10:32:14.45/va/03,08,usb,yes,28,29 2006.145.10:32:14.45/va/04,07,usb,yes,32,33 2006.145.10:32:14.45/va/05,04,usb,yes,28,28 2006.145.10:32:14.45/va/06,04,usb,yes,31,31 2006.145.10:32:14.45/va/07,04,usb,yes,31,32 2006.145.10:32:14.45/va/08,04,usb,yes,27,32 2006.145.10:32:14.68/valo/01,524.99,yes,locked 2006.145.10:32:14.68/valo/02,534.99,yes,locked 2006.145.10:32:14.68/valo/03,564.99,yes,locked 2006.145.10:32:14.68/valo/04,624.99,yes,locked 2006.145.10:32:14.68/valo/05,734.99,yes,locked 2006.145.10:32:14.68/valo/06,814.99,yes,locked 2006.145.10:32:14.68/valo/07,864.99,yes,locked 2006.145.10:32:14.68/valo/08,884.99,yes,locked 2006.145.10:32:15.77/vb/01,03,usb,yes,36,33 2006.145.10:32:15.77/vb/02,04,usb,yes,31,31 2006.145.10:32:15.77/vb/03,04,usb,yes,28,31 2006.145.10:32:15.77/vb/04,04,usb,yes,32,31 2006.145.10:32:15.77/vb/05,04,usb,yes,25,27 2006.145.10:32:15.77/vb/06,04,usb,yes,29,26 2006.145.10:32:15.77/vb/07,04,usb,yes,29,29 2006.145.10:32:15.77/vb/08,04,usb,yes,27,30 2006.145.10:32:16.00/vblo/01,629.99,yes,locked 2006.145.10:32:16.00/vblo/02,634.99,yes,locked 2006.145.10:32:16.00/vblo/03,649.99,yes,locked 2006.145.10:32:16.00/vblo/04,679.99,yes,locked 2006.145.10:32:16.00/vblo/05,709.99,yes,locked 2006.145.10:32:16.00/vblo/06,719.99,yes,locked 2006.145.10:32:16.00/vblo/07,734.99,yes,locked 2006.145.10:32:16.00/vblo/08,744.99,yes,locked 2006.145.10:32:16.15/vabw/8 2006.145.10:32:16.30/vbbw/8 2006.145.10:32:16.39/xfe/off,on,15.2 2006.145.10:32:16.78/ifatt/23,28,28,28 2006.145.10:32:17.07/fmout-gps/S +5.1E-08 2006.145.10:32:17.15:!2006.145.10:33:53 2006.145.10:33:53.00:data_valid=off 2006.145.10:33:53.00:"et 2006.145.10:33:53.01:!+3s 2006.145.10:33:56.02:"tape 2006.145.10:33:56.02:postob 2006.145.10:33:56.20/cable/+6.5451E-03 2006.145.10:33:56.20/wx/17.34,1019.3,64 2006.145.10:33:56.28/fmout-gps/S +5.0E-08 2006.145.10:33:56.29:scan_name=145-1035,jd0605,80 2006.145.10:33:56.29:source=3c274,123049.42,122328.0,2000.0,cw 2006.145.10:33:58.14#flagr#flagr/antenna,new-source 2006.145.10:33:58.14:checkk5 2006.145.10:33:58.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.10:33:59.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.10:33:59.49/chk_autoobs//k5ts3/ autoobs is running! 2006.145.10:33:59.94/chk_autoobs//k5ts4/ autoobs is running! 2006.145.10:34:00.37/chk_obsdata//k5ts1/T1451032??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.10:34:00.82/chk_obsdata//k5ts2/T1451032??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.10:34:01.26/chk_obsdata//k5ts3/T1451032??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.10:34:01.71/chk_obsdata//k5ts4/T1451032??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.10:34:02.46/k5log//k5ts1_log_newline 2006.145.10:34:03.21/k5log//k5ts2_log_newline 2006.145.10:34:03.95/k5log//k5ts3_log_newline 2006.145.10:34:04.69/k5log//k5ts4_log_newline 2006.145.10:34:04.71/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.10:34:04.71:setupk4=1 2006.145.10:34:04.71$setupk4/echo=on 2006.145.10:34:04.71$setupk4/pcalon 2006.145.10:34:04.71$pcalon/"no phase cal control is implemented here 2006.145.10:34:04.71$setupk4/"tpicd=stop 2006.145.10:34:04.71$setupk4/"rec=synch_on 2006.145.10:34:04.71$setupk4/"rec_mode=128 2006.145.10:34:04.71$setupk4/!* 2006.145.10:34:04.71$setupk4/recpk4 2006.145.10:34:04.71$recpk4/recpatch= 2006.145.10:34:04.72$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.10:34:04.72$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.10:34:04.72$setupk4/vck44 2006.145.10:34:04.72$vck44/valo=1,524.99 2006.145.10:34:04.72#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.10:34:04.72#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.10:34:04.72#ibcon#ireg 17 cls_cnt 0 2006.145.10:34:04.72#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.10:34:04.72#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.10:34:04.72#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.10:34:04.76#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.10:34:04.81#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.10:34:04.81#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.10:34:04.81#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.10:34:04.81#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.10:34:04.81$vck44/va=1,8 2006.145.10:34:04.81#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.10:34:04.81#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.10:34:04.81#ibcon#ireg 11 cls_cnt 2 2006.145.10:34:04.81#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.10:34:04.81#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.10:34:04.81#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.10:34:04.83#ibcon#[25=AT01-08\r\n] 2006.145.10:34:04.86#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.10:34:04.86#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.10:34:04.86#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.10:34:04.86#ibcon#ireg 7 cls_cnt 0 2006.145.10:34:04.86#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.10:34:04.98#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.10:34:04.98#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.10:34:05.00#ibcon#[25=USB\r\n] 2006.145.10:34:05.05#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.10:34:05.05#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.10:34:05.05#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.10:34:05.05#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.10:34:05.05$vck44/valo=2,534.99 2006.145.10:34:05.05#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.10:34:05.05#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.10:34:05.05#ibcon#ireg 17 cls_cnt 0 2006.145.10:34:05.05#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.10:34:05.05#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.10:34:05.05#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.10:34:05.06#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.10:34:05.10#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.10:34:05.10#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.10:34:05.10#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.10:34:05.10#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.10:34:05.10$vck44/va=2,7 2006.145.10:34:05.10#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.10:34:05.10#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.10:34:05.10#ibcon#ireg 11 cls_cnt 2 2006.145.10:34:05.10#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.10:34:05.17#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.10:34:05.17#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.10:34:05.19#ibcon#[25=AT02-07\r\n] 2006.145.10:34:05.22#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.10:34:05.22#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.10:34:05.22#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.10:34:05.22#ibcon#ireg 7 cls_cnt 0 2006.145.10:34:05.22#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.10:34:05.34#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.10:34:05.34#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.10:34:05.36#ibcon#[25=USB\r\n] 2006.145.10:34:05.39#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.10:34:05.39#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.10:34:05.39#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.10:34:05.39#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.10:34:05.39$vck44/valo=3,564.99 2006.145.10:34:05.39#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.10:34:05.39#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.10:34:05.39#ibcon#ireg 17 cls_cnt 0 2006.145.10:34:05.39#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.10:34:05.39#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.10:34:05.39#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.10:34:05.41#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.10:34:05.45#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.10:34:05.45#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.10:34:05.45#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.10:34:05.45#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.10:34:05.45$vck44/va=3,8 2006.145.10:34:05.45#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.10:34:05.45#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.10:34:05.45#ibcon#ireg 11 cls_cnt 2 2006.145.10:34:05.45#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.10:34:05.51#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.10:34:05.51#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.10:34:05.53#ibcon#[25=AT03-08\r\n] 2006.145.10:34:05.56#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.10:34:05.56#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.10:34:05.56#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.10:34:05.56#ibcon#ireg 7 cls_cnt 0 2006.145.10:34:05.56#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.10:34:05.68#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.10:34:05.68#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.10:34:05.70#ibcon#[25=USB\r\n] 2006.145.10:34:05.73#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.10:34:05.73#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.10:34:05.73#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.10:34:05.73#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.10:34:05.73$vck44/valo=4,624.99 2006.145.10:34:05.73#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.10:34:05.73#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.10:34:05.73#ibcon#ireg 17 cls_cnt 0 2006.145.10:34:05.73#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.10:34:05.73#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.10:34:05.73#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.10:34:05.75#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.10:34:05.79#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.10:34:05.79#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.10:34:05.79#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.10:34:05.79#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.10:34:05.79$vck44/va=4,7 2006.145.10:34:05.79#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.10:34:05.79#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.10:34:05.79#ibcon#ireg 11 cls_cnt 2 2006.145.10:34:05.79#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.10:34:05.85#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.10:34:05.85#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.10:34:05.87#ibcon#[25=AT04-07\r\n] 2006.145.10:34:05.90#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.10:34:05.90#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.10:34:05.90#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.10:34:05.90#ibcon#ireg 7 cls_cnt 0 2006.145.10:34:05.90#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.10:34:06.02#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.10:34:06.02#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.10:34:06.04#ibcon#[25=USB\r\n] 2006.145.10:34:06.07#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.10:34:06.07#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.10:34:06.07#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.10:34:06.07#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.10:34:06.07$vck44/valo=5,734.99 2006.145.10:34:06.07#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.10:34:06.07#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.10:34:06.07#ibcon#ireg 17 cls_cnt 0 2006.145.10:34:06.07#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.10:34:06.07#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.10:34:06.07#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.10:34:06.09#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.10:34:06.14#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.10:34:06.14#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.10:34:06.14#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.10:34:06.14#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.10:34:06.14$vck44/va=5,4 2006.145.10:34:06.14#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.10:34:06.14#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.10:34:06.14#ibcon#ireg 11 cls_cnt 2 2006.145.10:34:06.14#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.10:34:06.18#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.10:34:06.18#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.10:34:06.20#ibcon#[25=AT05-04\r\n] 2006.145.10:34:06.23#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.10:34:06.23#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.10:34:06.23#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.10:34:06.23#ibcon#ireg 7 cls_cnt 0 2006.145.10:34:06.23#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.10:34:06.35#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.10:34:06.35#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.10:34:06.37#ibcon#[25=USB\r\n] 2006.145.10:34:06.40#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.10:34:06.40#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.10:34:06.40#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.10:34:06.40#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.10:34:06.40$vck44/valo=6,814.99 2006.145.10:34:06.40#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.10:34:06.40#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.10:34:06.40#ibcon#ireg 17 cls_cnt 0 2006.145.10:34:06.40#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.10:34:06.40#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.10:34:06.40#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.10:34:06.43#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.10:34:06.47#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.10:34:06.47#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.10:34:06.47#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.10:34:06.47#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.10:34:06.47$vck44/va=6,4 2006.145.10:34:06.47#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.10:34:06.47#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.10:34:06.47#ibcon#ireg 11 cls_cnt 2 2006.145.10:34:06.47#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.10:34:06.52#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.10:34:06.52#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.10:34:06.54#ibcon#[25=AT06-04\r\n] 2006.145.10:34:06.57#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.10:34:06.57#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.10:34:06.57#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.10:34:06.57#ibcon#ireg 7 cls_cnt 0 2006.145.10:34:06.57#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.10:34:06.69#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.10:34:06.69#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.10:34:06.71#ibcon#[25=USB\r\n] 2006.145.10:34:06.74#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.10:34:06.74#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.10:34:06.74#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.10:34:06.74#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.10:34:06.74$vck44/valo=7,864.99 2006.145.10:34:06.74#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.10:34:06.74#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.10:34:06.74#ibcon#ireg 17 cls_cnt 0 2006.145.10:34:06.74#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.10:34:06.74#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.10:34:06.74#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.10:34:06.76#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.10:34:06.80#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.10:34:06.80#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.10:34:06.80#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.10:34:06.80#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.10:34:06.80$vck44/va=7,4 2006.145.10:34:06.80#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.10:34:06.80#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.10:34:06.80#ibcon#ireg 11 cls_cnt 2 2006.145.10:34:06.80#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.10:34:06.86#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.10:34:06.86#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.10:34:06.88#ibcon#[25=AT07-04\r\n] 2006.145.10:34:06.91#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.10:34:06.91#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.10:34:06.91#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.10:34:06.91#ibcon#ireg 7 cls_cnt 0 2006.145.10:34:06.91#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.10:34:07.03#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.10:34:07.03#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.10:34:07.05#ibcon#[25=USB\r\n] 2006.145.10:34:07.08#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.10:34:07.08#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.10:34:07.08#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.10:34:07.08#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.10:34:07.08$vck44/valo=8,884.99 2006.145.10:34:07.08#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.10:34:07.08#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.10:34:07.08#ibcon#ireg 17 cls_cnt 0 2006.145.10:34:07.08#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.10:34:07.08#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.10:34:07.08#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.10:34:07.10#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.10:34:07.14#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.10:34:07.14#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.10:34:07.14#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.10:34:07.14#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.10:34:07.14$vck44/va=8,4 2006.145.10:34:07.14#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.10:34:07.14#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.10:34:07.14#ibcon#ireg 11 cls_cnt 2 2006.145.10:34:07.14#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.10:34:07.20#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.10:34:07.20#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.10:34:07.22#ibcon#[25=AT08-04\r\n] 2006.145.10:34:07.25#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.10:34:07.25#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.10:34:07.25#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.10:34:07.25#ibcon#ireg 7 cls_cnt 0 2006.145.10:34:07.25#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.10:34:07.37#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.10:34:07.37#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.10:34:07.39#ibcon#[25=USB\r\n] 2006.145.10:34:07.42#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.10:34:07.42#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.10:34:07.42#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.10:34:07.42#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.10:34:07.42$vck44/vblo=1,629.99 2006.145.10:34:07.42#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.10:34:07.42#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.10:34:07.42#ibcon#ireg 17 cls_cnt 0 2006.145.10:34:07.42#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.10:34:07.42#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.10:34:07.42#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.10:34:07.44#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.10:34:07.49#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.10:34:07.49#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.10:34:07.49#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.10:34:07.49#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.10:34:07.49$vck44/vb=1,3 2006.145.10:34:07.49#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.10:34:07.49#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.10:34:07.49#ibcon#ireg 11 cls_cnt 2 2006.145.10:34:07.49#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.10:34:07.49#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.10:34:07.49#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.10:34:07.51#ibcon#[27=AT01-03\r\n] 2006.145.10:34:07.54#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.10:34:07.54#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.10:34:07.54#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.10:34:07.54#ibcon#ireg 7 cls_cnt 0 2006.145.10:34:07.54#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.10:34:07.66#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.10:34:07.66#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.10:34:07.68#ibcon#[27=USB\r\n] 2006.145.10:34:07.71#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.10:34:07.71#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.10:34:07.71#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.10:34:07.71#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.10:34:07.71$vck44/vblo=2,634.99 2006.145.10:34:07.71#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.10:34:07.71#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.10:34:07.71#ibcon#ireg 17 cls_cnt 0 2006.145.10:34:07.71#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.10:34:07.71#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.10:34:07.71#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.10:34:07.73#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.10:34:07.77#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.10:34:07.77#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.10:34:07.77#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.10:34:07.77#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.10:34:07.77$vck44/vb=2,4 2006.145.10:34:07.77#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.10:34:07.77#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.10:34:07.77#ibcon#ireg 11 cls_cnt 2 2006.145.10:34:07.77#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.10:34:07.83#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.10:34:07.83#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.10:34:07.85#ibcon#[27=AT02-04\r\n] 2006.145.10:34:07.88#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.10:34:07.88#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.10:34:07.88#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.10:34:07.88#ibcon#ireg 7 cls_cnt 0 2006.145.10:34:07.88#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.10:34:08.00#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.10:34:08.00#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.10:34:08.02#ibcon#[27=USB\r\n] 2006.145.10:34:08.05#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.10:34:08.05#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.10:34:08.05#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.10:34:08.05#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.10:34:08.05$vck44/vblo=3,649.99 2006.145.10:34:08.05#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.10:34:08.05#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.10:34:08.05#ibcon#ireg 17 cls_cnt 0 2006.145.10:34:08.05#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.10:34:08.05#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.10:34:08.05#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.10:34:08.07#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.10:34:08.11#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.10:34:08.11#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.10:34:08.11#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.10:34:08.11#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.10:34:08.11$vck44/vb=3,4 2006.145.10:34:08.11#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.10:34:08.11#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.10:34:08.11#ibcon#ireg 11 cls_cnt 2 2006.145.10:34:08.11#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.10:34:08.17#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.10:34:08.17#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.10:34:08.19#ibcon#[27=AT03-04\r\n] 2006.145.10:34:08.22#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.10:34:08.22#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.10:34:08.22#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.10:34:08.22#ibcon#ireg 7 cls_cnt 0 2006.145.10:34:08.22#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.10:34:08.34#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.10:34:08.34#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.10:34:08.36#ibcon#[27=USB\r\n] 2006.145.10:34:08.39#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.10:34:08.39#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.10:34:08.39#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.10:34:08.39#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.10:34:08.39$vck44/vblo=4,679.99 2006.145.10:34:08.39#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.10:34:08.39#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.10:34:08.39#ibcon#ireg 17 cls_cnt 0 2006.145.10:34:08.39#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.10:34:08.39#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.10:34:08.39#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.10:34:08.41#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.10:34:08.45#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.10:34:08.45#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.10:34:08.45#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.10:34:08.45#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.10:34:08.45$vck44/vb=4,4 2006.145.10:34:08.45#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.10:34:08.45#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.10:34:08.45#ibcon#ireg 11 cls_cnt 2 2006.145.10:34:08.45#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.10:34:08.51#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.10:34:08.51#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.10:34:08.53#ibcon#[27=AT04-04\r\n] 2006.145.10:34:08.56#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.10:34:08.56#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.10:34:08.56#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.10:34:08.56#ibcon#ireg 7 cls_cnt 0 2006.145.10:34:08.56#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.10:34:08.68#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.10:34:08.68#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.10:34:08.70#ibcon#[27=USB\r\n] 2006.145.10:34:08.73#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.10:34:08.73#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.10:34:08.73#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.10:34:08.73#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.10:34:08.73$vck44/vblo=5,709.99 2006.145.10:34:08.73#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.10:34:08.73#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.10:34:08.73#ibcon#ireg 17 cls_cnt 0 2006.145.10:34:08.73#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.10:34:08.73#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.10:34:08.73#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.10:34:08.75#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.10:34:08.79#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.10:34:08.79#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.10:34:08.79#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.10:34:08.79#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.10:34:08.79$vck44/vb=5,4 2006.145.10:34:08.79#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.10:34:08.79#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.10:34:08.79#ibcon#ireg 11 cls_cnt 2 2006.145.10:34:08.79#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.10:34:08.85#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.10:34:08.85#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.10:34:08.87#ibcon#[27=AT05-04\r\n] 2006.145.10:34:08.90#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.10:34:08.90#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.10:34:08.90#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.10:34:08.90#ibcon#ireg 7 cls_cnt 0 2006.145.10:34:08.90#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.10:34:09.02#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.10:34:09.02#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.10:34:09.04#ibcon#[27=USB\r\n] 2006.145.10:34:09.07#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.10:34:09.07#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.10:34:09.07#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.10:34:09.07#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.10:34:09.07$vck44/vblo=6,719.99 2006.145.10:34:09.07#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.10:34:09.07#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.10:34:09.07#ibcon#ireg 17 cls_cnt 0 2006.145.10:34:09.07#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.10:34:09.07#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.10:34:09.07#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.10:34:09.09#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.10:34:09.10#abcon#<5=/05 3.2 5.4 17.34 651019.4\r\n> 2006.145.10:34:09.12#abcon#{5=INTERFACE CLEAR} 2006.145.10:34:09.13#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.10:34:09.13#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.10:34:09.13#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.10:34:09.13#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.10:34:09.13$vck44/vb=6,4 2006.145.10:34:09.13#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.10:34:09.13#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.10:34:09.13#ibcon#ireg 11 cls_cnt 2 2006.145.10:34:09.13#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.10:34:09.18#abcon#[5=S1D000X0/0*\r\n] 2006.145.10:34:09.19#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.10:34:09.19#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.10:34:09.21#ibcon#[27=AT06-04\r\n] 2006.145.10:34:09.24#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.10:34:09.24#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.10:34:09.24#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.10:34:09.24#ibcon#ireg 7 cls_cnt 0 2006.145.10:34:09.24#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.10:34:09.36#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.10:34:09.36#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.10:34:09.38#ibcon#[27=USB\r\n] 2006.145.10:34:09.41#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.10:34:09.41#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.10:34:09.41#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.10:34:09.41#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.10:34:09.41$vck44/vblo=7,734.99 2006.145.10:34:09.41#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.10:34:09.41#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.10:34:09.41#ibcon#ireg 17 cls_cnt 0 2006.145.10:34:09.41#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.10:34:09.41#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.10:34:09.41#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.10:34:09.43#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.10:34:09.47#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.10:34:09.47#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.10:34:09.47#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.10:34:09.47#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.10:34:09.47$vck44/vb=7,4 2006.145.10:34:09.47#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.10:34:09.47#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.10:34:09.47#ibcon#ireg 11 cls_cnt 2 2006.145.10:34:09.47#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.10:34:09.53#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.10:34:09.53#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.10:34:09.55#ibcon#[27=AT07-04\r\n] 2006.145.10:34:09.58#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.10:34:09.58#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.10:34:09.58#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.10:34:09.58#ibcon#ireg 7 cls_cnt 0 2006.145.10:34:09.58#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.10:34:09.70#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.10:34:09.70#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.10:34:09.72#ibcon#[27=USB\r\n] 2006.145.10:34:09.75#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.10:34:09.75#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.10:34:09.75#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.10:34:09.75#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.10:34:09.75$vck44/vblo=8,744.99 2006.145.10:34:09.75#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.10:34:09.75#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.10:34:09.75#ibcon#ireg 17 cls_cnt 0 2006.145.10:34:09.75#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.10:34:09.75#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.10:34:09.75#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.10:34:09.77#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.10:34:09.81#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.10:34:09.81#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.10:34:09.81#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.10:34:09.81#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.10:34:09.81$vck44/vb=8,4 2006.145.10:34:09.81#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.10:34:09.81#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.10:34:09.81#ibcon#ireg 11 cls_cnt 2 2006.145.10:34:09.81#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.10:34:09.87#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.10:34:09.87#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.10:34:09.89#ibcon#[27=AT08-04\r\n] 2006.145.10:34:09.92#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.10:34:09.92#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.10:34:09.92#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.10:34:09.92#ibcon#ireg 7 cls_cnt 0 2006.145.10:34:09.92#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.10:34:10.04#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.10:34:10.04#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.10:34:10.06#ibcon#[27=USB\r\n] 2006.145.10:34:10.09#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.10:34:10.09#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.10:34:10.09#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.10:34:10.09#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.10:34:10.09$vck44/vabw=wide 2006.145.10:34:10.09#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.10:34:10.09#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.10:34:10.09#ibcon#ireg 8 cls_cnt 0 2006.145.10:34:10.09#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.10:34:10.09#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.10:34:10.09#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.10:34:10.11#ibcon#[25=BW32\r\n] 2006.145.10:34:10.14#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.10:34:10.14#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.10:34:10.14#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.10:34:10.14#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.10:34:10.14$vck44/vbbw=wide 2006.145.10:34:10.14#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.10:34:10.14#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.10:34:10.14#ibcon#ireg 8 cls_cnt 0 2006.145.10:34:10.14#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.10:34:10.21#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.10:34:10.21#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.10:34:10.23#ibcon#[27=BW32\r\n] 2006.145.10:34:10.26#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.10:34:10.26#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.10:34:10.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.10:34:10.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.10:34:10.26$setupk4/ifdk4 2006.145.10:34:10.26$ifdk4/lo= 2006.145.10:34:10.26$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.10:34:10.26$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.10:34:10.26$ifdk4/patch= 2006.145.10:34:10.26$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.10:34:10.26$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.10:34:10.26$setupk4/!*+20s 2006.145.10:34:18.14#trakl#Source acquired 2006.145.10:34:19.27#abcon#<5=/05 3.2 5.4 17.33 661019.4\r\n> 2006.145.10:34:19.29#abcon#{5=INTERFACE CLEAR} 2006.145.10:34:19.35#abcon#[5=S1D000X0/0*\r\n] 2006.145.10:34:20.14#flagr#flagr/antenna,acquired 2006.145.10:34:24.72$setupk4/"tpicd 2006.145.10:34:24.72$setupk4/echo=off 2006.145.10:34:24.72$setupk4/xlog=off 2006.145.10:34:24.72:!2006.145.10:35:19 2006.145.10:35:19.00:preob 2006.145.10:35:19.14/onsource/TRACKING 2006.145.10:35:19.14:!2006.145.10:35:29 2006.145.10:35:29.00:"tape 2006.145.10:35:29.00:"st=record 2006.145.10:35:29.00:data_valid=on 2006.145.10:35:29.00:midob 2006.145.10:35:29.14/onsource/TRACKING 2006.145.10:35:29.14/wx/17.33,1019.4,66 2006.145.10:35:29.28/cable/+6.5442E-03 2006.145.10:35:30.37/va/01,08,usb,yes,31,33 2006.145.10:35:30.37/va/02,07,usb,yes,33,34 2006.145.10:35:30.37/va/03,08,usb,yes,30,31 2006.145.10:35:30.37/va/04,07,usb,yes,34,36 2006.145.10:35:30.37/va/05,04,usb,yes,29,30 2006.145.10:35:30.37/va/06,04,usb,yes,33,33 2006.145.10:35:30.37/va/07,04,usb,yes,33,35 2006.145.10:35:30.37/va/08,04,usb,yes,28,34 2006.145.10:35:30.60/valo/01,524.99,yes,locked 2006.145.10:35:30.60/valo/02,534.99,yes,locked 2006.145.10:35:30.60/valo/03,564.99,yes,locked 2006.145.10:35:30.60/valo/04,624.99,yes,locked 2006.145.10:35:30.60/valo/05,734.99,yes,locked 2006.145.10:35:30.60/valo/06,814.99,yes,locked 2006.145.10:35:30.60/valo/07,864.99,yes,locked 2006.145.10:35:30.60/valo/08,884.99,yes,locked 2006.145.10:35:31.69/vb/01,03,usb,yes,45,41 2006.145.10:35:31.69/vb/02,04,usb,yes,39,39 2006.145.10:35:31.69/vb/03,04,usb,yes,35,39 2006.145.10:35:31.69/vb/04,04,usb,yes,40,39 2006.145.10:35:31.69/vb/05,04,usb,yes,31,34 2006.145.10:35:31.69/vb/06,04,usb,yes,36,32 2006.145.10:35:31.69/vb/07,04,usb,yes,36,36 2006.145.10:35:31.69/vb/08,04,usb,yes,33,37 2006.145.10:35:31.92/vblo/01,629.99,yes,locked 2006.145.10:35:31.92/vblo/02,634.99,yes,locked 2006.145.10:35:31.92/vblo/03,649.99,yes,locked 2006.145.10:35:31.92/vblo/04,679.99,yes,locked 2006.145.10:35:31.92/vblo/05,709.99,yes,locked 2006.145.10:35:31.92/vblo/06,719.99,yes,locked 2006.145.10:35:31.92/vblo/07,734.99,yes,locked 2006.145.10:35:31.92/vblo/08,744.99,yes,locked 2006.145.10:35:32.07/vabw/8 2006.145.10:35:32.22/vbbw/8 2006.145.10:35:32.42/xfe/off,on,15.0 2006.145.10:35:32.79/ifatt/23,28,28,28 2006.145.10:35:33.08/fmout-gps/S +5.3E-08 2006.145.10:35:33.12:!2006.145.10:36:49 2006.145.10:36:49.00:data_valid=off 2006.145.10:36:49.00:"et 2006.145.10:36:49.00:!+3s 2006.145.10:36:52.02:"tape 2006.145.10:36:52.02:postob 2006.145.10:36:52.10/cable/+6.5434E-03 2006.145.10:36:52.10/wx/17.31,1019.4,65 2006.145.10:36:53.08/fmout-gps/S +5.4E-08 2006.145.10:36:53.08:scan_name=145-1043,jd0605,40 2006.145.10:36:53.08:source=1424-418,142756.30,-420619.4,2000.0,cw 2006.145.10:36:54.13#flagr#flagr/antenna,new-source 2006.145.10:36:54.13:checkk5 2006.145.10:36:54.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.10:36:54.99/chk_autoobs//k5ts2/ autoobs is running! 2006.145.10:36:55.42/chk_autoobs//k5ts3/ autoobs is running! 2006.145.10:36:55.84/chk_autoobs//k5ts4/ autoobs is running! 2006.145.10:36:56.27/chk_obsdata//k5ts1/T1451035??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.10:36:56.71/chk_obsdata//k5ts2/T1451035??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.10:36:57.14/chk_obsdata//k5ts3/T1451035??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.10:36:57.57/chk_obsdata//k5ts4/T1451035??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.10:36:58.34/k5log//k5ts1_log_newline 2006.145.10:36:59.08/k5log//k5ts2_log_newline 2006.145.10:36:59.83/k5log//k5ts3_log_newline 2006.145.10:37:00.59/k5log//k5ts4_log_newline 2006.145.10:37:00.61/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.10:37:00.61:setupk4=1 2006.145.10:37:00.61$setupk4/echo=on 2006.145.10:37:00.61$setupk4/pcalon 2006.145.10:37:00.61$pcalon/"no phase cal control is implemented here 2006.145.10:37:00.61$setupk4/"tpicd=stop 2006.145.10:37:00.61$setupk4/"rec=synch_on 2006.145.10:37:00.61$setupk4/"rec_mode=128 2006.145.10:37:00.61$setupk4/!* 2006.145.10:37:00.61$setupk4/recpk4 2006.145.10:37:00.61$recpk4/recpatch= 2006.145.10:37:00.62$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.10:37:00.62$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.10:37:00.62$setupk4/vck44 2006.145.10:37:00.62$vck44/valo=1,524.99 2006.145.10:37:00.62#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.10:37:00.62#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.10:37:00.62#ibcon#ireg 17 cls_cnt 0 2006.145.10:37:00.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.10:37:00.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.10:37:00.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.10:37:00.66#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.10:37:00.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.10:37:00.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.10:37:00.71#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.10:37:00.71#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.10:37:00.71$vck44/va=1,8 2006.145.10:37:00.71#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.10:37:00.71#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.10:37:00.71#ibcon#ireg 11 cls_cnt 2 2006.145.10:37:00.71#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.10:37:00.71#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.10:37:00.71#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.10:37:00.73#ibcon#[25=AT01-08\r\n] 2006.145.10:37:00.76#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.10:37:00.76#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.10:37:00.76#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.10:37:00.76#ibcon#ireg 7 cls_cnt 0 2006.145.10:37:00.76#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.10:37:00.89#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.10:37:00.89#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.10:37:00.90#ibcon#[25=USB\r\n] 2006.145.10:37:00.93#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.10:37:00.93#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.10:37:00.93#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.10:37:00.93#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.10:37:00.93$vck44/valo=2,534.99 2006.145.10:37:00.93#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.10:37:00.93#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.10:37:00.93#ibcon#ireg 17 cls_cnt 0 2006.145.10:37:00.93#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:37:00.93#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:37:00.93#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:37:00.96#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.10:37:01.00#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:37:01.00#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:37:01.00#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.10:37:01.00#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.10:37:01.00$vck44/va=2,7 2006.145.10:37:01.00#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.10:37:01.00#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.10:37:01.00#ibcon#ireg 11 cls_cnt 2 2006.145.10:37:01.00#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.10:37:01.05#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.10:37:01.05#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.10:37:01.07#ibcon#[25=AT02-07\r\n] 2006.145.10:37:01.10#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.10:37:01.10#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.10:37:01.10#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.10:37:01.10#ibcon#ireg 7 cls_cnt 0 2006.145.10:37:01.10#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.10:37:01.22#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.10:37:01.22#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.10:37:01.24#ibcon#[25=USB\r\n] 2006.145.10:37:01.27#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.10:37:01.27#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.10:37:01.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.10:37:01.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.10:37:01.27$vck44/valo=3,564.99 2006.145.10:37:01.27#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.10:37:01.27#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.10:37:01.27#ibcon#ireg 17 cls_cnt 0 2006.145.10:37:01.27#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.10:37:01.27#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.10:37:01.27#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.10:37:01.29#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.10:37:01.33#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.10:37:01.33#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.10:37:01.33#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.10:37:01.33#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.10:37:01.33$vck44/va=3,8 2006.145.10:37:01.33#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.10:37:01.33#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.10:37:01.33#ibcon#ireg 11 cls_cnt 2 2006.145.10:37:01.33#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.10:37:01.39#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.10:37:01.39#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.10:37:01.41#ibcon#[25=AT03-08\r\n] 2006.145.10:37:01.44#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.10:37:01.44#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.10:37:01.44#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.10:37:01.44#ibcon#ireg 7 cls_cnt 0 2006.145.10:37:01.44#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.10:37:01.56#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.10:37:01.56#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.10:37:01.58#ibcon#[25=USB\r\n] 2006.145.10:37:01.61#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.10:37:01.61#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.10:37:01.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.10:37:01.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.10:37:01.61$vck44/valo=4,624.99 2006.145.10:37:01.61#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.10:37:01.61#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.10:37:01.61#ibcon#ireg 17 cls_cnt 0 2006.145.10:37:01.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.10:37:01.61#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.10:37:01.61#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.10:37:01.63#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.10:37:01.67#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.10:37:01.67#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.10:37:01.67#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.10:37:01.67#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.10:37:01.67$vck44/va=4,7 2006.145.10:37:01.67#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.10:37:01.67#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.10:37:01.67#ibcon#ireg 11 cls_cnt 2 2006.145.10:37:01.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.10:37:01.73#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.10:37:01.73#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.10:37:01.75#ibcon#[25=AT04-07\r\n] 2006.145.10:37:01.78#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.10:37:01.78#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.10:37:01.78#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.10:37:01.78#ibcon#ireg 7 cls_cnt 0 2006.145.10:37:01.78#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.10:37:01.90#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.10:37:01.90#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.10:37:01.92#ibcon#[25=USB\r\n] 2006.145.10:37:01.95#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.10:37:01.95#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.10:37:01.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.10:37:01.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.10:37:01.95$vck44/valo=5,734.99 2006.145.10:37:01.95#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.10:37:01.95#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.10:37:01.95#ibcon#ireg 17 cls_cnt 0 2006.145.10:37:01.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.10:37:01.95#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.10:37:01.95#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.10:37:01.97#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.10:37:02.01#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.10:37:02.01#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.10:37:02.01#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.10:37:02.01#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.10:37:02.01$vck44/va=5,4 2006.145.10:37:02.01#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.10:37:02.01#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.10:37:02.01#ibcon#ireg 11 cls_cnt 2 2006.145.10:37:02.01#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.10:37:02.07#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.10:37:02.07#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.10:37:02.09#ibcon#[25=AT05-04\r\n] 2006.145.10:37:02.12#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.10:37:02.12#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.10:37:02.12#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.10:37:02.12#ibcon#ireg 7 cls_cnt 0 2006.145.10:37:02.12#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.10:37:02.19#abcon#<5=/05 3.2 5.1 17.31 651019.4\r\n> 2006.145.10:37:02.21#abcon#{5=INTERFACE CLEAR} 2006.145.10:37:02.24#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.10:37:02.24#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.10:37:02.26#ibcon#[25=USB\r\n] 2006.145.10:37:02.27#abcon#[5=S1D000X0/0*\r\n] 2006.145.10:37:02.29#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.10:37:02.29#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.10:37:02.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.10:37:02.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.10:37:02.29$vck44/valo=6,814.99 2006.145.10:37:02.29#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.10:37:02.29#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.10:37:02.29#ibcon#ireg 17 cls_cnt 0 2006.145.10:37:02.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.10:37:02.29#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.10:37:02.29#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.10:37:02.32#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.10:37:02.36#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.10:37:02.36#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.10:37:02.36#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.10:37:02.36#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.10:37:02.36$vck44/va=6,4 2006.145.10:37:02.36#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.10:37:02.36#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.10:37:02.36#ibcon#ireg 11 cls_cnt 2 2006.145.10:37:02.36#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.10:37:02.41#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.10:37:02.41#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.10:37:02.43#ibcon#[25=AT06-04\r\n] 2006.145.10:37:02.46#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.10:37:02.46#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.10:37:02.46#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.10:37:02.46#ibcon#ireg 7 cls_cnt 0 2006.145.10:37:02.46#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.10:37:02.58#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.10:37:02.58#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.10:37:02.60#ibcon#[25=USB\r\n] 2006.145.10:37:02.63#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.10:37:02.63#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.10:37:02.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.10:37:02.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.10:37:02.63$vck44/valo=7,864.99 2006.145.10:37:02.63#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.10:37:02.63#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.10:37:02.63#ibcon#ireg 17 cls_cnt 0 2006.145.10:37:02.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.10:37:02.63#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.10:37:02.63#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.10:37:02.65#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.10:37:02.69#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.10:37:02.69#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.10:37:02.69#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.10:37:02.69#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.10:37:02.69$vck44/va=7,4 2006.145.10:37:02.69#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.10:37:02.69#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.10:37:02.69#ibcon#ireg 11 cls_cnt 2 2006.145.10:37:02.69#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.10:37:02.75#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.10:37:02.75#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.10:37:02.77#ibcon#[25=AT07-04\r\n] 2006.145.10:37:02.80#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.10:37:02.80#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.10:37:02.80#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.10:37:02.80#ibcon#ireg 7 cls_cnt 0 2006.145.10:37:02.80#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.10:37:02.92#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.10:37:02.92#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.10:37:02.94#ibcon#[25=USB\r\n] 2006.145.10:37:02.97#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.10:37:02.97#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.10:37:02.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.10:37:02.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.10:37:02.97$vck44/valo=8,884.99 2006.145.10:37:02.97#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.10:37:02.97#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.10:37:02.97#ibcon#ireg 17 cls_cnt 0 2006.145.10:37:02.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.10:37:02.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.10:37:02.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.10:37:02.99#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.10:37:03.03#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.10:37:03.03#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.10:37:03.03#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.10:37:03.03#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.10:37:03.03$vck44/va=8,4 2006.145.10:37:03.03#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.10:37:03.03#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.10:37:03.03#ibcon#ireg 11 cls_cnt 2 2006.145.10:37:03.03#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.10:37:03.09#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.10:37:03.09#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.10:37:03.11#ibcon#[25=AT08-04\r\n] 2006.145.10:37:03.14#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.10:37:03.14#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.10:37:03.14#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.10:37:03.14#ibcon#ireg 7 cls_cnt 0 2006.145.10:37:03.14#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.10:37:03.26#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.10:37:03.26#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.10:37:03.28#ibcon#[25=USB\r\n] 2006.145.10:37:03.31#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.10:37:03.31#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.10:37:03.31#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.10:37:03.31#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.10:37:03.31$vck44/vblo=1,629.99 2006.145.10:37:03.31#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.10:37:03.31#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.10:37:03.31#ibcon#ireg 17 cls_cnt 0 2006.145.10:37:03.31#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.10:37:03.31#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.10:37:03.31#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.10:37:03.33#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.10:37:03.37#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.10:37:03.37#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.10:37:03.37#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.10:37:03.37#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.10:37:03.37$vck44/vb=1,3 2006.145.10:37:03.37#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.10:37:03.37#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.10:37:03.37#ibcon#ireg 11 cls_cnt 2 2006.145.10:37:03.37#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.10:37:03.37#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.10:37:03.37#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.10:37:03.39#ibcon#[27=AT01-03\r\n] 2006.145.10:37:03.42#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.10:37:03.42#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.10:37:03.42#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.10:37:03.42#ibcon#ireg 7 cls_cnt 0 2006.145.10:37:03.42#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.10:37:03.54#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.10:37:03.54#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.10:37:03.56#ibcon#[27=USB\r\n] 2006.145.10:37:03.59#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.10:37:03.59#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.10:37:03.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.10:37:03.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.10:37:03.59$vck44/vblo=2,634.99 2006.145.10:37:03.59#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.10:37:03.59#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.10:37:03.59#ibcon#ireg 17 cls_cnt 0 2006.145.10:37:03.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:37:03.59#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:37:03.59#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:37:03.61#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.10:37:03.65#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:37:03.65#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:37:03.65#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.10:37:03.65#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.10:37:03.65$vck44/vb=2,4 2006.145.10:37:03.65#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.10:37:03.65#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.10:37:03.65#ibcon#ireg 11 cls_cnt 2 2006.145.10:37:03.65#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.10:37:03.71#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.10:37:03.71#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.10:37:03.73#ibcon#[27=AT02-04\r\n] 2006.145.10:37:03.76#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.10:37:03.76#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.10:37:03.76#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.10:37:03.76#ibcon#ireg 7 cls_cnt 0 2006.145.10:37:03.76#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.10:37:03.88#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.10:37:03.88#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.10:37:03.90#ibcon#[27=USB\r\n] 2006.145.10:37:03.93#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.10:37:03.93#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.10:37:03.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.10:37:03.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.10:37:03.93$vck44/vblo=3,649.99 2006.145.10:37:03.93#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.10:37:03.93#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.10:37:03.93#ibcon#ireg 17 cls_cnt 0 2006.145.10:37:03.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.10:37:03.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.10:37:03.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.10:37:03.95#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.10:37:03.99#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.10:37:03.99#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.10:37:03.99#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.10:37:03.99#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.10:37:03.99$vck44/vb=3,4 2006.145.10:37:03.99#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.10:37:03.99#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.10:37:03.99#ibcon#ireg 11 cls_cnt 2 2006.145.10:37:03.99#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.10:37:04.05#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.10:37:04.05#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.10:37:04.07#ibcon#[27=AT03-04\r\n] 2006.145.10:37:04.10#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.10:37:04.10#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.10:37:04.10#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.10:37:04.10#ibcon#ireg 7 cls_cnt 0 2006.145.10:37:04.10#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.10:37:04.22#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.10:37:04.22#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.10:37:04.24#ibcon#[27=USB\r\n] 2006.145.10:37:04.27#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.10:37:04.27#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.10:37:04.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.10:37:04.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.10:37:04.27$vck44/vblo=4,679.99 2006.145.10:37:04.27#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.10:37:04.27#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.10:37:04.27#ibcon#ireg 17 cls_cnt 0 2006.145.10:37:04.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.10:37:04.27#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.10:37:04.27#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.10:37:04.29#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.10:37:04.33#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.10:37:04.33#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.10:37:04.33#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.10:37:04.33#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.10:37:04.33$vck44/vb=4,4 2006.145.10:37:04.33#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.10:37:04.33#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.10:37:04.33#ibcon#ireg 11 cls_cnt 2 2006.145.10:37:04.33#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.10:37:04.39#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.10:37:04.39#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.10:37:04.41#ibcon#[27=AT04-04\r\n] 2006.145.10:37:04.44#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.10:37:04.44#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.10:37:04.44#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.10:37:04.44#ibcon#ireg 7 cls_cnt 0 2006.145.10:37:04.44#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.10:37:04.56#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.10:37:04.56#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.10:37:04.58#ibcon#[27=USB\r\n] 2006.145.10:37:04.61#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.10:37:04.61#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.10:37:04.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.10:37:04.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.10:37:04.61$vck44/vblo=5,709.99 2006.145.10:37:04.61#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.10:37:04.61#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.10:37:04.61#ibcon#ireg 17 cls_cnt 0 2006.145.10:37:04.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.10:37:04.61#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.10:37:04.61#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.10:37:04.63#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.10:37:04.67#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.10:37:04.67#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.10:37:04.67#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.10:37:04.67#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.10:37:04.67$vck44/vb=5,4 2006.145.10:37:04.67#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.10:37:04.67#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.10:37:04.67#ibcon#ireg 11 cls_cnt 2 2006.145.10:37:04.67#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.10:37:04.73#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.10:37:04.73#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.10:37:04.75#ibcon#[27=AT05-04\r\n] 2006.145.10:37:04.78#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.10:37:04.78#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.10:37:04.78#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.10:37:04.78#ibcon#ireg 7 cls_cnt 0 2006.145.10:37:04.78#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.10:37:04.90#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.10:37:04.90#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.10:37:04.92#ibcon#[27=USB\r\n] 2006.145.10:37:04.95#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.10:37:04.95#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.10:37:04.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.10:37:04.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.10:37:04.95$vck44/vblo=6,719.99 2006.145.10:37:04.95#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.10:37:04.95#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.10:37:04.95#ibcon#ireg 17 cls_cnt 0 2006.145.10:37:04.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.10:37:04.95#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.10:37:04.95#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.10:37:04.97#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.10:37:05.01#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.10:37:05.01#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.10:37:05.01#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.10:37:05.01#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.10:37:05.01$vck44/vb=6,4 2006.145.10:37:05.01#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.10:37:05.01#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.10:37:05.01#ibcon#ireg 11 cls_cnt 2 2006.145.10:37:05.01#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.10:37:05.07#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.10:37:05.07#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.10:37:05.09#ibcon#[27=AT06-04\r\n] 2006.145.10:37:05.12#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.10:37:05.12#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.10:37:05.12#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.10:37:05.12#ibcon#ireg 7 cls_cnt 0 2006.145.10:37:05.12#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.10:37:05.24#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.10:37:05.24#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.10:37:05.26#ibcon#[27=USB\r\n] 2006.145.10:37:05.29#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.10:37:05.29#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.10:37:05.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.10:37:05.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.10:37:05.29$vck44/vblo=7,734.99 2006.145.10:37:05.29#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.10:37:05.29#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.10:37:05.29#ibcon#ireg 17 cls_cnt 0 2006.145.10:37:05.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.10:37:05.29#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.10:37:05.29#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.10:37:05.31#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.10:37:05.35#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.10:37:05.35#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.10:37:05.35#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.10:37:05.35#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.10:37:05.35$vck44/vb=7,4 2006.145.10:37:05.35#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.10:37:05.35#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.10:37:05.35#ibcon#ireg 11 cls_cnt 2 2006.145.10:37:05.35#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.10:37:05.41#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.10:37:05.41#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.10:37:05.43#ibcon#[27=AT07-04\r\n] 2006.145.10:37:05.46#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.10:37:05.46#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.10:37:05.46#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.10:37:05.46#ibcon#ireg 7 cls_cnt 0 2006.145.10:37:05.46#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.10:37:05.58#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.10:37:05.58#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.10:37:05.60#ibcon#[27=USB\r\n] 2006.145.10:37:05.63#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.10:37:05.63#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.10:37:05.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.10:37:05.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.10:37:05.63$vck44/vblo=8,744.99 2006.145.10:37:05.63#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.10:37:05.63#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.10:37:05.63#ibcon#ireg 17 cls_cnt 0 2006.145.10:37:05.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.10:37:05.63#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.10:37:05.63#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.10:37:05.65#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.10:37:05.69#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.10:37:05.69#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.10:37:05.69#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.10:37:05.69#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.10:37:05.69$vck44/vb=8,4 2006.145.10:37:05.69#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.10:37:05.69#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.10:37:05.69#ibcon#ireg 11 cls_cnt 2 2006.145.10:37:05.69#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.10:37:05.75#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.10:37:05.75#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.10:37:05.77#ibcon#[27=AT08-04\r\n] 2006.145.10:37:05.80#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.10:37:05.80#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.10:37:05.80#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.10:37:05.80#ibcon#ireg 7 cls_cnt 0 2006.145.10:37:05.80#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.10:37:05.92#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.10:37:05.92#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.10:37:05.94#ibcon#[27=USB\r\n] 2006.145.10:37:05.97#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.10:37:05.97#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.10:37:05.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.10:37:05.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.10:37:05.97$vck44/vabw=wide 2006.145.10:37:05.97#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.10:37:05.97#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.10:37:05.97#ibcon#ireg 8 cls_cnt 0 2006.145.10:37:05.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.10:37:05.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.10:37:05.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.10:37:05.99#ibcon#[25=BW32\r\n] 2006.145.10:37:06.02#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.10:37:06.02#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.10:37:06.02#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.10:37:06.02#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.10:37:06.02$vck44/vbbw=wide 2006.145.10:37:06.02#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.10:37:06.02#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.10:37:06.02#ibcon#ireg 8 cls_cnt 0 2006.145.10:37:06.02#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.10:37:06.09#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.10:37:06.09#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.10:37:06.11#ibcon#[27=BW32\r\n] 2006.145.10:37:06.14#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.10:37:06.14#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.10:37:06.14#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.10:37:06.14#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.10:37:06.14$setupk4/ifdk4 2006.145.10:37:06.14$ifdk4/lo= 2006.145.10:37:06.14$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.10:37:06.14$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.10:37:06.14$ifdk4/patch= 2006.145.10:37:06.14$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.10:37:06.14$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.10:37:06.14$setupk4/!*+20s 2006.145.10:37:12.36#abcon#<5=/05 3.2 5.1 17.31 651019.4\r\n> 2006.145.10:37:12.38#abcon#{5=INTERFACE CLEAR} 2006.145.10:37:12.46#abcon#[5=S1D000X0/0*\r\n] 2006.145.10:37:20.62$setupk4/"tpicd 2006.145.10:37:20.62$setupk4/echo=off 2006.145.10:37:20.62$setupk4/xlog=off 2006.145.10:37:20.62:!2006.145.10:43:25 2006.145.10:37:28.13#trakl#Source acquired 2006.145.10:37:29.13#flagr#flagr/antenna,acquired 2006.145.10:43:25.00:preob 2006.145.10:43:25.15/onsource/TRACKING 2006.145.10:43:25.15:!2006.145.10:43:35 2006.145.10:43:35.02:"tape 2006.145.10:43:35.02:"st=record 2006.145.10:43:35.02:data_valid=on 2006.145.10:43:35.02:midob 2006.145.10:43:36.15/onsource/TRACKING 2006.145.10:43:36.15/wx/17.21,1019.6,66 2006.145.10:43:36.33/cable/+6.5454E-03 2006.145.10:43:37.42/va/01,08,usb,yes,37,40 2006.145.10:43:37.42/va/02,07,usb,yes,40,41 2006.145.10:43:37.42/va/03,08,usb,yes,37,38 2006.145.10:43:37.42/va/04,07,usb,yes,41,43 2006.145.10:43:37.42/va/05,04,usb,yes,36,37 2006.145.10:43:37.42/va/06,04,usb,yes,40,40 2006.145.10:43:37.42/va/07,04,usb,yes,41,42 2006.145.10:43:37.42/va/08,04,usb,yes,35,42 2006.145.10:43:37.65/valo/01,524.99,yes,locked 2006.145.10:43:37.65/valo/02,534.99,yes,locked 2006.145.10:43:37.65/valo/03,564.99,yes,locked 2006.145.10:43:37.65/valo/04,624.99,yes,locked 2006.145.10:43:37.65/valo/05,734.99,yes,locked 2006.145.10:43:37.65/valo/06,814.99,yes,locked 2006.145.10:43:37.65/valo/07,864.99,yes,locked 2006.145.10:43:37.65/valo/08,884.99,yes,locked 2006.145.10:43:38.74/vb/01,03,usb,yes,39,41 2006.145.10:43:38.74/vb/02,04,usb,yes,34,39 2006.145.10:43:38.74/vb/03,04,usb,yes,31,35 2006.145.10:43:38.74/vb/04,04,usb,yes,36,34 2006.145.10:43:38.74/vb/05,04,usb,yes,28,31 2006.145.10:43:38.74/vb/06,04,usb,yes,33,29 2006.145.10:43:38.74/vb/07,04,usb,yes,33,32 2006.145.10:43:38.74/vb/08,04,usb,yes,30,34 2006.145.10:43:38.97/vblo/01,629.99,yes,locked 2006.145.10:43:38.97/vblo/02,634.99,yes,locked 2006.145.10:43:38.97/vblo/03,649.99,yes,locked 2006.145.10:43:38.97/vblo/04,679.99,yes,locked 2006.145.10:43:38.97/vblo/05,709.99,yes,locked 2006.145.10:43:38.97/vblo/06,719.99,yes,locked 2006.145.10:43:38.97/vblo/07,734.99,yes,locked 2006.145.10:43:38.97/vblo/08,744.99,yes,locked 2006.145.10:43:39.12/vabw/8 2006.145.10:43:39.27/vbbw/8 2006.145.10:43:39.36/xfe/off,on,15.2 2006.145.10:43:39.73/ifatt/23,28,28,28 2006.145.10:43:40.07/fmout-gps/S +5.7E-08 2006.145.10:43:40.16:!2006.145.10:44:15 2006.145.10:44:15.02:data_valid=off 2006.145.10:44:15.02:"et 2006.145.10:44:15.02:!+3s 2006.145.10:44:18.05:"tape 2006.145.10:44:18.06:postob 2006.145.10:44:18.21/cable/+6.5422E-03 2006.145.10:44:18.22/wx/17.19,1019.6,66 2006.145.10:44:18.29/fmout-gps/S +5.6E-08 2006.145.10:44:18.29:scan_name=145-1049,jd0605,70 2006.145.10:44:18.30:source=1611+343,161341.06,341247.9,2000.0,cw 2006.145.10:44:19.14#flagr#flagr/antenna,new-source 2006.145.10:44:19.15:checkk5 2006.145.10:44:19.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.10:44:20.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.10:44:20.48/chk_autoobs//k5ts3/ autoobs is running! 2006.145.10:44:20.91/chk_autoobs//k5ts4/ autoobs is running! 2006.145.10:44:21.34/chk_obsdata//k5ts1/T1451043??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.10:44:21.77/chk_obsdata//k5ts2/T1451043??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.10:44:22.22/chk_obsdata//k5ts3/T1451043??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.10:44:22.66/chk_obsdata//k5ts4/T1451043??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.10:44:23.41/k5log//k5ts1_log_newline 2006.145.10:44:24.16/k5log//k5ts2_log_newline 2006.145.10:44:24.90/k5log//k5ts3_log_newline 2006.145.10:44:25.66/k5log//k5ts4_log_newline 2006.145.10:44:25.69/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.10:44:25.69:setupk4=1 2006.145.10:44:25.69$setupk4/echo=on 2006.145.10:44:25.69$setupk4/pcalon 2006.145.10:44:25.69$pcalon/"no phase cal control is implemented here 2006.145.10:44:25.69$setupk4/"tpicd=stop 2006.145.10:44:25.69$setupk4/"rec=synch_on 2006.145.10:44:25.69$setupk4/"rec_mode=128 2006.145.10:44:25.69$setupk4/!* 2006.145.10:44:25.69$setupk4/recpk4 2006.145.10:44:25.69$recpk4/recpatch= 2006.145.10:44:25.69$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.10:44:25.69$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.10:44:25.69$setupk4/vck44 2006.145.10:44:25.69$vck44/valo=1,524.99 2006.145.10:44:25.69#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.10:44:25.69#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.10:44:25.69#ibcon#ireg 17 cls_cnt 0 2006.145.10:44:25.69#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.10:44:25.69#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.10:44:25.69#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.10:44:25.73#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.10:44:25.77#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.10:44:25.77#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.10:44:25.77#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.10:44:25.77#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.10:44:25.77$vck44/va=1,8 2006.145.10:44:25.77#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.10:44:25.77#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.10:44:25.77#ibcon#ireg 11 cls_cnt 2 2006.145.10:44:25.77#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.10:44:25.77#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.10:44:25.77#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.10:44:25.79#ibcon#[25=AT01-08\r\n] 2006.145.10:44:25.82#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.10:44:25.82#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.10:44:25.82#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.10:44:25.82#ibcon#ireg 7 cls_cnt 0 2006.145.10:44:25.82#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.10:44:25.95#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.10:44:25.95#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.10:44:25.97#ibcon#[25=USB\r\n] 2006.145.10:44:25.99#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.10:44:25.99#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.10:44:25.99#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.10:44:25.99#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.10:44:25.99$vck44/valo=2,534.99 2006.145.10:44:25.99#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.10:44:25.99#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.10:44:25.99#ibcon#ireg 17 cls_cnt 0 2006.145.10:44:25.99#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.10:44:25.99#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.10:44:25.99#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.10:44:26.02#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.10:44:26.06#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.10:44:26.06#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.10:44:26.06#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.10:44:26.06#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.10:44:26.06$vck44/va=2,7 2006.145.10:44:26.06#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.10:44:26.06#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.10:44:26.06#ibcon#ireg 11 cls_cnt 2 2006.145.10:44:26.06#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.10:44:26.11#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.10:44:26.11#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.10:44:26.13#ibcon#[25=AT02-07\r\n] 2006.145.10:44:26.16#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.10:44:26.16#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.10:44:26.16#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.10:44:26.16#ibcon#ireg 7 cls_cnt 0 2006.145.10:44:26.16#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.10:44:26.28#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.10:44:26.28#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.10:44:26.30#ibcon#[25=USB\r\n] 2006.145.10:44:26.33#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.10:44:26.33#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.10:44:26.33#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.10:44:26.33#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.10:44:26.33$vck44/valo=3,564.99 2006.145.10:44:26.33#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.10:44:26.33#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.10:44:26.33#ibcon#ireg 17 cls_cnt 0 2006.145.10:44:26.33#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.10:44:26.33#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.10:44:26.33#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.10:44:26.35#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.10:44:26.39#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.10:44:26.39#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.10:44:26.39#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.10:44:26.39#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.10:44:26.39$vck44/va=3,8 2006.145.10:44:26.39#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.10:44:26.39#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.10:44:26.39#ibcon#ireg 11 cls_cnt 2 2006.145.10:44:26.39#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.10:44:26.45#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.10:44:26.45#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.10:44:26.47#ibcon#[25=AT03-08\r\n] 2006.145.10:44:26.50#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.10:44:26.50#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.10:44:26.50#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.10:44:26.50#ibcon#ireg 7 cls_cnt 0 2006.145.10:44:26.50#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.10:44:26.62#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.10:44:26.62#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.10:44:26.64#ibcon#[25=USB\r\n] 2006.145.10:44:26.67#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.10:44:26.67#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.10:44:26.67#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.10:44:26.67#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.10:44:26.67$vck44/valo=4,624.99 2006.145.10:44:26.67#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.10:44:26.67#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.10:44:26.67#ibcon#ireg 17 cls_cnt 0 2006.145.10:44:26.67#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.10:44:26.67#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.10:44:26.67#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.10:44:26.69#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.10:44:26.73#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.10:44:26.73#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.10:44:26.73#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.10:44:26.73#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.10:44:26.73$vck44/va=4,7 2006.145.10:44:26.73#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.10:44:26.73#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.10:44:26.73#ibcon#ireg 11 cls_cnt 2 2006.145.10:44:26.73#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.10:44:26.79#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.10:44:26.79#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.10:44:26.81#ibcon#[25=AT04-07\r\n] 2006.145.10:44:26.84#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.10:44:26.84#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.10:44:26.84#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.10:44:26.84#ibcon#ireg 7 cls_cnt 0 2006.145.10:44:26.84#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.10:44:26.96#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.10:44:26.96#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.10:44:26.98#ibcon#[25=USB\r\n] 2006.145.10:44:27.01#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.10:44:27.01#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.10:44:27.01#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.10:44:27.01#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.10:44:27.01$vck44/valo=5,734.99 2006.145.10:44:27.01#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.10:44:27.01#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.10:44:27.01#ibcon#ireg 17 cls_cnt 0 2006.145.10:44:27.01#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.10:44:27.01#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.10:44:27.01#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.10:44:27.03#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.10:44:27.07#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.10:44:27.07#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.10:44:27.07#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.10:44:27.07#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.10:44:27.07$vck44/va=5,4 2006.145.10:44:27.07#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.10:44:27.07#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.10:44:27.07#ibcon#ireg 11 cls_cnt 2 2006.145.10:44:27.07#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.10:44:27.13#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.10:44:27.13#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.10:44:27.16#ibcon#[25=AT05-04\r\n] 2006.145.10:44:27.19#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.10:44:27.19#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.10:44:27.19#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.10:44:27.19#ibcon#ireg 7 cls_cnt 0 2006.145.10:44:27.19#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.10:44:27.31#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.10:44:27.31#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.10:44:27.33#ibcon#[25=USB\r\n] 2006.145.10:44:27.36#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.10:44:27.36#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.10:44:27.36#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.10:44:27.36#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.10:44:27.36$vck44/valo=6,814.99 2006.145.10:44:27.36#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.10:44:27.36#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.10:44:27.36#ibcon#ireg 17 cls_cnt 0 2006.145.10:44:27.36#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.10:44:27.36#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.10:44:27.36#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.10:44:27.38#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.10:44:27.42#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.10:44:27.42#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.10:44:27.42#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.10:44:27.42#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.10:44:27.42$vck44/va=6,4 2006.145.10:44:27.42#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.10:44:27.42#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.10:44:27.42#ibcon#ireg 11 cls_cnt 2 2006.145.10:44:27.42#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.10:44:27.48#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.10:44:27.48#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.10:44:27.50#ibcon#[25=AT06-04\r\n] 2006.145.10:44:27.53#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.10:44:27.53#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.10:44:27.53#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.10:44:27.53#ibcon#ireg 7 cls_cnt 0 2006.145.10:44:27.53#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.10:44:27.65#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.10:44:27.65#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.10:44:27.67#ibcon#[25=USB\r\n] 2006.145.10:44:27.70#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.10:44:27.70#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.10:44:27.70#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.10:44:27.70#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.10:44:27.70$vck44/valo=7,864.99 2006.145.10:44:27.70#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.10:44:27.70#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.10:44:27.70#ibcon#ireg 17 cls_cnt 0 2006.145.10:44:27.70#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.10:44:27.70#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.10:44:27.70#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.10:44:27.72#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.10:44:27.76#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.10:44:27.76#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.10:44:27.76#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.10:44:27.76#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.10:44:27.76$vck44/va=7,4 2006.145.10:44:27.76#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.10:44:27.76#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.10:44:27.76#ibcon#ireg 11 cls_cnt 2 2006.145.10:44:27.76#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.10:44:27.82#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.10:44:27.82#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.10:44:27.84#ibcon#[25=AT07-04\r\n] 2006.145.10:44:27.87#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.10:44:27.87#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.10:44:27.87#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.10:44:27.87#ibcon#ireg 7 cls_cnt 0 2006.145.10:44:27.87#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.10:44:27.99#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.10:44:27.99#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.10:44:28.01#ibcon#[25=USB\r\n] 2006.145.10:44:28.04#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.10:44:28.04#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.10:44:28.04#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.10:44:28.04#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.10:44:28.04$vck44/valo=8,884.99 2006.145.10:44:28.04#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.10:44:28.04#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.10:44:28.04#ibcon#ireg 17 cls_cnt 0 2006.145.10:44:28.04#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.10:44:28.04#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.10:44:28.04#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.10:44:28.06#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.10:44:28.10#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.10:44:28.10#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.10:44:28.10#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.10:44:28.10#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.10:44:28.10$vck44/va=8,4 2006.145.10:44:28.10#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.10:44:28.10#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.10:44:28.10#ibcon#ireg 11 cls_cnt 2 2006.145.10:44:28.10#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.10:44:28.16#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.10:44:28.16#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.10:44:28.18#ibcon#[25=AT08-04\r\n] 2006.145.10:44:28.21#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.10:44:28.21#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.10:44:28.21#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.10:44:28.21#ibcon#ireg 7 cls_cnt 0 2006.145.10:44:28.21#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.10:44:28.33#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.10:44:28.33#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.10:44:28.35#ibcon#[25=USB\r\n] 2006.145.10:44:28.39#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.10:44:28.39#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.10:44:28.39#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.10:44:28.39#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.10:44:28.39$vck44/vblo=1,629.99 2006.145.10:44:28.39#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.10:44:28.39#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.10:44:28.39#ibcon#ireg 17 cls_cnt 0 2006.145.10:44:28.39#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.10:44:28.39#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.10:44:28.39#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.10:44:28.41#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.10:44:28.44#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.10:44:28.44#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.10:44:28.44#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.10:44:28.44#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.10:44:28.44$vck44/vb=1,3 2006.145.10:44:28.44#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.10:44:28.44#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.10:44:28.44#ibcon#ireg 11 cls_cnt 2 2006.145.10:44:28.44#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.10:44:28.44#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.10:44:28.44#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.10:44:28.46#ibcon#[27=AT01-03\r\n] 2006.145.10:44:28.49#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.10:44:28.49#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.10:44:28.49#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.10:44:28.49#ibcon#ireg 7 cls_cnt 0 2006.145.10:44:28.49#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.10:44:28.61#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.10:44:28.61#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.10:44:28.63#ibcon#[27=USB\r\n] 2006.145.10:44:28.66#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.10:44:28.66#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.10:44:28.66#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.10:44:28.66#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.10:44:28.66$vck44/vblo=2,634.99 2006.145.10:44:28.66#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.10:44:28.66#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.10:44:28.66#ibcon#ireg 17 cls_cnt 0 2006.145.10:44:28.66#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.10:44:28.66#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.10:44:28.66#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.10:44:28.68#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.10:44:28.72#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.10:44:28.72#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.10:44:28.72#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.10:44:28.72#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.10:44:28.72$vck44/vb=2,4 2006.145.10:44:28.72#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.10:44:28.72#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.10:44:28.72#ibcon#ireg 11 cls_cnt 2 2006.145.10:44:28.72#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.10:44:28.78#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.10:44:28.78#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.10:44:28.80#ibcon#[27=AT02-04\r\n] 2006.145.10:44:28.83#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.10:44:28.83#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.10:44:28.83#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.10:44:28.83#ibcon#ireg 7 cls_cnt 0 2006.145.10:44:28.83#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.10:44:28.95#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.10:44:28.95#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.10:44:28.97#ibcon#[27=USB\r\n] 2006.145.10:44:29.00#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.10:44:29.00#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.10:44:29.00#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.10:44:29.00#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.10:44:29.00$vck44/vblo=3,649.99 2006.145.10:44:29.00#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.10:44:29.00#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.10:44:29.00#ibcon#ireg 17 cls_cnt 0 2006.145.10:44:29.00#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.10:44:29.00#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.10:44:29.00#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.10:44:29.02#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.10:44:29.06#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.10:44:29.06#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.10:44:29.06#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.10:44:29.06#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.10:44:29.06$vck44/vb=3,4 2006.145.10:44:29.06#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.10:44:29.06#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.10:44:29.06#ibcon#ireg 11 cls_cnt 2 2006.145.10:44:29.06#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.10:44:29.12#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.10:44:29.12#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.10:44:29.14#ibcon#[27=AT03-04\r\n] 2006.145.10:44:29.17#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.10:44:29.17#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.10:44:29.17#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.10:44:29.17#ibcon#ireg 7 cls_cnt 0 2006.145.10:44:29.17#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.10:44:29.29#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.10:44:29.29#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.10:44:29.31#ibcon#[27=USB\r\n] 2006.145.10:44:29.34#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.10:44:29.34#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.10:44:29.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.10:44:29.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.10:44:29.34$vck44/vblo=4,679.99 2006.145.10:44:29.34#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.10:44:29.34#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.10:44:29.34#ibcon#ireg 17 cls_cnt 0 2006.145.10:44:29.34#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.10:44:29.34#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.10:44:29.34#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.10:44:29.36#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.10:44:29.40#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.10:44:29.40#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.10:44:29.40#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.10:44:29.40#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.10:44:29.40$vck44/vb=4,4 2006.145.10:44:29.40#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.10:44:29.40#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.10:44:29.40#ibcon#ireg 11 cls_cnt 2 2006.145.10:44:29.40#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.10:44:29.46#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.10:44:29.46#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.10:44:29.48#ibcon#[27=AT04-04\r\n] 2006.145.10:44:29.51#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.10:44:29.51#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.10:44:29.51#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.10:44:29.51#ibcon#ireg 7 cls_cnt 0 2006.145.10:44:29.51#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.10:44:29.63#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.10:44:29.63#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.10:44:29.65#ibcon#[27=USB\r\n] 2006.145.10:44:29.68#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.10:44:29.68#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.10:44:29.68#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.10:44:29.68#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.10:44:29.68$vck44/vblo=5,709.99 2006.145.10:44:29.68#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.10:44:29.68#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.10:44:29.68#ibcon#ireg 17 cls_cnt 0 2006.145.10:44:29.68#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.10:44:29.68#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.10:44:29.68#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.10:44:29.70#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.10:44:29.72#abcon#<5=/06 3.4 5.9 17.19 651019.6\r\n> 2006.145.10:44:29.74#abcon#{5=INTERFACE CLEAR} 2006.145.10:44:29.74#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.10:44:29.74#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.10:44:29.74#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.10:44:29.74#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.10:44:29.74$vck44/vb=5,4 2006.145.10:44:29.74#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.10:44:29.74#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.10:44:29.74#ibcon#ireg 11 cls_cnt 2 2006.145.10:44:29.74#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.10:44:29.80#abcon#[5=S1D000X0/0*\r\n] 2006.145.10:44:29.80#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.10:44:29.80#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.10:44:29.82#ibcon#[27=AT05-04\r\n] 2006.145.10:44:29.85#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.10:44:29.85#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.10:44:29.85#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.10:44:29.85#ibcon#ireg 7 cls_cnt 0 2006.145.10:44:29.85#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.10:44:29.97#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.10:44:29.97#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.10:44:29.99#ibcon#[27=USB\r\n] 2006.145.10:44:30.02#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.10:44:30.02#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.10:44:30.02#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.10:44:30.02#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.10:44:30.02$vck44/vblo=6,719.99 2006.145.10:44:30.02#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.10:44:30.02#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.10:44:30.02#ibcon#ireg 17 cls_cnt 0 2006.145.10:44:30.02#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.10:44:30.02#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.10:44:30.02#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.10:44:30.04#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.10:44:30.08#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.10:44:30.08#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.10:44:30.08#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.10:44:30.08#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.10:44:30.08$vck44/vb=6,4 2006.145.10:44:30.08#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.10:44:30.08#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.10:44:30.08#ibcon#ireg 11 cls_cnt 2 2006.145.10:44:30.08#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.10:44:30.14#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.10:44:30.14#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.10:44:30.16#ibcon#[27=AT06-04\r\n] 2006.145.10:44:30.19#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.10:44:30.19#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.10:44:30.19#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.10:44:30.19#ibcon#ireg 7 cls_cnt 0 2006.145.10:44:30.19#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.10:44:30.31#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.10:44:30.31#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.10:44:30.33#ibcon#[27=USB\r\n] 2006.145.10:44:30.36#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.10:44:30.36#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.10:44:30.36#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.10:44:30.36#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.10:44:30.36$vck44/vblo=7,734.99 2006.145.10:44:30.36#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.10:44:30.36#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.10:44:30.36#ibcon#ireg 17 cls_cnt 0 2006.145.10:44:30.36#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.10:44:30.36#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.10:44:30.36#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.10:44:30.38#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.10:44:30.42#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.10:44:30.42#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.10:44:30.42#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.10:44:30.42#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.10:44:30.42$vck44/vb=7,4 2006.145.10:44:30.42#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.10:44:30.42#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.10:44:30.42#ibcon#ireg 11 cls_cnt 2 2006.145.10:44:30.42#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.10:44:30.48#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.10:44:30.48#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.10:44:30.50#ibcon#[27=AT07-04\r\n] 2006.145.10:44:30.53#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.10:44:30.53#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.10:44:30.53#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.10:44:30.53#ibcon#ireg 7 cls_cnt 0 2006.145.10:44:30.53#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.10:44:30.65#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.10:44:30.65#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.10:44:30.67#ibcon#[27=USB\r\n] 2006.145.10:44:30.70#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.10:44:30.70#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.10:44:30.70#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.10:44:30.70#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.10:44:30.70$vck44/vblo=8,744.99 2006.145.10:44:30.70#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.10:44:30.70#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.10:44:30.70#ibcon#ireg 17 cls_cnt 0 2006.145.10:44:30.70#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.10:44:30.70#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.10:44:30.70#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.10:44:30.72#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.10:44:30.76#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.10:44:30.76#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.10:44:30.76#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.10:44:30.76#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.10:44:30.76$vck44/vb=8,4 2006.145.10:44:30.76#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.10:44:30.76#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.10:44:30.76#ibcon#ireg 11 cls_cnt 2 2006.145.10:44:30.76#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.10:44:30.82#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.10:44:30.82#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.10:44:30.84#ibcon#[27=AT08-04\r\n] 2006.145.10:44:30.87#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.10:44:30.87#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.10:44:30.87#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.10:44:30.87#ibcon#ireg 7 cls_cnt 0 2006.145.10:44:30.87#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.10:44:30.99#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.10:44:30.99#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.10:44:31.01#ibcon#[27=USB\r\n] 2006.145.10:44:31.04#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.10:44:31.04#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.10:44:31.04#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.10:44:31.04#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.10:44:31.04$vck44/vabw=wide 2006.145.10:44:31.04#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.10:44:31.04#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.10:44:31.04#ibcon#ireg 8 cls_cnt 0 2006.145.10:44:31.04#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.10:44:31.04#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.10:44:31.04#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.10:44:31.06#ibcon#[25=BW32\r\n] 2006.145.10:44:31.09#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.10:44:31.09#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.10:44:31.09#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.10:44:31.09#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.10:44:31.09$vck44/vbbw=wide 2006.145.10:44:31.09#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.10:44:31.09#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.10:44:31.09#ibcon#ireg 8 cls_cnt 0 2006.145.10:44:31.09#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.10:44:31.16#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.10:44:31.16#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.10:44:31.18#ibcon#[27=BW32\r\n] 2006.145.10:44:31.21#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.10:44:31.21#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.10:44:31.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.10:44:31.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.10:44:31.21$setupk4/ifdk4 2006.145.10:44:31.21$ifdk4/lo= 2006.145.10:44:31.21$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.10:44:31.21$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.10:44:31.22$ifdk4/patch= 2006.145.10:44:31.22$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.10:44:31.22$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.10:44:31.22$setupk4/!*+20s 2006.145.10:44:39.89#abcon#<5=/06 3.4 5.9 17.18 641019.6\r\n> 2006.145.10:44:39.91#abcon#{5=INTERFACE CLEAR} 2006.145.10:44:39.97#abcon#[5=S1D000X0/0*\r\n] 2006.145.10:44:45.71$setupk4/"tpicd 2006.145.10:44:45.71$setupk4/echo=off 2006.145.10:44:45.71$setupk4/xlog=off 2006.145.10:44:45.71:!2006.145.10:49:36 2006.145.10:44:54.14#trakl#Source acquired 2006.145.10:44:54.14#flagr#flagr/antenna,acquired 2006.145.10:49:36.00:preob 2006.145.10:49:37.14/onsource/TRACKING 2006.145.10:49:37.14:!2006.145.10:49:46 2006.145.10:49:46.00:"tape 2006.145.10:49:46.00:"st=record 2006.145.10:49:46.00:data_valid=on 2006.145.10:49:46.00:midob 2006.145.10:49:46.14/onsource/TRACKING 2006.145.10:49:46.14/wx/17.09,1019.6,64 2006.145.10:49:46.32/cable/+6.5459E-03 2006.145.10:49:47.41/va/01,08,usb,yes,28,31 2006.145.10:49:47.41/va/02,07,usb,yes,30,31 2006.145.10:49:47.41/va/03,08,usb,yes,28,29 2006.145.10:49:47.41/va/04,07,usb,yes,32,33 2006.145.10:49:47.41/va/05,04,usb,yes,27,28 2006.145.10:49:47.41/va/06,04,usb,yes,31,31 2006.145.10:49:47.41/va/07,04,usb,yes,31,32 2006.145.10:49:47.41/va/08,04,usb,yes,26,32 2006.145.10:49:47.64/valo/01,524.99,yes,locked 2006.145.10:49:47.64/valo/02,534.99,yes,locked 2006.145.10:49:47.64/valo/03,564.99,yes,locked 2006.145.10:49:47.64/valo/04,624.99,yes,locked 2006.145.10:49:47.64/valo/05,734.99,yes,locked 2006.145.10:49:47.64/valo/06,814.99,yes,locked 2006.145.10:49:47.64/valo/07,864.99,yes,locked 2006.145.10:49:47.64/valo/08,884.99,yes,locked 2006.145.10:49:48.73/vb/01,03,usb,yes,36,33 2006.145.10:49:48.73/vb/02,04,usb,yes,31,31 2006.145.10:49:48.73/vb/03,04,usb,yes,28,31 2006.145.10:49:48.73/vb/04,04,usb,yes,32,31 2006.145.10:49:48.73/vb/05,04,usb,yes,25,28 2006.145.10:49:48.73/vb/06,04,usb,yes,30,26 2006.145.10:49:48.73/vb/07,04,usb,yes,29,29 2006.145.10:49:48.73/vb/08,04,usb,yes,27,30 2006.145.10:49:48.96/vblo/01,629.99,yes,locked 2006.145.10:49:48.96/vblo/02,634.99,yes,locked 2006.145.10:49:48.96/vblo/03,649.99,yes,locked 2006.145.10:49:48.96/vblo/04,679.99,yes,locked 2006.145.10:49:48.96/vblo/05,709.99,yes,locked 2006.145.10:49:48.96/vblo/06,719.99,yes,locked 2006.145.10:49:48.96/vblo/07,734.99,yes,locked 2006.145.10:49:48.96/vblo/08,744.99,yes,locked 2006.145.10:49:49.11/vabw/8 2006.145.10:49:49.26/vbbw/8 2006.145.10:49:49.35/xfe/off,on,15.0 2006.145.10:49:49.72/ifatt/23,28,28,28 2006.145.10:49:50.07/fmout-gps/S +5.7E-08 2006.145.10:49:50.15:!2006.145.10:50:56 2006.145.10:50:56.01:data_valid=off 2006.145.10:50:56.02:"et 2006.145.10:50:56.02:!+3s 2006.145.10:50:59.03:"tape 2006.145.10:50:59.04:postob 2006.145.10:50:59.25/cable/+6.5439E-03 2006.145.10:50:59.26/wx/17.07,1019.6,64 2006.145.10:50:59.31/fmout-gps/S +5.8E-08 2006.145.10:50:59.31:scan_name=145-1058,jd0605,40 2006.145.10:50:59.31:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.145.10:51:01.14#flagr#flagr/antenna,new-source 2006.145.10:51:01.14:checkk5 2006.145.10:51:01.61/chk_autoobs//k5ts1/ autoobs is running! 2006.145.10:51:02.05/chk_autoobs//k5ts2/ autoobs is running! 2006.145.10:51:02.49/chk_autoobs//k5ts3/ autoobs is running! 2006.145.10:51:02.91/chk_autoobs//k5ts4/ autoobs is running! 2006.145.10:51:03.34/chk_obsdata//k5ts1/T1451049??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.10:51:03.79/chk_obsdata//k5ts2/T1451049??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.10:51:04.25/chk_obsdata//k5ts3/T1451049??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.10:51:04.68/chk_obsdata//k5ts4/T1451049??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.10:51:05.45/k5log//k5ts1_log_newline 2006.145.10:51:06.21/k5log//k5ts2_log_newline 2006.145.10:51:06.94/k5log//k5ts3_log_newline 2006.145.10:51:07.69/k5log//k5ts4_log_newline 2006.145.10:51:07.72/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.10:51:07.72:setupk4=1 2006.145.10:51:07.72$setupk4/echo=on 2006.145.10:51:07.72$setupk4/pcalon 2006.145.10:51:07.72$pcalon/"no phase cal control is implemented here 2006.145.10:51:07.72$setupk4/"tpicd=stop 2006.145.10:51:07.72$setupk4/"rec=synch_on 2006.145.10:51:07.72$setupk4/"rec_mode=128 2006.145.10:51:07.72$setupk4/!* 2006.145.10:51:07.72$setupk4/recpk4 2006.145.10:51:07.72$recpk4/recpatch= 2006.145.10:51:07.73$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.10:51:07.73$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.10:51:07.73$setupk4/vck44 2006.145.10:51:07.73$vck44/valo=1,524.99 2006.145.10:51:07.73#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.10:51:07.73#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.10:51:07.73#ibcon#ireg 17 cls_cnt 0 2006.145.10:51:07.73#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.10:51:07.73#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.10:51:07.73#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.10:51:07.76#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.10:51:07.80#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.10:51:07.80#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.10:51:07.80#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.10:51:07.80#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.10:51:07.80$vck44/va=1,8 2006.145.10:51:07.80#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.10:51:07.80#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.10:51:07.80#ibcon#ireg 11 cls_cnt 2 2006.145.10:51:07.80#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.10:51:07.80#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.10:51:07.80#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.10:51:07.82#ibcon#[25=AT01-08\r\n] 2006.145.10:51:07.85#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.10:51:07.85#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.10:51:07.85#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.10:51:07.85#ibcon#ireg 7 cls_cnt 0 2006.145.10:51:07.85#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.10:51:07.98#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.10:51:07.98#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.10:51:07.99#ibcon#[25=USB\r\n] 2006.145.10:51:08.02#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.10:51:08.02#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.10:51:08.02#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.10:51:08.02#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.10:51:08.02$vck44/valo=2,534.99 2006.145.10:51:08.02#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.10:51:08.02#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.10:51:08.02#ibcon#ireg 17 cls_cnt 0 2006.145.10:51:08.02#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.10:51:08.02#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.10:51:08.02#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.10:51:08.05#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.10:51:08.09#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.10:51:08.09#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.10:51:08.09#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.10:51:08.09#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.10:51:08.09$vck44/va=2,7 2006.145.10:51:08.09#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.10:51:08.09#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.10:51:08.09#ibcon#ireg 11 cls_cnt 2 2006.145.10:51:08.09#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.10:51:08.14#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.10:51:08.14#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.10:51:08.16#ibcon#[25=AT02-07\r\n] 2006.145.10:51:08.19#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.10:51:08.19#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.10:51:08.19#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.10:51:08.19#ibcon#ireg 7 cls_cnt 0 2006.145.10:51:08.19#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.10:51:08.31#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.10:51:08.31#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.10:51:08.33#ibcon#[25=USB\r\n] 2006.145.10:51:08.36#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.10:51:08.36#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.10:51:08.36#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.10:51:08.36#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.10:51:08.36$vck44/valo=3,564.99 2006.145.10:51:08.36#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.10:51:08.36#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.10:51:08.36#ibcon#ireg 17 cls_cnt 0 2006.145.10:51:08.36#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.10:51:08.36#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.10:51:08.36#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.10:51:08.38#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.10:51:08.42#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.10:51:08.42#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.10:51:08.42#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.10:51:08.42#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.10:51:08.42$vck44/va=3,8 2006.145.10:51:08.42#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.10:51:08.42#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.10:51:08.42#ibcon#ireg 11 cls_cnt 2 2006.145.10:51:08.42#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.10:51:08.48#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.10:51:08.48#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.10:51:08.50#ibcon#[25=AT03-08\r\n] 2006.145.10:51:08.53#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.10:51:08.53#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.10:51:08.53#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.10:51:08.53#ibcon#ireg 7 cls_cnt 0 2006.145.10:51:08.53#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.10:51:08.65#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.10:51:08.65#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.10:51:08.67#ibcon#[25=USB\r\n] 2006.145.10:51:08.70#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.10:51:08.70#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.10:51:08.70#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.10:51:08.70#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.10:51:08.70$vck44/valo=4,624.99 2006.145.10:51:08.70#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.10:51:08.70#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.10:51:08.70#ibcon#ireg 17 cls_cnt 0 2006.145.10:51:08.70#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.10:51:08.70#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.10:51:08.70#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.10:51:08.72#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.10:51:08.76#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.10:51:08.76#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.10:51:08.76#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.10:51:08.76#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.10:51:08.76$vck44/va=4,7 2006.145.10:51:08.76#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.10:51:08.76#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.10:51:08.76#ibcon#ireg 11 cls_cnt 2 2006.145.10:51:08.76#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.10:51:08.82#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.10:51:08.82#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.10:51:08.84#ibcon#[25=AT04-07\r\n] 2006.145.10:51:08.87#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.10:51:08.87#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.10:51:08.87#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.10:51:08.87#ibcon#ireg 7 cls_cnt 0 2006.145.10:51:08.87#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.10:51:08.99#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.10:51:08.99#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.10:51:09.01#ibcon#[25=USB\r\n] 2006.145.10:51:09.04#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.10:51:09.04#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.10:51:09.04#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.10:51:09.04#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.10:51:09.04$vck44/valo=5,734.99 2006.145.10:51:09.04#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.10:51:09.04#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.10:51:09.04#ibcon#ireg 17 cls_cnt 0 2006.145.10:51:09.04#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.10:51:09.04#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.10:51:09.04#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.10:51:09.06#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.10:51:09.10#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.10:51:09.10#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.10:51:09.10#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.10:51:09.10#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.10:51:09.10$vck44/va=5,4 2006.145.10:51:09.10#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.10:51:09.10#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.10:51:09.10#ibcon#ireg 11 cls_cnt 2 2006.145.10:51:09.10#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.10:51:09.16#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.10:51:09.16#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.10:51:09.18#ibcon#[25=AT05-04\r\n] 2006.145.10:51:09.21#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.10:51:09.21#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.10:51:09.21#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.10:51:09.21#ibcon#ireg 7 cls_cnt 0 2006.145.10:51:09.21#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.10:51:09.33#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.10:51:09.33#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.10:51:09.35#ibcon#[25=USB\r\n] 2006.145.10:51:09.38#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.10:51:09.38#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.10:51:09.38#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.10:51:09.38#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.10:51:09.38$vck44/valo=6,814.99 2006.145.10:51:09.38#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.10:51:09.38#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.10:51:09.38#ibcon#ireg 17 cls_cnt 0 2006.145.10:51:09.38#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.10:51:09.38#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.10:51:09.38#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.10:51:09.40#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.10:51:09.44#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.10:51:09.44#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.10:51:09.44#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.10:51:09.44#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.10:51:09.44$vck44/va=6,4 2006.145.10:51:09.44#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.10:51:09.44#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.10:51:09.44#ibcon#ireg 11 cls_cnt 2 2006.145.10:51:09.44#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.10:51:09.50#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.10:51:09.50#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.10:51:09.52#ibcon#[25=AT06-04\r\n] 2006.145.10:51:09.55#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.10:51:09.55#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.10:51:09.55#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.10:51:09.55#ibcon#ireg 7 cls_cnt 0 2006.145.10:51:09.55#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.10:51:09.67#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.10:51:09.67#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.10:51:09.69#ibcon#[25=USB\r\n] 2006.145.10:51:09.72#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.10:51:09.72#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.10:51:09.72#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.10:51:09.72#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.10:51:09.72$vck44/valo=7,864.99 2006.145.10:51:09.72#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.10:51:09.72#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.10:51:09.72#ibcon#ireg 17 cls_cnt 0 2006.145.10:51:09.72#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.10:51:09.72#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.10:51:09.72#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.10:51:09.74#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.10:51:09.78#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.10:51:09.78#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.10:51:09.78#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.10:51:09.78#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.10:51:09.78$vck44/va=7,4 2006.145.10:51:09.78#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.10:51:09.78#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.10:51:09.78#ibcon#ireg 11 cls_cnt 2 2006.145.10:51:09.78#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.10:51:09.84#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.10:51:09.84#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.10:51:09.86#ibcon#[25=AT07-04\r\n] 2006.145.10:51:09.89#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.10:51:09.89#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.10:51:09.89#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.10:51:09.89#ibcon#ireg 7 cls_cnt 0 2006.145.10:51:09.89#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.10:51:10.01#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.10:51:10.01#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.10:51:10.03#ibcon#[25=USB\r\n] 2006.145.10:51:10.06#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.10:51:10.06#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.10:51:10.06#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.10:51:10.06#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.10:51:10.06$vck44/valo=8,884.99 2006.145.10:51:10.06#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.10:51:10.06#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.10:51:10.06#ibcon#ireg 17 cls_cnt 0 2006.145.10:51:10.06#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.10:51:10.06#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.10:51:10.06#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.10:51:10.08#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.10:51:10.12#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.10:51:10.12#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.10:51:10.12#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.10:51:10.12#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.10:51:10.12$vck44/va=8,4 2006.145.10:51:10.12#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.10:51:10.12#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.10:51:10.12#ibcon#ireg 11 cls_cnt 2 2006.145.10:51:10.12#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.10:51:10.18#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.10:51:10.18#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.10:51:10.20#ibcon#[25=AT08-04\r\n] 2006.145.10:51:10.23#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.10:51:10.23#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.10:51:10.23#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.10:51:10.23#ibcon#ireg 7 cls_cnt 0 2006.145.10:51:10.23#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.10:51:10.36#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.10:51:10.36#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.10:51:10.37#ibcon#[25=USB\r\n] 2006.145.10:51:10.40#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.10:51:10.40#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.10:51:10.40#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.10:51:10.40#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.10:51:10.40$vck44/vblo=1,629.99 2006.145.10:51:10.40#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.10:51:10.40#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.10:51:10.40#ibcon#ireg 17 cls_cnt 0 2006.145.10:51:10.40#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.10:51:10.40#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.10:51:10.40#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.10:51:10.43#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.10:51:10.47#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.10:51:10.47#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.10:51:10.47#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.10:51:10.47#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.10:51:10.47$vck44/vb=1,3 2006.145.10:51:10.47#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.10:51:10.47#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.10:51:10.47#ibcon#ireg 11 cls_cnt 2 2006.145.10:51:10.47#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.10:51:10.47#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.10:51:10.47#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.10:51:10.49#ibcon#[27=AT01-03\r\n] 2006.145.10:51:10.52#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.10:51:10.52#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.10:51:10.52#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.10:51:10.52#ibcon#ireg 7 cls_cnt 0 2006.145.10:51:10.52#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.10:51:10.64#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.10:51:10.64#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.10:51:10.66#ibcon#[27=USB\r\n] 2006.145.10:51:10.69#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.10:51:10.69#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.10:51:10.69#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.10:51:10.69#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.10:51:10.69$vck44/vblo=2,634.99 2006.145.10:51:10.69#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.10:51:10.69#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.10:51:10.69#ibcon#ireg 17 cls_cnt 0 2006.145.10:51:10.69#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.10:51:10.69#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.10:51:10.69#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.10:51:10.71#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.10:51:10.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.10:51:10.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.10:51:10.75#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.10:51:10.75#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.10:51:10.75$vck44/vb=2,4 2006.145.10:51:10.75#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.10:51:10.75#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.10:51:10.75#ibcon#ireg 11 cls_cnt 2 2006.145.10:51:10.75#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.10:51:10.81#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.10:51:10.81#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.10:51:10.83#ibcon#[27=AT02-04\r\n] 2006.145.10:51:10.86#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.10:51:10.86#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.10:51:10.86#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.10:51:10.86#ibcon#ireg 7 cls_cnt 0 2006.145.10:51:10.86#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.10:51:10.98#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.10:51:10.98#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.10:51:11.00#ibcon#[27=USB\r\n] 2006.145.10:51:11.03#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.10:51:11.03#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.10:51:11.03#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.10:51:11.03#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.10:51:11.03$vck44/vblo=3,649.99 2006.145.10:51:11.03#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.10:51:11.03#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.10:51:11.03#ibcon#ireg 17 cls_cnt 0 2006.145.10:51:11.03#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.10:51:11.03#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.10:51:11.03#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.10:51:11.05#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.10:51:11.09#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.10:51:11.09#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.10:51:11.09#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.10:51:11.09#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.10:51:11.09$vck44/vb=3,4 2006.145.10:51:11.09#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.10:51:11.09#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.10:51:11.09#ibcon#ireg 11 cls_cnt 2 2006.145.10:51:11.09#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.10:51:11.15#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.10:51:11.15#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.10:51:11.17#ibcon#[27=AT03-04\r\n] 2006.145.10:51:11.20#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.10:51:11.20#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.10:51:11.20#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.10:51:11.20#ibcon#ireg 7 cls_cnt 0 2006.145.10:51:11.20#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.10:51:11.32#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.10:51:11.32#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.10:51:11.34#ibcon#[27=USB\r\n] 2006.145.10:51:11.37#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.10:51:11.37#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.10:51:11.37#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.10:51:11.37#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.10:51:11.37$vck44/vblo=4,679.99 2006.145.10:51:11.37#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.10:51:11.37#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.10:51:11.37#ibcon#ireg 17 cls_cnt 0 2006.145.10:51:11.37#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.10:51:11.37#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.10:51:11.37#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.10:51:11.39#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.10:51:11.43#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.10:51:11.43#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.10:51:11.43#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.10:51:11.43#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.10:51:11.43$vck44/vb=4,4 2006.145.10:51:11.43#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.10:51:11.43#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.10:51:11.43#ibcon#ireg 11 cls_cnt 2 2006.145.10:51:11.43#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.10:51:11.49#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.10:51:11.49#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.10:51:11.51#ibcon#[27=AT04-04\r\n] 2006.145.10:51:11.54#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.10:51:11.54#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.10:51:11.54#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.10:51:11.54#ibcon#ireg 7 cls_cnt 0 2006.145.10:51:11.54#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.10:51:11.66#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.10:51:11.66#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.10:51:11.68#ibcon#[27=USB\r\n] 2006.145.10:51:11.71#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.10:51:11.71#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.10:51:11.71#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.10:51:11.71#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.10:51:11.71$vck44/vblo=5,709.99 2006.145.10:51:11.71#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.10:51:11.71#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.10:51:11.71#ibcon#ireg 17 cls_cnt 0 2006.145.10:51:11.71#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.10:51:11.71#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.10:51:11.71#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.10:51:11.73#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.10:51:11.77#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.10:51:11.77#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.10:51:11.77#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.10:51:11.77#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.10:51:11.77$vck44/vb=5,4 2006.145.10:51:11.77#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.10:51:11.77#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.10:51:11.77#ibcon#ireg 11 cls_cnt 2 2006.145.10:51:11.77#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.10:51:11.83#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.10:51:11.83#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.10:51:11.85#ibcon#[27=AT05-04\r\n] 2006.145.10:51:11.88#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.10:51:11.88#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.10:51:11.88#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.10:51:11.88#ibcon#ireg 7 cls_cnt 0 2006.145.10:51:11.88#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.10:51:12.00#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.10:51:12.00#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.10:51:12.02#ibcon#[27=USB\r\n] 2006.145.10:51:12.05#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.10:51:12.05#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.10:51:12.05#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.10:51:12.05#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.10:51:12.05$vck44/vblo=6,719.99 2006.145.10:51:12.05#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.10:51:12.05#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.10:51:12.05#ibcon#ireg 17 cls_cnt 0 2006.145.10:51:12.05#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.10:51:12.05#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.10:51:12.05#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.10:51:12.07#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.10:51:12.11#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.10:51:12.11#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.10:51:12.11#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.10:51:12.11#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.10:51:12.11$vck44/vb=6,4 2006.145.10:51:12.11#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.10:51:12.11#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.10:51:12.11#ibcon#ireg 11 cls_cnt 2 2006.145.10:51:12.11#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.10:51:12.17#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.10:51:12.17#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.10:51:12.19#ibcon#[27=AT06-04\r\n] 2006.145.10:51:12.22#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.10:51:12.22#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.10:51:12.22#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.10:51:12.22#ibcon#ireg 7 cls_cnt 0 2006.145.10:51:12.22#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.10:51:12.34#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.10:51:12.34#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.10:51:12.36#ibcon#[27=USB\r\n] 2006.145.10:51:12.39#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.10:51:12.39#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.10:51:12.39#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.10:51:12.39#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.10:51:12.39$vck44/vblo=7,734.99 2006.145.10:51:12.39#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.10:51:12.39#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.10:51:12.39#ibcon#ireg 17 cls_cnt 0 2006.145.10:51:12.39#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.10:51:12.39#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.10:51:12.39#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.10:51:12.41#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.10:51:12.45#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.10:51:12.45#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.10:51:12.45#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.10:51:12.45#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.10:51:12.45$vck44/vb=7,4 2006.145.10:51:12.45#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.10:51:12.45#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.10:51:12.45#ibcon#ireg 11 cls_cnt 2 2006.145.10:51:12.45#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.10:51:12.51#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.10:51:12.51#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.10:51:12.53#ibcon#[27=AT07-04\r\n] 2006.145.10:51:12.56#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.10:51:12.56#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.10:51:12.56#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.10:51:12.56#ibcon#ireg 7 cls_cnt 0 2006.145.10:51:12.56#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.10:51:12.68#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.10:51:12.68#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.10:51:12.70#ibcon#[27=USB\r\n] 2006.145.10:51:12.73#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.10:51:12.73#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.10:51:12.73#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.10:51:12.73#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.10:51:12.73$vck44/vblo=8,744.99 2006.145.10:51:12.73#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.10:51:12.73#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.10:51:12.73#ibcon#ireg 17 cls_cnt 0 2006.145.10:51:12.73#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.10:51:12.73#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.10:51:12.73#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.10:51:12.75#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.10:51:12.79#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.10:51:12.79#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.10:51:12.79#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.10:51:12.79#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.10:51:12.79$vck44/vb=8,4 2006.145.10:51:12.79#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.10:51:12.79#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.10:51:12.79#ibcon#ireg 11 cls_cnt 2 2006.145.10:51:12.79#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.10:51:12.85#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.10:51:12.85#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.10:51:12.87#ibcon#[27=AT08-04\r\n] 2006.145.10:51:12.90#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.10:51:12.90#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.10:51:12.90#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.10:51:12.90#ibcon#ireg 7 cls_cnt 0 2006.145.10:51:12.90#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.10:51:13.02#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.10:51:13.02#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.10:51:13.04#ibcon#[27=USB\r\n] 2006.145.10:51:13.07#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.10:51:13.07#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.10:51:13.07#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.10:51:13.07#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.10:51:13.07$vck44/vabw=wide 2006.145.10:51:13.07#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.10:51:13.07#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.10:51:13.07#ibcon#ireg 8 cls_cnt 0 2006.145.10:51:13.07#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.10:51:13.07#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.10:51:13.07#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.10:51:13.09#ibcon#[25=BW32\r\n] 2006.145.10:51:13.12#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.10:51:13.12#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.10:51:13.12#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.10:51:13.12#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.10:51:13.12$vck44/vbbw=wide 2006.145.10:51:13.12#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.10:51:13.12#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.10:51:13.12#ibcon#ireg 8 cls_cnt 0 2006.145.10:51:13.12#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:51:13.19#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:51:13.19#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:51:13.21#ibcon#[27=BW32\r\n] 2006.145.10:51:13.24#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:51:13.24#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.10:51:13.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.10:51:13.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.10:51:13.24$setupk4/ifdk4 2006.145.10:51:13.24$ifdk4/lo= 2006.145.10:51:13.24$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.10:51:13.24$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.10:51:13.24$ifdk4/patch= 2006.145.10:51:13.24$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.10:51:13.24$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.10:51:13.24$setupk4/!*+20s 2006.145.10:51:16.60#abcon#<5=/05 3.4 5.9 17.07 641019.6\r\n> 2006.145.10:51:16.62#abcon#{5=INTERFACE CLEAR} 2006.145.10:51:16.68#abcon#[5=S1D000X0/0*\r\n] 2006.145.10:51:26.14#trakl#Source acquired 2006.145.10:51:26.14#flagr#flagr/antenna,acquired 2006.145.10:51:26.77#abcon#<5=/05 3.5 5.9 17.07 641019.7\r\n> 2006.145.10:51:26.79#abcon#{5=INTERFACE CLEAR} 2006.145.10:51:26.85#abcon#[5=S1D000X0/0*\r\n] 2006.145.10:51:27.73$setupk4/"tpicd 2006.145.10:51:27.73$setupk4/echo=off 2006.145.10:51:27.73$setupk4/xlog=off 2006.145.10:51:27.73:!2006.145.10:57:52 2006.145.10:57:52.00:preob 2006.145.10:57:52.14/onsource/TRACKING 2006.145.10:57:52.14:!2006.145.10:58:02 2006.145.10:58:02.00:"tape 2006.145.10:58:02.00:"st=record 2006.145.10:58:02.00:data_valid=on 2006.145.10:58:02.00:midob 2006.145.10:58:02.14/onsource/TRACKING 2006.145.10:58:02.14/wx/17.00,1019.7,66 2006.145.10:58:02.21/cable/+6.5458E-03 2006.145.10:58:03.30/va/01,08,usb,yes,35,38 2006.145.10:58:03.30/va/02,07,usb,yes,38,39 2006.145.10:58:03.30/va/03,08,usb,yes,35,36 2006.145.10:58:03.30/va/04,07,usb,yes,39,41 2006.145.10:58:03.30/va/05,04,usb,yes,34,35 2006.145.10:58:03.30/va/06,04,usb,yes,38,38 2006.145.10:58:03.30/va/07,04,usb,yes,39,40 2006.145.10:58:03.30/va/08,04,usb,yes,33,40 2006.145.10:58:03.53/valo/01,524.99,yes,locked 2006.145.10:58:03.53/valo/02,534.99,yes,locked 2006.145.10:58:03.53/valo/03,564.99,yes,locked 2006.145.10:58:03.53/valo/04,624.99,yes,locked 2006.145.10:58:03.53/valo/05,734.99,yes,locked 2006.145.10:58:03.53/valo/06,814.99,yes,locked 2006.145.10:58:03.53/valo/07,864.99,yes,locked 2006.145.10:58:03.53/valo/08,884.99,yes,locked 2006.145.10:58:04.62/vb/01,03,usb,yes,41,39 2006.145.10:58:04.62/vb/02,04,usb,yes,36,36 2006.145.10:58:04.62/vb/03,04,usb,yes,32,36 2006.145.10:58:04.62/vb/04,04,usb,yes,37,36 2006.145.10:58:04.62/vb/05,04,usb,yes,29,32 2006.145.10:58:04.62/vb/06,04,usb,yes,34,30 2006.145.10:58:04.62/vb/07,04,usb,yes,34,34 2006.145.10:58:04.62/vb/08,04,usb,yes,31,35 2006.145.10:58:04.85/vblo/01,629.99,yes,locked 2006.145.10:58:04.85/vblo/02,634.99,yes,locked 2006.145.10:58:04.85/vblo/03,649.99,yes,locked 2006.145.10:58:04.85/vblo/04,679.99,yes,locked 2006.145.10:58:04.85/vblo/05,709.99,yes,locked 2006.145.10:58:04.85/vblo/06,719.99,yes,locked 2006.145.10:58:04.85/vblo/07,734.99,yes,locked 2006.145.10:58:04.85/vblo/08,744.99,yes,locked 2006.145.10:58:05.00/vabw/8 2006.145.10:58:05.15/vbbw/8 2006.145.10:58:05.24/xfe/off,on,16.0 2006.145.10:58:05.63/ifatt/23,28,28,28 2006.145.10:58:06.07/fmout-gps/S +5.8E-08 2006.145.10:58:06.11:!2006.145.10:58:42 2006.145.10:58:42.01:data_valid=off 2006.145.10:58:42.02:"et 2006.145.10:58:42.02:!+3s 2006.145.10:58:45.03:"tape 2006.145.10:58:45.03:postob 2006.145.10:58:45.12/cable/+6.5458E-03 2006.145.10:58:45.12/wx/16.99,1019.7,66 2006.145.10:58:45.21/fmout-gps/S +5.7E-08 2006.145.10:58:45.21:scan_name=145-1059,jd0605,70 2006.145.10:58:45.21:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.145.10:58:47.14#flagr#flagr/antenna,new-source 2006.145.10:58:47.15:checkk5 2006.145.10:58:47.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.10:58:48.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.10:58:48.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.10:58:48.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.10:58:49.32/chk_obsdata//k5ts1/T1451058??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.10:58:49.75/chk_obsdata//k5ts2/T1451058??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.10:58:50.18/chk_obsdata//k5ts3/T1451058??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.10:58:50.62/chk_obsdata//k5ts4/T1451058??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.10:58:51.39/k5log//k5ts1_log_newline 2006.145.10:58:52.13/k5log//k5ts2_log_newline 2006.145.10:58:52.88/k5log//k5ts3_log_newline 2006.145.10:58:53.63/k5log//k5ts4_log_newline 2006.145.10:58:53.65/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.10:58:53.65:setupk4=1 2006.145.10:58:53.65$setupk4/echo=on 2006.145.10:58:53.65$setupk4/pcalon 2006.145.10:58:53.65$pcalon/"no phase cal control is implemented here 2006.145.10:58:53.65$setupk4/"tpicd=stop 2006.145.10:58:53.65$setupk4/"rec=synch_on 2006.145.10:58:53.65$setupk4/"rec_mode=128 2006.145.10:58:53.65$setupk4/!* 2006.145.10:58:53.65$setupk4/recpk4 2006.145.10:58:53.65$recpk4/recpatch= 2006.145.10:58:53.65$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.10:58:53.65$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.10:58:53.65$setupk4/vck44 2006.145.10:58:53.65$vck44/valo=1,524.99 2006.145.10:58:53.65#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.10:58:53.65#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.10:58:53.65#ibcon#ireg 17 cls_cnt 0 2006.145.10:58:53.65#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.10:58:53.65#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.10:58:53.65#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.10:58:53.69#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.10:58:53.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.10:58:53.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.10:58:53.74#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.10:58:53.74#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.10:58:53.74$vck44/va=1,8 2006.145.10:58:53.74#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.10:58:53.74#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.10:58:53.74#ibcon#ireg 11 cls_cnt 2 2006.145.10:58:53.74#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.10:58:53.74#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.10:58:53.74#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.10:58:53.76#ibcon#[25=AT01-08\r\n] 2006.145.10:58:53.79#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.10:58:53.79#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.10:58:53.79#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.10:58:53.79#ibcon#ireg 7 cls_cnt 0 2006.145.10:58:53.79#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.10:58:53.92#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.10:58:53.92#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.10:58:53.93#ibcon#[25=USB\r\n] 2006.145.10:58:53.96#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.10:58:53.96#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.10:58:53.96#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.10:58:53.96#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.10:58:53.96$vck44/valo=2,534.99 2006.145.10:58:53.96#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.10:58:53.96#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.10:58:53.96#ibcon#ireg 17 cls_cnt 0 2006.145.10:58:53.96#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.10:58:53.96#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.10:58:53.96#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.10:58:53.99#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.10:58:54.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.10:58:54.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.10:58:54.03#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.10:58:54.03#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.10:58:54.03$vck44/va=2,7 2006.145.10:58:54.03#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.10:58:54.03#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.10:58:54.03#ibcon#ireg 11 cls_cnt 2 2006.145.10:58:54.03#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.10:58:54.08#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.10:58:54.08#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.10:58:54.10#ibcon#[25=AT02-07\r\n] 2006.145.10:58:54.13#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.10:58:54.13#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.10:58:54.13#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.10:58:54.13#ibcon#ireg 7 cls_cnt 0 2006.145.10:58:54.13#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.10:58:54.25#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.10:58:54.25#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.10:58:54.27#ibcon#[25=USB\r\n] 2006.145.10:58:54.30#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.10:58:54.30#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.10:58:54.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.10:58:54.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.10:58:54.30$vck44/valo=3,564.99 2006.145.10:58:54.30#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.10:58:54.30#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.10:58:54.30#ibcon#ireg 17 cls_cnt 0 2006.145.10:58:54.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.10:58:54.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.10:58:54.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.10:58:54.32#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.10:58:54.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.10:58:54.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.10:58:54.36#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.10:58:54.36#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.10:58:54.36$vck44/va=3,8 2006.145.10:58:54.36#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.10:58:54.36#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.10:58:54.36#ibcon#ireg 11 cls_cnt 2 2006.145.10:58:54.36#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.10:58:54.40#abcon#<5=/05 2.4 4.8 16.99 651019.7\r\n> 2006.145.10:58:54.42#abcon#{5=INTERFACE CLEAR} 2006.145.10:58:54.42#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.10:58:54.42#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.10:58:54.44#ibcon#[25=AT03-08\r\n] 2006.145.10:58:54.47#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.10:58:54.47#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.10:58:54.47#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.10:58:54.47#ibcon#ireg 7 cls_cnt 0 2006.145.10:58:54.47#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.10:58:54.48#abcon#[5=S1D000X0/0*\r\n] 2006.145.10:58:54.59#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.10:58:54.59#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.10:58:54.61#ibcon#[25=USB\r\n] 2006.145.10:58:54.64#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.10:58:54.64#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.10:58:54.64#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.10:58:54.64#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.10:58:54.64$vck44/valo=4,624.99 2006.145.10:58:54.64#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.10:58:54.64#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.10:58:54.64#ibcon#ireg 17 cls_cnt 0 2006.145.10:58:54.64#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.10:58:54.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.10:58:54.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.10:58:54.66#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.10:58:54.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.10:58:54.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.10:58:54.70#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.10:58:54.70#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.10:58:54.70$vck44/va=4,7 2006.145.10:58:54.70#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.10:58:54.70#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.10:58:54.70#ibcon#ireg 11 cls_cnt 2 2006.145.10:58:54.70#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.10:58:54.76#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.10:58:54.76#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.10:58:54.78#ibcon#[25=AT04-07\r\n] 2006.145.10:58:54.81#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.10:58:54.81#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.10:58:54.81#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.10:58:54.81#ibcon#ireg 7 cls_cnt 0 2006.145.10:58:54.81#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.10:58:54.93#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.10:58:54.93#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.10:58:54.95#ibcon#[25=USB\r\n] 2006.145.10:58:54.98#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.10:58:54.98#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.10:58:54.98#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.10:58:54.98#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.10:58:54.98$vck44/valo=5,734.99 2006.145.10:58:54.98#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.10:58:54.98#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.10:58:54.98#ibcon#ireg 17 cls_cnt 0 2006.145.10:58:54.98#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.10:58:54.98#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.10:58:54.98#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.10:58:55.00#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.10:58:55.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.10:58:55.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.10:58:55.04#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.10:58:55.04#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.10:58:55.04$vck44/va=5,4 2006.145.10:58:55.04#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.10:58:55.04#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.10:58:55.04#ibcon#ireg 11 cls_cnt 2 2006.145.10:58:55.04#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.10:58:55.10#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.10:58:55.10#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.10:58:55.12#ibcon#[25=AT05-04\r\n] 2006.145.10:58:55.15#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.10:58:55.15#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.10:58:55.15#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.10:58:55.15#ibcon#ireg 7 cls_cnt 0 2006.145.10:58:55.15#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.10:58:55.27#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.10:58:55.27#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.10:58:55.29#ibcon#[25=USB\r\n] 2006.145.10:58:55.32#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.10:58:55.32#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.10:58:55.32#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.10:58:55.32#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.10:58:55.32$vck44/valo=6,814.99 2006.145.10:58:55.32#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.10:58:55.32#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.10:58:55.32#ibcon#ireg 17 cls_cnt 0 2006.145.10:58:55.32#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.10:58:55.32#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.10:58:55.32#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.10:58:55.34#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.10:58:55.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.10:58:55.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.10:58:55.38#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.10:58:55.38#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.10:58:55.38$vck44/va=6,4 2006.145.10:58:55.38#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.10:58:55.38#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.10:58:55.38#ibcon#ireg 11 cls_cnt 2 2006.145.10:58:55.38#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.10:58:55.44#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.10:58:55.44#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.10:58:55.46#ibcon#[25=AT06-04\r\n] 2006.145.10:58:55.49#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.10:58:55.49#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.10:58:55.49#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.10:58:55.49#ibcon#ireg 7 cls_cnt 0 2006.145.10:58:55.49#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.10:58:55.61#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.10:58:55.61#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.10:58:55.63#ibcon#[25=USB\r\n] 2006.145.10:58:55.66#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.10:58:55.66#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.10:58:55.66#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.10:58:55.66#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.10:58:55.66$vck44/valo=7,864.99 2006.145.10:58:55.66#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.10:58:55.66#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.10:58:55.66#ibcon#ireg 17 cls_cnt 0 2006.145.10:58:55.66#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.10:58:55.66#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.10:58:55.66#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.10:58:55.68#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.10:58:55.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.10:58:55.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.10:58:55.72#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.10:58:55.72#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.10:58:55.72$vck44/va=7,4 2006.145.10:58:55.72#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.10:58:55.72#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.10:58:55.72#ibcon#ireg 11 cls_cnt 2 2006.145.10:58:55.72#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.10:58:55.78#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.10:58:55.78#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.10:58:55.80#ibcon#[25=AT07-04\r\n] 2006.145.10:58:55.83#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.10:58:55.83#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.10:58:55.83#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.10:58:55.83#ibcon#ireg 7 cls_cnt 0 2006.145.10:58:55.83#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.10:58:55.95#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.10:58:55.95#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.10:58:55.97#ibcon#[25=USB\r\n] 2006.145.10:58:56.00#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.10:58:56.00#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.10:58:56.00#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.10:58:56.00#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.10:58:56.00$vck44/valo=8,884.99 2006.145.10:58:56.00#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.10:58:56.00#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.10:58:56.00#ibcon#ireg 17 cls_cnt 0 2006.145.10:58:56.00#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.10:58:56.00#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.10:58:56.00#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.10:58:56.02#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.10:58:56.06#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.10:58:56.06#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.10:58:56.06#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.10:58:56.06#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.10:58:56.06$vck44/va=8,4 2006.145.10:58:56.06#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.10:58:56.06#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.10:58:56.06#ibcon#ireg 11 cls_cnt 2 2006.145.10:58:56.06#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.10:58:56.12#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.10:58:56.12#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.10:58:56.14#ibcon#[25=AT08-04\r\n] 2006.145.10:58:56.17#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.10:58:56.17#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.10:58:56.17#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.10:58:56.17#ibcon#ireg 7 cls_cnt 0 2006.145.10:58:56.17#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.10:58:56.29#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.10:58:56.29#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.10:58:56.31#ibcon#[25=USB\r\n] 2006.145.10:58:56.34#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.10:58:56.34#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.10:58:56.34#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.10:58:56.34#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.10:58:56.34$vck44/vblo=1,629.99 2006.145.10:58:56.34#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.10:58:56.34#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.10:58:56.34#ibcon#ireg 17 cls_cnt 0 2006.145.10:58:56.34#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.10:58:56.34#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.10:58:56.34#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.10:58:56.36#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.10:58:56.40#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.10:58:56.40#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.10:58:56.40#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.10:58:56.40#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.10:58:56.40$vck44/vb=1,3 2006.145.10:58:56.40#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.10:58:56.40#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.10:58:56.40#ibcon#ireg 11 cls_cnt 2 2006.145.10:58:56.40#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.10:58:56.40#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.10:58:56.40#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.10:58:56.42#ibcon#[27=AT01-03\r\n] 2006.145.10:58:56.45#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.10:58:56.45#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.10:58:56.45#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.10:58:56.45#ibcon#ireg 7 cls_cnt 0 2006.145.10:58:56.45#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.10:58:56.57#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.10:58:56.57#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.10:58:56.59#ibcon#[27=USB\r\n] 2006.145.10:58:56.62#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.10:58:56.62#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.10:58:56.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.10:58:56.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.10:58:56.62$vck44/vblo=2,634.99 2006.145.10:58:56.62#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.10:58:56.62#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.10:58:56.62#ibcon#ireg 17 cls_cnt 0 2006.145.10:58:56.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.10:58:56.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.10:58:56.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.10:58:56.64#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.10:58:56.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.10:58:56.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.10:58:56.68#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.10:58:56.68#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.10:58:56.68$vck44/vb=2,4 2006.145.10:58:56.68#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.10:58:56.68#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.10:58:56.68#ibcon#ireg 11 cls_cnt 2 2006.145.10:58:56.68#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.10:58:56.74#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.10:58:56.74#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.10:58:56.76#ibcon#[27=AT02-04\r\n] 2006.145.10:58:56.79#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.10:58:56.79#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.10:58:56.79#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.10:58:56.79#ibcon#ireg 7 cls_cnt 0 2006.145.10:58:56.79#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.10:58:56.91#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.10:58:56.91#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.10:58:56.93#ibcon#[27=USB\r\n] 2006.145.10:58:56.96#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.10:58:56.96#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.10:58:56.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.10:58:56.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.10:58:56.96$vck44/vblo=3,649.99 2006.145.10:58:56.96#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.10:58:56.96#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.10:58:56.96#ibcon#ireg 17 cls_cnt 0 2006.145.10:58:56.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.10:58:56.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.10:58:56.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.10:58:56.98#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.10:58:57.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.10:58:57.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.10:58:57.02#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.10:58:57.02#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.10:58:57.02$vck44/vb=3,4 2006.145.10:58:57.02#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.10:58:57.02#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.10:58:57.02#ibcon#ireg 11 cls_cnt 2 2006.145.10:58:57.02#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.10:58:57.08#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.10:58:57.08#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.10:58:57.10#ibcon#[27=AT03-04\r\n] 2006.145.10:58:57.13#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.10:58:57.13#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.10:58:57.13#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.10:58:57.13#ibcon#ireg 7 cls_cnt 0 2006.145.10:58:57.13#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.10:58:57.25#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.10:58:57.25#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.10:58:57.27#ibcon#[27=USB\r\n] 2006.145.10:58:57.30#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.10:58:57.30#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.10:58:57.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.10:58:57.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.10:58:57.30$vck44/vblo=4,679.99 2006.145.10:58:57.30#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.10:58:57.30#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.10:58:57.30#ibcon#ireg 17 cls_cnt 0 2006.145.10:58:57.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.10:58:57.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.10:58:57.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.10:58:57.32#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.10:58:57.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.10:58:57.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.10:58:57.36#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.10:58:57.36#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.10:58:57.36$vck44/vb=4,4 2006.145.10:58:57.36#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.10:58:57.36#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.10:58:57.36#ibcon#ireg 11 cls_cnt 2 2006.145.10:58:57.36#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.10:58:57.42#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.10:58:57.42#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.10:58:57.44#ibcon#[27=AT04-04\r\n] 2006.145.10:58:57.47#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.10:58:57.47#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.10:58:57.47#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.10:58:57.47#ibcon#ireg 7 cls_cnt 0 2006.145.10:58:57.47#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.10:58:57.59#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.10:58:57.59#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.10:58:57.61#ibcon#[27=USB\r\n] 2006.145.10:58:57.64#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.10:58:57.64#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.10:58:57.64#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.10:58:57.64#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.10:58:57.64$vck44/vblo=5,709.99 2006.145.10:58:57.64#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.10:58:57.64#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.10:58:57.64#ibcon#ireg 17 cls_cnt 0 2006.145.10:58:57.64#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.10:58:57.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.10:58:57.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.10:58:57.66#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.10:58:57.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.10:58:57.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.10:58:57.70#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.10:58:57.70#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.10:58:57.70$vck44/vb=5,4 2006.145.10:58:57.70#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.10:58:57.70#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.10:58:57.70#ibcon#ireg 11 cls_cnt 2 2006.145.10:58:57.70#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.10:58:57.76#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.10:58:57.76#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.10:58:57.78#ibcon#[27=AT05-04\r\n] 2006.145.10:58:57.81#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.10:58:57.81#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.10:58:57.81#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.10:58:57.81#ibcon#ireg 7 cls_cnt 0 2006.145.10:58:57.81#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.10:58:57.93#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.10:58:57.93#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.10:58:57.95#ibcon#[27=USB\r\n] 2006.145.10:58:57.98#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.10:58:57.98#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.10:58:57.98#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.10:58:57.98#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.10:58:57.98$vck44/vblo=6,719.99 2006.145.10:58:57.98#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.10:58:57.98#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.10:58:57.98#ibcon#ireg 17 cls_cnt 0 2006.145.10:58:57.98#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.10:58:57.98#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.10:58:57.98#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.10:58:58.00#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.10:58:58.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.10:58:58.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.10:58:58.04#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.10:58:58.04#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.10:58:58.04$vck44/vb=6,4 2006.145.10:58:58.04#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.10:58:58.04#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.10:58:58.04#ibcon#ireg 11 cls_cnt 2 2006.145.10:58:58.04#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.10:58:58.10#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.10:58:58.10#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.10:58:58.12#ibcon#[27=AT06-04\r\n] 2006.145.10:58:58.15#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.10:58:58.15#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.10:58:58.15#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.10:58:58.15#ibcon#ireg 7 cls_cnt 0 2006.145.10:58:58.15#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.10:58:58.27#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.10:58:58.27#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.10:58:58.29#ibcon#[27=USB\r\n] 2006.145.10:58:58.32#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.10:58:58.32#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.10:58:58.32#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.10:58:58.32#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.10:58:58.32$vck44/vblo=7,734.99 2006.145.10:58:58.32#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.10:58:58.32#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.10:58:58.32#ibcon#ireg 17 cls_cnt 0 2006.145.10:58:58.32#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.10:58:58.32#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.10:58:58.32#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.10:58:58.34#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.10:58:58.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.10:58:58.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.10:58:58.38#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.10:58:58.38#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.10:58:58.38$vck44/vb=7,4 2006.145.10:58:58.38#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.10:58:58.38#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.10:58:58.38#ibcon#ireg 11 cls_cnt 2 2006.145.10:58:58.38#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.10:58:58.44#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.10:58:58.44#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.10:58:58.46#ibcon#[27=AT07-04\r\n] 2006.145.10:58:58.49#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.10:58:58.49#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.10:58:58.49#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.10:58:58.49#ibcon#ireg 7 cls_cnt 0 2006.145.10:58:58.49#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.10:58:58.61#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.10:58:58.61#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.10:58:58.63#ibcon#[27=USB\r\n] 2006.145.10:58:58.66#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.10:58:58.66#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.10:58:58.66#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.10:58:58.66#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.10:58:58.66$vck44/vblo=8,744.99 2006.145.10:58:58.66#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.10:58:58.66#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.10:58:58.66#ibcon#ireg 17 cls_cnt 0 2006.145.10:58:58.66#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.10:58:58.66#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.10:58:58.66#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.10:58:58.68#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.10:58:58.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.10:58:58.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.10:58:58.72#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.10:58:58.72#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.10:58:58.72$vck44/vb=8,4 2006.145.10:58:58.72#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.10:58:58.72#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.10:58:58.72#ibcon#ireg 11 cls_cnt 2 2006.145.10:58:58.72#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.10:58:58.78#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.10:58:58.78#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.10:58:58.80#ibcon#[27=AT08-04\r\n] 2006.145.10:58:58.83#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.10:58:58.83#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.10:58:58.83#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.10:58:58.83#ibcon#ireg 7 cls_cnt 0 2006.145.10:58:58.83#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.10:58:58.95#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.10:58:58.95#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.10:58:58.97#ibcon#[27=USB\r\n] 2006.145.10:58:59.00#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.10:58:59.00#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.10:58:59.00#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.10:58:59.00#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.10:58:59.00$vck44/vabw=wide 2006.145.10:58:59.00#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.10:58:59.00#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.10:58:59.00#ibcon#ireg 8 cls_cnt 0 2006.145.10:58:59.00#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.10:58:59.00#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.10:58:59.00#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.10:58:59.02#ibcon#[25=BW32\r\n] 2006.145.10:58:59.05#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.10:58:59.05#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.10:58:59.05#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.10:58:59.05#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.10:58:59.05$vck44/vbbw=wide 2006.145.10:58:59.05#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.10:58:59.05#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.10:58:59.05#ibcon#ireg 8 cls_cnt 0 2006.145.10:58:59.05#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.10:58:59.12#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.10:58:59.12#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.10:58:59.14#ibcon#[27=BW32\r\n] 2006.145.10:58:59.17#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.10:58:59.17#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.10:58:59.17#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.10:58:59.17#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.10:58:59.17$setupk4/ifdk4 2006.145.10:58:59.17$ifdk4/lo= 2006.145.10:58:59.17$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.10:58:59.17$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.10:58:59.17$ifdk4/patch= 2006.145.10:58:59.17$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.10:58:59.17$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.10:58:59.17$setupk4/!*+20s 2006.145.10:59:04.57#abcon#<5=/05 2.4 4.8 16.99 651019.7\r\n> 2006.145.10:59:04.59#abcon#{5=INTERFACE CLEAR} 2006.145.10:59:04.65#abcon#[5=S1D000X0/0*\r\n] 2006.145.10:59:13.66$setupk4/"tpicd 2006.145.10:59:13.66$setupk4/echo=off 2006.145.10:59:13.66$setupk4/xlog=off 2006.145.10:59:13.66:!2006.145.10:59:47 2006.145.10:59:44.14#trakl#Source acquired 2006.145.10:59:45.14#flagr#flagr/antenna,acquired 2006.145.10:59:47.00:preob 2006.145.10:59:47.14/onsource/TRACKING 2006.145.10:59:47.14:!2006.145.10:59:57 2006.145.10:59:57.00:"tape 2006.145.10:59:57.00:"st=record 2006.145.10:59:57.00:data_valid=on 2006.145.10:59:57.00:midob 2006.145.10:59:57.14/onsource/TRACKING 2006.145.10:59:57.14/wx/16.97,1019.7,66 2006.145.10:59:57.25/cable/+6.5448E-03 2006.145.10:59:58.34/va/01,08,usb,yes,35,37 2006.145.10:59:58.34/va/02,07,usb,yes,37,38 2006.145.10:59:58.34/va/03,08,usb,yes,33,35 2006.145.10:59:58.34/va/04,07,usb,yes,38,40 2006.145.10:59:58.34/va/05,04,usb,yes,33,34 2006.145.10:59:58.34/va/06,04,usb,yes,37,37 2006.145.10:59:58.34/va/07,04,usb,yes,38,39 2006.145.10:59:58.34/va/08,04,usb,yes,32,38 2006.145.10:59:58.57/valo/01,524.99,yes,locked 2006.145.10:59:58.57/valo/02,534.99,yes,locked 2006.145.10:59:58.57/valo/03,564.99,yes,locked 2006.145.10:59:58.57/valo/04,624.99,yes,locked 2006.145.10:59:58.57/valo/05,734.99,yes,locked 2006.145.10:59:58.57/valo/06,814.99,yes,locked 2006.145.10:59:58.57/valo/07,864.99,yes,locked 2006.145.10:59:58.57/valo/08,884.99,yes,locked 2006.145.10:59:59.66/vb/01,03,usb,yes,39,37 2006.145.10:59:59.66/vb/02,04,usb,yes,35,34 2006.145.10:59:59.66/vb/03,04,usb,yes,31,34 2006.145.10:59:59.66/vb/04,04,usb,yes,36,35 2006.145.10:59:59.66/vb/05,04,usb,yes,28,31 2006.145.10:59:59.66/vb/06,04,usb,yes,33,29 2006.145.10:59:59.66/vb/07,04,usb,yes,33,32 2006.145.10:59:59.66/vb/08,04,usb,yes,30,34 2006.145.10:59:59.89/vblo/01,629.99,yes,locked 2006.145.10:59:59.89/vblo/02,634.99,yes,locked 2006.145.10:59:59.89/vblo/03,649.99,yes,locked 2006.145.10:59:59.89/vblo/04,679.99,yes,locked 2006.145.10:59:59.89/vblo/05,709.99,yes,locked 2006.145.10:59:59.89/vblo/06,719.99,yes,locked 2006.145.10:59:59.89/vblo/07,734.99,yes,locked 2006.145.10:59:59.89/vblo/08,744.99,yes,locked 2006.145.11:00:00.04/vabw/8 2006.145.11:00:00.19/vbbw/8 2006.145.11:00:00.28/xfe/off,on,15.2 2006.145.11:00:00.65/ifatt/23,28,28,28 2006.145.11:00:01.07/fmout-gps/S +5.7E-08 2006.145.11:00:01.11:!2006.145.11:01:07 2006.145.11:01:07.01:data_valid=off 2006.145.11:01:07.01:"et 2006.145.11:01:07.02:!+3s 2006.145.11:01:10.03:"tape 2006.145.11:01:10.03:postob 2006.145.11:01:10.16/cable/+6.5440E-03 2006.145.11:01:10.16/wx/16.96,1019.8,66 2006.145.11:01:10.23/fmout-gps/S +5.6E-08 2006.145.11:01:10.23:scan_name=145-1105,jd0605,400 2006.145.11:01:10.23:source=1418+546,141946.60,542314.8,2000.0,cw 2006.145.11:01:12.14#flagr#flagr/antenna,new-source 2006.145.11:01:12.14:checkk5 2006.145.11:01:12.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.11:01:13.00/chk_autoobs//k5ts2/ autoobs is running! 2006.145.11:01:13.43/chk_autoobs//k5ts3/ autoobs is running! 2006.145.11:01:13.86/chk_autoobs//k5ts4/ autoobs is running! 2006.145.11:01:14.29/chk_obsdata//k5ts1/T1451059??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.11:01:14.72/chk_obsdata//k5ts2/T1451059??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.11:01:15.16/chk_obsdata//k5ts3/T1451059??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.11:01:15.60/chk_obsdata//k5ts4/T1451059??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.11:01:16.35/k5log//k5ts1_log_newline 2006.145.11:01:17.09/k5log//k5ts2_log_newline 2006.145.11:01:17.85/k5log//k5ts3_log_newline 2006.145.11:01:18.59/k5log//k5ts4_log_newline 2006.145.11:01:18.62/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.11:01:18.62:setupk4=1 2006.145.11:01:18.62$setupk4/echo=on 2006.145.11:01:18.62$setupk4/pcalon 2006.145.11:01:18.62$pcalon/"no phase cal control is implemented here 2006.145.11:01:18.62$setupk4/"tpicd=stop 2006.145.11:01:18.62$setupk4/"rec=synch_on 2006.145.11:01:18.62$setupk4/"rec_mode=128 2006.145.11:01:18.62$setupk4/!* 2006.145.11:01:18.62$setupk4/recpk4 2006.145.11:01:18.62$recpk4/recpatch= 2006.145.11:01:18.62$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.11:01:18.62$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.11:01:18.62$setupk4/vck44 2006.145.11:01:18.62$vck44/valo=1,524.99 2006.145.11:01:18.62#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.11:01:18.62#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.11:01:18.62#ibcon#ireg 17 cls_cnt 0 2006.145.11:01:18.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:01:18.62#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:01:18.62#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:01:18.66#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.11:01:18.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:01:18.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:01:18.71#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.11:01:18.71#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.11:01:18.71$vck44/va=1,8 2006.145.11:01:18.71#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.11:01:18.71#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.11:01:18.71#ibcon#ireg 11 cls_cnt 2 2006.145.11:01:18.71#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.11:01:18.71#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.11:01:18.71#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.11:01:18.73#ibcon#[25=AT01-08\r\n] 2006.145.11:01:18.76#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.11:01:18.76#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.11:01:18.76#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.11:01:18.76#ibcon#ireg 7 cls_cnt 0 2006.145.11:01:18.76#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.11:01:18.89#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.11:01:18.89#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.11:01:18.90#ibcon#[25=USB\r\n] 2006.145.11:01:18.93#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.11:01:18.93#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.11:01:18.93#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.11:01:18.93#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.11:01:18.93$vck44/valo=2,534.99 2006.145.11:01:18.93#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.11:01:18.93#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.11:01:18.93#ibcon#ireg 17 cls_cnt 0 2006.145.11:01:18.93#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.11:01:18.93#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.11:01:18.93#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.11:01:18.96#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.11:01:19.00#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.11:01:19.00#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.11:01:19.00#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.11:01:19.00#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.11:01:19.00$vck44/va=2,7 2006.145.11:01:19.00#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.11:01:19.00#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.11:01:19.00#ibcon#ireg 11 cls_cnt 2 2006.145.11:01:19.00#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.11:01:19.05#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.11:01:19.05#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.11:01:19.07#ibcon#[25=AT02-07\r\n] 2006.145.11:01:19.10#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.11:01:19.10#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.11:01:19.10#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.11:01:19.10#ibcon#ireg 7 cls_cnt 0 2006.145.11:01:19.10#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.11:01:19.22#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.11:01:19.22#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.11:01:19.24#ibcon#[25=USB\r\n] 2006.145.11:01:19.27#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.11:01:19.27#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.11:01:19.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.11:01:19.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.11:01:19.27$vck44/valo=3,564.99 2006.145.11:01:19.27#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.11:01:19.27#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.11:01:19.27#ibcon#ireg 17 cls_cnt 0 2006.145.11:01:19.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.11:01:19.27#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.11:01:19.27#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.11:01:19.29#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.11:01:19.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.11:01:19.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.11:01:19.33#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.11:01:19.33#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.11:01:19.33$vck44/va=3,8 2006.145.11:01:19.33#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.11:01:19.33#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.11:01:19.33#ibcon#ireg 11 cls_cnt 2 2006.145.11:01:19.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:01:19.39#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:01:19.39#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:01:19.41#ibcon#[25=AT03-08\r\n] 2006.145.11:01:19.44#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:01:19.44#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:01:19.44#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.11:01:19.44#ibcon#ireg 7 cls_cnt 0 2006.145.11:01:19.44#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:01:19.56#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:01:19.56#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:01:19.58#ibcon#[25=USB\r\n] 2006.145.11:01:19.61#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:01:19.61#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:01:19.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.11:01:19.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.11:01:19.61$vck44/valo=4,624.99 2006.145.11:01:19.61#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.11:01:19.61#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.11:01:19.61#ibcon#ireg 17 cls_cnt 0 2006.145.11:01:19.61#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:01:19.61#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:01:19.61#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:01:19.63#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.11:01:19.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:01:19.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:01:19.67#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.11:01:19.67#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.11:01:19.67$vck44/va=4,7 2006.145.11:01:19.67#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.11:01:19.67#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.11:01:19.67#ibcon#ireg 11 cls_cnt 2 2006.145.11:01:19.67#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.11:01:19.73#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.11:01:19.73#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.11:01:19.75#ibcon#[25=AT04-07\r\n] 2006.145.11:01:19.78#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.11:01:19.78#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.11:01:19.78#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.11:01:19.78#ibcon#ireg 7 cls_cnt 0 2006.145.11:01:19.78#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.11:01:19.90#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.11:01:19.90#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.11:01:19.92#ibcon#[25=USB\r\n] 2006.145.11:01:19.95#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.11:01:19.95#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.11:01:19.95#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.11:01:19.95#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.11:01:19.95$vck44/valo=5,734.99 2006.145.11:01:19.95#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.11:01:19.95#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.11:01:19.95#ibcon#ireg 17 cls_cnt 0 2006.145.11:01:19.95#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:01:19.95#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:01:19.95#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:01:19.97#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.11:01:20.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:01:20.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:01:20.01#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.11:01:20.01#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.11:01:20.01$vck44/va=5,4 2006.145.11:01:20.01#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.11:01:20.01#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.11:01:20.01#ibcon#ireg 11 cls_cnt 2 2006.145.11:01:20.01#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:01:20.07#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:01:20.07#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:01:20.09#ibcon#[25=AT05-04\r\n] 2006.145.11:01:20.12#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:01:20.12#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:01:20.12#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.11:01:20.12#ibcon#ireg 7 cls_cnt 0 2006.145.11:01:20.12#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:01:20.24#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:01:20.24#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:01:20.26#ibcon#[25=USB\r\n] 2006.145.11:01:20.29#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:01:20.29#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:01:20.29#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.11:01:20.29#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.11:01:20.29$vck44/valo=6,814.99 2006.145.11:01:20.29#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.11:01:20.29#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.11:01:20.29#ibcon#ireg 17 cls_cnt 0 2006.145.11:01:20.29#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:01:20.29#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:01:20.29#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:01:20.31#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.11:01:20.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:01:20.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:01:20.35#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.11:01:20.35#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.11:01:20.35$vck44/va=6,4 2006.145.11:01:20.35#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.11:01:20.35#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.11:01:20.35#ibcon#ireg 11 cls_cnt 2 2006.145.11:01:20.35#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:01:20.41#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:01:20.41#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:01:20.43#ibcon#[25=AT06-04\r\n] 2006.145.11:01:20.46#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:01:20.46#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:01:20.46#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.11:01:20.46#ibcon#ireg 7 cls_cnt 0 2006.145.11:01:20.46#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:01:20.58#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:01:20.58#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:01:20.60#ibcon#[25=USB\r\n] 2006.145.11:01:20.63#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:01:20.63#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:01:20.63#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.11:01:20.63#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.11:01:20.63$vck44/valo=7,864.99 2006.145.11:01:20.63#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.11:01:20.63#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.11:01:20.63#ibcon#ireg 17 cls_cnt 0 2006.145.11:01:20.63#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:01:20.63#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:01:20.63#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:01:20.65#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.11:01:20.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:01:20.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:01:20.69#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.11:01:20.69#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.11:01:20.69$vck44/va=7,4 2006.145.11:01:20.69#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.11:01:20.69#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.11:01:20.69#ibcon#ireg 11 cls_cnt 2 2006.145.11:01:20.69#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:01:20.75#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:01:20.75#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:01:20.77#ibcon#[25=AT07-04\r\n] 2006.145.11:01:20.80#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:01:20.80#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:01:20.80#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.11:01:20.80#ibcon#ireg 7 cls_cnt 0 2006.145.11:01:20.80#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:01:20.92#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:01:20.92#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:01:20.94#ibcon#[25=USB\r\n] 2006.145.11:01:20.97#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:01:20.97#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:01:20.97#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.11:01:20.97#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.11:01:20.97$vck44/valo=8,884.99 2006.145.11:01:20.97#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.11:01:20.97#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.11:01:20.97#ibcon#ireg 17 cls_cnt 0 2006.145.11:01:20.97#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:01:20.97#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:01:20.97#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:01:20.99#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.11:01:21.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:01:21.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:01:21.03#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.11:01:21.03#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.11:01:21.03$vck44/va=8,4 2006.145.11:01:21.03#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.11:01:21.03#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.11:01:21.03#ibcon#ireg 11 cls_cnt 2 2006.145.11:01:21.03#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.11:01:21.09#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.11:01:21.09#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.11:01:21.11#ibcon#[25=AT08-04\r\n] 2006.145.11:01:21.14#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.11:01:21.14#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.11:01:21.14#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.11:01:21.14#ibcon#ireg 7 cls_cnt 0 2006.145.11:01:21.14#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.11:01:21.26#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.11:01:21.26#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.11:01:21.28#ibcon#[25=USB\r\n] 2006.145.11:01:21.31#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.11:01:21.31#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.11:01:21.31#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.11:01:21.31#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.11:01:21.31$vck44/vblo=1,629.99 2006.145.11:01:21.31#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.11:01:21.31#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.11:01:21.31#ibcon#ireg 17 cls_cnt 0 2006.145.11:01:21.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:01:21.31#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:01:21.31#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:01:21.34#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.11:01:21.38#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:01:21.38#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:01:21.38#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.11:01:21.38#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.11:01:21.38$vck44/vb=1,3 2006.145.11:01:21.38#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.11:01:21.38#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.11:01:21.38#ibcon#ireg 11 cls_cnt 2 2006.145.11:01:21.38#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.11:01:21.38#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.11:01:21.38#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.11:01:21.40#ibcon#[27=AT01-03\r\n] 2006.145.11:01:21.43#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.11:01:21.43#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.11:01:21.43#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.11:01:21.43#ibcon#ireg 7 cls_cnt 0 2006.145.11:01:21.43#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.11:01:21.55#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.11:01:21.55#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.11:01:21.57#ibcon#[27=USB\r\n] 2006.145.11:01:21.60#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.11:01:21.60#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.11:01:21.60#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.11:01:21.60#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.11:01:21.60$vck44/vblo=2,634.99 2006.145.11:01:21.60#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.11:01:21.60#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.11:01:21.60#ibcon#ireg 17 cls_cnt 0 2006.145.11:01:21.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:01:21.60#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:01:21.60#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:01:21.62#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.11:01:21.66#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:01:21.66#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:01:21.66#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.11:01:21.66#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.11:01:21.66$vck44/vb=2,4 2006.145.11:01:21.66#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.11:01:21.66#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.11:01:21.66#ibcon#ireg 11 cls_cnt 2 2006.145.11:01:21.66#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.11:01:21.72#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.11:01:21.72#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.11:01:21.74#ibcon#[27=AT02-04\r\n] 2006.145.11:01:21.77#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.11:01:21.77#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.11:01:21.77#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.11:01:21.77#ibcon#ireg 7 cls_cnt 0 2006.145.11:01:21.77#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.11:01:21.89#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.11:01:21.89#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.11:01:21.91#ibcon#[27=USB\r\n] 2006.145.11:01:21.94#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.11:01:21.94#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.11:01:21.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.11:01:21.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.11:01:21.94$vck44/vblo=3,649.99 2006.145.11:01:21.94#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.11:01:21.94#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.11:01:21.94#ibcon#ireg 17 cls_cnt 0 2006.145.11:01:21.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.11:01:21.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.11:01:21.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.11:01:21.96#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.11:01:22.00#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.11:01:22.00#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.11:01:22.00#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.11:01:22.00#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.11:01:22.00$vck44/vb=3,4 2006.145.11:01:22.00#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.11:01:22.00#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.11:01:22.00#ibcon#ireg 11 cls_cnt 2 2006.145.11:01:22.00#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.11:01:22.06#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.11:01:22.06#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.11:01:22.08#ibcon#[27=AT03-04\r\n] 2006.145.11:01:22.11#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.11:01:22.11#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.11:01:22.11#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.11:01:22.11#ibcon#ireg 7 cls_cnt 0 2006.145.11:01:22.11#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.11:01:22.23#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.11:01:22.23#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.11:01:22.25#ibcon#[27=USB\r\n] 2006.145.11:01:22.28#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.11:01:22.28#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.11:01:22.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.11:01:22.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.11:01:22.28$vck44/vblo=4,679.99 2006.145.11:01:22.28#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.11:01:22.28#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.11:01:22.28#ibcon#ireg 17 cls_cnt 0 2006.145.11:01:22.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.11:01:22.28#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.11:01:22.28#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.11:01:22.30#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.11:01:22.34#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.11:01:22.34#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.11:01:22.34#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.11:01:22.34#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.11:01:22.34$vck44/vb=4,4 2006.145.11:01:22.34#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.11:01:22.34#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.11:01:22.34#ibcon#ireg 11 cls_cnt 2 2006.145.11:01:22.34#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:01:22.40#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:01:22.40#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:01:22.42#ibcon#[27=AT04-04\r\n] 2006.145.11:01:22.45#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:01:22.45#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:01:22.45#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.11:01:22.45#ibcon#ireg 7 cls_cnt 0 2006.145.11:01:22.45#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:01:22.57#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:01:22.57#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:01:22.59#ibcon#[27=USB\r\n] 2006.145.11:01:22.62#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:01:22.62#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:01:22.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.11:01:22.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.11:01:22.62$vck44/vblo=5,709.99 2006.145.11:01:22.62#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.11:01:22.62#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.11:01:22.62#ibcon#ireg 17 cls_cnt 0 2006.145.11:01:22.62#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:01:22.62#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:01:22.62#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:01:22.64#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.11:01:22.68#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:01:22.68#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:01:22.68#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.11:01:22.68#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.11:01:22.68$vck44/vb=5,4 2006.145.11:01:22.68#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.11:01:22.68#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.11:01:22.68#ibcon#ireg 11 cls_cnt 2 2006.145.11:01:22.68#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.11:01:22.74#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.11:01:22.74#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.11:01:22.76#ibcon#[27=AT05-04\r\n] 2006.145.11:01:22.79#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.11:01:22.79#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.11:01:22.79#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.11:01:22.79#ibcon#ireg 7 cls_cnt 0 2006.145.11:01:22.79#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.11:01:22.91#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.11:01:22.91#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.11:01:22.93#ibcon#[27=USB\r\n] 2006.145.11:01:22.96#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.11:01:22.96#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.11:01:22.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.11:01:22.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.11:01:22.96$vck44/vblo=6,719.99 2006.145.11:01:22.96#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.11:01:22.96#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.11:01:22.96#ibcon#ireg 17 cls_cnt 0 2006.145.11:01:22.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:01:22.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:01:22.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:01:22.98#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.11:01:23.02#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:01:23.02#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:01:23.02#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.11:01:23.02#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.11:01:23.02$vck44/vb=6,4 2006.145.11:01:23.02#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.11:01:23.02#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.11:01:23.02#ibcon#ireg 11 cls_cnt 2 2006.145.11:01:23.02#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:01:23.08#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:01:23.08#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:01:23.10#ibcon#[27=AT06-04\r\n] 2006.145.11:01:23.13#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:01:23.13#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:01:23.13#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.11:01:23.13#ibcon#ireg 7 cls_cnt 0 2006.145.11:01:23.13#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:01:23.25#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:01:23.25#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:01:23.27#ibcon#[27=USB\r\n] 2006.145.11:01:23.30#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:01:23.30#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:01:23.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.11:01:23.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.11:01:23.30$vck44/vblo=7,734.99 2006.145.11:01:23.30#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.11:01:23.30#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.11:01:23.30#ibcon#ireg 17 cls_cnt 0 2006.145.11:01:23.30#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:01:23.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:01:23.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:01:23.32#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.11:01:23.36#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:01:23.36#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:01:23.36#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.11:01:23.36#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.11:01:23.36$vck44/vb=7,4 2006.145.11:01:23.36#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.11:01:23.36#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.11:01:23.36#ibcon#ireg 11 cls_cnt 2 2006.145.11:01:23.36#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:01:23.42#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:01:23.42#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:01:23.44#ibcon#[27=AT07-04\r\n] 2006.145.11:01:23.47#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:01:23.47#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:01:23.47#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.11:01:23.47#ibcon#ireg 7 cls_cnt 0 2006.145.11:01:23.47#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:01:23.59#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:01:23.59#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:01:23.61#ibcon#[27=USB\r\n] 2006.145.11:01:23.64#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:01:23.64#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:01:23.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.11:01:23.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.11:01:23.64$vck44/vblo=8,744.99 2006.145.11:01:23.64#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.11:01:23.64#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.11:01:23.64#ibcon#ireg 17 cls_cnt 0 2006.145.11:01:23.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:01:23.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:01:23.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:01:23.66#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.11:01:23.70#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:01:23.70#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:01:23.70#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.11:01:23.70#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.11:01:23.70$vck44/vb=8,4 2006.145.11:01:23.70#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.11:01:23.70#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.11:01:23.70#ibcon#ireg 11 cls_cnt 2 2006.145.11:01:23.70#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:01:23.76#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:01:23.76#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:01:23.78#ibcon#[27=AT08-04\r\n] 2006.145.11:01:23.81#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:01:23.81#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:01:23.81#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.11:01:23.81#ibcon#ireg 7 cls_cnt 0 2006.145.11:01:23.81#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:01:23.93#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:01:23.93#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:01:23.95#ibcon#[27=USB\r\n] 2006.145.11:01:23.98#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:01:23.98#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:01:23.98#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.11:01:23.98#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.11:01:23.98$vck44/vabw=wide 2006.145.11:01:23.98#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.11:01:23.98#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.11:01:23.98#ibcon#ireg 8 cls_cnt 0 2006.145.11:01:23.98#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:01:23.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:01:23.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:01:24.00#ibcon#[25=BW32\r\n] 2006.145.11:01:24.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:01:24.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:01:24.03#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.11:01:24.03#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.11:01:24.03$vck44/vbbw=wide 2006.145.11:01:24.03#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.11:01:24.03#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.11:01:24.03#ibcon#ireg 8 cls_cnt 0 2006.145.11:01:24.03#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:01:24.10#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:01:24.10#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:01:24.12#ibcon#[27=BW32\r\n] 2006.145.11:01:24.15#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:01:24.15#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:01:24.15#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.11:01:24.15#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.11:01:24.15$setupk4/ifdk4 2006.145.11:01:24.15$ifdk4/lo= 2006.145.11:01:24.15$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.11:01:24.15$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.11:01:24.15$ifdk4/patch= 2006.145.11:01:24.15$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.11:01:24.15$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.11:01:24.15$setupk4/!*+20s 2006.145.11:01:26.95#abcon#<5=/05 2.1 4.8 16.95 661019.8\r\n> 2006.145.11:01:26.97#abcon#{5=INTERFACE CLEAR} 2006.145.11:01:27.05#abcon#[5=S1D000X0/0*\r\n] 2006.145.11:01:37.14#abcon#<5=/05 2.1 4.8 16.95 671019.8\r\n> 2006.145.11:01:37.16#abcon#{5=INTERFACE CLEAR} 2006.145.11:01:37.22#abcon#[5=S1D000X0/0*\r\n] 2006.145.11:01:38.63$setupk4/"tpicd 2006.145.11:01:38.63$setupk4/echo=off 2006.145.11:01:38.63$setupk4/xlog=off 2006.145.11:01:38.63:!2006.145.11:05:18 2006.145.11:01:49.14#trakl#Source acquired 2006.145.11:01:49.14#flagr#flagr/antenna,acquired 2006.145.11:05:18.00:preob 2006.145.11:05:18.14/onsource/TRACKING 2006.145.11:05:18.14:!2006.145.11:05:28 2006.145.11:05:28.00:"tape 2006.145.11:05:28.00:"st=record 2006.145.11:05:28.00:data_valid=on 2006.145.11:05:28.00:midob 2006.145.11:05:28.14/onsource/TRACKING 2006.145.11:05:28.14/wx/16.88,1019.9,66 2006.145.11:05:28.28/cable/+6.5446E-03 2006.145.11:05:29.37/va/01,08,usb,yes,28,30 2006.145.11:05:29.37/va/02,07,usb,yes,29,30 2006.145.11:05:29.37/va/03,08,usb,yes,27,28 2006.145.11:05:29.37/va/04,07,usb,yes,30,32 2006.145.11:05:29.37/va/05,04,usb,yes,27,27 2006.145.11:05:29.37/va/06,04,usb,yes,30,30 2006.145.11:05:29.37/va/07,04,usb,yes,30,31 2006.145.11:05:29.37/va/08,04,usb,yes,26,31 2006.145.11:05:29.60/valo/01,524.99,yes,locked 2006.145.11:05:29.60/valo/02,534.99,yes,locked 2006.145.11:05:29.60/valo/03,564.99,yes,locked 2006.145.11:05:29.60/valo/04,624.99,yes,locked 2006.145.11:05:29.60/valo/05,734.99,yes,locked 2006.145.11:05:29.60/valo/06,814.99,yes,locked 2006.145.11:05:29.60/valo/07,864.99,yes,locked 2006.145.11:05:29.60/valo/08,884.99,yes,locked 2006.145.11:05:30.69/vb/01,03,usb,yes,35,33 2006.145.11:05:30.69/vb/02,04,usb,yes,31,31 2006.145.11:05:30.69/vb/03,04,usb,yes,28,30 2006.145.11:05:30.69/vb/04,04,usb,yes,32,31 2006.145.11:05:30.69/vb/05,04,usb,yes,25,27 2006.145.11:05:30.69/vb/06,04,usb,yes,29,25 2006.145.11:05:30.69/vb/07,04,usb,yes,29,28 2006.145.11:05:30.69/vb/08,04,usb,yes,26,30 2006.145.11:05:30.93/vblo/01,629.99,yes,locked 2006.145.11:05:30.93/vblo/02,634.99,yes,locked 2006.145.11:05:30.93/vblo/03,649.99,yes,locked 2006.145.11:05:30.93/vblo/04,679.99,yes,locked 2006.145.11:05:30.93/vblo/05,709.99,yes,locked 2006.145.11:05:30.93/vblo/06,719.99,yes,locked 2006.145.11:05:30.93/vblo/07,734.99,yes,locked 2006.145.11:05:30.93/vblo/08,744.99,yes,locked 2006.145.11:05:31.08/vabw/8 2006.145.11:05:31.23/vbbw/8 2006.145.11:05:31.32/xfe/off,on,14.7 2006.145.11:05:31.71/ifatt/23,28,28,28 2006.145.11:05:32.08/fmout-gps/S +5.4E-08 2006.145.11:05:32.12:!2006.145.11:12:08 2006.145.11:12:08.00:data_valid=off 2006.145.11:12:08.00:"et 2006.145.11:12:08.00:!+3s 2006.145.11:12:11.02:"tape 2006.145.11:12:11.02:postob 2006.145.11:12:11.17/cable/+6.5443E-03 2006.145.11:12:11.17/wx/16.76,1020.0,66 2006.145.11:12:12.08/fmout-gps/S +5.4E-08 2006.145.11:12:12.08:scan_name=145-1119,jd0605,390 2006.145.11:12:12.08:source=1308+326,131028.66,322043.8,2000.0,cw 2006.145.11:12:13.14#flagr#flagr/antenna,new-source 2006.145.11:12:13.14:checkk5 2006.145.11:12:13.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.11:12:14.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.11:12:14.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.11:12:14.91/chk_autoobs//k5ts4/ autoobs is running! 2006.145.11:12:15.35/chk_obsdata//k5ts1/T1451105??a.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.145.11:12:15.78/chk_obsdata//k5ts2/T1451105??b.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.145.11:12:19.19/chk_obsdata//k5ts3/T1451105??c.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.145.11:12:19.64/chk_obsdata//k5ts4/T1451105??d.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.145.11:12:20.39/k5log//k5ts1_log_newline 2006.145.11:12:21.14/k5log//k5ts2_log_newline 2006.145.11:12:21.89/k5log//k5ts3_log_newline 2006.145.11:12:22.64/k5log//k5ts4_log_newline 2006.145.11:12:22.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.11:12:22.67:setupk4=1 2006.145.11:12:22.67$setupk4/echo=on 2006.145.11:12:22.67$setupk4/pcalon 2006.145.11:12:22.67$pcalon/"no phase cal control is implemented here 2006.145.11:12:22.67$setupk4/"tpicd=stop 2006.145.11:12:22.67$setupk4/"rec=synch_on 2006.145.11:12:22.67$setupk4/"rec_mode=128 2006.145.11:12:22.67$setupk4/!* 2006.145.11:12:22.67$setupk4/recpk4 2006.145.11:12:22.67$recpk4/recpatch= 2006.145.11:12:22.67$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.11:12:22.67$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.11:12:22.67$setupk4/vck44 2006.145.11:12:22.67$vck44/valo=1,524.99 2006.145.11:12:22.67#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.11:12:22.67#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.11:12:22.67#ibcon#ireg 17 cls_cnt 0 2006.145.11:12:22.67#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:12:22.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:12:22.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:12:22.71#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.11:12:22.76#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:12:22.76#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:12:22.76#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.11:12:22.76#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.11:12:22.76$vck44/va=1,8 2006.145.11:12:22.76#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.11:12:22.76#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.11:12:22.76#ibcon#ireg 11 cls_cnt 2 2006.145.11:12:22.76#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.11:12:22.76#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.11:12:22.76#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.11:12:22.78#ibcon#[25=AT01-08\r\n] 2006.145.11:12:22.81#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.11:12:22.81#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.11:12:22.81#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.11:12:22.81#ibcon#ireg 7 cls_cnt 0 2006.145.11:12:22.81#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.11:12:22.93#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.11:12:22.93#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.11:12:22.95#ibcon#[25=USB\r\n] 2006.145.11:12:22.98#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.11:12:22.98#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.11:12:22.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.11:12:22.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.11:12:22.98$vck44/valo=2,534.99 2006.145.11:12:22.98#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.11:12:22.98#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.11:12:22.98#ibcon#ireg 17 cls_cnt 0 2006.145.11:12:22.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.11:12:22.98#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.11:12:22.98#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.11:12:23.01#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.11:12:23.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.11:12:23.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.11:12:23.05#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.11:12:23.05#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.11:12:23.05$vck44/va=2,7 2006.145.11:12:23.05#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.11:12:23.05#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.11:12:23.05#ibcon#ireg 11 cls_cnt 2 2006.145.11:12:23.05#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:12:23.10#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:12:23.10#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:12:23.12#ibcon#[25=AT02-07\r\n] 2006.145.11:12:23.15#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:12:23.15#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:12:23.15#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.11:12:23.15#ibcon#ireg 7 cls_cnt 0 2006.145.11:12:23.15#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:12:23.27#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:12:23.27#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:12:23.29#ibcon#[25=USB\r\n] 2006.145.11:12:23.32#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:12:23.32#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:12:23.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.11:12:23.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.11:12:23.32$vck44/valo=3,564.99 2006.145.11:12:23.32#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.11:12:23.32#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.11:12:23.32#ibcon#ireg 17 cls_cnt 0 2006.145.11:12:23.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:12:23.32#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:12:23.32#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:12:23.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.11:12:23.38#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:12:23.38#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:12:23.38#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.11:12:23.38#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.11:12:23.38$vck44/va=3,8 2006.145.11:12:23.38#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.11:12:23.38#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.11:12:23.38#ibcon#ireg 11 cls_cnt 2 2006.145.11:12:23.38#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:12:23.44#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:12:23.44#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:12:23.46#ibcon#[25=AT03-08\r\n] 2006.145.11:12:23.49#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:12:23.49#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:12:23.49#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.11:12:23.49#ibcon#ireg 7 cls_cnt 0 2006.145.11:12:23.49#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:12:23.61#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:12:23.61#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:12:23.63#ibcon#[25=USB\r\n] 2006.145.11:12:23.66#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:12:23.66#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:12:23.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.11:12:23.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.11:12:23.66$vck44/valo=4,624.99 2006.145.11:12:23.66#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.11:12:23.66#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.11:12:23.66#ibcon#ireg 17 cls_cnt 0 2006.145.11:12:23.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:12:23.66#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:12:23.66#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:12:23.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.11:12:23.72#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:12:23.72#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:12:23.72#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.11:12:23.72#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.11:12:23.72$vck44/va=4,7 2006.145.11:12:23.72#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.11:12:23.72#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.11:12:23.72#ibcon#ireg 11 cls_cnt 2 2006.145.11:12:23.72#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:12:23.78#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:12:23.78#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:12:23.80#ibcon#[25=AT04-07\r\n] 2006.145.11:12:23.83#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:12:23.83#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:12:23.83#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.11:12:23.83#ibcon#ireg 7 cls_cnt 0 2006.145.11:12:23.83#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:12:23.95#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:12:23.95#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:12:23.97#ibcon#[25=USB\r\n] 2006.145.11:12:24.00#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:12:24.00#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:12:24.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.11:12:24.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.11:12:24.00$vck44/valo=5,734.99 2006.145.11:12:24.00#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.11:12:24.00#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.11:12:24.00#ibcon#ireg 17 cls_cnt 0 2006.145.11:12:24.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:12:24.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:12:24.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:12:24.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.11:12:24.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:12:24.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:12:24.06#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.11:12:24.06#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.11:12:24.06$vck44/va=5,4 2006.145.11:12:24.06#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.11:12:24.06#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.11:12:24.06#ibcon#ireg 11 cls_cnt 2 2006.145.11:12:24.06#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:12:24.12#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:12:24.12#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:12:24.14#ibcon#[25=AT05-04\r\n] 2006.145.11:12:24.17#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:12:24.17#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:12:24.17#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.11:12:24.17#ibcon#ireg 7 cls_cnt 0 2006.145.11:12:24.17#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:12:24.29#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:12:24.29#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:12:24.31#ibcon#[25=USB\r\n] 2006.145.11:12:24.34#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:12:24.34#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:12:24.34#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.11:12:24.34#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.11:12:24.34$vck44/valo=6,814.99 2006.145.11:12:24.34#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.11:12:24.34#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.11:12:24.34#ibcon#ireg 17 cls_cnt 0 2006.145.11:12:24.34#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:12:24.34#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:12:24.34#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:12:24.36#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.11:12:24.40#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:12:24.40#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:12:24.40#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.11:12:24.40#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.11:12:24.40$vck44/va=6,4 2006.145.11:12:24.40#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.11:12:24.40#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.11:12:24.40#ibcon#ireg 11 cls_cnt 2 2006.145.11:12:24.40#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.11:12:24.46#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.11:12:24.46#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.11:12:24.48#ibcon#[25=AT06-04\r\n] 2006.145.11:12:24.51#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.11:12:24.51#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.11:12:24.51#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.11:12:24.51#ibcon#ireg 7 cls_cnt 0 2006.145.11:12:24.51#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.11:12:24.63#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.11:12:24.63#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.11:12:24.65#ibcon#[25=USB\r\n] 2006.145.11:12:24.68#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.11:12:24.68#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.11:12:24.68#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.11:12:24.68#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.11:12:24.68$vck44/valo=7,864.99 2006.145.11:12:24.68#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.11:12:24.68#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.11:12:24.68#ibcon#ireg 17 cls_cnt 0 2006.145.11:12:24.68#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.11:12:24.68#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.11:12:24.68#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.11:12:24.70#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.11:12:24.74#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.11:12:24.74#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.11:12:24.74#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.11:12:24.74#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.11:12:24.74$vck44/va=7,4 2006.145.11:12:24.74#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.11:12:24.74#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.11:12:24.74#ibcon#ireg 11 cls_cnt 2 2006.145.11:12:24.74#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.11:12:24.80#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.11:12:24.80#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.11:12:24.82#ibcon#[25=AT07-04\r\n] 2006.145.11:12:24.85#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.11:12:24.85#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.11:12:24.85#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.11:12:24.85#ibcon#ireg 7 cls_cnt 0 2006.145.11:12:24.85#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.11:12:24.97#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.11:12:24.97#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.11:12:24.99#ibcon#[25=USB\r\n] 2006.145.11:12:25.02#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.11:12:25.02#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.11:12:25.02#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.11:12:25.02#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.11:12:25.02$vck44/valo=8,884.99 2006.145.11:12:25.02#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.11:12:25.02#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.11:12:25.02#ibcon#ireg 17 cls_cnt 0 2006.145.11:12:25.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:12:25.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:12:25.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:12:25.04#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.11:12:25.08#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:12:25.08#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:12:25.08#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.11:12:25.08#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.11:12:25.08$vck44/va=8,4 2006.145.11:12:25.08#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.11:12:25.08#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.11:12:25.08#ibcon#ireg 11 cls_cnt 2 2006.145.11:12:25.08#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.11:12:25.14#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.11:12:25.14#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.11:12:25.16#ibcon#[25=AT08-04\r\n] 2006.145.11:12:25.19#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.11:12:25.19#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.11:12:25.19#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.11:12:25.19#ibcon#ireg 7 cls_cnt 0 2006.145.11:12:25.19#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.11:12:25.31#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.11:12:25.31#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.11:12:25.33#ibcon#[25=USB\r\n] 2006.145.11:12:25.36#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.11:12:25.36#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.11:12:25.36#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.11:12:25.36#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.11:12:25.36$vck44/vblo=1,629.99 2006.145.11:12:25.36#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.11:12:25.36#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.11:12:25.36#ibcon#ireg 17 cls_cnt 0 2006.145.11:12:25.36#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.11:12:25.36#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.11:12:25.36#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.11:12:25.38#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.11:12:25.42#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.11:12:25.42#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.11:12:25.42#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.11:12:25.42#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.11:12:25.42$vck44/vb=1,3 2006.145.11:12:25.42#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.11:12:25.42#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.11:12:25.42#ibcon#ireg 11 cls_cnt 2 2006.145.11:12:25.42#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.11:12:25.42#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.11:12:25.42#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.11:12:25.44#ibcon#[27=AT01-03\r\n] 2006.145.11:12:25.47#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.11:12:25.47#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.11:12:25.47#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.11:12:25.47#ibcon#ireg 7 cls_cnt 0 2006.145.11:12:25.47#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.11:12:25.59#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.11:12:25.59#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.11:12:25.61#ibcon#[27=USB\r\n] 2006.145.11:12:25.64#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.11:12:25.64#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.11:12:25.64#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.11:12:25.64#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.11:12:25.64$vck44/vblo=2,634.99 2006.145.11:12:25.64#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.11:12:25.64#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.11:12:25.64#ibcon#ireg 17 cls_cnt 0 2006.145.11:12:25.64#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:12:25.64#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:12:25.64#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:12:25.66#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.11:12:25.70#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:12:25.70#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:12:25.70#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.11:12:25.70#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.11:12:25.70$vck44/vb=2,4 2006.145.11:12:25.70#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.11:12:25.70#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.11:12:25.70#ibcon#ireg 11 cls_cnt 2 2006.145.11:12:25.70#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.11:12:25.76#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.11:12:25.76#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.11:12:25.78#ibcon#[27=AT02-04\r\n] 2006.145.11:12:25.81#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.11:12:25.81#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.11:12:25.81#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.11:12:25.81#ibcon#ireg 7 cls_cnt 0 2006.145.11:12:25.81#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.11:12:25.93#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.11:12:25.93#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.11:12:25.95#ibcon#[27=USB\r\n] 2006.145.11:12:25.98#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.11:12:25.98#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.11:12:25.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.11:12:25.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.11:12:25.98$vck44/vblo=3,649.99 2006.145.11:12:25.98#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.11:12:25.98#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.11:12:25.98#ibcon#ireg 17 cls_cnt 0 2006.145.11:12:25.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.11:12:25.98#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.11:12:25.98#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.11:12:26.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.11:12:26.04#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.11:12:26.04#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.11:12:26.04#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.11:12:26.04#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.11:12:26.04$vck44/vb=3,4 2006.145.11:12:26.04#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.11:12:26.04#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.11:12:26.04#ibcon#ireg 11 cls_cnt 2 2006.145.11:12:26.04#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:12:26.10#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:12:26.10#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:12:26.12#ibcon#[27=AT03-04\r\n] 2006.145.11:12:26.15#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:12:26.15#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:12:26.15#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.11:12:26.15#ibcon#ireg 7 cls_cnt 0 2006.145.11:12:26.15#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:12:26.27#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:12:26.27#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:12:26.29#ibcon#[27=USB\r\n] 2006.145.11:12:26.32#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:12:26.32#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:12:26.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.11:12:26.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.11:12:26.32$vck44/vblo=4,679.99 2006.145.11:12:26.32#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.11:12:26.32#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.11:12:26.32#ibcon#ireg 17 cls_cnt 0 2006.145.11:12:26.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:12:26.32#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:12:26.32#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:12:26.34#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.11:12:26.38#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:12:26.38#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:12:26.38#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.11:12:26.38#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.11:12:26.38$vck44/vb=4,4 2006.145.11:12:26.38#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.11:12:26.38#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.11:12:26.38#ibcon#ireg 11 cls_cnt 2 2006.145.11:12:26.38#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:12:26.44#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:12:26.44#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:12:26.46#ibcon#[27=AT04-04\r\n] 2006.145.11:12:26.49#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:12:26.49#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:12:26.49#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.11:12:26.49#ibcon#ireg 7 cls_cnt 0 2006.145.11:12:26.49#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:12:26.61#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:12:26.61#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:12:26.63#ibcon#[27=USB\r\n] 2006.145.11:12:26.66#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:12:26.66#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:12:26.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.11:12:26.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.11:12:26.66$vck44/vblo=5,709.99 2006.145.11:12:26.66#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.11:12:26.66#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.11:12:26.66#ibcon#ireg 17 cls_cnt 0 2006.145.11:12:26.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:12:26.66#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:12:26.66#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:12:26.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.11:12:26.72#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:12:26.72#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:12:26.72#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.11:12:26.72#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.11:12:26.72$vck44/vb=5,4 2006.145.11:12:26.72#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.11:12:26.72#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.11:12:26.72#ibcon#ireg 11 cls_cnt 2 2006.145.11:12:26.72#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:12:26.78#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:12:26.78#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:12:26.80#ibcon#[27=AT05-04\r\n] 2006.145.11:12:26.83#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:12:26.83#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:12:26.83#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.11:12:26.83#ibcon#ireg 7 cls_cnt 0 2006.145.11:12:26.83#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:12:26.95#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:12:26.95#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:12:26.97#ibcon#[27=USB\r\n] 2006.145.11:12:27.00#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:12:27.00#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:12:27.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.11:12:27.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.11:12:27.00$vck44/vblo=6,719.99 2006.145.11:12:27.00#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.11:12:27.00#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.11:12:27.00#ibcon#ireg 17 cls_cnt 0 2006.145.11:12:27.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:12:27.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:12:27.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:12:27.02#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.11:12:27.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:12:27.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:12:27.06#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.11:12:27.06#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.11:12:27.06$vck44/vb=6,4 2006.145.11:12:27.06#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.11:12:27.06#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.11:12:27.06#ibcon#ireg 11 cls_cnt 2 2006.145.11:12:27.06#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:12:27.12#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:12:27.12#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:12:27.14#ibcon#[27=AT06-04\r\n] 2006.145.11:12:27.17#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:12:27.17#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:12:27.17#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.11:12:27.17#ibcon#ireg 7 cls_cnt 0 2006.145.11:12:27.17#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:12:27.29#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:12:27.29#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:12:27.31#ibcon#[27=USB\r\n] 2006.145.11:12:27.34#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:12:27.34#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:12:27.34#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.11:12:27.34#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.11:12:27.34$vck44/vblo=7,734.99 2006.145.11:12:27.34#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.11:12:27.34#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.11:12:27.34#ibcon#ireg 17 cls_cnt 0 2006.145.11:12:27.34#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:12:27.34#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:12:27.34#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:12:27.36#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.11:12:27.40#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:12:27.40#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:12:27.40#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.11:12:27.40#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.11:12:27.40$vck44/vb=7,4 2006.145.11:12:27.40#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.11:12:27.40#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.11:12:27.40#ibcon#ireg 11 cls_cnt 2 2006.145.11:12:27.40#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.11:12:27.46#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.11:12:27.46#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.11:12:27.48#ibcon#[27=AT07-04\r\n] 2006.145.11:12:27.51#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.11:12:27.51#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.11:12:27.51#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.11:12:27.51#ibcon#ireg 7 cls_cnt 0 2006.145.11:12:27.51#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.11:12:27.63#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.11:12:27.63#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.11:12:27.65#ibcon#[27=USB\r\n] 2006.145.11:12:27.68#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.11:12:27.68#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.11:12:27.68#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.11:12:27.68#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.11:12:27.68$vck44/vblo=8,744.99 2006.145.11:12:27.68#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.11:12:27.68#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.11:12:27.68#ibcon#ireg 17 cls_cnt 0 2006.145.11:12:27.68#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.11:12:27.68#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.11:12:27.68#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.11:12:27.70#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.11:12:27.74#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.11:12:27.74#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.11:12:27.74#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.11:12:27.74#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.11:12:27.74$vck44/vb=8,4 2006.145.11:12:27.74#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.11:12:27.74#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.11:12:27.74#ibcon#ireg 11 cls_cnt 2 2006.145.11:12:27.74#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.11:12:27.80#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.11:12:27.80#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.11:12:27.82#ibcon#[27=AT08-04\r\n] 2006.145.11:12:27.85#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.11:12:27.85#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.11:12:27.85#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.11:12:27.85#ibcon#ireg 7 cls_cnt 0 2006.145.11:12:27.85#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.11:12:27.97#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.11:12:27.97#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.11:12:27.99#ibcon#[27=USB\r\n] 2006.145.11:12:28.02#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.11:12:28.02#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.11:12:28.02#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.11:12:28.02#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.11:12:28.02$vck44/vabw=wide 2006.145.11:12:28.02#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.11:12:28.02#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.11:12:28.02#ibcon#ireg 8 cls_cnt 0 2006.145.11:12:28.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:12:28.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:12:28.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:12:28.04#ibcon#[25=BW32\r\n] 2006.145.11:12:28.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:12:28.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:12:28.07#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.11:12:28.07#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.11:12:28.07$vck44/vbbw=wide 2006.145.11:12:28.07#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.11:12:28.07#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.11:12:28.07#ibcon#ireg 8 cls_cnt 0 2006.145.11:12:28.07#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:12:28.14#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:12:28.14#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:12:28.16#ibcon#[27=BW32\r\n] 2006.145.11:12:28.19#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:12:28.19#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:12:28.19#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.11:12:28.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.11:12:28.19$setupk4/ifdk4 2006.145.11:12:28.19$ifdk4/lo= 2006.145.11:12:28.19$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.11:12:28.19$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.11:12:28.19$ifdk4/patch= 2006.145.11:12:28.19$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.11:12:28.19$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.11:12:28.19$setupk4/!*+20s 2006.145.11:12:31.00#abcon#<5=/05 2.2 3.4 16.76 661020.0\r\n> 2006.145.11:12:31.02#abcon#{5=INTERFACE CLEAR} 2006.145.11:12:31.08#abcon#[5=S1D000X0/0*\r\n] 2006.145.11:12:41.17#abcon#<5=/05 2.2 3.4 16.76 671020.0\r\n> 2006.145.11:12:41.19#abcon#{5=INTERFACE CLEAR} 2006.145.11:12:41.25#abcon#[5=S1D000X0/0*\r\n] 2006.145.11:12:42.68$setupk4/"tpicd 2006.145.11:12:42.68$setupk4/echo=off 2006.145.11:12:42.68$setupk4/xlog=off 2006.145.11:12:42.68:!2006.145.11:18:58 2006.145.11:12:49.14#trakl#Source acquired 2006.145.11:12:50.14#flagr#flagr/antenna,acquired 2006.145.11:18:58.02:preob 2006.145.11:18:59.14/onsource/TRACKING 2006.145.11:18:59.14:!2006.145.11:19:08 2006.145.11:19:08.02:"tape 2006.145.11:19:08.02:"st=record 2006.145.11:19:08.02:data_valid=on 2006.145.11:19:08.02:midob 2006.145.11:19:09.14/onsource/TRACKING 2006.145.11:19:09.14/wx/16.68,1020.1,68 2006.145.11:19:09.32/cable/+6.5464E-03 2006.145.11:19:10.41/va/01,08,usb,yes,28,30 2006.145.11:19:10.41/va/02,07,usb,yes,29,30 2006.145.11:19:10.42/va/03,08,usb,yes,27,28 2006.145.11:19:10.42/va/04,07,usb,yes,31,32 2006.145.11:19:10.42/va/05,04,usb,yes,27,27 2006.145.11:19:10.42/va/06,04,usb,yes,30,30 2006.145.11:19:10.42/va/07,04,usb,yes,30,31 2006.145.11:19:10.42/va/08,04,usb,yes,26,31 2006.145.11:19:10.65/valo/01,524.99,yes,locked 2006.145.11:19:10.65/valo/02,534.99,yes,locked 2006.145.11:19:10.65/valo/03,564.99,yes,locked 2006.145.11:19:10.65/valo/04,624.99,yes,locked 2006.145.11:19:10.65/valo/05,734.99,yes,locked 2006.145.11:19:10.65/valo/06,814.99,yes,locked 2006.145.11:19:10.65/valo/07,864.99,yes,locked 2006.145.11:19:10.65/valo/08,884.99,yes,locked 2006.145.11:19:11.73/vb/01,03,usb,yes,35,33 2006.145.11:19:11.73/vb/02,04,usb,yes,31,31 2006.145.11:19:11.73/vb/03,04,usb,yes,28,31 2006.145.11:19:11.74/vb/04,04,usb,yes,32,31 2006.145.11:19:11.74/vb/05,04,usb,yes,25,27 2006.145.11:19:11.74/vb/06,04,usb,yes,29,25 2006.145.11:19:11.74/vb/07,04,usb,yes,29,28 2006.145.11:19:11.74/vb/08,04,usb,yes,26,30 2006.145.11:19:11.97/vblo/01,629.99,yes,locked 2006.145.11:19:11.97/vblo/02,634.99,yes,locked 2006.145.11:19:11.97/vblo/03,649.99,yes,locked 2006.145.11:19:11.97/vblo/04,679.99,yes,locked 2006.145.11:19:11.97/vblo/05,709.99,yes,locked 2006.145.11:19:11.97/vblo/06,719.99,yes,locked 2006.145.11:19:11.97/vblo/07,734.99,yes,locked 2006.145.11:19:11.97/vblo/08,744.99,yes,locked 2006.145.11:19:12.11/vabw/8 2006.145.11:19:12.26/vbbw/8 2006.145.11:19:12.41/xfe/off,on,15.0 2006.145.11:19:12.78/ifatt/23,28,28,28 2006.145.11:19:13.07/fmout-gps/S +5.3E-08 2006.145.11:19:13.12:!2006.145.11:25:38 2006.145.11:25:38.00:data_valid=off 2006.145.11:25:38.01:"et 2006.145.11:25:38.01:!+3s 2006.145.11:25:41.04:"tape 2006.145.11:25:41.05:postob 2006.145.11:25:41.25/cable/+6.5438E-03 2006.145.11:25:41.26/wx/16.60,1020.2,68 2006.145.11:25:41.33/fmout-gps/S +5.4E-08 2006.145.11:25:41.33:scan_name=145-1126,jd0605,100 2006.145.11:25:41.33:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.145.11:25:42.14#flagr#flagr/antenna,new-source 2006.145.11:25:42.15:checkk5 2006.145.11:25:42.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.11:25:42.99/chk_autoobs//k5ts2/ autoobs is running! 2006.145.11:25:43.43/chk_autoobs//k5ts3/ autoobs is running! 2006.145.11:25:43.86/chk_autoobs//k5ts4/ autoobs is running! 2006.145.11:25:44.29/chk_obsdata//k5ts1/T1451119??a.dat file size is correct (nominal:1560MB, actual:1556MB). 2006.145.11:25:44.72/chk_obsdata//k5ts2/T1451119??b.dat file size is correct (nominal:1560MB, actual:1556MB). 2006.145.11:25:45.15/chk_obsdata//k5ts3/T1451119??c.dat file size is correct (nominal:1560MB, actual:1556MB). 2006.145.11:25:45.58/chk_obsdata//k5ts4/T1451119??d.dat file size is correct (nominal:1560MB, actual:1556MB). 2006.145.11:25:46.35/k5log//k5ts1_log_newline 2006.145.11:25:47.10/k5log//k5ts2_log_newline 2006.145.11:25:47.86/k5log//k5ts3_log_newline 2006.145.11:25:48.61/k5log//k5ts4_log_newline 2006.145.11:25:48.63/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.11:25:48.63:setupk4=1 2006.145.11:25:48.63$setupk4/echo=on 2006.145.11:25:48.63$setupk4/pcalon 2006.145.11:25:48.63$pcalon/"no phase cal control is implemented here 2006.145.11:25:48.63$setupk4/"tpicd=stop 2006.145.11:25:48.63$setupk4/"rec=synch_on 2006.145.11:25:48.63$setupk4/"rec_mode=128 2006.145.11:25:48.63$setupk4/!* 2006.145.11:25:48.63$setupk4/recpk4 2006.145.11:25:48.63$recpk4/recpatch= 2006.145.11:25:48.64$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.11:25:48.64$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.11:25:48.64$setupk4/vck44 2006.145.11:25:48.64$vck44/valo=1,524.99 2006.145.11:25:48.64#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.11:25:48.64#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.11:25:48.64#ibcon#ireg 17 cls_cnt 0 2006.145.11:25:48.64#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.11:25:48.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.11:25:48.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.11:25:48.65#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.11:25:48.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.11:25:48.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.11:25:48.71#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.11:25:48.71#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.11:25:48.71$vck44/va=1,8 2006.145.11:25:48.71#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.11:25:48.71#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.11:25:48.71#ibcon#ireg 11 cls_cnt 2 2006.145.11:25:48.71#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.11:25:48.71#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.11:25:48.71#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.11:25:48.73#ibcon#[25=AT01-08\r\n] 2006.145.11:25:48.75#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.11:25:48.75#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.11:25:48.75#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.11:25:48.75#ibcon#ireg 7 cls_cnt 0 2006.145.11:25:48.75#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.11:25:48.87#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.11:25:48.87#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.11:25:48.89#ibcon#[25=USB\r\n] 2006.145.11:25:48.92#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.11:25:48.92#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.11:25:48.92#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.11:25:48.92#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.11:25:48.92$vck44/valo=2,534.99 2006.145.11:25:48.92#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.11:25:48.92#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.11:25:48.92#ibcon#ireg 17 cls_cnt 0 2006.145.11:25:48.92#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.11:25:48.92#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.11:25:48.92#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.11:25:48.94#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.11:25:48.98#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.11:25:48.98#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.11:25:48.98#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.11:25:48.98#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.11:25:48.98$vck44/va=2,7 2006.145.11:25:48.98#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.11:25:48.98#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.11:25:48.98#ibcon#ireg 11 cls_cnt 2 2006.145.11:25:48.98#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.11:25:49.04#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.11:25:49.04#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.11:25:49.06#ibcon#[25=AT02-07\r\n] 2006.145.11:25:49.09#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.11:25:49.09#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.11:25:49.09#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.11:25:49.09#ibcon#ireg 7 cls_cnt 0 2006.145.11:25:49.09#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.11:25:49.21#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.11:25:49.21#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.11:25:49.23#ibcon#[25=USB\r\n] 2006.145.11:25:49.26#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.11:25:49.26#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.11:25:49.26#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.11:25:49.26#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.11:25:49.26$vck44/valo=3,564.99 2006.145.11:25:49.26#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.11:25:49.26#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.11:25:49.26#ibcon#ireg 17 cls_cnt 0 2006.145.11:25:49.26#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.11:25:49.26#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.11:25:49.26#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.11:25:49.28#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.11:25:49.32#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.11:25:49.32#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.11:25:49.32#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.11:25:49.32#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.11:25:49.32$vck44/va=3,8 2006.145.11:25:49.32#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.11:25:49.32#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.11:25:49.32#ibcon#ireg 11 cls_cnt 2 2006.145.11:25:49.32#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.11:25:49.38#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.11:25:49.38#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.11:25:49.40#ibcon#[25=AT03-08\r\n] 2006.145.11:25:49.43#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.11:25:49.43#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.11:25:49.43#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.11:25:49.43#ibcon#ireg 7 cls_cnt 0 2006.145.11:25:49.43#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.11:25:49.55#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.11:25:49.55#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.11:25:49.57#ibcon#[25=USB\r\n] 2006.145.11:25:49.60#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.11:25:49.60#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.11:25:49.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.11:25:49.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.11:25:49.60$vck44/valo=4,624.99 2006.145.11:25:49.60#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.11:25:49.60#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.11:25:49.60#ibcon#ireg 17 cls_cnt 0 2006.145.11:25:49.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:25:49.60#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:25:49.60#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:25:49.62#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.11:25:49.66#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:25:49.66#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:25:49.66#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.11:25:49.66#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.11:25:49.66$vck44/va=4,7 2006.145.11:25:49.66#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.11:25:49.66#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.11:25:49.66#ibcon#ireg 11 cls_cnt 2 2006.145.11:25:49.66#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.11:25:49.72#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.11:25:49.72#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.11:25:49.74#ibcon#[25=AT04-07\r\n] 2006.145.11:25:49.77#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.11:25:49.77#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.11:25:49.77#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.11:25:49.77#ibcon#ireg 7 cls_cnt 0 2006.145.11:25:49.77#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.11:25:49.89#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.11:25:49.89#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.11:25:49.91#ibcon#[25=USB\r\n] 2006.145.11:25:49.94#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.11:25:49.94#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.11:25:49.94#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.11:25:49.94#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.11:25:49.94$vck44/valo=5,734.99 2006.145.11:25:49.94#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.11:25:49.94#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.11:25:49.94#ibcon#ireg 17 cls_cnt 0 2006.145.11:25:49.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.11:25:49.94#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.11:25:49.94#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.11:25:49.97#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.11:25:50.01#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.11:25:50.01#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.11:25:50.01#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.11:25:50.01#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.11:25:50.01$vck44/va=5,4 2006.145.11:25:50.01#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.11:25:50.01#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.11:25:50.01#ibcon#ireg 11 cls_cnt 2 2006.145.11:25:50.01#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.11:25:50.07#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.11:25:50.07#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.11:25:50.08#ibcon#[25=AT05-04\r\n] 2006.145.11:25:50.11#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.11:25:50.11#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.11:25:50.11#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.11:25:50.11#ibcon#ireg 7 cls_cnt 0 2006.145.11:25:50.11#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.11:25:50.23#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.11:25:50.23#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.11:25:50.25#ibcon#[25=USB\r\n] 2006.145.11:25:50.28#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.11:25:50.28#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.11:25:50.28#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.11:25:50.28#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.11:25:50.28$vck44/valo=6,814.99 2006.145.11:25:50.28#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.11:25:50.28#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.11:25:50.28#ibcon#ireg 17 cls_cnt 0 2006.145.11:25:50.28#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.11:25:50.28#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.11:25:50.28#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.11:25:50.30#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.11:25:50.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.11:25:50.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.11:25:50.34#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.11:25:50.34#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.11:25:50.34$vck44/va=6,4 2006.145.11:25:50.34#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.11:25:50.34#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.11:25:50.34#ibcon#ireg 11 cls_cnt 2 2006.145.11:25:50.34#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.11:25:50.40#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.11:25:50.40#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.11:25:50.42#ibcon#[25=AT06-04\r\n] 2006.145.11:25:50.45#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.11:25:50.45#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.11:25:50.45#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.11:25:50.45#ibcon#ireg 7 cls_cnt 0 2006.145.11:25:50.45#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.11:25:50.57#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.11:25:50.57#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.11:25:50.59#ibcon#[25=USB\r\n] 2006.145.11:25:50.62#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.11:25:50.62#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.11:25:50.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.11:25:50.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.11:25:50.62$vck44/valo=7,864.99 2006.145.11:25:50.62#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.11:25:50.62#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.11:25:50.62#ibcon#ireg 17 cls_cnt 0 2006.145.11:25:50.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.11:25:50.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.11:25:50.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.11:25:50.64#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.11:25:50.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.11:25:50.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.11:25:50.68#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.11:25:50.68#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.11:25:50.68$vck44/va=7,4 2006.145.11:25:50.68#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.11:25:50.68#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.11:25:50.68#ibcon#ireg 11 cls_cnt 2 2006.145.11:25:50.68#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.11:25:50.74#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.11:25:50.74#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.11:25:50.76#ibcon#[25=AT07-04\r\n] 2006.145.11:25:50.79#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.11:25:50.79#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.11:25:50.79#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.11:25:50.79#ibcon#ireg 7 cls_cnt 0 2006.145.11:25:50.79#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.11:25:50.91#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.11:25:50.91#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.11:25:50.93#ibcon#[25=USB\r\n] 2006.145.11:25:50.96#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.11:25:50.96#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.11:25:50.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.11:25:50.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.11:25:50.96$vck44/valo=8,884.99 2006.145.11:25:50.96#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.11:25:50.96#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.11:25:50.96#ibcon#ireg 17 cls_cnt 0 2006.145.11:25:50.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.11:25:50.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.11:25:50.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.11:25:50.98#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.11:25:51.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.11:25:51.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.11:25:51.02#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.11:25:51.02#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.11:25:51.02$vck44/va=8,4 2006.145.11:25:51.02#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.11:25:51.02#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.11:25:51.02#ibcon#ireg 11 cls_cnt 2 2006.145.11:25:51.02#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.11:25:51.08#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.11:25:51.08#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.11:25:51.10#ibcon#[25=AT08-04\r\n] 2006.145.11:25:51.13#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.11:25:51.13#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.11:25:51.13#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.11:25:51.13#ibcon#ireg 7 cls_cnt 0 2006.145.11:25:51.13#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.11:25:51.25#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.11:25:51.25#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.11:25:51.27#ibcon#[25=USB\r\n] 2006.145.11:25:51.30#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.11:25:51.30#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.11:25:51.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.11:25:51.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.11:25:51.30$vck44/vblo=1,629.99 2006.145.11:25:51.30#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.11:25:51.30#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.11:25:51.30#ibcon#ireg 17 cls_cnt 0 2006.145.11:25:51.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.11:25:51.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.11:25:51.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.11:25:51.32#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.11:25:51.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.11:25:51.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.11:25:51.36#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.11:25:51.36#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.11:25:51.36$vck44/vb=1,3 2006.145.11:25:51.36#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.11:25:51.36#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.11:25:51.36#ibcon#ireg 11 cls_cnt 2 2006.145.11:25:51.36#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.11:25:51.36#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.11:25:51.36#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.11:25:51.38#ibcon#[27=AT01-03\r\n] 2006.145.11:25:51.41#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.11:25:51.41#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.11:25:51.41#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.11:25:51.41#ibcon#ireg 7 cls_cnt 0 2006.145.11:25:51.41#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.11:25:51.53#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.11:25:51.53#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.11:25:51.55#ibcon#[27=USB\r\n] 2006.145.11:25:51.58#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.11:25:51.58#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.11:25:51.58#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.11:25:51.58#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.11:25:51.58$vck44/vblo=2,634.99 2006.145.11:25:51.58#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.11:25:51.58#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.11:25:51.58#ibcon#ireg 17 cls_cnt 0 2006.145.11:25:51.58#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.11:25:51.58#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.11:25:51.58#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.11:25:51.60#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.11:25:51.64#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.11:25:51.64#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.11:25:51.64#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.11:25:51.64#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.11:25:51.64$vck44/vb=2,4 2006.145.11:25:51.64#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.11:25:51.64#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.11:25:51.64#ibcon#ireg 11 cls_cnt 2 2006.145.11:25:51.64#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.11:25:51.70#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.11:25:51.70#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.11:25:51.72#ibcon#[27=AT02-04\r\n] 2006.145.11:25:51.75#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.11:25:51.75#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.11:25:51.75#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.11:25:51.75#ibcon#ireg 7 cls_cnt 0 2006.145.11:25:51.75#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.11:25:51.87#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.11:25:51.87#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.11:25:51.89#ibcon#[27=USB\r\n] 2006.145.11:25:51.92#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.11:25:51.92#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.11:25:51.92#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.11:25:51.92#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.11:25:51.92$vck44/vblo=3,649.99 2006.145.11:25:51.92#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.11:25:51.92#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.11:25:51.92#ibcon#ireg 17 cls_cnt 0 2006.145.11:25:51.92#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.11:25:51.92#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.11:25:51.92#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.11:25:51.94#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.11:25:51.98#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.11:25:51.98#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.11:25:51.98#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.11:25:51.98#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.11:25:51.98$vck44/vb=3,4 2006.145.11:25:51.98#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.11:25:51.98#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.11:25:51.98#ibcon#ireg 11 cls_cnt 2 2006.145.11:25:51.98#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.11:25:52.04#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.11:25:52.04#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.11:25:52.06#ibcon#[27=AT03-04\r\n] 2006.145.11:25:52.09#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.11:25:52.09#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.11:25:52.09#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.11:25:52.09#ibcon#ireg 7 cls_cnt 0 2006.145.11:25:52.09#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.11:25:52.21#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.11:25:52.21#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.11:25:52.23#ibcon#[27=USB\r\n] 2006.145.11:25:52.26#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.11:25:52.26#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.11:25:52.26#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.11:25:52.26#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.11:25:52.26$vck44/vblo=4,679.99 2006.145.11:25:52.26#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.11:25:52.26#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.11:25:52.26#ibcon#ireg 17 cls_cnt 0 2006.145.11:25:52.26#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.11:25:52.26#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.11:25:52.26#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.11:25:52.28#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.11:25:52.32#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.11:25:52.32#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.11:25:52.32#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.11:25:52.32#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.11:25:52.32$vck44/vb=4,4 2006.145.11:25:52.32#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.11:25:52.32#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.11:25:52.32#ibcon#ireg 11 cls_cnt 2 2006.145.11:25:52.32#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.11:25:52.38#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.11:25:52.38#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.11:25:52.40#ibcon#[27=AT04-04\r\n] 2006.145.11:25:52.43#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.11:25:52.43#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.11:25:52.43#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.11:25:52.43#ibcon#ireg 7 cls_cnt 0 2006.145.11:25:52.43#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.11:25:52.55#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.11:25:52.55#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.11:25:52.57#ibcon#[27=USB\r\n] 2006.145.11:25:52.60#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.11:25:52.60#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.11:25:52.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.11:25:52.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.11:25:52.60$vck44/vblo=5,709.99 2006.145.11:25:52.60#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.11:25:52.60#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.11:25:52.60#ibcon#ireg 17 cls_cnt 0 2006.145.11:25:52.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:25:52.60#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:25:52.60#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:25:52.62#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.11:25:52.66#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:25:52.66#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:25:52.66#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.11:25:52.66#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.11:25:52.66$vck44/vb=5,4 2006.145.11:25:52.66#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.11:25:52.66#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.11:25:52.66#ibcon#ireg 11 cls_cnt 2 2006.145.11:25:52.66#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.11:25:52.72#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.11:25:52.72#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.11:25:52.74#ibcon#[27=AT05-04\r\n] 2006.145.11:25:52.77#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.11:25:52.77#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.11:25:52.77#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.11:25:52.77#ibcon#ireg 7 cls_cnt 0 2006.145.11:25:52.77#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.11:25:52.89#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.11:25:52.89#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.11:25:52.91#ibcon#[27=USB\r\n] 2006.145.11:25:52.94#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.11:25:52.94#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.11:25:52.94#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.11:25:52.94#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.11:25:52.94$vck44/vblo=6,719.99 2006.145.11:25:52.94#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.11:25:52.94#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.11:25:52.94#ibcon#ireg 17 cls_cnt 0 2006.145.11:25:52.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.11:25:52.94#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.11:25:52.94#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.11:25:52.96#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.11:25:53.00#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.11:25:53.00#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.11:25:53.00#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.11:25:53.00#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.11:25:53.00$vck44/vb=6,4 2006.145.11:25:53.00#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.11:25:53.00#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.11:25:53.00#ibcon#ireg 11 cls_cnt 2 2006.145.11:25:53.00#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.11:25:53.06#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.11:25:53.06#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.11:25:53.08#ibcon#[27=AT06-04\r\n] 2006.145.11:25:53.11#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.11:25:53.11#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.11:25:53.11#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.11:25:53.11#ibcon#ireg 7 cls_cnt 0 2006.145.11:25:53.11#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.11:25:53.23#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.11:25:53.23#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.11:25:53.25#ibcon#[27=USB\r\n] 2006.145.11:25:53.28#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.11:25:53.28#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.11:25:53.28#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.11:25:53.28#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.11:25:53.28$vck44/vblo=7,734.99 2006.145.11:25:53.28#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.11:25:53.28#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.11:25:53.28#ibcon#ireg 17 cls_cnt 0 2006.145.11:25:53.28#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.11:25:53.28#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.11:25:53.28#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.11:25:53.30#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.11:25:53.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.11:25:53.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.11:25:53.34#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.11:25:53.34#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.11:25:53.34$vck44/vb=7,4 2006.145.11:25:53.34#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.11:25:53.34#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.11:25:53.34#ibcon#ireg 11 cls_cnt 2 2006.145.11:25:53.34#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.11:25:53.40#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.11:25:53.40#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.11:25:53.42#ibcon#[27=AT07-04\r\n] 2006.145.11:25:53.45#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.11:25:53.45#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.11:25:53.45#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.11:25:53.45#ibcon#ireg 7 cls_cnt 0 2006.145.11:25:53.45#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.11:25:53.57#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.11:25:53.57#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.11:25:53.59#ibcon#[27=USB\r\n] 2006.145.11:25:53.62#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.11:25:53.62#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.11:25:53.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.11:25:53.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.11:25:53.62$vck44/vblo=8,744.99 2006.145.11:25:53.62#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.11:25:53.62#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.11:25:53.62#ibcon#ireg 17 cls_cnt 0 2006.145.11:25:53.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.11:25:53.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.11:25:53.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.11:25:53.64#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.11:25:53.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.11:25:53.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.11:25:53.68#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.11:25:53.68#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.11:25:53.68$vck44/vb=8,4 2006.145.11:25:53.68#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.11:25:53.68#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.11:25:53.68#ibcon#ireg 11 cls_cnt 2 2006.145.11:25:53.68#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.11:25:53.74#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.11:25:53.74#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.11:25:53.76#ibcon#[27=AT08-04\r\n] 2006.145.11:25:53.79#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.11:25:53.79#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.11:25:53.79#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.11:25:53.79#ibcon#ireg 7 cls_cnt 0 2006.145.11:25:53.79#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.11:25:53.91#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.11:25:53.91#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.11:25:53.93#ibcon#[27=USB\r\n] 2006.145.11:25:53.96#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.11:25:53.96#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.11:25:53.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.11:25:53.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.11:25:53.96$vck44/vabw=wide 2006.145.11:25:53.96#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.11:25:53.96#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.11:25:53.96#ibcon#ireg 8 cls_cnt 0 2006.145.11:25:53.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.11:25:53.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.11:25:53.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.11:25:53.98#ibcon#[25=BW32\r\n] 2006.145.11:25:54.01#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.11:25:54.01#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.11:25:54.01#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.11:25:54.01#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.11:25:54.01$vck44/vbbw=wide 2006.145.11:25:54.01#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.11:25:54.01#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.11:25:54.01#ibcon#ireg 8 cls_cnt 0 2006.145.11:25:54.01#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.11:25:54.08#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.11:25:54.08#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.11:25:54.10#ibcon#[27=BW32\r\n] 2006.145.11:25:54.13#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.11:25:54.13#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.11:25:54.13#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.11:25:54.13#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.11:25:54.13$setupk4/ifdk4 2006.145.11:25:54.13$ifdk4/lo= 2006.145.11:25:54.13$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.11:25:54.13$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.11:25:54.13$ifdk4/patch= 2006.145.11:25:54.13$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.11:25:54.13$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.11:25:54.13$setupk4/!*+20s 2006.145.11:25:54.65#abcon#<5=/05 2.1 3.5 16.59 681020.3\r\n> 2006.145.11:25:54.67#abcon#{5=INTERFACE CLEAR} 2006.145.11:25:54.73#abcon#[5=S1D000X0/0*\r\n] 2006.145.11:26:04.82#abcon#<5=/05 2.1 3.5 16.59 681020.2\r\n> 2006.145.11:26:04.84#abcon#{5=INTERFACE CLEAR} 2006.145.11:26:04.90#abcon#[5=S1D000X0/0*\r\n] 2006.145.11:26:08.14#trakl#Source acquired 2006.145.11:26:08.64$setupk4/"tpicd 2006.145.11:26:08.64$setupk4/echo=off 2006.145.11:26:08.64$setupk4/xlog=off 2006.145.11:26:08.64:!2006.145.11:26:24 2006.145.11:26:10.14#flagr#flagr/antenna,acquired 2006.145.11:26:24.00:preob 2006.145.11:26:24.14/onsource/TRACKING 2006.145.11:26:24.14:!2006.145.11:26:34 2006.145.11:26:34.00:"tape 2006.145.11:26:34.00:"st=record 2006.145.11:26:34.00:data_valid=on 2006.145.11:26:34.00:midob 2006.145.11:26:34.14/onsource/TRACKING 2006.145.11:26:34.14/wx/16.59,1020.3,68 2006.145.11:26:34.25/cable/+6.5458E-03 2006.145.11:26:35.34/va/01,08,usb,yes,29,30 2006.145.11:26:35.34/va/02,07,usb,yes,30,31 2006.145.11:26:35.34/va/03,08,usb,yes,28,29 2006.145.11:26:35.34/va/04,07,usb,yes,32,33 2006.145.11:26:35.34/va/05,04,usb,yes,27,28 2006.145.11:26:35.34/va/06,04,usb,yes,31,31 2006.145.11:26:35.34/va/07,04,usb,yes,31,32 2006.145.11:26:35.34/va/08,04,usb,yes,27,32 2006.145.11:26:35.57/valo/01,524.99,yes,locked 2006.145.11:26:35.57/valo/02,534.99,yes,locked 2006.145.11:26:35.57/valo/03,564.99,yes,locked 2006.145.11:26:35.57/valo/04,624.99,yes,locked 2006.145.11:26:35.57/valo/05,734.99,yes,locked 2006.145.11:26:35.57/valo/06,814.99,yes,locked 2006.145.11:26:35.57/valo/07,864.99,yes,locked 2006.145.11:26:35.57/valo/08,884.99,yes,locked 2006.145.11:26:36.66/vb/01,03,usb,yes,36,33 2006.145.11:26:36.66/vb/02,04,usb,yes,31,31 2006.145.11:26:36.66/vb/03,04,usb,yes,28,31 2006.145.11:26:36.66/vb/04,04,usb,yes,32,31 2006.145.11:26:36.66/vb/05,04,usb,yes,25,27 2006.145.11:26:36.66/vb/06,04,usb,yes,29,26 2006.145.11:26:36.66/vb/07,04,usb,yes,29,29 2006.145.11:26:36.66/vb/08,04,usb,yes,27,30 2006.145.11:26:36.90/vblo/01,629.99,yes,locked 2006.145.11:26:36.90/vblo/02,634.99,yes,locked 2006.145.11:26:36.90/vblo/03,649.99,yes,locked 2006.145.11:26:36.90/vblo/04,679.99,yes,locked 2006.145.11:26:36.90/vblo/05,709.99,yes,locked 2006.145.11:26:36.90/vblo/06,719.99,yes,locked 2006.145.11:26:36.90/vblo/07,734.99,yes,locked 2006.145.11:26:36.90/vblo/08,744.99,yes,locked 2006.145.11:26:37.05/vabw/8 2006.145.11:26:37.20/vbbw/8 2006.145.11:26:37.29/xfe/off,on,15.0 2006.145.11:26:37.68/ifatt/23,28,28,28 2006.145.11:26:38.07/fmout-gps/S +5.4E-08 2006.145.11:26:38.11:!2006.145.11:28:14 2006.145.11:28:14.01:data_valid=off 2006.145.11:28:14.02:"et 2006.145.11:28:14.02:!+3s 2006.145.11:28:17.03:"tape 2006.145.11:28:17.04:postob 2006.145.11:28:17.20/cable/+6.5451E-03 2006.145.11:28:17.21/wx/16.56,1020.3,68 2006.145.11:28:17.29/fmout-gps/S +5.4E-08 2006.145.11:28:17.29:scan_name=145-1129,jd0605,80 2006.145.11:28:17.29:source=3c274,123049.42,122328.0,2000.0,cw 2006.145.11:28:19.13#flagr#flagr/antenna,new-source 2006.145.11:28:19.14:checkk5 2006.145.11:28:19.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.11:28:20.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.11:28:20.45/chk_autoobs//k5ts3/ autoobs is running! 2006.145.11:28:20.88/chk_autoobs//k5ts4/ autoobs is running! 2006.145.11:28:21.31/chk_obsdata//k5ts1/T1451126??a.dat file size is correct (nominal:400MB, actual:400MB). 2006.145.11:28:21.77/chk_obsdata//k5ts2/T1451126??b.dat file size is correct (nominal:400MB, actual:400MB). 2006.145.11:28:22.21/chk_obsdata//k5ts3/T1451126??c.dat file size is correct (nominal:400MB, actual:400MB). 2006.145.11:28:22.66/chk_obsdata//k5ts4/T1451126??d.dat file size is correct (nominal:400MB, actual:400MB). 2006.145.11:28:23.39/k5log//k5ts1_log_newline 2006.145.11:28:24.13/k5log//k5ts2_log_newline 2006.145.11:28:24.87/k5log//k5ts3_log_newline 2006.145.11:28:25.63/k5log//k5ts4_log_newline 2006.145.11:28:25.65/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.11:28:25.65:setupk4=1 2006.145.11:28:25.65$setupk4/echo=on 2006.145.11:28:25.65$setupk4/pcalon 2006.145.11:28:25.65$pcalon/"no phase cal control is implemented here 2006.145.11:28:25.65$setupk4/"tpicd=stop 2006.145.11:28:25.65$setupk4/"rec=synch_on 2006.145.11:28:25.65$setupk4/"rec_mode=128 2006.145.11:28:25.65$setupk4/!* 2006.145.11:28:25.65$setupk4/recpk4 2006.145.11:28:25.65$recpk4/recpatch= 2006.145.11:28:25.66$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.11:28:25.66$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.11:28:25.66$setupk4/vck44 2006.145.11:28:25.66$vck44/valo=1,524.99 2006.145.11:28:25.66#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.11:28:25.66#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.11:28:25.66#ibcon#ireg 17 cls_cnt 0 2006.145.11:28:25.66#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:28:25.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:28:25.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:28:25.70#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.11:28:25.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:28:25.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:28:25.74#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.11:28:25.74#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.11:28:25.74$vck44/va=1,8 2006.145.11:28:25.74#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.11:28:25.74#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.11:28:25.74#ibcon#ireg 11 cls_cnt 2 2006.145.11:28:25.74#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:28:25.74#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:28:25.74#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:28:25.76#ibcon#[25=AT01-08\r\n] 2006.145.11:28:25.79#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:28:25.79#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:28:25.79#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.11:28:25.79#ibcon#ireg 7 cls_cnt 0 2006.145.11:28:25.79#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:28:25.91#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:28:25.91#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:28:25.93#ibcon#[25=USB\r\n] 2006.145.11:28:25.98#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:28:25.98#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:28:25.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.11:28:25.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.11:28:25.98$vck44/valo=2,534.99 2006.145.11:28:25.98#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.11:28:25.98#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.11:28:25.98#ibcon#ireg 17 cls_cnt 0 2006.145.11:28:25.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:28:25.98#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:28:25.98#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:28:25.99#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.11:28:26.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:28:26.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:28:26.03#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.11:28:26.03#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.11:28:26.03$vck44/va=2,7 2006.145.11:28:26.03#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.11:28:26.03#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.11:28:26.03#ibcon#ireg 11 cls_cnt 2 2006.145.11:28:26.03#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:28:26.10#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:28:26.10#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:28:26.12#ibcon#[25=AT02-07\r\n] 2006.145.11:28:26.15#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:28:26.15#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:28:26.15#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.11:28:26.15#ibcon#ireg 7 cls_cnt 0 2006.145.11:28:26.15#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:28:26.27#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:28:26.27#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:28:26.29#ibcon#[25=USB\r\n] 2006.145.11:28:26.32#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:28:26.32#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:28:26.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.11:28:26.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.11:28:26.32$vck44/valo=3,564.99 2006.145.11:28:26.32#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.11:28:26.32#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.11:28:26.32#ibcon#ireg 17 cls_cnt 0 2006.145.11:28:26.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:28:26.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:28:26.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:28:26.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.11:28:26.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:28:26.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:28:26.38#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.11:28:26.38#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.11:28:26.38$vck44/va=3,8 2006.145.11:28:26.38#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.11:28:26.38#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.11:28:26.38#ibcon#ireg 11 cls_cnt 2 2006.145.11:28:26.38#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:28:26.44#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:28:26.44#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:28:26.46#ibcon#[25=AT03-08\r\n] 2006.145.11:28:26.49#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:28:26.49#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:28:26.49#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.11:28:26.49#ibcon#ireg 7 cls_cnt 0 2006.145.11:28:26.49#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:28:26.61#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:28:26.61#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:28:26.63#ibcon#[25=USB\r\n] 2006.145.11:28:26.66#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:28:26.66#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:28:26.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.11:28:26.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.11:28:26.66$vck44/valo=4,624.99 2006.145.11:28:26.66#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.11:28:26.66#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.11:28:26.66#ibcon#ireg 17 cls_cnt 0 2006.145.11:28:26.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:28:26.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:28:26.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:28:26.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.11:28:26.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:28:26.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:28:26.72#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.11:28:26.72#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.11:28:26.72$vck44/va=4,7 2006.145.11:28:26.72#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.11:28:26.72#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.11:28:26.72#ibcon#ireg 11 cls_cnt 2 2006.145.11:28:26.72#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.11:28:26.78#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.11:28:26.78#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.11:28:26.80#ibcon#[25=AT04-07\r\n] 2006.145.11:28:26.83#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.11:28:26.83#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.11:28:26.83#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.11:28:26.83#ibcon#ireg 7 cls_cnt 0 2006.145.11:28:26.83#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.11:28:26.95#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.11:28:26.95#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.11:28:26.97#ibcon#[25=USB\r\n] 2006.145.11:28:27.00#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.11:28:27.00#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.11:28:27.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.11:28:27.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.11:28:27.00$vck44/valo=5,734.99 2006.145.11:28:27.00#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.11:28:27.00#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.11:28:27.00#ibcon#ireg 17 cls_cnt 0 2006.145.11:28:27.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:28:27.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:28:27.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:28:27.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.11:28:27.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:28:27.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:28:27.06#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.11:28:27.06#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.11:28:27.06$vck44/va=5,4 2006.145.11:28:27.06#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.11:28:27.06#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.11:28:27.06#ibcon#ireg 11 cls_cnt 2 2006.145.11:28:27.06#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.11:28:27.12#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.11:28:27.12#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.11:28:27.14#ibcon#[25=AT05-04\r\n] 2006.145.11:28:27.17#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.11:28:27.17#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.11:28:27.17#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.11:28:27.17#ibcon#ireg 7 cls_cnt 0 2006.145.11:28:27.17#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.11:28:27.20#abcon#<5=/05 2.1 3.6 16.56 681020.3\r\n> 2006.145.11:28:27.23#abcon#{5=INTERFACE CLEAR} 2006.145.11:28:27.28#abcon#[5=S1D000X0/0*\r\n] 2006.145.11:28:27.30#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.11:28:27.30#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.11:28:27.32#ibcon#[25=USB\r\n] 2006.145.11:28:27.35#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.11:28:27.35#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.11:28:27.35#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.11:28:27.35#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.11:28:27.35$vck44/valo=6,814.99 2006.145.11:28:27.35#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.11:28:27.35#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.11:28:27.35#ibcon#ireg 17 cls_cnt 0 2006.145.11:28:27.35#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.11:28:27.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.11:28:27.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.11:28:27.37#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.11:28:27.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.11:28:27.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.11:28:27.41#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.11:28:27.41#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.11:28:27.41$vck44/va=6,4 2006.145.11:28:27.41#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.11:28:27.41#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.11:28:27.41#ibcon#ireg 11 cls_cnt 2 2006.145.11:28:27.41#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.11:28:27.47#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.11:28:27.47#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.11:28:27.49#ibcon#[25=AT06-04\r\n] 2006.145.11:28:27.52#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.11:28:27.52#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.11:28:27.52#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.11:28:27.52#ibcon#ireg 7 cls_cnt 0 2006.145.11:28:27.52#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.11:28:27.64#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.11:28:27.64#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.11:28:27.66#ibcon#[25=USB\r\n] 2006.145.11:28:27.69#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.11:28:27.69#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.11:28:27.69#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.11:28:27.69#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.11:28:27.69$vck44/valo=7,864.99 2006.145.11:28:27.69#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.11:28:27.69#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.11:28:27.69#ibcon#ireg 17 cls_cnt 0 2006.145.11:28:27.69#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.11:28:27.69#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.11:28:27.69#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.11:28:27.71#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.11:28:27.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.11:28:27.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.11:28:27.75#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.11:28:27.75#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.11:28:27.75$vck44/va=7,4 2006.145.11:28:27.75#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.11:28:27.75#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.11:28:27.75#ibcon#ireg 11 cls_cnt 2 2006.145.11:28:27.75#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:28:27.81#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:28:27.81#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:28:27.83#ibcon#[25=AT07-04\r\n] 2006.145.11:28:27.86#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:28:27.86#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:28:27.86#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.11:28:27.86#ibcon#ireg 7 cls_cnt 0 2006.145.11:28:27.86#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:28:27.98#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:28:27.98#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:28:28.00#ibcon#[25=USB\r\n] 2006.145.11:28:28.03#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:28:28.03#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:28:28.03#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.11:28:28.03#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.11:28:28.03$vck44/valo=8,884.99 2006.145.11:28:28.03#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.11:28:28.03#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.11:28:28.03#ibcon#ireg 17 cls_cnt 0 2006.145.11:28:28.03#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:28:28.03#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:28:28.03#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:28:28.05#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.11:28:28.09#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:28:28.09#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:28:28.09#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.11:28:28.09#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.11:28:28.09$vck44/va=8,4 2006.145.11:28:28.09#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.11:28:28.09#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.11:28:28.09#ibcon#ireg 11 cls_cnt 2 2006.145.11:28:28.09#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.11:28:28.15#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.11:28:28.15#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.11:28:28.17#ibcon#[25=AT08-04\r\n] 2006.145.11:28:28.20#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.11:28:28.20#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.11:28:28.20#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.11:28:28.20#ibcon#ireg 7 cls_cnt 0 2006.145.11:28:28.20#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.11:28:28.32#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.11:28:28.32#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.11:28:28.34#ibcon#[25=USB\r\n] 2006.145.11:28:28.37#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.11:28:28.37#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.11:28:28.37#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.11:28:28.37#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.11:28:28.37$vck44/vblo=1,629.99 2006.145.11:28:28.37#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.11:28:28.37#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.11:28:28.37#ibcon#ireg 17 cls_cnt 0 2006.145.11:28:28.37#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:28:28.37#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:28:28.37#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:28:28.39#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.11:28:28.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:28:28.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:28:28.43#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.11:28:28.43#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.11:28:28.43$vck44/vb=1,3 2006.145.11:28:28.43#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.11:28:28.43#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.11:28:28.43#ibcon#ireg 11 cls_cnt 2 2006.145.11:28:28.43#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:28:28.43#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:28:28.43#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:28:28.45#ibcon#[27=AT01-03\r\n] 2006.145.11:28:28.48#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:28:28.48#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:28:28.48#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.11:28:28.48#ibcon#ireg 7 cls_cnt 0 2006.145.11:28:28.48#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:28:28.60#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:28:28.60#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:28:28.62#ibcon#[27=USB\r\n] 2006.145.11:28:28.65#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:28:28.65#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:28:28.65#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.11:28:28.65#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.11:28:28.65$vck44/vblo=2,634.99 2006.145.11:28:28.65#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.11:28:28.65#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.11:28:28.65#ibcon#ireg 17 cls_cnt 0 2006.145.11:28:28.65#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:28:28.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:28:28.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:28:28.67#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.11:28:28.71#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:28:28.71#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:28:28.71#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.11:28:28.71#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.11:28:28.71$vck44/vb=2,4 2006.145.11:28:28.71#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.11:28:28.71#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.11:28:28.71#ibcon#ireg 11 cls_cnt 2 2006.145.11:28:28.71#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:28:28.77#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:28:28.77#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:28:28.79#ibcon#[27=AT02-04\r\n] 2006.145.11:28:28.82#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:28:28.82#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:28:28.82#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.11:28:28.82#ibcon#ireg 7 cls_cnt 0 2006.145.11:28:28.82#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:28:28.94#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:28:28.94#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:28:28.96#ibcon#[27=USB\r\n] 2006.145.11:28:28.99#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:28:28.99#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:28:28.99#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.11:28:28.99#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.11:28:28.99$vck44/vblo=3,649.99 2006.145.11:28:28.99#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.11:28:28.99#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.11:28:28.99#ibcon#ireg 17 cls_cnt 0 2006.145.11:28:28.99#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:28:28.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:28:28.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:28:29.01#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.11:28:29.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:28:29.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:28:29.05#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.11:28:29.05#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.11:28:29.05$vck44/vb=3,4 2006.145.11:28:29.05#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.11:28:29.05#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.11:28:29.05#ibcon#ireg 11 cls_cnt 2 2006.145.11:28:29.05#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:28:29.11#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:28:29.11#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:28:29.13#ibcon#[27=AT03-04\r\n] 2006.145.11:28:29.16#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:28:29.16#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:28:29.16#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.11:28:29.16#ibcon#ireg 7 cls_cnt 0 2006.145.11:28:29.16#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:28:29.28#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:28:29.28#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:28:29.30#ibcon#[27=USB\r\n] 2006.145.11:28:29.33#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:28:29.33#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:28:29.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.11:28:29.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.11:28:29.33$vck44/vblo=4,679.99 2006.145.11:28:29.33#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.11:28:29.33#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.11:28:29.33#ibcon#ireg 17 cls_cnt 0 2006.145.11:28:29.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:28:29.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:28:29.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:28:29.35#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.11:28:29.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:28:29.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:28:29.39#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.11:28:29.39#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.11:28:29.39$vck44/vb=4,4 2006.145.11:28:29.39#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.11:28:29.39#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.11:28:29.39#ibcon#ireg 11 cls_cnt 2 2006.145.11:28:29.39#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.11:28:29.45#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.11:28:29.45#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.11:28:29.47#ibcon#[27=AT04-04\r\n] 2006.145.11:28:29.50#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.11:28:29.50#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.11:28:29.50#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.11:28:29.50#ibcon#ireg 7 cls_cnt 0 2006.145.11:28:29.50#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.11:28:29.62#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.11:28:29.62#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.11:28:29.64#ibcon#[27=USB\r\n] 2006.145.11:28:29.67#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.11:28:29.67#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.11:28:29.67#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.11:28:29.67#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.11:28:29.67$vck44/vblo=5,709.99 2006.145.11:28:29.67#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.11:28:29.67#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.11:28:29.67#ibcon#ireg 17 cls_cnt 0 2006.145.11:28:29.67#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:28:29.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:28:29.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:28:29.69#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.11:28:29.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:28:29.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:28:29.73#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.11:28:29.73#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.11:28:29.73$vck44/vb=5,4 2006.145.11:28:29.73#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.11:28:29.73#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.11:28:29.73#ibcon#ireg 11 cls_cnt 2 2006.145.11:28:29.73#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.11:28:29.79#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.11:28:29.79#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.11:28:29.81#ibcon#[27=AT05-04\r\n] 2006.145.11:28:29.84#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.11:28:29.84#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.11:28:29.84#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.11:28:29.84#ibcon#ireg 7 cls_cnt 0 2006.145.11:28:29.84#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.11:28:29.96#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.11:28:29.96#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.11:28:29.98#ibcon#[27=USB\r\n] 2006.145.11:28:30.01#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.11:28:30.01#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.11:28:30.01#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.11:28:30.01#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.11:28:30.01$vck44/vblo=6,719.99 2006.145.11:28:30.01#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.11:28:30.01#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.11:28:30.01#ibcon#ireg 17 cls_cnt 0 2006.145.11:28:30.01#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:28:30.01#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:28:30.01#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:28:30.03#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.11:28:30.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:28:30.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:28:30.07#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.11:28:30.07#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.11:28:30.07$vck44/vb=6,4 2006.145.11:28:30.07#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.11:28:30.07#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.11:28:30.07#ibcon#ireg 11 cls_cnt 2 2006.145.11:28:30.07#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.11:28:30.13#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.11:28:30.13#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.11:28:30.15#ibcon#[27=AT06-04\r\n] 2006.145.11:28:30.18#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.11:28:30.18#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.11:28:30.18#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.11:28:30.18#ibcon#ireg 7 cls_cnt 0 2006.145.11:28:30.18#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.11:28:30.30#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.11:28:30.30#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.11:28:30.32#ibcon#[27=USB\r\n] 2006.145.11:28:30.37#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.11:28:30.37#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.11:28:30.37#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.11:28:30.37#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.11:28:30.37$vck44/vblo=7,734.99 2006.145.11:28:30.37#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.11:28:30.37#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.11:28:30.37#ibcon#ireg 17 cls_cnt 0 2006.145.11:28:30.37#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.11:28:30.37#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.11:28:30.37#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.11:28:30.38#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.11:28:30.42#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.11:28:30.42#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.11:28:30.42#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.11:28:30.42#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.11:28:30.42$vck44/vb=7,4 2006.145.11:28:30.42#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.11:28:30.42#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.11:28:30.42#ibcon#ireg 11 cls_cnt 2 2006.145.11:28:30.42#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.11:28:30.49#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.11:28:30.49#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.11:28:30.51#ibcon#[27=AT07-04\r\n] 2006.145.11:28:30.54#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.11:28:30.54#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.11:28:30.54#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.11:28:30.54#ibcon#ireg 7 cls_cnt 0 2006.145.11:28:30.54#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.11:28:30.66#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.11:28:30.66#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.11:28:30.68#ibcon#[27=USB\r\n] 2006.145.11:28:30.71#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.11:28:30.71#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.11:28:30.71#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.11:28:30.71#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.11:28:30.71$vck44/vblo=8,744.99 2006.145.11:28:30.71#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.11:28:30.71#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.11:28:30.71#ibcon#ireg 17 cls_cnt 0 2006.145.11:28:30.71#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.11:28:30.71#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.11:28:30.71#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.11:28:30.73#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.11:28:30.77#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.11:28:30.77#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.11:28:30.77#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.11:28:30.77#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.11:28:30.77$vck44/vb=8,4 2006.145.11:28:30.77#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.11:28:30.77#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.11:28:30.77#ibcon#ireg 11 cls_cnt 2 2006.145.11:28:30.77#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:28:30.83#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:28:30.83#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:28:30.85#ibcon#[27=AT08-04\r\n] 2006.145.11:28:30.88#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:28:30.88#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:28:30.88#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.11:28:30.88#ibcon#ireg 7 cls_cnt 0 2006.145.11:28:30.88#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:28:31.00#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:28:31.00#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:28:31.02#ibcon#[27=USB\r\n] 2006.145.11:28:31.05#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:28:31.05#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:28:31.05#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.11:28:31.05#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.11:28:31.05$vck44/vabw=wide 2006.145.11:28:31.05#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.11:28:31.05#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.11:28:31.05#ibcon#ireg 8 cls_cnt 0 2006.145.11:28:31.05#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:28:31.05#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:28:31.05#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:28:31.07#ibcon#[25=BW32\r\n] 2006.145.11:28:31.10#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:28:31.10#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:28:31.10#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.11:28:31.10#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.11:28:31.10$vck44/vbbw=wide 2006.145.11:28:31.10#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.11:28:31.10#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.11:28:31.10#ibcon#ireg 8 cls_cnt 0 2006.145.11:28:31.10#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:28:31.17#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:28:31.17#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:28:31.19#ibcon#[27=BW32\r\n] 2006.145.11:28:31.22#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:28:31.22#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:28:31.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.11:28:31.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.11:28:31.22$setupk4/ifdk4 2006.145.11:28:31.22$ifdk4/lo= 2006.145.11:28:31.22$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.11:28:31.22$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.11:28:31.22$ifdk4/patch= 2006.145.11:28:31.22$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.11:28:31.22$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.11:28:31.22$setupk4/!*+20s 2006.145.11:28:37.37#abcon#<5=/05 2.1 3.5 16.56 681020.3\r\n> 2006.145.11:28:37.39#abcon#{5=INTERFACE CLEAR} 2006.145.11:28:37.45#abcon#[5=S1D000X0/0*\r\n] 2006.145.11:28:38.13#trakl#Source acquired 2006.145.11:28:38.13#flagr#flagr/antenna,acquired 2006.145.11:28:45.66$setupk4/"tpicd 2006.145.11:28:45.66$setupk4/echo=off 2006.145.11:28:45.66$setupk4/xlog=off 2006.145.11:28:45.66:!2006.145.11:29:30 2006.145.11:29:30.00:preob 2006.145.11:29:30.14/onsource/TRACKING 2006.145.11:29:30.14:!2006.145.11:29:40 2006.145.11:29:40.00:"tape 2006.145.11:29:40.00:"st=record 2006.145.11:29:40.00:data_valid=on 2006.145.11:29:40.00:midob 2006.145.11:29:41.14/onsource/TRACKING 2006.145.11:29:41.14/wx/16.55,1020.2,68 2006.145.11:29:41.29/cable/+6.5451E-03 2006.145.11:29:42.38/va/01,08,usb,yes,31,33 2006.145.11:29:42.38/va/02,07,usb,yes,33,34 2006.145.11:29:42.38/va/03,08,usb,yes,30,31 2006.145.11:29:42.38/va/04,07,usb,yes,34,36 2006.145.11:29:42.38/va/05,04,usb,yes,30,30 2006.145.11:29:42.38/va/06,04,usb,yes,33,33 2006.145.11:29:42.38/va/07,04,usb,yes,33,35 2006.145.11:29:42.38/va/08,04,usb,yes,28,34 2006.145.11:29:42.61/valo/01,524.99,yes,locked 2006.145.11:29:42.61/valo/02,534.99,yes,locked 2006.145.11:29:42.61/valo/03,564.99,yes,locked 2006.145.11:29:42.61/valo/04,624.99,yes,locked 2006.145.11:29:42.61/valo/05,734.99,yes,locked 2006.145.11:29:42.61/valo/06,814.99,yes,locked 2006.145.11:29:42.61/valo/07,864.99,yes,locked 2006.145.11:29:42.61/valo/08,884.99,yes,locked 2006.145.11:29:43.70/vb/01,03,usb,yes,44,41 2006.145.11:29:43.70/vb/02,04,usb,yes,39,38 2006.145.11:29:43.70/vb/03,04,usb,yes,35,39 2006.145.11:29:43.70/vb/04,04,usb,yes,40,39 2006.145.11:29:43.70/vb/05,04,usb,yes,31,34 2006.145.11:29:43.70/vb/06,04,usb,yes,36,32 2006.145.11:29:43.70/vb/07,04,usb,yes,36,36 2006.145.11:29:43.70/vb/08,04,usb,yes,33,37 2006.145.11:29:43.93/vblo/01,629.99,yes,locked 2006.145.11:29:43.93/vblo/02,634.99,yes,locked 2006.145.11:29:43.93/vblo/03,649.99,yes,locked 2006.145.11:29:43.93/vblo/04,679.99,yes,locked 2006.145.11:29:43.93/vblo/05,709.99,yes,locked 2006.145.11:29:43.93/vblo/06,719.99,yes,locked 2006.145.11:29:43.93/vblo/07,734.99,yes,locked 2006.145.11:29:43.93/vblo/08,744.99,yes,locked 2006.145.11:29:44.08/vabw/8 2006.145.11:29:44.23/vbbw/8 2006.145.11:29:44.32/xfe/off,on,14.7 2006.145.11:29:44.72/ifatt/23,28,28,28 2006.145.11:29:45.07/fmout-gps/S +5.4E-08 2006.145.11:29:45.15:!2006.145.11:31:00 2006.145.11:31:00.01:data_valid=off 2006.145.11:31:00.02:"et 2006.145.11:31:00.02:!+3s 2006.145.11:31:03.03:"tape 2006.145.11:31:03.04:postob 2006.145.11:31:03.12/cable/+6.5450E-03 2006.145.11:31:03.13/wx/16.54,1020.3,69 2006.145.11:31:03.18/fmout-gps/S +5.3E-08 2006.145.11:31:03.19:scan_name=145-1137,jd0605,40 2006.145.11:31:03.19:source=1424-418,142756.30,-420619.4,2000.0,cw 2006.145.11:31:04.14#flagr#flagr/antenna,new-source 2006.145.11:31:04.15:checkk5 2006.145.11:31:04.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.11:31:05.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.11:31:05.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.11:31:05.91/chk_autoobs//k5ts4/ autoobs is running! 2006.145.11:31:06.33/chk_obsdata//k5ts1/T1451129??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.11:31:06.77/chk_obsdata//k5ts2/T1451129??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.11:31:07.22/chk_obsdata//k5ts3/T1451129??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.11:31:07.66/chk_obsdata//k5ts4/T1451129??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.11:31:08.41/k5log//k5ts1_log_newline 2006.145.11:31:09.16/k5log//k5ts2_log_newline 2006.145.11:31:09.92/k5log//k5ts3_log_newline 2006.145.11:31:10.67/k5log//k5ts4_log_newline 2006.145.11:31:10.69/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.11:31:10.69:setupk4=1 2006.145.11:31:10.69$setupk4/echo=on 2006.145.11:31:10.69$setupk4/pcalon 2006.145.11:31:10.69$pcalon/"no phase cal control is implemented here 2006.145.11:31:10.69$setupk4/"tpicd=stop 2006.145.11:31:10.69$setupk4/"rec=synch_on 2006.145.11:31:10.69$setupk4/"rec_mode=128 2006.145.11:31:10.69$setupk4/!* 2006.145.11:31:10.69$setupk4/recpk4 2006.145.11:31:10.69$recpk4/recpatch= 2006.145.11:31:10.70$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.11:31:10.70$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.11:31:10.70$setupk4/vck44 2006.145.11:31:10.70$vck44/valo=1,524.99 2006.145.11:31:10.70#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.11:31:10.70#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.11:31:10.70#ibcon#ireg 17 cls_cnt 0 2006.145.11:31:10.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.11:31:10.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.11:31:10.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.11:31:10.74#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.11:31:10.78#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.11:31:10.78#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.11:31:10.78#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.11:31:10.78#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.11:31:10.78$vck44/va=1,8 2006.145.11:31:10.78#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.11:31:10.78#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.11:31:10.78#ibcon#ireg 11 cls_cnt 2 2006.145.11:31:10.78#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.11:31:10.78#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.11:31:10.78#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.11:31:10.80#ibcon#[25=AT01-08\r\n] 2006.145.11:31:10.83#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.11:31:10.83#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.11:31:10.83#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.11:31:10.83#ibcon#ireg 7 cls_cnt 0 2006.145.11:31:10.83#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.11:31:10.95#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.11:31:10.95#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.11:31:10.97#ibcon#[25=USB\r\n] 2006.145.11:31:11.00#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.11:31:11.00#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.11:31:11.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.11:31:11.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.11:31:11.00$vck44/valo=2,534.99 2006.145.11:31:11.00#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.11:31:11.00#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.11:31:11.00#ibcon#ireg 17 cls_cnt 0 2006.145.11:31:11.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.11:31:11.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.11:31:11.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.11:31:11.04#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.11:31:11.08#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.11:31:11.08#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.11:31:11.08#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.11:31:11.08#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.11:31:11.08$vck44/va=2,7 2006.145.11:31:11.08#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.11:31:11.08#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.11:31:11.08#ibcon#ireg 11 cls_cnt 2 2006.145.11:31:11.08#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.11:31:11.12#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.11:31:11.12#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.11:31:11.14#ibcon#[25=AT02-07\r\n] 2006.145.11:31:11.17#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.11:31:11.17#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.11:31:11.17#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.11:31:11.17#ibcon#ireg 7 cls_cnt 0 2006.145.11:31:11.17#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.11:31:11.29#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.11:31:11.29#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.11:31:11.31#ibcon#[25=USB\r\n] 2006.145.11:31:11.34#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.11:31:11.34#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.11:31:11.34#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.11:31:11.34#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.11:31:11.34$vck44/valo=3,564.99 2006.145.11:31:11.34#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.11:31:11.34#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.11:31:11.34#ibcon#ireg 17 cls_cnt 0 2006.145.11:31:11.34#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.11:31:11.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.11:31:11.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.11:31:11.36#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.11:31:11.40#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.11:31:11.40#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.11:31:11.40#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.11:31:11.40#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.11:31:11.40$vck44/va=3,8 2006.145.11:31:11.40#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.11:31:11.40#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.11:31:11.40#ibcon#ireg 11 cls_cnt 2 2006.145.11:31:11.40#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.11:31:11.46#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.11:31:11.46#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.11:31:11.48#ibcon#[25=AT03-08\r\n] 2006.145.11:31:11.51#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.11:31:11.51#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.11:31:11.51#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.11:31:11.51#ibcon#ireg 7 cls_cnt 0 2006.145.11:31:11.51#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.11:31:11.63#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.11:31:11.63#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.11:31:11.65#ibcon#[25=USB\r\n] 2006.145.11:31:11.68#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.11:31:11.68#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.11:31:11.68#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.11:31:11.68#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.11:31:11.68$vck44/valo=4,624.99 2006.145.11:31:11.68#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.11:31:11.68#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.11:31:11.68#ibcon#ireg 17 cls_cnt 0 2006.145.11:31:11.68#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.11:31:11.68#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.11:31:11.68#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.11:31:11.70#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.11:31:11.74#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.11:31:11.74#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.11:31:11.74#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.11:31:11.74#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.11:31:11.74$vck44/va=4,7 2006.145.11:31:11.74#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.11:31:11.74#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.11:31:11.74#ibcon#ireg 11 cls_cnt 2 2006.145.11:31:11.74#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.11:31:11.80#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.11:31:11.80#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.11:31:11.82#ibcon#[25=AT04-07\r\n] 2006.145.11:31:11.85#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.11:31:11.85#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.11:31:11.85#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.11:31:11.85#ibcon#ireg 7 cls_cnt 0 2006.145.11:31:11.85#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.11:31:11.98#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.11:31:11.98#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.11:31:12.00#ibcon#[25=USB\r\n] 2006.145.11:31:12.03#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.11:31:12.03#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.11:31:12.03#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.11:31:12.03#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.11:31:12.03$vck44/valo=5,734.99 2006.145.11:31:12.03#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.11:31:12.03#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.11:31:12.03#ibcon#ireg 17 cls_cnt 0 2006.145.11:31:12.03#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.11:31:12.03#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.11:31:12.03#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.11:31:12.05#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.11:31:12.09#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.11:31:12.09#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.11:31:12.09#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.11:31:12.09#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.11:31:12.09$vck44/va=5,4 2006.145.11:31:12.09#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.11:31:12.09#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.11:31:12.09#ibcon#ireg 11 cls_cnt 2 2006.145.11:31:12.09#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.11:31:12.15#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.11:31:12.15#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.11:31:12.18#ibcon#[25=AT05-04\r\n] 2006.145.11:31:12.21#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.11:31:12.21#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.11:31:12.21#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.11:31:12.21#ibcon#ireg 7 cls_cnt 0 2006.145.11:31:12.21#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.11:31:12.33#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.11:31:12.33#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.11:31:12.35#ibcon#[25=USB\r\n] 2006.145.11:31:12.38#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.11:31:12.38#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.11:31:12.38#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.11:31:12.38#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.11:31:12.38$vck44/valo=6,814.99 2006.145.11:31:12.38#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.11:31:12.38#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.11:31:12.38#ibcon#ireg 17 cls_cnt 0 2006.145.11:31:12.38#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.11:31:12.38#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.11:31:12.38#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.11:31:12.40#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.11:31:12.44#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.11:31:12.44#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.11:31:12.44#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.11:31:12.44#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.11:31:12.44$vck44/va=6,4 2006.145.11:31:12.44#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.11:31:12.44#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.11:31:12.44#ibcon#ireg 11 cls_cnt 2 2006.145.11:31:12.44#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.11:31:12.50#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.11:31:12.50#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.11:31:12.52#ibcon#[25=AT06-04\r\n] 2006.145.11:31:12.55#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.11:31:12.55#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.11:31:12.55#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.11:31:12.55#ibcon#ireg 7 cls_cnt 0 2006.145.11:31:12.55#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.11:31:12.67#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.11:31:12.67#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.11:31:12.69#ibcon#[25=USB\r\n] 2006.145.11:31:12.72#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.11:31:12.72#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.11:31:12.72#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.11:31:12.72#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.11:31:12.72$vck44/valo=7,864.99 2006.145.11:31:12.72#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.11:31:12.72#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.11:31:12.72#ibcon#ireg 17 cls_cnt 0 2006.145.11:31:12.72#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.11:31:12.72#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.11:31:12.72#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.11:31:12.74#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.11:31:12.78#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.11:31:12.78#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.11:31:12.78#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.11:31:12.78#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.11:31:12.78$vck44/va=7,4 2006.145.11:31:12.78#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.11:31:12.78#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.11:31:12.78#ibcon#ireg 11 cls_cnt 2 2006.145.11:31:12.78#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.11:31:12.84#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.11:31:12.84#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.11:31:12.86#ibcon#[25=AT07-04\r\n] 2006.145.11:31:12.89#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.11:31:12.89#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.11:31:12.89#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.11:31:12.89#ibcon#ireg 7 cls_cnt 0 2006.145.11:31:12.89#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.11:31:13.01#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.11:31:13.01#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.11:31:13.03#ibcon#[25=USB\r\n] 2006.145.11:31:13.06#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.11:31:13.06#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.11:31:13.06#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.11:31:13.06#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.11:31:13.06$vck44/valo=8,884.99 2006.145.11:31:13.06#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.11:31:13.06#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.11:31:13.06#ibcon#ireg 17 cls_cnt 0 2006.145.11:31:13.06#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.11:31:13.06#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.11:31:13.06#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.11:31:13.08#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.11:31:13.12#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.11:31:13.12#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.11:31:13.12#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.11:31:13.12#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.11:31:13.12$vck44/va=8,4 2006.145.11:31:13.12#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.11:31:13.12#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.11:31:13.12#ibcon#ireg 11 cls_cnt 2 2006.145.11:31:13.12#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.11:31:13.18#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.11:31:13.18#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.11:31:13.20#ibcon#[25=AT08-04\r\n] 2006.145.11:31:13.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.11:31:13.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.11:31:13.26#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.11:31:13.26#ibcon#ireg 7 cls_cnt 0 2006.145.11:31:13.26#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.11:31:13.37#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.11:31:13.37#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.11:31:13.39#ibcon#[25=USB\r\n] 2006.145.11:31:13.42#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.11:31:13.42#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.11:31:13.42#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.11:31:13.42#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.11:31:13.42$vck44/vblo=1,629.99 2006.145.11:31:13.42#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.11:31:13.42#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.11:31:13.42#ibcon#ireg 17 cls_cnt 0 2006.145.11:31:13.42#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.11:31:13.42#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.11:31:13.42#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.11:31:13.45#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.11:31:13.49#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.11:31:13.49#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.11:31:13.49#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.11:31:13.49#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.11:31:13.49$vck44/vb=1,3 2006.145.11:31:13.49#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.11:31:13.49#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.11:31:13.49#ibcon#ireg 11 cls_cnt 2 2006.145.11:31:13.49#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.11:31:13.49#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.11:31:13.49#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.11:31:13.51#ibcon#[27=AT01-03\r\n] 2006.145.11:31:13.54#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.11:31:13.54#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.11:31:13.54#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.11:31:13.54#ibcon#ireg 7 cls_cnt 0 2006.145.11:31:13.54#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.11:31:13.66#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.11:31:13.66#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.11:31:13.68#ibcon#[27=USB\r\n] 2006.145.11:31:13.71#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.11:31:13.71#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.11:31:13.71#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.11:31:13.71#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.11:31:13.71$vck44/vblo=2,634.99 2006.145.11:31:13.71#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.11:31:13.71#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.11:31:13.71#ibcon#ireg 17 cls_cnt 0 2006.145.11:31:13.71#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.11:31:13.71#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.11:31:13.71#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.11:31:13.73#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.11:31:13.77#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.11:31:13.77#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.11:31:13.77#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.11:31:13.77#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.11:31:13.77$vck44/vb=2,4 2006.145.11:31:13.77#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.11:31:13.77#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.11:31:13.77#ibcon#ireg 11 cls_cnt 2 2006.145.11:31:13.77#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.11:31:13.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.11:31:13.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.11:31:13.85#ibcon#[27=AT02-04\r\n] 2006.145.11:31:13.88#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.11:31:13.88#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.11:31:13.88#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.11:31:13.88#ibcon#ireg 7 cls_cnt 0 2006.145.11:31:13.88#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.11:31:14.00#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.11:31:14.00#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.11:31:14.02#ibcon#[27=USB\r\n] 2006.145.11:31:14.05#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.11:31:14.05#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.11:31:14.05#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.11:31:14.05#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.11:31:14.05$vck44/vblo=3,649.99 2006.145.11:31:14.05#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.11:31:14.05#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.11:31:14.05#ibcon#ireg 17 cls_cnt 0 2006.145.11:31:14.05#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.11:31:14.05#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.11:31:14.05#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.11:31:14.07#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.11:31:14.11#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.11:31:14.11#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.11:31:14.11#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.11:31:14.11#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.11:31:14.11$vck44/vb=3,4 2006.145.11:31:14.11#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.11:31:14.11#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.11:31:14.11#ibcon#ireg 11 cls_cnt 2 2006.145.11:31:14.11#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.11:31:14.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.11:31:14.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.11:31:14.19#ibcon#[27=AT03-04\r\n] 2006.145.11:31:14.22#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.11:31:14.22#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.11:31:14.22#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.11:31:14.22#ibcon#ireg 7 cls_cnt 0 2006.145.11:31:14.22#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.11:31:14.34#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.11:31:14.34#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.11:31:14.36#ibcon#[27=USB\r\n] 2006.145.11:31:14.39#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.11:31:14.39#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.11:31:14.39#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.11:31:14.39#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.11:31:14.39$vck44/vblo=4,679.99 2006.145.11:31:14.39#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.11:31:14.39#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.11:31:14.39#ibcon#ireg 17 cls_cnt 0 2006.145.11:31:14.39#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.11:31:14.39#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.11:31:14.39#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.11:31:14.41#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.11:31:14.45#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.11:31:14.45#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.11:31:14.45#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.11:31:14.45#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.11:31:14.45$vck44/vb=4,4 2006.145.11:31:14.45#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.11:31:14.45#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.11:31:14.45#ibcon#ireg 11 cls_cnt 2 2006.145.11:31:14.45#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.11:31:14.51#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.11:31:14.51#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.11:31:14.53#ibcon#[27=AT04-04\r\n] 2006.145.11:31:14.56#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.11:31:14.56#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.11:31:14.56#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.11:31:14.56#ibcon#ireg 7 cls_cnt 0 2006.145.11:31:14.56#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.11:31:14.68#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.11:31:14.68#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.11:31:14.70#ibcon#[27=USB\r\n] 2006.145.11:31:14.73#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.11:31:14.73#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.11:31:14.73#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.11:31:14.73#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.11:31:14.73$vck44/vblo=5,709.99 2006.145.11:31:14.73#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.11:31:14.73#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.11:31:14.73#ibcon#ireg 17 cls_cnt 0 2006.145.11:31:14.73#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.11:31:14.73#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.11:31:14.73#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.11:31:14.75#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.11:31:14.79#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.11:31:14.79#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.11:31:14.79#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.11:31:14.79#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.11:31:14.79$vck44/vb=5,4 2006.145.11:31:14.79#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.11:31:14.79#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.11:31:14.79#ibcon#ireg 11 cls_cnt 2 2006.145.11:31:14.79#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.11:31:14.85#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.11:31:14.85#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.11:31:14.87#ibcon#[27=AT05-04\r\n] 2006.145.11:31:14.90#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.11:31:14.90#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.11:31:14.90#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.11:31:14.90#ibcon#ireg 7 cls_cnt 0 2006.145.11:31:14.90#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.11:31:15.02#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.11:31:15.02#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.11:31:15.04#ibcon#[27=USB\r\n] 2006.145.11:31:15.07#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.11:31:15.07#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.11:31:15.07#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.11:31:15.07#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.11:31:15.07$vck44/vblo=6,719.99 2006.145.11:31:15.07#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.11:31:15.07#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.11:31:15.07#ibcon#ireg 17 cls_cnt 0 2006.145.11:31:15.07#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.11:31:15.07#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.11:31:15.07#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.11:31:15.09#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.11:31:15.13#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.11:31:15.13#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.11:31:15.13#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.11:31:15.13#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.11:31:15.13$vck44/vb=6,4 2006.145.11:31:15.13#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.11:31:15.13#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.11:31:15.13#ibcon#ireg 11 cls_cnt 2 2006.145.11:31:15.13#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.11:31:15.19#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.11:31:15.19#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.11:31:15.21#ibcon#[27=AT06-04\r\n] 2006.145.11:31:15.24#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.11:31:15.24#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.11:31:15.24#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.11:31:15.24#ibcon#ireg 7 cls_cnt 0 2006.145.11:31:15.24#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.11:31:15.36#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.11:31:15.36#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.11:31:15.38#ibcon#[27=USB\r\n] 2006.145.11:31:15.41#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.11:31:15.41#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.11:31:15.41#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.11:31:15.41#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.11:31:15.41$vck44/vblo=7,734.99 2006.145.11:31:15.41#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.11:31:15.41#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.11:31:15.41#ibcon#ireg 17 cls_cnt 0 2006.145.11:31:15.41#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.11:31:15.41#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.11:31:15.41#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.11:31:15.43#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.11:31:15.47#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.11:31:15.47#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.11:31:15.47#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.11:31:15.47#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.11:31:15.47$vck44/vb=7,4 2006.145.11:31:15.47#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.11:31:15.47#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.11:31:15.47#ibcon#ireg 11 cls_cnt 2 2006.145.11:31:15.47#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.11:31:15.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.11:31:15.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.11:31:15.55#ibcon#[27=AT07-04\r\n] 2006.145.11:31:15.58#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.11:31:15.58#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.11:31:15.58#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.11:31:15.58#ibcon#ireg 7 cls_cnt 0 2006.145.11:31:15.58#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.11:31:15.70#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.11:31:15.70#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.11:31:15.72#ibcon#[27=USB\r\n] 2006.145.11:31:15.75#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.11:31:15.75#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.11:31:15.75#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.11:31:15.75#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.11:31:15.75$vck44/vblo=8,744.99 2006.145.11:31:15.75#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.11:31:15.75#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.11:31:15.75#ibcon#ireg 17 cls_cnt 0 2006.145.11:31:15.75#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.11:31:15.75#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.11:31:15.75#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.11:31:15.77#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.11:31:15.81#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.11:31:15.81#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.11:31:15.81#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.11:31:15.81#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.11:31:15.81$vck44/vb=8,4 2006.145.11:31:15.81#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.11:31:15.81#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.11:31:15.81#ibcon#ireg 11 cls_cnt 2 2006.145.11:31:15.81#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.11:31:15.87#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.11:31:15.87#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.11:31:15.89#ibcon#[27=AT08-04\r\n] 2006.145.11:31:15.92#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.11:31:15.92#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.11:31:15.92#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.11:31:15.92#ibcon#ireg 7 cls_cnt 0 2006.145.11:31:15.92#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.11:31:16.04#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.11:31:16.04#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.11:31:16.06#ibcon#[27=USB\r\n] 2006.145.11:31:16.09#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.11:31:16.09#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.11:31:16.09#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.11:31:16.09#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.11:31:16.09$vck44/vabw=wide 2006.145.11:31:16.09#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.11:31:16.09#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.11:31:16.09#ibcon#ireg 8 cls_cnt 0 2006.145.11:31:16.09#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.11:31:16.09#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.11:31:16.09#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.11:31:16.11#ibcon#[25=BW32\r\n] 2006.145.11:31:16.14#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.11:31:16.14#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.11:31:16.14#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.11:31:16.14#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.11:31:16.14$vck44/vbbw=wide 2006.145.11:31:16.14#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.11:31:16.14#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.11:31:16.14#ibcon#ireg 8 cls_cnt 0 2006.145.11:31:16.14#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:31:16.21#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:31:16.21#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:31:16.23#ibcon#[27=BW32\r\n] 2006.145.11:31:16.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:31:16.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:31:16.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.11:31:16.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.11:31:16.26$setupk4/ifdk4 2006.145.11:31:16.26$ifdk4/lo= 2006.145.11:31:16.26$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.11:31:16.26$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.11:31:16.26$ifdk4/patch= 2006.145.11:31:16.26$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.11:31:16.26$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.11:31:16.26$setupk4/!*+20s 2006.145.11:31:20.31#abcon#<5=/05 2.1 3.5 16.53 691020.3\r\n> 2006.145.11:31:20.33#abcon#{5=INTERFACE CLEAR} 2006.145.11:31:20.39#abcon#[5=S1D000X0/0*\r\n] 2006.145.11:31:30.48#abcon#<5=/05 2.2 3.5 16.53 681020.3\r\n> 2006.145.11:31:30.50#abcon#{5=INTERFACE CLEAR} 2006.145.11:31:30.56#abcon#[5=S1D000X0/0*\r\n] 2006.145.11:31:30.70$setupk4/"tpicd 2006.145.11:31:30.70$setupk4/echo=off 2006.145.11:31:30.70$setupk4/xlog=off 2006.145.11:31:30.70:!2006.145.11:37:36 2006.145.11:31:32.14#trakl#Source acquired 2006.145.11:31:32.14#flagr#flagr/antenna,acquired 2006.145.11:37:36.00:preob 2006.145.11:37:36.14/onsource/TRACKING 2006.145.11:37:36.14:!2006.145.11:37:46 2006.145.11:37:46.00:"tape 2006.145.11:37:46.00:"st=record 2006.145.11:37:46.00:data_valid=on 2006.145.11:37:46.00:midob 2006.145.11:37:47.14/onsource/TRACKING 2006.145.11:37:47.14/wx/16.46,1020.4,70 2006.145.11:37:47.37/cable/+6.5465E-03 2006.145.11:37:48.46/va/01,08,usb,yes,33,36 2006.145.11:37:48.46/va/02,07,usb,yes,36,37 2006.145.11:37:48.46/va/03,08,usb,yes,33,34 2006.145.11:37:48.46/va/04,07,usb,yes,37,39 2006.145.11:37:48.46/va/05,04,usb,yes,32,33 2006.145.11:37:48.46/va/06,04,usb,yes,36,36 2006.145.11:37:48.46/va/07,04,usb,yes,36,38 2006.145.11:37:48.46/va/08,04,usb,yes,31,37 2006.145.11:37:48.69/valo/01,524.99,yes,locked 2006.145.11:37:48.69/valo/02,534.99,yes,locked 2006.145.11:37:48.69/valo/03,564.99,yes,locked 2006.145.11:37:48.69/valo/04,624.99,yes,locked 2006.145.11:37:48.69/valo/05,734.99,yes,locked 2006.145.11:37:48.69/valo/06,814.99,yes,locked 2006.145.11:37:48.69/valo/07,864.99,yes,locked 2006.145.11:37:48.69/valo/08,884.99,yes,locked 2006.145.11:37:49.78/vb/01,03,usb,yes,38,35 2006.145.11:37:49.78/vb/02,04,usb,yes,33,33 2006.145.11:37:49.78/vb/03,04,usb,yes,30,33 2006.145.11:37:49.78/vb/04,04,usb,yes,35,34 2006.145.11:37:49.78/vb/05,04,usb,yes,27,30 2006.145.11:37:49.78/vb/06,04,usb,yes,32,28 2006.145.11:37:49.78/vb/07,04,usb,yes,32,31 2006.145.11:37:49.78/vb/08,04,usb,yes,30,33 2006.145.11:37:50.02/vblo/01,629.99,yes,locked 2006.145.11:37:50.02/vblo/02,634.99,yes,locked 2006.145.11:37:50.02/vblo/03,649.99,yes,locked 2006.145.11:37:50.02/vblo/04,679.99,yes,locked 2006.145.11:37:50.02/vblo/05,709.99,yes,locked 2006.145.11:37:50.02/vblo/06,719.99,yes,locked 2006.145.11:37:50.02/vblo/07,734.99,yes,locked 2006.145.11:37:50.02/vblo/08,744.99,yes,locked 2006.145.11:37:50.17/vabw/8 2006.145.11:37:50.32/vbbw/8 2006.145.11:37:50.41/xfe/off,on,15.5 2006.145.11:37:50.78/ifatt/23,28,28,28 2006.145.11:37:51.07/fmout-gps/S +5.2E-08 2006.145.11:37:51.15:!2006.145.11:38:26 2006.145.11:38:26.01:data_valid=off 2006.145.11:38:26.01:"et 2006.145.11:38:26.02:!+3s 2006.145.11:38:29.03:"tape 2006.145.11:38:29.03:postob 2006.145.11:38:29.25/cable/+6.5471E-03 2006.145.11:38:29.25/wx/16.46,1020.4,70 2006.145.11:38:29.34/fmout-gps/S +5.3E-08 2006.145.11:38:29.34:scan_name=145-1143,jd0605,40 2006.145.11:38:29.34:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.145.11:38:31.14#flagr#flagr/antenna,new-source 2006.145.11:38:31.14:checkk5 2006.145.11:38:31.57/chk_autoobs//k5ts1/ autoobs is running! 2006.145.11:38:32.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.11:38:32.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.11:38:32.91/chk_autoobs//k5ts4/ autoobs is running! 2006.145.11:38:33.34/chk_obsdata//k5ts1/T1451137??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.11:38:33.78/chk_obsdata//k5ts2/T1451137??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.11:38:34.21/chk_obsdata//k5ts3/T1451137??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.11:38:34.65/chk_obsdata//k5ts4/T1451137??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.11:38:35.41/k5log//k5ts1_log_newline 2006.145.11:38:36.16/k5log//k5ts2_log_newline 2006.145.11:38:36.90/k5log//k5ts3_log_newline 2006.145.11:38:37.64/k5log//k5ts4_log_newline 2006.145.11:38:37.66/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.11:38:37.66:setupk4=1 2006.145.11:38:37.66$setupk4/echo=on 2006.145.11:38:37.66$setupk4/pcalon 2006.145.11:38:37.66$pcalon/"no phase cal control is implemented here 2006.145.11:38:37.66$setupk4/"tpicd=stop 2006.145.11:38:37.66$setupk4/"rec=synch_on 2006.145.11:38:37.66$setupk4/"rec_mode=128 2006.145.11:38:37.66$setupk4/!* 2006.145.11:38:37.66$setupk4/recpk4 2006.145.11:38:37.66$recpk4/recpatch= 2006.145.11:38:37.66$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.11:38:37.66$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.11:38:37.66$setupk4/vck44 2006.145.11:38:37.66$vck44/valo=1,524.99 2006.145.11:38:37.66#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.11:38:37.66#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.11:38:37.66#ibcon#ireg 17 cls_cnt 0 2006.145.11:38:37.66#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:38:37.66#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:38:37.66#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:38:37.68#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.11:38:37.71#abcon#[5=S1D000X0/0*\r\n] 2006.145.11:38:37.73#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:38:37.73#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:38:37.73#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.11:38:37.73#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.11:38:37.73$vck44/va=1,8 2006.145.11:38:37.73#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.11:38:37.73#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.11:38:37.73#ibcon#ireg 11 cls_cnt 2 2006.145.11:38:37.73#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:38:37.73#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:38:37.73#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:38:37.75#ibcon#[25=AT01-08\r\n] 2006.145.11:38:37.78#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:38:37.78#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:38:37.78#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.11:38:37.78#ibcon#ireg 7 cls_cnt 0 2006.145.11:38:37.78#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:38:37.90#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:38:37.90#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:38:37.92#ibcon#[25=USB\r\n] 2006.145.11:38:37.95#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:38:37.95#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:38:37.95#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.11:38:37.95#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.11:38:37.95$vck44/valo=2,534.99 2006.145.11:38:37.95#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.11:38:37.95#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.11:38:37.95#ibcon#ireg 17 cls_cnt 0 2006.145.11:38:37.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:38:37.95#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:38:37.95#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:38:37.98#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.11:38:38.02#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:38:38.02#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:38:38.02#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.11:38:38.02#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.11:38:38.02$vck44/va=2,7 2006.145.11:38:38.02#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.11:38:38.02#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.11:38:38.02#ibcon#ireg 11 cls_cnt 2 2006.145.11:38:38.02#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:38:38.07#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:38:38.07#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:38:38.09#ibcon#[25=AT02-07\r\n] 2006.145.11:38:38.12#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:38:38.12#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:38:38.12#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.11:38:38.12#ibcon#ireg 7 cls_cnt 0 2006.145.11:38:38.12#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:38:38.24#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:38:38.24#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:38:38.26#ibcon#[25=USB\r\n] 2006.145.11:38:38.29#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:38:38.29#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:38:38.29#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.11:38:38.29#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.11:38:38.29$vck44/valo=3,564.99 2006.145.11:38:38.29#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.11:38:38.29#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.11:38:38.29#ibcon#ireg 17 cls_cnt 0 2006.145.11:38:38.29#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:38:38.29#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:38:38.29#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:38:38.31#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.11:38:38.35#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:38:38.35#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:38:38.35#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.11:38:38.35#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.11:38:38.35$vck44/va=3,8 2006.145.11:38:38.35#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.11:38:38.35#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.11:38:38.35#ibcon#ireg 11 cls_cnt 2 2006.145.11:38:38.35#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:38:38.41#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:38:38.41#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:38:38.43#ibcon#[25=AT03-08\r\n] 2006.145.11:38:38.46#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:38:38.46#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:38:38.46#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.11:38:38.46#ibcon#ireg 7 cls_cnt 0 2006.145.11:38:38.46#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:38:38.58#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:38:38.58#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:38:38.60#ibcon#[25=USB\r\n] 2006.145.11:38:38.63#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:38:38.63#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:38:38.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.11:38:38.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.11:38:38.63$vck44/valo=4,624.99 2006.145.11:38:38.63#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.11:38:38.63#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.11:38:38.63#ibcon#ireg 17 cls_cnt 0 2006.145.11:38:38.63#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:38:38.63#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:38:38.63#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:38:38.65#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.11:38:38.69#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:38:38.69#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:38:38.69#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.11:38:38.69#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.11:38:38.69$vck44/va=4,7 2006.145.11:38:38.69#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.11:38:38.69#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.11:38:38.69#ibcon#ireg 11 cls_cnt 2 2006.145.11:38:38.69#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:38:38.75#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:38:38.75#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:38:38.77#ibcon#[25=AT04-07\r\n] 2006.145.11:38:38.80#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:38:38.80#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:38:38.80#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.11:38:38.80#ibcon#ireg 7 cls_cnt 0 2006.145.11:38:38.80#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:38:38.92#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:38:38.92#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:38:38.94#ibcon#[25=USB\r\n] 2006.145.11:38:38.97#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:38:38.97#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:38:38.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.11:38:38.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.11:38:38.97$vck44/valo=5,734.99 2006.145.11:38:38.97#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.11:38:38.97#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.11:38:38.97#ibcon#ireg 17 cls_cnt 0 2006.145.11:38:38.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:38:38.97#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:38:38.97#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:38:38.99#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.11:38:39.03#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:38:39.03#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:38:39.03#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.11:38:39.03#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.11:38:39.03$vck44/va=5,4 2006.145.11:38:39.03#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.11:38:39.03#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.11:38:39.03#ibcon#ireg 11 cls_cnt 2 2006.145.11:38:39.03#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.11:38:39.09#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.11:38:39.09#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.11:38:39.11#ibcon#[25=AT05-04\r\n] 2006.145.11:38:39.14#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.11:38:39.14#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.11:38:39.14#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.11:38:39.14#ibcon#ireg 7 cls_cnt 0 2006.145.11:38:39.14#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.11:38:39.28#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.11:38:39.28#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.11:38:39.29#ibcon#[25=USB\r\n] 2006.145.11:38:39.32#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.11:38:39.32#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.11:38:39.32#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.11:38:39.32#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.11:38:39.32$vck44/valo=6,814.99 2006.145.11:38:39.32#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.11:38:39.32#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.11:38:39.32#ibcon#ireg 17 cls_cnt 0 2006.145.11:38:39.32#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.11:38:39.32#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.11:38:39.32#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.11:38:39.35#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.11:38:39.39#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.11:38:39.39#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.11:38:39.39#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.11:38:39.39#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.11:38:39.39$vck44/va=6,4 2006.145.11:38:39.39#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.11:38:39.39#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.11:38:39.39#ibcon#ireg 11 cls_cnt 2 2006.145.11:38:39.39#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.11:38:39.44#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.11:38:39.44#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.11:38:39.46#ibcon#[25=AT06-04\r\n] 2006.145.11:38:39.49#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.11:38:39.49#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.11:38:39.49#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.11:38:39.49#ibcon#ireg 7 cls_cnt 0 2006.145.11:38:39.49#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.11:38:39.61#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.11:38:39.61#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.11:38:39.63#ibcon#[25=USB\r\n] 2006.145.11:38:39.66#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.11:38:39.66#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.11:38:39.66#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.11:38:39.66#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.11:38:39.66$vck44/valo=7,864.99 2006.145.11:38:39.66#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.11:38:39.66#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.11:38:39.66#ibcon#ireg 17 cls_cnt 0 2006.145.11:38:39.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:38:39.66#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:38:39.66#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:38:39.68#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.11:38:39.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:38:39.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:38:39.72#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.11:38:39.72#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.11:38:39.72$vck44/va=7,4 2006.145.11:38:39.72#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.11:38:39.72#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.11:38:39.72#ibcon#ireg 11 cls_cnt 2 2006.145.11:38:39.72#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.11:38:39.78#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.11:38:39.78#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.11:38:39.80#ibcon#[25=AT07-04\r\n] 2006.145.11:38:39.83#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.11:38:39.83#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.11:38:39.83#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.11:38:39.83#ibcon#ireg 7 cls_cnt 0 2006.145.11:38:39.83#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.11:38:39.95#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.11:38:39.95#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.11:38:39.97#ibcon#[25=USB\r\n] 2006.145.11:38:40.00#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.11:38:40.00#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.11:38:40.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.11:38:40.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.11:38:40.00$vck44/valo=8,884.99 2006.145.11:38:40.00#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.11:38:40.00#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.11:38:40.00#ibcon#ireg 17 cls_cnt 0 2006.145.11:38:40.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.11:38:40.00#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.11:38:40.00#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.11:38:40.02#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.11:38:40.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.11:38:40.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.11:38:40.06#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.11:38:40.06#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.11:38:40.06$vck44/va=8,4 2006.145.11:38:40.06#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.11:38:40.06#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.11:38:40.06#ibcon#ireg 11 cls_cnt 2 2006.145.11:38:40.06#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.11:38:40.12#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.11:38:40.12#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.11:38:40.14#ibcon#[25=AT08-04\r\n] 2006.145.11:38:40.17#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.11:38:40.17#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.11:38:40.17#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.11:38:40.17#ibcon#ireg 7 cls_cnt 0 2006.145.11:38:40.17#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.11:38:40.29#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.11:38:40.29#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.11:38:40.31#ibcon#[25=USB\r\n] 2006.145.11:38:40.34#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.11:38:40.34#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.11:38:40.34#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.11:38:40.34#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.11:38:40.34$vck44/vblo=1,629.99 2006.145.11:38:40.34#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.11:38:40.34#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.11:38:40.34#ibcon#ireg 17 cls_cnt 0 2006.145.11:38:40.34#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:38:40.34#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:38:40.34#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:38:40.36#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.11:38:40.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:38:40.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:38:40.40#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.11:38:40.40#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.11:38:40.40$vck44/vb=1,3 2006.145.11:38:40.40#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.11:38:40.40#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.11:38:40.40#ibcon#ireg 11 cls_cnt 2 2006.145.11:38:40.40#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.11:38:40.40#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.11:38:40.40#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.11:38:40.42#ibcon#[27=AT01-03\r\n] 2006.145.11:38:40.45#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.11:38:40.45#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.11:38:40.45#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.11:38:40.45#ibcon#ireg 7 cls_cnt 0 2006.145.11:38:40.45#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.11:38:40.57#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.11:38:40.57#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.11:38:40.59#ibcon#[27=USB\r\n] 2006.145.11:38:40.62#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.11:38:40.62#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.11:38:40.62#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.11:38:40.62#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.11:38:40.62$vck44/vblo=2,634.99 2006.145.11:38:40.62#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.11:38:40.62#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.11:38:40.62#ibcon#ireg 17 cls_cnt 0 2006.145.11:38:40.62#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.11:38:40.62#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.11:38:40.62#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.11:38:40.64#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.11:38:40.68#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.11:38:40.68#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.11:38:40.68#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.11:38:40.68#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.11:38:40.68$vck44/vb=2,4 2006.145.11:38:40.68#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.11:38:40.68#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.11:38:40.68#ibcon#ireg 11 cls_cnt 2 2006.145.11:38:40.68#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:38:40.74#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:38:40.74#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:38:40.76#ibcon#[27=AT02-04\r\n] 2006.145.11:38:40.79#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:38:40.79#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:38:40.79#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.11:38:40.79#ibcon#ireg 7 cls_cnt 0 2006.145.11:38:40.79#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:38:40.91#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:38:40.91#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:38:40.93#ibcon#[27=USB\r\n] 2006.145.11:38:40.96#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:38:40.96#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:38:40.96#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.11:38:40.96#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.11:38:40.96$vck44/vblo=3,649.99 2006.145.11:38:40.96#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.11:38:40.96#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.11:38:40.96#ibcon#ireg 17 cls_cnt 0 2006.145.11:38:40.96#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:38:40.96#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:38:40.96#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:38:40.98#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.11:38:41.02#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:38:41.02#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:38:41.02#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.11:38:41.02#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.11:38:41.02$vck44/vb=3,4 2006.145.11:38:41.02#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.11:38:41.02#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.11:38:41.02#ibcon#ireg 11 cls_cnt 2 2006.145.11:38:41.02#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:38:41.08#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:38:41.08#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:38:41.10#ibcon#[27=AT03-04\r\n] 2006.145.11:38:41.13#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:38:41.13#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:38:41.13#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.11:38:41.13#ibcon#ireg 7 cls_cnt 0 2006.145.11:38:41.13#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:38:41.25#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:38:41.25#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:38:41.27#ibcon#[27=USB\r\n] 2006.145.11:38:41.30#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:38:41.30#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:38:41.30#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.11:38:41.30#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.11:38:41.30$vck44/vblo=4,679.99 2006.145.11:38:41.30#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.11:38:41.30#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.11:38:41.30#ibcon#ireg 17 cls_cnt 0 2006.145.11:38:41.30#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:38:41.30#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:38:41.30#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:38:41.32#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.11:38:41.36#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:38:41.36#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:38:41.36#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.11:38:41.36#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.11:38:41.36$vck44/vb=4,4 2006.145.11:38:41.36#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.11:38:41.36#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.11:38:41.36#ibcon#ireg 11 cls_cnt 2 2006.145.11:38:41.36#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:38:41.42#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:38:41.42#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:38:41.44#ibcon#[27=AT04-04\r\n] 2006.145.11:38:41.47#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:38:41.47#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:38:41.47#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.11:38:41.47#ibcon#ireg 7 cls_cnt 0 2006.145.11:38:41.47#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:38:41.59#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:38:41.59#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:38:41.61#ibcon#[27=USB\r\n] 2006.145.11:38:41.64#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:38:41.64#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:38:41.64#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.11:38:41.64#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.11:38:41.64$vck44/vblo=5,709.99 2006.145.11:38:41.64#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.11:38:41.64#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.11:38:41.64#ibcon#ireg 17 cls_cnt 0 2006.145.11:38:41.64#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:38:41.64#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:38:41.64#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:38:41.66#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.11:38:41.70#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:38:41.70#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:38:41.70#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.11:38:41.70#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.11:38:41.70$vck44/vb=5,4 2006.145.11:38:41.70#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.11:38:41.70#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.11:38:41.70#ibcon#ireg 11 cls_cnt 2 2006.145.11:38:41.70#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:38:41.76#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:38:41.76#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:38:41.78#ibcon#[27=AT05-04\r\n] 2006.145.11:38:41.81#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:38:41.81#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:38:41.81#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.11:38:41.81#ibcon#ireg 7 cls_cnt 0 2006.145.11:38:41.81#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:38:41.93#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:38:41.93#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:38:41.95#ibcon#[27=USB\r\n] 2006.145.11:38:41.98#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:38:41.98#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:38:41.98#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.11:38:41.98#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.11:38:41.98$vck44/vblo=6,719.99 2006.145.11:38:41.98#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.11:38:41.98#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.11:38:41.98#ibcon#ireg 17 cls_cnt 0 2006.145.11:38:41.98#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:38:41.98#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:38:41.98#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:38:42.00#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.11:38:42.04#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:38:42.04#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:38:42.04#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.11:38:42.04#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.11:38:42.04$vck44/vb=6,4 2006.145.11:38:42.04#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.11:38:42.04#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.11:38:42.04#ibcon#ireg 11 cls_cnt 2 2006.145.11:38:42.04#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.11:38:42.10#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.11:38:42.10#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.11:38:42.12#ibcon#[27=AT06-04\r\n] 2006.145.11:38:42.15#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.11:38:42.15#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.11:38:42.15#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.11:38:42.15#ibcon#ireg 7 cls_cnt 0 2006.145.11:38:42.15#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.11:38:42.27#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.11:38:42.27#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.11:38:42.29#ibcon#[27=USB\r\n] 2006.145.11:38:42.32#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.11:38:42.32#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.11:38:42.32#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.11:38:42.32#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.11:38:42.32$vck44/vblo=7,734.99 2006.145.11:38:42.32#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.11:38:42.32#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.11:38:42.32#ibcon#ireg 17 cls_cnt 0 2006.145.11:38:42.32#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.11:38:42.32#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.11:38:42.32#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.11:38:42.34#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.11:38:42.38#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.11:38:42.38#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.11:38:42.38#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.11:38:42.38#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.11:38:42.38$vck44/vb=7,4 2006.145.11:38:42.38#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.11:38:42.38#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.11:38:42.38#ibcon#ireg 11 cls_cnt 2 2006.145.11:38:42.38#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.11:38:42.44#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.11:38:42.44#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.11:38:42.46#ibcon#[27=AT07-04\r\n] 2006.145.11:38:42.49#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.11:38:42.49#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.11:38:42.49#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.11:38:42.49#ibcon#ireg 7 cls_cnt 0 2006.145.11:38:42.49#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.11:38:42.61#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.11:38:42.61#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.11:38:42.63#ibcon#[27=USB\r\n] 2006.145.11:38:42.66#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.11:38:42.66#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.11:38:42.66#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.11:38:42.66#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.11:38:42.66$vck44/vblo=8,744.99 2006.145.11:38:42.66#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.11:38:42.66#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.11:38:42.66#ibcon#ireg 17 cls_cnt 0 2006.145.11:38:42.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:38:42.66#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:38:42.66#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:38:42.68#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.11:38:42.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:38:42.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:38:42.72#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.11:38:42.72#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.11:38:42.72$vck44/vb=8,4 2006.145.11:38:42.72#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.11:38:42.72#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.11:38:42.72#ibcon#ireg 11 cls_cnt 2 2006.145.11:38:42.72#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.11:38:42.78#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.11:38:42.78#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.11:38:42.80#ibcon#[27=AT08-04\r\n] 2006.145.11:38:42.83#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.11:38:42.83#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.11:38:42.83#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.11:38:42.83#ibcon#ireg 7 cls_cnt 0 2006.145.11:38:42.83#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.11:38:42.95#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.11:38:42.95#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.11:38:42.97#ibcon#[27=USB\r\n] 2006.145.11:38:43.00#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.11:38:43.00#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.11:38:43.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.11:38:43.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.11:38:43.00$vck44/vabw=wide 2006.145.11:38:43.00#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.11:38:43.00#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.11:38:43.00#ibcon#ireg 8 cls_cnt 0 2006.145.11:38:43.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.11:38:43.00#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.11:38:43.00#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.11:38:43.02#ibcon#[25=BW32\r\n] 2006.145.11:38:43.05#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.11:38:43.05#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.11:38:43.05#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.11:38:43.05#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.11:38:43.05$vck44/vbbw=wide 2006.145.11:38:43.05#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.11:38:43.05#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.11:38:43.05#ibcon#ireg 8 cls_cnt 0 2006.145.11:38:43.05#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:38:43.12#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:38:43.12#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:38:43.14#ibcon#[27=BW32\r\n] 2006.145.11:38:43.17#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:38:43.17#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:38:43.17#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.11:38:43.17#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.11:38:43.17$setupk4/ifdk4 2006.145.11:38:43.17$ifdk4/lo= 2006.145.11:38:43.17$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.11:38:43.17$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.11:38:43.17$ifdk4/patch= 2006.145.11:38:43.17$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.11:38:43.17$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.11:38:43.17$setupk4/!*+20s 2006.145.11:38:47.80#abcon#<5=/05 2.1 3.7 16.45 701020.4\r\n> 2006.145.11:38:47.82#abcon#{5=INTERFACE CLEAR} 2006.145.11:38:47.88#abcon#[5=S1D000X0/0*\r\n] 2006.145.11:38:57.67$setupk4/"tpicd 2006.145.11:38:57.67$setupk4/echo=off 2006.145.11:38:57.67$setupk4/xlog=off 2006.145.11:38:57.67:!2006.145.11:43:02 2006.145.11:39:01.14#trakl#Source acquired 2006.145.11:39:02.14#flagr#flagr/antenna,acquired 2006.145.11:43:02.00:preob 2006.145.11:43:03.14/onsource/TRACKING 2006.145.11:43:03.14:!2006.145.11:43:12 2006.145.11:43:12.00:"tape 2006.145.11:43:12.00:"st=record 2006.145.11:43:12.00:data_valid=on 2006.145.11:43:12.00:midob 2006.145.11:43:12.14/onsource/TRACKING 2006.145.11:43:12.14/wx/16.40,1020.4,71 2006.145.11:43:12.29/cable/+6.5456E-03 2006.145.11:43:13.38/va/01,08,usb,yes,31,33 2006.145.11:43:13.38/va/02,07,usb,yes,33,34 2006.145.11:43:13.38/va/03,08,usb,yes,30,31 2006.145.11:43:13.38/va/04,07,usb,yes,34,36 2006.145.11:43:13.38/va/05,04,usb,yes,30,30 2006.145.11:43:13.38/va/06,04,usb,yes,33,33 2006.145.11:43:13.38/va/07,04,usb,yes,34,35 2006.145.11:43:13.38/va/08,04,usb,yes,29,34 2006.145.11:43:13.61/valo/01,524.99,yes,locked 2006.145.11:43:13.61/valo/02,534.99,yes,locked 2006.145.11:43:13.61/valo/03,564.99,yes,locked 2006.145.11:43:13.61/valo/04,624.99,yes,locked 2006.145.11:43:13.61/valo/05,734.99,yes,locked 2006.145.11:43:13.61/valo/06,814.99,yes,locked 2006.145.11:43:13.61/valo/07,864.99,yes,locked 2006.145.11:43:13.61/valo/08,884.99,yes,locked 2006.145.11:43:14.70/vb/01,03,usb,yes,38,35 2006.145.11:43:14.70/vb/02,04,usb,yes,33,33 2006.145.11:43:14.70/vb/03,04,usb,yes,30,33 2006.145.11:43:14.70/vb/04,04,usb,yes,34,33 2006.145.11:43:14.70/vb/05,04,usb,yes,27,29 2006.145.11:43:14.70/vb/06,04,usb,yes,31,27 2006.145.11:43:14.70/vb/07,04,usb,yes,31,31 2006.145.11:43:14.70/vb/08,04,usb,yes,28,32 2006.145.11:43:14.93/vblo/01,629.99,yes,locked 2006.145.11:43:14.93/vblo/02,634.99,yes,locked 2006.145.11:43:14.93/vblo/03,649.99,yes,locked 2006.145.11:43:14.93/vblo/04,679.99,yes,locked 2006.145.11:43:14.93/vblo/05,709.99,yes,locked 2006.145.11:43:14.93/vblo/06,719.99,yes,locked 2006.145.11:43:14.93/vblo/07,734.99,yes,locked 2006.145.11:43:14.93/vblo/08,744.99,yes,locked 2006.145.11:43:15.08/vabw/8 2006.145.11:43:15.23/vbbw/8 2006.145.11:43:15.32/xfe/off,on,15.2 2006.145.11:43:15.71/ifatt/23,28,28,28 2006.145.11:43:16.07/fmout-gps/S +5.1E-08 2006.145.11:43:16.15:!2006.145.11:43:52 2006.145.11:43:52.01:data_valid=off 2006.145.11:43:52.01:"et 2006.145.11:43:52.02:!+3s 2006.145.11:43:55.03:"tape 2006.145.11:43:55.03:postob 2006.145.11:43:55.18/cable/+6.5459E-03 2006.145.11:43:55.18/wx/16.38,1020.5,71 2006.145.11:43:55.24/fmout-gps/S +5.2E-08 2006.145.11:43:55.24:scan_name=145-1146,jd0605,180 2006.145.11:43:55.25:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.145.11:43:57.13#flagr#flagr/antenna,new-source 2006.145.11:43:57.13:checkk5 2006.145.11:43:57.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.11:43:57.99/chk_autoobs//k5ts2/ autoobs is running! 2006.145.11:43:58.42/chk_autoobs//k5ts3/ autoobs is running! 2006.145.11:43:58.84/chk_autoobs//k5ts4/ autoobs is running! 2006.145.11:43:59.27/chk_obsdata//k5ts1/T1451143??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.11:43:59.71/chk_obsdata//k5ts2/T1451143??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.11:44:00.14/chk_obsdata//k5ts3/T1451143??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.11:44:00.58/chk_obsdata//k5ts4/T1451143??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.11:44:01.34/k5log//k5ts1_log_newline 2006.145.11:44:02.08/k5log//k5ts2_log_newline 2006.145.11:44:02.81/k5log//k5ts3_log_newline 2006.145.11:44:03.56/k5log//k5ts4_log_newline 2006.145.11:44:03.58/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.11:44:03.58:setupk4=1 2006.145.11:44:03.58$setupk4/echo=on 2006.145.11:44:03.58$setupk4/pcalon 2006.145.11:44:03.58$pcalon/"no phase cal control is implemented here 2006.145.11:44:03.58$setupk4/"tpicd=stop 2006.145.11:44:03.58$setupk4/"rec=synch_on 2006.145.11:44:03.58$setupk4/"rec_mode=128 2006.145.11:44:03.58$setupk4/!* 2006.145.11:44:03.58$setupk4/recpk4 2006.145.11:44:03.58$recpk4/recpatch= 2006.145.11:44:03.59$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.11:44:03.59$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.11:44:03.59$setupk4/vck44 2006.145.11:44:03.59$vck44/valo=1,524.99 2006.145.11:44:03.59#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.11:44:03.59#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.11:44:03.59#ibcon#ireg 17 cls_cnt 0 2006.145.11:44:03.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.11:44:03.59#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.11:44:03.59#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.11:44:03.63#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.11:44:03.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.11:44:03.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.11:44:03.68#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.11:44:03.68#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.11:44:03.68$vck44/va=1,8 2006.145.11:44:03.68#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.11:44:03.68#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.11:44:03.68#ibcon#ireg 11 cls_cnt 2 2006.145.11:44:03.68#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.11:44:03.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.11:44:03.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.11:44:03.70#ibcon#[25=AT01-08\r\n] 2006.145.11:44:03.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.11:44:03.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.11:44:03.73#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.11:44:03.73#ibcon#ireg 7 cls_cnt 0 2006.145.11:44:03.73#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.11:44:03.85#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.11:44:03.85#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.11:44:03.87#ibcon#[25=USB\r\n] 2006.145.11:44:03.92#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.11:44:03.92#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.11:44:03.92#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.11:44:03.92#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.11:44:03.92$vck44/valo=2,534.99 2006.145.11:44:03.92#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.11:44:03.92#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.11:44:03.92#ibcon#ireg 17 cls_cnt 0 2006.145.11:44:03.92#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.11:44:03.92#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.11:44:03.92#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.11:44:03.93#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.11:44:03.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.11:44:03.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.11:44:03.97#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.11:44:03.97#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.11:44:03.97$vck44/va=2,7 2006.145.11:44:03.97#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.11:44:03.97#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.11:44:03.97#ibcon#ireg 11 cls_cnt 2 2006.145.11:44:03.97#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.11:44:04.04#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.11:44:04.04#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.11:44:04.06#ibcon#[25=AT02-07\r\n] 2006.145.11:44:04.09#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.11:44:04.09#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.11:44:04.09#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.11:44:04.09#ibcon#ireg 7 cls_cnt 0 2006.145.11:44:04.09#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.11:44:04.21#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.11:44:04.21#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.11:44:04.23#ibcon#[25=USB\r\n] 2006.145.11:44:04.26#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.11:44:04.26#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.11:44:04.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.11:44:04.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.11:44:04.26$vck44/valo=3,564.99 2006.145.11:44:04.26#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.11:44:04.26#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.11:44:04.26#ibcon#ireg 17 cls_cnt 0 2006.145.11:44:04.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.11:44:04.26#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.11:44:04.26#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.11:44:04.28#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.11:44:04.32#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.11:44:04.32#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.11:44:04.32#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.11:44:04.32#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.11:44:04.32$vck44/va=3,8 2006.145.11:44:04.32#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.11:44:04.32#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.11:44:04.32#ibcon#ireg 11 cls_cnt 2 2006.145.11:44:04.32#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.11:44:04.38#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.11:44:04.38#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.11:44:04.40#ibcon#[25=AT03-08\r\n] 2006.145.11:44:04.43#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.11:44:04.43#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.11:44:04.43#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.11:44:04.43#ibcon#ireg 7 cls_cnt 0 2006.145.11:44:04.43#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.11:44:04.55#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.11:44:04.55#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.11:44:04.57#ibcon#[25=USB\r\n] 2006.145.11:44:04.60#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.11:44:04.60#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.11:44:04.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.11:44:04.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.11:44:04.60$vck44/valo=4,624.99 2006.145.11:44:04.60#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.11:44:04.60#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.11:44:04.60#ibcon#ireg 17 cls_cnt 0 2006.145.11:44:04.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.11:44:04.60#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.11:44:04.60#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.11:44:04.62#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.11:44:04.66#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.11:44:04.66#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.11:44:04.66#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.11:44:04.66#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.11:44:04.66$vck44/va=4,7 2006.145.11:44:04.66#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.11:44:04.66#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.11:44:04.66#ibcon#ireg 11 cls_cnt 2 2006.145.11:44:04.66#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.11:44:04.72#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.11:44:04.72#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.11:44:04.74#ibcon#[25=AT04-07\r\n] 2006.145.11:44:04.77#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.11:44:04.77#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.11:44:04.77#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.11:44:04.77#ibcon#ireg 7 cls_cnt 0 2006.145.11:44:04.77#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.11:44:04.89#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.11:44:04.89#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.11:44:04.91#ibcon#[25=USB\r\n] 2006.145.11:44:04.94#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.11:44:04.94#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.11:44:04.94#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.11:44:04.94#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.11:44:04.94$vck44/valo=5,734.99 2006.145.11:44:04.94#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.11:44:04.94#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.11:44:04.94#ibcon#ireg 17 cls_cnt 0 2006.145.11:44:04.94#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:44:04.94#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:44:04.94#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:44:04.96#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.11:44:05.01#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:44:05.01#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:44:05.01#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.11:44:05.01#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.11:44:05.01$vck44/va=5,4 2006.145.11:44:05.01#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.11:44:05.01#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.11:44:05.01#ibcon#ireg 11 cls_cnt 2 2006.145.11:44:05.01#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.11:44:05.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.11:44:05.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.11:44:05.07#ibcon#[25=AT05-04\r\n] 2006.145.11:44:05.11#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.11:44:05.11#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.11:44:05.11#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.11:44:05.11#ibcon#ireg 7 cls_cnt 0 2006.145.11:44:05.11#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.11:44:05.22#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.11:44:05.22#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.11:44:05.24#ibcon#[25=USB\r\n] 2006.145.11:44:05.27#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.11:44:05.27#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.11:44:05.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.11:44:05.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.11:44:05.27$vck44/valo=6,814.99 2006.145.11:44:05.27#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.11:44:05.27#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.11:44:05.27#ibcon#ireg 17 cls_cnt 0 2006.145.11:44:05.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.11:44:05.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.11:44:05.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.11:44:05.30#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.11:44:05.34#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.11:44:05.34#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.11:44:05.34#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.11:44:05.34#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.11:44:05.34$vck44/va=6,4 2006.145.11:44:05.34#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.11:44:05.34#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.11:44:05.34#ibcon#ireg 11 cls_cnt 2 2006.145.11:44:05.34#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.11:44:05.39#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.11:44:05.39#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.11:44:05.41#ibcon#[25=AT06-04\r\n] 2006.145.11:44:05.44#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.11:44:05.44#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.11:44:05.44#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.11:44:05.44#ibcon#ireg 7 cls_cnt 0 2006.145.11:44:05.44#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.11:44:05.56#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.11:44:05.56#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.11:44:05.58#ibcon#[25=USB\r\n] 2006.145.11:44:05.61#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.11:44:05.61#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.11:44:05.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.11:44:05.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.11:44:05.61$vck44/valo=7,864.99 2006.145.11:44:05.61#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.11:44:05.61#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.11:44:05.61#ibcon#ireg 17 cls_cnt 0 2006.145.11:44:05.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.11:44:05.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.11:44:05.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.11:44:05.63#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.11:44:05.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.11:44:05.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.11:44:05.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.11:44:05.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.11:44:05.67$vck44/va=7,4 2006.145.11:44:05.67#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.11:44:05.67#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.11:44:05.67#ibcon#ireg 11 cls_cnt 2 2006.145.11:44:05.67#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.11:44:05.73#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.11:44:05.73#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.11:44:05.75#ibcon#[25=AT07-04\r\n] 2006.145.11:44:05.78#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.11:44:05.78#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.11:44:05.78#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.11:44:05.78#ibcon#ireg 7 cls_cnt 0 2006.145.11:44:05.78#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.11:44:05.90#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.11:44:05.90#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.11:44:05.92#ibcon#[25=USB\r\n] 2006.145.11:44:05.95#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.11:44:05.95#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.11:44:05.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.11:44:05.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.11:44:05.95$vck44/valo=8,884.99 2006.145.11:44:05.95#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.11:44:05.95#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.11:44:05.95#ibcon#ireg 17 cls_cnt 0 2006.145.11:44:05.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.11:44:05.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.11:44:05.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.11:44:05.97#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.11:44:06.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.11:44:06.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.11:44:06.01#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.11:44:06.01#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.11:44:06.01$vck44/va=8,4 2006.145.11:44:06.01#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.11:44:06.01#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.11:44:06.01#ibcon#ireg 11 cls_cnt 2 2006.145.11:44:06.01#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.11:44:06.07#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.11:44:06.07#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.11:44:06.09#ibcon#[25=AT08-04\r\n] 2006.145.11:44:06.12#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.11:44:06.12#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.11:44:06.12#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.11:44:06.12#ibcon#ireg 7 cls_cnt 0 2006.145.11:44:06.12#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.11:44:06.24#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.11:44:06.24#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.11:44:06.26#ibcon#[25=USB\r\n] 2006.145.11:44:06.29#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.11:44:06.29#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.11:44:06.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.11:44:06.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.11:44:06.29$vck44/vblo=1,629.99 2006.145.11:44:06.29#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.11:44:06.29#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.11:44:06.29#ibcon#ireg 17 cls_cnt 0 2006.145.11:44:06.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.11:44:06.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.11:44:06.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.11:44:06.31#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.11:44:06.35#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.11:44:06.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.11:44:06.35#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.11:44:06.35#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.11:44:06.35$vck44/vb=1,3 2006.145.11:44:06.35#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.11:44:06.35#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.11:44:06.35#ibcon#ireg 11 cls_cnt 2 2006.145.11:44:06.35#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.11:44:06.35#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.11:44:06.35#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.11:44:06.37#ibcon#[27=AT01-03\r\n] 2006.145.11:44:06.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.11:44:06.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.11:44:06.40#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.11:44:06.40#ibcon#ireg 7 cls_cnt 0 2006.145.11:44:06.40#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.11:44:06.52#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.11:44:06.52#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.11:44:06.54#ibcon#[27=USB\r\n] 2006.145.11:44:06.57#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.11:44:06.57#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.11:44:06.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.11:44:06.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.11:44:06.57$vck44/vblo=2,634.99 2006.145.11:44:06.57#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.11:44:06.57#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.11:44:06.57#ibcon#ireg 17 cls_cnt 0 2006.145.11:44:06.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.11:44:06.57#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.11:44:06.57#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.11:44:06.59#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.11:44:06.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.11:44:06.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.11:44:06.63#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.11:44:06.63#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.11:44:06.63$vck44/vb=2,4 2006.145.11:44:06.63#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.11:44:06.63#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.11:44:06.63#ibcon#ireg 11 cls_cnt 2 2006.145.11:44:06.63#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.11:44:06.69#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.11:44:06.69#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.11:44:06.71#ibcon#[27=AT02-04\r\n] 2006.145.11:44:06.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.11:44:06.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.11:44:06.74#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.11:44:06.74#ibcon#ireg 7 cls_cnt 0 2006.145.11:44:06.74#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.11:44:06.86#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.11:44:06.86#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.11:44:06.88#ibcon#[27=USB\r\n] 2006.145.11:44:06.91#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.11:44:06.91#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.11:44:06.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.11:44:06.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.11:44:06.91$vck44/vblo=3,649.99 2006.145.11:44:06.91#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.11:44:06.91#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.11:44:06.91#ibcon#ireg 17 cls_cnt 0 2006.145.11:44:06.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.11:44:06.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.11:44:06.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.11:44:06.93#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.11:44:06.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.11:44:06.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.11:44:06.97#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.11:44:06.97#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.11:44:06.97$vck44/vb=3,4 2006.145.11:44:06.97#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.11:44:06.97#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.11:44:06.97#ibcon#ireg 11 cls_cnt 2 2006.145.11:44:06.97#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.11:44:07.03#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.11:44:07.03#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.11:44:07.05#ibcon#[27=AT03-04\r\n] 2006.145.11:44:07.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.11:44:07.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.11:44:07.08#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.11:44:07.08#ibcon#ireg 7 cls_cnt 0 2006.145.11:44:07.08#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.11:44:07.20#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.11:44:07.20#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.11:44:07.22#ibcon#[27=USB\r\n] 2006.145.11:44:07.25#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.11:44:07.25#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.11:44:07.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.11:44:07.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.11:44:07.25$vck44/vblo=4,679.99 2006.145.11:44:07.25#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.11:44:07.25#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.11:44:07.25#ibcon#ireg 17 cls_cnt 0 2006.145.11:44:07.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.11:44:07.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.11:44:07.25#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.11:44:07.27#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.11:44:07.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.11:44:07.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.11:44:07.31#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.11:44:07.31#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.11:44:07.31$vck44/vb=4,4 2006.145.11:44:07.31#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.11:44:07.31#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.11:44:07.31#ibcon#ireg 11 cls_cnt 2 2006.145.11:44:07.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.11:44:07.37#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.11:44:07.37#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.11:44:07.39#ibcon#[27=AT04-04\r\n] 2006.145.11:44:07.42#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.11:44:07.42#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.11:44:07.42#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.11:44:07.42#ibcon#ireg 7 cls_cnt 0 2006.145.11:44:07.42#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.11:44:07.54#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.11:44:07.54#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.11:44:07.56#ibcon#[27=USB\r\n] 2006.145.11:44:07.59#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.11:44:07.59#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.11:44:07.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.11:44:07.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.11:44:07.59$vck44/vblo=5,709.99 2006.145.11:44:07.59#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.11:44:07.59#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.11:44:07.59#ibcon#ireg 17 cls_cnt 0 2006.145.11:44:07.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.11:44:07.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.11:44:07.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.11:44:07.61#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.11:44:07.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.11:44:07.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.11:44:07.65#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.11:44:07.65#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.11:44:07.65$vck44/vb=5,4 2006.145.11:44:07.65#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.11:44:07.65#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.11:44:07.65#ibcon#ireg 11 cls_cnt 2 2006.145.11:44:07.65#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.11:44:07.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.11:44:07.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.11:44:07.73#ibcon#[27=AT05-04\r\n] 2006.145.11:44:07.76#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.11:44:07.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.11:44:07.76#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.11:44:07.76#ibcon#ireg 7 cls_cnt 0 2006.145.11:44:07.76#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.11:44:07.88#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.11:44:07.88#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.11:44:07.90#ibcon#[27=USB\r\n] 2006.145.11:44:07.93#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.11:44:07.93#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.11:44:07.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.11:44:07.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.11:44:07.93$vck44/vblo=6,719.99 2006.145.11:44:07.93#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.11:44:07.93#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.11:44:07.93#ibcon#ireg 17 cls_cnt 0 2006.145.11:44:07.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:44:07.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:44:07.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:44:07.95#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.11:44:07.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:44:07.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.11:44:07.99#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.11:44:07.99#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.11:44:07.99$vck44/vb=6,4 2006.145.11:44:07.99#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.11:44:07.99#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.11:44:07.99#ibcon#ireg 11 cls_cnt 2 2006.145.11:44:07.99#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.11:44:08.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.11:44:08.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.11:44:08.07#ibcon#[27=AT06-04\r\n] 2006.145.11:44:08.10#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.11:44:08.10#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.11:44:08.10#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.11:44:08.10#ibcon#ireg 7 cls_cnt 0 2006.145.11:44:08.10#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.11:44:08.22#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.11:44:08.22#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.11:44:08.24#ibcon#[27=USB\r\n] 2006.145.11:44:08.27#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.11:44:08.27#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.11:44:08.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.11:44:08.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.11:44:08.27$vck44/vblo=7,734.99 2006.145.11:44:08.27#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.11:44:08.27#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.11:44:08.27#ibcon#ireg 17 cls_cnt 0 2006.145.11:44:08.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.11:44:08.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.11:44:08.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.11:44:08.29#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.11:44:08.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.11:44:08.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.11:44:08.33#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.11:44:08.33#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.11:44:08.33$vck44/vb=7,4 2006.145.11:44:08.33#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.11:44:08.33#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.11:44:08.33#ibcon#ireg 11 cls_cnt 2 2006.145.11:44:08.33#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.11:44:08.39#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.11:44:08.39#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.11:44:08.41#ibcon#[27=AT07-04\r\n] 2006.145.11:44:08.44#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.11:44:08.44#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.11:44:08.44#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.11:44:08.44#ibcon#ireg 7 cls_cnt 0 2006.145.11:44:08.44#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.11:44:08.56#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.11:44:08.56#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.11:44:08.58#ibcon#[27=USB\r\n] 2006.145.11:44:08.61#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.11:44:08.61#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.11:44:08.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.11:44:08.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.11:44:08.61$vck44/vblo=8,744.99 2006.145.11:44:08.61#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.11:44:08.61#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.11:44:08.61#ibcon#ireg 17 cls_cnt 0 2006.145.11:44:08.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.11:44:08.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.11:44:08.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.11:44:08.63#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.11:44:08.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.11:44:08.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.11:44:08.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.11:44:08.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.11:44:08.67$vck44/vb=8,4 2006.145.11:44:08.67#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.11:44:08.67#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.11:44:08.67#ibcon#ireg 11 cls_cnt 2 2006.145.11:44:08.67#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.11:44:08.73#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.11:44:08.73#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.11:44:08.75#ibcon#[27=AT08-04\r\n] 2006.145.11:44:08.78#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.11:44:08.78#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.11:44:08.78#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.11:44:08.78#ibcon#ireg 7 cls_cnt 0 2006.145.11:44:08.78#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.11:44:08.90#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.11:44:08.90#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.11:44:08.92#ibcon#[27=USB\r\n] 2006.145.11:44:08.95#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.11:44:08.95#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.11:44:08.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.11:44:08.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.11:44:08.95$vck44/vabw=wide 2006.145.11:44:08.95#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.11:44:08.95#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.11:44:08.95#ibcon#ireg 8 cls_cnt 0 2006.145.11:44:08.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.11:44:08.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.11:44:08.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.11:44:08.97#ibcon#[25=BW32\r\n] 2006.145.11:44:09.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.11:44:09.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.11:44:09.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.11:44:09.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.11:44:09.00$vck44/vbbw=wide 2006.145.11:44:09.00#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.11:44:09.00#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.11:44:09.00#ibcon#ireg 8 cls_cnt 0 2006.145.11:44:09.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.11:44:09.07#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.11:44:09.07#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.11:44:09.09#ibcon#[27=BW32\r\n] 2006.145.11:44:09.12#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.11:44:09.12#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.11:44:09.12#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.11:44:09.12#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.11:44:09.12$setupk4/ifdk4 2006.145.11:44:09.12$ifdk4/lo= 2006.145.11:44:09.12$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.11:44:09.12$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.11:44:09.12$ifdk4/patch= 2006.145.11:44:09.12$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.11:44:09.12$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.11:44:09.12$setupk4/!*+20s 2006.145.11:44:13.38#abcon#<5=/05 2.0 3.7 16.38 711020.5\r\n> 2006.145.11:44:13.40#abcon#{5=INTERFACE CLEAR} 2006.145.11:44:13.46#abcon#[5=S1D000X0/0*\r\n] 2006.145.11:44:23.55#abcon#<5=/05 1.9 3.7 16.38 711020.5\r\n> 2006.145.11:44:23.57#abcon#{5=INTERFACE CLEAR} 2006.145.11:44:23.59$setupk4/"tpicd 2006.145.11:44:23.59$setupk4/echo=off 2006.145.11:44:23.59$setupk4/xlog=off 2006.145.11:44:23.59:!2006.145.11:46:04 2006.145.11:44:45.13#trakl#Source acquired 2006.145.11:44:46.13#flagr#flagr/antenna,acquired 2006.145.11:46:04.00:preob 2006.145.11:46:05.14/onsource/TRACKING 2006.145.11:46:05.14:!2006.145.11:46:14 2006.145.11:46:14.00:"tape 2006.145.11:46:14.00:"st=record 2006.145.11:46:14.00:data_valid=on 2006.145.11:46:14.00:midob 2006.145.11:46:14.14/onsource/TRACKING 2006.145.11:46:14.14/wx/16.36,1020.5,72 2006.145.11:46:14.29/cable/+6.5461E-03 2006.145.11:46:15.38/va/01,08,usb,yes,28,30 2006.145.11:46:15.38/va/02,07,usb,yes,30,31 2006.145.11:46:15.38/va/03,08,usb,yes,27,28 2006.145.11:46:15.38/va/04,07,usb,yes,31,33 2006.145.11:46:15.38/va/05,04,usb,yes,27,27 2006.145.11:46:15.38/va/06,04,usb,yes,30,30 2006.145.11:46:15.38/va/07,04,usb,yes,31,32 2006.145.11:46:15.38/va/08,04,usb,yes,26,31 2006.145.11:46:15.61/valo/01,524.99,yes,locked 2006.145.11:46:15.61/valo/02,534.99,yes,locked 2006.145.11:46:15.61/valo/03,564.99,yes,locked 2006.145.11:46:15.61/valo/04,624.99,yes,locked 2006.145.11:46:15.61/valo/05,734.99,yes,locked 2006.145.11:46:15.61/valo/06,814.99,yes,locked 2006.145.11:46:15.61/valo/07,864.99,yes,locked 2006.145.11:46:15.61/valo/08,884.99,yes,locked 2006.145.11:46:16.70/vb/01,03,usb,yes,35,33 2006.145.11:46:16.70/vb/02,04,usb,yes,31,31 2006.145.11:46:16.70/vb/03,04,usb,yes,28,31 2006.145.11:46:16.70/vb/04,04,usb,yes,32,31 2006.145.11:46:16.70/vb/05,04,usb,yes,25,27 2006.145.11:46:16.70/vb/06,04,usb,yes,29,25 2006.145.11:46:16.70/vb/07,04,usb,yes,29,28 2006.145.11:46:16.70/vb/08,04,usb,yes,27,30 2006.145.11:46:16.93/vblo/01,629.99,yes,locked 2006.145.11:46:16.93/vblo/02,634.99,yes,locked 2006.145.11:46:16.93/vblo/03,649.99,yes,locked 2006.145.11:46:16.93/vblo/04,679.99,yes,locked 2006.145.11:46:16.93/vblo/05,709.99,yes,locked 2006.145.11:46:16.93/vblo/06,719.99,yes,locked 2006.145.11:46:16.93/vblo/07,734.99,yes,locked 2006.145.11:46:16.93/vblo/08,744.99,yes,locked 2006.145.11:46:17.08/vabw/8 2006.145.11:46:17.23/vbbw/8 2006.145.11:46:17.32/xfe/off,on,15.5 2006.145.11:46:17.69/ifatt/23,28,28,28 2006.145.11:46:18.07/fmout-gps/S +5.2E-08 2006.145.11:46:18.11:!2006.145.11:49:14 2006.145.11:49:14.00:data_valid=off 2006.145.11:49:14.00:"et 2006.145.11:49:14.00:!+3s 2006.145.11:49:17.02:"tape 2006.145.11:49:17.02:postob 2006.145.11:49:17.18/cable/+6.5460E-03 2006.145.11:49:17.18/wx/16.31,1020.5,71 2006.145.11:49:18.07/fmout-gps/S +5.2E-08 2006.145.11:49:18.07:scan_name=145-1152,jd0605,100 2006.145.11:49:18.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.145.11:49:18.14#flagr#flagr/antenna,new-source 2006.145.11:49:19.14:checkk5 2006.145.11:49:19.57/chk_autoobs//k5ts1/ autoobs is running! 2006.145.11:49:20.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.11:49:20.45/chk_autoobs//k5ts3/ autoobs is running! 2006.145.11:49:20.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.11:49:21.32/chk_obsdata//k5ts1/T1451146??a.dat file size is correct (nominal:720MB, actual:716MB). 2006.145.11:49:21.78/chk_obsdata//k5ts2/T1451146??b.dat file size is correct (nominal:720MB, actual:716MB). 2006.145.11:49:22.22/chk_obsdata//k5ts3/T1451146??c.dat file size is correct (nominal:720MB, actual:716MB). 2006.145.11:49:22.64/chk_obsdata//k5ts4/T1451146??d.dat file size is correct (nominal:720MB, actual:716MB). 2006.145.11:49:23.39/k5log//k5ts1_log_newline 2006.145.11:49:24.14/k5log//k5ts2_log_newline 2006.145.11:49:24.89/k5log//k5ts3_log_newline 2006.145.11:49:25.64/k5log//k5ts4_log_newline 2006.145.11:49:25.66/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.11:49:25.66:setupk4=1 2006.145.11:49:25.66$setupk4/echo=on 2006.145.11:49:25.66$setupk4/pcalon 2006.145.11:49:25.66$pcalon/"no phase cal control is implemented here 2006.145.11:49:25.66$setupk4/"tpicd=stop 2006.145.11:49:25.66$setupk4/"rec=synch_on 2006.145.11:49:25.66$setupk4/"rec_mode=128 2006.145.11:49:25.66$setupk4/!* 2006.145.11:49:25.66$setupk4/recpk4 2006.145.11:49:25.66$recpk4/recpatch= 2006.145.11:49:25.67$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.11:49:25.67$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.11:49:25.67$setupk4/vck44 2006.145.11:49:25.67$vck44/valo=1,524.99 2006.145.11:49:25.67#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.11:49:25.67#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.11:49:25.67#ibcon#ireg 17 cls_cnt 0 2006.145.11:49:25.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.11:49:25.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.11:49:25.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.11:49:25.71#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.11:49:25.76#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.11:49:25.76#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.11:49:25.76#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.11:49:25.76#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.11:49:25.76$vck44/va=1,8 2006.145.11:49:25.76#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.11:49:25.76#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.11:49:25.76#ibcon#ireg 11 cls_cnt 2 2006.145.11:49:25.76#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.11:49:25.76#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.11:49:25.76#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.11:49:25.78#ibcon#[25=AT01-08\r\n] 2006.145.11:49:25.81#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.11:49:25.81#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.11:49:25.81#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.11:49:25.81#ibcon#ireg 7 cls_cnt 0 2006.145.11:49:25.81#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.11:49:25.93#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.11:49:25.93#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.11:49:25.95#ibcon#[25=USB\r\n] 2006.145.11:49:25.98#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.11:49:25.98#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.11:49:25.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.11:49:25.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.11:49:25.98$vck44/valo=2,534.99 2006.145.11:49:25.98#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.11:49:25.98#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.11:49:25.98#ibcon#ireg 17 cls_cnt 0 2006.145.11:49:25.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.11:49:25.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.11:49:25.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.11:49:26.01#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.11:49:26.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.11:49:26.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.11:49:26.05#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.11:49:26.05#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.11:49:26.05$vck44/va=2,7 2006.145.11:49:26.05#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.11:49:26.05#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.11:49:26.05#ibcon#ireg 11 cls_cnt 2 2006.145.11:49:26.05#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:49:26.10#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:49:26.10#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:49:26.12#ibcon#[25=AT02-07\r\n] 2006.145.11:49:26.15#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:49:26.15#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:49:26.15#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.11:49:26.15#ibcon#ireg 7 cls_cnt 0 2006.145.11:49:26.15#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:49:26.27#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:49:26.27#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:49:26.29#ibcon#[25=USB\r\n] 2006.145.11:49:26.32#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:49:26.32#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:49:26.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.11:49:26.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.11:49:26.32$vck44/valo=3,564.99 2006.145.11:49:26.32#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.11:49:26.32#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.11:49:26.32#ibcon#ireg 17 cls_cnt 0 2006.145.11:49:26.32#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:49:26.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:49:26.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:49:26.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.11:49:26.38#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:49:26.38#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:49:26.38#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.11:49:26.38#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.11:49:26.38$vck44/va=3,8 2006.145.11:49:26.38#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.11:49:26.38#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.11:49:26.38#ibcon#ireg 11 cls_cnt 2 2006.145.11:49:26.38#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.11:49:26.44#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.11:49:26.44#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.11:49:26.46#ibcon#[25=AT03-08\r\n] 2006.145.11:49:26.49#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.11:49:26.49#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.11:49:26.49#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.11:49:26.49#ibcon#ireg 7 cls_cnt 0 2006.145.11:49:26.49#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.11:49:26.61#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.11:49:26.61#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.11:49:26.63#ibcon#[25=USB\r\n] 2006.145.11:49:26.66#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.11:49:26.66#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.11:49:26.66#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.11:49:26.66#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.11:49:26.66$vck44/valo=4,624.99 2006.145.11:49:26.66#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.11:49:26.66#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.11:49:26.66#ibcon#ireg 17 cls_cnt 0 2006.145.11:49:26.66#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:49:26.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:49:26.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:49:26.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.11:49:26.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:49:26.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:49:26.72#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.11:49:26.72#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.11:49:26.72$vck44/va=4,7 2006.145.11:49:26.72#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.11:49:26.72#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.11:49:26.72#ibcon#ireg 11 cls_cnt 2 2006.145.11:49:26.72#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:49:26.78#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:49:26.78#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:49:26.80#ibcon#[25=AT04-07\r\n] 2006.145.11:49:26.83#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:49:26.83#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:49:26.83#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.11:49:26.83#ibcon#ireg 7 cls_cnt 0 2006.145.11:49:26.83#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:49:26.95#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:49:26.95#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:49:26.97#ibcon#[25=USB\r\n] 2006.145.11:49:27.00#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:49:27.00#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:49:27.00#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.11:49:27.00#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.11:49:27.00$vck44/valo=5,734.99 2006.145.11:49:27.00#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.11:49:27.00#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.11:49:27.00#ibcon#ireg 17 cls_cnt 0 2006.145.11:49:27.00#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:49:27.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:49:27.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:49:27.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.11:49:27.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:49:27.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:49:27.06#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.11:49:27.06#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.11:49:27.06$vck44/va=5,4 2006.145.11:49:27.06#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.11:49:27.06#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.11:49:27.06#ibcon#ireg 11 cls_cnt 2 2006.145.11:49:27.06#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:49:27.12#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:49:27.12#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:49:27.14#ibcon#[25=AT05-04\r\n] 2006.145.11:49:27.17#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:49:27.17#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:49:27.17#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.11:49:27.17#ibcon#ireg 7 cls_cnt 0 2006.145.11:49:27.17#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:49:27.29#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:49:27.29#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:49:27.31#ibcon#[25=USB\r\n] 2006.145.11:49:27.34#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:49:27.34#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:49:27.34#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.11:49:27.34#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.11:49:27.34$vck44/valo=6,814.99 2006.145.11:49:27.34#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.11:49:27.34#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.11:49:27.34#ibcon#ireg 17 cls_cnt 0 2006.145.11:49:27.34#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:49:27.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:49:27.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:49:27.36#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.11:49:27.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:49:27.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:49:27.40#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.11:49:27.40#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.11:49:27.40$vck44/va=6,4 2006.145.11:49:27.40#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.11:49:27.40#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.11:49:27.40#ibcon#ireg 11 cls_cnt 2 2006.145.11:49:27.40#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:49:27.46#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:49:27.46#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:49:27.48#ibcon#[25=AT06-04\r\n] 2006.145.11:49:27.51#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:49:27.51#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:49:27.51#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.11:49:27.51#ibcon#ireg 7 cls_cnt 0 2006.145.11:49:27.51#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:49:27.63#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:49:27.63#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:49:27.65#ibcon#[25=USB\r\n] 2006.145.11:49:27.68#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:49:27.68#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:49:27.68#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.11:49:27.68#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.11:49:27.68$vck44/valo=7,864.99 2006.145.11:49:27.68#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.11:49:27.68#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.11:49:27.68#ibcon#ireg 17 cls_cnt 0 2006.145.11:49:27.68#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:49:27.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:49:27.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:49:27.70#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.11:49:27.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:49:27.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:49:27.74#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.11:49:27.74#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.11:49:27.74$vck44/va=7,4 2006.145.11:49:27.74#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.11:49:27.74#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.11:49:27.74#ibcon#ireg 11 cls_cnt 2 2006.145.11:49:27.74#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.11:49:27.80#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.11:49:27.80#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.11:49:27.82#ibcon#[25=AT07-04\r\n] 2006.145.11:49:27.85#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.11:49:27.85#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.11:49:27.85#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.11:49:27.85#ibcon#ireg 7 cls_cnt 0 2006.145.11:49:27.85#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.11:49:27.97#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.11:49:27.97#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.11:49:27.99#ibcon#[25=USB\r\n] 2006.145.11:49:28.02#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.11:49:28.02#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.11:49:28.02#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.11:49:28.02#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.11:49:28.02$vck44/valo=8,884.99 2006.145.11:49:28.02#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.11:49:28.02#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.11:49:28.02#ibcon#ireg 17 cls_cnt 0 2006.145.11:49:28.02#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:49:28.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:49:28.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:49:28.04#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.11:49:28.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:49:28.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:49:28.08#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.11:49:28.08#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.11:49:28.08$vck44/va=8,4 2006.145.11:49:28.08#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.11:49:28.08#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.11:49:28.08#ibcon#ireg 11 cls_cnt 2 2006.145.11:49:28.08#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.11:49:28.14#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.11:49:28.14#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.11:49:28.16#ibcon#[25=AT08-04\r\n] 2006.145.11:49:28.19#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.11:49:28.19#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.11:49:28.19#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.11:49:28.19#ibcon#ireg 7 cls_cnt 0 2006.145.11:49:28.19#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.11:49:28.31#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.11:49:28.31#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.11:49:28.35#ibcon#[25=USB\r\n] 2006.145.11:49:28.38#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.11:49:28.38#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.11:49:28.38#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.11:49:28.38#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.11:49:28.38$vck44/vblo=1,629.99 2006.145.11:49:28.38#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.11:49:28.38#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.11:49:28.38#ibcon#ireg 17 cls_cnt 0 2006.145.11:49:28.38#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:49:28.38#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:49:28.38#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:49:28.40#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.11:49:28.44#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:49:28.44#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:49:28.44#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.11:49:28.44#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.11:49:28.44$vck44/vb=1,3 2006.145.11:49:28.44#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.11:49:28.44#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.11:49:28.44#ibcon#ireg 11 cls_cnt 2 2006.145.11:49:28.44#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.11:49:28.44#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.11:49:28.44#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.11:49:28.46#ibcon#[27=AT01-03\r\n] 2006.145.11:49:28.49#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.11:49:28.49#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.11:49:28.49#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.11:49:28.49#ibcon#ireg 7 cls_cnt 0 2006.145.11:49:28.49#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.11:49:28.61#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.11:49:28.61#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.11:49:28.63#ibcon#[27=USB\r\n] 2006.145.11:49:28.65#abcon#<5=/05 1.6 3.2 16.31 721020.5\r\n> 2006.145.11:49:28.66#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.11:49:28.66#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.11:49:28.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.11:49:28.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.11:49:28.66$vck44/vblo=2,634.99 2006.145.11:49:28.66#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.11:49:28.66#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.11:49:28.66#ibcon#ireg 17 cls_cnt 0 2006.145.11:49:28.66#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.11:49:28.66#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.11:49:28.66#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.11:49:28.67#abcon#{5=INTERFACE CLEAR} 2006.145.11:49:28.68#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.11:49:28.72#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.11:49:28.72#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.11:49:28.72#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.11:49:28.72#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.11:49:28.72$vck44/vb=2,4 2006.145.11:49:28.72#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.11:49:28.72#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.11:49:28.72#ibcon#ireg 11 cls_cnt 2 2006.145.11:49:28.72#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:49:28.73#abcon#[5=S1D000X0/0*\r\n] 2006.145.11:49:28.78#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:49:28.78#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:49:28.80#ibcon#[27=AT02-04\r\n] 2006.145.11:49:28.83#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:49:28.83#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.11:49:28.83#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.11:49:28.83#ibcon#ireg 7 cls_cnt 0 2006.145.11:49:28.83#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:49:28.95#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:49:28.95#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:49:28.97#ibcon#[27=USB\r\n] 2006.145.11:49:29.00#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:49:29.00#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.11:49:29.00#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.11:49:29.00#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.11:49:29.00$vck44/vblo=3,649.99 2006.145.11:49:29.00#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.11:49:29.00#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.11:49:29.00#ibcon#ireg 17 cls_cnt 0 2006.145.11:49:29.00#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:49:29.00#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:49:29.00#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:49:29.02#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.11:49:29.06#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:49:29.06#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.11:49:29.06#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.11:49:29.06#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.11:49:29.06$vck44/vb=3,4 2006.145.11:49:29.06#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.11:49:29.06#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.11:49:29.06#ibcon#ireg 11 cls_cnt 2 2006.145.11:49:29.06#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.11:49:29.12#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.11:49:29.12#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.11:49:29.14#ibcon#[27=AT03-04\r\n] 2006.145.11:49:29.17#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.11:49:29.17#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.11:49:29.17#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.11:49:29.17#ibcon#ireg 7 cls_cnt 0 2006.145.11:49:29.17#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.11:49:29.29#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.11:49:29.29#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.11:49:29.31#ibcon#[27=USB\r\n] 2006.145.11:49:29.34#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.11:49:29.34#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.11:49:29.34#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.11:49:29.34#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.11:49:29.34$vck44/vblo=4,679.99 2006.145.11:49:29.34#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.11:49:29.34#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.11:49:29.34#ibcon#ireg 17 cls_cnt 0 2006.145.11:49:29.34#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:49:29.34#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:49:29.34#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:49:29.36#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.11:49:29.40#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:49:29.40#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.11:49:29.40#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.11:49:29.40#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.11:49:29.40$vck44/vb=4,4 2006.145.11:49:29.40#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.11:49:29.40#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.11:49:29.40#ibcon#ireg 11 cls_cnt 2 2006.145.11:49:29.40#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:49:29.46#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:49:29.46#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:49:29.48#ibcon#[27=AT04-04\r\n] 2006.145.11:49:29.51#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:49:29.51#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.11:49:29.51#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.11:49:29.51#ibcon#ireg 7 cls_cnt 0 2006.145.11:49:29.51#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:49:29.63#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:49:29.63#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:49:29.65#ibcon#[27=USB\r\n] 2006.145.11:49:29.68#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:49:29.68#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.11:49:29.68#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.11:49:29.68#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.11:49:29.68$vck44/vblo=5,709.99 2006.145.11:49:29.68#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.11:49:29.68#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.11:49:29.68#ibcon#ireg 17 cls_cnt 0 2006.145.11:49:29.68#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:49:29.68#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:49:29.68#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:49:29.70#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.11:49:29.74#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:49:29.74#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.11:49:29.74#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.11:49:29.74#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.11:49:29.74$vck44/vb=5,4 2006.145.11:49:29.74#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.11:49:29.74#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.11:49:29.74#ibcon#ireg 11 cls_cnt 2 2006.145.11:49:29.74#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:49:29.80#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:49:29.80#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:49:29.82#ibcon#[27=AT05-04\r\n] 2006.145.11:49:29.85#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:49:29.85#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.11:49:29.85#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.11:49:29.85#ibcon#ireg 7 cls_cnt 0 2006.145.11:49:29.85#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:49:29.97#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:49:29.97#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:49:29.99#ibcon#[27=USB\r\n] 2006.145.11:49:30.02#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:49:30.02#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.11:49:30.02#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.11:49:30.02#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.11:49:30.02$vck44/vblo=6,719.99 2006.145.11:49:30.02#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.11:49:30.02#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.11:49:30.02#ibcon#ireg 17 cls_cnt 0 2006.145.11:49:30.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:49:30.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:49:30.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:49:30.04#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.11:49:30.08#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:49:30.08#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:49:30.08#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.11:49:30.08#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.11:49:30.08$vck44/vb=6,4 2006.145.11:49:30.08#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.11:49:30.08#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.11:49:30.08#ibcon#ireg 11 cls_cnt 2 2006.145.11:49:30.08#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:49:30.14#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:49:30.14#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:49:30.16#ibcon#[27=AT06-04\r\n] 2006.145.11:49:30.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:49:30.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.11:49:30.19#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.11:49:30.19#ibcon#ireg 7 cls_cnt 0 2006.145.11:49:30.19#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:49:30.31#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:49:30.31#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:49:30.33#ibcon#[27=USB\r\n] 2006.145.11:49:30.36#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:49:30.36#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.11:49:30.36#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.11:49:30.36#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.11:49:30.36$vck44/vblo=7,734.99 2006.145.11:49:30.36#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.11:49:30.36#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.11:49:30.36#ibcon#ireg 17 cls_cnt 0 2006.145.11:49:30.36#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:49:30.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:49:30.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:49:30.38#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.11:49:30.42#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:49:30.42#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.11:49:30.42#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.11:49:30.42#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.11:49:30.42$vck44/vb=7,4 2006.145.11:49:30.42#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.11:49:30.42#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.11:49:30.42#ibcon#ireg 11 cls_cnt 2 2006.145.11:49:30.42#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.11:49:30.48#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.11:49:30.48#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.11:49:30.50#ibcon#[27=AT07-04\r\n] 2006.145.11:49:30.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.11:49:30.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.11:49:30.53#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.11:49:30.53#ibcon#ireg 7 cls_cnt 0 2006.145.11:49:30.53#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.11:49:30.65#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.11:49:30.65#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.11:49:30.67#ibcon#[27=USB\r\n] 2006.145.11:49:30.70#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.11:49:30.70#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.11:49:30.70#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.11:49:30.70#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.11:49:30.70$vck44/vblo=8,744.99 2006.145.11:49:30.70#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.11:49:30.70#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.11:49:30.70#ibcon#ireg 17 cls_cnt 0 2006.145.11:49:30.70#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:49:30.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:49:30.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:49:30.72#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.11:49:30.76#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:49:30.76#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.11:49:30.76#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.11:49:30.76#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.11:49:30.76$vck44/vb=8,4 2006.145.11:49:30.76#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.11:49:30.76#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.11:49:30.76#ibcon#ireg 11 cls_cnt 2 2006.145.11:49:30.76#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.11:49:30.82#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.11:49:30.82#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.11:49:30.84#ibcon#[27=AT08-04\r\n] 2006.145.11:49:30.87#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.11:49:30.87#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.11:49:30.87#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.11:49:30.87#ibcon#ireg 7 cls_cnt 0 2006.145.11:49:30.87#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.11:49:30.99#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.11:49:30.99#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.11:49:31.01#ibcon#[27=USB\r\n] 2006.145.11:49:31.04#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.11:49:31.04#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.11:49:31.04#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.11:49:31.04#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.11:49:31.04$vck44/vabw=wide 2006.145.11:49:31.04#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.11:49:31.04#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.11:49:31.04#ibcon#ireg 8 cls_cnt 0 2006.145.11:49:31.04#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:49:31.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:49:31.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:49:31.06#ibcon#[25=BW32\r\n] 2006.145.11:49:31.09#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:49:31.09#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.11:49:31.09#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.11:49:31.09#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.11:49:31.09$vck44/vbbw=wide 2006.145.11:49:31.09#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.11:49:31.09#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.11:49:31.09#ibcon#ireg 8 cls_cnt 0 2006.145.11:49:31.09#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:49:31.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:49:31.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:49:31.18#ibcon#[27=BW32\r\n] 2006.145.11:49:31.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:49:31.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:49:31.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.11:49:31.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.11:49:31.21$setupk4/ifdk4 2006.145.11:49:31.21$ifdk4/lo= 2006.145.11:49:31.21$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.11:49:31.21$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.11:49:31.21$ifdk4/patch= 2006.145.11:49:31.21$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.11:49:31.21$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.11:49:31.21$setupk4/!*+20s 2006.145.11:49:38.82#abcon#<5=/05 1.6 3.2 16.31 721020.6\r\n> 2006.145.11:49:38.84#abcon#{5=INTERFACE CLEAR} 2006.145.11:49:38.92#abcon#[5=S1D000X0/0*\r\n] 2006.145.11:49:44.14#trakl#Source acquired 2006.145.11:49:45.14#flagr#flagr/antenna,acquired 2006.145.11:49:45.67$setupk4/"tpicd 2006.145.11:49:45.67$setupk4/echo=off 2006.145.11:49:45.67$setupk4/xlog=off 2006.145.11:49:45.67:!2006.145.11:51:50 2006.145.11:51:50.00:preob 2006.145.11:51:50.14/onsource/TRACKING 2006.145.11:51:50.14:!2006.145.11:52:00 2006.145.11:52:00.00:"tape 2006.145.11:52:00.00:"st=record 2006.145.11:52:00.00:data_valid=on 2006.145.11:52:00.00:midob 2006.145.11:52:00.14/onsource/TRACKING 2006.145.11:52:00.14/wx/16.27,1020.5,73 2006.145.11:52:00.22/cable/+6.5477E-03 2006.145.11:52:01.31/va/01,08,usb,yes,45,48 2006.145.11:52:01.31/va/02,07,usb,yes,48,49 2006.145.11:52:01.31/va/03,08,usb,yes,44,46 2006.145.11:52:01.31/va/04,07,usb,yes,50,53 2006.145.11:52:01.31/va/05,04,usb,yes,44,45 2006.145.11:52:01.31/va/06,04,usb,yes,49,49 2006.145.11:52:01.31/va/07,04,usb,yes,49,51 2006.145.11:52:01.31/va/08,04,usb,yes,42,50 2006.145.11:52:01.54/valo/01,524.99,yes,locked 2006.145.11:52:01.54/valo/02,534.99,yes,locked 2006.145.11:52:01.54/valo/03,564.99,yes,locked 2006.145.11:52:01.54/valo/04,624.99,yes,locked 2006.145.11:52:01.54/valo/05,734.99,yes,locked 2006.145.11:52:01.54/valo/06,814.99,yes,locked 2006.145.11:52:01.54/valo/07,864.99,yes,locked 2006.145.11:52:01.54/valo/08,884.99,yes,locked 2006.145.11:52:02.63/vb/01,03,usb,yes,50,49 2006.145.11:52:02.63/vb/02,04,usb,yes,44,45 2006.145.11:52:02.63/vb/03,04,usb,yes,40,45 2006.145.11:52:02.63/vb/04,04,usb,yes,46,45 2006.145.11:52:02.63/vb/05,04,usb,yes,37,40 2006.145.11:52:02.63/vb/06,04,usb,yes,43,38 2006.145.11:52:02.63/vb/07,04,usb,yes,42,42 2006.145.11:52:02.63/vb/08,04,usb,yes,38,43 2006.145.11:52:02.86/vblo/01,629.99,yes,locked 2006.145.11:52:02.86/vblo/02,634.99,yes,locked 2006.145.11:52:02.86/vblo/03,649.99,yes,locked 2006.145.11:52:02.86/vblo/04,679.99,yes,locked 2006.145.11:52:02.86/vblo/05,709.99,yes,locked 2006.145.11:52:02.86/vblo/06,719.99,yes,locked 2006.145.11:52:02.86/vblo/07,734.99,yes,locked 2006.145.11:52:02.86/vblo/08,744.99,yes,locked 2006.145.11:52:03.01/vabw/8 2006.145.11:52:03.16/vbbw/8 2006.145.11:52:03.29/xfe/off,on,14.2 2006.145.11:52:03.66/ifatt/23,28,28,28 2006.145.11:52:04.07/fmout-gps/S +5.1E-08 2006.145.11:52:04.11:!2006.145.11:53:40 2006.145.11:53:40.00:data_valid=off 2006.145.11:53:40.00:"et 2006.145.11:53:40.00:!+3s 2006.145.11:53:43.02:"tape 2006.145.11:53:43.02:postob 2006.145.11:53:43.17/cable/+6.5464E-03 2006.145.11:53:43.21/wx/16.24,1020.6,73 2006.145.11:53:44.08/fmout-gps/S +5.2E-08 2006.145.11:53:44.08:scan_name=145-1154,jd0605,200 2006.145.11:53:44.08:source=0014+813,001708.47,813508.1,2000.0,neutral 2006.145.11:53:45.13#flagr#flagr/antenna,new-source 2006.145.11:53:45.13:checkk5 2006.145.11:53:45.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.11:53:46.04/chk_autoobs//k5ts2/ autoobs is running! 2006.145.11:53:46.48/chk_autoobs//k5ts3/ autoobs is running! 2006.145.11:53:46.92/chk_autoobs//k5ts4/ autoobs is running! 2006.145.11:53:47.35/chk_obsdata//k5ts1/T1451152??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.11:53:47.80/chk_obsdata//k5ts2/T1451152??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.11:53:48.23/chk_obsdata//k5ts3/T1451152??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.11:53:48.68/chk_obsdata//k5ts4/T1451152??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.11:53:49.43/k5log//k5ts1_log_newline 2006.145.11:53:50.19/k5log//k5ts2_log_newline 2006.145.11:53:50.93/k5log//k5ts3_log_newline 2006.145.11:53:51.66/k5log//k5ts4_log_newline 2006.145.11:53:51.68/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.11:53:51.68:setupk4=1 2006.145.11:53:51.68$setupk4/echo=on 2006.145.11:53:51.68$setupk4/pcalon 2006.145.11:53:51.68$pcalon/"no phase cal control is implemented here 2006.145.11:53:51.68$setupk4/"tpicd=stop 2006.145.11:53:51.68$setupk4/"rec=synch_on 2006.145.11:53:51.68$setupk4/"rec_mode=128 2006.145.11:53:51.68$setupk4/!* 2006.145.11:53:51.68$setupk4/recpk4 2006.145.11:53:51.68$recpk4/recpatch= 2006.145.11:53:51.69$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.11:53:51.69$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.11:53:51.69$setupk4/vck44 2006.145.11:53:51.69$vck44/valo=1,524.99 2006.145.11:53:51.69#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.11:53:51.69#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.11:53:51.69#ibcon#ireg 17 cls_cnt 0 2006.145.11:53:51.69#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.11:53:51.69#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.11:53:51.69#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.11:53:51.73#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.11:53:51.78#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.11:53:51.78#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.11:53:51.78#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.11:53:51.78#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.11:53:51.78$vck44/va=1,8 2006.145.11:53:51.78#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.11:53:51.78#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.11:53:51.78#ibcon#ireg 11 cls_cnt 2 2006.145.11:53:51.78#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.11:53:51.78#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.11:53:51.78#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.11:53:51.80#ibcon#[25=AT01-08\r\n] 2006.145.11:53:51.83#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.11:53:51.83#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.11:53:51.83#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.11:53:51.83#ibcon#ireg 7 cls_cnt 0 2006.145.11:53:51.83#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.11:53:51.95#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.11:53:51.95#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.11:53:51.97#ibcon#[25=USB\r\n] 2006.145.11:53:52.00#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.11:53:52.00#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.11:53:52.00#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.11:53:52.00#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.11:53:52.00$vck44/valo=2,534.99 2006.145.11:53:52.00#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.11:53:52.00#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.11:53:52.00#ibcon#ireg 17 cls_cnt 0 2006.145.11:53:52.00#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.11:53:52.00#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.11:53:52.00#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.11:53:52.03#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.11:53:52.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.11:53:52.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.11:53:52.07#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.11:53:52.07#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.11:53:52.07$vck44/va=2,7 2006.145.11:53:52.07#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.11:53:52.07#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.11:53:52.07#ibcon#ireg 11 cls_cnt 2 2006.145.11:53:52.07#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.11:53:52.12#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.11:53:52.12#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.11:53:52.14#ibcon#[25=AT02-07\r\n] 2006.145.11:53:52.17#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.11:53:52.17#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.11:53:52.17#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.11:53:52.17#ibcon#ireg 7 cls_cnt 0 2006.145.11:53:52.17#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.11:53:52.29#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.11:53:52.29#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.11:53:52.31#ibcon#[25=USB\r\n] 2006.145.11:53:52.34#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.11:53:52.34#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.11:53:52.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.11:53:52.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.11:53:52.34$vck44/valo=3,564.99 2006.145.11:53:52.34#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.11:53:52.34#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.11:53:52.34#ibcon#ireg 17 cls_cnt 0 2006.145.11:53:52.34#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.11:53:52.34#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.11:53:52.34#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.11:53:52.36#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.11:53:52.40#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.11:53:52.40#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.11:53:52.40#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.11:53:52.40#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.11:53:52.40$vck44/va=3,8 2006.145.11:53:52.40#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.11:53:52.40#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.11:53:52.40#ibcon#ireg 11 cls_cnt 2 2006.145.11:53:52.40#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.11:53:52.46#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.11:53:52.46#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.11:53:52.48#ibcon#[25=AT03-08\r\n] 2006.145.11:53:52.51#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.11:53:52.51#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.11:53:52.51#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.11:53:52.51#ibcon#ireg 7 cls_cnt 0 2006.145.11:53:52.51#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.11:53:52.63#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.11:53:52.63#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.11:53:52.65#ibcon#[25=USB\r\n] 2006.145.11:53:52.68#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.11:53:52.68#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.11:53:52.68#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.11:53:52.68#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.11:53:52.68$vck44/valo=4,624.99 2006.145.11:53:52.68#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.11:53:52.68#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.11:53:52.68#ibcon#ireg 17 cls_cnt 0 2006.145.11:53:52.68#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.11:53:52.68#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.11:53:52.68#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.11:53:52.70#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.11:53:52.74#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.11:53:52.74#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.11:53:52.74#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.11:53:52.74#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.11:53:52.74$vck44/va=4,7 2006.145.11:53:52.74#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.11:53:52.74#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.11:53:52.74#ibcon#ireg 11 cls_cnt 2 2006.145.11:53:52.74#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.11:53:52.80#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.11:53:52.80#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.11:53:52.82#ibcon#[25=AT04-07\r\n] 2006.145.11:53:52.85#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.11:53:52.85#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.11:53:52.85#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.11:53:52.85#ibcon#ireg 7 cls_cnt 0 2006.145.11:53:52.85#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.11:53:52.97#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.11:53:52.97#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.11:53:52.99#ibcon#[25=USB\r\n] 2006.145.11:53:53.02#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.11:53:53.02#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.11:53:53.02#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.11:53:53.02#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.11:53:53.02$vck44/valo=5,734.99 2006.145.11:53:53.02#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.11:53:53.02#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.11:53:53.02#ibcon#ireg 17 cls_cnt 0 2006.145.11:53:53.02#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.11:53:53.02#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.11:53:53.02#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.11:53:53.04#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.11:53:53.08#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.11:53:53.08#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.11:53:53.08#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.11:53:53.08#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.11:53:53.08$vck44/va=5,4 2006.145.11:53:53.08#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.11:53:53.08#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.11:53:53.08#ibcon#ireg 11 cls_cnt 2 2006.145.11:53:53.08#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.11:53:53.14#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.11:53:53.14#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.11:53:53.16#ibcon#[25=AT05-04\r\n] 2006.145.11:53:53.19#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.11:53:53.19#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.11:53:53.19#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.11:53:53.19#ibcon#ireg 7 cls_cnt 0 2006.145.11:53:53.19#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.11:53:53.21#abcon#<5=/05 1.5 2.8 16.24 731020.5\r\n> 2006.145.11:53:53.23#abcon#{5=INTERFACE CLEAR} 2006.145.11:53:53.29#abcon#[5=S1D000X0/0*\r\n] 2006.145.11:53:53.31#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.11:53:53.31#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.11:53:53.33#ibcon#[25=USB\r\n] 2006.145.11:53:53.37#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.11:53:53.37#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.11:53:53.37#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.11:53:53.37#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.11:53:53.37$vck44/valo=6,814.99 2006.145.11:53:53.37#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.11:53:53.37#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.11:53:53.37#ibcon#ireg 17 cls_cnt 0 2006.145.11:53:53.37#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.11:53:53.37#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.11:53:53.37#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.11:53:53.40#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.11:53:53.44#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.11:53:53.44#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.11:53:53.44#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.11:53:53.44#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.11:53:53.44$vck44/va=6,4 2006.145.11:53:53.44#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.11:53:53.44#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.11:53:53.44#ibcon#ireg 11 cls_cnt 2 2006.145.11:53:53.44#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.11:53:53.49#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.11:53:53.49#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.11:53:53.51#ibcon#[25=AT06-04\r\n] 2006.145.11:53:53.54#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.11:53:53.54#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.11:53:53.54#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.11:53:53.54#ibcon#ireg 7 cls_cnt 0 2006.145.11:53:53.54#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.11:53:53.66#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.11:53:53.66#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.11:53:53.68#ibcon#[25=USB\r\n] 2006.145.11:53:53.71#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.11:53:53.71#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.11:53:53.71#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.11:53:53.71#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.11:53:53.71$vck44/valo=7,864.99 2006.145.11:53:53.71#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.11:53:53.71#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.11:53:53.71#ibcon#ireg 17 cls_cnt 0 2006.145.11:53:53.71#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.11:53:53.71#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.11:53:53.71#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.11:53:53.73#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.11:53:53.77#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.11:53:53.77#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.11:53:53.77#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.11:53:53.77#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.11:53:53.77$vck44/va=7,4 2006.145.11:53:53.77#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.11:53:53.77#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.11:53:53.77#ibcon#ireg 11 cls_cnt 2 2006.145.11:53:53.77#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.11:53:53.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.11:53:53.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.11:53:53.85#ibcon#[25=AT07-04\r\n] 2006.145.11:53:53.88#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.11:53:53.88#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.11:53:53.88#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.11:53:53.88#ibcon#ireg 7 cls_cnt 0 2006.145.11:53:53.88#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.11:53:54.00#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.11:53:54.00#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.11:53:54.02#ibcon#[25=USB\r\n] 2006.145.11:53:54.05#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.11:53:54.05#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.11:53:54.05#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.11:53:54.05#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.11:53:54.05$vck44/valo=8,884.99 2006.145.11:53:54.05#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.11:53:54.05#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.11:53:54.05#ibcon#ireg 17 cls_cnt 0 2006.145.11:53:54.05#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.11:53:54.05#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.11:53:54.05#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.11:53:54.07#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.11:53:54.11#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.11:53:54.11#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.11:53:54.11#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.11:53:54.11#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.11:53:54.11$vck44/va=8,4 2006.145.11:53:54.11#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.11:53:54.11#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.11:53:54.11#ibcon#ireg 11 cls_cnt 2 2006.145.11:53:54.11#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.11:53:54.17#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.11:53:54.17#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.11:53:54.19#ibcon#[25=AT08-04\r\n] 2006.145.11:53:54.22#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.11:53:54.22#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.11:53:54.22#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.11:53:54.22#ibcon#ireg 7 cls_cnt 0 2006.145.11:53:54.22#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.11:53:54.34#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.11:53:54.34#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.11:53:54.36#ibcon#[25=USB\r\n] 2006.145.11:53:54.39#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.11:53:54.39#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.11:53:54.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.11:53:54.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.11:53:54.39$vck44/vblo=1,629.99 2006.145.11:53:54.39#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.11:53:54.39#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.11:53:54.39#ibcon#ireg 17 cls_cnt 0 2006.145.11:53:54.39#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.11:53:54.39#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.11:53:54.39#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.11:53:54.41#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.11:53:54.45#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.11:53:54.45#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.11:53:54.45#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.11:53:54.45#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.11:53:54.45$vck44/vb=1,3 2006.145.11:53:54.45#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.11:53:54.45#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.11:53:54.45#ibcon#ireg 11 cls_cnt 2 2006.145.11:53:54.45#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.11:53:54.45#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.11:53:54.45#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.11:53:54.47#ibcon#[27=AT01-03\r\n] 2006.145.11:53:54.50#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.11:53:54.50#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.11:53:54.50#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.11:53:54.50#ibcon#ireg 7 cls_cnt 0 2006.145.11:53:54.50#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.11:53:54.62#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.11:53:54.62#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.11:53:54.64#ibcon#[27=USB\r\n] 2006.145.11:53:54.67#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.11:53:54.67#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.11:53:54.67#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.11:53:54.67#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.11:53:54.67$vck44/vblo=2,634.99 2006.145.11:53:54.67#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.11:53:54.67#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.11:53:54.67#ibcon#ireg 17 cls_cnt 0 2006.145.11:53:54.67#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.11:53:54.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.11:53:54.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.11:53:54.69#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.11:53:54.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.11:53:54.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.11:53:54.73#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.11:53:54.73#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.11:53:54.73$vck44/vb=2,4 2006.145.11:53:54.73#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.11:53:54.73#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.11:53:54.73#ibcon#ireg 11 cls_cnt 2 2006.145.11:53:54.73#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.11:53:54.79#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.11:53:54.79#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.11:53:54.81#ibcon#[27=AT02-04\r\n] 2006.145.11:53:54.84#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.11:53:54.84#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.11:53:54.84#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.11:53:54.84#ibcon#ireg 7 cls_cnt 0 2006.145.11:53:54.84#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.11:53:54.96#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.11:53:54.96#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.11:53:54.98#ibcon#[27=USB\r\n] 2006.145.11:53:55.01#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.11:53:55.01#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.11:53:55.01#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.11:53:55.01#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.11:53:55.01$vck44/vblo=3,649.99 2006.145.11:53:55.01#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.11:53:55.01#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.11:53:55.01#ibcon#ireg 17 cls_cnt 0 2006.145.11:53:55.01#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.11:53:55.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.11:53:55.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.11:53:55.03#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.11:53:55.07#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.11:53:55.07#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.11:53:55.07#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.11:53:55.07#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.11:53:55.07$vck44/vb=3,4 2006.145.11:53:55.07#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.11:53:55.07#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.11:53:55.07#ibcon#ireg 11 cls_cnt 2 2006.145.11:53:55.07#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.11:53:55.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.11:53:55.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.11:53:55.15#ibcon#[27=AT03-04\r\n] 2006.145.11:53:55.18#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.11:53:55.18#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.11:53:55.18#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.11:53:55.18#ibcon#ireg 7 cls_cnt 0 2006.145.11:53:55.18#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.11:53:55.30#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.11:53:55.30#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.11:53:55.32#ibcon#[27=USB\r\n] 2006.145.11:53:55.35#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.11:53:55.35#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.11:53:55.35#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.11:53:55.35#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.11:53:55.35$vck44/vblo=4,679.99 2006.145.11:53:55.35#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.11:53:55.35#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.11:53:55.35#ibcon#ireg 17 cls_cnt 0 2006.145.11:53:55.35#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.11:53:55.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.11:53:55.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.11:53:55.37#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.11:53:55.41#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.11:53:55.41#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.11:53:55.41#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.11:53:55.41#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.11:53:55.41$vck44/vb=4,4 2006.145.11:53:55.41#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.11:53:55.41#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.11:53:55.41#ibcon#ireg 11 cls_cnt 2 2006.145.11:53:55.41#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.11:53:55.47#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.11:53:55.47#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.11:53:55.49#ibcon#[27=AT04-04\r\n] 2006.145.11:53:55.52#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.11:53:55.52#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.11:53:55.52#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.11:53:55.52#ibcon#ireg 7 cls_cnt 0 2006.145.11:53:55.52#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.11:53:55.64#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.11:53:55.64#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.11:53:55.66#ibcon#[27=USB\r\n] 2006.145.11:53:55.69#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.11:53:55.69#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.11:53:55.69#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.11:53:55.69#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.11:53:55.69$vck44/vblo=5,709.99 2006.145.11:53:55.69#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.11:53:55.69#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.11:53:55.69#ibcon#ireg 17 cls_cnt 0 2006.145.11:53:55.69#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.11:53:55.69#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.11:53:55.69#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.11:53:55.71#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.11:53:55.75#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.11:53:55.75#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.11:53:55.75#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.11:53:55.75#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.11:53:55.75$vck44/vb=5,4 2006.145.11:53:55.75#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.11:53:55.75#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.11:53:55.75#ibcon#ireg 11 cls_cnt 2 2006.145.11:53:55.75#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.11:53:55.81#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.11:53:55.81#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.11:53:55.83#ibcon#[27=AT05-04\r\n] 2006.145.11:53:55.86#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.11:53:55.86#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.11:53:55.86#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.11:53:55.86#ibcon#ireg 7 cls_cnt 0 2006.145.11:53:55.86#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.11:53:55.98#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.11:53:55.98#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.11:53:56.00#ibcon#[27=USB\r\n] 2006.145.11:53:56.03#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.11:53:56.03#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.11:53:56.03#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.11:53:56.03#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.11:53:56.03$vck44/vblo=6,719.99 2006.145.11:53:56.03#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.11:53:56.03#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.11:53:56.03#ibcon#ireg 17 cls_cnt 0 2006.145.11:53:56.03#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.11:53:56.03#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.11:53:56.03#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.11:53:56.05#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.11:53:56.09#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.11:53:56.09#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.11:53:56.09#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.11:53:56.09#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.11:53:56.09$vck44/vb=6,4 2006.145.11:53:56.09#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.11:53:56.09#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.11:53:56.09#ibcon#ireg 11 cls_cnt 2 2006.145.11:53:56.09#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.11:53:56.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.11:53:56.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.11:53:56.17#ibcon#[27=AT06-04\r\n] 2006.145.11:53:56.20#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.11:53:56.20#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.11:53:56.20#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.11:53:56.20#ibcon#ireg 7 cls_cnt 0 2006.145.11:53:56.20#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.11:53:56.32#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.11:53:56.32#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.11:53:56.34#ibcon#[27=USB\r\n] 2006.145.11:53:56.37#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.11:53:56.37#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.11:53:56.37#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.11:53:56.37#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.11:53:56.37$vck44/vblo=7,734.99 2006.145.11:53:56.37#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.11:53:56.37#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.11:53:56.37#ibcon#ireg 17 cls_cnt 0 2006.145.11:53:56.37#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.11:53:56.37#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.11:53:56.37#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.11:53:56.39#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.11:53:56.43#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.11:53:56.43#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.11:53:56.43#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.11:53:56.43#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.11:53:56.43$vck44/vb=7,4 2006.145.11:53:56.43#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.11:53:56.43#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.11:53:56.43#ibcon#ireg 11 cls_cnt 2 2006.145.11:53:56.43#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.11:53:56.49#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.11:53:56.49#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.11:53:56.51#ibcon#[27=AT07-04\r\n] 2006.145.11:53:56.54#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.11:53:56.54#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.11:53:56.54#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.11:53:56.54#ibcon#ireg 7 cls_cnt 0 2006.145.11:53:56.54#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.11:53:56.66#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.11:53:56.66#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.11:53:56.68#ibcon#[27=USB\r\n] 2006.145.11:53:56.71#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.11:53:56.71#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.11:53:56.71#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.11:53:56.71#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.11:53:56.71$vck44/vblo=8,744.99 2006.145.11:53:56.71#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.11:53:56.71#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.11:53:56.71#ibcon#ireg 17 cls_cnt 0 2006.145.11:53:56.71#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.11:53:56.71#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.11:53:56.71#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.11:53:56.73#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.11:53:56.77#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.11:53:56.77#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.11:53:56.77#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.11:53:56.77#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.11:53:56.77$vck44/vb=8,4 2006.145.11:53:56.77#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.11:53:56.77#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.11:53:56.77#ibcon#ireg 11 cls_cnt 2 2006.145.11:53:56.77#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.11:53:56.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.11:53:56.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.11:53:56.85#ibcon#[27=AT08-04\r\n] 2006.145.11:53:56.88#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.11:53:56.88#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.11:53:56.88#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.11:53:56.88#ibcon#ireg 7 cls_cnt 0 2006.145.11:53:56.88#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.11:53:57.00#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.11:53:57.00#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.11:53:57.02#ibcon#[27=USB\r\n] 2006.145.11:53:57.05#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.11:53:57.05#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.11:53:57.05#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.11:53:57.05#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.11:53:57.05$vck44/vabw=wide 2006.145.11:53:57.05#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.11:53:57.05#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.11:53:57.05#ibcon#ireg 8 cls_cnt 0 2006.145.11:53:57.05#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.11:53:57.05#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.11:53:57.05#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.11:53:57.07#ibcon#[25=BW32\r\n] 2006.145.11:53:57.10#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.11:53:57.10#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.11:53:57.10#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.11:53:57.10#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.11:53:57.10$vck44/vbbw=wide 2006.145.11:53:57.10#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.11:53:57.10#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.11:53:57.10#ibcon#ireg 8 cls_cnt 0 2006.145.11:53:57.10#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.11:53:57.17#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.11:53:57.17#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.11:53:57.19#ibcon#[27=BW32\r\n] 2006.145.11:53:57.22#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.11:53:57.22#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.11:53:57.22#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.11:53:57.22#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.11:53:57.22$setupk4/ifdk4 2006.145.11:53:57.22$ifdk4/lo= 2006.145.11:53:57.22$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.11:53:57.22$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.11:53:57.22$ifdk4/patch= 2006.145.11:53:57.22$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.11:53:57.22$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.11:53:57.22$setupk4/!*+20s 2006.145.11:54:03.38#abcon#<5=/05 1.5 2.8 16.24 731020.6\r\n> 2006.145.11:54:03.40#abcon#{5=INTERFACE CLEAR} 2006.145.11:54:03.46#abcon#[5=S1D000X0/0*\r\n] 2006.145.11:54:10.14#trakl#Source acquired 2006.145.11:54:10.14#flagr#flagr/antenna,acquired 2006.145.11:54:11.69$setupk4/"tpicd 2006.145.11:54:11.69$setupk4/echo=off 2006.145.11:54:11.69$setupk4/xlog=off 2006.145.11:54:11.69:!2006.145.11:54:30 2006.145.11:54:30.00:preob 2006.145.11:54:30.14/onsource/TRACKING 2006.145.11:54:30.14:!2006.145.11:54:40 2006.145.11:54:40.00:"tape 2006.145.11:54:40.00:"st=record 2006.145.11:54:40.00:data_valid=on 2006.145.11:54:40.00:midob 2006.145.11:54:40.14/onsource/TRACKING 2006.145.11:54:40.14/wx/16.23,1020.5,73 2006.145.11:54:40.21/cable/+6.5460E-03 2006.145.11:54:41.30/va/01,08,usb,yes,29,31 2006.145.11:54:41.30/va/02,07,usb,yes,31,32 2006.145.11:54:41.30/va/03,08,usb,yes,28,29 2006.145.11:54:41.30/va/04,07,usb,yes,32,33 2006.145.11:54:41.30/va/05,04,usb,yes,28,28 2006.145.11:54:41.30/va/06,04,usb,yes,31,31 2006.145.11:54:41.30/va/07,04,usb,yes,31,33 2006.145.11:54:41.30/va/08,04,usb,yes,27,32 2006.145.11:54:41.53/valo/01,524.99,yes,locked 2006.145.11:54:41.53/valo/02,534.99,yes,locked 2006.145.11:54:41.53/valo/03,564.99,yes,locked 2006.145.11:54:41.53/valo/04,624.99,yes,locked 2006.145.11:54:41.53/valo/05,734.99,yes,locked 2006.145.11:54:41.53/valo/06,814.99,yes,locked 2006.145.11:54:41.53/valo/07,864.99,yes,locked 2006.145.11:54:41.53/valo/08,884.99,yes,locked 2006.145.11:54:42.62/vb/01,03,usb,yes,36,33 2006.145.11:54:42.62/vb/02,04,usb,yes,31,31 2006.145.11:54:42.62/vb/03,04,usb,yes,28,31 2006.145.11:54:42.62/vb/04,04,usb,yes,33,31 2006.145.11:54:42.62/vb/05,04,usb,yes,25,28 2006.145.11:54:42.62/vb/06,04,usb,yes,30,26 2006.145.11:54:42.62/vb/07,04,usb,yes,29,29 2006.145.11:54:42.62/vb/08,04,usb,yes,27,30 2006.145.11:54:42.85/vblo/01,629.99,yes,locked 2006.145.11:54:42.85/vblo/02,634.99,yes,locked 2006.145.11:54:42.85/vblo/03,649.99,yes,locked 2006.145.11:54:42.85/vblo/04,679.99,yes,locked 2006.145.11:54:42.85/vblo/05,709.99,yes,locked 2006.145.11:54:42.85/vblo/06,719.99,yes,locked 2006.145.11:54:42.85/vblo/07,734.99,yes,locked 2006.145.11:54:42.85/vblo/08,744.99,yes,locked 2006.145.11:54:43.00/vabw/8 2006.145.11:54:43.15/vbbw/8 2006.145.11:54:43.24/xfe/off,on,15.0 2006.145.11:54:43.63/ifatt/23,28,28,28 2006.145.11:54:44.08/fmout-gps/S +5.1E-08 2006.145.11:54:44.12:!2006.145.11:58:00 2006.145.11:58:00.02:data_valid=off 2006.145.11:58:00.02:"et 2006.145.11:58:00.02:!+3s 2006.145.11:58:03.05:"tape 2006.145.11:58:03.09:postob 2006.145.11:58:03.17/cable/+6.5450E-03 2006.145.11:58:03.18/wx/16.17,1020.6,74 2006.145.11:58:03.25/fmout-gps/S +5.1E-08 2006.145.11:58:03.25:scan_name=145-1208,jd0605,400 2006.145.11:58:03.25:source=1308+326,131028.66,322043.8,2000.0,ccw 2006.145.11:58:04.15#flagr#flagr/antenna,new-source 2006.145.11:58:04.15:checkk5 2006.145.11:58:04.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.11:58:05.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.11:58:05.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.11:58:05.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.11:58:06.32/chk_obsdata//k5ts1/T1451154??a.dat file size is correct (nominal:800MB, actual:796MB). 2006.145.11:58:06.77/chk_obsdata//k5ts2/T1451154??b.dat file size is correct (nominal:800MB, actual:796MB). 2006.145.11:58:07.18/chk_obsdata//k5ts3/T1451154??c.dat file size is correct (nominal:800MB, actual:796MB). 2006.145.11:58:07.62/chk_obsdata//k5ts4/T1451154??d.dat file size is correct (nominal:800MB, actual:796MB). 2006.145.11:58:08.39/k5log//k5ts1_log_newline 2006.145.11:58:09.14/k5log//k5ts2_log_newline 2006.145.11:58:09.89/k5log//k5ts3_log_newline 2006.145.11:58:10.63/k5log//k5ts4_log_newline 2006.145.11:58:10.65/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.11:58:10.65:setupk4=1 2006.145.11:58:10.65$setupk4/echo=on 2006.145.11:58:10.65$setupk4/pcalon 2006.145.11:58:10.65$pcalon/"no phase cal control is implemented here 2006.145.11:58:10.65$setupk4/"tpicd=stop 2006.145.11:58:10.65$setupk4/"rec=synch_on 2006.145.11:58:10.66$setupk4/"rec_mode=128 2006.145.11:58:10.66$setupk4/!* 2006.145.11:58:10.66$setupk4/recpk4 2006.145.11:58:10.66$recpk4/recpatch= 2006.145.11:58:10.66$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.11:58:10.66$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.11:58:10.66$setupk4/vck44 2006.145.11:58:10.66$vck44/valo=1,524.99 2006.145.11:58:10.66#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.11:58:10.66#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.11:58:10.66#ibcon#ireg 17 cls_cnt 0 2006.145.11:58:10.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:58:10.66#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:58:10.66#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:58:10.72#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.11:58:10.76#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:58:10.76#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:58:10.76#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.11:58:10.76#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.11:58:10.77$vck44/va=1,8 2006.145.11:58:10.77#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.11:58:10.77#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.11:58:10.77#ibcon#ireg 11 cls_cnt 2 2006.145.11:58:10.77#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.11:58:10.77#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.11:58:10.77#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.11:58:10.79#ibcon#[25=AT01-08\r\n] 2006.145.11:58:10.81#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.11:58:10.81#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.11:58:10.81#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.11:58:10.81#ibcon#ireg 7 cls_cnt 0 2006.145.11:58:10.81#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.11:58:10.94#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.11:58:10.94#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.11:58:10.96#ibcon#[25=USB\r\n] 2006.145.11:58:10.98#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.11:58:10.98#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.11:58:10.98#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.11:58:10.98#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.11:58:10.99$vck44/valo=2,534.99 2006.145.11:58:10.99#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.11:58:10.99#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.11:58:10.99#ibcon#ireg 17 cls_cnt 0 2006.145.11:58:10.99#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.11:58:10.99#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.11:58:10.99#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.11:58:11.02#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.11:58:11.05#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.11:58:11.05#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.11:58:11.05#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.11:58:11.05#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.11:58:11.06$vck44/va=2,7 2006.145.11:58:11.06#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.11:58:11.06#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.11:58:11.06#ibcon#ireg 11 cls_cnt 2 2006.145.11:58:11.06#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.11:58:11.09#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.11:58:11.09#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.11:58:11.11#ibcon#[25=AT02-07\r\n] 2006.145.11:58:11.15#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.11:58:11.15#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.11:58:11.15#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.11:58:11.15#ibcon#ireg 7 cls_cnt 0 2006.145.11:58:11.15#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.11:58:11.26#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.11:58:11.26#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.11:58:11.28#ibcon#[25=USB\r\n] 2006.145.11:58:11.31#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.11:58:11.31#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.11:58:11.31#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.11:58:11.31#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.11:58:11.31$vck44/valo=3,564.99 2006.145.11:58:11.32#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.11:58:11.32#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.11:58:11.32#ibcon#ireg 17 cls_cnt 0 2006.145.11:58:11.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:58:11.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:58:11.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:58:11.33#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.11:58:11.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:58:11.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:58:11.37#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.11:58:11.37#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.11:58:11.37$vck44/va=3,8 2006.145.11:58:11.38#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.11:58:11.38#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.11:58:11.38#ibcon#ireg 11 cls_cnt 2 2006.145.11:58:11.38#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.11:58:11.42#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.11:58:11.42#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.11:58:11.44#ibcon#[25=AT03-08\r\n] 2006.145.11:58:11.47#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.11:58:11.47#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.11:58:11.47#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.11:58:11.47#ibcon#ireg 7 cls_cnt 0 2006.145.11:58:11.47#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.11:58:11.59#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.11:58:11.59#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.11:58:11.61#ibcon#[25=USB\r\n] 2006.145.11:58:11.64#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.11:58:11.64#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.11:58:11.64#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.11:58:11.64#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.11:58:11.64$vck44/valo=4,624.99 2006.145.11:58:11.65#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.11:58:11.65#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.11:58:11.65#ibcon#ireg 17 cls_cnt 0 2006.145.11:58:11.65#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.11:58:11.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.11:58:11.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.11:58:11.66#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.11:58:11.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.11:58:11.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.11:58:11.70#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.11:58:11.70#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.11:58:11.70$vck44/va=4,7 2006.145.11:58:11.71#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.11:58:11.71#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.11:58:11.71#ibcon#ireg 11 cls_cnt 2 2006.145.11:58:11.71#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:58:11.75#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:58:11.75#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:58:11.77#ibcon#[25=AT04-07\r\n] 2006.145.11:58:11.80#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:58:11.80#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:58:11.80#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.11:58:11.80#ibcon#ireg 7 cls_cnt 0 2006.145.11:58:11.80#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:58:11.92#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:58:11.92#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:58:11.94#ibcon#[25=USB\r\n] 2006.145.11:58:11.97#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:58:11.97#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:58:11.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.11:58:11.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.11:58:11.97$vck44/valo=5,734.99 2006.145.11:58:11.97#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.11:58:11.97#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.11:58:11.98#ibcon#ireg 17 cls_cnt 0 2006.145.11:58:11.98#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:58:11.98#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:58:11.98#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:58:11.99#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.11:58:12.03#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:58:12.03#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:58:12.03#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.11:58:12.03#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.11:58:12.03$vck44/va=5,4 2006.145.11:58:12.03#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.11:58:12.03#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.11:58:12.04#ibcon#ireg 11 cls_cnt 2 2006.145.11:58:12.04#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:58:12.08#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:58:12.08#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:58:12.10#ibcon#[25=AT05-04\r\n] 2006.145.11:58:12.13#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:58:12.13#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:58:12.13#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.11:58:12.13#ibcon#ireg 7 cls_cnt 0 2006.145.11:58:12.13#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:58:12.27#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:58:12.27#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:58:12.28#ibcon#[25=USB\r\n] 2006.145.11:58:12.31#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:58:12.31#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:58:12.31#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.11:58:12.31#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.11:58:12.31$vck44/valo=6,814.99 2006.145.11:58:12.32#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.11:58:12.32#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.11:58:12.32#ibcon#ireg 17 cls_cnt 0 2006.145.11:58:12.32#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:58:12.32#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:58:12.32#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:58:12.35#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.11:58:12.38#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:58:12.38#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:58:12.38#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.11:58:12.38#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.11:58:12.39$vck44/va=6,4 2006.145.11:58:12.39#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.11:58:12.39#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.11:58:12.39#ibcon#ireg 11 cls_cnt 2 2006.145.11:58:12.39#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:58:12.42#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:58:12.42#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:58:12.44#ibcon#[25=AT06-04\r\n] 2006.145.11:58:12.47#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:58:12.47#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:58:12.47#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.11:58:12.47#ibcon#ireg 7 cls_cnt 0 2006.145.11:58:12.47#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:58:12.59#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:58:12.59#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:58:12.61#ibcon#[25=USB\r\n] 2006.145.11:58:12.64#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:58:12.64#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:58:12.64#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.11:58:12.64#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.11:58:12.64$vck44/valo=7,864.99 2006.145.11:58:12.65#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.11:58:12.65#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.11:58:12.65#ibcon#ireg 17 cls_cnt 0 2006.145.11:58:12.65#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:58:12.65#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:58:12.65#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:58:12.66#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.11:58:12.70#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:58:12.70#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:58:12.70#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.11:58:12.70#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.11:58:12.70$vck44/va=7,4 2006.145.11:58:12.71#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.11:58:12.71#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.11:58:12.71#ibcon#ireg 11 cls_cnt 2 2006.145.11:58:12.71#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:58:12.75#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:58:12.75#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:58:12.77#ibcon#[25=AT07-04\r\n] 2006.145.11:58:12.80#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:58:12.80#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:58:12.80#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.11:58:12.80#ibcon#ireg 7 cls_cnt 0 2006.145.11:58:12.80#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:58:12.92#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:58:12.92#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:58:12.94#ibcon#[25=USB\r\n] 2006.145.11:58:12.97#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:58:12.97#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:58:12.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.11:58:12.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.11:58:12.97$vck44/valo=8,884.99 2006.145.11:58:12.98#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.11:58:12.98#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.11:58:12.98#ibcon#ireg 17 cls_cnt 0 2006.145.11:58:12.98#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:58:12.98#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:58:12.98#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:58:12.99#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.11:58:13.03#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:58:13.03#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:58:13.03#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.11:58:13.03#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.11:58:13.03$vck44/va=8,4 2006.145.11:58:13.04#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.11:58:13.04#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.11:58:13.04#ibcon#ireg 11 cls_cnt 2 2006.145.11:58:13.04#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.11:58:13.08#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.11:58:13.08#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.11:58:13.10#ibcon#[25=AT08-04\r\n] 2006.145.11:58:13.14#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.11:58:13.14#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.11:58:13.14#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.11:58:13.14#ibcon#ireg 7 cls_cnt 0 2006.145.11:58:13.14#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.11:58:13.25#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.11:58:13.25#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.11:58:13.27#ibcon#[25=USB\r\n] 2006.145.11:58:13.30#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.11:58:13.30#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.11:58:13.30#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.11:58:13.30#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.11:58:13.30$vck44/vblo=1,629.99 2006.145.11:58:13.30#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.11:58:13.31#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.11:58:13.31#ibcon#ireg 17 cls_cnt 0 2006.145.11:58:13.31#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.11:58:13.31#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.11:58:13.31#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.11:58:13.32#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.11:58:13.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.11:58:13.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.11:58:13.36#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.11:58:13.36#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.11:58:13.36$vck44/vb=1,3 2006.145.11:58:13.36#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.11:58:13.37#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.11:58:13.37#ibcon#ireg 11 cls_cnt 2 2006.145.11:58:13.37#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.11:58:13.37#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.11:58:13.37#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.11:58:13.40#ibcon#[27=AT01-03\r\n] 2006.145.11:58:13.43#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.11:58:13.43#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.11:58:13.43#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.11:58:13.43#ibcon#ireg 7 cls_cnt 0 2006.145.11:58:13.43#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.11:58:13.55#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.11:58:13.55#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.11:58:13.57#ibcon#[27=USB\r\n] 2006.145.11:58:13.60#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.11:58:13.60#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.11:58:13.60#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.11:58:13.60#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.11:58:13.60$vck44/vblo=2,634.99 2006.145.11:58:13.61#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.11:58:13.61#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.11:58:13.61#ibcon#ireg 17 cls_cnt 0 2006.145.11:58:13.61#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:58:13.61#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:58:13.61#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:58:13.62#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.11:58:13.66#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:58:13.66#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.11:58:13.66#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.11:58:13.66#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.11:58:13.67$vck44/vb=2,4 2006.145.11:58:13.67#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.11:58:13.67#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.11:58:13.67#ibcon#ireg 11 cls_cnt 2 2006.145.11:58:13.67#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.11:58:13.71#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.11:58:13.71#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.11:58:13.73#ibcon#[27=AT02-04\r\n] 2006.145.11:58:13.76#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.11:58:13.76#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.11:58:13.76#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.11:58:13.76#ibcon#ireg 7 cls_cnt 0 2006.145.11:58:13.76#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.11:58:13.88#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.11:58:13.88#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.11:58:13.90#ibcon#[27=USB\r\n] 2006.145.11:58:13.93#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.11:58:13.93#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.11:58:13.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.11:58:13.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.11:58:13.93$vck44/vblo=3,649.99 2006.145.11:58:13.94#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.11:58:13.94#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.11:58:13.94#ibcon#ireg 17 cls_cnt 0 2006.145.11:58:13.94#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.11:58:13.94#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.11:58:13.94#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.11:58:13.95#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.11:58:13.99#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.11:58:13.99#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.11:58:13.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.11:58:13.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.11:58:13.99$vck44/vb=3,4 2006.145.11:58:14.00#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.11:58:14.00#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.11:58:14.00#ibcon#ireg 11 cls_cnt 2 2006.145.11:58:14.00#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.11:58:14.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.11:58:14.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.11:58:14.06#ibcon#[27=AT03-04\r\n] 2006.145.11:58:14.09#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.11:58:14.09#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.11:58:14.09#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.11:58:14.09#ibcon#ireg 7 cls_cnt 0 2006.145.11:58:14.09#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.11:58:14.21#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.11:58:14.21#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.11:58:14.23#ibcon#[27=USB\r\n] 2006.145.11:58:14.26#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.11:58:14.26#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.11:58:14.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.11:58:14.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.11:58:14.26$vck44/vblo=4,679.99 2006.145.11:58:14.27#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.11:58:14.27#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.11:58:14.27#ibcon#ireg 17 cls_cnt 0 2006.145.11:58:14.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:58:14.27#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:58:14.27#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:58:14.28#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.11:58:14.32#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:58:14.32#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.11:58:14.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.11:58:14.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.11:58:14.32$vck44/vb=4,4 2006.145.11:58:14.33#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.11:58:14.33#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.11:58:14.33#ibcon#ireg 11 cls_cnt 2 2006.145.11:58:14.33#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.11:58:14.37#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.11:58:14.37#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.11:58:14.39#ibcon#[27=AT04-04\r\n] 2006.145.11:58:14.42#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.11:58:14.42#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.11:58:14.42#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.11:58:14.42#ibcon#ireg 7 cls_cnt 0 2006.145.11:58:14.42#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.11:58:14.54#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.11:58:14.54#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.11:58:14.56#ibcon#[27=USB\r\n] 2006.145.11:58:14.59#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.11:58:14.59#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.11:58:14.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.11:58:14.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.11:58:14.59$vck44/vblo=5,709.99 2006.145.11:58:14.60#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.11:58:14.60#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.11:58:14.60#ibcon#ireg 17 cls_cnt 0 2006.145.11:58:14.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.11:58:14.60#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.11:58:14.60#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.11:58:14.61#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.11:58:14.65#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.11:58:14.65#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.11:58:14.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.11:58:14.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.11:58:14.65$vck44/vb=5,4 2006.145.11:58:14.65#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.11:58:14.66#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.11:58:14.66#ibcon#ireg 11 cls_cnt 2 2006.145.11:58:14.66#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:58:14.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:58:14.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:58:14.72#ibcon#[27=AT05-04\r\n] 2006.145.11:58:14.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:58:14.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.11:58:14.75#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.11:58:14.75#ibcon#ireg 7 cls_cnt 0 2006.145.11:58:14.75#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:58:14.87#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:58:14.87#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:58:14.89#ibcon#[27=USB\r\n] 2006.145.11:58:14.92#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:58:14.92#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.11:58:14.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.11:58:14.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.11:58:14.92$vck44/vblo=6,719.99 2006.145.11:58:14.93#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.11:58:14.93#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.11:58:14.93#ibcon#ireg 17 cls_cnt 0 2006.145.11:58:14.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:58:14.93#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:58:14.93#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:58:14.94#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.11:58:14.98#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:58:14.98#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.11:58:14.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.11:58:14.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.11:58:14.99$vck44/vb=6,4 2006.145.11:58:14.99#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.11:58:14.99#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.11:58:14.99#ibcon#ireg 11 cls_cnt 2 2006.145.11:58:14.99#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:58:15.03#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:58:15.03#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:58:15.05#ibcon#[27=AT06-04\r\n] 2006.145.11:58:15.08#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:58:15.08#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.11:58:15.08#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.11:58:15.08#ibcon#ireg 7 cls_cnt 0 2006.145.11:58:15.08#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:58:15.20#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:58:15.20#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:58:15.22#ibcon#[27=USB\r\n] 2006.145.11:58:15.25#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:58:15.25#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.11:58:15.25#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.11:58:15.25#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.11:58:15.25$vck44/vblo=7,734.99 2006.145.11:58:15.26#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.11:58:15.26#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.11:58:15.26#ibcon#ireg 17 cls_cnt 0 2006.145.11:58:15.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:58:15.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:58:15.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:58:15.27#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.11:58:15.31#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:58:15.31#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.11:58:15.31#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.11:58:15.31#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.11:58:15.31$vck44/vb=7,4 2006.145.11:58:15.31#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.11:58:15.31#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.11:58:15.31#ibcon#ireg 11 cls_cnt 2 2006.145.11:58:15.31#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:58:15.37#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:58:15.37#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:58:15.39#ibcon#[27=AT07-04\r\n] 2006.145.11:58:15.42#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:58:15.42#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.11:58:15.42#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.11:58:15.42#ibcon#ireg 7 cls_cnt 0 2006.145.11:58:15.42#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:58:15.54#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:58:15.54#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:58:15.56#ibcon#[27=USB\r\n] 2006.145.11:58:15.59#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:58:15.59#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.11:58:15.59#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.11:58:15.59#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.11:58:15.59$vck44/vblo=8,744.99 2006.145.11:58:15.59#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.11:58:15.59#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.11:58:15.59#ibcon#ireg 17 cls_cnt 0 2006.145.11:58:15.59#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:58:15.59#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:58:15.59#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:58:15.61#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.11:58:15.65#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:58:15.65#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.11:58:15.65#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.11:58:15.65#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.11:58:15.65$vck44/vb=8,4 2006.145.11:58:15.65#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.11:58:15.65#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.11:58:15.65#ibcon#ireg 11 cls_cnt 2 2006.145.11:58:15.65#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:58:15.71#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:58:15.71#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:58:15.73#ibcon#[27=AT08-04\r\n] 2006.145.11:58:15.76#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:58:15.76#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.11:58:15.76#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.11:58:15.76#ibcon#ireg 7 cls_cnt 0 2006.145.11:58:15.76#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:58:15.88#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:58:15.88#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:58:15.90#ibcon#[27=USB\r\n] 2006.145.11:58:15.93#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:58:15.93#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.11:58:15.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.11:58:15.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.11:58:15.93$vck44/vabw=wide 2006.145.11:58:15.93#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.11:58:15.93#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.11:58:15.93#ibcon#ireg 8 cls_cnt 0 2006.145.11:58:15.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:58:15.93#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:58:15.93#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:58:15.95#ibcon#[25=BW32\r\n] 2006.145.11:58:15.98#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:58:15.98#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.11:58:15.98#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.11:58:15.98#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.11:58:15.98$vck44/vbbw=wide 2006.145.11:58:15.98#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.11:58:15.98#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.11:58:15.98#ibcon#ireg 8 cls_cnt 0 2006.145.11:58:15.98#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:58:16.05#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:58:16.05#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:58:16.07#ibcon#[27=BW32\r\n] 2006.145.11:58:16.10#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:58:16.10#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.11:58:16.10#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.11:58:16.10#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.11:58:16.10$setupk4/ifdk4 2006.145.11:58:16.10$ifdk4/lo= 2006.145.11:58:16.11$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.11:58:16.11$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.11:58:16.11$ifdk4/patch= 2006.145.11:58:16.11$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.11:58:16.11$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.11:58:16.11$setupk4/!*+20s 2006.145.11:58:17.63#abcon#<5=/04 1.5 2.8 16.17 741020.6\r\n> 2006.145.11:58:17.65#abcon#{5=INTERFACE CLEAR} 2006.145.11:58:17.71#abcon#[5=S1D000X0/0*\r\n] 2006.145.11:58:27.80#abcon#<5=/04 1.5 2.6 16.17 741020.6\r\n> 2006.145.11:58:27.82#abcon#{5=INTERFACE CLEAR} 2006.145.11:58:27.88#abcon#[5=S1D000X0/0*\r\n] 2006.145.11:58:30.68$setupk4/"tpicd 2006.145.11:58:30.68$setupk4/echo=off 2006.145.11:58:30.68$setupk4/xlog=off 2006.145.11:58:30.68:!2006.145.12:08:10 2006.145.11:58:54.14#trakl#Source acquired 2006.145.11:58:56.14#flagr#flagr/antenna,acquired 2006.145.12:08:10.00:preob 2006.145.12:08:10.14/onsource/TRACKING 2006.145.12:08:10.14:!2006.145.12:08:20 2006.145.12:08:20.00:"tape 2006.145.12:08:20.00:"st=record 2006.145.12:08:20.00:data_valid=on 2006.145.12:08:20.00:midob 2006.145.12:08:20.14/onsource/TRACKING 2006.145.12:08:20.14/wx/16.00,1020.6,75 2006.145.12:08:20.33/cable/+6.5455E-03 2006.145.12:08:21.42/va/01,08,usb,yes,28,30 2006.145.12:08:21.42/va/02,07,usb,yes,30,30 2006.145.12:08:21.42/va/03,08,usb,yes,27,28 2006.145.12:08:21.42/va/04,07,usb,yes,31,32 2006.145.12:08:21.42/va/05,04,usb,yes,27,27 2006.145.12:08:21.42/va/06,04,usb,yes,30,30 2006.145.12:08:21.42/va/07,04,usb,yes,30,31 2006.145.12:08:21.42/va/08,04,usb,yes,26,31 2006.145.12:08:21.65/valo/01,524.99,yes,locked 2006.145.12:08:21.65/valo/02,534.99,yes,locked 2006.145.12:08:21.65/valo/03,564.99,yes,locked 2006.145.12:08:21.65/valo/04,624.99,yes,locked 2006.145.12:08:21.65/valo/05,734.99,yes,locked 2006.145.12:08:21.65/valo/06,814.99,yes,locked 2006.145.12:08:21.65/valo/07,864.99,yes,locked 2006.145.12:08:21.65/valo/08,884.99,yes,locked 2006.145.12:08:22.74/vb/01,03,usb,yes,35,33 2006.145.12:08:22.74/vb/02,04,usb,yes,31,31 2006.145.12:08:22.74/vb/03,04,usb,yes,28,31 2006.145.12:08:22.74/vb/04,04,usb,yes,32,31 2006.145.12:08:22.74/vb/05,04,usb,yes,25,27 2006.145.12:08:22.74/vb/06,04,usb,yes,29,25 2006.145.12:08:22.74/vb/07,04,usb,yes,29,29 2006.145.12:08:22.74/vb/08,04,usb,yes,27,30 2006.145.12:08:22.97/vblo/01,629.99,yes,locked 2006.145.12:08:22.97/vblo/02,634.99,yes,locked 2006.145.12:08:22.97/vblo/03,649.99,yes,locked 2006.145.12:08:22.97/vblo/04,679.99,yes,locked 2006.145.12:08:22.97/vblo/05,709.99,yes,locked 2006.145.12:08:22.97/vblo/06,719.99,yes,locked 2006.145.12:08:22.97/vblo/07,734.99,yes,locked 2006.145.12:08:22.97/vblo/08,744.99,yes,locked 2006.145.12:08:23.12/vabw/8 2006.145.12:08:23.27/vbbw/8 2006.145.12:08:23.36/xfe/off,on,15.0 2006.145.12:08:23.75/ifatt/23,28,28,28 2006.145.12:08:24.07/fmout-gps/S +5.2E-08 2006.145.12:08:24.11:!2006.145.12:15:00 2006.145.12:15:00.00:data_valid=off 2006.145.12:15:00.00:"et 2006.145.12:15:00.01:!+3s 2006.145.12:15:03.02:"tape 2006.145.12:15:03.02:postob 2006.145.12:15:03.10/cable/+6.5498E-03 2006.145.12:15:03.10/wx/15.91,1020.6,77 2006.145.12:15:03.18/fmout-gps/S +5.2E-08 2006.145.12:15:03.18:scan_name=145-1215,jd0605,100 2006.145.12:15:03.18:source=1334-127,133739.78,-125724.7,2000.0,ccw 2006.145.12:15:05.14#flagr#flagr/antenna,new-source 2006.145.12:15:05.14:checkk5 2006.145.12:15:05.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.12:15:06.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.12:15:06.48/chk_autoobs//k5ts3/ autoobs is running! 2006.145.12:15:06.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.12:15:07.33/chk_obsdata//k5ts1/T1451208??a.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.145.12:15:07.77/chk_obsdata//k5ts2/T1451208??b.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.145.12:15:08.21/chk_obsdata//k5ts3/T1451208??c.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.145.12:15:08.67/chk_obsdata//k5ts4/T1451208??d.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.145.12:15:09.44/k5log//k5ts1_log_newline 2006.145.12:15:10.18/k5log//k5ts2_log_newline 2006.145.12:15:10.92/k5log//k5ts3_log_newline 2006.145.12:15:11.66/k5log//k5ts4_log_newline 2006.145.12:15:11.69/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.12:15:11.69:setupk4=1 2006.145.12:15:11.69$setupk4/echo=on 2006.145.12:15:11.69$setupk4/pcalon 2006.145.12:15:11.69$pcalon/"no phase cal control is implemented here 2006.145.12:15:11.69$setupk4/"tpicd=stop 2006.145.12:15:11.69$setupk4/"rec=synch_on 2006.145.12:15:11.69$setupk4/"rec_mode=128 2006.145.12:15:11.69$setupk4/!* 2006.145.12:15:11.69$setupk4/recpk4 2006.145.12:15:11.69$recpk4/recpatch= 2006.145.12:15:11.69$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.12:15:11.69$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.12:15:11.69$setupk4/vck44 2006.145.12:15:11.69$vck44/valo=1,524.99 2006.145.12:15:11.69#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.12:15:11.69#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.12:15:11.69#ibcon#ireg 17 cls_cnt 0 2006.145.12:15:11.69#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.12:15:11.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.12:15:11.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.12:15:11.73#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.12:15:11.78#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.12:15:11.78#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.12:15:11.78#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.12:15:11.78#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.12:15:11.78$vck44/va=1,8 2006.145.12:15:11.78#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.12:15:11.78#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.12:15:11.78#ibcon#ireg 11 cls_cnt 2 2006.145.12:15:11.78#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.12:15:11.78#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.12:15:11.78#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.12:15:11.80#ibcon#[25=AT01-08\r\n] 2006.145.12:15:11.83#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.12:15:11.83#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.12:15:11.83#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.12:15:11.83#ibcon#ireg 7 cls_cnt 0 2006.145.12:15:11.83#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.12:15:11.95#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.12:15:11.95#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.12:15:11.97#ibcon#[25=USB\r\n] 2006.145.12:15:12.00#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.12:15:12.00#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.12:15:12.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.12:15:12.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.12:15:12.00$vck44/valo=2,534.99 2006.145.12:15:12.00#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.12:15:12.00#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.12:15:12.00#ibcon#ireg 17 cls_cnt 0 2006.145.12:15:12.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.12:15:12.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.12:15:12.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.12:15:12.03#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.12:15:12.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.12:15:12.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.12:15:12.07#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.12:15:12.07#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.12:15:12.07$vck44/va=2,7 2006.145.12:15:12.07#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.12:15:12.07#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.12:15:12.07#ibcon#ireg 11 cls_cnt 2 2006.145.12:15:12.07#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.12:15:12.12#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.12:15:12.12#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.12:15:12.14#ibcon#[25=AT02-07\r\n] 2006.145.12:15:12.17#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.12:15:12.17#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.12:15:12.17#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.12:15:12.17#ibcon#ireg 7 cls_cnt 0 2006.145.12:15:12.17#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.12:15:12.29#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.12:15:12.29#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.12:15:12.31#ibcon#[25=USB\r\n] 2006.145.12:15:12.34#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.12:15:12.34#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.12:15:12.34#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.12:15:12.34#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.12:15:12.34$vck44/valo=3,564.99 2006.145.12:15:12.34#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.12:15:12.34#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.12:15:12.34#ibcon#ireg 17 cls_cnt 0 2006.145.12:15:12.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.12:15:12.34#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.12:15:12.34#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.12:15:12.36#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.12:15:12.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.12:15:12.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.12:15:12.40#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.12:15:12.40#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.12:15:12.40$vck44/va=3,8 2006.145.12:15:12.40#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.12:15:12.40#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.12:15:12.40#ibcon#ireg 11 cls_cnt 2 2006.145.12:15:12.40#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.12:15:12.46#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.12:15:12.46#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.12:15:12.48#ibcon#[25=AT03-08\r\n] 2006.145.12:15:12.51#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.12:15:12.51#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.12:15:12.51#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.12:15:12.51#ibcon#ireg 7 cls_cnt 0 2006.145.12:15:12.51#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.12:15:12.63#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.12:15:12.63#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.12:15:12.65#ibcon#[25=USB\r\n] 2006.145.12:15:12.68#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.12:15:12.68#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.12:15:12.68#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.12:15:12.68#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.12:15:12.68$vck44/valo=4,624.99 2006.145.12:15:12.68#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.12:15:12.68#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.12:15:12.68#ibcon#ireg 17 cls_cnt 0 2006.145.12:15:12.68#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.12:15:12.68#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.12:15:12.68#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.12:15:12.70#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.12:15:12.74#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.12:15:12.74#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.12:15:12.74#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.12:15:12.74#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.12:15:12.74$vck44/va=4,7 2006.145.12:15:12.74#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.12:15:12.74#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.12:15:12.74#ibcon#ireg 11 cls_cnt 2 2006.145.12:15:12.74#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.12:15:12.80#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.12:15:12.80#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.12:15:12.82#ibcon#[25=AT04-07\r\n] 2006.145.12:15:12.85#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.12:15:12.85#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.12:15:12.85#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.12:15:12.85#ibcon#ireg 7 cls_cnt 0 2006.145.12:15:12.85#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.12:15:12.97#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.12:15:12.97#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.12:15:12.99#ibcon#[25=USB\r\n] 2006.145.12:15:13.02#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.12:15:13.02#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.12:15:13.02#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.12:15:13.02#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.12:15:13.02$vck44/valo=5,734.99 2006.145.12:15:13.02#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.12:15:13.02#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.12:15:13.02#ibcon#ireg 17 cls_cnt 0 2006.145.12:15:13.02#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.12:15:13.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.12:15:13.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.12:15:13.04#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.12:15:13.08#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.12:15:13.08#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.12:15:13.08#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.12:15:13.08#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.12:15:13.08$vck44/va=5,4 2006.145.12:15:13.08#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.12:15:13.08#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.12:15:13.08#ibcon#ireg 11 cls_cnt 2 2006.145.12:15:13.08#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.12:15:13.14#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.12:15:13.14#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.12:15:13.16#ibcon#[25=AT05-04\r\n] 2006.145.12:15:13.20#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.12:15:13.20#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.12:15:13.20#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.12:15:13.20#ibcon#ireg 7 cls_cnt 0 2006.145.12:15:13.20#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.12:15:13.31#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.12:15:13.31#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.12:15:13.33#ibcon#[25=USB\r\n] 2006.145.12:15:13.36#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.12:15:13.36#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.12:15:13.36#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.12:15:13.36#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.12:15:13.36$vck44/valo=6,814.99 2006.145.12:15:13.36#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.12:15:13.36#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.12:15:13.36#ibcon#ireg 17 cls_cnt 0 2006.145.12:15:13.36#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.12:15:13.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.12:15:13.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.12:15:13.39#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.12:15:13.43#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.12:15:13.43#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.12:15:13.43#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.12:15:13.43#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.12:15:13.43$vck44/va=6,4 2006.145.12:15:13.43#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.12:15:13.43#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.12:15:13.43#ibcon#ireg 11 cls_cnt 2 2006.145.12:15:13.43#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.12:15:13.48#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.12:15:13.48#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.12:15:13.50#ibcon#[25=AT06-04\r\n] 2006.145.12:15:13.53#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.12:15:13.53#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.12:15:13.53#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.12:15:13.53#ibcon#ireg 7 cls_cnt 0 2006.145.12:15:13.53#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.12:15:13.65#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.12:15:13.65#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.12:15:13.67#ibcon#[25=USB\r\n] 2006.145.12:15:13.70#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.12:15:13.70#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.12:15:13.70#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.12:15:13.70#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.12:15:13.70$vck44/valo=7,864.99 2006.145.12:15:13.70#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.12:15:13.70#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.12:15:13.70#ibcon#ireg 17 cls_cnt 0 2006.145.12:15:13.70#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.12:15:13.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.12:15:13.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.12:15:13.72#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.12:15:13.76#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.12:15:13.76#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.12:15:13.76#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.12:15:13.76#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.12:15:13.76$vck44/va=7,4 2006.145.12:15:13.76#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.12:15:13.76#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.12:15:13.76#ibcon#ireg 11 cls_cnt 2 2006.145.12:15:13.76#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.12:15:13.82#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.12:15:13.82#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.12:15:13.84#ibcon#[25=AT07-04\r\n] 2006.145.12:15:13.87#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.12:15:13.87#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.12:15:13.87#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.12:15:13.87#ibcon#ireg 7 cls_cnt 0 2006.145.12:15:13.87#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.12:15:13.99#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.12:15:13.99#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.12:15:14.01#ibcon#[25=USB\r\n] 2006.145.12:15:14.04#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.12:15:14.04#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.12:15:14.04#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.12:15:14.04#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.12:15:14.04$vck44/valo=8,884.99 2006.145.12:15:14.04#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.12:15:14.04#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.12:15:14.04#ibcon#ireg 17 cls_cnt 0 2006.145.12:15:14.04#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.12:15:14.04#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.12:15:14.04#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.12:15:14.06#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.12:15:14.10#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.12:15:14.10#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.12:15:14.10#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.12:15:14.10#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.12:15:14.10$vck44/va=8,4 2006.145.12:15:14.10#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.12:15:14.10#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.12:15:14.10#ibcon#ireg 11 cls_cnt 2 2006.145.12:15:14.10#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.12:15:14.16#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.12:15:14.16#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.12:15:14.18#ibcon#[25=AT08-04\r\n] 2006.145.12:15:14.21#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.12:15:14.21#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.12:15:14.21#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.12:15:14.21#ibcon#ireg 7 cls_cnt 0 2006.145.12:15:14.21#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.12:15:14.33#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.12:15:14.33#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.12:15:14.35#ibcon#[25=USB\r\n] 2006.145.12:15:14.38#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.12:15:14.38#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.12:15:14.38#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.12:15:14.38#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.12:15:14.38$vck44/vblo=1,629.99 2006.145.12:15:14.38#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.12:15:14.38#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.12:15:14.38#ibcon#ireg 17 cls_cnt 0 2006.145.12:15:14.38#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.12:15:14.38#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.12:15:14.38#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.12:15:14.40#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.12:15:14.44#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.12:15:14.44#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.12:15:14.44#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.12:15:14.44#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.12:15:14.44$vck44/vb=1,3 2006.145.12:15:14.44#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.12:15:14.44#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.12:15:14.44#ibcon#ireg 11 cls_cnt 2 2006.145.12:15:14.44#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.12:15:14.44#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.12:15:14.44#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.12:15:14.46#ibcon#[27=AT01-03\r\n] 2006.145.12:15:14.49#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.12:15:14.49#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.12:15:14.49#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.12:15:14.49#ibcon#ireg 7 cls_cnt 0 2006.145.12:15:14.49#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.12:15:14.61#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.12:15:14.61#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.12:15:14.63#ibcon#[27=USB\r\n] 2006.145.12:15:14.66#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.12:15:14.66#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.12:15:14.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.12:15:14.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.12:15:14.66$vck44/vblo=2,634.99 2006.145.12:15:14.66#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.12:15:14.66#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.12:15:14.66#ibcon#ireg 17 cls_cnt 0 2006.145.12:15:14.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.12:15:14.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.12:15:14.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.12:15:14.68#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.12:15:14.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.12:15:14.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.12:15:14.72#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.12:15:14.72#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.12:15:14.72$vck44/vb=2,4 2006.145.12:15:14.72#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.12:15:14.72#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.12:15:14.72#ibcon#ireg 11 cls_cnt 2 2006.145.12:15:14.72#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.12:15:14.78#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.12:15:14.78#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.12:15:14.80#ibcon#[27=AT02-04\r\n] 2006.145.12:15:14.83#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.12:15:14.83#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.12:15:14.83#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.12:15:14.83#ibcon#ireg 7 cls_cnt 0 2006.145.12:15:14.83#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.12:15:14.95#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.12:15:14.95#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.12:15:14.97#ibcon#[27=USB\r\n] 2006.145.12:15:15.00#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.12:15:15.00#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.12:15:15.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.12:15:15.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.12:15:15.00$vck44/vblo=3,649.99 2006.145.12:15:15.00#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.12:15:15.00#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.12:15:15.00#ibcon#ireg 17 cls_cnt 0 2006.145.12:15:15.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.12:15:15.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.12:15:15.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.12:15:15.02#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.12:15:15.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.12:15:15.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.12:15:15.06#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.12:15:15.06#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.12:15:15.06$vck44/vb=3,4 2006.145.12:15:15.06#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.12:15:15.06#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.12:15:15.06#ibcon#ireg 11 cls_cnt 2 2006.145.12:15:15.06#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.12:15:15.12#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.12:15:15.12#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.12:15:15.14#ibcon#[27=AT03-04\r\n] 2006.145.12:15:15.17#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.12:15:15.17#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.12:15:15.17#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.12:15:15.17#ibcon#ireg 7 cls_cnt 0 2006.145.12:15:15.17#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.12:15:15.29#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.12:15:15.29#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.12:15:15.31#ibcon#[27=USB\r\n] 2006.145.12:15:15.34#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.12:15:15.34#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.12:15:15.34#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.12:15:15.34#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.12:15:15.34$vck44/vblo=4,679.99 2006.145.12:15:15.34#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.12:15:15.34#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.12:15:15.34#ibcon#ireg 17 cls_cnt 0 2006.145.12:15:15.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.12:15:15.34#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.12:15:15.34#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.12:15:15.36#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.12:15:15.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.12:15:15.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.12:15:15.40#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.12:15:15.40#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.12:15:15.40$vck44/vb=4,4 2006.145.12:15:15.40#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.12:15:15.40#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.12:15:15.40#ibcon#ireg 11 cls_cnt 2 2006.145.12:15:15.40#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.12:15:15.46#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.12:15:15.46#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.12:15:15.48#ibcon#[27=AT04-04\r\n] 2006.145.12:15:15.51#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.12:15:15.51#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.12:15:15.51#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.12:15:15.51#ibcon#ireg 7 cls_cnt 0 2006.145.12:15:15.51#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.12:15:15.63#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.12:15:15.63#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.12:15:15.65#ibcon#[27=USB\r\n] 2006.145.12:15:15.68#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.12:15:15.68#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.12:15:15.68#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.12:15:15.68#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.12:15:15.68$vck44/vblo=5,709.99 2006.145.12:15:15.68#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.12:15:15.68#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.12:15:15.68#ibcon#ireg 17 cls_cnt 0 2006.145.12:15:15.68#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.12:15:15.68#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.12:15:15.68#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.12:15:15.70#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.12:15:15.74#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.12:15:15.74#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.12:15:15.74#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.12:15:15.74#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.12:15:15.74$vck44/vb=5,4 2006.145.12:15:15.74#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.12:15:15.74#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.12:15:15.74#ibcon#ireg 11 cls_cnt 2 2006.145.12:15:15.74#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.12:15:15.80#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.12:15:15.80#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.12:15:15.82#ibcon#[27=AT05-04\r\n] 2006.145.12:15:15.85#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.12:15:15.85#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.12:15:15.85#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.12:15:15.85#ibcon#ireg 7 cls_cnt 0 2006.145.12:15:15.85#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.12:15:15.97#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.12:15:15.97#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.12:15:15.99#ibcon#[27=USB\r\n] 2006.145.12:15:16.02#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.12:15:16.02#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.12:15:16.02#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.12:15:16.02#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.12:15:16.02$vck44/vblo=6,719.99 2006.145.12:15:16.02#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.12:15:16.02#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.12:15:16.02#ibcon#ireg 17 cls_cnt 0 2006.145.12:15:16.02#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.12:15:16.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.12:15:16.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.12:15:16.04#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.12:15:16.08#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.12:15:16.08#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.12:15:16.08#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.12:15:16.08#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.12:15:16.08$vck44/vb=6,4 2006.145.12:15:16.08#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.12:15:16.08#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.12:15:16.08#ibcon#ireg 11 cls_cnt 2 2006.145.12:15:16.08#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.12:15:16.14#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.12:15:16.14#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.12:15:16.16#ibcon#[27=AT06-04\r\n] 2006.145.12:15:16.19#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.12:15:16.19#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.12:15:16.19#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.12:15:16.19#ibcon#ireg 7 cls_cnt 0 2006.145.12:15:16.19#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.12:15:16.31#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.12:15:16.31#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.12:15:16.33#ibcon#[27=USB\r\n] 2006.145.12:15:16.36#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.12:15:16.36#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.12:15:16.36#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.12:15:16.36#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.12:15:16.36$vck44/vblo=7,734.99 2006.145.12:15:16.36#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.12:15:16.36#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.12:15:16.36#ibcon#ireg 17 cls_cnt 0 2006.145.12:15:16.36#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.12:15:16.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.12:15:16.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.12:15:16.38#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.12:15:16.42#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.12:15:16.42#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.12:15:16.42#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.12:15:16.42#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.12:15:16.42$vck44/vb=7,4 2006.145.12:15:16.42#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.12:15:16.42#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.12:15:16.42#ibcon#ireg 11 cls_cnt 2 2006.145.12:15:16.42#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.12:15:16.48#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.12:15:16.48#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.12:15:16.50#ibcon#[27=AT07-04\r\n] 2006.145.12:15:16.53#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.12:15:16.53#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.12:15:16.53#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.12:15:16.53#ibcon#ireg 7 cls_cnt 0 2006.145.12:15:16.53#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.12:15:16.65#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.12:15:16.65#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.12:15:16.67#ibcon#[27=USB\r\n] 2006.145.12:15:16.70#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.12:15:16.70#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.12:15:16.70#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.12:15:16.70#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.12:15:16.70$vck44/vblo=8,744.99 2006.145.12:15:16.70#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.12:15:16.70#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.12:15:16.70#ibcon#ireg 17 cls_cnt 0 2006.145.12:15:16.70#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.12:15:16.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.12:15:16.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.12:15:16.72#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.12:15:16.76#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.12:15:16.76#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.12:15:16.76#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.12:15:16.76#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.12:15:16.76$vck44/vb=8,4 2006.145.12:15:16.76#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.12:15:16.76#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.12:15:16.76#ibcon#ireg 11 cls_cnt 2 2006.145.12:15:16.76#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.12:15:16.82#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.12:15:16.82#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.12:15:16.84#ibcon#[27=AT08-04\r\n] 2006.145.12:15:16.87#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.12:15:16.87#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.12:15:16.87#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.12:15:16.87#ibcon#ireg 7 cls_cnt 0 2006.145.12:15:16.87#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.12:15:16.99#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.12:15:16.99#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.12:15:17.01#ibcon#[27=USB\r\n] 2006.145.12:15:17.04#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.12:15:17.04#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.12:15:17.04#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.12:15:17.04#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.12:15:17.04$vck44/vabw=wide 2006.145.12:15:17.04#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.12:15:17.04#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.12:15:17.04#ibcon#ireg 8 cls_cnt 0 2006.145.12:15:17.04#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.12:15:17.04#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.12:15:17.04#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.12:15:17.06#ibcon#[25=BW32\r\n] 2006.145.12:15:17.09#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.12:15:17.09#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.12:15:17.09#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.12:15:17.09#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.12:15:17.09$vck44/vbbw=wide 2006.145.12:15:17.09#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.12:15:17.09#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.12:15:17.09#ibcon#ireg 8 cls_cnt 0 2006.145.12:15:17.09#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:15:17.16#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:15:17.16#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:15:17.18#ibcon#[27=BW32\r\n] 2006.145.12:15:17.21#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:15:17.21#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:15:17.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.12:15:17.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.12:15:17.21$setupk4/ifdk4 2006.145.12:15:17.21$ifdk4/lo= 2006.145.12:15:17.21$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.12:15:17.21$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.12:15:17.21$ifdk4/patch= 2006.145.12:15:17.21$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.12:15:17.21$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.12:15:17.21$setupk4/!*+20s 2006.145.12:15:17.62#abcon#<5=/04 1.5 2.4 15.91 771020.6\r\n> 2006.145.12:15:17.64#abcon#{5=INTERFACE CLEAR} 2006.145.12:15:17.70#abcon#[5=S1D000X0/0*\r\n] 2006.145.12:15:27.79#abcon#<5=/04 1.5 2.4 15.91 771020.6\r\n> 2006.145.12:15:27.81#abcon#{5=INTERFACE CLEAR} 2006.145.12:15:27.89#abcon#[5=S1D000X0/0*\r\n] 2006.145.12:15:31.70$setupk4/"tpicd 2006.145.12:15:31.70$setupk4/echo=off 2006.145.12:15:31.70$setupk4/xlog=off 2006.145.12:15:31.70:!2006.145.12:15:43 2006.145.12:15:34.14#trakl#Source acquired 2006.145.12:15:36.14#flagr#flagr/antenna,acquired 2006.145.12:15:43.00:preob 2006.145.12:15:43.14/onsource/TRACKING 2006.145.12:15:43.14:!2006.145.12:15:53 2006.145.12:15:53.00:"tape 2006.145.12:15:53.00:"st=record 2006.145.12:15:53.00:data_valid=on 2006.145.12:15:53.00:midob 2006.145.12:15:54.14/onsource/TRACKING 2006.145.12:15:54.14/wx/15.90,1020.6,77 2006.145.12:15:54.25/cable/+6.5483E-03 2006.145.12:15:55.34/va/01,08,usb,yes,28,30 2006.145.12:15:55.34/va/02,07,usb,yes,30,31 2006.145.12:15:55.34/va/03,08,usb,yes,28,29 2006.145.12:15:55.34/va/04,07,usb,yes,31,33 2006.145.12:15:55.34/va/05,04,usb,yes,27,28 2006.145.12:15:55.34/va/06,04,usb,yes,31,30 2006.145.12:15:55.34/va/07,04,usb,yes,31,32 2006.145.12:15:55.34/va/08,04,usb,yes,26,32 2006.145.12:15:55.57/valo/01,524.99,yes,locked 2006.145.12:15:55.57/valo/02,534.99,yes,locked 2006.145.12:15:55.57/valo/03,564.99,yes,locked 2006.145.12:15:55.57/valo/04,624.99,yes,locked 2006.145.12:15:55.57/valo/05,734.99,yes,locked 2006.145.12:15:55.57/valo/06,814.99,yes,locked 2006.145.12:15:55.57/valo/07,864.99,yes,locked 2006.145.12:15:55.57/valo/08,884.99,yes,locked 2006.145.12:15:56.66/vb/01,03,usb,yes,35,33 2006.145.12:15:56.66/vb/02,04,usb,yes,31,31 2006.145.12:15:56.66/vb/03,04,usb,yes,28,31 2006.145.12:15:56.66/vb/04,04,usb,yes,32,31 2006.145.12:15:56.66/vb/05,04,usb,yes,25,27 2006.145.12:15:56.66/vb/06,04,usb,yes,29,26 2006.145.12:15:56.66/vb/07,04,usb,yes,29,29 2006.145.12:15:56.66/vb/08,04,usb,yes,27,30 2006.145.12:15:56.89/vblo/01,629.99,yes,locked 2006.145.12:15:56.89/vblo/02,634.99,yes,locked 2006.145.12:15:56.89/vblo/03,649.99,yes,locked 2006.145.12:15:56.89/vblo/04,679.99,yes,locked 2006.145.12:15:56.89/vblo/05,709.99,yes,locked 2006.145.12:15:56.89/vblo/06,719.99,yes,locked 2006.145.12:15:56.89/vblo/07,734.99,yes,locked 2006.145.12:15:56.89/vblo/08,744.99,yes,locked 2006.145.12:15:57.04/vabw/8 2006.145.12:15:57.19/vbbw/8 2006.145.12:15:57.28/xfe/off,on,15.2 2006.145.12:15:57.68/ifatt/23,28,28,28 2006.145.12:15:58.07/fmout-gps/S +5.3E-08 2006.145.12:15:58.11:!2006.145.12:17:33 2006.145.12:17:33.01:data_valid=off 2006.145.12:17:33.01:"et 2006.145.12:17:33.02:!+3s 2006.145.12:17:36.03:"tape 2006.145.12:17:36.03:postob 2006.145.12:17:36.21/cable/+6.5490E-03 2006.145.12:17:36.21/wx/15.89,1020.6,77 2006.145.12:17:36.29/fmout-gps/S +5.3E-08 2006.145.12:17:36.29:scan_name=145-1218,jd0605,80 2006.145.12:17:36.29:source=3c274,123049.42,122328.0,2000.0,ccw 2006.145.12:17:38.13#flagr#flagr/antenna,new-source 2006.145.12:17:38.13:checkk5 2006.145.12:17:38.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.12:17:39.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.12:17:39.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.12:17:39.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.12:17:40.31/chk_obsdata//k5ts1/T1451215??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.12:17:40.74/chk_obsdata//k5ts2/T1451215??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.12:17:41.19/chk_obsdata//k5ts3/T1451215??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.12:17:41.63/chk_obsdata//k5ts4/T1451215??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.12:17:42.40/k5log//k5ts1_log_newline 2006.145.12:17:43.14/k5log//k5ts2_log_newline 2006.145.12:17:43.89/k5log//k5ts3_log_newline 2006.145.12:17:44.63/k5log//k5ts4_log_newline 2006.145.12:17:44.66/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.12:17:44.66:setupk4=1 2006.145.12:17:44.66$setupk4/echo=on 2006.145.12:17:44.66$setupk4/pcalon 2006.145.12:17:44.66$pcalon/"no phase cal control is implemented here 2006.145.12:17:44.66$setupk4/"tpicd=stop 2006.145.12:17:44.66$setupk4/"rec=synch_on 2006.145.12:17:44.66$setupk4/"rec_mode=128 2006.145.12:17:44.66$setupk4/!* 2006.145.12:17:44.66$setupk4/recpk4 2006.145.12:17:44.66$recpk4/recpatch= 2006.145.12:17:44.66$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.12:17:44.66$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.12:17:44.66$setupk4/vck44 2006.145.12:17:44.66$vck44/valo=1,524.99 2006.145.12:17:44.66#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.12:17:44.66#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.12:17:44.66#ibcon#ireg 17 cls_cnt 0 2006.145.12:17:44.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.12:17:44.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.12:17:44.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.12:17:44.70#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.12:17:44.75#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.12:17:44.75#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.12:17:44.75#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.12:17:44.75#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.12:17:44.75$vck44/va=1,8 2006.145.12:17:44.75#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.12:17:44.75#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.12:17:44.75#ibcon#ireg 11 cls_cnt 2 2006.145.12:17:44.75#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.12:17:44.75#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.12:17:44.75#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.12:17:44.77#ibcon#[25=AT01-08\r\n] 2006.145.12:17:44.80#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.12:17:44.80#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.12:17:44.80#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.12:17:44.80#ibcon#ireg 7 cls_cnt 0 2006.145.12:17:44.80#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.12:17:44.92#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.12:17:44.92#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.12:17:44.94#ibcon#[25=USB\r\n] 2006.145.12:17:44.99#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.12:17:44.99#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.12:17:44.99#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.12:17:44.99#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.12:17:44.99$vck44/valo=2,534.99 2006.145.12:17:44.99#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.12:17:44.99#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.12:17:44.99#ibcon#ireg 17 cls_cnt 0 2006.145.12:17:44.99#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.12:17:44.99#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.12:17:44.99#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.12:17:45.00#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.12:17:45.04#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.12:17:45.04#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.12:17:45.04#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.12:17:45.04#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.12:17:45.04$vck44/va=2,7 2006.145.12:17:45.04#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.12:17:45.04#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.12:17:45.04#ibcon#ireg 11 cls_cnt 2 2006.145.12:17:45.04#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.12:17:45.11#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.12:17:45.11#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.12:17:45.13#ibcon#[25=AT02-07\r\n] 2006.145.12:17:45.16#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.12:17:45.16#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.12:17:45.16#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.12:17:45.16#ibcon#ireg 7 cls_cnt 0 2006.145.12:17:45.16#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.12:17:45.28#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.12:17:45.28#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.12:17:45.30#ibcon#[25=USB\r\n] 2006.145.12:17:45.33#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.12:17:45.33#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.12:17:45.33#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.12:17:45.33#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.12:17:45.33$vck44/valo=3,564.99 2006.145.12:17:45.33#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.12:17:45.33#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.12:17:45.33#ibcon#ireg 17 cls_cnt 0 2006.145.12:17:45.33#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.12:17:45.33#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.12:17:45.33#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.12:17:45.35#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.12:17:45.39#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.12:17:45.39#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.12:17:45.39#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.12:17:45.39#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.12:17:45.39$vck44/va=3,8 2006.145.12:17:45.39#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.12:17:45.39#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.12:17:45.39#ibcon#ireg 11 cls_cnt 2 2006.145.12:17:45.39#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.12:17:45.45#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.12:17:45.45#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.12:17:45.47#ibcon#[25=AT03-08\r\n] 2006.145.12:17:45.50#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.12:17:45.50#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.12:17:45.50#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.12:17:45.50#ibcon#ireg 7 cls_cnt 0 2006.145.12:17:45.50#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.12:17:45.62#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.12:17:45.62#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.12:17:45.64#ibcon#[25=USB\r\n] 2006.145.12:17:45.67#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.12:17:45.67#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.12:17:45.67#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.12:17:45.67#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.12:17:45.67$vck44/valo=4,624.99 2006.145.12:17:45.67#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.12:17:45.67#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.12:17:45.67#ibcon#ireg 17 cls_cnt 0 2006.145.12:17:45.67#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.12:17:45.67#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.12:17:45.67#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.12:17:45.69#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.12:17:45.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.12:17:45.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.12:17:45.73#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.12:17:45.73#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.12:17:45.73$vck44/va=4,7 2006.145.12:17:45.73#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.12:17:45.73#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.12:17:45.73#ibcon#ireg 11 cls_cnt 2 2006.145.12:17:45.73#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.12:17:45.79#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.12:17:45.79#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.12:17:45.81#ibcon#[25=AT04-07\r\n] 2006.145.12:17:45.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.12:17:45.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.12:17:45.84#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.12:17:45.84#ibcon#ireg 7 cls_cnt 0 2006.145.12:17:45.84#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.12:17:45.96#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.12:17:45.96#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.12:17:45.98#ibcon#[25=USB\r\n] 2006.145.12:17:46.01#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.12:17:46.01#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.12:17:46.01#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.12:17:46.01#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.12:17:46.01$vck44/valo=5,734.99 2006.145.12:17:46.01#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.12:17:46.01#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.12:17:46.01#ibcon#ireg 17 cls_cnt 0 2006.145.12:17:46.01#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.12:17:46.01#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.12:17:46.01#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.12:17:46.03#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.12:17:46.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.12:17:46.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.12:17:46.07#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.12:17:46.07#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.12:17:46.07$vck44/va=5,4 2006.145.12:17:46.07#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.12:17:46.07#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.12:17:46.07#ibcon#ireg 11 cls_cnt 2 2006.145.12:17:46.07#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.12:17:46.13#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.12:17:46.13#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.12:17:46.15#ibcon#[25=AT05-04\r\n] 2006.145.12:17:46.18#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.12:17:46.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.12:17:46.18#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.12:17:46.18#ibcon#ireg 7 cls_cnt 0 2006.145.12:17:46.18#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.12:17:46.31#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.12:17:46.31#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.12:17:46.32#ibcon#[25=USB\r\n] 2006.145.12:17:46.35#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.12:17:46.35#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.12:17:46.35#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.12:17:46.35#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.12:17:46.35$vck44/valo=6,814.99 2006.145.12:17:46.35#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.12:17:46.35#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.12:17:46.35#ibcon#ireg 17 cls_cnt 0 2006.145.12:17:46.35#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.12:17:46.35#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.12:17:46.35#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.12:17:46.38#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.12:17:46.42#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.12:17:46.42#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.12:17:46.42#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.12:17:46.42#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.12:17:46.42$vck44/va=6,4 2006.145.12:17:46.42#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.12:17:46.42#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.12:17:46.42#ibcon#ireg 11 cls_cnt 2 2006.145.12:17:46.42#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.12:17:46.48#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.12:17:46.48#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.12:17:46.50#ibcon#[25=AT06-04\r\n] 2006.145.12:17:46.53#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.12:17:46.53#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.12:17:46.53#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.12:17:46.53#ibcon#ireg 7 cls_cnt 0 2006.145.12:17:46.53#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.12:17:46.65#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.12:17:46.65#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.12:17:46.67#ibcon#[25=USB\r\n] 2006.145.12:17:46.70#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.12:17:46.70#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.12:17:46.70#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.12:17:46.70#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.12:17:46.70$vck44/valo=7,864.99 2006.145.12:17:46.70#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.12:17:46.70#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.12:17:46.70#ibcon#ireg 17 cls_cnt 0 2006.145.12:17:46.70#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.12:17:46.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.12:17:46.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.12:17:46.72#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.12:17:46.76#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.12:17:46.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.12:17:46.76#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.12:17:46.76#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.12:17:46.76$vck44/va=7,4 2006.145.12:17:46.76#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.12:17:46.76#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.12:17:46.76#ibcon#ireg 11 cls_cnt 2 2006.145.12:17:46.76#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.12:17:46.82#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.12:17:46.82#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.12:17:46.84#ibcon#[25=AT07-04\r\n] 2006.145.12:17:46.87#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.12:17:46.87#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.12:17:46.87#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.12:17:46.87#ibcon#ireg 7 cls_cnt 0 2006.145.12:17:46.87#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.12:17:46.99#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.12:17:46.99#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.12:17:47.01#ibcon#[25=USB\r\n] 2006.145.12:17:47.04#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.12:17:47.04#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.12:17:47.04#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.12:17:47.04#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.12:17:47.04$vck44/valo=8,884.99 2006.145.12:17:47.04#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.12:17:47.04#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.12:17:47.04#ibcon#ireg 17 cls_cnt 0 2006.145.12:17:47.04#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.12:17:47.04#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.12:17:47.04#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.12:17:47.06#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.12:17:47.10#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.12:17:47.10#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.12:17:47.10#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.12:17:47.10#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.12:17:47.10$vck44/va=8,4 2006.145.12:17:47.10#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.12:17:47.10#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.12:17:47.10#ibcon#ireg 11 cls_cnt 2 2006.145.12:17:47.10#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.12:17:47.16#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.12:17:47.16#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.12:17:47.18#ibcon#[25=AT08-04\r\n] 2006.145.12:17:47.21#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.12:17:47.21#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.12:17:47.21#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.12:17:47.21#ibcon#ireg 7 cls_cnt 0 2006.145.12:17:47.21#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.12:17:47.33#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.12:17:47.33#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.12:17:47.35#ibcon#[25=USB\r\n] 2006.145.12:17:47.38#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.12:17:47.38#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.12:17:47.38#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.12:17:47.38#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.12:17:47.38$vck44/vblo=1,629.99 2006.145.12:17:47.38#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.12:17:47.38#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.12:17:47.38#ibcon#ireg 17 cls_cnt 0 2006.145.12:17:47.38#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.12:17:47.38#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.12:17:47.38#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.12:17:47.40#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.12:17:47.44#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.12:17:47.44#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.12:17:47.44#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.12:17:47.44#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.12:17:47.44$vck44/vb=1,3 2006.145.12:17:47.44#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.12:17:47.44#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.12:17:47.44#ibcon#ireg 11 cls_cnt 2 2006.145.12:17:47.44#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.12:17:47.44#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.12:17:47.44#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.12:17:47.46#ibcon#[27=AT01-03\r\n] 2006.145.12:17:47.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.12:17:47.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.12:17:47.49#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.12:17:47.49#ibcon#ireg 7 cls_cnt 0 2006.145.12:17:47.49#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.12:17:47.61#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.12:17:47.61#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.12:17:47.63#ibcon#[27=USB\r\n] 2006.145.12:17:47.66#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.12:17:47.66#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.12:17:47.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.12:17:47.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.12:17:47.66$vck44/vblo=2,634.99 2006.145.12:17:47.66#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.12:17:47.66#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.12:17:47.66#ibcon#ireg 17 cls_cnt 0 2006.145.12:17:47.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.12:17:47.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.12:17:47.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.12:17:47.68#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.12:17:47.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.12:17:47.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.12:17:47.72#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.12:17:47.72#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.12:17:47.72$vck44/vb=2,4 2006.145.12:17:47.72#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.12:17:47.72#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.12:17:47.72#ibcon#ireg 11 cls_cnt 2 2006.145.12:17:47.72#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.12:17:47.78#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.12:17:47.78#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.12:17:47.80#ibcon#[27=AT02-04\r\n] 2006.145.12:17:47.83#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.12:17:47.83#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.12:17:47.83#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.12:17:47.83#ibcon#ireg 7 cls_cnt 0 2006.145.12:17:47.83#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.12:17:47.95#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.12:17:47.95#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.12:17:47.97#ibcon#[27=USB\r\n] 2006.145.12:17:48.00#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.12:17:48.00#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.12:17:48.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.12:17:48.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.12:17:48.00$vck44/vblo=3,649.99 2006.145.12:17:48.00#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.12:17:48.00#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.12:17:48.00#ibcon#ireg 17 cls_cnt 0 2006.145.12:17:48.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.12:17:48.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.12:17:48.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.12:17:48.02#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.12:17:48.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.12:17:48.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.12:17:48.06#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.12:17:48.06#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.12:17:48.06$vck44/vb=3,4 2006.145.12:17:48.06#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.12:17:48.06#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.12:17:48.06#ibcon#ireg 11 cls_cnt 2 2006.145.12:17:48.06#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.12:17:48.12#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.12:17:48.12#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.12:17:48.14#ibcon#[27=AT03-04\r\n] 2006.145.12:17:48.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.12:17:48.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.12:17:48.17#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.12:17:48.17#ibcon#ireg 7 cls_cnt 0 2006.145.12:17:48.17#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.12:17:48.29#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.12:17:48.29#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.12:17:48.31#ibcon#[27=USB\r\n] 2006.145.12:17:48.34#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.12:17:48.34#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.12:17:48.34#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.12:17:48.34#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.12:17:48.34$vck44/vblo=4,679.99 2006.145.12:17:48.34#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.12:17:48.34#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.12:17:48.34#ibcon#ireg 17 cls_cnt 0 2006.145.12:17:48.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.12:17:48.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.12:17:48.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.12:17:48.36#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.12:17:48.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.12:17:48.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.12:17:48.40#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.12:17:48.40#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.12:17:48.40$vck44/vb=4,4 2006.145.12:17:48.40#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.12:17:48.40#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.12:17:48.40#ibcon#ireg 11 cls_cnt 2 2006.145.12:17:48.40#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.12:17:48.46#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.12:17:48.46#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.12:17:48.48#ibcon#[27=AT04-04\r\n] 2006.145.12:17:48.51#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.12:17:48.51#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.12:17:48.51#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.12:17:48.51#ibcon#ireg 7 cls_cnt 0 2006.145.12:17:48.51#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.12:17:48.63#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.12:17:48.63#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.12:17:48.65#ibcon#[27=USB\r\n] 2006.145.12:17:48.68#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.12:17:48.68#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.12:17:48.68#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.12:17:48.68#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.12:17:48.68$vck44/vblo=5,709.99 2006.145.12:17:48.68#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.12:17:48.68#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.12:17:48.68#ibcon#ireg 17 cls_cnt 0 2006.145.12:17:48.68#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.12:17:48.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.12:17:48.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.12:17:48.70#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.12:17:48.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.12:17:48.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.12:17:48.74#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.12:17:48.74#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.12:17:48.74$vck44/vb=5,4 2006.145.12:17:48.74#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.12:17:48.74#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.12:17:48.74#ibcon#ireg 11 cls_cnt 2 2006.145.12:17:48.74#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.12:17:48.80#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.12:17:48.80#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.12:17:48.82#ibcon#[27=AT05-04\r\n] 2006.145.12:17:48.85#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.12:17:48.85#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.12:17:48.85#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.12:17:48.85#ibcon#ireg 7 cls_cnt 0 2006.145.12:17:48.85#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.12:17:48.97#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.12:17:48.97#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.12:17:48.99#ibcon#[27=USB\r\n] 2006.145.12:17:49.02#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.12:17:49.02#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.12:17:49.02#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.12:17:49.02#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.12:17:49.02$vck44/vblo=6,719.99 2006.145.12:17:49.02#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.12:17:49.02#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.12:17:49.02#ibcon#ireg 17 cls_cnt 0 2006.145.12:17:49.02#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.12:17:49.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.12:17:49.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.12:17:49.04#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.12:17:49.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.12:17:49.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.12:17:49.08#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.12:17:49.08#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.12:17:49.08$vck44/vb=6,4 2006.145.12:17:49.08#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.12:17:49.08#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.12:17:49.08#ibcon#ireg 11 cls_cnt 2 2006.145.12:17:49.08#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.12:17:49.14#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.12:17:49.14#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.12:17:49.16#ibcon#[27=AT06-04\r\n] 2006.145.12:17:49.19#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.12:17:49.19#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.12:17:49.19#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.12:17:49.19#ibcon#ireg 7 cls_cnt 0 2006.145.12:17:49.19#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.12:17:49.31#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.12:17:49.31#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.12:17:49.33#ibcon#[27=USB\r\n] 2006.145.12:17:49.36#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.12:17:49.36#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.12:17:49.36#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.12:17:49.36#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.12:17:49.36$vck44/vblo=7,734.99 2006.145.12:17:49.36#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.12:17:49.36#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.12:17:49.36#ibcon#ireg 17 cls_cnt 0 2006.145.12:17:49.36#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.12:17:49.36#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.12:17:49.36#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.12:17:49.38#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.12:17:49.42#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.12:17:49.42#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.12:17:49.42#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.12:17:49.42#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.12:17:49.42$vck44/vb=7,4 2006.145.12:17:49.42#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.12:17:49.42#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.12:17:49.42#ibcon#ireg 11 cls_cnt 2 2006.145.12:17:49.42#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.12:17:49.48#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.12:17:49.48#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.12:17:49.50#ibcon#[27=AT07-04\r\n] 2006.145.12:17:49.53#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.12:17:49.53#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.12:17:49.53#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.12:17:49.53#ibcon#ireg 7 cls_cnt 0 2006.145.12:17:49.53#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.12:17:49.65#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.12:17:49.65#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.12:17:49.67#ibcon#[27=USB\r\n] 2006.145.12:17:49.70#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.12:17:49.70#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.12:17:49.70#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.12:17:49.70#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.12:17:49.70$vck44/vblo=8,744.99 2006.145.12:17:49.70#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.12:17:49.70#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.12:17:49.70#ibcon#ireg 17 cls_cnt 0 2006.145.12:17:49.70#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.12:17:49.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.12:17:49.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.12:17:49.72#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.12:17:49.76#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.12:17:49.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.12:17:49.76#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.12:17:49.76#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.12:17:49.76$vck44/vb=8,4 2006.145.12:17:49.76#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.12:17:49.76#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.12:17:49.76#ibcon#ireg 11 cls_cnt 2 2006.145.12:17:49.76#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.12:17:49.82#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.12:17:49.82#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.12:17:49.84#ibcon#[27=AT08-04\r\n] 2006.145.12:17:49.87#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.12:17:49.87#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.12:17:49.87#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.12:17:49.87#ibcon#ireg 7 cls_cnt 0 2006.145.12:17:49.87#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.12:17:49.99#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.12:17:49.99#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.12:17:50.01#ibcon#[27=USB\r\n] 2006.145.12:17:50.04#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.12:17:50.04#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.12:17:50.04#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.12:17:50.04#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.12:17:50.04$vck44/vabw=wide 2006.145.12:17:50.04#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.12:17:50.04#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.12:17:50.04#ibcon#ireg 8 cls_cnt 0 2006.145.12:17:50.04#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.12:17:50.04#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.12:17:50.04#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.12:17:50.06#ibcon#[25=BW32\r\n] 2006.145.12:17:50.09#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.12:17:50.09#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.12:17:50.09#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.12:17:50.09#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.12:17:50.09$vck44/vbbw=wide 2006.145.12:17:50.09#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.12:17:50.09#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.12:17:50.09#ibcon#ireg 8 cls_cnt 0 2006.145.12:17:50.09#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.12:17:50.16#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.12:17:50.16#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.12:17:50.18#ibcon#[27=BW32\r\n] 2006.145.12:17:50.21#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.12:17:50.21#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.12:17:50.21#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.12:17:50.21#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.12:17:50.21$setupk4/ifdk4 2006.145.12:17:50.21$ifdk4/lo= 2006.145.12:17:50.21$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.12:17:50.21$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.12:17:50.21$ifdk4/patch= 2006.145.12:17:50.21$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.12:17:50.21$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.12:17:50.21$setupk4/!*+20s 2006.145.12:17:50.31#abcon#<5=/04 1.5 2.3 15.88 771020.6\r\n> 2006.145.12:17:50.33#abcon#{5=INTERFACE CLEAR} 2006.145.12:17:50.39#abcon#[5=S1D000X0/0*\r\n] 2006.145.12:17:59.13#trakl#Source acquired 2006.145.12:18:00.13#flagr#flagr/antenna,acquired 2006.145.12:18:00.48#abcon#<5=/04 1.5 2.2 15.88 771020.6\r\n> 2006.145.12:18:00.50#abcon#{5=INTERFACE CLEAR} 2006.145.12:18:00.56#abcon#[5=S1D000X0/0*\r\n] 2006.145.12:18:04.67$setupk4/"tpicd 2006.145.12:18:04.67$setupk4/echo=off 2006.145.12:18:04.67$setupk4/xlog=off 2006.145.12:18:04.67:!2006.145.12:18:49 2006.145.12:18:49.00:preob 2006.145.12:18:49.13/onsource/TRACKING 2006.145.12:18:49.13:!2006.145.12:18:59 2006.145.12:18:59.00:"tape 2006.145.12:18:59.00:"st=record 2006.145.12:18:59.00:data_valid=on 2006.145.12:18:59.00:midob 2006.145.12:19:00.13/onsource/TRACKING 2006.145.12:19:00.13/wx/15.87,1020.7,77 2006.145.12:19:00.29/cable/+6.5474E-03 2006.145.12:19:01.38/va/01,08,usb,yes,31,33 2006.145.12:19:01.38/va/02,07,usb,yes,33,34 2006.145.12:19:01.38/va/03,08,usb,yes,30,31 2006.145.12:19:01.38/va/04,07,usb,yes,34,36 2006.145.12:19:01.38/va/05,04,usb,yes,30,30 2006.145.12:19:01.38/va/06,04,usb,yes,33,33 2006.145.12:19:01.38/va/07,04,usb,yes,33,35 2006.145.12:19:01.38/va/08,04,usb,yes,29,34 2006.145.12:19:01.61/valo/01,524.99,yes,locked 2006.145.12:19:01.61/valo/02,534.99,yes,locked 2006.145.12:19:01.61/valo/03,564.99,yes,locked 2006.145.12:19:01.61/valo/04,624.99,yes,locked 2006.145.12:19:01.61/valo/05,734.99,yes,locked 2006.145.12:19:01.61/valo/06,814.99,yes,locked 2006.145.12:19:01.61/valo/07,864.99,yes,locked 2006.145.12:19:01.61/valo/08,884.99,yes,locked 2006.145.12:19:02.70/vb/01,03,usb,yes,44,41 2006.145.12:19:02.70/vb/02,04,usb,yes,39,38 2006.145.12:19:02.70/vb/03,04,usb,yes,35,39 2006.145.12:19:02.70/vb/04,04,usb,yes,40,39 2006.145.12:19:02.70/vb/05,04,usb,yes,31,34 2006.145.12:19:02.70/vb/06,04,usb,yes,36,32 2006.145.12:19:02.70/vb/07,04,usb,yes,36,36 2006.145.12:19:02.70/vb/08,04,usb,yes,33,37 2006.145.12:19:02.93/vblo/01,629.99,yes,locked 2006.145.12:19:02.93/vblo/02,634.99,yes,locked 2006.145.12:19:02.93/vblo/03,649.99,yes,locked 2006.145.12:19:02.93/vblo/04,679.99,yes,locked 2006.145.12:19:02.93/vblo/05,709.99,yes,locked 2006.145.12:19:02.93/vblo/06,719.99,yes,locked 2006.145.12:19:02.93/vblo/07,734.99,yes,locked 2006.145.12:19:02.93/vblo/08,744.99,yes,locked 2006.145.12:19:03.08/vabw/8 2006.145.12:19:03.23/vbbw/8 2006.145.12:19:03.32/xfe/off,on,14.2 2006.145.12:19:03.71/ifatt/23,28,28,28 2006.145.12:19:04.07/fmout-gps/S +5.3E-08 2006.145.12:19:04.15:!2006.145.12:20:19 2006.145.12:20:19.00:data_valid=off 2006.145.12:20:19.00:"et 2006.145.12:20:19.01:!+3s 2006.145.12:20:22.02:"tape 2006.145.12:20:22.02:postob 2006.145.12:20:22.16/cable/+6.5451E-03 2006.145.12:20:22.16/wx/15.85,1020.6,78 2006.145.12:20:22.23/fmout-gps/S +5.4E-08 2006.145.12:20:22.23:scan_name=145-1222,jd0605,780 2006.145.12:20:22.23:source=0059+581,010245.76,582411.1,2000.0,neutral 2006.145.12:20:23.14#flagr#flagr/antenna,new-source 2006.145.12:20:23.14:checkk5 2006.145.12:20:23.62/chk_autoobs//k5ts1/ autoobs is running! 2006.145.12:20:24.05/chk_autoobs//k5ts2/ autoobs is running! 2006.145.12:20:24.48/chk_autoobs//k5ts3/ autoobs is running! 2006.145.12:20:24.93/chk_autoobs//k5ts4/ autoobs is running! 2006.145.12:20:25.35/chk_obsdata//k5ts1/T1451218??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.12:20:25.80/chk_obsdata//k5ts2/T1451218??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.12:20:26.24/chk_obsdata//k5ts3/T1451218??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.12:20:26.69/chk_obsdata//k5ts4/T1451218??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.12:20:27.47/k5log//k5ts1_log_newline 2006.145.12:20:28.21/k5log//k5ts2_log_newline 2006.145.12:20:28.95/k5log//k5ts3_log_newline 2006.145.12:20:29.69/k5log//k5ts4_log_newline 2006.145.12:20:29.72/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.12:20:29.72:setupk4=1 2006.145.12:20:29.72$setupk4/echo=on 2006.145.12:20:29.72$setupk4/pcalon 2006.145.12:20:29.72$pcalon/"no phase cal control is implemented here 2006.145.12:20:29.72$setupk4/"tpicd=stop 2006.145.12:20:29.72$setupk4/"rec=synch_on 2006.145.12:20:29.72$setupk4/"rec_mode=128 2006.145.12:20:29.72$setupk4/!* 2006.145.12:20:29.72$setupk4/recpk4 2006.145.12:20:29.72$recpk4/recpatch= 2006.145.12:20:29.72$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.12:20:29.72$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.12:20:29.72$setupk4/vck44 2006.145.12:20:29.72$vck44/valo=1,524.99 2006.145.12:20:29.72#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.12:20:29.72#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.12:20:29.72#ibcon#ireg 17 cls_cnt 0 2006.145.12:20:29.72#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.12:20:29.72#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.12:20:29.72#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.12:20:29.76#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.12:20:29.81#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.12:20:29.81#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.12:20:29.81#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.12:20:29.81#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.12:20:29.81$vck44/va=1,8 2006.145.12:20:29.81#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.12:20:29.81#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.12:20:29.81#ibcon#ireg 11 cls_cnt 2 2006.145.12:20:29.81#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.12:20:29.81#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.12:20:29.81#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.12:20:29.83#ibcon#[25=AT01-08\r\n] 2006.145.12:20:29.86#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.12:20:29.86#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.12:20:29.86#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.12:20:29.86#ibcon#ireg 7 cls_cnt 0 2006.145.12:20:29.86#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.12:20:29.98#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.12:20:29.98#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.12:20:30.00#ibcon#[25=USB\r\n] 2006.145.12:20:30.06#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.12:20:30.06#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.12:20:30.06#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.12:20:30.06#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.12:20:30.06$vck44/valo=2,534.99 2006.145.12:20:30.06#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.12:20:30.06#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.12:20:30.06#ibcon#ireg 17 cls_cnt 0 2006.145.12:20:30.06#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.12:20:30.06#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.12:20:30.06#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.12:20:30.07#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.12:20:30.11#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.12:20:30.11#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.12:20:30.11#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.12:20:30.11#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.12:20:30.11$vck44/va=2,7 2006.145.12:20:30.11#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.12:20:30.11#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.12:20:30.11#ibcon#ireg 11 cls_cnt 2 2006.145.12:20:30.11#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.12:20:30.18#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.12:20:30.18#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.12:20:30.20#ibcon#[25=AT02-07\r\n] 2006.145.12:20:30.23#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.12:20:30.23#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.12:20:30.23#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.12:20:30.23#ibcon#ireg 7 cls_cnt 0 2006.145.12:20:30.23#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.12:20:30.35#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.12:20:30.35#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.12:20:30.37#ibcon#[25=USB\r\n] 2006.145.12:20:30.40#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.12:20:30.40#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.12:20:30.40#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.12:20:30.40#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.12:20:30.40$vck44/valo=3,564.99 2006.145.12:20:30.40#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.12:20:30.40#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.12:20:30.40#ibcon#ireg 17 cls_cnt 0 2006.145.12:20:30.40#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.12:20:30.40#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.12:20:30.40#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.12:20:30.42#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.12:20:30.46#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.12:20:30.46#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.12:20:30.46#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.12:20:30.46#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.12:20:30.46$vck44/va=3,8 2006.145.12:20:30.46#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.12:20:30.46#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.12:20:30.46#ibcon#ireg 11 cls_cnt 2 2006.145.12:20:30.46#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.12:20:30.52#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.12:20:30.52#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.12:20:30.54#ibcon#[25=AT03-08\r\n] 2006.145.12:20:30.57#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.12:20:30.57#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.12:20:30.57#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.12:20:30.57#ibcon#ireg 7 cls_cnt 0 2006.145.12:20:30.57#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.12:20:30.69#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.12:20:30.69#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.12:20:30.71#ibcon#[25=USB\r\n] 2006.145.12:20:30.74#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.12:20:30.74#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.12:20:30.74#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.12:20:30.74#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.12:20:30.74$vck44/valo=4,624.99 2006.145.12:20:30.74#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.12:20:30.74#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.12:20:30.74#ibcon#ireg 17 cls_cnt 0 2006.145.12:20:30.74#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.12:20:30.74#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.12:20:30.74#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.12:20:30.76#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.12:20:30.80#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.12:20:30.80#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.12:20:30.80#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.12:20:30.80#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.12:20:30.80$vck44/va=4,7 2006.145.12:20:30.80#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.12:20:30.80#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.12:20:30.80#ibcon#ireg 11 cls_cnt 2 2006.145.12:20:30.80#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.12:20:30.86#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.12:20:30.86#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.12:20:30.88#ibcon#[25=AT04-07\r\n] 2006.145.12:20:30.91#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.12:20:30.91#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.12:20:30.91#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.12:20:30.91#ibcon#ireg 7 cls_cnt 0 2006.145.12:20:30.91#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.12:20:31.03#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.12:20:31.03#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.12:20:31.05#ibcon#[25=USB\r\n] 2006.145.12:20:31.09#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.12:20:31.09#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.12:20:31.09#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.12:20:31.09#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.12:20:31.09$vck44/valo=5,734.99 2006.145.12:20:31.09#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.12:20:31.09#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.12:20:31.09#ibcon#ireg 17 cls_cnt 0 2006.145.12:20:31.09#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:20:31.09#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:20:31.09#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:20:31.10#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.12:20:31.14#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:20:31.14#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:20:31.14#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.12:20:31.14#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.12:20:31.14$vck44/va=5,4 2006.145.12:20:31.14#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.12:20:31.14#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.12:20:31.14#ibcon#ireg 11 cls_cnt 2 2006.145.12:20:31.14#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.12:20:31.21#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.12:20:31.21#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.12:20:31.23#ibcon#[25=AT05-04\r\n] 2006.145.12:20:31.28#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.12:20:31.28#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.12:20:31.28#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.12:20:31.28#ibcon#ireg 7 cls_cnt 0 2006.145.12:20:31.28#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.12:20:31.39#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.12:20:31.39#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.12:20:31.41#ibcon#[25=USB\r\n] 2006.145.12:20:31.44#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.12:20:31.44#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.12:20:31.44#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.12:20:31.44#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.12:20:31.44$vck44/valo=6,814.99 2006.145.12:20:31.44#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.12:20:31.44#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.12:20:31.44#ibcon#ireg 17 cls_cnt 0 2006.145.12:20:31.44#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.12:20:31.44#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.12:20:31.44#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.12:20:31.46#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.12:20:31.50#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.12:20:31.50#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.12:20:31.50#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.12:20:31.50#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.12:20:31.50$vck44/va=6,4 2006.145.12:20:31.50#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.12:20:31.50#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.12:20:31.50#ibcon#ireg 11 cls_cnt 2 2006.145.12:20:31.50#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.12:20:31.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.12:20:31.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.12:20:31.58#ibcon#[25=AT06-04\r\n] 2006.145.12:20:31.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.12:20:31.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.12:20:31.61#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.12:20:31.61#ibcon#ireg 7 cls_cnt 0 2006.145.12:20:31.61#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.12:20:31.73#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.12:20:31.73#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.12:20:31.75#ibcon#[25=USB\r\n] 2006.145.12:20:31.78#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.12:20:31.78#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.12:20:31.78#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.12:20:31.78#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.12:20:31.78$vck44/valo=7,864.99 2006.145.12:20:31.78#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.12:20:31.78#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.12:20:31.78#ibcon#ireg 17 cls_cnt 0 2006.145.12:20:31.78#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.12:20:31.78#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.12:20:31.78#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.12:20:31.80#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.12:20:31.84#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.12:20:31.84#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.12:20:31.84#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.12:20:31.84#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.12:20:31.84$vck44/va=7,4 2006.145.12:20:31.84#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.12:20:31.84#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.12:20:31.84#ibcon#ireg 11 cls_cnt 2 2006.145.12:20:31.84#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.12:20:31.90#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.12:20:31.90#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.12:20:31.92#ibcon#[25=AT07-04\r\n] 2006.145.12:20:31.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.12:20:31.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.12:20:31.95#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.12:20:31.95#ibcon#ireg 7 cls_cnt 0 2006.145.12:20:31.95#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.12:20:32.07#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.12:20:32.07#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.12:20:32.09#ibcon#[25=USB\r\n] 2006.145.12:20:32.12#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.12:20:32.12#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.12:20:32.12#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.12:20:32.12#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.12:20:32.12$vck44/valo=8,884.99 2006.145.12:20:32.12#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.12:20:32.12#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.12:20:32.12#ibcon#ireg 17 cls_cnt 0 2006.145.12:20:32.12#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.12:20:32.12#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.12:20:32.12#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.12:20:32.14#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.12:20:32.18#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.12:20:32.18#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.12:20:32.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.12:20:32.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.12:20:32.18$vck44/va=8,4 2006.145.12:20:32.18#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.12:20:32.18#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.12:20:32.18#ibcon#ireg 11 cls_cnt 2 2006.145.12:20:32.18#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.12:20:32.24#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.12:20:32.24#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.12:20:32.26#ibcon#[25=AT08-04\r\n] 2006.145.12:20:32.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.12:20:32.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.12:20:32.29#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.12:20:32.29#ibcon#ireg 7 cls_cnt 0 2006.145.12:20:32.29#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.12:20:32.41#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.12:20:32.41#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.12:20:32.43#ibcon#[25=USB\r\n] 2006.145.12:20:32.46#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.12:20:32.46#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.12:20:32.46#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.12:20:32.46#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.12:20:32.46$vck44/vblo=1,629.99 2006.145.12:20:32.46#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.12:20:32.46#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.12:20:32.46#ibcon#ireg 17 cls_cnt 0 2006.145.12:20:32.46#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.12:20:32.46#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.12:20:32.46#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.12:20:32.49#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.12:20:32.53#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.12:20:32.53#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.12:20:32.53#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.12:20:32.53#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.12:20:32.53$vck44/vb=1,3 2006.145.12:20:32.53#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.12:20:32.53#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.12:20:32.53#ibcon#ireg 11 cls_cnt 2 2006.145.12:20:32.53#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.12:20:32.53#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.12:20:32.53#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.12:20:32.55#ibcon#[27=AT01-03\r\n] 2006.145.12:20:32.58#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.12:20:32.58#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.12:20:32.58#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.12:20:32.58#ibcon#ireg 7 cls_cnt 0 2006.145.12:20:32.58#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.12:20:32.70#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.12:20:32.70#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.12:20:32.72#ibcon#[27=USB\r\n] 2006.145.12:20:32.75#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.12:20:32.75#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.12:20:32.75#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.12:20:32.75#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.12:20:32.75$vck44/vblo=2,634.99 2006.145.12:20:32.75#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.12:20:32.75#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.12:20:32.75#ibcon#ireg 17 cls_cnt 0 2006.145.12:20:32.75#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.12:20:32.75#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.12:20:32.75#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.12:20:32.77#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.12:20:32.81#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.12:20:32.81#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.12:20:32.81#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.12:20:32.81#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.12:20:32.81$vck44/vb=2,4 2006.145.12:20:32.81#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.12:20:32.81#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.12:20:32.81#ibcon#ireg 11 cls_cnt 2 2006.145.12:20:32.81#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.12:20:32.87#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.12:20:32.87#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.12:20:32.89#ibcon#[27=AT02-04\r\n] 2006.145.12:20:32.92#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.12:20:32.92#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.12:20:32.92#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.12:20:32.92#ibcon#ireg 7 cls_cnt 0 2006.145.12:20:32.92#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.12:20:33.03#abcon#<5=/05 1.5 2.2 15.85 781020.6\r\n> 2006.145.12:20:33.04#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.12:20:33.04#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.12:20:33.05#abcon#{5=INTERFACE CLEAR} 2006.145.12:20:33.06#ibcon#[27=USB\r\n] 2006.145.12:20:33.09#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.12:20:33.09#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.12:20:33.09#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.12:20:33.09#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.12:20:33.09$vck44/vblo=3,649.99 2006.145.12:20:33.09#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.12:20:33.09#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.12:20:33.09#ibcon#ireg 17 cls_cnt 0 2006.145.12:20:33.09#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.12:20:33.09#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.12:20:33.09#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.12:20:33.11#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.12:20:33.11#abcon#[5=S1D000X0/0*\r\n] 2006.145.12:20:33.15#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.12:20:33.15#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.12:20:33.15#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.12:20:33.15#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.12:20:33.15$vck44/vb=3,4 2006.145.12:20:33.15#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.12:20:33.15#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.12:20:33.15#ibcon#ireg 11 cls_cnt 2 2006.145.12:20:33.15#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.12:20:33.21#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.12:20:33.21#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.12:20:33.23#ibcon#[27=AT03-04\r\n] 2006.145.12:20:33.26#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.12:20:33.26#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.12:20:33.26#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.12:20:33.26#ibcon#ireg 7 cls_cnt 0 2006.145.12:20:33.26#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.12:20:33.38#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.12:20:33.38#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.12:20:33.40#ibcon#[27=USB\r\n] 2006.145.12:20:33.43#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.12:20:33.43#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.12:20:33.43#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.12:20:33.43#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.12:20:33.43$vck44/vblo=4,679.99 2006.145.12:20:33.43#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.12:20:33.43#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.12:20:33.43#ibcon#ireg 17 cls_cnt 0 2006.145.12:20:33.43#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.12:20:33.43#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.12:20:33.43#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.12:20:33.45#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.12:20:33.49#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.12:20:33.49#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.12:20:33.49#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.12:20:33.49#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.12:20:33.49$vck44/vb=4,4 2006.145.12:20:33.49#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.12:20:33.49#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.12:20:33.49#ibcon#ireg 11 cls_cnt 2 2006.145.12:20:33.49#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.12:20:33.55#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.12:20:33.55#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.12:20:33.57#ibcon#[27=AT04-04\r\n] 2006.145.12:20:33.60#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.12:20:33.60#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.12:20:33.60#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.12:20:33.60#ibcon#ireg 7 cls_cnt 0 2006.145.12:20:33.60#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.12:20:33.72#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.12:20:33.72#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.12:20:33.74#ibcon#[27=USB\r\n] 2006.145.12:20:33.77#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.12:20:33.77#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.12:20:33.77#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.12:20:33.77#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.12:20:33.77$vck44/vblo=5,709.99 2006.145.12:20:33.77#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.12:20:33.77#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.12:20:33.77#ibcon#ireg 17 cls_cnt 0 2006.145.12:20:33.77#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:20:33.77#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:20:33.77#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:20:33.79#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.12:20:33.83#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:20:33.83#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:20:33.83#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.12:20:33.83#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.12:20:33.83$vck44/vb=5,4 2006.145.12:20:33.83#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.12:20:33.83#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.12:20:33.83#ibcon#ireg 11 cls_cnt 2 2006.145.12:20:33.83#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.12:20:33.89#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.12:20:33.89#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.12:20:33.91#ibcon#[27=AT05-04\r\n] 2006.145.12:20:33.94#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.12:20:33.94#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.12:20:33.94#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.12:20:33.94#ibcon#ireg 7 cls_cnt 0 2006.145.12:20:33.94#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.12:20:34.06#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.12:20:34.06#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.12:20:34.08#ibcon#[27=USB\r\n] 2006.145.12:20:34.11#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.12:20:34.11#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.12:20:34.11#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.12:20:34.11#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.12:20:34.11$vck44/vblo=6,719.99 2006.145.12:20:34.11#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.12:20:34.11#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.12:20:34.11#ibcon#ireg 17 cls_cnt 0 2006.145.12:20:34.11#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.12:20:34.11#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.12:20:34.11#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.12:20:34.13#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.12:20:34.17#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.12:20:34.17#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.12:20:34.17#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.12:20:34.17#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.12:20:34.17$vck44/vb=6,4 2006.145.12:20:34.17#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.12:20:34.17#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.12:20:34.17#ibcon#ireg 11 cls_cnt 2 2006.145.12:20:34.17#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.12:20:34.23#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.12:20:34.23#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.12:20:34.25#ibcon#[27=AT06-04\r\n] 2006.145.12:20:34.28#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.12:20:34.28#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.12:20:34.28#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.12:20:34.28#ibcon#ireg 7 cls_cnt 0 2006.145.12:20:34.28#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.12:20:34.40#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.12:20:34.40#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.12:20:34.42#ibcon#[27=USB\r\n] 2006.145.12:20:34.45#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.12:20:34.45#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.12:20:34.45#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.12:20:34.45#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.12:20:34.45$vck44/vblo=7,734.99 2006.145.12:20:34.45#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.12:20:34.45#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.12:20:34.45#ibcon#ireg 17 cls_cnt 0 2006.145.12:20:34.45#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.12:20:34.45#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.12:20:34.45#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.12:20:34.47#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.12:20:34.51#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.12:20:34.51#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.12:20:34.51#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.12:20:34.51#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.12:20:34.51$vck44/vb=7,4 2006.145.12:20:34.51#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.12:20:34.51#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.12:20:34.51#ibcon#ireg 11 cls_cnt 2 2006.145.12:20:34.51#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.12:20:34.57#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.12:20:34.57#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.12:20:34.59#ibcon#[27=AT07-04\r\n] 2006.145.12:20:34.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.12:20:34.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.12:20:34.62#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.12:20:34.62#ibcon#ireg 7 cls_cnt 0 2006.145.12:20:34.62#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.12:20:34.74#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.12:20:34.74#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.12:20:34.76#ibcon#[27=USB\r\n] 2006.145.12:20:34.79#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.12:20:34.79#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.12:20:34.79#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.12:20:34.79#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.12:20:34.79$vck44/vblo=8,744.99 2006.145.12:20:34.79#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.12:20:34.79#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.12:20:34.79#ibcon#ireg 17 cls_cnt 0 2006.145.12:20:34.79#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.12:20:34.79#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.12:20:34.79#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.12:20:34.81#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.12:20:34.85#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.12:20:34.85#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.12:20:34.85#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.12:20:34.85#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.12:20:34.85$vck44/vb=8,4 2006.145.12:20:34.85#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.12:20:34.85#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.12:20:34.85#ibcon#ireg 11 cls_cnt 2 2006.145.12:20:34.85#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.12:20:34.91#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.12:20:34.91#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.12:20:34.93#ibcon#[27=AT08-04\r\n] 2006.145.12:20:34.96#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.12:20:34.96#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.12:20:34.96#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.12:20:34.96#ibcon#ireg 7 cls_cnt 0 2006.145.12:20:34.96#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.12:20:35.08#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.12:20:35.08#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.12:20:35.10#ibcon#[27=USB\r\n] 2006.145.12:20:35.13#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.12:20:35.13#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.12:20:35.13#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.12:20:35.13#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.12:20:35.13$vck44/vabw=wide 2006.145.12:20:35.13#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.12:20:35.13#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.12:20:35.13#ibcon#ireg 8 cls_cnt 0 2006.145.12:20:35.13#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.12:20:35.13#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.12:20:35.13#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.12:20:35.15#ibcon#[25=BW32\r\n] 2006.145.12:20:35.18#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.12:20:35.18#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.12:20:35.18#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.12:20:35.18#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.12:20:35.18$vck44/vbbw=wide 2006.145.12:20:35.18#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.12:20:35.18#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.12:20:35.18#ibcon#ireg 8 cls_cnt 0 2006.145.12:20:35.18#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.12:20:35.25#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.12:20:35.25#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.12:20:35.27#ibcon#[27=BW32\r\n] 2006.145.12:20:35.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.12:20:35.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.12:20:35.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.12:20:35.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.12:20:35.30$setupk4/ifdk4 2006.145.12:20:35.30$ifdk4/lo= 2006.145.12:20:35.30$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.12:20:35.30$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.12:20:35.30$ifdk4/patch= 2006.145.12:20:35.30$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.12:20:35.30$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.12:20:35.30$setupk4/!*+20s 2006.145.12:20:43.20#abcon#<5=/05 1.5 2.2 15.85 781020.6\r\n> 2006.145.12:20:43.22#abcon#{5=INTERFACE CLEAR} 2006.145.12:20:43.28#abcon#[5=S1D000X0/0*\r\n] 2006.145.12:20:49.73$setupk4/"tpicd 2006.145.12:20:49.73$setupk4/echo=off 2006.145.12:20:49.73$setupk4/xlog=off 2006.145.12:20:49.73:!2006.145.12:22:49 2006.145.12:21:17.14#trakl#Source acquired 2006.145.12:21:18.14#flagr#flagr/antenna,acquired 2006.145.12:22:49.00:preob 2006.145.12:22:49.14/onsource/TRACKING 2006.145.12:22:49.14:!2006.145.12:22:59 2006.145.12:22:59.00:"tape 2006.145.12:22:59.00:"st=record 2006.145.12:22:59.00:data_valid=on 2006.145.12:22:59.00:midob 2006.145.12:23:00.14/onsource/TRACKING 2006.145.12:23:00.14/wx/15.82,1020.6,78 2006.145.12:23:00.29/cable/+6.5477E-03 2006.145.12:23:01.38/va/01,08,usb,yes,41,44 2006.145.12:23:01.38/va/02,07,usb,yes,44,45 2006.145.12:23:01.38/va/03,08,usb,yes,40,42 2006.145.12:23:01.38/va/04,07,usb,yes,45,48 2006.145.12:23:01.38/va/05,04,usb,yes,40,41 2006.145.12:23:01.38/va/06,04,usb,yes,44,44 2006.145.12:23:01.38/va/07,04,usb,yes,45,46 2006.145.12:23:01.38/va/08,04,usb,yes,39,46 2006.145.12:23:01.61/valo/01,524.99,yes,locked 2006.145.12:23:01.61/valo/02,534.99,yes,locked 2006.145.12:23:01.61/valo/03,564.99,yes,locked 2006.145.12:23:01.61/valo/04,624.99,yes,locked 2006.145.12:23:01.61/valo/05,734.99,yes,locked 2006.145.12:23:01.61/valo/06,814.99,yes,locked 2006.145.12:23:01.61/valo/07,864.99,yes,locked 2006.145.12:23:01.61/valo/08,884.99,yes,locked 2006.145.12:23:02.70/vb/01,03,usb,yes,56,99 2006.145.12:23:02.70/vb/02,04,usb,yes,35,96 2006.145.12:23:02.70/vb/03,04,usb,yes,30,80 2006.145.12:23:02.70/vb/04,04,usb,yes,34,33 2006.145.12:23:02.70/vb/05,04,usb,yes,29,32 2006.145.12:23:02.70/vb/06,04,usb,yes,34,30 2006.145.12:23:02.70/vb/07,04,usb,yes,32,32 2006.145.12:23:02.70/vb/08,04,usb,yes,30,33 2006.145.12:23:02.94/vblo/01,629.99,yes,locked 2006.145.12:23:02.94/vblo/02,634.99,yes,locked 2006.145.12:23:02.94/vblo/03,649.99,yes,locked 2006.145.12:23:02.94/vblo/04,679.99,yes,locked 2006.145.12:23:02.94/vblo/05,709.99,yes,locked 2006.145.12:23:02.94/vblo/06,719.99,yes,locked 2006.145.12:23:02.94/vblo/07,734.99,yes,locked 2006.145.12:23:02.94/vblo/08,744.99,yes,locked 2006.145.12:23:03.09/vabw/8 2006.145.12:23:03.24/vbbw/8 2006.145.12:23:03.33/xfe/off,on,15.2 2006.145.12:23:03.71/ifatt/23,28,28,28 2006.145.12:23:04.08/fmout-gps/S +5.3E-08 2006.145.12:23:04.16:!2006.145.12:35:59 2006.145.12:35:59.02:data_valid=off 2006.145.12:35:59.02:"et 2006.145.12:35:59.02:!+3s 2006.145.12:36:02.06:"tape 2006.145.12:36:02.06:postob 2006.145.12:36:02.25/cable/+6.5460E-03 2006.145.12:36:02.26/wx/15.70,1020.6,80 2006.145.12:36:02.31/fmout-gps/S +5.5E-08 2006.145.12:36:02.32:scan_name=145-1237,jd0605,40 2006.145.12:36:02.32:source=1424-418,142756.30,-420619.4,2000.0,cw 2006.145.12:36:03.15#flagr#flagr/antenna,new-source 2006.145.12:36:03.15:checkk5 2006.145.12:36:03.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.12:36:04.04/chk_autoobs//k5ts2/ autoobs is running! 2006.145.12:36:04.49/chk_autoobs//k5ts3/ autoobs is running! 2006.145.12:36:04.92/chk_autoobs//k5ts4/ autoobs is running! 2006.145.12:36:05.65/chk_obsdata//k5ts1/T1451222??a.dat file size is correct (nominal:3120MB, actual:3120MB). 2006.145.12:36:06.39/chk_obsdata//k5ts2/T1451222??b.dat file size is correct (nominal:3120MB, actual:3120MB). 2006.145.12:36:07.14/chk_obsdata//k5ts3/T1451222??c.dat file size is correct (nominal:3120MB, actual:3120MB). 2006.145.12:36:07.88/chk_obsdata//k5ts4/T1451222??d.dat file size is correct (nominal:3120MB, actual:3120MB). 2006.145.12:36:08.62/k5log//k5ts1_log_newline 2006.145.12:36:09.36/k5log//k5ts2_log_newline 2006.145.12:36:10.10/k5log//k5ts3_log_newline 2006.145.12:36:10.83/k5log//k5ts4_log_newline 2006.145.12:36:10.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.12:36:10.86:setupk4=1 2006.145.12:36:10.86$setupk4/echo=on 2006.145.12:36:10.86$setupk4/pcalon 2006.145.12:36:10.86$pcalon/"no phase cal control is implemented here 2006.145.12:36:10.86$setupk4/"tpicd=stop 2006.145.12:36:10.86$setupk4/"rec=synch_on 2006.145.12:36:10.86$setupk4/"rec_mode=128 2006.145.12:36:10.86$setupk4/!* 2006.145.12:36:10.86$setupk4/recpk4 2006.145.12:36:10.86$recpk4/recpatch= 2006.145.12:36:10.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.12:36:10.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.12:36:10.87$setupk4/vck44 2006.145.12:36:10.87$vck44/valo=1,524.99 2006.145.12:36:10.87#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.12:36:10.87#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.12:36:10.87#ibcon#ireg 17 cls_cnt 0 2006.145.12:36:10.87#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.12:36:10.87#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.12:36:10.87#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.12:36:10.90#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.12:36:10.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.12:36:10.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.12:36:10.95#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.12:36:10.95#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.12:36:10.95$vck44/va=1,8 2006.145.12:36:10.95#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.12:36:10.96#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.12:36:10.96#ibcon#ireg 11 cls_cnt 2 2006.145.12:36:10.96#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.12:36:10.96#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.12:36:10.96#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.12:36:10.97#ibcon#[25=AT01-08\r\n] 2006.145.12:36:11.00#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.12:36:11.00#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.12:36:11.00#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.12:36:11.00#ibcon#ireg 7 cls_cnt 0 2006.145.12:36:11.00#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.12:36:11.12#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.12:36:11.12#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.12:36:11.14#ibcon#[25=USB\r\n] 2006.145.12:36:11.20#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.12:36:11.20#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.12:36:11.20#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.12:36:11.20#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.12:36:11.20$vck44/valo=2,534.99 2006.145.12:36:11.20#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.12:36:11.20#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.12:36:11.20#ibcon#ireg 17 cls_cnt 0 2006.145.12:36:11.20#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.12:36:11.20#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.12:36:11.20#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.12:36:11.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.12:36:11.25#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.12:36:11.25#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.12:36:11.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.12:36:11.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.12:36:11.25$vck44/va=2,7 2006.145.12:36:11.26#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.12:36:11.26#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.12:36:11.26#ibcon#ireg 11 cls_cnt 2 2006.145.12:36:11.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.12:36:11.31#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.12:36:11.31#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.12:36:11.33#ibcon#[25=AT02-07\r\n] 2006.145.12:36:11.36#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.12:36:11.36#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.12:36:11.36#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.12:36:11.36#ibcon#ireg 7 cls_cnt 0 2006.145.12:36:11.36#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.12:36:11.48#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.12:36:11.48#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.12:36:11.50#ibcon#[25=USB\r\n] 2006.145.12:36:11.53#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.12:36:11.53#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.12:36:11.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.12:36:11.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.12:36:11.53$vck44/valo=3,564.99 2006.145.12:36:11.53#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.12:36:11.53#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.12:36:11.54#ibcon#ireg 17 cls_cnt 0 2006.145.12:36:11.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.12:36:11.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.12:36:11.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.12:36:11.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.12:36:11.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.12:36:11.59#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.12:36:11.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.12:36:11.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.12:36:11.59$vck44/va=3,8 2006.145.12:36:11.60#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.12:36:11.60#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.12:36:11.60#ibcon#ireg 11 cls_cnt 2 2006.145.12:36:11.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.12:36:11.64#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.12:36:11.64#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.12:36:11.66#ibcon#[25=AT03-08\r\n] 2006.145.12:36:11.69#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.12:36:11.69#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.12:36:11.69#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.12:36:11.69#ibcon#ireg 7 cls_cnt 0 2006.145.12:36:11.69#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.12:36:11.81#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.12:36:11.81#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.12:36:11.83#ibcon#[25=USB\r\n] 2006.145.12:36:11.86#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.12:36:11.86#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.12:36:11.86#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.12:36:11.86#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.12:36:11.86$vck44/valo=4,624.99 2006.145.12:36:11.87#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.12:36:11.87#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.12:36:11.87#ibcon#ireg 17 cls_cnt 0 2006.145.12:36:11.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.12:36:11.87#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.12:36:11.87#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.12:36:11.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.12:36:11.92#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.12:36:11.92#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.12:36:11.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.12:36:11.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.12:36:11.92$vck44/va=4,7 2006.145.12:36:11.92#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.12:36:11.93#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.12:36:11.93#ibcon#ireg 11 cls_cnt 2 2006.145.12:36:11.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.12:36:11.97#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.12:36:11.97#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.12:36:11.99#ibcon#[25=AT04-07\r\n] 2006.145.12:36:12.02#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.12:36:12.02#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.12:36:12.02#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.12:36:12.02#ibcon#ireg 7 cls_cnt 0 2006.145.12:36:12.02#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.12:36:12.14#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.12:36:12.14#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.12:36:12.16#ibcon#[25=USB\r\n] 2006.145.12:36:12.20#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.12:36:12.20#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.12:36:12.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.12:36:12.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.12:36:12.20$vck44/valo=5,734.99 2006.145.12:36:12.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.12:36:12.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.12:36:12.20#ibcon#ireg 17 cls_cnt 0 2006.145.12:36:12.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.12:36:12.20#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.12:36:12.20#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.12:36:12.22#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.12:36:12.25#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.12:36:12.25#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.12:36:12.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.12:36:12.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.12:36:12.26$vck44/va=5,4 2006.145.12:36:12.26#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.12:36:12.26#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.12:36:12.26#ibcon#ireg 11 cls_cnt 2 2006.145.12:36:12.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.12:36:12.32#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.12:36:12.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.12:36:12.33#ibcon#[25=AT05-04\r\n] 2006.145.12:36:12.36#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.12:36:12.36#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.12:36:12.36#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.12:36:12.36#ibcon#ireg 7 cls_cnt 0 2006.145.12:36:12.36#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.12:36:12.49#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.12:36:12.49#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.12:36:12.50#ibcon#[25=USB\r\n] 2006.145.12:36:12.53#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.12:36:12.53#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.12:36:12.53#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.12:36:12.53#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.12:36:12.53$vck44/valo=6,814.99 2006.145.12:36:12.53#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.12:36:12.54#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.12:36:12.54#ibcon#ireg 17 cls_cnt 0 2006.145.12:36:12.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.12:36:12.54#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.12:36:12.54#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.12:36:12.55#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.12:36:12.59#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.12:36:12.59#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.12:36:12.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.12:36:12.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.12:36:12.59$vck44/va=6,4 2006.145.12:36:12.59#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.12:36:12.59#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.12:36:12.60#ibcon#ireg 11 cls_cnt 2 2006.145.12:36:12.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.12:36:12.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.12:36:12.64#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.12:36:12.66#ibcon#[25=AT06-04\r\n] 2006.145.12:36:12.69#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.12:36:12.69#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.12:36:12.69#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.12:36:12.69#ibcon#ireg 7 cls_cnt 0 2006.145.12:36:12.69#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.12:36:12.81#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.12:36:12.81#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.12:36:12.83#ibcon#[25=USB\r\n] 2006.145.12:36:12.86#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.12:36:12.86#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.12:36:12.86#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.12:36:12.86#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.12:36:12.86$vck44/valo=7,864.99 2006.145.12:36:12.87#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.12:36:12.87#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.12:36:12.87#ibcon#ireg 17 cls_cnt 0 2006.145.12:36:12.87#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.12:36:12.87#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.12:36:12.87#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.12:36:12.88#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.12:36:12.92#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.12:36:12.92#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.12:36:12.92#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.12:36:12.92#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.12:36:12.92$vck44/va=7,4 2006.145.12:36:12.92#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.12:36:12.92#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.12:36:12.92#ibcon#ireg 11 cls_cnt 2 2006.145.12:36:12.93#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.12:36:12.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.12:36:12.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.12:36:13.00#ibcon#[25=AT07-04\r\n] 2006.145.12:36:13.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.12:36:13.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.12:36:13.03#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.12:36:13.03#ibcon#ireg 7 cls_cnt 0 2006.145.12:36:13.03#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.12:36:13.15#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.12:36:13.15#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.12:36:13.17#ibcon#[25=USB\r\n] 2006.145.12:36:13.20#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.12:36:13.20#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.12:36:13.20#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.12:36:13.20#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.12:36:13.20$vck44/valo=8,884.99 2006.145.12:36:13.21#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.12:36:13.21#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.12:36:13.21#ibcon#ireg 17 cls_cnt 0 2006.145.12:36:13.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.12:36:13.21#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.12:36:13.21#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.12:36:13.22#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.12:36:13.26#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.12:36:13.26#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.12:36:13.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.12:36:13.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.12:36:13.26$vck44/va=8,4 2006.145.12:36:13.26#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.12:36:13.26#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.12:36:13.26#ibcon#ireg 11 cls_cnt 2 2006.145.12:36:13.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.12:36:13.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.12:36:13.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.12:36:13.34#ibcon#[25=AT08-04\r\n] 2006.145.12:36:13.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.12:36:13.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.12:36:13.37#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.12:36:13.37#ibcon#ireg 7 cls_cnt 0 2006.145.12:36:13.37#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.12:36:13.49#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.12:36:13.49#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.12:36:13.51#ibcon#[25=USB\r\n] 2006.145.12:36:13.54#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.12:36:13.54#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.12:36:13.54#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.12:36:13.54#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.12:36:13.55$vck44/vblo=1,629.99 2006.145.12:36:13.55#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.12:36:13.55#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.12:36:13.55#ibcon#ireg 17 cls_cnt 0 2006.145.12:36:13.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.12:36:13.55#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.12:36:13.55#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.12:36:13.56#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.12:36:13.60#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.12:36:13.60#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.12:36:13.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.12:36:13.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.12:36:13.61$vck44/vb=1,3 2006.145.12:36:13.61#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.12:36:13.61#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.12:36:13.61#ibcon#ireg 11 cls_cnt 2 2006.145.12:36:13.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.12:36:13.61#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.12:36:13.61#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.12:36:13.62#ibcon#[27=AT01-03\r\n] 2006.145.12:36:13.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.12:36:13.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.12:36:13.65#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.12:36:13.65#ibcon#ireg 7 cls_cnt 0 2006.145.12:36:13.65#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.12:36:13.77#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.12:36:13.77#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.12:36:13.79#ibcon#[27=USB\r\n] 2006.145.12:36:13.82#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.12:36:13.82#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.12:36:13.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.12:36:13.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.12:36:13.83$vck44/vblo=2,634.99 2006.145.12:36:13.83#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.12:36:13.83#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.12:36:13.83#ibcon#ireg 17 cls_cnt 0 2006.145.12:36:13.83#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.12:36:13.83#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.12:36:13.83#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.12:36:13.84#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.12:36:13.88#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.12:36:13.88#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.12:36:13.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.12:36:13.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.12:36:13.89$vck44/vb=2,4 2006.145.12:36:13.89#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.12:36:13.89#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.12:36:13.89#ibcon#ireg 11 cls_cnt 2 2006.145.12:36:13.89#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.12:36:13.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.12:36:13.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.12:36:13.95#ibcon#[27=AT02-04\r\n] 2006.145.12:36:13.98#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.12:36:13.98#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.12:36:13.98#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.12:36:13.98#ibcon#ireg 7 cls_cnt 0 2006.145.12:36:13.98#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.12:36:14.10#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.12:36:14.10#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.12:36:14.12#ibcon#[27=USB\r\n] 2006.145.12:36:14.15#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.12:36:14.15#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.12:36:14.15#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.12:36:14.15#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.12:36:14.15$vck44/vblo=3,649.99 2006.145.12:36:14.15#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.12:36:14.16#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.12:36:14.16#ibcon#ireg 17 cls_cnt 0 2006.145.12:36:14.16#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.12:36:14.16#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.12:36:14.16#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.12:36:14.17#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.12:36:14.21#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.12:36:14.21#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.12:36:14.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.12:36:14.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.12:36:14.21$vck44/vb=3,4 2006.145.12:36:14.21#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.12:36:14.21#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.12:36:14.21#ibcon#ireg 11 cls_cnt 2 2006.145.12:36:14.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.12:36:14.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.12:36:14.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.12:36:14.29#ibcon#[27=AT03-04\r\n] 2006.145.12:36:14.32#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.12:36:14.32#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.12:36:14.32#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.12:36:14.32#ibcon#ireg 7 cls_cnt 0 2006.145.12:36:14.32#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.12:36:14.44#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.12:36:14.44#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.12:36:14.46#ibcon#[27=USB\r\n] 2006.145.12:36:14.49#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.12:36:14.49#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.12:36:14.49#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.12:36:14.49#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.12:36:14.49$vck44/vblo=4,679.99 2006.145.12:36:14.49#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.12:36:14.49#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.12:36:14.50#ibcon#ireg 17 cls_cnt 0 2006.145.12:36:14.50#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.12:36:14.50#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.12:36:14.50#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.12:36:14.51#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.12:36:14.55#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.12:36:14.55#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.12:36:14.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.12:36:14.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.12:36:14.55$vck44/vb=4,4 2006.145.12:36:14.55#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.12:36:14.55#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.12:36:14.55#ibcon#ireg 11 cls_cnt 2 2006.145.12:36:14.56#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.12:36:14.60#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.12:36:14.60#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.12:36:14.62#ibcon#[27=AT04-04\r\n] 2006.145.12:36:14.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.12:36:14.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.12:36:14.65#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.12:36:14.65#ibcon#ireg 7 cls_cnt 0 2006.145.12:36:14.65#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.12:36:14.77#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.12:36:14.77#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.12:36:14.79#ibcon#[27=USB\r\n] 2006.145.12:36:14.82#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.12:36:14.82#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.12:36:14.82#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.12:36:14.82#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.12:36:14.82$vck44/vblo=5,709.99 2006.145.12:36:14.83#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.12:36:14.83#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.12:36:14.83#ibcon#ireg 17 cls_cnt 0 2006.145.12:36:14.83#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.12:36:14.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.12:36:14.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.12:36:14.84#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.12:36:14.88#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.12:36:14.88#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.12:36:14.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.12:36:14.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.12:36:14.88$vck44/vb=5,4 2006.145.12:36:14.88#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.12:36:14.88#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.12:36:14.88#ibcon#ireg 11 cls_cnt 2 2006.145.12:36:14.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.12:36:14.94#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.12:36:14.94#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.12:36:14.96#ibcon#[27=AT05-04\r\n] 2006.145.12:36:14.99#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.12:36:14.99#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.12:36:14.99#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.12:36:14.99#ibcon#ireg 7 cls_cnt 0 2006.145.12:36:14.99#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.12:36:15.11#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.12:36:15.11#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.12:36:15.13#ibcon#[27=USB\r\n] 2006.145.12:36:15.16#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.12:36:15.16#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.12:36:15.16#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.12:36:15.16#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.12:36:15.17$vck44/vblo=6,719.99 2006.145.12:36:15.17#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.12:36:15.17#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.12:36:15.17#ibcon#ireg 17 cls_cnt 0 2006.145.12:36:15.17#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.12:36:15.17#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.12:36:15.17#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.12:36:15.18#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.12:36:15.22#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.12:36:15.22#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.12:36:15.22#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.12:36:15.22#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.12:36:15.22$vck44/vb=6,4 2006.145.12:36:15.23#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.12:36:15.23#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.12:36:15.23#ibcon#ireg 11 cls_cnt 2 2006.145.12:36:15.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.12:36:15.27#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.12:36:15.27#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.12:36:15.29#ibcon#[27=AT06-04\r\n] 2006.145.12:36:15.32#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.12:36:15.32#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.12:36:15.32#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.12:36:15.32#ibcon#ireg 7 cls_cnt 0 2006.145.12:36:15.32#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.12:36:15.44#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.12:36:15.44#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.12:36:15.46#ibcon#[27=USB\r\n] 2006.145.12:36:15.49#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.12:36:15.49#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.12:36:15.49#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.12:36:15.49#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.12:36:15.49$vck44/vblo=7,734.99 2006.145.12:36:15.49#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.12:36:15.49#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.12:36:15.49#ibcon#ireg 17 cls_cnt 0 2006.145.12:36:15.49#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.12:36:15.49#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.12:36:15.49#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.12:36:15.51#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.12:36:15.55#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.12:36:15.55#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.12:36:15.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.12:36:15.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.12:36:15.55$vck44/vb=7,4 2006.145.12:36:15.55#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.12:36:15.55#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.12:36:15.55#ibcon#ireg 11 cls_cnt 2 2006.145.12:36:15.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.12:36:15.61#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.12:36:15.61#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.12:36:15.63#ibcon#[27=AT07-04\r\n] 2006.145.12:36:15.66#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.12:36:15.66#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.12:36:15.66#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.12:36:15.66#ibcon#ireg 7 cls_cnt 0 2006.145.12:36:15.66#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.12:36:15.78#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.12:36:15.78#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.12:36:15.80#ibcon#[27=USB\r\n] 2006.145.12:36:15.83#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.12:36:15.83#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.12:36:15.83#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.12:36:15.83#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.12:36:15.83$vck44/vblo=8,744.99 2006.145.12:36:15.83#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.12:36:15.83#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.12:36:15.83#ibcon#ireg 17 cls_cnt 0 2006.145.12:36:15.83#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.12:36:15.83#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.12:36:15.83#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.12:36:15.85#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.12:36:15.89#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.12:36:15.89#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.12:36:15.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.12:36:15.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.12:36:15.89$vck44/vb=8,4 2006.145.12:36:15.89#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.12:36:15.89#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.12:36:15.89#ibcon#ireg 11 cls_cnt 2 2006.145.12:36:15.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.12:36:15.95#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.12:36:15.95#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.12:36:15.97#ibcon#[27=AT08-04\r\n] 2006.145.12:36:16.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.12:36:16.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.12:36:16.00#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.12:36:16.00#ibcon#ireg 7 cls_cnt 0 2006.145.12:36:16.00#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.12:36:16.12#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.12:36:16.12#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.12:36:16.14#ibcon#[27=USB\r\n] 2006.145.12:36:16.17#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.12:36:16.17#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.12:36:16.17#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.12:36:16.17#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.12:36:16.17$vck44/vabw=wide 2006.145.12:36:16.17#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.12:36:16.17#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.12:36:16.17#ibcon#ireg 8 cls_cnt 0 2006.145.12:36:16.17#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.12:36:16.17#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.12:36:16.17#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.12:36:16.19#ibcon#[25=BW32\r\n] 2006.145.12:36:16.22#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.12:36:16.22#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.12:36:16.22#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.12:36:16.22#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.12:36:16.22$vck44/vbbw=wide 2006.145.12:36:16.22#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.12:36:16.22#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.12:36:16.22#ibcon#ireg 8 cls_cnt 0 2006.145.12:36:16.22#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.12:36:16.29#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.12:36:16.29#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.12:36:16.31#ibcon#[27=BW32\r\n] 2006.145.12:36:16.34#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.12:36:16.34#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.12:36:16.34#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.12:36:16.34#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.12:36:16.34$setupk4/ifdk4 2006.145.12:36:16.34$ifdk4/lo= 2006.145.12:36:16.35$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.12:36:16.35$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.12:36:16.35$ifdk4/patch= 2006.145.12:36:16.35$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.12:36:16.35$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.12:36:16.35$setupk4/!*+20s 2006.145.12:36:18.97#abcon#<5=/05 1.4 2.2 15.70 801020.6\r\n> 2006.145.12:36:18.99#abcon#{5=INTERFACE CLEAR} 2006.145.12:36:19.05#abcon#[5=S1D000X0/0*\r\n] 2006.145.12:36:29.14#abcon#<5=/05 1.4 2.2 15.69 801020.5\r\n> 2006.145.12:36:29.16#abcon#{5=INTERFACE CLEAR} 2006.145.12:36:29.22#abcon#[5=S1D000X0/0*\r\n] 2006.145.12:36:30.88$setupk4/"tpicd 2006.145.12:36:30.88$setupk4/echo=off 2006.145.12:36:30.88$setupk4/xlog=off 2006.145.12:36:30.88:!2006.145.12:37:09 2006.145.12:37:04.14#trakl#Source acquired 2006.145.12:37:05.14#flagr#flagr/antenna,acquired 2006.145.12:37:09.00:preob 2006.145.12:37:09.14/onsource/TRACKING 2006.145.12:37:09.15:!2006.145.12:37:19 2006.145.12:37:19.01:"tape 2006.145.12:37:19.01:"st=record 2006.145.12:37:19.01:data_valid=on 2006.145.12:37:19.02:midob 2006.145.12:37:20.14/onsource/TRACKING 2006.145.12:37:20.15/wx/15.69,1020.6,80 2006.145.12:37:20.20/cable/+6.5470E-03 2006.145.12:37:21.29/va/01,08,usb,yes,32,35 2006.145.12:37:21.29/va/02,07,usb,yes,34,35 2006.145.12:37:21.29/va/03,08,usb,yes,31,33 2006.145.12:37:21.29/va/04,07,usb,yes,36,38 2006.145.12:37:21.29/va/05,04,usb,yes,31,32 2006.145.12:37:21.29/va/06,04,usb,yes,35,35 2006.145.12:37:21.29/va/07,04,usb,yes,35,36 2006.145.12:37:21.29/va/08,04,usb,yes,30,36 2006.145.12:37:21.52/valo/01,524.99,yes,locked 2006.145.12:37:21.52/valo/02,534.99,yes,locked 2006.145.12:37:21.52/valo/03,564.99,yes,locked 2006.145.12:37:21.52/valo/04,624.99,yes,locked 2006.145.12:37:21.52/valo/05,734.99,yes,locked 2006.145.12:37:21.52/valo/06,814.99,yes,locked 2006.145.12:37:21.52/valo/07,864.99,yes,locked 2006.145.12:37:21.52/valo/08,884.99,yes,locked 2006.145.12:37:22.61/vb/01,03,usb,yes,38,36 2006.145.12:37:22.61/vb/02,04,usb,yes,34,33 2006.145.12:37:22.61/vb/03,04,usb,yes,31,34 2006.145.12:37:22.61/vb/04,04,usb,yes,35,34 2006.145.12:37:22.61/vb/05,04,usb,yes,27,30 2006.145.12:37:22.61/vb/06,04,usb,yes,32,28 2006.145.12:37:22.61/vb/07,04,usb,yes,32,32 2006.145.12:37:22.61/vb/08,04,usb,yes,29,33 2006.145.12:37:22.84/vblo/01,629.99,yes,locked 2006.145.12:37:22.84/vblo/02,634.99,yes,locked 2006.145.12:37:22.84/vblo/03,649.99,yes,locked 2006.145.12:37:22.84/vblo/04,679.99,yes,locked 2006.145.12:37:22.84/vblo/05,709.99,yes,locked 2006.145.12:37:22.84/vblo/06,719.99,yes,locked 2006.145.12:37:22.84/vblo/07,734.99,yes,locked 2006.145.12:37:22.84/vblo/08,744.99,yes,locked 2006.145.12:37:22.99/vabw/8 2006.145.12:37:23.14/vbbw/8 2006.145.12:37:23.23/xfe/off,on,14.5 2006.145.12:37:23.60/ifatt/23,28,28,28 2006.145.12:37:24.07/fmout-gps/S +5.6E-08 2006.145.12:37:24.15:!2006.145.12:37:59 2006.145.12:37:59.01:data_valid=off 2006.145.12:37:59.02:"et 2006.145.12:37:59.02:!+3s 2006.145.12:38:02.05:"tape 2006.145.12:38:02.09:postob 2006.145.12:38:02.28/cable/+6.5467E-03 2006.145.12:38:02.29/wx/15.68,1020.6,80 2006.145.12:38:02.37/fmout-gps/S +5.7E-08 2006.145.12:38:02.37:scan_name=145-1242,jd0605,40 2006.145.12:38:02.37:source=3c345,164258.81,394837.0,2000.0,cw 2006.145.12:38:04.14#flagr#flagr/antenna,new-source 2006.145.12:38:04.15:checkk5 2006.145.12:38:04.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.12:38:05.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.12:38:05.51/chk_autoobs//k5ts3/ autoobs is running! 2006.145.12:38:05.94/chk_autoobs//k5ts4/ autoobs is running! 2006.145.12:38:06.36/chk_obsdata//k5ts1/T1451237??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.12:38:06.79/chk_obsdata//k5ts2/T1451237??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.12:38:07.23/chk_obsdata//k5ts3/T1451237??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.12:38:07.68/chk_obsdata//k5ts4/T1451237??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.12:38:08.45/k5log//k5ts1_log_newline 2006.145.12:38:09.22/k5log//k5ts2_log_newline 2006.145.12:38:09.96/k5log//k5ts3_log_newline 2006.145.12:38:10.71/k5log//k5ts4_log_newline 2006.145.12:38:10.73/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.12:38:10.73:setupk4=1 2006.145.12:38:10.73$setupk4/echo=on 2006.145.12:38:10.73$setupk4/pcalon 2006.145.12:38:10.73$pcalon/"no phase cal control is implemented here 2006.145.12:38:10.73$setupk4/"tpicd=stop 2006.145.12:38:10.73$setupk4/"rec=synch_on 2006.145.12:38:10.73$setupk4/"rec_mode=128 2006.145.12:38:10.73$setupk4/!* 2006.145.12:38:10.73$setupk4/recpk4 2006.145.12:38:10.73$recpk4/recpatch= 2006.145.12:38:10.73$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.12:38:10.74$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.12:38:10.74$setupk4/vck44 2006.145.12:38:10.74$vck44/valo=1,524.99 2006.145.12:38:10.74#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.12:38:10.74#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.12:38:10.74#ibcon#ireg 17 cls_cnt 0 2006.145.12:38:10.74#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.12:38:10.74#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.12:38:10.74#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.12:38:10.77#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.12:38:10.82#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.12:38:10.82#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.12:38:10.82#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.12:38:10.82#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.12:38:10.82$vck44/va=1,8 2006.145.12:38:10.82#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.12:38:10.82#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.12:38:10.82#ibcon#ireg 11 cls_cnt 2 2006.145.12:38:10.82#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.12:38:10.82#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.12:38:10.82#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.12:38:10.84#ibcon#[25=AT01-08\r\n] 2006.145.12:38:10.87#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.12:38:10.87#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.12:38:10.87#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.12:38:10.87#ibcon#ireg 7 cls_cnt 0 2006.145.12:38:10.87#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.12:38:10.99#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.12:38:10.99#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.12:38:11.01#ibcon#[25=USB\r\n] 2006.145.12:38:11.06#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.12:38:11.06#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.12:38:11.06#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.12:38:11.06#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.12:38:11.06$vck44/valo=2,534.99 2006.145.12:38:11.06#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.12:38:11.06#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.12:38:11.06#ibcon#ireg 17 cls_cnt 0 2006.145.12:38:11.06#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.12:38:11.06#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.12:38:11.06#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.12:38:11.07#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.12:38:11.09#abcon#<5=/05 1.4 2.0 15.68 801020.6\r\n> 2006.145.12:38:11.11#abcon#{5=INTERFACE CLEAR} 2006.145.12:38:11.11#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.12:38:11.11#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.12:38:11.11#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.12:38:11.11#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.12:38:11.11$vck44/va=2,7 2006.145.12:38:11.11#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.12:38:11.11#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.12:38:11.11#ibcon#ireg 11 cls_cnt 2 2006.145.12:38:11.11#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.12:38:11.17#abcon#[5=S1D000X0/0*\r\n] 2006.145.12:38:11.18#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.12:38:11.18#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.12:38:11.20#ibcon#[25=AT02-07\r\n] 2006.145.12:38:11.23#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.12:38:11.23#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.12:38:11.23#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.12:38:11.23#ibcon#ireg 7 cls_cnt 0 2006.145.12:38:11.23#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.12:38:11.35#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.12:38:11.35#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.12:38:11.37#ibcon#[25=USB\r\n] 2006.145.12:38:11.40#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.12:38:11.40#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.12:38:11.40#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.12:38:11.40#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.12:38:11.40$vck44/valo=3,564.99 2006.145.12:38:11.40#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.12:38:11.40#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.12:38:11.40#ibcon#ireg 17 cls_cnt 0 2006.145.12:38:11.40#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.12:38:11.40#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.12:38:11.40#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.12:38:11.42#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.12:38:11.46#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.12:38:11.46#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.12:38:11.46#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.12:38:11.46#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.12:38:11.46$vck44/va=3,8 2006.145.12:38:11.46#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.12:38:11.46#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.12:38:11.46#ibcon#ireg 11 cls_cnt 2 2006.145.12:38:11.46#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.12:38:11.52#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.12:38:11.52#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.12:38:11.54#ibcon#[25=AT03-08\r\n] 2006.145.12:38:11.57#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.12:38:11.57#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.12:38:11.57#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.12:38:11.57#ibcon#ireg 7 cls_cnt 0 2006.145.12:38:11.57#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.12:38:11.69#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.12:38:11.69#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.12:38:11.71#ibcon#[25=USB\r\n] 2006.145.12:38:11.74#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.12:38:11.74#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.12:38:11.74#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.12:38:11.74#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.12:38:11.74$vck44/valo=4,624.99 2006.145.12:38:11.74#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.12:38:11.74#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.12:38:11.74#ibcon#ireg 17 cls_cnt 0 2006.145.12:38:11.74#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.12:38:11.74#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.12:38:11.74#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.12:38:11.76#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.12:38:11.80#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.12:38:11.80#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.12:38:11.80#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.12:38:11.80#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.12:38:11.80$vck44/va=4,7 2006.145.12:38:11.80#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.12:38:11.80#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.12:38:11.80#ibcon#ireg 11 cls_cnt 2 2006.145.12:38:11.80#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.12:38:11.86#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.12:38:11.86#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.12:38:11.88#ibcon#[25=AT04-07\r\n] 2006.145.12:38:11.91#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.12:38:11.91#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.12:38:11.91#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.12:38:11.91#ibcon#ireg 7 cls_cnt 0 2006.145.12:38:11.91#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.12:38:12.03#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.12:38:12.03#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.12:38:12.05#ibcon#[25=USB\r\n] 2006.145.12:38:12.08#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.12:38:12.08#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.12:38:12.08#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.12:38:12.08#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.12:38:12.08$vck44/valo=5,734.99 2006.145.12:38:12.08#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.12:38:12.08#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.12:38:12.08#ibcon#ireg 17 cls_cnt 0 2006.145.12:38:12.08#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.12:38:12.08#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.12:38:12.08#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.12:38:12.10#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.12:38:12.14#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.12:38:12.14#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.12:38:12.14#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.12:38:12.14#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.12:38:12.14$vck44/va=5,4 2006.145.12:38:12.15#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.12:38:12.15#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.12:38:12.15#ibcon#ireg 11 cls_cnt 2 2006.145.12:38:12.15#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.12:38:12.19#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.12:38:12.19#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.12:38:12.22#ibcon#[25=AT05-04\r\n] 2006.145.12:38:12.25#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.12:38:12.25#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.12:38:12.25#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.12:38:12.25#ibcon#ireg 7 cls_cnt 0 2006.145.12:38:12.25#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.12:38:12.36#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.12:38:12.36#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.12:38:12.38#ibcon#[25=USB\r\n] 2006.145.12:38:12.41#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.12:38:12.41#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.12:38:12.41#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.12:38:12.41#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.12:38:12.41$vck44/valo=6,814.99 2006.145.12:38:12.41#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.12:38:12.41#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.12:38:12.41#ibcon#ireg 17 cls_cnt 0 2006.145.12:38:12.41#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.12:38:12.41#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.12:38:12.41#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.12:38:12.43#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.12:38:12.47#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.12:38:12.47#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.12:38:12.47#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.12:38:12.47#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.12:38:12.47$vck44/va=6,4 2006.145.12:38:12.47#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.12:38:12.47#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.12:38:12.47#ibcon#ireg 11 cls_cnt 2 2006.145.12:38:12.47#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.12:38:12.53#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.12:38:12.53#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.12:38:12.55#ibcon#[25=AT06-04\r\n] 2006.145.12:38:12.58#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.12:38:12.58#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.12:38:12.58#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.12:38:12.58#ibcon#ireg 7 cls_cnt 0 2006.145.12:38:12.58#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.12:38:12.70#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.12:38:12.70#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.12:38:12.72#ibcon#[25=USB\r\n] 2006.145.12:38:12.75#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.12:38:12.75#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.12:38:12.75#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.12:38:12.75#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.12:38:12.75$vck44/valo=7,864.99 2006.145.12:38:12.75#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.12:38:12.75#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.12:38:12.75#ibcon#ireg 17 cls_cnt 0 2006.145.12:38:12.75#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.12:38:12.75#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.12:38:12.75#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.12:38:12.77#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.12:38:12.81#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.12:38:12.81#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.12:38:12.81#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.12:38:12.81#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.12:38:12.81$vck44/va=7,4 2006.145.12:38:12.81#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.12:38:12.81#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.12:38:12.81#ibcon#ireg 11 cls_cnt 2 2006.145.12:38:12.81#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.12:38:12.87#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.12:38:12.87#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.12:38:12.89#ibcon#[25=AT07-04\r\n] 2006.145.12:38:12.92#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.12:38:12.92#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.12:38:12.92#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.12:38:12.92#ibcon#ireg 7 cls_cnt 0 2006.145.12:38:12.92#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.12:38:13.04#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.12:38:13.04#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.12:38:13.06#ibcon#[25=USB\r\n] 2006.145.12:38:13.09#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.12:38:13.09#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.12:38:13.09#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.12:38:13.09#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.12:38:13.09$vck44/valo=8,884.99 2006.145.12:38:13.09#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.12:38:13.09#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.12:38:13.09#ibcon#ireg 17 cls_cnt 0 2006.145.12:38:13.09#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.12:38:13.09#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.12:38:13.09#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.12:38:13.11#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.12:38:13.15#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.12:38:13.15#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.12:38:13.15#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.12:38:13.15#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.12:38:13.15$vck44/va=8,4 2006.145.12:38:13.15#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.12:38:13.15#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.12:38:13.15#ibcon#ireg 11 cls_cnt 2 2006.145.12:38:13.15#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.12:38:13.21#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.12:38:13.21#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.12:38:13.23#ibcon#[25=AT08-04\r\n] 2006.145.12:38:13.26#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.12:38:13.26#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.12:38:13.26#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.12:38:13.26#ibcon#ireg 7 cls_cnt 0 2006.145.12:38:13.26#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.12:38:13.40#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.12:38:13.40#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.12:38:13.42#ibcon#[25=USB\r\n] 2006.145.12:38:13.45#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.12:38:13.45#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.12:38:13.45#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.12:38:13.45#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.12:38:13.45$vck44/vblo=1,629.99 2006.145.12:38:13.45#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.12:38:13.45#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.12:38:13.45#ibcon#ireg 17 cls_cnt 0 2006.145.12:38:13.45#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.12:38:13.45#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.12:38:13.45#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.12:38:13.47#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.12:38:13.52#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.12:38:13.52#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.12:38:13.52#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.12:38:13.52#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.12:38:13.52$vck44/vb=1,3 2006.145.12:38:13.52#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.12:38:13.52#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.12:38:13.52#ibcon#ireg 11 cls_cnt 2 2006.145.12:38:13.52#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.12:38:13.52#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.12:38:13.52#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.12:38:13.53#ibcon#[27=AT01-03\r\n] 2006.145.12:38:13.56#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.12:38:13.56#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.12:38:13.56#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.12:38:13.56#ibcon#ireg 7 cls_cnt 0 2006.145.12:38:13.56#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.12:38:13.68#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.12:38:13.68#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.12:38:13.70#ibcon#[27=USB\r\n] 2006.145.12:38:13.73#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.12:38:13.73#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.12:38:13.73#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.12:38:13.73#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.12:38:13.73$vck44/vblo=2,634.99 2006.145.12:38:13.73#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.12:38:13.73#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.12:38:13.73#ibcon#ireg 17 cls_cnt 0 2006.145.12:38:13.73#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.12:38:13.73#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.12:38:13.73#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.12:38:13.75#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.12:38:13.79#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.12:38:13.79#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.12:38:13.79#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.12:38:13.79#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.12:38:13.79$vck44/vb=2,4 2006.145.12:38:13.79#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.12:38:13.79#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.12:38:13.79#ibcon#ireg 11 cls_cnt 2 2006.145.12:38:13.79#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.12:38:13.85#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.12:38:13.85#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.12:38:13.87#ibcon#[27=AT02-04\r\n] 2006.145.12:38:13.90#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.12:38:13.90#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.12:38:13.90#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.12:38:13.90#ibcon#ireg 7 cls_cnt 0 2006.145.12:38:13.90#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.12:38:14.02#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.12:38:14.02#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.12:38:14.04#ibcon#[27=USB\r\n] 2006.145.12:38:14.07#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.12:38:14.07#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.12:38:14.07#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.12:38:14.07#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.12:38:14.07$vck44/vblo=3,649.99 2006.145.12:38:14.07#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.12:38:14.07#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.12:38:14.07#ibcon#ireg 17 cls_cnt 0 2006.145.12:38:14.07#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.12:38:14.07#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.12:38:14.07#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.12:38:14.09#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.12:38:14.13#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.12:38:14.13#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.12:38:14.13#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.12:38:14.13#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.12:38:14.13$vck44/vb=3,4 2006.145.12:38:14.13#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.12:38:14.13#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.12:38:14.13#ibcon#ireg 11 cls_cnt 2 2006.145.12:38:14.13#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.12:38:14.19#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.12:38:14.19#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.12:38:14.21#ibcon#[27=AT03-04\r\n] 2006.145.12:38:14.24#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.12:38:14.24#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.12:38:14.24#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.12:38:14.24#ibcon#ireg 7 cls_cnt 0 2006.145.12:38:14.24#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.12:38:14.36#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.12:38:14.36#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.12:38:14.38#ibcon#[27=USB\r\n] 2006.145.12:38:14.41#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.12:38:14.41#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.12:38:14.41#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.12:38:14.41#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.12:38:14.41$vck44/vblo=4,679.99 2006.145.12:38:14.41#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.12:38:14.41#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.12:38:14.41#ibcon#ireg 17 cls_cnt 0 2006.145.12:38:14.41#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.12:38:14.41#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.12:38:14.41#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.12:38:14.43#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.12:38:14.47#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.12:38:14.47#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.12:38:14.47#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.12:38:14.47#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.12:38:14.47$vck44/vb=4,4 2006.145.12:38:14.47#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.12:38:14.47#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.12:38:14.47#ibcon#ireg 11 cls_cnt 2 2006.145.12:38:14.47#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.12:38:14.53#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.12:38:14.53#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.12:38:14.55#ibcon#[27=AT04-04\r\n] 2006.145.12:38:14.58#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.12:38:14.58#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.12:38:14.58#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.12:38:14.58#ibcon#ireg 7 cls_cnt 0 2006.145.12:38:14.58#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.12:38:14.70#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.12:38:14.70#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.12:38:14.72#ibcon#[27=USB\r\n] 2006.145.12:38:14.75#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.12:38:14.75#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.12:38:14.75#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.12:38:14.75#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.12:38:14.75$vck44/vblo=5,709.99 2006.145.12:38:14.75#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.12:38:14.75#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.12:38:14.75#ibcon#ireg 17 cls_cnt 0 2006.145.12:38:14.75#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.12:38:14.75#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.12:38:14.75#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.12:38:14.77#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.12:38:14.81#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.12:38:14.81#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.12:38:14.81#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.12:38:14.81#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.12:38:14.81$vck44/vb=5,4 2006.145.12:38:14.81#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.12:38:14.81#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.12:38:14.81#ibcon#ireg 11 cls_cnt 2 2006.145.12:38:14.81#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.12:38:14.87#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.12:38:14.87#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.12:38:14.89#ibcon#[27=AT05-04\r\n] 2006.145.12:38:14.92#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.12:38:14.92#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.12:38:14.92#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.12:38:14.92#ibcon#ireg 7 cls_cnt 0 2006.145.12:38:14.92#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.12:38:15.04#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.12:38:15.04#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.12:38:15.06#ibcon#[27=USB\r\n] 2006.145.12:38:15.09#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.12:38:15.09#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.12:38:15.09#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.12:38:15.09#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.12:38:15.09$vck44/vblo=6,719.99 2006.145.12:38:15.09#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.12:38:15.09#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.12:38:15.09#ibcon#ireg 17 cls_cnt 0 2006.145.12:38:15.09#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.12:38:15.09#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.12:38:15.09#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.12:38:15.11#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.12:38:15.15#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.12:38:15.15#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.12:38:15.15#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.12:38:15.15#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.12:38:15.15$vck44/vb=6,4 2006.145.12:38:15.15#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.12:38:15.15#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.12:38:15.15#ibcon#ireg 11 cls_cnt 2 2006.145.12:38:15.15#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.12:38:15.21#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.12:38:15.21#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.12:38:15.23#ibcon#[27=AT06-04\r\n] 2006.145.12:38:15.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.12:38:15.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.12:38:15.26#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.12:38:15.26#ibcon#ireg 7 cls_cnt 0 2006.145.12:38:15.26#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.12:38:15.38#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.12:38:15.38#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.12:38:15.40#ibcon#[27=USB\r\n] 2006.145.12:38:15.43#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.12:38:15.43#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.12:38:15.43#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.12:38:15.43#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.12:38:15.43$vck44/vblo=7,734.99 2006.145.12:38:15.43#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.12:38:15.43#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.12:38:15.43#ibcon#ireg 17 cls_cnt 0 2006.145.12:38:15.43#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.12:38:15.43#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.12:38:15.43#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.12:38:15.45#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.12:38:15.49#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.12:38:15.49#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.12:38:15.49#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.12:38:15.49#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.12:38:15.49$vck44/vb=7,4 2006.145.12:38:15.49#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.12:38:15.49#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.12:38:15.49#ibcon#ireg 11 cls_cnt 2 2006.145.12:38:15.49#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.12:38:15.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.12:38:15.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.12:38:15.57#ibcon#[27=AT07-04\r\n] 2006.145.12:38:15.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.12:38:15.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.12:38:15.60#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.12:38:15.60#ibcon#ireg 7 cls_cnt 0 2006.145.12:38:15.60#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.12:38:15.72#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.12:38:15.72#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.12:38:15.74#ibcon#[27=USB\r\n] 2006.145.12:38:15.77#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.12:38:15.77#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.12:38:15.77#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.12:38:15.77#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.12:38:15.77$vck44/vblo=8,744.99 2006.145.12:38:15.77#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.12:38:15.77#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.12:38:15.77#ibcon#ireg 17 cls_cnt 0 2006.145.12:38:15.77#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.12:38:15.77#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.12:38:15.77#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.12:38:15.79#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.12:38:15.83#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.12:38:15.83#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.12:38:15.83#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.12:38:15.83#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.12:38:15.83$vck44/vb=8,4 2006.145.12:38:15.83#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.12:38:15.83#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.12:38:15.83#ibcon#ireg 11 cls_cnt 2 2006.145.12:38:15.83#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.12:38:15.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.12:38:15.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.12:38:15.91#ibcon#[27=AT08-04\r\n] 2006.145.12:38:15.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.12:38:15.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.12:38:15.94#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.12:38:15.94#ibcon#ireg 7 cls_cnt 0 2006.145.12:38:15.94#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.12:38:16.06#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.12:38:16.06#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.12:38:16.08#ibcon#[27=USB\r\n] 2006.145.12:38:16.11#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.12:38:16.11#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.12:38:16.11#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.12:38:16.11#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.12:38:16.11$vck44/vabw=wide 2006.145.12:38:16.11#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.12:38:16.11#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.12:38:16.11#ibcon#ireg 8 cls_cnt 0 2006.145.12:38:16.11#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.12:38:16.11#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.12:38:16.11#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.12:38:16.13#ibcon#[25=BW32\r\n] 2006.145.12:38:16.16#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.12:38:16.16#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.12:38:16.16#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.12:38:16.16#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.12:38:16.16$vck44/vbbw=wide 2006.145.12:38:16.16#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.12:38:16.16#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.12:38:16.16#ibcon#ireg 8 cls_cnt 0 2006.145.12:38:16.16#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:38:16.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:38:16.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:38:16.25#ibcon#[27=BW32\r\n] 2006.145.12:38:16.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:38:16.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:38:16.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.12:38:16.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.12:38:16.28$setupk4/ifdk4 2006.145.12:38:16.28$ifdk4/lo= 2006.145.12:38:16.28$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.12:38:16.28$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.12:38:16.28$ifdk4/patch= 2006.145.12:38:16.29$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.12:38:16.29$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.12:38:16.29$setupk4/!*+20s 2006.145.12:38:21.26#abcon#<5=/05 1.4 2.0 15.68 801020.6\r\n> 2006.145.12:38:21.28#abcon#{5=INTERFACE CLEAR} 2006.145.12:38:21.34#abcon#[5=S1D000X0/0*\r\n] 2006.145.12:38:30.75$setupk4/"tpicd 2006.145.12:38:30.75$setupk4/echo=off 2006.145.12:38:30.75$setupk4/xlog=off 2006.145.12:38:30.75:!2006.145.12:42:40 2006.145.12:38:46.14#trakl#Source acquired 2006.145.12:38:47.14#flagr#flagr/antenna,acquired 2006.145.12:42:40.00:preob 2006.145.12:42:40.13/onsource/TRACKING 2006.145.12:42:40.13:!2006.145.12:42:50 2006.145.12:42:50.00:"tape 2006.145.12:42:50.00:"st=record 2006.145.12:42:50.00:data_valid=on 2006.145.12:42:50.00:midob 2006.145.12:42:50.13/onsource/TRACKING 2006.145.12:42:50.13/wx/15.63,1020.6,81 2006.145.12:42:50.29/cable/+6.5464E-03 2006.145.12:42:51.38/va/01,08,usb,yes,28,30 2006.145.12:42:51.38/va/02,07,usb,yes,30,31 2006.145.12:42:51.38/va/03,08,usb,yes,27,28 2006.145.12:42:51.38/va/04,07,usb,yes,31,33 2006.145.12:42:51.38/va/05,04,usb,yes,27,28 2006.145.12:42:51.38/va/06,04,usb,yes,30,30 2006.145.12:42:51.38/va/07,04,usb,yes,31,32 2006.145.12:42:51.38/va/08,04,usb,yes,26,31 2006.145.12:42:51.61/valo/01,524.99,yes,locked 2006.145.12:42:51.61/valo/02,534.99,yes,locked 2006.145.12:42:51.61/valo/03,564.99,yes,locked 2006.145.12:42:51.61/valo/04,624.99,yes,locked 2006.145.12:42:51.61/valo/05,734.99,yes,locked 2006.145.12:42:51.61/valo/06,814.99,yes,locked 2006.145.12:42:51.61/valo/07,864.99,yes,locked 2006.145.12:42:51.61/valo/08,884.99,yes,locked 2006.145.12:42:52.70/vb/01,03,usb,yes,35,33 2006.145.12:42:52.70/vb/02,04,usb,yes,31,31 2006.145.12:42:52.70/vb/03,04,usb,yes,28,31 2006.145.12:42:52.70/vb/04,04,usb,yes,32,31 2006.145.12:42:52.70/vb/05,04,usb,yes,25,27 2006.145.12:42:52.70/vb/06,04,usb,yes,29,26 2006.145.12:42:52.70/vb/07,04,usb,yes,29,29 2006.145.12:42:52.70/vb/08,04,usb,yes,27,30 2006.145.12:42:52.94/vblo/01,629.99,yes,locked 2006.145.12:42:52.94/vblo/02,634.99,yes,locked 2006.145.12:42:52.94/vblo/03,649.99,yes,locked 2006.145.12:42:52.94/vblo/04,679.99,yes,locked 2006.145.12:42:52.94/vblo/05,709.99,yes,locked 2006.145.12:42:52.94/vblo/06,719.99,yes,locked 2006.145.12:42:52.94/vblo/07,734.99,yes,locked 2006.145.12:42:52.94/vblo/08,744.99,yes,locked 2006.145.12:42:53.09/vabw/8 2006.145.12:42:53.24/vbbw/8 2006.145.12:42:53.33/xfe/off,on,15.0 2006.145.12:42:53.72/ifatt/23,28,28,28 2006.145.12:42:54.07/fmout-gps/S +5.8E-08 2006.145.12:42:54.11:!2006.145.12:43:30 2006.145.12:43:30.01:data_valid=off 2006.145.12:43:30.02:"et 2006.145.12:43:30.02:!+3s 2006.145.12:43:33.03:"tape 2006.145.12:43:33.04:postob 2006.145.12:43:33.25/cable/+6.5490E-03 2006.145.12:43:33.26/wx/15.63,1020.5,81 2006.145.12:43:33.34/fmout-gps/S +5.8E-08 2006.145.12:43:33.35:scan_name=145-1244,jd0605,784 2006.145.12:43:33.35:source=1749+096,175132.82,093900.7,2000.0,cw 2006.145.12:43:35.13#flagr#flagr/antenna,new-source 2006.145.12:43:35.14:checkk5 2006.145.12:43:35.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.12:43:36.00/chk_autoobs//k5ts2/ autoobs is running! 2006.145.12:43:36.44/chk_autoobs//k5ts3/ autoobs is running! 2006.145.12:43:36.87/chk_autoobs//k5ts4/ autoobs is running! 2006.145.12:43:37.32/chk_obsdata//k5ts1/T1451242??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.12:43:37.75/chk_obsdata//k5ts2/T1451242??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.12:43:38.19/chk_obsdata//k5ts3/T1451242??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.12:43:38.63/chk_obsdata//k5ts4/T1451242??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.12:43:39.44/k5log//k5ts1_log_newline 2006.145.12:43:40.20/k5log//k5ts2_log_newline 2006.145.12:43:40.95/k5log//k5ts3_log_newline 2006.145.12:43:41.68/k5log//k5ts4_log_newline 2006.145.12:43:41.70/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.12:43:41.70:setupk4=1 2006.145.12:43:41.70$setupk4/echo=on 2006.145.12:43:41.70$setupk4/pcalon 2006.145.12:43:41.70$pcalon/"no phase cal control is implemented here 2006.145.12:43:41.70$setupk4/"tpicd=stop 2006.145.12:43:41.70$setupk4/"rec=synch_on 2006.145.12:43:41.70$setupk4/"rec_mode=128 2006.145.12:43:41.70$setupk4/!* 2006.145.12:43:41.70$setupk4/recpk4 2006.145.12:43:41.70$recpk4/recpatch= 2006.145.12:43:41.71$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.12:43:41.71$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.12:43:41.71$setupk4/vck44 2006.145.12:43:41.71$vck44/valo=1,524.99 2006.145.12:43:41.71#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.12:43:41.71#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.12:43:41.71#ibcon#ireg 17 cls_cnt 0 2006.145.12:43:41.71#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.12:43:41.71#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.12:43:41.71#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.12:43:41.74#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.12:43:41.79#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.12:43:41.79#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.12:43:41.79#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.12:43:41.79#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.12:43:41.79$vck44/va=1,8 2006.145.12:43:41.79#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.12:43:41.79#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.12:43:41.79#ibcon#ireg 11 cls_cnt 2 2006.145.12:43:41.79#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.12:43:41.79#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.12:43:41.79#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.12:43:41.81#ibcon#[25=AT01-08\r\n] 2006.145.12:43:41.84#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.12:43:41.84#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.12:43:41.84#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.12:43:41.84#ibcon#ireg 7 cls_cnt 0 2006.145.12:43:41.84#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.12:43:41.96#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.12:43:41.96#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.12:43:41.98#ibcon#[25=USB\r\n] 2006.145.12:43:42.03#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.12:43:42.03#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.12:43:42.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.12:43:42.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.12:43:42.03$vck44/valo=2,534.99 2006.145.12:43:42.03#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.12:43:42.03#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.12:43:42.03#ibcon#ireg 17 cls_cnt 0 2006.145.12:43:42.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.12:43:42.03#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.12:43:42.03#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.12:43:42.04#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.12:43:42.08#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.12:43:42.08#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.12:43:42.08#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.12:43:42.08#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.12:43:42.08$vck44/va=2,7 2006.145.12:43:42.08#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.12:43:42.08#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.12:43:42.08#ibcon#ireg 11 cls_cnt 2 2006.145.12:43:42.08#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.12:43:42.15#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.12:43:42.15#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.12:43:42.17#ibcon#[25=AT02-07\r\n] 2006.145.12:43:42.20#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.12:43:42.20#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.12:43:42.20#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.12:43:42.20#ibcon#ireg 7 cls_cnt 0 2006.145.12:43:42.20#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.12:43:42.32#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.12:43:42.32#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.12:43:42.34#ibcon#[25=USB\r\n] 2006.145.12:43:42.37#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.12:43:42.37#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.12:43:42.37#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.12:43:42.37#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.12:43:42.37$vck44/valo=3,564.99 2006.145.12:43:42.37#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.12:43:42.37#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.12:43:42.37#ibcon#ireg 17 cls_cnt 0 2006.145.12:43:42.37#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.12:43:42.37#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.12:43:42.37#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.12:43:42.39#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.12:43:42.43#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.12:43:42.43#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.12:43:42.43#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.12:43:42.43#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.12:43:42.43$vck44/va=3,8 2006.145.12:43:42.43#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.12:43:42.43#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.12:43:42.43#ibcon#ireg 11 cls_cnt 2 2006.145.12:43:42.43#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.12:43:42.49#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.12:43:42.49#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.12:43:42.51#ibcon#[25=AT03-08\r\n] 2006.145.12:43:42.54#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.12:43:42.54#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.12:43:42.54#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.12:43:42.54#ibcon#ireg 7 cls_cnt 0 2006.145.12:43:42.54#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.12:43:42.66#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.12:43:42.66#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.12:43:42.68#ibcon#[25=USB\r\n] 2006.145.12:43:42.71#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.12:43:42.71#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.12:43:42.71#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.12:43:42.71#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.12:43:42.71$vck44/valo=4,624.99 2006.145.12:43:42.71#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.12:43:42.71#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.12:43:42.71#ibcon#ireg 17 cls_cnt 0 2006.145.12:43:42.71#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.12:43:42.71#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.12:43:42.71#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.12:43:42.73#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.12:43:42.77#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.12:43:42.77#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.12:43:42.77#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.12:43:42.77#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.12:43:42.77$vck44/va=4,7 2006.145.12:43:42.77#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.12:43:42.77#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.12:43:42.77#ibcon#ireg 11 cls_cnt 2 2006.145.12:43:42.77#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.12:43:42.83#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.12:43:42.83#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.12:43:42.85#ibcon#[25=AT04-07\r\n] 2006.145.12:43:42.88#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.12:43:42.88#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.12:43:42.88#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.12:43:42.88#ibcon#ireg 7 cls_cnt 0 2006.145.12:43:42.88#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.12:43:43.00#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.12:43:43.00#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.12:43:43.02#ibcon#[25=USB\r\n] 2006.145.12:43:43.05#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.12:43:43.05#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.12:43:43.05#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.12:43:43.05#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.12:43:43.05$vck44/valo=5,734.99 2006.145.12:43:43.05#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.12:43:43.05#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.12:43:43.05#ibcon#ireg 17 cls_cnt 0 2006.145.12:43:43.05#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.12:43:43.05#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.12:43:43.05#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.12:43:43.07#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.12:43:43.11#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.12:43:43.11#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.12:43:43.11#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.12:43:43.11#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.12:43:43.11$vck44/va=5,4 2006.145.12:43:43.11#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.12:43:43.11#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.12:43:43.11#ibcon#ireg 11 cls_cnt 2 2006.145.12:43:43.11#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.12:43:43.17#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.12:43:43.17#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.12:43:43.19#ibcon#[25=AT05-04\r\n] 2006.145.12:43:43.22#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.12:43:43.22#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.12:43:43.22#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.12:43:43.22#ibcon#ireg 7 cls_cnt 0 2006.145.12:43:43.22#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.12:43:43.34#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.12:43:43.34#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.12:43:43.36#ibcon#[25=USB\r\n] 2006.145.12:43:43.39#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.12:43:43.39#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.12:43:43.39#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.12:43:43.39#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.12:43:43.39$vck44/valo=6,814.99 2006.145.12:43:43.39#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.12:43:43.39#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.12:43:43.39#ibcon#ireg 17 cls_cnt 0 2006.145.12:43:43.39#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.12:43:43.39#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.12:43:43.39#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.12:43:43.42#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.12:43:43.46#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.12:43:43.46#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.12:43:43.46#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.12:43:43.46#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.12:43:43.46$vck44/va=6,4 2006.145.12:43:43.46#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.12:43:43.46#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.12:43:43.46#ibcon#ireg 11 cls_cnt 2 2006.145.12:43:43.46#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.12:43:43.51#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.12:43:43.51#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.12:43:43.53#ibcon#[25=AT06-04\r\n] 2006.145.12:43:43.56#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.12:43:43.56#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.12:43:43.56#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.12:43:43.56#ibcon#ireg 7 cls_cnt 0 2006.145.12:43:43.56#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.12:43:43.68#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.12:43:43.68#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.12:43:43.70#ibcon#[25=USB\r\n] 2006.145.12:43:43.73#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.12:43:43.73#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.12:43:43.73#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.12:43:43.73#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.12:43:43.73$vck44/valo=7,864.99 2006.145.12:43:43.73#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.12:43:43.73#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.12:43:43.73#ibcon#ireg 17 cls_cnt 0 2006.145.12:43:43.73#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.12:43:43.73#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.12:43:43.73#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.12:43:43.75#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.12:43:43.79#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.12:43:43.79#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.12:43:43.79#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.12:43:43.79#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.12:43:43.79$vck44/va=7,4 2006.145.12:43:43.79#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.12:43:43.79#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.12:43:43.79#ibcon#ireg 11 cls_cnt 2 2006.145.12:43:43.79#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.12:43:43.85#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.12:43:43.85#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.12:43:43.87#ibcon#[25=AT07-04\r\n] 2006.145.12:43:43.90#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.12:43:43.90#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.12:43:43.90#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.12:43:43.90#ibcon#ireg 7 cls_cnt 0 2006.145.12:43:43.90#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.12:43:44.02#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.12:43:44.02#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.12:43:44.04#ibcon#[25=USB\r\n] 2006.145.12:43:44.07#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.12:43:44.07#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.12:43:44.07#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.12:43:44.07#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.12:43:44.07$vck44/valo=8,884.99 2006.145.12:43:44.07#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.12:43:44.07#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.12:43:44.07#ibcon#ireg 17 cls_cnt 0 2006.145.12:43:44.07#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.12:43:44.07#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.12:43:44.07#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.12:43:44.09#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.12:43:44.13#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.12:43:44.13#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.12:43:44.13#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.12:43:44.13#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.12:43:44.13$vck44/va=8,4 2006.145.12:43:44.13#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.12:43:44.13#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.12:43:44.13#ibcon#ireg 11 cls_cnt 2 2006.145.12:43:44.13#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.12:43:44.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.12:43:44.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.12:43:44.21#ibcon#[25=AT08-04\r\n] 2006.145.12:43:44.24#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.12:43:44.24#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.12:43:44.24#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.12:43:44.24#ibcon#ireg 7 cls_cnt 0 2006.145.12:43:44.24#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.12:43:44.36#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.12:43:44.36#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.12:43:44.38#ibcon#[25=USB\r\n] 2006.145.12:43:44.41#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.12:43:44.41#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.12:43:44.41#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.12:43:44.41#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.12:43:44.41$vck44/vblo=1,629.99 2006.145.12:43:44.41#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.12:43:44.41#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.12:43:44.41#ibcon#ireg 17 cls_cnt 0 2006.145.12:43:44.41#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.12:43:44.41#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.12:43:44.41#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.12:43:44.43#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.12:43:44.47#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.12:43:44.47#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.12:43:44.47#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.12:43:44.47#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.12:43:44.47$vck44/vb=1,3 2006.145.12:43:44.47#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.12:43:44.47#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.12:43:44.47#ibcon#ireg 11 cls_cnt 2 2006.145.12:43:44.47#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.12:43:44.47#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.12:43:44.47#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.12:43:44.51#ibcon#[27=AT01-03\r\n] 2006.145.12:43:44.54#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.12:43:44.54#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.12:43:44.54#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.12:43:44.54#ibcon#ireg 7 cls_cnt 0 2006.145.12:43:44.54#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.12:43:44.66#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.12:43:44.66#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.12:43:44.68#ibcon#[27=USB\r\n] 2006.145.12:43:44.71#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.12:43:44.71#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.12:43:44.71#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.12:43:44.71#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.12:43:44.71$vck44/vblo=2,634.99 2006.145.12:43:44.71#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.12:43:44.71#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.12:43:44.71#ibcon#ireg 17 cls_cnt 0 2006.145.12:43:44.71#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.12:43:44.71#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.12:43:44.71#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.12:43:44.73#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.12:43:44.77#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.12:43:44.77#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.12:43:44.77#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.12:43:44.77#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.12:43:44.77$vck44/vb=2,4 2006.145.12:43:44.77#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.12:43:44.77#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.12:43:44.77#ibcon#ireg 11 cls_cnt 2 2006.145.12:43:44.77#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.12:43:44.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.12:43:44.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.12:43:44.85#ibcon#[27=AT02-04\r\n] 2006.145.12:43:44.88#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.12:43:44.88#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.12:43:44.88#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.12:43:44.88#ibcon#ireg 7 cls_cnt 0 2006.145.12:43:44.88#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.12:43:45.00#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.12:43:45.00#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.12:43:45.02#ibcon#[27=USB\r\n] 2006.145.12:43:45.05#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.12:43:45.05#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.12:43:45.05#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.12:43:45.05#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.12:43:45.05$vck44/vblo=3,649.99 2006.145.12:43:45.05#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.12:43:45.05#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.12:43:45.05#ibcon#ireg 17 cls_cnt 0 2006.145.12:43:45.05#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.12:43:45.05#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.12:43:45.05#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.12:43:45.07#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.12:43:45.11#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.12:43:45.11#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.12:43:45.11#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.12:43:45.11#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.12:43:45.11$vck44/vb=3,4 2006.145.12:43:45.11#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.12:43:45.11#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.12:43:45.11#ibcon#ireg 11 cls_cnt 2 2006.145.12:43:45.11#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.12:43:45.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.12:43:45.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.12:43:45.19#ibcon#[27=AT03-04\r\n] 2006.145.12:43:45.22#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.12:43:45.22#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.12:43:45.22#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.12:43:45.22#ibcon#ireg 7 cls_cnt 0 2006.145.12:43:45.22#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.12:43:45.34#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.12:43:45.34#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.12:43:45.36#ibcon#[27=USB\r\n] 2006.145.12:43:45.39#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.12:43:45.39#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.12:43:45.39#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.12:43:45.39#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.12:43:45.39$vck44/vblo=4,679.99 2006.145.12:43:45.39#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.12:43:45.39#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.12:43:45.39#ibcon#ireg 17 cls_cnt 0 2006.145.12:43:45.39#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.12:43:45.39#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.12:43:45.39#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.12:43:45.41#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.12:43:45.45#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.12:43:45.45#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.12:43:45.45#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.12:43:45.45#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.12:43:45.45$vck44/vb=4,4 2006.145.12:43:45.45#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.12:43:45.45#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.12:43:45.45#ibcon#ireg 11 cls_cnt 2 2006.145.12:43:45.45#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.12:43:45.51#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.12:43:45.51#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.12:43:45.53#ibcon#[27=AT04-04\r\n] 2006.145.12:43:45.56#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.12:43:45.56#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.12:43:45.56#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.12:43:45.56#ibcon#ireg 7 cls_cnt 0 2006.145.12:43:45.56#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.12:43:45.68#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.12:43:45.68#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.12:43:45.70#ibcon#[27=USB\r\n] 2006.145.12:43:45.73#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.12:43:45.73#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.12:43:45.73#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.12:43:45.73#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.12:43:45.73$vck44/vblo=5,709.99 2006.145.12:43:45.73#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.12:43:45.73#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.12:43:45.73#ibcon#ireg 17 cls_cnt 0 2006.145.12:43:45.73#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.12:43:45.73#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.12:43:45.73#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.12:43:45.75#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.12:43:45.79#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.12:43:45.79#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.12:43:45.79#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.12:43:45.79#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.12:43:45.79$vck44/vb=5,4 2006.145.12:43:45.79#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.12:43:45.79#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.12:43:45.79#ibcon#ireg 11 cls_cnt 2 2006.145.12:43:45.79#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.12:43:45.85#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.12:43:45.85#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.12:43:45.87#ibcon#[27=AT05-04\r\n] 2006.145.12:43:45.90#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.12:43:45.90#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.12:43:45.90#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.12:43:45.90#ibcon#ireg 7 cls_cnt 0 2006.145.12:43:45.90#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.12:43:46.02#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.12:43:46.02#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.12:43:46.04#ibcon#[27=USB\r\n] 2006.145.12:43:46.07#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.12:43:46.07#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.12:43:46.07#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.12:43:46.07#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.12:43:46.07$vck44/vblo=6,719.99 2006.145.12:43:46.07#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.12:43:46.07#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.12:43:46.07#ibcon#ireg 17 cls_cnt 0 2006.145.12:43:46.07#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.12:43:46.07#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.12:43:46.07#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.12:43:46.09#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.12:43:46.13#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.12:43:46.13#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.12:43:46.13#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.12:43:46.13#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.12:43:46.13$vck44/vb=6,4 2006.145.12:43:46.13#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.12:43:46.13#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.12:43:46.13#ibcon#ireg 11 cls_cnt 2 2006.145.12:43:46.13#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.12:43:46.19#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.12:43:46.19#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.12:43:46.21#ibcon#[27=AT06-04\r\n] 2006.145.12:43:46.24#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.12:43:46.24#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.12:43:46.24#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.12:43:46.24#ibcon#ireg 7 cls_cnt 0 2006.145.12:43:46.24#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.12:43:46.36#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.12:43:46.36#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.12:43:46.38#ibcon#[27=USB\r\n] 2006.145.12:43:46.41#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.12:43:46.41#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.12:43:46.41#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.12:43:46.41#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.12:43:46.41$vck44/vblo=7,734.99 2006.145.12:43:46.41#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.12:43:46.41#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.12:43:46.41#ibcon#ireg 17 cls_cnt 0 2006.145.12:43:46.41#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.12:43:46.41#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.12:43:46.41#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.12:43:46.43#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.12:43:46.47#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.12:43:46.47#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.12:43:46.47#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.12:43:46.47#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.12:43:46.47$vck44/vb=7,4 2006.145.12:43:46.47#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.12:43:46.47#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.12:43:46.47#ibcon#ireg 11 cls_cnt 2 2006.145.12:43:46.47#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.12:43:46.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.12:43:46.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.12:43:46.55#ibcon#[27=AT07-04\r\n] 2006.145.12:43:46.58#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.12:43:46.58#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.12:43:46.58#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.12:43:46.58#ibcon#ireg 7 cls_cnt 0 2006.145.12:43:46.58#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.12:43:46.70#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.12:43:46.70#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.12:43:46.72#ibcon#[27=USB\r\n] 2006.145.12:43:46.72#abcon#<5=/05 1.4 2.0 15.62 811020.6\r\n> 2006.145.12:43:46.74#abcon#{5=INTERFACE CLEAR} 2006.145.12:43:46.75#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.12:43:46.75#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.12:43:46.75#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.12:43:46.75#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.12:43:46.75$vck44/vblo=8,744.99 2006.145.12:43:46.75#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.12:43:46.75#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.12:43:46.75#ibcon#ireg 17 cls_cnt 0 2006.145.12:43:46.75#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.12:43:46.75#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.12:43:46.75#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.12:43:46.77#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.12:43:46.80#abcon#[5=S1D000X0/0*\r\n] 2006.145.12:43:46.81#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.12:43:46.81#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.12:43:46.81#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.12:43:46.81#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.12:43:46.81$vck44/vb=8,4 2006.145.12:43:46.81#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.12:43:46.81#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.12:43:46.81#ibcon#ireg 11 cls_cnt 2 2006.145.12:43:46.81#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.12:43:46.87#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.12:43:46.87#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.12:43:46.89#ibcon#[27=AT08-04\r\n] 2006.145.12:43:46.92#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.12:43:46.92#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.12:43:46.92#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.12:43:46.92#ibcon#ireg 7 cls_cnt 0 2006.145.12:43:46.92#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.12:43:47.04#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.12:43:47.04#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.12:43:47.06#ibcon#[27=USB\r\n] 2006.145.12:43:47.09#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.12:43:47.09#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.12:43:47.09#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.12:43:47.09#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.12:43:47.09$vck44/vabw=wide 2006.145.12:43:47.09#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.12:43:47.09#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.12:43:47.09#ibcon#ireg 8 cls_cnt 0 2006.145.12:43:47.09#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.12:43:47.09#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.12:43:47.09#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.12:43:47.11#ibcon#[25=BW32\r\n] 2006.145.12:43:47.14#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.12:43:47.14#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.12:43:47.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.12:43:47.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.12:43:47.14$vck44/vbbw=wide 2006.145.12:43:47.14#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.12:43:47.14#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.12:43:47.14#ibcon#ireg 8 cls_cnt 0 2006.145.12:43:47.14#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.12:43:47.21#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.12:43:47.21#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.12:43:47.23#ibcon#[27=BW32\r\n] 2006.145.12:43:47.26#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.12:43:47.26#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.12:43:47.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.12:43:47.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.12:43:47.26$setupk4/ifdk4 2006.145.12:43:47.26$ifdk4/lo= 2006.145.12:43:47.26$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.12:43:47.26$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.12:43:47.26$ifdk4/patch= 2006.145.12:43:47.26$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.12:43:47.26$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.12:43:47.26$setupk4/!*+20s 2006.145.12:43:56.89#abcon#<5=/05 1.4 2.1 15.62 811020.6\r\n> 2006.145.12:43:56.91#abcon#{5=INTERFACE CLEAR} 2006.145.12:43:56.97#abcon#[5=S1D000X0/0*\r\n] 2006.145.12:43:57.13#trakl#Source acquired 2006.145.12:43:57.13#flagr#flagr/antenna,acquired 2006.145.12:44:01.71$setupk4/"tpicd 2006.145.12:44:01.71$setupk4/echo=off 2006.145.12:44:01.71$setupk4/xlog=off 2006.145.12:44:01.71:!2006.145.12:44:26 2006.145.12:44:26.00:preob 2006.145.12:44:26.14/onsource/TRACKING 2006.145.12:44:26.14:!2006.145.12:44:36 2006.145.12:44:36.00:"tape 2006.145.12:44:36.00:"st=record 2006.145.12:44:36.00:data_valid=on 2006.145.12:44:36.00:midob 2006.145.12:44:36.14/onsource/TRACKING 2006.145.12:44:36.14/wx/15.62,1020.5,81 2006.145.12:44:36.32/cable/+6.5470E-03 2006.145.12:44:37.41/va/01,08,usb,yes,29,31 2006.145.12:44:37.41/va/02,07,usb,yes,30,31 2006.145.12:44:37.41/va/03,08,usb,yes,28,29 2006.145.12:44:37.41/va/04,07,usb,yes,32,33 2006.145.12:44:37.41/va/05,04,usb,yes,28,28 2006.145.12:44:37.41/va/06,04,usb,yes,31,31 2006.145.12:44:37.41/va/07,04,usb,yes,31,32 2006.145.12:44:37.41/va/08,04,usb,yes,27,32 2006.145.12:44:37.64/valo/01,524.99,yes,locked 2006.145.12:44:37.64/valo/02,534.99,yes,locked 2006.145.12:44:37.64/valo/03,564.99,yes,locked 2006.145.12:44:37.64/valo/04,624.99,yes,locked 2006.145.12:44:37.64/valo/05,734.99,yes,locked 2006.145.12:44:37.64/valo/06,814.99,yes,locked 2006.145.12:44:37.64/valo/07,864.99,yes,locked 2006.145.12:44:37.64/valo/08,884.99,yes,locked 2006.145.12:44:38.73/vb/01,03,usb,yes,36,33 2006.145.12:44:38.73/vb/02,04,usb,yes,31,31 2006.145.12:44:38.73/vb/03,04,usb,yes,28,31 2006.145.12:44:38.73/vb/04,04,usb,yes,32,31 2006.145.12:44:38.73/vb/05,04,usb,yes,25,28 2006.145.12:44:38.73/vb/06,04,usb,yes,30,26 2006.145.12:44:38.73/vb/07,04,usb,yes,29,29 2006.145.12:44:38.73/vb/08,04,usb,yes,27,30 2006.145.12:44:38.96/vblo/01,629.99,yes,locked 2006.145.12:44:38.96/vblo/02,634.99,yes,locked 2006.145.12:44:38.96/vblo/03,649.99,yes,locked 2006.145.12:44:38.96/vblo/04,679.99,yes,locked 2006.145.12:44:38.96/vblo/05,709.99,yes,locked 2006.145.12:44:38.96/vblo/06,719.99,yes,locked 2006.145.12:44:38.96/vblo/07,734.99,yes,locked 2006.145.12:44:38.96/vblo/08,744.99,yes,locked 2006.145.12:44:39.11/vabw/8 2006.145.12:44:39.26/vbbw/8 2006.145.12:44:39.35/xfe/off,on,15.0 2006.145.12:44:39.74/ifatt/23,28,28,28 2006.145.12:44:40.07/fmout-gps/S +5.8E-08 2006.145.12:44:40.15:!2006.145.12:57:40 2006.145.12:57:40.00:data_valid=off 2006.145.12:57:40.00:"et 2006.145.12:57:40.01:!+3s 2006.145.12:57:43.02:"tape 2006.145.12:57:43.02:postob 2006.145.12:57:43.17/cable/+6.5471E-03 2006.145.12:57:43.17/wx/15.50,1020.5,82 2006.145.12:57:44.07/fmout-gps/S +5.8E-08 2006.145.12:57:44.07:scan_name=145-1258,jd0605,40 2006.145.12:57:44.08:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.145.12:57:45.13#flagr#flagr/antenna,new-source 2006.145.12:57:45.13:checkk5 2006.145.12:57:45.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.12:57:46.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.12:57:46.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.12:57:46.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.12:57:47.63/chk_obsdata//k5ts1/T1451244??a.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.12:57:48.39/chk_obsdata//k5ts2/T1451244??b.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.12:57:49.13/chk_obsdata//k5ts3/T1451244??c.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.12:57:49.88/chk_obsdata//k5ts4/T1451244??d.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.12:57:50.63/k5log//k5ts1_log_newline 2006.145.12:57:51.37/k5log//k5ts2_log_newline 2006.145.12:57:52.12/k5log//k5ts3_log_newline 2006.145.12:57:52.86/k5log//k5ts4_log_newline 2006.145.12:57:52.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.12:57:52.88:setupk4=1 2006.145.12:57:52.88$setupk4/echo=on 2006.145.12:57:52.88$setupk4/pcalon 2006.145.12:57:52.88$pcalon/"no phase cal control is implemented here 2006.145.12:57:52.88$setupk4/"tpicd=stop 2006.145.12:57:52.88$setupk4/"rec=synch_on 2006.145.12:57:52.88$setupk4/"rec_mode=128 2006.145.12:57:52.88$setupk4/!* 2006.145.12:57:52.88$setupk4/recpk4 2006.145.12:57:52.88$recpk4/recpatch= 2006.145.12:57:52.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.12:57:52.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.12:57:52.88$setupk4/vck44 2006.145.12:57:52.88$vck44/valo=1,524.99 2006.145.12:57:52.88#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.12:57:52.88#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.12:57:52.88#ibcon#ireg 17 cls_cnt 0 2006.145.12:57:52.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:57:52.88#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:57:52.88#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:57:52.90#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.12:57:52.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:57:52.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:57:52.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.12:57:52.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.12:57:52.95$vck44/va=1,8 2006.145.12:57:52.95#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.12:57:52.95#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.12:57:52.95#ibcon#ireg 11 cls_cnt 2 2006.145.12:57:52.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.12:57:52.95#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.12:57:52.95#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.12:57:52.97#ibcon#[25=AT01-08\r\n] 2006.145.12:57:53.00#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.12:57:53.00#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.12:57:53.00#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.12:57:53.00#ibcon#ireg 7 cls_cnt 0 2006.145.12:57:53.00#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.12:57:53.12#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.12:57:53.12#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.12:57:53.14#ibcon#[25=USB\r\n] 2006.145.12:57:53.17#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.12:57:53.17#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.12:57:53.17#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.12:57:53.17#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.12:57:53.17$vck44/valo=2,534.99 2006.145.12:57:53.17#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.12:57:53.17#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.12:57:53.17#ibcon#ireg 17 cls_cnt 0 2006.145.12:57:53.17#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.12:57:53.17#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.12:57:53.17#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.12:57:53.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.12:57:53.24#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.12:57:53.24#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.12:57:53.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.12:57:53.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.12:57:53.24$vck44/va=2,7 2006.145.12:57:53.24#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.12:57:53.24#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.12:57:53.24#ibcon#ireg 11 cls_cnt 2 2006.145.12:57:53.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.12:57:53.29#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.12:57:53.29#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.12:57:53.31#ibcon#[25=AT02-07\r\n] 2006.145.12:57:53.34#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.12:57:53.34#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.12:57:53.34#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.12:57:53.34#ibcon#ireg 7 cls_cnt 0 2006.145.12:57:53.34#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.12:57:53.46#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.12:57:53.46#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.12:57:53.48#ibcon#[25=USB\r\n] 2006.145.12:57:53.51#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.12:57:53.51#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.12:57:53.51#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.12:57:53.51#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.12:57:53.51$vck44/valo=3,564.99 2006.145.12:57:53.51#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.12:57:53.51#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.12:57:53.51#ibcon#ireg 17 cls_cnt 0 2006.145.12:57:53.51#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.12:57:53.51#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.12:57:53.51#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.12:57:53.53#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.12:57:53.57#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.12:57:53.57#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.12:57:53.57#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.12:57:53.57#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.12:57:53.57$vck44/va=3,8 2006.145.12:57:53.57#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.12:57:53.57#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.12:57:53.57#ibcon#ireg 11 cls_cnt 2 2006.145.12:57:53.57#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.12:57:53.63#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.12:57:53.63#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.12:57:53.65#ibcon#[25=AT03-08\r\n] 2006.145.12:57:53.68#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.12:57:53.68#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.12:57:53.68#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.12:57:53.68#ibcon#ireg 7 cls_cnt 0 2006.145.12:57:53.68#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.12:57:53.80#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.12:57:53.80#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.12:57:53.82#ibcon#[25=USB\r\n] 2006.145.12:57:53.85#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.12:57:53.85#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.12:57:53.85#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.12:57:53.85#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.12:57:53.85$vck44/valo=4,624.99 2006.145.12:57:53.85#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.12:57:53.85#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.12:57:53.85#ibcon#ireg 17 cls_cnt 0 2006.145.12:57:53.85#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.12:57:53.85#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.12:57:53.85#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.12:57:53.87#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.12:57:53.91#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.12:57:53.91#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.12:57:53.91#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.12:57:53.91#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.12:57:53.91$vck44/va=4,7 2006.145.12:57:53.91#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.12:57:53.91#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.12:57:53.91#ibcon#ireg 11 cls_cnt 2 2006.145.12:57:53.91#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.12:57:53.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.12:57:53.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.12:57:53.99#ibcon#[25=AT04-07\r\n] 2006.145.12:57:54.02#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.12:57:54.02#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.12:57:54.02#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.12:57:54.02#ibcon#ireg 7 cls_cnt 0 2006.145.12:57:54.02#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.12:57:54.14#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.12:57:54.14#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.12:57:54.16#ibcon#[25=USB\r\n] 2006.145.12:57:54.19#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.12:57:54.19#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.12:57:54.19#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.12:57:54.19#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.12:57:54.19$vck44/valo=5,734.99 2006.145.12:57:54.19#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.12:57:54.19#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.12:57:54.19#ibcon#ireg 17 cls_cnt 0 2006.145.12:57:54.19#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.12:57:54.19#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.12:57:54.19#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.12:57:54.21#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.12:57:54.25#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.12:57:54.25#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.12:57:54.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.12:57:54.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.12:57:54.25$vck44/va=5,4 2006.145.12:57:54.25#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.12:57:54.25#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.12:57:54.25#ibcon#ireg 11 cls_cnt 2 2006.145.12:57:54.25#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.12:57:54.31#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.12:57:54.31#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.12:57:54.33#ibcon#[25=AT05-04\r\n] 2006.145.12:57:54.36#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.12:57:54.36#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.12:57:54.36#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.12:57:54.36#ibcon#ireg 7 cls_cnt 0 2006.145.12:57:54.36#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.12:57:54.48#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.12:57:54.48#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.12:57:54.50#ibcon#[25=USB\r\n] 2006.145.12:57:54.53#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.12:57:54.53#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.12:57:54.53#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.12:57:54.53#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.12:57:54.53$vck44/valo=6,814.99 2006.145.12:57:54.53#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.12:57:54.53#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.12:57:54.53#ibcon#ireg 17 cls_cnt 0 2006.145.12:57:54.53#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.12:57:54.53#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.12:57:54.53#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.12:57:54.56#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.12:57:54.60#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.12:57:54.60#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.12:57:54.60#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.12:57:54.60#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.12:57:54.60$vck44/va=6,4 2006.145.12:57:54.60#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.12:57:54.60#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.12:57:54.60#ibcon#ireg 11 cls_cnt 2 2006.145.12:57:54.60#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.12:57:54.65#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.12:57:54.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.12:57:54.67#ibcon#[25=AT06-04\r\n] 2006.145.12:57:54.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.12:57:54.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.12:57:54.70#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.12:57:54.70#ibcon#ireg 7 cls_cnt 0 2006.145.12:57:54.70#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.12:57:54.82#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.12:57:54.82#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.12:57:54.84#ibcon#[25=USB\r\n] 2006.145.12:57:54.87#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.12:57:54.87#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.12:57:54.87#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.12:57:54.87#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.12:57:54.87$vck44/valo=7,864.99 2006.145.12:57:54.87#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.12:57:54.87#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.12:57:54.87#ibcon#ireg 17 cls_cnt 0 2006.145.12:57:54.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.12:57:54.87#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.12:57:54.87#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.12:57:54.89#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.12:57:54.93#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.12:57:54.93#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.12:57:54.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.12:57:54.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.12:57:54.93$vck44/va=7,4 2006.145.12:57:54.93#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.12:57:54.93#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.12:57:54.93#ibcon#ireg 11 cls_cnt 2 2006.145.12:57:54.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.12:57:54.99#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.12:57:54.99#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.12:57:55.01#ibcon#[25=AT07-04\r\n] 2006.145.12:57:55.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.12:57:55.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.12:57:55.04#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.12:57:55.04#ibcon#ireg 7 cls_cnt 0 2006.145.12:57:55.04#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.12:57:55.16#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.12:57:55.16#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.12:57:55.18#ibcon#[25=USB\r\n] 2006.145.12:57:55.21#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.12:57:55.21#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.12:57:55.21#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.12:57:55.21#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.12:57:55.21$vck44/valo=8,884.99 2006.145.12:57:55.21#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.12:57:55.21#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.12:57:55.21#ibcon#ireg 17 cls_cnt 0 2006.145.12:57:55.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.12:57:55.21#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.12:57:55.21#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.12:57:55.23#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.12:57:55.27#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.12:57:55.27#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.12:57:55.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.12:57:55.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.12:57:55.27$vck44/va=8,4 2006.145.12:57:55.27#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.12:57:55.27#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.12:57:55.27#ibcon#ireg 11 cls_cnt 2 2006.145.12:57:55.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.12:57:55.33#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.12:57:55.33#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.12:57:55.35#ibcon#[25=AT08-04\r\n] 2006.145.12:57:55.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.12:57:55.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.12:57:55.38#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.12:57:55.38#ibcon#ireg 7 cls_cnt 0 2006.145.12:57:55.38#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.12:57:55.50#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.12:57:55.50#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.12:57:55.52#ibcon#[25=USB\r\n] 2006.145.12:57:55.55#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.12:57:55.55#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.12:57:55.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.12:57:55.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.12:57:55.55$vck44/vblo=1,629.99 2006.145.12:57:55.55#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.12:57:55.55#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.12:57:55.55#ibcon#ireg 17 cls_cnt 0 2006.145.12:57:55.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.12:57:55.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.12:57:55.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.12:57:55.57#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.12:57:55.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.12:57:55.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.12:57:55.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.12:57:55.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.12:57:55.61$vck44/vb=1,3 2006.145.12:57:55.61#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.12:57:55.61#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.12:57:55.61#ibcon#ireg 11 cls_cnt 2 2006.145.12:57:55.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.12:57:55.61#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.12:57:55.61#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.12:57:55.63#ibcon#[27=AT01-03\r\n] 2006.145.12:57:55.66#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.12:57:55.66#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.12:57:55.66#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.12:57:55.66#ibcon#ireg 7 cls_cnt 0 2006.145.12:57:55.66#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.12:57:55.78#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.12:57:55.78#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.12:57:55.80#ibcon#[27=USB\r\n] 2006.145.12:57:55.83#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.12:57:55.83#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.12:57:55.83#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.12:57:55.83#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.12:57:55.83$vck44/vblo=2,634.99 2006.145.12:57:55.83#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.12:57:55.83#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.12:57:55.83#ibcon#ireg 17 cls_cnt 0 2006.145.12:57:55.83#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:57:55.83#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:57:55.83#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:57:55.85#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.12:57:55.89#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:57:55.89#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.12:57:55.89#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.12:57:55.89#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.12:57:55.89$vck44/vb=2,4 2006.145.12:57:55.89#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.12:57:55.89#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.12:57:55.89#ibcon#ireg 11 cls_cnt 2 2006.145.12:57:55.89#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.12:57:55.95#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.12:57:55.95#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.12:57:55.97#ibcon#[27=AT02-04\r\n] 2006.145.12:57:56.00#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.12:57:56.00#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.12:57:56.00#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.12:57:56.00#ibcon#ireg 7 cls_cnt 0 2006.145.12:57:56.00#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.12:57:56.12#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.12:57:56.12#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.12:57:56.14#ibcon#[27=USB\r\n] 2006.145.12:57:56.17#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.12:57:56.17#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.12:57:56.17#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.12:57:56.17#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.12:57:56.17$vck44/vblo=3,649.99 2006.145.12:57:56.17#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.12:57:56.17#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.12:57:56.17#ibcon#ireg 17 cls_cnt 0 2006.145.12:57:56.17#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.12:57:56.17#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.12:57:56.17#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.12:57:56.19#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.12:57:56.23#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.12:57:56.23#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.12:57:56.23#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.12:57:56.23#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.12:57:56.23$vck44/vb=3,4 2006.145.12:57:56.23#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.12:57:56.23#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.12:57:56.23#ibcon#ireg 11 cls_cnt 2 2006.145.12:57:56.23#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.12:57:56.29#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.12:57:56.29#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.12:57:56.31#ibcon#[27=AT03-04\r\n] 2006.145.12:57:56.34#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.12:57:56.34#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.12:57:56.34#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.12:57:56.34#ibcon#ireg 7 cls_cnt 0 2006.145.12:57:56.34#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.12:57:56.46#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.12:57:56.46#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.12:57:56.48#ibcon#[27=USB\r\n] 2006.145.12:57:56.51#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.12:57:56.51#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.12:57:56.51#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.12:57:56.51#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.12:57:56.51$vck44/vblo=4,679.99 2006.145.12:57:56.51#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.12:57:56.51#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.12:57:56.51#ibcon#ireg 17 cls_cnt 0 2006.145.12:57:56.51#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.12:57:56.51#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.12:57:56.51#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.12:57:56.53#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.12:57:56.57#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.12:57:56.57#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.12:57:56.57#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.12:57:56.57#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.12:57:56.57$vck44/vb=4,4 2006.145.12:57:56.57#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.12:57:56.57#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.12:57:56.57#ibcon#ireg 11 cls_cnt 2 2006.145.12:57:56.57#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.12:57:56.63#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.12:57:56.63#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.12:57:56.65#ibcon#[27=AT04-04\r\n] 2006.145.12:57:56.68#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.12:57:56.68#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.12:57:56.68#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.12:57:56.68#ibcon#ireg 7 cls_cnt 0 2006.145.12:57:56.68#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.12:57:56.80#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.12:57:56.80#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.12:57:56.82#ibcon#[27=USB\r\n] 2006.145.12:57:56.85#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.12:57:56.85#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.12:57:56.85#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.12:57:56.85#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.12:57:56.85$vck44/vblo=5,709.99 2006.145.12:57:56.85#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.12:57:56.85#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.12:57:56.85#ibcon#ireg 17 cls_cnt 0 2006.145.12:57:56.85#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.12:57:56.85#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.12:57:56.85#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.12:57:56.87#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.12:57:56.91#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.12:57:56.91#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.12:57:56.91#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.12:57:56.91#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.12:57:56.91$vck44/vb=5,4 2006.145.12:57:56.91#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.12:57:56.91#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.12:57:56.91#ibcon#ireg 11 cls_cnt 2 2006.145.12:57:56.91#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.12:57:56.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.12:57:56.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.12:57:56.99#ibcon#[27=AT05-04\r\n] 2006.145.12:57:57.02#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.12:57:57.02#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.12:57:57.02#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.12:57:57.02#ibcon#ireg 7 cls_cnt 0 2006.145.12:57:57.02#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.12:57:57.14#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.12:57:57.14#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.12:57:57.16#ibcon#[27=USB\r\n] 2006.145.12:57:57.19#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.12:57:57.19#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.12:57:57.19#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.12:57:57.19#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.12:57:57.19$vck44/vblo=6,719.99 2006.145.12:57:57.19#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.12:57:57.19#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.12:57:57.19#ibcon#ireg 17 cls_cnt 0 2006.145.12:57:57.19#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.12:57:57.19#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.12:57:57.19#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.12:57:57.21#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.12:57:57.25#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.12:57:57.25#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.12:57:57.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.12:57:57.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.12:57:57.25$vck44/vb=6,4 2006.145.12:57:57.25#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.12:57:57.25#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.12:57:57.25#ibcon#ireg 11 cls_cnt 2 2006.145.12:57:57.25#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.12:57:57.31#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.12:57:57.31#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.12:57:57.33#ibcon#[27=AT06-04\r\n] 2006.145.12:57:57.36#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.12:57:57.36#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.12:57:57.36#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.12:57:57.36#ibcon#ireg 7 cls_cnt 0 2006.145.12:57:57.36#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.12:57:57.48#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.12:57:57.48#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.12:57:57.50#ibcon#[27=USB\r\n] 2006.145.12:57:57.53#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.12:57:57.53#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.12:57:57.53#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.12:57:57.53#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.12:57:57.53$vck44/vblo=7,734.99 2006.145.12:57:57.53#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.12:57:57.53#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.12:57:57.53#ibcon#ireg 17 cls_cnt 0 2006.145.12:57:57.53#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.12:57:57.53#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.12:57:57.53#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.12:57:57.55#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.12:57:57.59#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.12:57:57.59#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.12:57:57.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.12:57:57.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.12:57:57.59$vck44/vb=7,4 2006.145.12:57:57.59#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.12:57:57.59#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.12:57:57.59#ibcon#ireg 11 cls_cnt 2 2006.145.12:57:57.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.12:57:57.65#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.12:57:57.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.12:57:57.67#ibcon#[27=AT07-04\r\n] 2006.145.12:57:57.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.12:57:57.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.12:57:57.70#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.12:57:57.70#ibcon#ireg 7 cls_cnt 0 2006.145.12:57:57.70#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.12:57:57.82#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.12:57:57.82#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.12:57:57.84#ibcon#[27=USB\r\n] 2006.145.12:57:57.87#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.12:57:57.87#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.12:57:57.87#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.12:57:57.87#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.12:57:57.87$vck44/vblo=8,744.99 2006.145.12:57:57.87#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.12:57:57.87#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.12:57:57.87#ibcon#ireg 17 cls_cnt 0 2006.145.12:57:57.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.12:57:57.87#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.12:57:57.87#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.12:57:57.89#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.12:57:57.93#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.12:57:57.93#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.12:57:57.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.12:57:57.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.12:57:57.93$vck44/vb=8,4 2006.145.12:57:57.93#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.12:57:57.93#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.12:57:57.93#ibcon#ireg 11 cls_cnt 2 2006.145.12:57:57.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.12:57:57.99#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.12:57:57.99#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.12:57:58.01#ibcon#[27=AT08-04\r\n] 2006.145.12:57:58.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.12:57:58.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.12:57:58.04#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.12:57:58.04#ibcon#ireg 7 cls_cnt 0 2006.145.12:57:58.04#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.12:57:58.16#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.12:57:58.16#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.12:57:58.18#ibcon#[27=USB\r\n] 2006.145.12:57:58.21#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.12:57:58.21#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.12:57:58.21#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.12:57:58.21#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.12:57:58.21$vck44/vabw=wide 2006.145.12:57:58.21#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.12:57:58.21#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.12:57:58.21#ibcon#ireg 8 cls_cnt 0 2006.145.12:57:58.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.12:57:58.21#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.12:57:58.21#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.12:57:58.23#ibcon#[25=BW32\r\n] 2006.145.12:57:58.26#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.12:57:58.26#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.12:57:58.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.12:57:58.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.12:57:58.26$vck44/vbbw=wide 2006.145.12:57:58.26#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.12:57:58.26#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.12:57:58.26#ibcon#ireg 8 cls_cnt 0 2006.145.12:57:58.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.12:57:58.33#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.12:57:58.33#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.12:57:58.35#ibcon#[27=BW32\r\n] 2006.145.12:57:58.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.12:57:58.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.12:57:58.38#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.12:57:58.38#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.12:57:58.38$setupk4/ifdk4 2006.145.12:57:58.38$ifdk4/lo= 2006.145.12:57:58.38$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.12:57:58.38$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.12:57:58.38$ifdk4/patch= 2006.145.12:57:58.38$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.12:57:58.38$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.12:57:58.38$setupk4/!*+20s 2006.145.12:58:00.14#trakl#Source acquired 2006.145.12:58:01.14#flagr#flagr/antenna,acquired 2006.145.12:58:01.42#abcon#<5=/05 1.2 2.0 15.50 821020.5\r\n> 2006.145.12:58:01.44#abcon#{5=INTERFACE CLEAR} 2006.145.12:58:01.50#abcon#[5=S1D000X0/0*\r\n] 2006.145.12:58:11.59#abcon#<5=/05 1.2 2.0 15.50 821020.5\r\n> 2006.145.12:58:11.61#abcon#{5=INTERFACE CLEAR} 2006.145.12:58:11.67#abcon#[5=S1D000X0/0*\r\n] 2006.145.12:58:12.89$setupk4/"tpicd 2006.145.12:58:12.89$setupk4/echo=off 2006.145.12:58:12.89$setupk4/xlog=off 2006.145.12:58:12.89:!2006.145.12:58:06 2006.145.12:58:12.89:preob 2006.145.12:58:14.14/onsource/TRACKING 2006.145.12:58:14.14:!2006.145.12:58:16 2006.145.12:58:16.00:"tape 2006.145.12:58:16.00:"st=record 2006.145.12:58:16.00:data_valid=on 2006.145.12:58:16.00:midob 2006.145.12:58:16.14/onsource/TRACKING 2006.145.12:58:16.14/wx/15.50,1020.5,82 2006.145.12:58:16.28/cable/+6.5479E-03 2006.145.12:58:17.37/va/01,08,usb,yes,29,31 2006.145.12:58:17.37/va/02,07,usb,yes,31,32 2006.145.12:58:17.37/va/03,08,usb,yes,28,29 2006.145.12:58:17.37/va/04,07,usb,yes,32,34 2006.145.12:58:17.37/va/05,04,usb,yes,28,28 2006.145.12:58:17.37/va/06,04,usb,yes,31,31 2006.145.12:58:17.37/va/07,04,usb,yes,32,33 2006.145.12:58:17.37/va/08,04,usb,yes,27,32 2006.145.12:58:17.60/valo/01,524.99,yes,locked 2006.145.12:58:17.60/valo/02,534.99,yes,locked 2006.145.12:58:17.60/valo/03,564.99,yes,locked 2006.145.12:58:17.60/valo/04,624.99,yes,locked 2006.145.12:58:17.60/valo/05,734.99,yes,locked 2006.145.12:58:17.60/valo/06,814.99,yes,locked 2006.145.12:58:17.60/valo/07,864.99,yes,locked 2006.145.12:58:17.60/valo/08,884.99,yes,locked 2006.145.12:58:18.69/vb/01,03,usb,yes,37,34 2006.145.12:58:18.69/vb/02,04,usb,yes,32,32 2006.145.12:58:18.69/vb/03,04,usb,yes,29,32 2006.145.12:58:18.69/vb/04,04,usb,yes,33,32 2006.145.12:58:18.69/vb/05,04,usb,yes,26,28 2006.145.12:58:18.69/vb/06,04,usb,yes,30,27 2006.145.12:58:18.69/vb/07,04,usb,yes,30,30 2006.145.12:58:18.69/vb/08,04,usb,yes,29,31 2006.145.12:58:18.92/vblo/01,629.99,yes,locked 2006.145.12:58:18.92/vblo/02,634.99,yes,locked 2006.145.12:58:18.92/vblo/03,649.99,yes,locked 2006.145.12:58:18.92/vblo/04,679.99,yes,locked 2006.145.12:58:18.92/vblo/05,709.99,yes,locked 2006.145.12:58:18.92/vblo/06,719.99,yes,locked 2006.145.12:58:18.92/vblo/07,734.99,yes,locked 2006.145.12:58:18.92/vblo/08,744.99,yes,locked 2006.145.12:58:19.07/vabw/8 2006.145.12:58:19.22/vbbw/8 2006.145.12:58:19.31/xfe/off,on,15.2 2006.145.12:58:19.70/ifatt/23,28,28,28 2006.145.12:58:20.07/fmout-gps/S +5.7E-08 2006.145.12:58:20.11:!2006.145.12:58:56 2006.145.12:58:56.00:data_valid=off 2006.145.12:58:56.00:"et 2006.145.12:58:56.01:!+3s 2006.145.12:58:59.02:"tape 2006.145.12:58:59.02:postob 2006.145.12:58:59.12/cable/+6.5477E-03 2006.145.12:58:59.12/wx/15.49,1020.5,82 2006.145.12:58:59.20/fmout-gps/S +5.8E-08 2006.145.12:58:59.20:scan_name=145-1300,jd0605,100 2006.145.12:58:59.20:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.145.12:59:00.14#flagr#flagr/antenna,new-source 2006.145.12:59:00.14:checkk5 2006.145.12:59:00.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.12:59:01.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.12:59:01.49/chk_autoobs//k5ts3/ autoobs is running! 2006.145.12:59:01.92/chk_autoobs//k5ts4/ autoobs is running! 2006.145.12:59:02.33/chk_obsdata//k5ts1/T1451258??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.12:59:02.77/chk_obsdata//k5ts2/T1451258??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.12:59:03.20/chk_obsdata//k5ts3/T1451258??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.12:59:03.65/chk_obsdata//k5ts4/T1451258??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.12:59:04.40/k5log//k5ts1_log_newline 2006.145.12:59:05.14/k5log//k5ts2_log_newline 2006.145.12:59:05.89/k5log//k5ts3_log_newline 2006.145.12:59:06.63/k5log//k5ts4_log_newline 2006.145.12:59:06.65/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.12:59:06.65:setupk4=1 2006.145.12:59:06.65$setupk4/echo=on 2006.145.12:59:06.65$setupk4/pcalon 2006.145.12:59:06.65$pcalon/"no phase cal control is implemented here 2006.145.12:59:06.65$setupk4/"tpicd=stop 2006.145.12:59:06.65$setupk4/"rec=synch_on 2006.145.12:59:06.65$setupk4/"rec_mode=128 2006.145.12:59:06.65$setupk4/!* 2006.145.12:59:06.65$setupk4/recpk4 2006.145.12:59:06.65$recpk4/recpatch= 2006.145.12:59:06.66$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.12:59:06.66$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.12:59:06.66$setupk4/vck44 2006.145.12:59:06.66$vck44/valo=1,524.99 2006.145.12:59:06.66#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.12:59:06.66#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.12:59:06.66#ibcon#ireg 17 cls_cnt 0 2006.145.12:59:06.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.12:59:06.66#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.12:59:06.66#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.12:59:06.70#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.12:59:06.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.12:59:06.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.12:59:06.74#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.12:59:06.74#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.12:59:06.75$vck44/va=1,8 2006.145.12:59:06.75#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.12:59:06.75#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.12:59:06.75#ibcon#ireg 11 cls_cnt 2 2006.145.12:59:06.75#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.12:59:06.75#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.12:59:06.75#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.12:59:06.77#ibcon#[25=AT01-08\r\n] 2006.145.12:59:06.80#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.12:59:06.80#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.12:59:06.80#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.12:59:06.80#ibcon#ireg 7 cls_cnt 0 2006.145.12:59:06.80#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.12:59:06.92#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.12:59:06.92#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.12:59:06.94#ibcon#[25=USB\r\n] 2006.145.12:59:06.97#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.12:59:06.97#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.12:59:06.97#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.12:59:06.97#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.12:59:06.97$vck44/valo=2,534.99 2006.145.12:59:06.97#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.12:59:06.97#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.12:59:06.97#ibcon#ireg 17 cls_cnt 0 2006.145.12:59:06.97#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.12:59:06.97#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.12:59:06.97#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.12:59:06.99#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.12:59:07.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.12:59:07.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.12:59:07.03#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.12:59:07.03#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.12:59:07.03$vck44/va=2,7 2006.145.12:59:07.03#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.12:59:07.03#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.12:59:07.03#ibcon#ireg 11 cls_cnt 2 2006.145.12:59:07.03#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.12:59:07.09#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.12:59:07.09#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.12:59:07.11#ibcon#[25=AT02-07\r\n] 2006.145.12:59:07.14#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.12:59:07.14#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.12:59:07.14#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.12:59:07.14#ibcon#ireg 7 cls_cnt 0 2006.145.12:59:07.14#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.12:59:07.26#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.12:59:07.26#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.12:59:07.28#ibcon#[25=USB\r\n] 2006.145.12:59:07.31#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.12:59:07.31#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.12:59:07.31#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.12:59:07.31#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.12:59:07.31$vck44/valo=3,564.99 2006.145.12:59:07.31#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.12:59:07.31#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.12:59:07.31#ibcon#ireg 17 cls_cnt 0 2006.145.12:59:07.31#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.12:59:07.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.12:59:07.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.12:59:07.33#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.12:59:07.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.12:59:07.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.12:59:07.37#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.12:59:07.37#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.12:59:07.37$vck44/va=3,8 2006.145.12:59:07.37#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.12:59:07.37#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.12:59:07.37#ibcon#ireg 11 cls_cnt 2 2006.145.12:59:07.37#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.12:59:07.43#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.12:59:07.43#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.12:59:07.45#ibcon#[25=AT03-08\r\n] 2006.145.12:59:07.48#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.12:59:07.48#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.12:59:07.48#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.12:59:07.48#ibcon#ireg 7 cls_cnt 0 2006.145.12:59:07.48#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.12:59:07.60#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.12:59:07.60#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.12:59:07.62#ibcon#[25=USB\r\n] 2006.145.12:59:07.65#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.12:59:07.65#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.12:59:07.65#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.12:59:07.65#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.12:59:07.65$vck44/valo=4,624.99 2006.145.12:59:07.65#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.12:59:07.65#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.12:59:07.65#ibcon#ireg 17 cls_cnt 0 2006.145.12:59:07.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.12:59:07.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.12:59:07.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.12:59:07.67#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.12:59:07.71#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.12:59:07.71#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.12:59:07.71#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.12:59:07.71#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.12:59:07.71$vck44/va=4,7 2006.145.12:59:07.71#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.12:59:07.71#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.12:59:07.71#ibcon#ireg 11 cls_cnt 2 2006.145.12:59:07.71#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.12:59:07.77#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.12:59:07.77#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.12:59:07.79#ibcon#[25=AT04-07\r\n] 2006.145.12:59:07.82#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.12:59:07.82#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.12:59:07.82#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.12:59:07.82#ibcon#ireg 7 cls_cnt 0 2006.145.12:59:07.82#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.12:59:07.94#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.12:59:07.94#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.12:59:07.96#ibcon#[25=USB\r\n] 2006.145.12:59:07.99#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.12:59:07.99#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.12:59:07.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.12:59:07.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.12:59:07.99$vck44/valo=5,734.99 2006.145.12:59:07.99#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.12:59:07.99#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.12:59:07.99#ibcon#ireg 17 cls_cnt 0 2006.145.12:59:07.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.12:59:07.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.12:59:07.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.12:59:08.01#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.12:59:08.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.12:59:08.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.12:59:08.05#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.12:59:08.05#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.12:59:08.05$vck44/va=5,4 2006.145.12:59:08.05#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.12:59:08.05#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.12:59:08.05#ibcon#ireg 11 cls_cnt 2 2006.145.12:59:08.05#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.12:59:08.11#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.12:59:08.11#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.12:59:08.13#ibcon#[25=AT05-04\r\n] 2006.145.12:59:08.16#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.12:59:08.16#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.12:59:08.16#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.12:59:08.16#ibcon#ireg 7 cls_cnt 0 2006.145.12:59:08.16#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.12:59:08.28#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.12:59:08.28#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.12:59:08.30#ibcon#[25=USB\r\n] 2006.145.12:59:08.33#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.12:59:08.33#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.12:59:08.33#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.12:59:08.33#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.12:59:08.33$vck44/valo=6,814.99 2006.145.12:59:08.33#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.12:59:08.33#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.12:59:08.33#ibcon#ireg 17 cls_cnt 0 2006.145.12:59:08.33#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.12:59:08.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.12:59:08.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.12:59:08.35#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.12:59:08.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.12:59:08.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.12:59:08.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.12:59:08.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.12:59:08.39$vck44/va=6,4 2006.145.12:59:08.39#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.12:59:08.39#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.12:59:08.39#ibcon#ireg 11 cls_cnt 2 2006.145.12:59:08.39#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.12:59:08.45#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.12:59:08.45#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.12:59:08.47#ibcon#[25=AT06-04\r\n] 2006.145.12:59:08.50#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.12:59:08.50#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.12:59:08.50#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.12:59:08.50#ibcon#ireg 7 cls_cnt 0 2006.145.12:59:08.50#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.12:59:08.62#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.12:59:08.62#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.12:59:08.64#ibcon#[25=USB\r\n] 2006.145.12:59:08.67#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.12:59:08.67#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.12:59:08.67#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.12:59:08.67#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.12:59:08.67$vck44/valo=7,864.99 2006.145.12:59:08.67#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.12:59:08.67#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.12:59:08.67#ibcon#ireg 17 cls_cnt 0 2006.145.12:59:08.67#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.12:59:08.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.12:59:08.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.12:59:08.69#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.12:59:08.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.12:59:08.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.12:59:08.73#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.12:59:08.73#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.12:59:08.73$vck44/va=7,4 2006.145.12:59:08.73#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.12:59:08.73#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.12:59:08.73#ibcon#ireg 11 cls_cnt 2 2006.145.12:59:08.73#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.12:59:08.79#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.12:59:08.79#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.12:59:08.81#ibcon#[25=AT07-04\r\n] 2006.145.12:59:08.84#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.12:59:08.84#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.12:59:08.84#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.12:59:08.84#ibcon#ireg 7 cls_cnt 0 2006.145.12:59:08.84#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.12:59:08.96#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.12:59:08.96#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.12:59:08.98#ibcon#[25=USB\r\n] 2006.145.12:59:09.01#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.12:59:09.01#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.12:59:09.01#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.12:59:09.01#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.12:59:09.01$vck44/valo=8,884.99 2006.145.12:59:09.01#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.12:59:09.01#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.12:59:09.01#ibcon#ireg 17 cls_cnt 0 2006.145.12:59:09.01#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.12:59:09.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.12:59:09.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.12:59:09.03#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.12:59:09.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.12:59:09.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.12:59:09.07#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.12:59:09.07#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.12:59:09.07$vck44/va=8,4 2006.145.12:59:09.07#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.12:59:09.07#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.12:59:09.07#ibcon#ireg 11 cls_cnt 2 2006.145.12:59:09.07#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.12:59:09.13#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.12:59:09.13#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.12:59:09.15#ibcon#[25=AT08-04\r\n] 2006.145.12:59:09.18#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.12:59:09.18#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.12:59:09.18#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.12:59:09.18#ibcon#ireg 7 cls_cnt 0 2006.145.12:59:09.18#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.12:59:09.30#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.12:59:09.30#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.12:59:09.32#ibcon#[25=USB\r\n] 2006.145.12:59:09.35#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.12:59:09.35#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.12:59:09.35#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.12:59:09.35#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.12:59:09.35$vck44/vblo=1,629.99 2006.145.12:59:09.35#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.12:59:09.35#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.12:59:09.35#ibcon#ireg 17 cls_cnt 0 2006.145.12:59:09.35#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.12:59:09.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.12:59:09.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.12:59:09.37#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.12:59:09.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.12:59:09.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.12:59:09.41#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.12:59:09.41#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.12:59:09.41$vck44/vb=1,3 2006.145.12:59:09.41#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.12:59:09.41#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.12:59:09.41#ibcon#ireg 11 cls_cnt 2 2006.145.12:59:09.41#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.12:59:09.41#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.12:59:09.41#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.12:59:09.43#ibcon#[27=AT01-03\r\n] 2006.145.12:59:09.46#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.12:59:09.46#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.12:59:09.46#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.12:59:09.46#ibcon#ireg 7 cls_cnt 0 2006.145.12:59:09.46#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.12:59:09.58#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.12:59:09.58#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.12:59:09.60#ibcon#[27=USB\r\n] 2006.145.12:59:09.63#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.12:59:09.63#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.12:59:09.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.12:59:09.63#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.12:59:09.63$vck44/vblo=2,634.99 2006.145.12:59:09.63#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.12:59:09.63#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.12:59:09.63#ibcon#ireg 17 cls_cnt 0 2006.145.12:59:09.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.12:59:09.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.12:59:09.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.12:59:09.65#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.12:59:09.69#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.12:59:09.69#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.12:59:09.69#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.12:59:09.69#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.12:59:09.69$vck44/vb=2,4 2006.145.12:59:09.69#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.12:59:09.69#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.12:59:09.69#ibcon#ireg 11 cls_cnt 2 2006.145.12:59:09.69#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.12:59:09.75#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.12:59:09.75#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.12:59:09.77#ibcon#[27=AT02-04\r\n] 2006.145.12:59:09.80#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.12:59:09.80#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.12:59:09.80#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.12:59:09.80#ibcon#ireg 7 cls_cnt 0 2006.145.12:59:09.80#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.12:59:09.92#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.12:59:09.92#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.12:59:09.94#ibcon#[27=USB\r\n] 2006.145.12:59:09.97#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.12:59:09.97#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.12:59:09.97#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.12:59:09.97#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.12:59:09.97$vck44/vblo=3,649.99 2006.145.12:59:09.97#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.12:59:09.97#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.12:59:09.97#ibcon#ireg 17 cls_cnt 0 2006.145.12:59:09.97#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.12:59:09.97#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.12:59:09.97#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.12:59:09.99#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.12:59:10.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.12:59:10.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.12:59:10.03#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.12:59:10.03#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.12:59:10.03$vck44/vb=3,4 2006.145.12:59:10.03#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.12:59:10.03#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.12:59:10.03#ibcon#ireg 11 cls_cnt 2 2006.145.12:59:10.03#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.12:59:10.09#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.12:59:10.09#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.12:59:10.11#ibcon#[27=AT03-04\r\n] 2006.145.12:59:10.14#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.12:59:10.14#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.12:59:10.14#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.12:59:10.14#ibcon#ireg 7 cls_cnt 0 2006.145.12:59:10.14#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.12:59:10.26#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.12:59:10.26#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.12:59:10.28#ibcon#[27=USB\r\n] 2006.145.12:59:10.31#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.12:59:10.31#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.12:59:10.31#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.12:59:10.31#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.12:59:10.31$vck44/vblo=4,679.99 2006.145.12:59:10.31#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.12:59:10.31#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.12:59:10.31#ibcon#ireg 17 cls_cnt 0 2006.145.12:59:10.31#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.12:59:10.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.12:59:10.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.12:59:10.33#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.12:59:10.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.12:59:10.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.12:59:10.37#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.12:59:10.37#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.12:59:10.37$vck44/vb=4,4 2006.145.12:59:10.37#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.12:59:10.37#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.12:59:10.37#ibcon#ireg 11 cls_cnt 2 2006.145.12:59:10.37#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.12:59:10.43#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.12:59:10.43#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.12:59:10.45#ibcon#[27=AT04-04\r\n] 2006.145.12:59:10.48#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.12:59:10.48#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.12:59:10.48#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.12:59:10.48#ibcon#ireg 7 cls_cnt 0 2006.145.12:59:10.48#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.12:59:10.60#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.12:59:10.60#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.12:59:10.62#ibcon#[27=USB\r\n] 2006.145.12:59:10.65#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.12:59:10.65#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.12:59:10.65#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.12:59:10.65#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.12:59:10.65$vck44/vblo=5,709.99 2006.145.12:59:10.65#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.12:59:10.65#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.12:59:10.65#ibcon#ireg 17 cls_cnt 0 2006.145.12:59:10.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.12:59:10.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.12:59:10.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.12:59:10.67#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.12:59:10.71#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.12:59:10.71#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.12:59:10.71#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.12:59:10.71#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.12:59:10.71$vck44/vb=5,4 2006.145.12:59:10.71#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.12:59:10.71#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.12:59:10.71#ibcon#ireg 11 cls_cnt 2 2006.145.12:59:10.71#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.12:59:10.77#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.12:59:10.77#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.12:59:10.79#ibcon#[27=AT05-04\r\n] 2006.145.12:59:10.82#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.12:59:10.82#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.12:59:10.82#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.12:59:10.82#ibcon#ireg 7 cls_cnt 0 2006.145.12:59:10.82#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.12:59:10.94#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.12:59:10.94#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.12:59:10.96#ibcon#[27=USB\r\n] 2006.145.12:59:10.99#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.12:59:10.99#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.12:59:10.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.12:59:10.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.12:59:10.99$vck44/vblo=6,719.99 2006.145.12:59:10.99#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.12:59:10.99#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.12:59:10.99#ibcon#ireg 17 cls_cnt 0 2006.145.12:59:10.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.12:59:10.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.12:59:10.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.12:59:11.01#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.12:59:11.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.12:59:11.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.12:59:11.05#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.12:59:11.05#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.12:59:11.05$vck44/vb=6,4 2006.145.12:59:11.05#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.12:59:11.05#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.12:59:11.05#ibcon#ireg 11 cls_cnt 2 2006.145.12:59:11.05#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.12:59:11.11#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.12:59:11.11#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.12:59:11.13#ibcon#[27=AT06-04\r\n] 2006.145.12:59:11.16#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.12:59:11.16#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.12:59:11.16#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.12:59:11.16#ibcon#ireg 7 cls_cnt 0 2006.145.12:59:11.16#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.12:59:11.28#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.12:59:11.28#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.12:59:11.30#ibcon#[27=USB\r\n] 2006.145.12:59:11.33#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.12:59:11.33#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.12:59:11.33#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.12:59:11.33#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.12:59:11.33$vck44/vblo=7,734.99 2006.145.12:59:11.33#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.12:59:11.33#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.12:59:11.33#ibcon#ireg 17 cls_cnt 0 2006.145.12:59:11.33#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.12:59:11.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.12:59:11.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.12:59:11.35#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.12:59:11.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.12:59:11.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.12:59:11.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.12:59:11.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.12:59:11.39$vck44/vb=7,4 2006.145.12:59:11.39#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.12:59:11.39#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.12:59:11.39#ibcon#ireg 11 cls_cnt 2 2006.145.12:59:11.39#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.12:59:11.45#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.12:59:11.45#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.12:59:11.47#ibcon#[27=AT07-04\r\n] 2006.145.12:59:11.50#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.12:59:11.50#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.12:59:11.50#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.12:59:11.50#ibcon#ireg 7 cls_cnt 0 2006.145.12:59:11.50#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.12:59:11.62#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.12:59:11.62#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.12:59:11.64#ibcon#[27=USB\r\n] 2006.145.12:59:11.67#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.12:59:11.67#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.12:59:11.67#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.12:59:11.67#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.12:59:11.67$vck44/vblo=8,744.99 2006.145.12:59:11.67#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.12:59:11.67#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.12:59:11.67#ibcon#ireg 17 cls_cnt 0 2006.145.12:59:11.67#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.12:59:11.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.12:59:11.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.12:59:11.69#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.12:59:11.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.12:59:11.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.12:59:11.73#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.12:59:11.73#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.12:59:11.73$vck44/vb=8,4 2006.145.12:59:11.73#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.12:59:11.73#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.12:59:11.73#ibcon#ireg 11 cls_cnt 2 2006.145.12:59:11.73#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.12:59:11.79#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.12:59:11.79#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.12:59:11.81#ibcon#[27=AT08-04\r\n] 2006.145.12:59:11.84#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.12:59:11.84#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.12:59:11.84#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.12:59:11.84#ibcon#ireg 7 cls_cnt 0 2006.145.12:59:11.84#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.12:59:11.96#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.12:59:11.96#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.12:59:11.98#ibcon#[27=USB\r\n] 2006.145.12:59:12.01#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.12:59:12.01#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.12:59:12.01#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.12:59:12.01#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.12:59:12.01$vck44/vabw=wide 2006.145.12:59:12.01#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.12:59:12.01#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.12:59:12.01#ibcon#ireg 8 cls_cnt 0 2006.145.12:59:12.01#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.12:59:12.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.12:59:12.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.12:59:12.03#ibcon#[25=BW32\r\n] 2006.145.12:59:12.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.12:59:12.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.12:59:12.06#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.12:59:12.06#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.12:59:12.06$vck44/vbbw=wide 2006.145.12:59:12.06#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.12:59:12.06#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.12:59:12.06#ibcon#ireg 8 cls_cnt 0 2006.145.12:59:12.06#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.12:59:12.13#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.12:59:12.13#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.12:59:12.15#ibcon#[27=BW32\r\n] 2006.145.12:59:12.18#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.12:59:12.18#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.12:59:12.18#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.12:59:12.18#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.12:59:12.18$setupk4/ifdk4 2006.145.12:59:12.18$ifdk4/lo= 2006.145.12:59:12.18$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.12:59:12.18$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.12:59:12.18$ifdk4/patch= 2006.145.12:59:12.18$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.12:59:12.18$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.12:59:12.18$setupk4/!*+20s 2006.145.12:59:12.62#abcon#<5=/05 1.1 2.0 15.49 821020.5\r\n> 2006.145.12:59:12.64#abcon#{5=INTERFACE CLEAR} 2006.145.12:59:12.70#abcon#[5=S1D000X0/0*\r\n] 2006.145.12:59:22.79#abcon#<5=/05 1.1 1.9 15.49 821020.5\r\n> 2006.145.12:59:22.81#abcon#{5=INTERFACE CLEAR} 2006.145.12:59:22.87#abcon#[5=S1D000X0/0*\r\n] 2006.145.12:59:26.66$setupk4/"tpicd 2006.145.12:59:26.66$setupk4/echo=off 2006.145.12:59:26.66$setupk4/xlog=off 2006.145.12:59:26.66:!2006.145.13:00:08 2006.145.12:59:33.13#trakl#Source acquired 2006.145.12:59:34.13#flagr#flagr/antenna,acquired 2006.145.13:00:08.00:preob 2006.145.13:00:08.13/onsource/TRACKING 2006.145.13:00:08.13:!2006.145.13:00:18 2006.145.13:00:18.00:"tape 2006.145.13:00:18.00:"st=record 2006.145.13:00:18.00:data_valid=on 2006.145.13:00:18.00:midob 2006.145.13:00:19.13/onsource/TRACKING 2006.145.13:00:19.13/wx/15.48,1020.5,82 2006.145.13:00:19.28/cable/+6.5481E-03 2006.145.13:00:20.37/va/01,08,usb,yes,29,31 2006.145.13:00:20.37/va/02,07,usb,yes,31,31 2006.145.13:00:20.37/va/03,08,usb,yes,28,29 2006.145.13:00:20.37/va/04,07,usb,yes,32,33 2006.145.13:00:20.37/va/05,04,usb,yes,27,28 2006.145.13:00:20.37/va/06,04,usb,yes,31,31 2006.145.13:00:20.37/va/07,04,usb,yes,31,32 2006.145.13:00:20.37/va/08,04,usb,yes,27,32 2006.145.13:00:20.60/valo/01,524.99,yes,locked 2006.145.13:00:20.60/valo/02,534.99,yes,locked 2006.145.13:00:20.60/valo/03,564.99,yes,locked 2006.145.13:00:20.60/valo/04,624.99,yes,locked 2006.145.13:00:20.60/valo/05,734.99,yes,locked 2006.145.13:00:20.60/valo/06,814.99,yes,locked 2006.145.13:00:20.60/valo/07,864.99,yes,locked 2006.145.13:00:20.60/valo/08,884.99,yes,locked 2006.145.13:00:21.69/vb/01,03,usb,yes,36,33 2006.145.13:00:21.69/vb/02,04,usb,yes,31,31 2006.145.13:00:21.69/vb/03,04,usb,yes,28,31 2006.145.13:00:21.69/vb/04,04,usb,yes,32,31 2006.145.13:00:21.69/vb/05,04,usb,yes,25,28 2006.145.13:00:21.69/vb/06,04,usb,yes,29,26 2006.145.13:00:21.69/vb/07,04,usb,yes,29,29 2006.145.13:00:21.69/vb/08,04,usb,yes,27,30 2006.145.13:00:21.92/vblo/01,629.99,yes,locked 2006.145.13:00:21.92/vblo/02,634.99,yes,locked 2006.145.13:00:21.92/vblo/03,649.99,yes,locked 2006.145.13:00:21.92/vblo/04,679.99,yes,locked 2006.145.13:00:21.92/vblo/05,709.99,yes,locked 2006.145.13:00:21.92/vblo/06,719.99,yes,locked 2006.145.13:00:21.92/vblo/07,734.99,yes,locked 2006.145.13:00:21.92/vblo/08,744.99,yes,locked 2006.145.13:00:22.07/vabw/8 2006.145.13:00:22.22/vbbw/8 2006.145.13:00:22.31/xfe/off,on,15.5 2006.145.13:00:22.70/ifatt/23,28,28,28 2006.145.13:00:23.08/fmout-gps/S +5.7E-08 2006.145.13:00:23.16:!2006.145.13:01:58 2006.145.13:01:58.00:data_valid=off 2006.145.13:01:58.00:"et 2006.145.13:01:58.01:!+3s 2006.145.13:02:01.02:"tape 2006.145.13:02:01.02:postob 2006.145.13:02:01.22/cable/+6.5499E-03 2006.145.13:02:01.22/wx/15.46,1020.5,83 2006.145.13:02:01.31/fmout-gps/S +5.6E-08 2006.145.13:02:01.31:scan_name=145-1303,jd0605,80 2006.145.13:02:01.31:source=3c274,123049.42,122328.0,2000.0,cw 2006.145.13:02:03.14#flagr#flagr/antenna,new-source 2006.145.13:02:03.14:checkk5 2006.145.13:02:03.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.13:02:04.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.13:02:04.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.13:02:04.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.13:02:05.32/chk_obsdata//k5ts1/T1451300??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.13:02:05.77/chk_obsdata//k5ts2/T1451300??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.13:02:06.21/chk_obsdata//k5ts3/T1451300??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.13:02:06.65/chk_obsdata//k5ts4/T1451300??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.13:02:07.40/k5log//k5ts1_log_newline 2006.145.13:02:08.14/k5log//k5ts2_log_newline 2006.145.13:02:08.89/k5log//k5ts3_log_newline 2006.145.13:02:09.64/k5log//k5ts4_log_newline 2006.145.13:02:09.66/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.13:02:09.66:setupk4=1 2006.145.13:02:09.66$setupk4/echo=on 2006.145.13:02:09.66$setupk4/pcalon 2006.145.13:02:09.66$pcalon/"no phase cal control is implemented here 2006.145.13:02:09.66$setupk4/"tpicd=stop 2006.145.13:02:09.66$setupk4/"rec=synch_on 2006.145.13:02:09.66$setupk4/"rec_mode=128 2006.145.13:02:09.66$setupk4/!* 2006.145.13:02:09.66$setupk4/recpk4 2006.145.13:02:09.66$recpk4/recpatch= 2006.145.13:02:09.67$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.13:02:09.67$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.13:02:09.67$setupk4/vck44 2006.145.13:02:09.67$vck44/valo=1,524.99 2006.145.13:02:09.67#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.13:02:09.67#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.13:02:09.67#ibcon#ireg 17 cls_cnt 0 2006.145.13:02:09.67#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.13:02:09.67#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.13:02:09.67#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.13:02:09.71#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.13:02:09.76#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.13:02:09.76#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.13:02:09.76#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.13:02:09.76#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.13:02:09.76$vck44/va=1,8 2006.145.13:02:09.76#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.13:02:09.76#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.13:02:09.76#ibcon#ireg 11 cls_cnt 2 2006.145.13:02:09.76#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.13:02:09.76#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.13:02:09.76#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.13:02:09.78#ibcon#[25=AT01-08\r\n] 2006.145.13:02:09.81#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.13:02:09.81#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.13:02:09.81#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.13:02:09.81#ibcon#ireg 7 cls_cnt 0 2006.145.13:02:09.81#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.13:02:09.93#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.13:02:09.93#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.13:02:09.95#ibcon#[25=USB\r\n] 2006.145.13:02:09.98#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.13:02:09.98#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.13:02:09.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.13:02:09.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.13:02:09.98$vck44/valo=2,534.99 2006.145.13:02:09.98#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.13:02:09.98#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.13:02:09.98#ibcon#ireg 17 cls_cnt 0 2006.145.13:02:09.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.13:02:09.98#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.13:02:09.98#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.13:02:10.01#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.13:02:10.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.13:02:10.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.13:02:10.05#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.13:02:10.05#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.13:02:10.05$vck44/va=2,7 2006.145.13:02:10.05#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.13:02:10.05#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.13:02:10.05#ibcon#ireg 11 cls_cnt 2 2006.145.13:02:10.05#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.13:02:10.10#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.13:02:10.10#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.13:02:10.12#ibcon#[25=AT02-07\r\n] 2006.145.13:02:10.15#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.13:02:10.15#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.13:02:10.15#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.13:02:10.15#ibcon#ireg 7 cls_cnt 0 2006.145.13:02:10.15#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.13:02:10.27#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.13:02:10.27#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.13:02:10.29#ibcon#[25=USB\r\n] 2006.145.13:02:10.32#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.13:02:10.32#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.13:02:10.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.13:02:10.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.13:02:10.32$vck44/valo=3,564.99 2006.145.13:02:10.32#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.13:02:10.32#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.13:02:10.32#ibcon#ireg 17 cls_cnt 0 2006.145.13:02:10.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.13:02:10.32#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.13:02:10.32#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.13:02:10.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.13:02:10.38#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.13:02:10.38#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.13:02:10.38#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.13:02:10.38#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.13:02:10.38$vck44/va=3,8 2006.145.13:02:10.38#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.13:02:10.38#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.13:02:10.38#ibcon#ireg 11 cls_cnt 2 2006.145.13:02:10.38#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.13:02:10.44#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.13:02:10.44#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.13:02:10.46#ibcon#[25=AT03-08\r\n] 2006.145.13:02:10.49#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.13:02:10.49#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.13:02:10.49#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.13:02:10.49#ibcon#ireg 7 cls_cnt 0 2006.145.13:02:10.49#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.13:02:10.61#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.13:02:10.61#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.13:02:10.63#ibcon#[25=USB\r\n] 2006.145.13:02:10.66#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.13:02:10.66#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.13:02:10.66#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.13:02:10.66#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.13:02:10.66$vck44/valo=4,624.99 2006.145.13:02:10.66#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.13:02:10.66#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.13:02:10.66#ibcon#ireg 17 cls_cnt 0 2006.145.13:02:10.66#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.13:02:10.66#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.13:02:10.66#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.13:02:10.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.13:02:10.72#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.13:02:10.72#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.13:02:10.72#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.13:02:10.72#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.13:02:10.72$vck44/va=4,7 2006.145.13:02:10.72#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.13:02:10.72#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.13:02:10.72#ibcon#ireg 11 cls_cnt 2 2006.145.13:02:10.72#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.13:02:10.78#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.13:02:10.78#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.13:02:10.80#ibcon#[25=AT04-07\r\n] 2006.145.13:02:10.83#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.13:02:10.83#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.13:02:10.83#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.13:02:10.83#ibcon#ireg 7 cls_cnt 0 2006.145.13:02:10.83#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.13:02:10.95#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.13:02:10.95#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.13:02:10.97#ibcon#[25=USB\r\n] 2006.145.13:02:11.00#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.13:02:11.00#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.13:02:11.00#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.13:02:11.00#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.13:02:11.00$vck44/valo=5,734.99 2006.145.13:02:11.00#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.13:02:11.00#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.13:02:11.00#ibcon#ireg 17 cls_cnt 0 2006.145.13:02:11.00#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.13:02:11.00#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.13:02:11.00#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.13:02:11.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.13:02:11.06#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.13:02:11.06#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.13:02:11.06#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.13:02:11.06#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.13:02:11.06$vck44/va=5,4 2006.145.13:02:11.06#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.13:02:11.06#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.13:02:11.06#ibcon#ireg 11 cls_cnt 2 2006.145.13:02:11.06#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.13:02:11.12#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.13:02:11.12#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.13:02:11.14#ibcon#[25=AT05-04\r\n] 2006.145.13:02:11.17#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.13:02:11.17#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.13:02:11.17#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.13:02:11.17#ibcon#ireg 7 cls_cnt 0 2006.145.13:02:11.17#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.13:02:11.29#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.13:02:11.29#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.13:02:11.31#ibcon#[25=USB\r\n] 2006.145.13:02:11.34#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.13:02:11.34#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.13:02:11.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.13:02:11.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.13:02:11.34$vck44/valo=6,814.99 2006.145.13:02:11.34#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.13:02:11.34#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.13:02:11.34#ibcon#ireg 17 cls_cnt 0 2006.145.13:02:11.34#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.13:02:11.34#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.13:02:11.34#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.13:02:11.36#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.13:02:11.40#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.13:02:11.40#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.13:02:11.40#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.13:02:11.40#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.13:02:11.40$vck44/va=6,4 2006.145.13:02:11.40#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.13:02:11.40#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.13:02:11.40#ibcon#ireg 11 cls_cnt 2 2006.145.13:02:11.40#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.13:02:11.46#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.13:02:11.46#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.13:02:11.48#ibcon#[25=AT06-04\r\n] 2006.145.13:02:11.51#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.13:02:11.51#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.13:02:11.51#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.13:02:11.51#ibcon#ireg 7 cls_cnt 0 2006.145.13:02:11.51#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.13:02:11.63#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.13:02:11.63#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.13:02:11.65#ibcon#[25=USB\r\n] 2006.145.13:02:11.68#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.13:02:11.68#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.13:02:11.68#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.13:02:11.68#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.13:02:11.68$vck44/valo=7,864.99 2006.145.13:02:11.68#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.13:02:11.68#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.13:02:11.68#ibcon#ireg 17 cls_cnt 0 2006.145.13:02:11.68#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.13:02:11.68#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.13:02:11.68#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.13:02:11.70#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.13:02:11.74#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.13:02:11.74#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.13:02:11.74#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.13:02:11.74#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.13:02:11.74$vck44/va=7,4 2006.145.13:02:11.74#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.13:02:11.74#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.13:02:11.74#ibcon#ireg 11 cls_cnt 2 2006.145.13:02:11.74#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.13:02:11.80#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.13:02:11.80#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.13:02:11.82#ibcon#[25=AT07-04\r\n] 2006.145.13:02:11.85#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.13:02:11.85#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.13:02:11.85#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.13:02:11.85#ibcon#ireg 7 cls_cnt 0 2006.145.13:02:11.85#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.13:02:11.97#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.13:02:11.97#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.13:02:11.99#ibcon#[25=USB\r\n] 2006.145.13:02:12.02#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.13:02:12.02#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.13:02:12.02#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.13:02:12.02#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.13:02:12.02$vck44/valo=8,884.99 2006.145.13:02:12.02#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.13:02:12.02#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.13:02:12.02#ibcon#ireg 17 cls_cnt 0 2006.145.13:02:12.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.13:02:12.02#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.13:02:12.02#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.13:02:12.04#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.13:02:12.08#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.13:02:12.08#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.13:02:12.08#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.13:02:12.08#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.13:02:12.08$vck44/va=8,4 2006.145.13:02:12.08#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.13:02:12.08#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.13:02:12.08#ibcon#ireg 11 cls_cnt 2 2006.145.13:02:12.08#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.13:02:12.14#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.13:02:12.14#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.13:02:12.16#ibcon#[25=AT08-04\r\n] 2006.145.13:02:12.19#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.13:02:12.19#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.13:02:12.19#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.13:02:12.19#ibcon#ireg 7 cls_cnt 0 2006.145.13:02:12.19#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.13:02:12.31#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.13:02:12.31#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.13:02:12.35#ibcon#[25=USB\r\n] 2006.145.13:02:12.38#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.13:02:12.38#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.13:02:12.38#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.13:02:12.38#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.13:02:12.38$vck44/vblo=1,629.99 2006.145.13:02:12.38#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.13:02:12.38#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.13:02:12.38#ibcon#ireg 17 cls_cnt 0 2006.145.13:02:12.38#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.13:02:12.38#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.13:02:12.38#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.13:02:12.40#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.13:02:12.44#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.13:02:12.44#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.13:02:12.44#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.13:02:12.44#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.13:02:12.44$vck44/vb=1,3 2006.145.13:02:12.44#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.13:02:12.44#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.13:02:12.44#ibcon#ireg 11 cls_cnt 2 2006.145.13:02:12.44#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.13:02:12.44#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.13:02:12.44#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.13:02:12.46#ibcon#[27=AT01-03\r\n] 2006.145.13:02:12.49#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.13:02:12.49#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.13:02:12.49#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.13:02:12.49#ibcon#ireg 7 cls_cnt 0 2006.145.13:02:12.49#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.13:02:12.61#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.13:02:12.61#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.13:02:12.63#ibcon#[27=USB\r\n] 2006.145.13:02:12.66#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.13:02:12.66#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.13:02:12.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.13:02:12.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.13:02:12.66$vck44/vblo=2,634.99 2006.145.13:02:12.66#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.13:02:12.66#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.13:02:12.66#ibcon#ireg 17 cls_cnt 0 2006.145.13:02:12.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.13:02:12.66#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.13:02:12.66#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.13:02:12.68#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.13:02:12.72#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.13:02:12.72#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.13:02:12.72#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.13:02:12.72#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.13:02:12.72$vck44/vb=2,4 2006.145.13:02:12.72#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.13:02:12.72#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.13:02:12.72#ibcon#ireg 11 cls_cnt 2 2006.145.13:02:12.72#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.13:02:12.78#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.13:02:12.78#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.13:02:12.80#ibcon#[27=AT02-04\r\n] 2006.145.13:02:12.83#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.13:02:12.83#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.13:02:12.83#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.13:02:12.83#ibcon#ireg 7 cls_cnt 0 2006.145.13:02:12.83#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.13:02:12.95#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.13:02:12.95#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.13:02:12.97#ibcon#[27=USB\r\n] 2006.145.13:02:13.00#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.13:02:13.00#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.13:02:13.00#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.13:02:13.00#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.13:02:13.00$vck44/vblo=3,649.99 2006.145.13:02:13.00#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.13:02:13.00#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.13:02:13.00#ibcon#ireg 17 cls_cnt 0 2006.145.13:02:13.00#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.13:02:13.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.13:02:13.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.13:02:13.02#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.13:02:13.06#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.13:02:13.06#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.13:02:13.06#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.13:02:13.06#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.13:02:13.06$vck44/vb=3,4 2006.145.13:02:13.06#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.13:02:13.06#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.13:02:13.06#ibcon#ireg 11 cls_cnt 2 2006.145.13:02:13.06#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.13:02:13.12#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.13:02:13.12#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.13:02:13.14#ibcon#[27=AT03-04\r\n] 2006.145.13:02:13.17#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.13:02:13.17#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.13:02:13.17#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.13:02:13.17#ibcon#ireg 7 cls_cnt 0 2006.145.13:02:13.17#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.13:02:13.29#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.13:02:13.29#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.13:02:13.31#ibcon#[27=USB\r\n] 2006.145.13:02:13.34#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.13:02:13.34#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.13:02:13.34#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.13:02:13.34#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.13:02:13.34$vck44/vblo=4,679.99 2006.145.13:02:13.34#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.13:02:13.34#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.13:02:13.34#ibcon#ireg 17 cls_cnt 0 2006.145.13:02:13.34#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.13:02:13.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.13:02:13.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.13:02:13.36#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.13:02:13.40#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.13:02:13.40#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.13:02:13.40#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.13:02:13.40#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.13:02:13.40$vck44/vb=4,4 2006.145.13:02:13.40#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.13:02:13.40#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.13:02:13.40#ibcon#ireg 11 cls_cnt 2 2006.145.13:02:13.40#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.13:02:13.46#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.13:02:13.46#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.13:02:13.48#ibcon#[27=AT04-04\r\n] 2006.145.13:02:13.51#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.13:02:13.51#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.13:02:13.51#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.13:02:13.51#ibcon#ireg 7 cls_cnt 0 2006.145.13:02:13.51#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.13:02:13.64#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.13:02:13.64#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.13:02:13.66#ibcon#[27=USB\r\n] 2006.145.13:02:13.69#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.13:02:13.69#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.13:02:13.69#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.13:02:13.69#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.13:02:13.69$vck44/vblo=5,709.99 2006.145.13:02:13.69#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.13:02:13.69#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.13:02:13.69#ibcon#ireg 17 cls_cnt 0 2006.145.13:02:13.69#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.13:02:13.69#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.13:02:13.69#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.13:02:13.71#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.13:02:13.75#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.13:02:13.75#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.13:02:13.75#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.13:02:13.75#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.13:02:13.75$vck44/vb=5,4 2006.145.13:02:13.75#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.13:02:13.75#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.13:02:13.75#ibcon#ireg 11 cls_cnt 2 2006.145.13:02:13.75#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.13:02:13.81#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.13:02:13.81#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.13:02:13.83#ibcon#[27=AT05-04\r\n] 2006.145.13:02:13.86#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.13:02:13.86#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.13:02:13.86#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.13:02:13.86#ibcon#ireg 7 cls_cnt 0 2006.145.13:02:13.86#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.13:02:13.98#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.13:02:13.98#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.13:02:14.00#ibcon#[27=USB\r\n] 2006.145.13:02:14.03#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.13:02:14.03#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.13:02:14.03#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.13:02:14.03#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.13:02:14.03$vck44/vblo=6,719.99 2006.145.13:02:14.03#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.13:02:14.03#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.13:02:14.03#ibcon#ireg 17 cls_cnt 0 2006.145.13:02:14.03#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.13:02:14.03#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.13:02:14.03#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.13:02:14.05#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.13:02:14.09#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.13:02:14.09#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.13:02:14.09#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.13:02:14.09#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.13:02:14.09$vck44/vb=6,4 2006.145.13:02:14.09#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.13:02:14.09#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.13:02:14.09#ibcon#ireg 11 cls_cnt 2 2006.145.13:02:14.09#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.13:02:14.15#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.13:02:14.15#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.13:02:14.17#ibcon#[27=AT06-04\r\n] 2006.145.13:02:14.20#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.13:02:14.20#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.13:02:14.20#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.13:02:14.20#ibcon#ireg 7 cls_cnt 0 2006.145.13:02:14.20#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.13:02:14.32#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.13:02:14.32#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.13:02:14.34#ibcon#[27=USB\r\n] 2006.145.13:02:14.37#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.13:02:14.37#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.13:02:14.37#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.13:02:14.37#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.13:02:14.37$vck44/vblo=7,734.99 2006.145.13:02:14.37#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.13:02:14.37#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.13:02:14.37#ibcon#ireg 17 cls_cnt 0 2006.145.13:02:14.37#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.13:02:14.37#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.13:02:14.37#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.13:02:14.39#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.13:02:14.43#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.13:02:14.43#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.13:02:14.43#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.13:02:14.43#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.13:02:14.43$vck44/vb=7,4 2006.145.13:02:14.43#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.13:02:14.43#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.13:02:14.43#ibcon#ireg 11 cls_cnt 2 2006.145.13:02:14.43#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.13:02:14.49#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.13:02:14.49#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.13:02:14.51#ibcon#[27=AT07-04\r\n] 2006.145.13:02:14.54#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.13:02:14.54#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.13:02:14.54#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.13:02:14.54#ibcon#ireg 7 cls_cnt 0 2006.145.13:02:14.54#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.13:02:14.66#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.13:02:14.66#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.13:02:14.68#ibcon#[27=USB\r\n] 2006.145.13:02:14.71#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.13:02:14.71#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.13:02:14.71#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.13:02:14.71#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.13:02:14.71$vck44/vblo=8,744.99 2006.145.13:02:14.71#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.13:02:14.71#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.13:02:14.71#ibcon#ireg 17 cls_cnt 0 2006.145.13:02:14.71#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.13:02:14.71#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.13:02:14.71#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.13:02:14.73#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.13:02:14.77#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.13:02:14.77#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.13:02:14.77#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.13:02:14.77#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.13:02:14.77$vck44/vb=8,4 2006.145.13:02:14.77#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.13:02:14.77#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.13:02:14.77#ibcon#ireg 11 cls_cnt 2 2006.145.13:02:14.77#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.13:02:14.83#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.13:02:14.83#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.13:02:14.85#ibcon#[27=AT08-04\r\n] 2006.145.13:02:14.88#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.13:02:14.88#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.13:02:14.88#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.13:02:14.88#ibcon#ireg 7 cls_cnt 0 2006.145.13:02:14.88#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.13:02:15.00#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.13:02:15.00#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.13:02:15.02#ibcon#[27=USB\r\n] 2006.145.13:02:15.05#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.13:02:15.05#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.13:02:15.05#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.13:02:15.05#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.13:02:15.05$vck44/vabw=wide 2006.145.13:02:15.05#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.13:02:15.05#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.13:02:15.05#ibcon#ireg 8 cls_cnt 0 2006.145.13:02:15.05#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.13:02:15.05#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.13:02:15.05#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.13:02:15.07#ibcon#[25=BW32\r\n] 2006.145.13:02:15.10#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.13:02:15.10#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.13:02:15.10#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.13:02:15.10#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.13:02:15.10$vck44/vbbw=wide 2006.145.13:02:15.10#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.13:02:15.10#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.13:02:15.10#ibcon#ireg 8 cls_cnt 0 2006.145.13:02:15.10#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.13:02:15.17#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.13:02:15.17#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.13:02:15.19#ibcon#[27=BW32\r\n] 2006.145.13:02:15.22#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.13:02:15.22#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.13:02:15.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.13:02:15.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.13:02:15.22$setupk4/ifdk4 2006.145.13:02:15.22$ifdk4/lo= 2006.145.13:02:15.22$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.13:02:15.22$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.13:02:15.22$ifdk4/patch= 2006.145.13:02:15.22$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.13:02:15.22$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.13:02:15.22$setupk4/!*+20s 2006.145.13:02:15.68#abcon#<5=/05 1.0 1.9 15.46 831020.5\r\n> 2006.145.13:02:15.70#abcon#{5=INTERFACE CLEAR} 2006.145.13:02:15.76#abcon#[5=S1D000X0/0*\r\n] 2006.145.13:02:25.14#trakl#Source acquired 2006.145.13:02:25.14#flagr#flagr/antenna,acquired 2006.145.13:02:25.85#abcon#<5=/05 1.0 1.9 15.45 831020.5\r\n> 2006.145.13:02:25.87#abcon#{5=INTERFACE CLEAR} 2006.145.13:02:25.93#abcon#[5=S1D000X0/0*\r\n] 2006.145.13:02:29.67$setupk4/"tpicd 2006.145.13:02:29.67$setupk4/echo=off 2006.145.13:02:29.67$setupk4/xlog=off 2006.145.13:02:29.67:!2006.145.13:03:24 2006.145.13:03:24.00:preob 2006.145.13:03:24.14/onsource/TRACKING 2006.145.13:03:24.14:!2006.145.13:03:34 2006.145.13:03:34.00:"tape 2006.145.13:03:34.00:"st=record 2006.145.13:03:34.00:data_valid=on 2006.145.13:03:34.00:midob 2006.145.13:03:34.14/onsource/TRACKING 2006.145.13:03:34.14/wx/15.44,1020.5,83 2006.145.13:03:34.29/cable/+6.5492E-03 2006.145.13:03:35.38/va/01,08,usb,yes,31,33 2006.145.13:03:35.38/va/02,07,usb,yes,33,34 2006.145.13:03:35.38/va/03,08,usb,yes,30,31 2006.145.13:03:35.38/va/04,07,usb,yes,34,36 2006.145.13:03:35.38/va/05,04,usb,yes,30,30 2006.145.13:03:35.38/va/06,04,usb,yes,33,33 2006.145.13:03:35.38/va/07,04,usb,yes,33,35 2006.145.13:03:35.38/va/08,04,usb,yes,29,34 2006.145.13:03:35.61/valo/01,524.99,yes,locked 2006.145.13:03:35.61/valo/02,534.99,yes,locked 2006.145.13:03:35.61/valo/03,564.99,yes,locked 2006.145.13:03:35.61/valo/04,624.99,yes,locked 2006.145.13:03:35.61/valo/05,734.99,yes,locked 2006.145.13:03:35.61/valo/06,814.99,yes,locked 2006.145.13:03:35.61/valo/07,864.99,yes,locked 2006.145.13:03:35.61/valo/08,884.99,yes,locked 2006.145.13:03:36.70/vb/01,03,usb,yes,44,40 2006.145.13:03:36.70/vb/02,04,usb,yes,38,38 2006.145.13:03:36.70/vb/03,04,usb,yes,35,38 2006.145.13:03:36.70/vb/04,04,usb,yes,39,38 2006.145.13:03:36.70/vb/05,04,usb,yes,31,34 2006.145.13:03:36.70/vb/06,04,usb,yes,36,32 2006.145.13:03:36.70/vb/07,04,usb,yes,35,35 2006.145.13:03:36.70/vb/08,04,usb,yes,33,36 2006.145.13:03:36.93/vblo/01,629.99,yes,locked 2006.145.13:03:36.93/vblo/02,634.99,yes,locked 2006.145.13:03:36.93/vblo/03,649.99,yes,locked 2006.145.13:03:36.93/vblo/04,679.99,yes,locked 2006.145.13:03:36.93/vblo/05,709.99,yes,locked 2006.145.13:03:36.93/vblo/06,719.99,yes,locked 2006.145.13:03:36.93/vblo/07,734.99,yes,locked 2006.145.13:03:36.93/vblo/08,744.99,yes,locked 2006.145.13:03:37.08/vabw/8 2006.145.13:03:37.23/vbbw/8 2006.145.13:03:37.32/xfe/off,on,14.7 2006.145.13:03:37.70/ifatt/23,28,28,28 2006.145.13:03:38.08/fmout-gps/S +5.5E-08 2006.145.13:03:38.16:!2006.145.13:04:54 2006.145.13:04:54.00:data_valid=off 2006.145.13:04:54.00:"et 2006.145.13:04:54.00:!+3s 2006.145.13:04:57.02:"tape 2006.145.13:04:57.02:postob 2006.145.13:04:57.18/cable/+6.5486E-03 2006.145.13:04:57.22/wx/15.43,1020.5,83 2006.145.13:04:58.08/fmout-gps/S +5.5E-08 2006.145.13:04:58.08:scan_name=145-1311,jd0605,310 2006.145.13:04:58.09:source=0642+449,064632.03,445116.6,2000.0,cw 2006.145.13:04:59.14#flagr#flagr/antenna,new-source 2006.145.13:04:59.14:checkk5 2006.145.13:04:59.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.13:05:00.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.13:05:00.48/chk_autoobs//k5ts3/ autoobs is running! 2006.145.13:05:00.91/chk_autoobs//k5ts4/ autoobs is running! 2006.145.13:05:01.32/chk_obsdata//k5ts1/T1451303??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.13:05:01.75/chk_obsdata//k5ts2/T1451303??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.13:05:02.18/chk_obsdata//k5ts3/T1451303??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.13:05:02.62/chk_obsdata//k5ts4/T1451303??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.13:05:03.38/k5log//k5ts1_log_newline 2006.145.13:05:04.14/k5log//k5ts2_log_newline 2006.145.13:05:04.89/k5log//k5ts3_log_newline 2006.145.13:05:05.62/k5log//k5ts4_log_newline 2006.145.13:05:05.64/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.13:05:05.64:setupk4=1 2006.145.13:05:05.64$setupk4/echo=on 2006.145.13:05:05.64$setupk4/pcalon 2006.145.13:05:05.64$pcalon/"no phase cal control is implemented here 2006.145.13:05:05.64$setupk4/"tpicd=stop 2006.145.13:05:05.64$setupk4/"rec=synch_on 2006.145.13:05:05.64$setupk4/"rec_mode=128 2006.145.13:05:05.64$setupk4/!* 2006.145.13:05:05.64$setupk4/recpk4 2006.145.13:05:05.64$recpk4/recpatch= 2006.145.13:05:05.65$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.13:05:05.65$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.13:05:05.65$setupk4/vck44 2006.145.13:05:05.65$vck44/valo=1,524.99 2006.145.13:05:05.65#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.13:05:05.65#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.13:05:05.65#ibcon#ireg 17 cls_cnt 0 2006.145.13:05:05.65#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:05:05.65#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:05:05.65#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:05:05.69#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.13:05:05.73#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:05:05.73#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:05:05.73#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.13:05:05.73#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.13:05:05.73$vck44/va=1,8 2006.145.13:05:05.73#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.13:05:05.73#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.13:05:05.73#ibcon#ireg 11 cls_cnt 2 2006.145.13:05:05.73#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.13:05:05.73#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.13:05:05.73#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.13:05:05.75#ibcon#[25=AT01-08\r\n] 2006.145.13:05:05.78#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.13:05:05.78#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.13:05:05.78#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.13:05:05.78#ibcon#ireg 7 cls_cnt 0 2006.145.13:05:05.78#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.13:05:05.90#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.13:05:05.90#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.13:05:05.92#ibcon#[25=USB\r\n] 2006.145.13:05:05.95#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.13:05:05.95#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.13:05:05.95#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.13:05:05.95#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.13:05:05.95$vck44/valo=2,534.99 2006.145.13:05:05.95#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.13:05:05.95#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.13:05:05.95#ibcon#ireg 17 cls_cnt 0 2006.145.13:05:05.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.13:05:05.95#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.13:05:05.95#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.13:05:05.98#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.13:05:06.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.13:05:06.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.13:05:06.02#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.13:05:06.02#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.13:05:06.02$vck44/va=2,7 2006.145.13:05:06.02#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.13:05:06.02#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.13:05:06.02#ibcon#ireg 11 cls_cnt 2 2006.145.13:05:06.02#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.13:05:06.07#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.13:05:06.07#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.13:05:06.09#ibcon#[25=AT02-07\r\n] 2006.145.13:05:06.12#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.13:05:06.12#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.13:05:06.12#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.13:05:06.12#ibcon#ireg 7 cls_cnt 0 2006.145.13:05:06.12#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.13:05:06.24#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.13:05:06.24#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.13:05:06.26#ibcon#[25=USB\r\n] 2006.145.13:05:06.29#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.13:05:06.29#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.13:05:06.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.13:05:06.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.13:05:06.29$vck44/valo=3,564.99 2006.145.13:05:06.29#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.13:05:06.29#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.13:05:06.29#ibcon#ireg 17 cls_cnt 0 2006.145.13:05:06.29#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:05:06.29#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:05:06.29#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:05:06.31#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.13:05:06.35#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:05:06.35#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:05:06.35#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.13:05:06.35#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.13:05:06.35$vck44/va=3,8 2006.145.13:05:06.35#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.13:05:06.35#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.13:05:06.35#ibcon#ireg 11 cls_cnt 2 2006.145.13:05:06.35#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.13:05:06.41#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.13:05:06.41#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.13:05:06.43#ibcon#[25=AT03-08\r\n] 2006.145.13:05:06.46#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.13:05:06.46#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.13:05:06.46#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.13:05:06.46#ibcon#ireg 7 cls_cnt 0 2006.145.13:05:06.46#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.13:05:06.58#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.13:05:06.58#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.13:05:06.60#ibcon#[25=USB\r\n] 2006.145.13:05:06.63#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.13:05:06.63#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.13:05:06.63#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.13:05:06.63#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.13:05:06.63$vck44/valo=4,624.99 2006.145.13:05:06.63#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.13:05:06.63#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.13:05:06.63#ibcon#ireg 17 cls_cnt 0 2006.145.13:05:06.63#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:05:06.63#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:05:06.63#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:05:06.65#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.13:05:06.69#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:05:06.69#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:05:06.69#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.13:05:06.69#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.13:05:06.69$vck44/va=4,7 2006.145.13:05:06.69#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.13:05:06.69#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.13:05:06.69#ibcon#ireg 11 cls_cnt 2 2006.145.13:05:06.69#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:05:06.75#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:05:06.75#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:05:06.77#ibcon#[25=AT04-07\r\n] 2006.145.13:05:06.80#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:05:06.80#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:05:06.80#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.13:05:06.80#ibcon#ireg 7 cls_cnt 0 2006.145.13:05:06.80#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:05:06.92#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:05:06.92#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:05:06.94#ibcon#[25=USB\r\n] 2006.145.13:05:06.97#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:05:06.97#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:05:06.97#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.13:05:06.97#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.13:05:06.97$vck44/valo=5,734.99 2006.145.13:05:06.97#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.13:05:06.97#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.13:05:06.97#ibcon#ireg 17 cls_cnt 0 2006.145.13:05:06.97#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:05:06.97#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:05:06.97#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:05:06.99#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.13:05:07.03#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:05:07.03#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:05:07.03#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.13:05:07.03#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.13:05:07.03$vck44/va=5,4 2006.145.13:05:07.03#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.13:05:07.03#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.13:05:07.03#ibcon#ireg 11 cls_cnt 2 2006.145.13:05:07.03#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:05:07.09#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:05:07.09#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:05:07.11#ibcon#[25=AT05-04\r\n] 2006.145.13:05:07.14#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:05:07.14#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:05:07.14#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.13:05:07.14#ibcon#ireg 7 cls_cnt 0 2006.145.13:05:07.14#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:05:07.26#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:05:07.26#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:05:07.28#ibcon#[25=USB\r\n] 2006.145.13:05:07.31#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:05:07.31#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:05:07.31#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.13:05:07.31#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.13:05:07.31$vck44/valo=6,814.99 2006.145.13:05:07.31#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.13:05:07.31#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.13:05:07.31#ibcon#ireg 17 cls_cnt 0 2006.145.13:05:07.31#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:05:07.31#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:05:07.31#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:05:07.33#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.13:05:07.37#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:05:07.37#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:05:07.37#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.13:05:07.37#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.13:05:07.37$vck44/va=6,4 2006.145.13:05:07.37#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.13:05:07.37#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.13:05:07.37#ibcon#ireg 11 cls_cnt 2 2006.145.13:05:07.37#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:05:07.43#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:05:07.43#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:05:07.45#ibcon#[25=AT06-04\r\n] 2006.145.13:05:07.48#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:05:07.48#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:05:07.48#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.13:05:07.48#ibcon#ireg 7 cls_cnt 0 2006.145.13:05:07.48#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:05:07.60#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:05:07.60#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:05:07.62#ibcon#[25=USB\r\n] 2006.145.13:05:07.65#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:05:07.65#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:05:07.65#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.13:05:07.65#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.13:05:07.65$vck44/valo=7,864.99 2006.145.13:05:07.65#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.13:05:07.65#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.13:05:07.65#ibcon#ireg 17 cls_cnt 0 2006.145.13:05:07.65#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:05:07.65#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:05:07.65#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:05:07.67#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.13:05:07.71#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:05:07.71#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:05:07.71#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.13:05:07.71#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.13:05:07.71$vck44/va=7,4 2006.145.13:05:07.71#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.13:05:07.71#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.13:05:07.71#ibcon#ireg 11 cls_cnt 2 2006.145.13:05:07.71#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.13:05:07.77#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.13:05:07.77#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.13:05:07.79#ibcon#[25=AT07-04\r\n] 2006.145.13:05:07.82#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.13:05:07.82#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.13:05:07.82#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.13:05:07.82#ibcon#ireg 7 cls_cnt 0 2006.145.13:05:07.82#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.13:05:07.94#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.13:05:07.94#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.13:05:07.96#ibcon#[25=USB\r\n] 2006.145.13:05:07.99#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.13:05:07.99#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.13:05:07.99#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.13:05:07.99#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.13:05:07.99$vck44/valo=8,884.99 2006.145.13:05:07.99#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.13:05:07.99#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.13:05:07.99#ibcon#ireg 17 cls_cnt 0 2006.145.13:05:07.99#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.13:05:07.99#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.13:05:07.99#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.13:05:08.01#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.13:05:08.05#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.13:05:08.05#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.13:05:08.05#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.13:05:08.05#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.13:05:08.05$vck44/va=8,4 2006.145.13:05:08.05#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.13:05:08.05#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.13:05:08.05#ibcon#ireg 11 cls_cnt 2 2006.145.13:05:08.05#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.13:05:08.11#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.13:05:08.11#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.13:05:08.13#ibcon#[25=AT08-04\r\n] 2006.145.13:05:08.16#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.13:05:08.16#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.13:05:08.16#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.13:05:08.16#ibcon#ireg 7 cls_cnt 0 2006.145.13:05:08.16#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.13:05:08.28#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.13:05:08.28#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.13:05:08.30#ibcon#[25=USB\r\n] 2006.145.13:05:08.33#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.13:05:08.33#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.13:05:08.33#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.13:05:08.33#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.13:05:08.33$vck44/vblo=1,629.99 2006.145.13:05:08.33#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.13:05:08.33#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.13:05:08.33#ibcon#ireg 17 cls_cnt 0 2006.145.13:05:08.33#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:05:08.33#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:05:08.33#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:05:08.35#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.13:05:08.39#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:05:08.39#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:05:08.39#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.13:05:08.39#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.13:05:08.39$vck44/vb=1,3 2006.145.13:05:08.39#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.13:05:08.39#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.13:05:08.39#ibcon#ireg 11 cls_cnt 2 2006.145.13:05:08.39#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.13:05:08.39#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.13:05:08.39#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.13:05:08.41#ibcon#[27=AT01-03\r\n] 2006.145.13:05:08.44#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.13:05:08.44#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.13:05:08.44#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.13:05:08.44#ibcon#ireg 7 cls_cnt 0 2006.145.13:05:08.44#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.13:05:08.56#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.13:05:08.56#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.13:05:08.58#ibcon#[27=USB\r\n] 2006.145.13:05:08.61#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.13:05:08.61#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.13:05:08.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.13:05:08.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.13:05:08.61$vck44/vblo=2,634.99 2006.145.13:05:08.61#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.13:05:08.61#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.13:05:08.61#ibcon#ireg 17 cls_cnt 0 2006.145.13:05:08.61#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:05:08.61#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:05:08.61#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:05:08.63#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.13:05:08.66#abcon#<5=/05 1.0 1.9 15.42 831020.5\r\n> 2006.145.13:05:08.67#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:05:08.67#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:05:08.67#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.13:05:08.67#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.13:05:08.67$vck44/vb=2,4 2006.145.13:05:08.67#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.13:05:08.67#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.13:05:08.67#ibcon#ireg 11 cls_cnt 2 2006.145.13:05:08.67#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.13:05:08.68#abcon#{5=INTERFACE CLEAR} 2006.145.13:05:08.73#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.13:05:08.73#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.13:05:08.74#abcon#[5=S1D000X0/0*\r\n] 2006.145.13:05:08.75#ibcon#[27=AT02-04\r\n] 2006.145.13:05:08.78#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.13:05:08.78#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.13:05:08.78#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.13:05:08.78#ibcon#ireg 7 cls_cnt 0 2006.145.13:05:08.78#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.13:05:08.90#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.13:05:08.90#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.13:05:08.92#ibcon#[27=USB\r\n] 2006.145.13:05:08.95#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.13:05:08.95#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.13:05:08.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.13:05:08.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.13:05:08.95$vck44/vblo=3,649.99 2006.145.13:05:08.95#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.13:05:08.95#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.13:05:08.95#ibcon#ireg 17 cls_cnt 0 2006.145.13:05:08.95#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:05:08.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:05:08.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:05:08.97#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.13:05:09.01#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:05:09.01#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:05:09.01#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.13:05:09.01#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.13:05:09.01$vck44/vb=3,4 2006.145.13:05:09.01#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.13:05:09.01#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.13:05:09.01#ibcon#ireg 11 cls_cnt 2 2006.145.13:05:09.01#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.13:05:09.07#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.13:05:09.07#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.13:05:09.09#ibcon#[27=AT03-04\r\n] 2006.145.13:05:09.12#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.13:05:09.12#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.13:05:09.12#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.13:05:09.12#ibcon#ireg 7 cls_cnt 0 2006.145.13:05:09.12#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.13:05:09.24#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.13:05:09.24#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.13:05:09.26#ibcon#[27=USB\r\n] 2006.145.13:05:09.29#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.13:05:09.29#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.13:05:09.29#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.13:05:09.29#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.13:05:09.29$vck44/vblo=4,679.99 2006.145.13:05:09.29#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.13:05:09.29#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.13:05:09.29#ibcon#ireg 17 cls_cnt 0 2006.145.13:05:09.29#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:05:09.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:05:09.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:05:09.31#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.13:05:09.35#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:05:09.35#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:05:09.35#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.13:05:09.35#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.13:05:09.35$vck44/vb=4,4 2006.145.13:05:09.35#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.13:05:09.35#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.13:05:09.35#ibcon#ireg 11 cls_cnt 2 2006.145.13:05:09.35#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:05:09.41#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:05:09.41#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:05:09.43#ibcon#[27=AT04-04\r\n] 2006.145.13:05:09.46#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:05:09.46#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:05:09.46#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.13:05:09.46#ibcon#ireg 7 cls_cnt 0 2006.145.13:05:09.46#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:05:09.58#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:05:09.58#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:05:09.60#ibcon#[27=USB\r\n] 2006.145.13:05:09.63#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:05:09.63#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:05:09.63#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.13:05:09.63#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.13:05:09.63$vck44/vblo=5,709.99 2006.145.13:05:09.63#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.13:05:09.63#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.13:05:09.63#ibcon#ireg 17 cls_cnt 0 2006.145.13:05:09.63#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:05:09.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:05:09.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:05:09.65#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.13:05:09.69#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:05:09.69#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:05:09.69#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.13:05:09.69#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.13:05:09.69$vck44/vb=5,4 2006.145.13:05:09.69#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.13:05:09.69#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.13:05:09.69#ibcon#ireg 11 cls_cnt 2 2006.145.13:05:09.69#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:05:09.75#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:05:09.75#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:05:09.77#ibcon#[27=AT05-04\r\n] 2006.145.13:05:09.80#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:05:09.80#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:05:09.80#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.13:05:09.80#ibcon#ireg 7 cls_cnt 0 2006.145.13:05:09.80#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:05:09.92#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:05:09.92#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:05:09.94#ibcon#[27=USB\r\n] 2006.145.13:05:09.97#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:05:09.97#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:05:09.97#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.13:05:09.97#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.13:05:09.97$vck44/vblo=6,719.99 2006.145.13:05:09.97#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.13:05:09.97#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.13:05:09.97#ibcon#ireg 17 cls_cnt 0 2006.145.13:05:09.97#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:05:09.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:05:09.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:05:09.99#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.13:05:10.03#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:05:10.03#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:05:10.03#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.13:05:10.03#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.13:05:10.03$vck44/vb=6,4 2006.145.13:05:10.03#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.13:05:10.03#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.13:05:10.03#ibcon#ireg 11 cls_cnt 2 2006.145.13:05:10.03#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:05:10.09#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:05:10.09#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:05:10.11#ibcon#[27=AT06-04\r\n] 2006.145.13:05:10.14#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:05:10.14#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:05:10.14#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.13:05:10.14#ibcon#ireg 7 cls_cnt 0 2006.145.13:05:10.14#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:05:10.26#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:05:10.26#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:05:10.28#ibcon#[27=USB\r\n] 2006.145.13:05:10.31#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:05:10.31#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:05:10.31#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.13:05:10.31#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.13:05:10.31$vck44/vblo=7,734.99 2006.145.13:05:10.31#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.13:05:10.31#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.13:05:10.31#ibcon#ireg 17 cls_cnt 0 2006.145.13:05:10.31#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:05:10.31#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:05:10.31#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:05:10.33#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.13:05:10.37#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:05:10.37#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:05:10.37#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.13:05:10.37#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.13:05:10.37$vck44/vb=7,4 2006.145.13:05:10.37#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.13:05:10.37#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.13:05:10.37#ibcon#ireg 11 cls_cnt 2 2006.145.13:05:10.37#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.13:05:10.43#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.13:05:10.43#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.13:05:10.45#ibcon#[27=AT07-04\r\n] 2006.145.13:05:10.48#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.13:05:10.48#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.13:05:10.48#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.13:05:10.48#ibcon#ireg 7 cls_cnt 0 2006.145.13:05:10.48#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.13:05:10.60#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.13:05:10.60#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.13:05:10.62#ibcon#[27=USB\r\n] 2006.145.13:05:10.65#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.13:05:10.65#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.13:05:10.65#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.13:05:10.65#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.13:05:10.65$vck44/vblo=8,744.99 2006.145.13:05:10.65#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.13:05:10.65#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.13:05:10.65#ibcon#ireg 17 cls_cnt 0 2006.145.13:05:10.65#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.13:05:10.65#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.13:05:10.65#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.13:05:10.67#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.13:05:10.71#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.13:05:10.71#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.13:05:10.71#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.13:05:10.71#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.13:05:10.71$vck44/vb=8,4 2006.145.13:05:10.71#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.13:05:10.71#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.13:05:10.71#ibcon#ireg 11 cls_cnt 2 2006.145.13:05:10.71#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.13:05:10.77#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.13:05:10.77#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.13:05:10.79#ibcon#[27=AT08-04\r\n] 2006.145.13:05:10.82#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.13:05:10.82#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.13:05:10.82#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.13:05:10.82#ibcon#ireg 7 cls_cnt 0 2006.145.13:05:10.82#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.13:05:10.94#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.13:05:10.94#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.13:05:10.96#ibcon#[27=USB\r\n] 2006.145.13:05:10.99#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.13:05:10.99#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.13:05:10.99#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.13:05:10.99#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.13:05:10.99$vck44/vabw=wide 2006.145.13:05:10.99#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.13:05:10.99#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.13:05:10.99#ibcon#ireg 8 cls_cnt 0 2006.145.13:05:10.99#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:05:10.99#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:05:10.99#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:05:11.01#ibcon#[25=BW32\r\n] 2006.145.13:05:11.04#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:05:11.04#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:05:11.04#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.13:05:11.04#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.13:05:11.04$vck44/vbbw=wide 2006.145.13:05:11.04#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.13:05:11.04#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.13:05:11.04#ibcon#ireg 8 cls_cnt 0 2006.145.13:05:11.04#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:05:11.11#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:05:11.11#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:05:11.13#ibcon#[27=BW32\r\n] 2006.145.13:05:11.16#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:05:11.16#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:05:11.16#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.13:05:11.16#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.13:05:11.16$setupk4/ifdk4 2006.145.13:05:11.16$ifdk4/lo= 2006.145.13:05:11.16$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.13:05:11.16$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.13:05:11.16$ifdk4/patch= 2006.145.13:05:11.16$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.13:05:11.16$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.13:05:11.16$setupk4/!*+20s 2006.145.13:05:18.83#abcon#<5=/05 1.0 1.9 15.42 831020.5\r\n> 2006.145.13:05:18.85#abcon#{5=INTERFACE CLEAR} 2006.145.13:05:18.91#abcon#[5=S1D000X0/0*\r\n] 2006.145.13:05:25.65$setupk4/"tpicd 2006.145.13:05:25.65$setupk4/echo=off 2006.145.13:05:25.65$setupk4/xlog=off 2006.145.13:05:25.65:!2006.145.13:11:42 2006.145.13:05:34.14#trakl#Source acquired 2006.145.13:05:34.14#flagr#flagr/antenna,acquired 2006.145.13:11:42.02:preob 2006.145.13:11:43.14/onsource/TRACKING 2006.145.13:11:43.14:!2006.145.13:11:52 2006.145.13:11:52.01:"tape 2006.145.13:11:52.02:"st=record 2006.145.13:11:52.02:data_valid=on 2006.145.13:11:52.02:midob 2006.145.13:11:53.14/onsource/TRACKING 2006.145.13:11:53.14/wx/15.37,1020.5,83 2006.145.13:11:53.33/cable/+6.5487E-03 2006.145.13:11:54.42/va/01,08,usb,yes,36,38 2006.145.13:11:54.42/va/02,07,usb,yes,38,39 2006.145.13:11:54.42/va/03,08,usb,yes,35,36 2006.145.13:11:54.42/va/04,07,usb,yes,39,41 2006.145.13:11:54.42/va/05,04,usb,yes,35,35 2006.145.13:11:54.42/va/06,04,usb,yes,39,39 2006.145.13:11:54.42/va/07,04,usb,yes,39,41 2006.145.13:11:54.42/va/08,04,usb,yes,34,40 2006.145.13:11:54.65/valo/01,524.99,yes,locked 2006.145.13:11:54.65/valo/02,534.99,yes,locked 2006.145.13:11:54.65/valo/03,564.99,yes,locked 2006.145.13:11:54.65/valo/04,624.99,yes,locked 2006.145.13:11:54.65/valo/05,734.99,yes,locked 2006.145.13:11:54.65/valo/06,814.99,yes,locked 2006.145.13:11:54.65/valo/07,864.99,yes,locked 2006.145.13:11:54.65/valo/08,884.99,yes,locked 2006.145.13:11:55.74/vb/01,03,usb,yes,40,43 2006.145.13:11:55.74/vb/02,04,usb,yes,35,40 2006.145.13:11:55.74/vb/03,04,usb,yes,32,36 2006.145.13:11:55.74/vb/04,04,usb,yes,37,36 2006.145.13:11:55.74/vb/05,04,usb,yes,29,32 2006.145.13:11:55.74/vb/06,04,usb,yes,34,30 2006.145.13:11:55.74/vb/07,04,usb,yes,34,34 2006.145.13:11:55.74/vb/08,04,usb,yes,31,35 2006.145.13:11:55.97/vblo/01,629.99,yes,locked 2006.145.13:11:55.97/vblo/02,634.99,yes,locked 2006.145.13:11:55.97/vblo/03,649.99,yes,locked 2006.145.13:11:55.97/vblo/04,679.99,yes,locked 2006.145.13:11:55.97/vblo/05,709.99,yes,locked 2006.145.13:11:55.97/vblo/06,719.99,yes,locked 2006.145.13:11:55.97/vblo/07,734.99,yes,locked 2006.145.13:11:55.97/vblo/08,744.99,yes,locked 2006.145.13:11:56.12/vabw/8 2006.145.13:11:56.27/vbbw/8 2006.145.13:11:56.36/xfe/off,on,15.2 2006.145.13:11:56.73/ifatt/23,28,28,28 2006.145.13:11:57.08/fmout-gps/S +5.4E-08 2006.145.13:11:57.16:!2006.145.13:17:02 2006.145.13:17:02.00:data_valid=off 2006.145.13:17:02.01:"et 2006.145.13:17:02.01:!+3s 2006.145.13:17:05.04:"tape 2006.145.13:17:05.05:postob 2006.145.13:17:05.25/cable/+6.5471E-03 2006.145.13:17:05.26/wx/15.35,1020.5,84 2006.145.13:17:05.34/fmout-gps/S +5.4E-08 2006.145.13:17:05.35:scan_name=145-1318,jd0605,400 2006.145.13:17:05.35:source=1308+326,131028.66,322043.8,2000.0,cw 2006.145.13:17:06.13#flagr#flagr/antenna,new-source 2006.145.13:17:06.14:checkk5 2006.145.13:17:06.61/chk_autoobs//k5ts1/ autoobs is running! 2006.145.13:17:07.06/chk_autoobs//k5ts2/ autoobs is running! 2006.145.13:17:07.51/chk_autoobs//k5ts3/ autoobs is running! 2006.145.13:17:07.96/chk_autoobs//k5ts4/ autoobs is running! 2006.145.13:17:08.39/chk_obsdata//k5ts1/T1451311??a.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.145.13:17:08.83/chk_obsdata//k5ts2/T1451311??b.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.145.13:17:09.26/chk_obsdata//k5ts3/T1451311??c.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.145.13:17:09.68/chk_obsdata//k5ts4/T1451311??d.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.145.13:17:10.45/k5log//k5ts1_log_newline 2006.145.13:17:11.20/k5log//k5ts2_log_newline 2006.145.13:17:11.95/k5log//k5ts3_log_newline 2006.145.13:17:12.71/k5log//k5ts4_log_newline 2006.145.13:17:12.74/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.13:17:12.74:setupk4=1 2006.145.13:17:12.74$setupk4/echo=on 2006.145.13:17:12.74$setupk4/pcalon 2006.145.13:17:12.74$pcalon/"no phase cal control is implemented here 2006.145.13:17:12.74$setupk4/"tpicd=stop 2006.145.13:17:12.74$setupk4/"rec=synch_on 2006.145.13:17:12.74$setupk4/"rec_mode=128 2006.145.13:17:12.74$setupk4/!* 2006.145.13:17:12.74$setupk4/recpk4 2006.145.13:17:12.74$recpk4/recpatch= 2006.145.13:17:12.74$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.13:17:12.74$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.13:17:12.74$setupk4/vck44 2006.145.13:17:12.74$vck44/valo=1,524.99 2006.145.13:17:12.74#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.13:17:12.74#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.13:17:12.74#ibcon#ireg 17 cls_cnt 0 2006.145.13:17:12.74#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:17:12.74#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:17:12.74#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:17:12.75#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.13:17:12.80#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:17:12.80#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:17:12.80#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.13:17:12.80#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.13:17:12.80$vck44/va=1,8 2006.145.13:17:12.80#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.13:17:12.80#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.13:17:12.80#ibcon#ireg 11 cls_cnt 2 2006.145.13:17:12.80#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:17:12.80#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:17:12.80#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:17:12.82#ibcon#[25=AT01-08\r\n] 2006.145.13:17:12.85#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:17:12.85#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:17:12.85#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.13:17:12.85#ibcon#ireg 7 cls_cnt 0 2006.145.13:17:12.85#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:17:12.97#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:17:12.97#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:17:12.99#ibcon#[25=USB\r\n] 2006.145.13:17:13.02#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:17:13.02#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:17:13.02#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.13:17:13.02#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.13:17:13.02$vck44/valo=2,534.99 2006.145.13:17:13.02#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.13:17:13.02#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.13:17:13.02#ibcon#ireg 17 cls_cnt 0 2006.145.13:17:13.02#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:17:13.02#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:17:13.02#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:17:13.06#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.13:17:13.09#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:17:13.09#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:17:13.09#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.13:17:13.09#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.13:17:13.09$vck44/va=2,7 2006.145.13:17:13.09#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.13:17:13.09#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.13:17:13.09#ibcon#ireg 11 cls_cnt 2 2006.145.13:17:13.09#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.13:17:13.15#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.13:17:13.15#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.13:17:13.16#ibcon#[25=AT02-07\r\n] 2006.145.13:17:13.19#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.13:17:13.19#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.13:17:13.19#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.13:17:13.19#ibcon#ireg 7 cls_cnt 0 2006.145.13:17:13.19#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.13:17:13.31#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.13:17:13.31#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.13:17:13.33#ibcon#[25=USB\r\n] 2006.145.13:17:13.36#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.13:17:13.36#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.13:17:13.36#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.13:17:13.36#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.13:17:13.36$vck44/valo=3,564.99 2006.145.13:17:13.36#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.13:17:13.36#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.13:17:13.36#ibcon#ireg 17 cls_cnt 0 2006.145.13:17:13.36#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:17:13.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:17:13.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:17:13.38#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.13:17:13.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:17:13.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:17:13.42#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.13:17:13.42#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.13:17:13.42$vck44/va=3,8 2006.145.13:17:13.42#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.13:17:13.42#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.13:17:13.42#ibcon#ireg 11 cls_cnt 2 2006.145.13:17:13.42#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.13:17:13.48#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.13:17:13.48#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.13:17:13.50#ibcon#[25=AT03-08\r\n] 2006.145.13:17:13.53#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.13:17:13.53#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.13:17:13.53#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.13:17:13.53#ibcon#ireg 7 cls_cnt 0 2006.145.13:17:13.53#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.13:17:13.65#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.13:17:13.65#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.13:17:13.67#ibcon#[25=USB\r\n] 2006.145.13:17:13.70#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.13:17:13.70#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.13:17:13.70#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.13:17:13.70#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.13:17:13.70$vck44/valo=4,624.99 2006.145.13:17:13.70#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.13:17:13.70#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.13:17:13.70#ibcon#ireg 17 cls_cnt 0 2006.145.13:17:13.70#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:17:13.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:17:13.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:17:13.72#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.13:17:13.76#abcon#<5=/05 0.9 2.0 15.35 841020.5\r\n> 2006.145.13:17:13.76#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:17:13.76#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:17:13.76#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.13:17:13.76#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.13:17:13.76$vck44/va=4,7 2006.145.13:17:13.76#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.13:17:13.76#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.13:17:13.76#ibcon#ireg 11 cls_cnt 2 2006.145.13:17:13.76#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.13:17:13.78#abcon#{5=INTERFACE CLEAR} 2006.145.13:17:13.82#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.13:17:13.82#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.13:17:13.84#ibcon#[25=AT04-07\r\n] 2006.145.13:17:13.84#abcon#[5=S1D000X0/0*\r\n] 2006.145.13:17:13.87#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.13:17:13.87#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.13:17:13.87#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.13:17:13.87#ibcon#ireg 7 cls_cnt 0 2006.145.13:17:13.87#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.13:17:13.99#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.13:17:13.99#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.13:17:14.01#ibcon#[25=USB\r\n] 2006.145.13:17:14.04#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.13:17:14.04#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.13:17:14.04#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.13:17:14.04#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.13:17:14.04$vck44/valo=5,734.99 2006.145.13:17:14.04#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.13:17:14.04#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.13:17:14.04#ibcon#ireg 17 cls_cnt 0 2006.145.13:17:14.04#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:17:14.04#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:17:14.04#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:17:14.06#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.13:17:14.10#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:17:14.10#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:17:14.10#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.13:17:14.10#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.13:17:14.10$vck44/va=5,4 2006.145.13:17:14.10#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.13:17:14.10#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.13:17:14.10#ibcon#ireg 11 cls_cnt 2 2006.145.13:17:14.10#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.13:17:14.16#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.13:17:14.16#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.13:17:14.18#ibcon#[25=AT05-04\r\n] 2006.145.13:17:14.21#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.13:17:14.21#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.13:17:14.21#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.13:17:14.21#ibcon#ireg 7 cls_cnt 0 2006.145.13:17:14.21#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.13:17:14.33#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.13:17:14.33#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.13:17:14.35#ibcon#[25=USB\r\n] 2006.145.13:17:14.38#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.13:17:14.38#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.13:17:14.38#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.13:17:14.38#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.13:17:14.38$vck44/valo=6,814.99 2006.145.13:17:14.38#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.13:17:14.38#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.13:17:14.38#ibcon#ireg 17 cls_cnt 0 2006.145.13:17:14.38#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:17:14.38#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:17:14.38#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:17:14.42#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.13:17:14.45#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:17:14.45#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:17:14.45#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.13:17:14.45#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.13:17:14.45$vck44/va=6,4 2006.145.13:17:14.45#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.13:17:14.45#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.13:17:14.45#ibcon#ireg 11 cls_cnt 2 2006.145.13:17:14.45#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:17:14.50#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:17:14.50#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:17:14.52#ibcon#[25=AT06-04\r\n] 2006.145.13:17:14.55#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:17:14.55#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:17:14.55#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.13:17:14.55#ibcon#ireg 7 cls_cnt 0 2006.145.13:17:14.55#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:17:14.67#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:17:14.67#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:17:14.69#ibcon#[25=USB\r\n] 2006.145.13:17:14.72#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:17:14.72#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:17:14.72#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.13:17:14.72#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.13:17:14.72$vck44/valo=7,864.99 2006.145.13:17:14.72#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.13:17:14.72#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.13:17:14.72#ibcon#ireg 17 cls_cnt 0 2006.145.13:17:14.72#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:17:14.72#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:17:14.72#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:17:14.74#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.13:17:14.78#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:17:14.78#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:17:14.78#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.13:17:14.78#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.13:17:14.78$vck44/va=7,4 2006.145.13:17:14.78#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.13:17:14.78#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.13:17:14.78#ibcon#ireg 11 cls_cnt 2 2006.145.13:17:14.78#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:17:14.84#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:17:14.84#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:17:14.86#ibcon#[25=AT07-04\r\n] 2006.145.13:17:14.89#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:17:14.89#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:17:14.89#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.13:17:14.89#ibcon#ireg 7 cls_cnt 0 2006.145.13:17:14.89#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:17:15.01#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:17:15.01#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:17:15.03#ibcon#[25=USB\r\n] 2006.145.13:17:15.06#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:17:15.06#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:17:15.06#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.13:17:15.06#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.13:17:15.06$vck44/valo=8,884.99 2006.145.13:17:15.06#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.13:17:15.06#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.13:17:15.06#ibcon#ireg 17 cls_cnt 0 2006.145.13:17:15.06#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:17:15.06#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:17:15.06#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:17:15.08#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.13:17:15.12#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:17:15.12#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:17:15.12#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.13:17:15.12#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.13:17:15.12$vck44/va=8,4 2006.145.13:17:15.12#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.13:17:15.12#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.13:17:15.12#ibcon#ireg 11 cls_cnt 2 2006.145.13:17:15.12#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:17:15.18#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:17:15.18#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:17:15.20#ibcon#[25=AT08-04\r\n] 2006.145.13:17:15.23#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:17:15.23#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:17:15.23#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.13:17:15.23#ibcon#ireg 7 cls_cnt 0 2006.145.13:17:15.23#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:17:15.35#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:17:15.35#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:17:15.37#ibcon#[25=USB\r\n] 2006.145.13:17:15.40#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:17:15.40#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:17:15.40#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.13:17:15.40#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.13:17:15.40$vck44/vblo=1,629.99 2006.145.13:17:15.40#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.13:17:15.40#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.13:17:15.40#ibcon#ireg 17 cls_cnt 0 2006.145.13:17:15.40#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:17:15.40#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:17:15.40#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:17:15.42#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.13:17:15.47#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:17:15.47#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:17:15.47#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.13:17:15.47#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.13:17:15.47$vck44/vb=1,3 2006.145.13:17:15.47#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.13:17:15.47#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.13:17:15.47#ibcon#ireg 11 cls_cnt 2 2006.145.13:17:15.47#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:17:15.47#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:17:15.47#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:17:15.48#ibcon#[27=AT01-03\r\n] 2006.145.13:17:15.51#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:17:15.51#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:17:15.51#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.13:17:15.51#ibcon#ireg 7 cls_cnt 0 2006.145.13:17:15.51#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:17:15.63#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:17:15.63#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:17:15.65#ibcon#[27=USB\r\n] 2006.145.13:17:15.68#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:17:15.68#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:17:15.68#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.13:17:15.68#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.13:17:15.68$vck44/vblo=2,634.99 2006.145.13:17:15.68#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.13:17:15.68#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.13:17:15.68#ibcon#ireg 17 cls_cnt 0 2006.145.13:17:15.68#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:17:15.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:17:15.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:17:15.72#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.13:17:15.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:17:15.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:17:15.75#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.13:17:15.75#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.13:17:15.75$vck44/vb=2,4 2006.145.13:17:15.75#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.13:17:15.75#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.13:17:15.75#ibcon#ireg 11 cls_cnt 2 2006.145.13:17:15.75#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.13:17:15.81#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.13:17:15.81#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.13:17:15.82#ibcon#[27=AT02-04\r\n] 2006.145.13:17:15.85#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.13:17:15.85#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.13:17:15.85#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.13:17:15.85#ibcon#ireg 7 cls_cnt 0 2006.145.13:17:15.85#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.13:17:15.97#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.13:17:15.97#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.13:17:15.99#ibcon#[27=USB\r\n] 2006.145.13:17:16.02#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.13:17:16.02#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.13:17:16.02#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.13:17:16.02#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.13:17:16.02$vck44/vblo=3,649.99 2006.145.13:17:16.02#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.13:17:16.02#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.13:17:16.02#ibcon#ireg 17 cls_cnt 0 2006.145.13:17:16.02#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:17:16.02#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:17:16.02#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:17:16.04#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.13:17:16.08#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:17:16.08#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:17:16.08#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.13:17:16.08#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.13:17:16.08$vck44/vb=3,4 2006.145.13:17:16.08#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.13:17:16.08#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.13:17:16.08#ibcon#ireg 11 cls_cnt 2 2006.145.13:17:16.08#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.13:17:16.14#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.13:17:16.14#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.13:17:16.16#ibcon#[27=AT03-04\r\n] 2006.145.13:17:16.19#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.13:17:16.19#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.13:17:16.19#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.13:17:16.19#ibcon#ireg 7 cls_cnt 0 2006.145.13:17:16.19#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.13:17:16.31#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.13:17:16.31#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.13:17:16.33#ibcon#[27=USB\r\n] 2006.145.13:17:16.36#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.13:17:16.36#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.13:17:16.36#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.13:17:16.36#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.13:17:16.36$vck44/vblo=4,679.99 2006.145.13:17:16.36#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.13:17:16.36#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.13:17:16.36#ibcon#ireg 17 cls_cnt 0 2006.145.13:17:16.36#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:17:16.36#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:17:16.36#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:17:16.38#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.13:17:16.42#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:17:16.42#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:17:16.42#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.13:17:16.42#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.13:17:16.42$vck44/vb=4,4 2006.145.13:17:16.42#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.13:17:16.42#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.13:17:16.42#ibcon#ireg 11 cls_cnt 2 2006.145.13:17:16.42#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.13:17:16.48#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.13:17:16.48#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.13:17:16.50#ibcon#[27=AT04-04\r\n] 2006.145.13:17:16.53#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.13:17:16.53#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.13:17:16.53#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.13:17:16.53#ibcon#ireg 7 cls_cnt 0 2006.145.13:17:16.53#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.13:17:16.65#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.13:17:16.65#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.13:17:16.67#ibcon#[27=USB\r\n] 2006.145.13:17:16.70#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.13:17:16.70#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.13:17:16.70#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.13:17:16.70#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.13:17:16.70$vck44/vblo=5,709.99 2006.145.13:17:16.70#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.13:17:16.70#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.13:17:16.70#ibcon#ireg 17 cls_cnt 0 2006.145.13:17:16.70#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:17:16.70#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:17:16.70#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:17:16.72#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.13:17:16.76#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:17:16.76#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:17:16.76#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.13:17:16.76#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.13:17:16.76$vck44/vb=5,4 2006.145.13:17:16.76#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.13:17:16.76#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.13:17:16.76#ibcon#ireg 11 cls_cnt 2 2006.145.13:17:16.76#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.13:17:16.82#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.13:17:16.82#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.13:17:16.84#ibcon#[27=AT05-04\r\n] 2006.145.13:17:16.88#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.13:17:16.88#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.13:17:16.88#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.13:17:16.88#ibcon#ireg 7 cls_cnt 0 2006.145.13:17:16.88#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.13:17:16.99#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.13:17:16.99#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.13:17:17.01#ibcon#[27=USB\r\n] 2006.145.13:17:17.04#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.13:17:17.04#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.13:17:17.04#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.13:17:17.04#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.13:17:17.04$vck44/vblo=6,719.99 2006.145.13:17:17.04#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.13:17:17.04#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.13:17:17.04#ibcon#ireg 17 cls_cnt 0 2006.145.13:17:17.04#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:17:17.04#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:17:17.04#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:17:17.06#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.13:17:17.10#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:17:17.10#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:17:17.10#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.13:17:17.10#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.13:17:17.10$vck44/vb=6,4 2006.145.13:17:17.10#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.13:17:17.10#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.13:17:17.10#ibcon#ireg 11 cls_cnt 2 2006.145.13:17:17.10#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.13:17:17.16#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.13:17:17.16#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.13:17:17.18#ibcon#[27=AT06-04\r\n] 2006.145.13:17:17.21#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.13:17:17.21#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.13:17:17.21#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.13:17:17.21#ibcon#ireg 7 cls_cnt 0 2006.145.13:17:17.21#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.13:17:17.33#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.13:17:17.33#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.13:17:17.35#ibcon#[27=USB\r\n] 2006.145.13:17:17.38#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.13:17:17.38#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.13:17:17.38#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.13:17:17.38#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.13:17:17.38$vck44/vblo=7,734.99 2006.145.13:17:17.38#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.13:17:17.38#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.13:17:17.38#ibcon#ireg 17 cls_cnt 0 2006.145.13:17:17.38#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:17:17.38#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:17:17.38#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:17:17.40#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.13:17:17.44#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:17:17.44#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:17:17.44#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.13:17:17.44#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.13:17:17.44$vck44/vb=7,4 2006.145.13:17:17.44#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.13:17:17.44#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.13:17:17.44#ibcon#ireg 11 cls_cnt 2 2006.145.13:17:17.44#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:17:17.50#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:17:17.50#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:17:17.52#ibcon#[27=AT07-04\r\n] 2006.145.13:17:17.55#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:17:17.55#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:17:17.55#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.13:17:17.55#ibcon#ireg 7 cls_cnt 0 2006.145.13:17:17.55#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:17:17.67#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:17:17.67#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:17:17.69#ibcon#[27=USB\r\n] 2006.145.13:17:17.72#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:17:17.72#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:17:17.72#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.13:17:17.72#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.13:17:17.72$vck44/vblo=8,744.99 2006.145.13:17:17.72#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.13:17:17.72#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.13:17:17.72#ibcon#ireg 17 cls_cnt 0 2006.145.13:17:17.72#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:17:17.72#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:17:17.72#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:17:17.74#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.13:17:17.78#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:17:17.78#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:17:17.78#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.13:17:17.78#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.13:17:17.78$vck44/vb=8,4 2006.145.13:17:17.78#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.13:17:17.78#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.13:17:17.78#ibcon#ireg 11 cls_cnt 2 2006.145.13:17:17.78#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:17:17.84#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:17:17.84#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:17:17.86#ibcon#[27=AT08-04\r\n] 2006.145.13:17:17.89#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:17:17.89#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:17:17.89#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.13:17:17.89#ibcon#ireg 7 cls_cnt 0 2006.145.13:17:17.89#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:17:18.01#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:17:18.01#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:17:18.03#ibcon#[27=USB\r\n] 2006.145.13:17:18.06#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:17:18.06#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:17:18.06#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.13:17:18.06#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.13:17:18.06$vck44/vabw=wide 2006.145.13:17:18.06#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.13:17:18.06#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.13:17:18.06#ibcon#ireg 8 cls_cnt 0 2006.145.13:17:18.06#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:17:18.06#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:17:18.06#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:17:18.08#ibcon#[25=BW32\r\n] 2006.145.13:17:18.11#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:17:18.11#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:17:18.11#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.13:17:18.11#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.13:17:18.11$vck44/vbbw=wide 2006.145.13:17:18.11#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.13:17:18.11#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.13:17:18.11#ibcon#ireg 8 cls_cnt 0 2006.145.13:17:18.11#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:17:18.18#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:17:18.18#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:17:18.20#ibcon#[27=BW32\r\n] 2006.145.13:17:18.23#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:17:18.23#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:17:18.23#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.13:17:18.23#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.13:17:18.23$setupk4/ifdk4 2006.145.13:17:18.23$ifdk4/lo= 2006.145.13:17:18.23$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.13:17:18.23$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.13:17:18.23$ifdk4/patch= 2006.145.13:17:18.23$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.13:17:18.24$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.13:17:18.24$setupk4/!*+20s 2006.145.13:17:23.93#abcon#<5=/05 0.9 2.0 15.35 841020.5\r\n> 2006.145.13:17:23.95#abcon#{5=INTERFACE CLEAR} 2006.145.13:17:24.01#abcon#[5=S1D000X0/0*\r\n] 2006.145.13:17:32.76$setupk4/"tpicd 2006.145.13:17:32.76$setupk4/echo=off 2006.145.13:17:32.76$setupk4/xlog=off 2006.145.13:17:32.76:!2006.145.13:18:14 2006.145.13:17:36.13#trakl#Source acquired 2006.145.13:17:38.13#flagr#flagr/antenna,acquired 2006.145.13:18:14.00:preob 2006.145.13:18:15.14/onsource/TRACKING 2006.145.13:18:15.14:!2006.145.13:18:24 2006.145.13:18:24.00:"tape 2006.145.13:18:24.00:"st=record 2006.145.13:18:24.00:data_valid=on 2006.145.13:18:24.00:midob 2006.145.13:18:24.14/onsource/TRACKING 2006.145.13:18:24.14/wx/15.34,1020.5,85 2006.145.13:18:24.20/cable/+6.5499E-03 2006.145.13:18:25.29/va/01,08,usb,yes,28,30 2006.145.13:18:25.29/va/02,07,usb,yes,29,30 2006.145.13:18:25.29/va/03,08,usb,yes,27,28 2006.145.13:18:25.29/va/04,07,usb,yes,31,32 2006.145.13:18:25.29/va/05,04,usb,yes,27,27 2006.145.13:18:25.29/va/06,04,usb,yes,30,30 2006.145.13:18:25.29/va/07,04,usb,yes,30,31 2006.145.13:18:25.29/va/08,04,usb,yes,26,31 2006.145.13:18:25.52/valo/01,524.99,yes,locked 2006.145.13:18:25.52/valo/02,534.99,yes,locked 2006.145.13:18:25.52/valo/03,564.99,yes,locked 2006.145.13:18:25.52/valo/04,624.99,yes,locked 2006.145.13:18:25.52/valo/05,734.99,yes,locked 2006.145.13:18:25.52/valo/06,814.99,yes,locked 2006.145.13:18:25.52/valo/07,864.99,yes,locked 2006.145.13:18:25.52/valo/08,884.99,yes,locked 2006.145.13:18:26.61/vb/01,03,usb,yes,35,33 2006.145.13:18:26.61/vb/02,04,usb,yes,30,30 2006.145.13:18:26.61/vb/03,04,usb,yes,28,30 2006.145.13:18:26.61/vb/04,04,usb,yes,32,31 2006.145.13:18:26.61/vb/05,04,usb,yes,25,27 2006.145.13:18:26.61/vb/06,04,usb,yes,29,25 2006.145.13:18:26.61/vb/07,04,usb,yes,29,28 2006.145.13:18:26.61/vb/08,04,usb,yes,26,29 2006.145.13:18:26.84/vblo/01,629.99,yes,locked 2006.145.13:18:26.84/vblo/02,634.99,yes,locked 2006.145.13:18:26.84/vblo/03,649.99,yes,locked 2006.145.13:18:26.84/vblo/04,679.99,yes,locked 2006.145.13:18:26.84/vblo/05,709.99,yes,locked 2006.145.13:18:26.84/vblo/06,719.99,yes,locked 2006.145.13:18:26.84/vblo/07,734.99,yes,locked 2006.145.13:18:26.84/vblo/08,744.99,yes,locked 2006.145.13:18:26.99/vabw/8 2006.145.13:18:27.14/vbbw/8 2006.145.13:18:27.23/xfe/off,on,15.0 2006.145.13:18:27.60/ifatt/23,28,28,28 2006.145.13:18:28.07/fmout-gps/S +5.3E-08 2006.145.13:18:28.12:!2006.145.13:25:04 2006.145.13:25:04.00:data_valid=off 2006.145.13:25:04.01:"et 2006.145.13:25:04.01:!+3s 2006.145.13:25:07.02:"tape 2006.145.13:25:07.03:postob 2006.145.13:25:07.16/cable/+6.5485E-03 2006.145.13:25:07.17/wx/15.29,1020.6,85 2006.145.13:25:07.22/fmout-gps/S +5.1E-08 2006.145.13:25:07.22:scan_name=145-1328,jd0605,310 2006.145.13:25:07.22:source=2201+315,220314.98,314538.3,2000.0,cw 2006.145.13:25:09.13#flagr#flagr/antenna,new-source 2006.145.13:25:09.14:checkk5 2006.145.13:25:09.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.13:25:10.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.13:25:10.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.13:25:10.91/chk_autoobs//k5ts4/ autoobs is running! 2006.145.13:25:11.34/chk_obsdata//k5ts1/T1451318??a.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.145.13:25:11.77/chk_obsdata//k5ts2/T1451318??b.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.145.13:25:12.20/chk_obsdata//k5ts3/T1451318??c.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.145.13:25:12.63/chk_obsdata//k5ts4/T1451318??d.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.145.13:25:13.40/k5log//k5ts1_log_newline 2006.145.13:25:14.14/k5log//k5ts2_log_newline 2006.145.13:25:14.88/k5log//k5ts3_log_newline 2006.145.13:25:15.63/k5log//k5ts4_log_newline 2006.145.13:25:15.66/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.13:25:15.66:setupk4=1 2006.145.13:25:15.66$setupk4/echo=on 2006.145.13:25:15.66$setupk4/pcalon 2006.145.13:25:15.66$pcalon/"no phase cal control is implemented here 2006.145.13:25:15.66$setupk4/"tpicd=stop 2006.145.13:25:15.66$setupk4/"rec=synch_on 2006.145.13:25:15.66$setupk4/"rec_mode=128 2006.145.13:25:15.66$setupk4/!* 2006.145.13:25:15.66$setupk4/recpk4 2006.145.13:25:15.66$recpk4/recpatch= 2006.145.13:25:15.66$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.13:25:15.66$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.13:25:15.67$setupk4/vck44 2006.145.13:25:15.67$vck44/valo=1,524.99 2006.145.13:25:15.67#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.13:25:15.67#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.13:25:15.67#ibcon#ireg 17 cls_cnt 0 2006.145.13:25:15.67#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:25:15.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:25:15.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:25:15.70#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.13:25:15.74#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:25:15.74#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:25:15.74#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.13:25:15.74#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.13:25:15.74$vck44/va=1,8 2006.145.13:25:15.74#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.13:25:15.74#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.13:25:15.74#ibcon#ireg 11 cls_cnt 2 2006.145.13:25:15.74#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.13:25:15.74#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.13:25:15.74#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.13:25:15.76#ibcon#[25=AT01-08\r\n] 2006.145.13:25:15.79#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.13:25:15.79#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.13:25:15.79#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.13:25:15.79#ibcon#ireg 7 cls_cnt 0 2006.145.13:25:15.79#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.13:25:15.92#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.13:25:15.92#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.13:25:15.93#ibcon#[25=USB\r\n] 2006.145.13:25:15.96#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.13:25:15.96#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.13:25:15.96#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.13:25:15.96#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.13:25:15.96$vck44/valo=2,534.99 2006.145.13:25:15.96#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.13:25:15.96#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.13:25:15.96#ibcon#ireg 17 cls_cnt 0 2006.145.13:25:15.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:25:15.96#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:25:15.96#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:25:15.99#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.13:25:16.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:25:16.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:25:16.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.13:25:16.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.13:25:16.03$vck44/va=2,7 2006.145.13:25:16.03#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.13:25:16.03#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.13:25:16.03#ibcon#ireg 11 cls_cnt 2 2006.145.13:25:16.03#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.13:25:16.08#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.13:25:16.08#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.13:25:16.10#ibcon#[25=AT02-07\r\n] 2006.145.13:25:16.13#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.13:25:16.13#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.13:25:16.13#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.13:25:16.13#ibcon#ireg 7 cls_cnt 0 2006.145.13:25:16.13#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.13:25:16.25#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.13:25:16.25#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.13:25:16.27#ibcon#[25=USB\r\n] 2006.145.13:25:16.30#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.13:25:16.30#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.13:25:16.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.13:25:16.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.13:25:16.30$vck44/valo=3,564.99 2006.145.13:25:16.30#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.13:25:16.30#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.13:25:16.30#ibcon#ireg 17 cls_cnt 0 2006.145.13:25:16.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.13:25:16.30#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.13:25:16.30#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.13:25:16.32#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.13:25:16.36#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.13:25:16.36#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.13:25:16.36#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.13:25:16.36#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.13:25:16.36$vck44/va=3,8 2006.145.13:25:16.36#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.13:25:16.36#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.13:25:16.36#ibcon#ireg 11 cls_cnt 2 2006.145.13:25:16.36#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.13:25:16.42#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.13:25:16.42#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.13:25:16.44#ibcon#[25=AT03-08\r\n] 2006.145.13:25:16.47#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.13:25:16.47#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.13:25:16.47#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.13:25:16.47#ibcon#ireg 7 cls_cnt 0 2006.145.13:25:16.47#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.13:25:16.59#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.13:25:16.59#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.13:25:16.61#ibcon#[25=USB\r\n] 2006.145.13:25:16.64#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.13:25:16.64#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.13:25:16.64#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.13:25:16.64#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.13:25:16.64$vck44/valo=4,624.99 2006.145.13:25:16.64#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.13:25:16.64#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.13:25:16.64#ibcon#ireg 17 cls_cnt 0 2006.145.13:25:16.64#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:25:16.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:25:16.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:25:16.66#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.13:25:16.70#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:25:16.70#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:25:16.70#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.13:25:16.70#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.13:25:16.70$vck44/va=4,7 2006.145.13:25:16.70#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.13:25:16.70#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.13:25:16.70#ibcon#ireg 11 cls_cnt 2 2006.145.13:25:16.70#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.13:25:16.76#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.13:25:16.76#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.13:25:16.78#ibcon#[25=AT04-07\r\n] 2006.145.13:25:16.81#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.13:25:16.81#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.13:25:16.81#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.13:25:16.81#ibcon#ireg 7 cls_cnt 0 2006.145.13:25:16.81#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.13:25:16.93#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.13:25:16.93#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.13:25:16.95#ibcon#[25=USB\r\n] 2006.145.13:25:16.98#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.13:25:16.98#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.13:25:16.98#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.13:25:16.98#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.13:25:16.98$vck44/valo=5,734.99 2006.145.13:25:16.98#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.13:25:16.98#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.13:25:16.98#ibcon#ireg 17 cls_cnt 0 2006.145.13:25:16.98#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:25:16.98#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:25:16.98#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:25:17.00#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.13:25:17.04#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:25:17.04#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:25:17.04#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.13:25:17.04#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.13:25:17.04$vck44/va=5,4 2006.145.13:25:17.04#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.13:25:17.04#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.13:25:17.04#ibcon#ireg 11 cls_cnt 2 2006.145.13:25:17.04#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:25:17.10#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:25:17.10#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:25:17.12#ibcon#[25=AT05-04\r\n] 2006.145.13:25:17.15#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:25:17.15#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:25:17.15#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.13:25:17.15#ibcon#ireg 7 cls_cnt 0 2006.145.13:25:17.15#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:25:17.27#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:25:17.27#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:25:17.29#ibcon#[25=USB\r\n] 2006.145.13:25:17.32#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:25:17.32#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:25:17.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.13:25:17.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.13:25:17.32$vck44/valo=6,814.99 2006.145.13:25:17.32#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.13:25:17.32#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.13:25:17.32#ibcon#ireg 17 cls_cnt 0 2006.145.13:25:17.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:25:17.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:25:17.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:25:17.34#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.13:25:17.38#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:25:17.38#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:25:17.38#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.13:25:17.38#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.13:25:17.38$vck44/va=6,4 2006.145.13:25:17.38#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.13:25:17.38#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.13:25:17.38#ibcon#ireg 11 cls_cnt 2 2006.145.13:25:17.38#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:25:17.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:25:17.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:25:17.46#ibcon#[25=AT06-04\r\n] 2006.145.13:25:17.49#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:25:17.49#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:25:17.49#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.13:25:17.49#ibcon#ireg 7 cls_cnt 0 2006.145.13:25:17.49#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:25:17.61#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:25:17.61#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:25:17.63#ibcon#[25=USB\r\n] 2006.145.13:25:17.66#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:25:17.66#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:25:17.66#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.13:25:17.66#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.13:25:17.66$vck44/valo=7,864.99 2006.145.13:25:17.66#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.13:25:17.66#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.13:25:17.66#ibcon#ireg 17 cls_cnt 0 2006.145.13:25:17.66#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:25:17.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:25:17.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:25:17.68#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.13:25:17.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:25:17.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:25:17.72#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.13:25:17.72#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.13:25:17.72$vck44/va=7,4 2006.145.13:25:17.72#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.13:25:17.72#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.13:25:17.72#ibcon#ireg 11 cls_cnt 2 2006.145.13:25:17.72#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:25:17.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:25:17.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:25:17.80#ibcon#[25=AT07-04\r\n] 2006.145.13:25:17.83#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:25:17.83#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:25:17.83#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.13:25:17.83#ibcon#ireg 7 cls_cnt 0 2006.145.13:25:17.83#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:25:17.95#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:25:17.95#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:25:17.97#ibcon#[25=USB\r\n] 2006.145.13:25:18.00#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:25:18.00#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:25:18.00#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.13:25:18.00#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.13:25:18.00$vck44/valo=8,884.99 2006.145.13:25:18.00#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.13:25:18.00#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.13:25:18.00#ibcon#ireg 17 cls_cnt 0 2006.145.13:25:18.00#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:25:18.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:25:18.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:25:18.02#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.13:25:18.06#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:25:18.06#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:25:18.06#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.13:25:18.06#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.13:25:18.06$vck44/va=8,4 2006.145.13:25:18.06#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.13:25:18.06#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.13:25:18.06#ibcon#ireg 11 cls_cnt 2 2006.145.13:25:18.06#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.13:25:18.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.13:25:18.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.13:25:18.14#ibcon#[25=AT08-04\r\n] 2006.145.13:25:18.17#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.13:25:18.17#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.13:25:18.17#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.13:25:18.17#ibcon#ireg 7 cls_cnt 0 2006.145.13:25:18.17#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.13:25:18.29#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.13:25:18.29#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.13:25:18.31#ibcon#[25=USB\r\n] 2006.145.13:25:18.34#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.13:25:18.34#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.13:25:18.34#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.13:25:18.34#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.13:25:18.34$vck44/vblo=1,629.99 2006.145.13:25:18.34#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.13:25:18.34#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.13:25:18.34#ibcon#ireg 17 cls_cnt 0 2006.145.13:25:18.34#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.13:25:18.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.13:25:18.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.13:25:18.36#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.13:25:18.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.13:25:18.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.13:25:18.40#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.13:25:18.40#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.13:25:18.40$vck44/vb=1,3 2006.145.13:25:18.40#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.13:25:18.40#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.13:25:18.40#ibcon#ireg 11 cls_cnt 2 2006.145.13:25:18.40#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.13:25:18.40#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.13:25:18.40#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.13:25:18.42#ibcon#[27=AT01-03\r\n] 2006.145.13:25:18.45#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.13:25:18.45#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.13:25:18.45#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.13:25:18.45#ibcon#ireg 7 cls_cnt 0 2006.145.13:25:18.45#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.13:25:18.57#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.13:25:18.57#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.13:25:18.59#ibcon#[27=USB\r\n] 2006.145.13:25:18.62#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.13:25:18.62#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.13:25:18.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.13:25:18.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.13:25:18.62$vck44/vblo=2,634.99 2006.145.13:25:18.62#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.13:25:18.62#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.13:25:18.62#ibcon#ireg 17 cls_cnt 0 2006.145.13:25:18.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:25:18.62#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:25:18.62#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:25:18.64#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.13:25:18.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:25:18.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:25:18.68#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.13:25:18.68#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.13:25:18.68$vck44/vb=2,4 2006.145.13:25:18.68#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.13:25:18.68#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.13:25:18.68#ibcon#ireg 11 cls_cnt 2 2006.145.13:25:18.68#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.13:25:18.74#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.13:25:18.74#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.13:25:18.76#ibcon#[27=AT02-04\r\n] 2006.145.13:25:18.79#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.13:25:18.79#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.13:25:18.79#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.13:25:18.79#ibcon#ireg 7 cls_cnt 0 2006.145.13:25:18.79#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.13:25:18.91#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.13:25:18.91#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.13:25:18.93#ibcon#[27=USB\r\n] 2006.145.13:25:18.96#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.13:25:18.96#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.13:25:18.96#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.13:25:18.96#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.13:25:18.96$vck44/vblo=3,649.99 2006.145.13:25:18.96#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.13:25:18.96#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.13:25:18.96#ibcon#ireg 17 cls_cnt 0 2006.145.13:25:18.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:25:18.96#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:25:18.96#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:25:18.98#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.13:25:19.02#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:25:19.02#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:25:19.02#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.13:25:19.02#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.13:25:19.02$vck44/vb=3,4 2006.145.13:25:19.02#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.13:25:19.02#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.13:25:19.02#ibcon#ireg 11 cls_cnt 2 2006.145.13:25:19.02#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.13:25:19.08#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.13:25:19.08#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.13:25:19.10#ibcon#[27=AT03-04\r\n] 2006.145.13:25:19.13#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.13:25:19.13#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.13:25:19.13#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.13:25:19.13#ibcon#ireg 7 cls_cnt 0 2006.145.13:25:19.13#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.13:25:19.25#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.13:25:19.25#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.13:25:19.27#ibcon#[27=USB\r\n] 2006.145.13:25:19.30#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.13:25:19.30#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.13:25:19.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.13:25:19.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.13:25:19.30$vck44/vblo=4,679.99 2006.145.13:25:19.30#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.13:25:19.30#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.13:25:19.30#ibcon#ireg 17 cls_cnt 0 2006.145.13:25:19.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.13:25:19.30#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.13:25:19.30#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.13:25:19.32#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.13:25:19.36#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.13:25:19.36#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.13:25:19.36#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.13:25:19.36#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.13:25:19.36$vck44/vb=4,4 2006.145.13:25:19.36#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.13:25:19.36#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.13:25:19.36#ibcon#ireg 11 cls_cnt 2 2006.145.13:25:19.36#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.13:25:19.42#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.13:25:19.42#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.13:25:19.44#ibcon#[27=AT04-04\r\n] 2006.145.13:25:19.47#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.13:25:19.47#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.13:25:19.47#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.13:25:19.47#ibcon#ireg 7 cls_cnt 0 2006.145.13:25:19.47#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.13:25:19.59#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.13:25:19.59#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.13:25:19.61#ibcon#[27=USB\r\n] 2006.145.13:25:19.64#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.13:25:19.64#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.13:25:19.64#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.13:25:19.64#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.13:25:19.64$vck44/vblo=5,709.99 2006.145.13:25:19.64#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.13:25:19.64#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.13:25:19.64#ibcon#ireg 17 cls_cnt 0 2006.145.13:25:19.64#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:25:19.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:25:19.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:25:19.66#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.13:25:19.70#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:25:19.70#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:25:19.70#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.13:25:19.70#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.13:25:19.70$vck44/vb=5,4 2006.145.13:25:19.70#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.13:25:19.70#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.13:25:19.70#ibcon#ireg 11 cls_cnt 2 2006.145.13:25:19.70#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.13:25:19.76#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.13:25:19.76#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.13:25:19.78#ibcon#[27=AT05-04\r\n] 2006.145.13:25:19.81#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.13:25:19.81#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.13:25:19.81#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.13:25:19.81#ibcon#ireg 7 cls_cnt 0 2006.145.13:25:19.81#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.13:25:19.93#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.13:25:19.93#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.13:25:19.95#ibcon#[27=USB\r\n] 2006.145.13:25:19.98#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.13:25:19.98#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.13:25:19.98#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.13:25:19.98#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.13:25:19.98$vck44/vblo=6,719.99 2006.145.13:25:19.98#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.13:25:19.98#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.13:25:19.98#ibcon#ireg 17 cls_cnt 0 2006.145.13:25:19.98#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:25:19.98#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:25:19.98#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:25:20.00#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.13:25:20.04#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:25:20.04#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:25:20.04#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.13:25:20.04#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.13:25:20.04$vck44/vb=6,4 2006.145.13:25:20.04#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.13:25:20.04#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.13:25:20.04#ibcon#ireg 11 cls_cnt 2 2006.145.13:25:20.04#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:25:20.10#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:25:20.10#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:25:20.12#ibcon#[27=AT06-04\r\n] 2006.145.13:25:20.15#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:25:20.15#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:25:20.15#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.13:25:20.15#ibcon#ireg 7 cls_cnt 0 2006.145.13:25:20.15#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:25:20.27#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:25:20.27#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:25:20.29#ibcon#[27=USB\r\n] 2006.145.13:25:20.32#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:25:20.32#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:25:20.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.13:25:20.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.13:25:20.32$vck44/vblo=7,734.99 2006.145.13:25:20.32#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.13:25:20.32#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.13:25:20.32#ibcon#ireg 17 cls_cnt 0 2006.145.13:25:20.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:25:20.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:25:20.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:25:20.34#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.13:25:20.38#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:25:20.38#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:25:20.38#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.13:25:20.38#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.13:25:20.38$vck44/vb=7,4 2006.145.13:25:20.38#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.13:25:20.38#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.13:25:20.38#ibcon#ireg 11 cls_cnt 2 2006.145.13:25:20.38#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:25:20.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:25:20.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:25:20.46#ibcon#[27=AT07-04\r\n] 2006.145.13:25:20.49#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:25:20.49#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:25:20.49#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.13:25:20.49#ibcon#ireg 7 cls_cnt 0 2006.145.13:25:20.49#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:25:20.61#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:25:20.61#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:25:20.63#ibcon#[27=USB\r\n] 2006.145.13:25:20.66#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:25:20.66#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:25:20.66#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.13:25:20.66#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.13:25:20.66$vck44/vblo=8,744.99 2006.145.13:25:20.66#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.13:25:20.66#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.13:25:20.66#ibcon#ireg 17 cls_cnt 0 2006.145.13:25:20.66#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:25:20.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:25:20.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:25:20.68#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.13:25:20.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:25:20.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:25:20.72#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.13:25:20.72#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.13:25:20.72$vck44/vb=8,4 2006.145.13:25:20.72#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.13:25:20.72#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.13:25:20.72#ibcon#ireg 11 cls_cnt 2 2006.145.13:25:20.72#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:25:20.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:25:20.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:25:20.80#ibcon#[27=AT08-04\r\n] 2006.145.13:25:20.83#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:25:20.83#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:25:20.83#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.13:25:20.83#ibcon#ireg 7 cls_cnt 0 2006.145.13:25:20.83#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:25:20.95#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:25:20.95#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:25:20.97#ibcon#[27=USB\r\n] 2006.145.13:25:21.00#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:25:21.00#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:25:21.00#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.13:25:21.00#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.13:25:21.00$vck44/vabw=wide 2006.145.13:25:21.00#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.13:25:21.00#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.13:25:21.00#ibcon#ireg 8 cls_cnt 0 2006.145.13:25:21.00#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:25:21.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:25:21.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:25:21.02#ibcon#[25=BW32\r\n] 2006.145.13:25:21.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:25:21.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:25:21.05#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.13:25:21.05#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.13:25:21.05$vck44/vbbw=wide 2006.145.13:25:21.05#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.13:25:21.05#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.13:25:21.05#ibcon#ireg 8 cls_cnt 0 2006.145.13:25:21.05#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:25:21.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:25:21.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:25:21.14#ibcon#[27=BW32\r\n] 2006.145.13:25:21.17#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:25:21.17#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:25:21.17#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.13:25:21.17#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.13:25:21.17$setupk4/ifdk4 2006.145.13:25:21.17$ifdk4/lo= 2006.145.13:25:21.17$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.13:25:21.17$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.13:25:21.17$ifdk4/patch= 2006.145.13:25:21.17$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.13:25:21.17$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.13:25:21.17$setupk4/!*+20s 2006.145.13:25:24.93#abcon#<5=/06 0.7 1.9 15.29 851020.6\r\n> 2006.145.13:25:24.95#abcon#{5=INTERFACE CLEAR} 2006.145.13:25:25.01#abcon#[5=S1D000X0/0*\r\n] 2006.145.13:25:35.10#abcon#<5=/06 0.7 1.9 15.28 851020.6\r\n> 2006.145.13:25:35.12#abcon#{5=INTERFACE CLEAR} 2006.145.13:25:35.18#abcon#[5=S1D000X0/0*\r\n] 2006.145.13:25:35.67$setupk4/"tpicd 2006.145.13:25:35.67$setupk4/echo=off 2006.145.13:25:35.67$setupk4/xlog=off 2006.145.13:25:35.67:!2006.145.13:28:20 2006.145.13:26:26.14#trakl#Source acquired 2006.145.13:26:28.14#flagr#flagr/antenna,acquired 2006.145.13:28:20.00:preob 2006.145.13:28:20.14/onsource/TRACKING 2006.145.13:28:20.14:!2006.145.13:28:30 2006.145.13:28:30.00:"tape 2006.145.13:28:30.00:"st=record 2006.145.13:28:30.00:data_valid=on 2006.145.13:28:30.00:midob 2006.145.13:28:31.14/onsource/TRACKING 2006.145.13:28:31.14/wx/15.24,1020.7,85 2006.145.13:28:31.25/cable/+6.5464E-03 2006.145.13:28:32.34/va/01,08,usb,yes,35,37 2006.145.13:28:32.34/va/02,07,usb,yes,37,38 2006.145.13:28:32.34/va/03,08,usb,yes,34,36 2006.145.13:28:32.34/va/04,07,usb,yes,39,41 2006.145.13:28:32.34/va/05,04,usb,yes,34,35 2006.145.13:28:32.34/va/06,04,usb,yes,38,38 2006.145.13:28:32.34/va/07,04,usb,yes,38,40 2006.145.13:28:32.34/va/08,04,usb,yes,33,39 2006.145.13:28:32.57/valo/01,524.99,yes,locked 2006.145.13:28:32.57/valo/02,534.99,yes,locked 2006.145.13:28:32.57/valo/03,564.99,yes,locked 2006.145.13:28:32.57/valo/04,624.99,yes,locked 2006.145.13:28:32.57/valo/05,734.99,yes,locked 2006.145.13:28:32.57/valo/06,814.99,yes,locked 2006.145.13:28:32.57/valo/07,864.99,yes,locked 2006.145.13:28:32.57/valo/08,884.99,yes,locked 2006.145.13:28:33.66/vb/01,03,usb,yes,40,38 2006.145.13:28:33.66/vb/02,04,usb,yes,35,35 2006.145.13:28:33.66/vb/03,04,usb,yes,32,36 2006.145.13:28:33.66/vb/04,04,usb,yes,37,36 2006.145.13:28:33.66/vb/05,04,usb,yes,29,32 2006.145.13:28:33.66/vb/06,04,usb,yes,34,30 2006.145.13:28:33.66/vb/07,04,usb,yes,34,33 2006.145.13:28:33.66/vb/08,04,usb,yes,31,35 2006.145.13:28:33.89/vblo/01,629.99,yes,locked 2006.145.13:28:33.89/vblo/02,634.99,yes,locked 2006.145.13:28:33.89/vblo/03,649.99,yes,locked 2006.145.13:28:33.89/vblo/04,679.99,yes,locked 2006.145.13:28:33.89/vblo/05,709.99,yes,locked 2006.145.13:28:33.89/vblo/06,719.99,yes,locked 2006.145.13:28:33.89/vblo/07,734.99,yes,locked 2006.145.13:28:33.89/vblo/08,744.99,yes,locked 2006.145.13:28:34.04/vabw/8 2006.145.13:28:34.19/vbbw/8 2006.145.13:28:34.28/xfe/off,on,15.2 2006.145.13:28:34.65/ifatt/23,28,28,28 2006.145.13:28:35.07/fmout-gps/S +5.0E-08 2006.145.13:28:35.11:!2006.145.13:33:40 2006.145.13:33:40.00:data_valid=off 2006.145.13:33:40.00:"et 2006.145.13:33:40.01:!+3s 2006.145.13:33:43.02:"tape 2006.145.13:33:43.02:postob 2006.145.13:33:43.12/cable/+6.5460E-03 2006.145.13:33:43.12/wx/15.10,1020.7,86 2006.145.13:33:43.20/fmout-gps/S +4.8E-08 2006.145.13:33:43.20:scan_name=145-1334,jd0605,40 2006.145.13:33:43.20:source=1908-201,191109.65,-200655.1,2000.0,cw 2006.145.13:33:45.13#flagr#flagr/antenna,new-source 2006.145.13:33:45.13:checkk5 2006.145.13:33:45.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.13:33:46.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.13:33:46.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.13:33:46.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.13:33:47.31/chk_obsdata//k5ts1/T1451328??a.dat file size is correct (nominal:1240MB, actual:1240MB). 2006.145.13:33:47.77/chk_obsdata//k5ts2/T1451328??b.dat file size is correct (nominal:1240MB, actual:1240MB). 2006.145.13:33:48.22/chk_obsdata//k5ts3/T1451328??c.dat file size is correct (nominal:1240MB, actual:1240MB). 2006.145.13:33:48.65/chk_obsdata//k5ts4/T1451328??d.dat file size is correct (nominal:1240MB, actual:1240MB). 2006.145.13:33:49.40/k5log//k5ts1_log_newline 2006.145.13:33:50.14/k5log//k5ts2_log_newline 2006.145.13:33:50.88/k5log//k5ts3_log_newline 2006.145.13:33:51.63/k5log//k5ts4_log_newline 2006.145.13:33:51.66/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.13:33:51.66:setupk4=1 2006.145.13:33:51.66$setupk4/echo=on 2006.145.13:33:51.66$setupk4/pcalon 2006.145.13:33:51.66$pcalon/"no phase cal control is implemented here 2006.145.13:33:51.66$setupk4/"tpicd=stop 2006.145.13:33:51.66$setupk4/"rec=synch_on 2006.145.13:33:51.66$setupk4/"rec_mode=128 2006.145.13:33:51.66$setupk4/!* 2006.145.13:33:51.66$setupk4/recpk4 2006.145.13:33:51.66$recpk4/recpatch= 2006.145.13:33:51.66$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.13:33:51.66$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.13:33:51.66$setupk4/vck44 2006.145.13:33:51.66$vck44/valo=1,524.99 2006.145.13:33:51.66#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.13:33:51.66#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.13:33:51.66#ibcon#ireg 17 cls_cnt 0 2006.145.13:33:51.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.13:33:51.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.13:33:51.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.13:33:51.70#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.13:33:51.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.13:33:51.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.13:33:51.75#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.13:33:51.75#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.13:33:51.75$vck44/va=1,8 2006.145.13:33:51.75#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.13:33:51.75#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.13:33:51.75#ibcon#ireg 11 cls_cnt 2 2006.145.13:33:51.75#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.13:33:51.75#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.13:33:51.75#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.13:33:51.77#ibcon#[25=AT01-08\r\n] 2006.145.13:33:51.80#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.13:33:51.80#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.13:33:51.80#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.13:33:51.80#ibcon#ireg 7 cls_cnt 0 2006.145.13:33:51.80#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.13:33:51.92#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.13:33:51.92#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.13:33:51.94#ibcon#[25=USB\r\n] 2006.145.13:33:51.99#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.13:33:51.99#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.13:33:51.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.13:33:51.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.13:33:51.99$vck44/valo=2,534.99 2006.145.13:33:51.99#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.13:33:51.99#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.13:33:51.99#ibcon#ireg 17 cls_cnt 0 2006.145.13:33:51.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.13:33:51.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.13:33:51.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.13:33:52.00#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.13:33:52.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.13:33:52.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.13:33:52.04#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.13:33:52.04#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.13:33:52.04$vck44/va=2,7 2006.145.13:33:52.04#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.13:33:52.04#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.13:33:52.04#ibcon#ireg 11 cls_cnt 2 2006.145.13:33:52.04#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.13:33:52.11#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.13:33:52.11#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.13:33:52.13#ibcon#[25=AT02-07\r\n] 2006.145.13:33:52.16#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.13:33:52.16#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.13:33:52.16#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.13:33:52.16#ibcon#ireg 7 cls_cnt 0 2006.145.13:33:52.16#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.13:33:52.28#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.13:33:52.28#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.13:33:52.30#ibcon#[25=USB\r\n] 2006.145.13:33:52.33#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.13:33:52.33#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.13:33:52.33#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.13:33:52.33#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.13:33:52.33$vck44/valo=3,564.99 2006.145.13:33:52.33#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.13:33:52.33#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.13:33:52.33#ibcon#ireg 17 cls_cnt 0 2006.145.13:33:52.33#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.13:33:52.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.13:33:52.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.13:33:52.35#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.13:33:52.39#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.13:33:52.39#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.13:33:52.39#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.13:33:52.39#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.13:33:52.39$vck44/va=3,8 2006.145.13:33:52.39#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.13:33:52.39#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.13:33:52.39#ibcon#ireg 11 cls_cnt 2 2006.145.13:33:52.39#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.13:33:52.45#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.13:33:52.45#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.13:33:52.47#ibcon#[25=AT03-08\r\n] 2006.145.13:33:52.50#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.13:33:52.50#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.13:33:52.50#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.13:33:52.50#ibcon#ireg 7 cls_cnt 0 2006.145.13:33:52.50#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.13:33:52.62#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.13:33:52.62#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.13:33:52.64#ibcon#[25=USB\r\n] 2006.145.13:33:52.67#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.13:33:52.67#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.13:33:52.67#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.13:33:52.67#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.13:33:52.67$vck44/valo=4,624.99 2006.145.13:33:52.67#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.13:33:52.67#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.13:33:52.67#ibcon#ireg 17 cls_cnt 0 2006.145.13:33:52.67#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.13:33:52.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.13:33:52.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.13:33:52.69#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.13:33:52.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.13:33:52.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.13:33:52.73#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.13:33:52.73#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.13:33:52.73$vck44/va=4,7 2006.145.13:33:52.73#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.13:33:52.73#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.13:33:52.73#ibcon#ireg 11 cls_cnt 2 2006.145.13:33:52.73#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.13:33:52.79#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.13:33:52.79#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.13:33:52.81#ibcon#[25=AT04-07\r\n] 2006.145.13:33:52.84#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.13:33:52.84#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.13:33:52.84#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.13:33:52.84#ibcon#ireg 7 cls_cnt 0 2006.145.13:33:52.84#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.13:33:52.96#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.13:33:52.96#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.13:33:52.98#ibcon#[25=USB\r\n] 2006.145.13:33:53.01#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.13:33:53.01#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.13:33:53.01#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.13:33:53.01#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.13:33:53.01$vck44/valo=5,734.99 2006.145.13:33:53.01#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.13:33:53.01#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.13:33:53.01#ibcon#ireg 17 cls_cnt 0 2006.145.13:33:53.01#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.13:33:53.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.13:33:53.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.13:33:53.03#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.13:33:53.07#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.13:33:53.07#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.13:33:53.07#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.13:33:53.07#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.13:33:53.07$vck44/va=5,4 2006.145.13:33:53.07#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.13:33:53.07#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.13:33:53.07#ibcon#ireg 11 cls_cnt 2 2006.145.13:33:53.07#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.13:33:53.13#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.13:33:53.13#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.13:33:53.16#ibcon#[25=AT05-04\r\n] 2006.145.13:33:53.19#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.13:33:53.19#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.13:33:53.19#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.13:33:53.19#ibcon#ireg 7 cls_cnt 0 2006.145.13:33:53.19#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.13:33:53.31#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.13:33:53.31#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.13:33:53.33#ibcon#[25=USB\r\n] 2006.145.13:33:53.36#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.13:33:53.36#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.13:33:53.36#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.13:33:53.36#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.13:33:53.36$vck44/valo=6,814.99 2006.145.13:33:53.36#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.13:33:53.36#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.13:33:53.36#ibcon#ireg 17 cls_cnt 0 2006.145.13:33:53.36#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.13:33:53.36#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.13:33:53.36#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.13:33:53.38#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.13:33:53.42#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.13:33:53.42#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.13:33:53.42#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.13:33:53.42#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.13:33:53.42$vck44/va=6,4 2006.145.13:33:53.42#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.13:33:53.42#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.13:33:53.42#ibcon#ireg 11 cls_cnt 2 2006.145.13:33:53.42#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.13:33:53.48#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.13:33:53.48#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.13:33:53.50#ibcon#[25=AT06-04\r\n] 2006.145.13:33:53.53#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.13:33:53.53#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.13:33:53.53#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.13:33:53.53#ibcon#ireg 7 cls_cnt 0 2006.145.13:33:53.53#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.13:33:53.65#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.13:33:53.65#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.13:33:53.67#ibcon#[25=USB\r\n] 2006.145.13:33:53.70#abcon#<5=/07 0.4 0.9 15.08 861020.7\r\n> 2006.145.13:33:53.70#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.13:33:53.70#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.13:33:53.70#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.13:33:53.70#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.13:33:53.70$vck44/valo=7,864.99 2006.145.13:33:53.70#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.13:33:53.70#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.13:33:53.70#ibcon#ireg 17 cls_cnt 0 2006.145.13:33:53.70#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:33:53.70#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:33:53.70#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:33:53.72#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.13:33:53.72#abcon#{5=INTERFACE CLEAR} 2006.145.13:33:53.76#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:33:53.76#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:33:53.76#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.13:33:53.76#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.13:33:53.76$vck44/va=7,4 2006.145.13:33:53.76#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.13:33:53.76#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.13:33:53.76#ibcon#ireg 11 cls_cnt 2 2006.145.13:33:53.76#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.13:33:53.78#abcon#[5=S1D000X0/0*\r\n] 2006.145.13:33:53.82#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.13:33:53.82#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.13:33:53.84#ibcon#[25=AT07-04\r\n] 2006.145.13:33:53.87#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.13:33:53.87#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.13:33:53.87#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.13:33:53.87#ibcon#ireg 7 cls_cnt 0 2006.145.13:33:53.87#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.13:33:53.99#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.13:33:53.99#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.13:33:54.01#ibcon#[25=USB\r\n] 2006.145.13:33:54.04#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.13:33:54.04#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.13:33:54.04#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.13:33:54.04#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.13:33:54.04$vck44/valo=8,884.99 2006.145.13:33:54.04#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.13:33:54.04#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.13:33:54.04#ibcon#ireg 17 cls_cnt 0 2006.145.13:33:54.04#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.13:33:54.04#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.13:33:54.04#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.13:33:54.06#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.13:33:54.10#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.13:33:54.10#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.13:33:54.10#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.13:33:54.10#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.13:33:54.10$vck44/va=8,4 2006.145.13:33:54.10#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.13:33:54.10#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.13:33:54.10#ibcon#ireg 11 cls_cnt 2 2006.145.13:33:54.10#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.13:33:54.16#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.13:33:54.16#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.13:33:54.18#ibcon#[25=AT08-04\r\n] 2006.145.13:33:54.21#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.13:33:54.21#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.13:33:54.21#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.13:33:54.21#ibcon#ireg 7 cls_cnt 0 2006.145.13:33:54.21#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.13:33:54.33#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.13:33:54.33#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.13:33:54.35#ibcon#[25=USB\r\n] 2006.145.13:33:54.38#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.13:33:54.38#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.13:33:54.38#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.13:33:54.38#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.13:33:54.38$vck44/vblo=1,629.99 2006.145.13:33:54.38#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.13:33:54.38#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.13:33:54.38#ibcon#ireg 17 cls_cnt 0 2006.145.13:33:54.38#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.13:33:54.38#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.13:33:54.38#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.13:33:54.40#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.13:33:54.44#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.13:33:54.44#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.13:33:54.44#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.13:33:54.44#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.13:33:54.44$vck44/vb=1,3 2006.145.13:33:54.44#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.13:33:54.44#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.13:33:54.44#ibcon#ireg 11 cls_cnt 2 2006.145.13:33:54.44#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.13:33:54.44#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.13:33:54.44#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.13:33:54.46#ibcon#[27=AT01-03\r\n] 2006.145.13:33:54.49#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.13:33:54.49#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.13:33:54.49#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.13:33:54.49#ibcon#ireg 7 cls_cnt 0 2006.145.13:33:54.49#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.13:33:54.61#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.13:33:54.61#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.13:33:54.63#ibcon#[27=USB\r\n] 2006.145.13:33:54.66#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.13:33:54.66#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.13:33:54.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.13:33:54.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.13:33:54.66$vck44/vblo=2,634.99 2006.145.13:33:54.66#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.13:33:54.66#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.13:33:54.66#ibcon#ireg 17 cls_cnt 0 2006.145.13:33:54.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.13:33:54.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.13:33:54.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.13:33:54.68#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.13:33:54.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.13:33:54.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.13:33:54.72#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.13:33:54.72#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.13:33:54.72$vck44/vb=2,4 2006.145.13:33:54.72#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.13:33:54.72#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.13:33:54.72#ibcon#ireg 11 cls_cnt 2 2006.145.13:33:54.72#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.13:33:54.78#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.13:33:54.78#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.13:33:54.80#ibcon#[27=AT02-04\r\n] 2006.145.13:33:54.83#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.13:33:54.83#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.13:33:54.83#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.13:33:54.83#ibcon#ireg 7 cls_cnt 0 2006.145.13:33:54.83#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.13:33:54.95#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.13:33:54.95#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.13:33:54.97#ibcon#[27=USB\r\n] 2006.145.13:33:55.00#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.13:33:55.00#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.13:33:55.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.13:33:55.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.13:33:55.00$vck44/vblo=3,649.99 2006.145.13:33:55.00#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.13:33:55.00#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.13:33:55.00#ibcon#ireg 17 cls_cnt 0 2006.145.13:33:55.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.13:33:55.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.13:33:55.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.13:33:55.02#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.13:33:55.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.13:33:55.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.13:33:55.06#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.13:33:55.06#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.13:33:55.06$vck44/vb=3,4 2006.145.13:33:55.06#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.13:33:55.06#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.13:33:55.06#ibcon#ireg 11 cls_cnt 2 2006.145.13:33:55.06#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.13:33:55.12#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.13:33:55.12#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.13:33:55.14#ibcon#[27=AT03-04\r\n] 2006.145.13:33:55.17#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.13:33:55.17#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.13:33:55.17#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.13:33:55.17#ibcon#ireg 7 cls_cnt 0 2006.145.13:33:55.17#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.13:33:55.29#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.13:33:55.29#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.13:33:55.31#ibcon#[27=USB\r\n] 2006.145.13:33:55.34#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.13:33:55.34#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.13:33:55.34#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.13:33:55.34#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.13:33:55.34$vck44/vblo=4,679.99 2006.145.13:33:55.34#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.13:33:55.34#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.13:33:55.34#ibcon#ireg 17 cls_cnt 0 2006.145.13:33:55.34#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.13:33:55.34#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.13:33:55.34#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.13:33:55.36#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.13:33:55.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.13:33:55.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.13:33:55.40#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.13:33:55.40#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.13:33:55.40$vck44/vb=4,4 2006.145.13:33:55.40#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.13:33:55.40#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.13:33:55.40#ibcon#ireg 11 cls_cnt 2 2006.145.13:33:55.40#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.13:33:55.46#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.13:33:55.46#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.13:33:55.48#ibcon#[27=AT04-04\r\n] 2006.145.13:33:55.51#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.13:33:55.51#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.13:33:55.51#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.13:33:55.51#ibcon#ireg 7 cls_cnt 0 2006.145.13:33:55.51#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.13:33:55.63#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.13:33:55.63#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.13:33:55.65#ibcon#[27=USB\r\n] 2006.145.13:33:55.68#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.13:33:55.68#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.13:33:55.68#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.13:33:55.68#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.13:33:55.68$vck44/vblo=5,709.99 2006.145.13:33:55.68#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.13:33:55.68#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.13:33:55.68#ibcon#ireg 17 cls_cnt 0 2006.145.13:33:55.68#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.13:33:55.68#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.13:33:55.68#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.13:33:55.70#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.13:33:55.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.13:33:55.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.13:33:55.74#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.13:33:55.74#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.13:33:55.74$vck44/vb=5,4 2006.145.13:33:55.74#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.13:33:55.74#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.13:33:55.74#ibcon#ireg 11 cls_cnt 2 2006.145.13:33:55.74#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.13:33:55.80#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.13:33:55.80#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.13:33:55.82#ibcon#[27=AT05-04\r\n] 2006.145.13:33:55.85#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.13:33:55.85#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.13:33:55.85#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.13:33:55.85#ibcon#ireg 7 cls_cnt 0 2006.145.13:33:55.85#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.13:33:55.97#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.13:33:55.97#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.13:33:55.99#ibcon#[27=USB\r\n] 2006.145.13:33:56.02#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.13:33:56.02#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.13:33:56.02#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.13:33:56.02#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.13:33:56.02$vck44/vblo=6,719.99 2006.145.13:33:56.02#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.13:33:56.02#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.13:33:56.02#ibcon#ireg 17 cls_cnt 0 2006.145.13:33:56.02#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.13:33:56.02#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.13:33:56.02#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.13:33:56.04#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.13:33:56.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.13:33:56.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.13:33:56.08#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.13:33:56.08#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.13:33:56.08$vck44/vb=6,4 2006.145.13:33:56.08#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.13:33:56.08#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.13:33:56.08#ibcon#ireg 11 cls_cnt 2 2006.145.13:33:56.08#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.13:33:56.14#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.13:33:56.14#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.13:33:56.16#ibcon#[27=AT06-04\r\n] 2006.145.13:33:56.19#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.13:33:56.19#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.13:33:56.19#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.13:33:56.19#ibcon#ireg 7 cls_cnt 0 2006.145.13:33:56.19#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.13:33:56.31#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.13:33:56.31#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.13:33:56.33#ibcon#[27=USB\r\n] 2006.145.13:33:56.36#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.13:33:56.36#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.13:33:56.36#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.13:33:56.36#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.13:33:56.36$vck44/vblo=7,734.99 2006.145.13:33:56.36#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.13:33:56.36#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.13:33:56.36#ibcon#ireg 17 cls_cnt 0 2006.145.13:33:56.36#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.13:33:56.36#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.13:33:56.36#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.13:33:56.38#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.13:33:56.42#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.13:33:56.42#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.13:33:56.42#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.13:33:56.42#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.13:33:56.42$vck44/vb=7,4 2006.145.13:33:56.42#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.13:33:56.42#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.13:33:56.42#ibcon#ireg 11 cls_cnt 2 2006.145.13:33:56.42#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.13:33:56.48#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.13:33:56.48#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.13:33:56.50#ibcon#[27=AT07-04\r\n] 2006.145.13:33:56.53#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.13:33:56.53#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.13:33:56.53#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.13:33:56.53#ibcon#ireg 7 cls_cnt 0 2006.145.13:33:56.53#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.13:33:56.65#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.13:33:56.65#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.13:33:56.67#ibcon#[27=USB\r\n] 2006.145.13:33:56.70#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.13:33:56.70#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.13:33:56.70#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.13:33:56.70#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.13:33:56.70$vck44/vblo=8,744.99 2006.145.13:33:56.70#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.13:33:56.70#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.13:33:56.70#ibcon#ireg 17 cls_cnt 0 2006.145.13:33:56.70#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.13:33:56.70#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.13:33:56.70#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.13:33:56.72#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.13:33:56.76#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.13:33:56.76#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.13:33:56.76#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.13:33:56.76#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.13:33:56.76$vck44/vb=8,4 2006.145.13:33:56.76#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.13:33:56.76#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.13:33:56.76#ibcon#ireg 11 cls_cnt 2 2006.145.13:33:56.76#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.13:33:56.82#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.13:33:56.82#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.13:33:56.84#ibcon#[27=AT08-04\r\n] 2006.145.13:33:56.87#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.13:33:56.87#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.13:33:56.87#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.13:33:56.87#ibcon#ireg 7 cls_cnt 0 2006.145.13:33:56.87#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.13:33:56.99#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.13:33:56.99#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.13:33:57.01#ibcon#[27=USB\r\n] 2006.145.13:33:57.04#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.13:33:57.04#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.13:33:57.04#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.13:33:57.04#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.13:33:57.04$vck44/vabw=wide 2006.145.13:33:57.04#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.13:33:57.04#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.13:33:57.04#ibcon#ireg 8 cls_cnt 0 2006.145.13:33:57.04#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.13:33:57.04#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.13:33:57.04#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.13:33:57.06#ibcon#[25=BW32\r\n] 2006.145.13:33:57.09#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.13:33:57.09#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.13:33:57.09#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.13:33:57.09#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.13:33:57.09$vck44/vbbw=wide 2006.145.13:33:57.09#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.13:33:57.09#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.13:33:57.09#ibcon#ireg 8 cls_cnt 0 2006.145.13:33:57.09#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.13:33:57.16#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.13:33:57.16#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.13:33:57.18#ibcon#[27=BW32\r\n] 2006.145.13:33:57.21#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.13:33:57.21#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.13:33:57.21#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.13:33:57.21#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.13:33:57.21$setupk4/ifdk4 2006.145.13:33:57.21$ifdk4/lo= 2006.145.13:33:57.21$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.13:33:57.21$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.13:33:57.21$ifdk4/patch= 2006.145.13:33:57.21$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.13:33:57.21$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.13:33:57.21$setupk4/!*+20s 2006.145.13:34:03.87#abcon#<5=/07 0.4 0.9 15.07 861020.7\r\n> 2006.145.13:34:03.89#abcon#{5=INTERFACE CLEAR} 2006.145.13:34:03.97#abcon#[5=S1D000X0/0*\r\n] 2006.145.13:34:11.67$setupk4/"tpicd 2006.145.13:34:11.67$setupk4/echo=off 2006.145.13:34:11.67$setupk4/xlog=off 2006.145.13:34:11.67:!2006.145.13:34:17 2006.145.13:34:15.13#trakl#Source acquired 2006.145.13:34:16.13#flagr#flagr/antenna,acquired 2006.145.13:34:17.00:preob 2006.145.13:34:17.13/onsource/TRACKING 2006.145.13:34:17.13:!2006.145.13:34:27 2006.145.13:34:27.00:"tape 2006.145.13:34:27.00:"st=record 2006.145.13:34:27.00:data_valid=on 2006.145.13:34:27.00:midob 2006.145.13:34:28.13/onsource/TRACKING 2006.145.13:34:28.13/wx/15.05,1020.7,86 2006.145.13:34:28.21/cable/+6.5498E-03 2006.145.13:34:29.30/va/01,08,usb,yes,33,35 2006.145.13:34:29.30/va/02,07,usb,yes,35,36 2006.145.13:34:29.30/va/03,08,usb,yes,32,34 2006.145.13:34:29.30/va/04,07,usb,yes,37,39 2006.145.13:34:29.30/va/05,04,usb,yes,32,33 2006.145.13:34:29.30/va/06,04,usb,yes,36,36 2006.145.13:34:29.30/va/07,04,usb,yes,36,38 2006.145.13:34:29.30/va/08,04,usb,yes,31,37 2006.145.13:34:29.53/valo/01,524.99,yes,locked 2006.145.13:34:29.53/valo/02,534.99,yes,locked 2006.145.13:34:29.53/valo/03,564.99,yes,locked 2006.145.13:34:29.53/valo/04,624.99,yes,locked 2006.145.13:34:29.53/valo/05,734.99,yes,locked 2006.145.13:34:29.53/valo/06,814.99,yes,locked 2006.145.13:34:29.53/valo/07,864.99,yes,locked 2006.145.13:34:29.53/valo/08,884.99,yes,locked 2006.145.13:34:30.62/vb/01,03,usb,yes,38,35 2006.145.13:34:30.62/vb/02,04,usb,yes,33,33 2006.145.13:34:30.62/vb/03,04,usb,yes,30,33 2006.145.13:34:30.62/vb/04,04,usb,yes,34,33 2006.145.13:34:30.62/vb/05,04,usb,yes,27,30 2006.145.13:34:30.62/vb/06,04,usb,yes,32,28 2006.145.13:34:30.62/vb/07,04,usb,yes,31,31 2006.145.13:34:30.62/vb/08,04,usb,yes,29,32 2006.145.13:34:30.86/vblo/01,629.99,yes,locked 2006.145.13:34:30.86/vblo/02,634.99,yes,locked 2006.145.13:34:30.86/vblo/03,649.99,yes,locked 2006.145.13:34:30.86/vblo/04,679.99,yes,locked 2006.145.13:34:30.86/vblo/05,709.99,yes,locked 2006.145.13:34:30.86/vblo/06,719.99,yes,locked 2006.145.13:34:30.86/vblo/07,734.99,yes,locked 2006.145.13:34:30.86/vblo/08,744.99,yes,locked 2006.145.13:34:31.01/vabw/8 2006.145.13:34:31.16/vbbw/8 2006.145.13:34:31.25/xfe/off,on,14.5 2006.145.13:34:31.62/ifatt/23,28,28,28 2006.145.13:34:32.07/fmout-gps/S +4.7E-08 2006.145.13:34:32.11:!2006.145.13:35:07 2006.145.13:35:07.01:data_valid=off 2006.145.13:35:07.01:"et 2006.145.13:35:07.02:!+3s 2006.145.13:35:10.03:"tape 2006.145.13:35:10.03:postob 2006.145.13:35:10.24/cable/+6.5482E-03 2006.145.13:35:10.24/wx/15.02,1020.8,87 2006.145.13:35:10.33/fmout-gps/S +4.7E-08 2006.145.13:35:10.33:scan_name=145-1335,jd0605,40 2006.145.13:35:10.33:source=1424-418,142756.30,-420619.4,2000.0,cw 2006.145.13:35:12.14#flagr#flagr/antenna,new-source 2006.145.13:35:12.14:checkk5 2006.145.13:35:12.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.13:35:13.00/chk_autoobs//k5ts2/ autoobs is running! 2006.145.13:35:13.45/chk_autoobs//k5ts3/ autoobs is running! 2006.145.13:35:13.87/chk_autoobs//k5ts4/ autoobs is running! 2006.145.13:35:14.30/chk_obsdata//k5ts1/T1451334??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.13:35:14.73/chk_obsdata//k5ts2/T1451334??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.13:35:15.17/chk_obsdata//k5ts3/T1451334??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.13:35:15.61/chk_obsdata//k5ts4/T1451334??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.13:35:16.37/k5log//k5ts1_log_newline 2006.145.13:35:17.11/k5log//k5ts2_log_newline 2006.145.13:35:17.85/k5log//k5ts3_log_newline 2006.145.13:35:18.60/k5log//k5ts4_log_newline 2006.145.13:35:18.63/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.13:35:18.63:setupk4=1 2006.145.13:35:18.63$setupk4/echo=on 2006.145.13:35:18.63$setupk4/pcalon 2006.145.13:35:18.63$pcalon/"no phase cal control is implemented here 2006.145.13:35:18.63$setupk4/"tpicd=stop 2006.145.13:35:18.63$setupk4/"rec=synch_on 2006.145.13:35:18.63$setupk4/"rec_mode=128 2006.145.13:35:18.63$setupk4/!* 2006.145.13:35:18.63$setupk4/recpk4 2006.145.13:35:18.63$recpk4/recpatch= 2006.145.13:35:18.63$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.13:35:18.63$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.13:35:18.63$setupk4/vck44 2006.145.13:35:18.63$vck44/valo=1,524.99 2006.145.13:35:18.63#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.13:35:18.63#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.13:35:18.63#ibcon#ireg 17 cls_cnt 0 2006.145.13:35:18.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:35:18.63#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:35:18.63#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:35:18.67#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.13:35:18.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:35:18.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:35:18.72#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.13:35:18.72#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.13:35:18.72$vck44/va=1,8 2006.145.13:35:18.72#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.13:35:18.72#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.13:35:18.72#ibcon#ireg 11 cls_cnt 2 2006.145.13:35:18.72#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:35:18.72#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:35:18.72#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:35:18.74#ibcon#[25=AT01-08\r\n] 2006.145.13:35:18.77#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:35:18.77#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:35:18.77#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.13:35:18.77#ibcon#ireg 7 cls_cnt 0 2006.145.13:35:18.77#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:35:18.89#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:35:18.89#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:35:18.91#ibcon#[25=USB\r\n] 2006.145.13:35:18.94#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:35:18.94#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:35:18.94#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.13:35:18.94#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.13:35:18.94$vck44/valo=2,534.99 2006.145.13:35:18.94#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.13:35:18.94#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.13:35:18.94#ibcon#ireg 17 cls_cnt 0 2006.145.13:35:18.94#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:35:18.94#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:35:18.94#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:35:18.97#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.13:35:19.01#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:35:19.01#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:35:19.01#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.13:35:19.01#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.13:35:19.01$vck44/va=2,7 2006.145.13:35:19.01#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.13:35:19.01#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.13:35:19.01#ibcon#ireg 11 cls_cnt 2 2006.145.13:35:19.01#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:35:19.06#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:35:19.06#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:35:19.08#ibcon#[25=AT02-07\r\n] 2006.145.13:35:19.11#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:35:19.11#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:35:19.11#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.13:35:19.11#ibcon#ireg 7 cls_cnt 0 2006.145.13:35:19.11#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:35:19.23#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:35:19.23#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:35:19.25#ibcon#[25=USB\r\n] 2006.145.13:35:19.28#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:35:19.28#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:35:19.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.13:35:19.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.13:35:19.28$vck44/valo=3,564.99 2006.145.13:35:19.28#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.13:35:19.28#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.13:35:19.28#ibcon#ireg 17 cls_cnt 0 2006.145.13:35:19.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:35:19.28#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:35:19.28#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:35:19.30#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.13:35:19.34#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:35:19.34#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:35:19.34#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.13:35:19.34#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.13:35:19.34$vck44/va=3,8 2006.145.13:35:19.34#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.13:35:19.34#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.13:35:19.34#ibcon#ireg 11 cls_cnt 2 2006.145.13:35:19.34#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:35:19.40#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:35:19.40#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:35:19.42#ibcon#[25=AT03-08\r\n] 2006.145.13:35:19.45#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:35:19.45#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:35:19.45#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.13:35:19.45#ibcon#ireg 7 cls_cnt 0 2006.145.13:35:19.45#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:35:19.57#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:35:19.57#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:35:19.59#ibcon#[25=USB\r\n] 2006.145.13:35:19.62#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:35:19.62#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:35:19.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.13:35:19.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.13:35:19.62$vck44/valo=4,624.99 2006.145.13:35:19.62#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.13:35:19.62#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.13:35:19.62#ibcon#ireg 17 cls_cnt 0 2006.145.13:35:19.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:35:19.62#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:35:19.62#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:35:19.64#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.13:35:19.68#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:35:19.68#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:35:19.68#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.13:35:19.68#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.13:35:19.68$vck44/va=4,7 2006.145.13:35:19.68#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.13:35:19.68#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.13:35:19.68#ibcon#ireg 11 cls_cnt 2 2006.145.13:35:19.68#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:35:19.74#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:35:19.74#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:35:19.76#ibcon#[25=AT04-07\r\n] 2006.145.13:35:19.79#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:35:19.79#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:35:19.79#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.13:35:19.79#ibcon#ireg 7 cls_cnt 0 2006.145.13:35:19.79#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:35:19.91#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:35:19.91#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:35:19.93#ibcon#[25=USB\r\n] 2006.145.13:35:19.96#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:35:19.96#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:35:19.96#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.13:35:19.96#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.13:35:19.96$vck44/valo=5,734.99 2006.145.13:35:19.96#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.13:35:19.96#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.13:35:19.96#ibcon#ireg 17 cls_cnt 0 2006.145.13:35:19.96#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:35:19.96#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:35:19.96#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:35:19.98#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.13:35:20.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:35:20.02#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:35:20.02#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.13:35:20.02#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.13:35:20.02$vck44/va=5,4 2006.145.13:35:20.02#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.13:35:20.02#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.13:35:20.02#ibcon#ireg 11 cls_cnt 2 2006.145.13:35:20.02#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.13:35:20.08#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.13:35:20.08#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.13:35:20.10#ibcon#[25=AT05-04\r\n] 2006.145.13:35:20.13#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.13:35:20.13#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.13:35:20.13#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.13:35:20.13#ibcon#ireg 7 cls_cnt 0 2006.145.13:35:20.13#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.13:35:20.25#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.13:35:20.25#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.13:35:20.27#ibcon#[25=USB\r\n] 2006.145.13:35:20.30#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.13:35:20.30#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.13:35:20.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.13:35:20.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.13:35:20.30$vck44/valo=6,814.99 2006.145.13:35:20.30#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.13:35:20.30#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.13:35:20.30#ibcon#ireg 17 cls_cnt 0 2006.145.13:35:20.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:35:20.30#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:35:20.30#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:35:20.33#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.13:35:20.37#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:35:20.37#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:35:20.37#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.13:35:20.37#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.13:35:20.37$vck44/va=6,4 2006.145.13:35:20.37#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.13:35:20.37#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.13:35:20.37#ibcon#ireg 11 cls_cnt 2 2006.145.13:35:20.37#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.13:35:20.42#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.13:35:20.42#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.13:35:20.44#ibcon#[25=AT06-04\r\n] 2006.145.13:35:20.47#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.13:35:20.47#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.13:35:20.47#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.13:35:20.47#ibcon#ireg 7 cls_cnt 0 2006.145.13:35:20.47#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.13:35:20.59#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.13:35:20.59#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.13:35:20.61#ibcon#[25=USB\r\n] 2006.145.13:35:20.64#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.13:35:20.64#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.13:35:20.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.13:35:20.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.13:35:20.64$vck44/valo=7,864.99 2006.145.13:35:20.64#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.13:35:20.64#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.13:35:20.64#ibcon#ireg 17 cls_cnt 0 2006.145.13:35:20.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:35:20.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:35:20.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:35:20.66#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.13:35:20.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:35:20.70#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:35:20.70#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.13:35:20.70#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.13:35:20.70$vck44/va=7,4 2006.145.13:35:20.70#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.13:35:20.70#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.13:35:20.70#ibcon#ireg 11 cls_cnt 2 2006.145.13:35:20.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.13:35:20.76#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.13:35:20.76#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.13:35:20.78#ibcon#[25=AT07-04\r\n] 2006.145.13:35:20.81#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.13:35:20.81#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.13:35:20.81#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.13:35:20.81#ibcon#ireg 7 cls_cnt 0 2006.145.13:35:20.81#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.13:35:20.93#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.13:35:20.93#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.13:35:20.95#ibcon#[25=USB\r\n] 2006.145.13:35:20.98#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.13:35:20.98#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.13:35:20.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.13:35:20.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.13:35:20.98$vck44/valo=8,884.99 2006.145.13:35:20.98#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.13:35:20.98#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.13:35:20.98#ibcon#ireg 17 cls_cnt 0 2006.145.13:35:20.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:35:20.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:35:20.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:35:21.00#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.13:35:21.04#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:35:21.04#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:35:21.04#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.13:35:21.04#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.13:35:21.04$vck44/va=8,4 2006.145.13:35:21.04#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.13:35:21.04#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.13:35:21.04#ibcon#ireg 11 cls_cnt 2 2006.145.13:35:21.04#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.13:35:21.10#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.13:35:21.10#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.13:35:21.12#ibcon#[25=AT08-04\r\n] 2006.145.13:35:21.15#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.13:35:21.15#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.13:35:21.15#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.13:35:21.15#ibcon#ireg 7 cls_cnt 0 2006.145.13:35:21.15#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.13:35:21.27#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.13:35:21.27#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.13:35:21.29#ibcon#[25=USB\r\n] 2006.145.13:35:21.32#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.13:35:21.32#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.13:35:21.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.13:35:21.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.13:35:21.32$vck44/vblo=1,629.99 2006.145.13:35:21.32#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.13:35:21.32#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.13:35:21.32#ibcon#ireg 17 cls_cnt 0 2006.145.13:35:21.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:35:21.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:35:21.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:35:21.34#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.13:35:21.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:35:21.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:35:21.38#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.13:35:21.38#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.13:35:21.38$vck44/vb=1,3 2006.145.13:35:21.38#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.13:35:21.38#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.13:35:21.38#ibcon#ireg 11 cls_cnt 2 2006.145.13:35:21.38#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.13:35:21.38#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.13:35:21.38#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.13:35:21.40#ibcon#[27=AT01-03\r\n] 2006.145.13:35:21.43#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.13:35:21.43#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.13:35:21.43#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.13:35:21.43#ibcon#ireg 7 cls_cnt 0 2006.145.13:35:21.43#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.13:35:21.55#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.13:35:21.55#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.13:35:21.57#ibcon#[27=USB\r\n] 2006.145.13:35:21.60#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.13:35:21.60#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.13:35:21.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.13:35:21.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.13:35:21.60$vck44/vblo=2,634.99 2006.145.13:35:21.60#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.13:35:21.60#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.13:35:21.60#ibcon#ireg 17 cls_cnt 0 2006.145.13:35:21.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:35:21.60#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:35:21.60#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:35:21.62#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.13:35:21.66#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:35:21.66#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:35:21.66#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.13:35:21.66#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.13:35:21.66$vck44/vb=2,4 2006.145.13:35:21.66#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.13:35:21.66#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.13:35:21.66#ibcon#ireg 11 cls_cnt 2 2006.145.13:35:21.66#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:35:21.72#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:35:21.72#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:35:21.74#ibcon#[27=AT02-04\r\n] 2006.145.13:35:21.77#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:35:21.77#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:35:21.77#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.13:35:21.77#ibcon#ireg 7 cls_cnt 0 2006.145.13:35:21.77#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:35:21.89#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:35:21.89#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:35:21.91#ibcon#[27=USB\r\n] 2006.145.13:35:21.94#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:35:21.94#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:35:21.94#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.13:35:21.94#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.13:35:21.94$vck44/vblo=3,649.99 2006.145.13:35:21.94#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.13:35:21.94#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.13:35:21.94#ibcon#ireg 17 cls_cnt 0 2006.145.13:35:21.94#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:35:21.94#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:35:21.94#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:35:21.96#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.13:35:22.00#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:35:22.00#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:35:22.00#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.13:35:22.00#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.13:35:22.00$vck44/vb=3,4 2006.145.13:35:22.00#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.13:35:22.00#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.13:35:22.00#ibcon#ireg 11 cls_cnt 2 2006.145.13:35:22.00#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:35:22.06#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:35:22.06#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:35:22.08#ibcon#[27=AT03-04\r\n] 2006.145.13:35:22.11#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:35:22.11#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:35:22.11#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.13:35:22.11#ibcon#ireg 7 cls_cnt 0 2006.145.13:35:22.11#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:35:22.23#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:35:22.23#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:35:22.25#ibcon#[27=USB\r\n] 2006.145.13:35:22.28#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:35:22.28#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:35:22.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.13:35:22.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.13:35:22.28$vck44/vblo=4,679.99 2006.145.13:35:22.28#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.13:35:22.28#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.13:35:22.28#ibcon#ireg 17 cls_cnt 0 2006.145.13:35:22.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:35:22.28#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:35:22.28#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:35:22.30#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.13:35:22.34#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:35:22.34#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:35:22.34#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.13:35:22.34#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.13:35:22.34$vck44/vb=4,4 2006.145.13:35:22.34#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.13:35:22.34#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.13:35:22.34#ibcon#ireg 11 cls_cnt 2 2006.145.13:35:22.34#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:35:22.40#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:35:22.40#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:35:22.42#ibcon#[27=AT04-04\r\n] 2006.145.13:35:22.45#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:35:22.45#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:35:22.45#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.13:35:22.45#ibcon#ireg 7 cls_cnt 0 2006.145.13:35:22.45#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:35:22.57#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:35:22.57#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:35:22.59#ibcon#[27=USB\r\n] 2006.145.13:35:22.62#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:35:22.62#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:35:22.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.13:35:22.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.13:35:22.62$vck44/vblo=5,709.99 2006.145.13:35:22.62#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.13:35:22.62#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.13:35:22.62#ibcon#ireg 17 cls_cnt 0 2006.145.13:35:22.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:35:22.62#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:35:22.62#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:35:22.64#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.13:35:22.68#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:35:22.68#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:35:22.68#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.13:35:22.68#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.13:35:22.68$vck44/vb=5,4 2006.145.13:35:22.68#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.13:35:22.68#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.13:35:22.68#ibcon#ireg 11 cls_cnt 2 2006.145.13:35:22.68#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:35:22.74#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:35:22.74#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:35:22.76#ibcon#[27=AT05-04\r\n] 2006.145.13:35:22.79#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:35:22.79#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:35:22.79#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.13:35:22.79#ibcon#ireg 7 cls_cnt 0 2006.145.13:35:22.79#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:35:22.91#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:35:22.91#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:35:22.93#ibcon#[27=USB\r\n] 2006.145.13:35:22.96#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:35:22.96#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:35:22.96#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.13:35:22.96#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.13:35:22.96$vck44/vblo=6,719.99 2006.145.13:35:22.96#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.13:35:22.96#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.13:35:22.96#ibcon#ireg 17 cls_cnt 0 2006.145.13:35:22.96#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:35:22.96#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:35:22.96#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:35:22.98#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.13:35:23.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:35:23.02#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:35:23.02#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.13:35:23.02#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.13:35:23.02$vck44/vb=6,4 2006.145.13:35:23.02#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.13:35:23.02#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.13:35:23.02#ibcon#ireg 11 cls_cnt 2 2006.145.13:35:23.02#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.13:35:23.08#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.13:35:23.08#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.13:35:23.10#ibcon#[27=AT06-04\r\n] 2006.145.13:35:23.13#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.13:35:23.13#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.13:35:23.13#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.13:35:23.13#ibcon#ireg 7 cls_cnt 0 2006.145.13:35:23.13#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.13:35:23.25#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.13:35:23.25#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.13:35:23.27#ibcon#[27=USB\r\n] 2006.145.13:35:23.30#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.13:35:23.30#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.13:35:23.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.13:35:23.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.13:35:23.30$vck44/vblo=7,734.99 2006.145.13:35:23.30#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.13:35:23.30#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.13:35:23.30#ibcon#ireg 17 cls_cnt 0 2006.145.13:35:23.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:35:23.30#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:35:23.30#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:35:23.32#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.13:35:23.36#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:35:23.36#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:35:23.36#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.13:35:23.36#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.13:35:23.36$vck44/vb=7,4 2006.145.13:35:23.36#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.13:35:23.36#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.13:35:23.36#ibcon#ireg 11 cls_cnt 2 2006.145.13:35:23.36#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.13:35:23.42#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.13:35:23.42#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.13:35:23.44#ibcon#[27=AT07-04\r\n] 2006.145.13:35:23.47#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.13:35:23.47#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.13:35:23.47#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.13:35:23.47#ibcon#ireg 7 cls_cnt 0 2006.145.13:35:23.47#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.13:35:23.59#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.13:35:23.59#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.13:35:23.61#ibcon#[27=USB\r\n] 2006.145.13:35:23.64#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.13:35:23.64#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.13:35:23.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.13:35:23.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.13:35:23.64$vck44/vblo=8,744.99 2006.145.13:35:23.64#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.13:35:23.64#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.13:35:23.64#ibcon#ireg 17 cls_cnt 0 2006.145.13:35:23.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:35:23.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:35:23.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:35:23.66#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.13:35:23.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:35:23.70#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:35:23.70#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.13:35:23.70#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.13:35:23.70$vck44/vb=8,4 2006.145.13:35:23.70#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.13:35:23.70#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.13:35:23.70#ibcon#ireg 11 cls_cnt 2 2006.145.13:35:23.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.13:35:23.76#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.13:35:23.76#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.13:35:23.78#ibcon#[27=AT08-04\r\n] 2006.145.13:35:23.81#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.13:35:23.81#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.13:35:23.81#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.13:35:23.81#ibcon#ireg 7 cls_cnt 0 2006.145.13:35:23.81#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.13:35:23.93#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.13:35:23.93#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.13:35:23.95#ibcon#[27=USB\r\n] 2006.145.13:35:23.98#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.13:35:23.98#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.13:35:23.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.13:35:23.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.13:35:23.98$vck44/vabw=wide 2006.145.13:35:23.98#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.13:35:23.98#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.13:35:23.98#ibcon#ireg 8 cls_cnt 0 2006.145.13:35:23.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:35:23.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:35:23.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:35:24.00#ibcon#[25=BW32\r\n] 2006.145.13:35:24.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:35:24.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:35:24.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.13:35:24.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.13:35:24.03$vck44/vbbw=wide 2006.145.13:35:24.03#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.13:35:24.03#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.13:35:24.03#ibcon#ireg 8 cls_cnt 0 2006.145.13:35:24.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:35:24.10#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:35:24.10#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:35:24.12#ibcon#[27=BW32\r\n] 2006.145.13:35:24.15#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:35:24.15#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:35:24.15#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.13:35:24.15#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.13:35:24.15$setupk4/ifdk4 2006.145.13:35:24.15$ifdk4/lo= 2006.145.13:35:24.15$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.13:35:24.15$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.13:35:24.15$ifdk4/patch= 2006.145.13:35:24.15$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.13:35:24.15$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.13:35:24.15$setupk4/!*+20s 2006.145.13:35:25.37#abcon#<5=/07 0.5 1.1 15.00 871020.8\r\n> 2006.145.13:35:25.39#abcon#{5=INTERFACE CLEAR} 2006.145.13:35:25.47#abcon#[5=S1D000X0/0*\r\n] 2006.145.13:35:35.56#abcon#<5=/07 0.5 1.0 14.99 871020.7\r\n> 2006.145.13:35:35.58#abcon#{5=INTERFACE CLEAR} 2006.145.13:35:35.64#abcon#[5=S1D000X0/0*\r\n] 2006.145.13:35:38.64$setupk4/"tpicd 2006.145.13:35:38.64$setupk4/echo=off 2006.145.13:35:38.64$setupk4/xlog=off 2006.145.13:35:38.64:!2006.145.13:35:43 2006.145.13:35:41.14#trakl#Source acquired 2006.145.13:35:43.00:preob 2006.145.13:35:43.14#flagr#flagr/antenna,acquired 2006.145.13:35:44.14/onsource/TRACKING 2006.145.13:35:44.14:!2006.145.13:35:53 2006.145.13:35:53.00:"tape 2006.145.13:35:53.00:"st=record 2006.145.13:35:53.00:data_valid=on 2006.145.13:35:53.00:midob 2006.145.13:35:53.14/onsource/TRACKING 2006.145.13:35:53.14/wx/14.98,1020.8,87 2006.145.13:35:53.37/cable/+6.5493E-03 2006.145.13:35:54.46/va/01,08,usb,yes,32,35 2006.145.13:35:54.46/va/02,07,usb,yes,35,35 2006.145.13:35:54.46/va/03,08,usb,yes,32,33 2006.145.13:35:54.46/va/04,07,usb,yes,36,38 2006.145.13:35:54.46/va/05,04,usb,yes,31,32 2006.145.13:35:54.46/va/06,04,usb,yes,35,35 2006.145.13:35:54.46/va/07,04,usb,yes,35,37 2006.145.13:35:54.46/va/08,04,usb,yes,30,36 2006.145.13:35:54.69/valo/01,524.99,yes,locked 2006.145.13:35:54.69/valo/02,534.99,yes,locked 2006.145.13:35:54.69/valo/03,564.99,yes,locked 2006.145.13:35:54.69/valo/04,624.99,yes,locked 2006.145.13:35:54.69/valo/05,734.99,yes,locked 2006.145.13:35:54.69/valo/06,814.99,yes,locked 2006.145.13:35:54.69/valo/07,864.99,yes,locked 2006.145.13:35:54.69/valo/08,884.99,yes,locked 2006.145.13:35:55.78/vb/01,03,usb,yes,39,36 2006.145.13:35:55.78/vb/02,04,usb,yes,34,34 2006.145.13:35:55.78/vb/03,04,usb,yes,31,34 2006.145.13:35:55.78/vb/04,04,usb,yes,35,34 2006.145.13:35:55.78/vb/05,04,usb,yes,28,30 2006.145.13:35:55.78/vb/06,04,usb,yes,32,29 2006.145.13:35:55.78/vb/07,04,usb,yes,32,32 2006.145.13:35:55.78/vb/08,04,usb,yes,30,33 2006.145.13:35:56.02/vblo/01,629.99,yes,locked 2006.145.13:35:56.02/vblo/02,634.99,yes,locked 2006.145.13:35:56.02/vblo/03,649.99,yes,locked 2006.145.13:35:56.02/vblo/04,679.99,yes,locked 2006.145.13:35:56.02/vblo/05,709.99,yes,locked 2006.145.13:35:56.02/vblo/06,719.99,yes,locked 2006.145.13:35:56.02/vblo/07,734.99,yes,locked 2006.145.13:35:56.02/vblo/08,744.99,yes,locked 2006.145.13:35:56.17/vabw/8 2006.145.13:35:56.32/vbbw/8 2006.145.13:35:56.44/xfe/off,on,15.0 2006.145.13:35:56.82/ifatt/23,28,28,28 2006.145.13:35:57.07/fmout-gps/S +4.7E-08 2006.145.13:35:57.15:!2006.145.13:36:33 2006.145.13:36:33.00:data_valid=off 2006.145.13:36:33.00:"et 2006.145.13:36:33.01:!+3s 2006.145.13:36:36.02:"tape 2006.145.13:36:36.02:postob 2006.145.13:36:36.09/cable/+6.5484E-03 2006.145.13:36:36.09/wx/14.96,1020.7,88 2006.145.13:36:36.17/fmout-gps/S +4.7E-08 2006.145.13:36:36.17:scan_name=145-1341,jd0605,100 2006.145.13:36:36.18:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.145.13:36:38.14#flagr#flagr/antenna,new-source 2006.145.13:36:38.14:checkk5 2006.145.13:36:38.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.13:36:39.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.13:36:39.45/chk_autoobs//k5ts3/ autoobs is running! 2006.145.13:36:39.87/chk_autoobs//k5ts4/ autoobs is running! 2006.145.13:36:40.29/chk_obsdata//k5ts1/T1451335??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.13:36:40.72/chk_obsdata//k5ts2/T1451335??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.13:36:41.17/chk_obsdata//k5ts3/T1451335??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.13:36:41.61/chk_obsdata//k5ts4/T1451335??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.13:36:42.36/k5log//k5ts1_log_newline 2006.145.13:36:43.11/k5log//k5ts2_log_newline 2006.145.13:36:43.85/k5log//k5ts3_log_newline 2006.145.13:36:44.60/k5log//k5ts4_log_newline 2006.145.13:36:44.63/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.13:36:44.63:setupk4=1 2006.145.13:36:44.63$setupk4/echo=on 2006.145.13:36:44.63$setupk4/pcalon 2006.145.13:36:44.63$pcalon/"no phase cal control is implemented here 2006.145.13:36:44.63$setupk4/"tpicd=stop 2006.145.13:36:44.63$setupk4/"rec=synch_on 2006.145.13:36:44.63$setupk4/"rec_mode=128 2006.145.13:36:44.63$setupk4/!* 2006.145.13:36:44.63$setupk4/recpk4 2006.145.13:36:44.63$recpk4/recpatch= 2006.145.13:36:44.63$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.13:36:44.63$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.13:36:44.63$setupk4/vck44 2006.145.13:36:44.63$vck44/valo=1,524.99 2006.145.13:36:44.63#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.13:36:44.63#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.13:36:44.63#ibcon#ireg 17 cls_cnt 0 2006.145.13:36:44.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.13:36:44.63#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.13:36:44.63#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.13:36:44.67#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.13:36:44.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.13:36:44.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.13:36:44.72#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.13:36:44.72#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.13:36:44.72$vck44/va=1,8 2006.145.13:36:44.72#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.13:36:44.72#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.13:36:44.72#ibcon#ireg 11 cls_cnt 2 2006.145.13:36:44.72#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.13:36:44.72#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.13:36:44.72#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.13:36:44.74#ibcon#[25=AT01-08\r\n] 2006.145.13:36:44.77#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.13:36:44.77#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.13:36:44.77#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.13:36:44.77#ibcon#ireg 7 cls_cnt 0 2006.145.13:36:44.77#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.13:36:44.90#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.13:36:44.90#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.13:36:44.91#ibcon#[25=USB\r\n] 2006.145.13:36:44.94#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.13:36:44.94#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.13:36:44.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.13:36:44.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.13:36:44.94$vck44/valo=2,534.99 2006.145.13:36:44.94#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.13:36:44.94#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.13:36:44.94#ibcon#ireg 17 cls_cnt 0 2006.145.13:36:44.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.13:36:44.94#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.13:36:44.94#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.13:36:44.97#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.13:36:45.01#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.13:36:45.01#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.13:36:45.01#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.13:36:45.01#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.13:36:45.01$vck44/va=2,7 2006.145.13:36:45.01#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.13:36:45.01#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.13:36:45.01#ibcon#ireg 11 cls_cnt 2 2006.145.13:36:45.01#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.13:36:45.06#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.13:36:45.06#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.13:36:45.08#ibcon#[25=AT02-07\r\n] 2006.145.13:36:45.11#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.13:36:45.11#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.13:36:45.11#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.13:36:45.11#ibcon#ireg 7 cls_cnt 0 2006.145.13:36:45.11#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.13:36:45.23#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.13:36:45.23#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.13:36:45.25#ibcon#[25=USB\r\n] 2006.145.13:36:45.28#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.13:36:45.28#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.13:36:45.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.13:36:45.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.13:36:45.28$vck44/valo=3,564.99 2006.145.13:36:45.28#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.13:36:45.28#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.13:36:45.28#ibcon#ireg 17 cls_cnt 0 2006.145.13:36:45.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.13:36:45.28#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.13:36:45.28#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.13:36:45.30#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.13:36:45.34#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.13:36:45.34#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.13:36:45.34#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.13:36:45.34#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.13:36:45.34$vck44/va=3,8 2006.145.13:36:45.34#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.13:36:45.34#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.13:36:45.34#ibcon#ireg 11 cls_cnt 2 2006.145.13:36:45.34#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.13:36:45.40#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.13:36:45.40#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.13:36:45.42#ibcon#[25=AT03-08\r\n] 2006.145.13:36:45.45#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.13:36:45.45#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.13:36:45.45#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.13:36:45.45#ibcon#ireg 7 cls_cnt 0 2006.145.13:36:45.45#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.13:36:45.57#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.13:36:45.57#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.13:36:45.59#ibcon#[25=USB\r\n] 2006.145.13:36:45.62#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.13:36:45.62#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.13:36:45.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.13:36:45.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.13:36:45.62$vck44/valo=4,624.99 2006.145.13:36:45.62#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.13:36:45.62#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.13:36:45.62#ibcon#ireg 17 cls_cnt 0 2006.145.13:36:45.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.13:36:45.62#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.13:36:45.62#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.13:36:45.64#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.13:36:45.68#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.13:36:45.68#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.13:36:45.68#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.13:36:45.68#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.13:36:45.68$vck44/va=4,7 2006.145.13:36:45.68#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.13:36:45.68#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.13:36:45.68#ibcon#ireg 11 cls_cnt 2 2006.145.13:36:45.68#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.13:36:45.74#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.13:36:45.74#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.13:36:45.76#ibcon#[25=AT04-07\r\n] 2006.145.13:36:45.79#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.13:36:45.79#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.13:36:45.79#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.13:36:45.79#ibcon#ireg 7 cls_cnt 0 2006.145.13:36:45.79#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.13:36:45.91#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.13:36:45.91#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.13:36:45.93#ibcon#[25=USB\r\n] 2006.145.13:36:45.96#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.13:36:45.96#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.13:36:45.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.13:36:45.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.13:36:45.96$vck44/valo=5,734.99 2006.145.13:36:45.96#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.13:36:45.96#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.13:36:45.96#ibcon#ireg 17 cls_cnt 0 2006.145.13:36:45.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.13:36:45.96#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.13:36:45.96#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.13:36:45.98#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.13:36:46.02#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.13:36:46.02#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.13:36:46.02#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.13:36:46.02#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.13:36:46.02$vck44/va=5,4 2006.145.13:36:46.02#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.13:36:46.02#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.13:36:46.02#ibcon#ireg 11 cls_cnt 2 2006.145.13:36:46.02#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.13:36:46.08#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.13:36:46.08#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.13:36:46.10#ibcon#[25=AT05-04\r\n] 2006.145.13:36:46.13#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.13:36:46.13#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.13:36:46.13#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.13:36:46.13#ibcon#ireg 7 cls_cnt 0 2006.145.13:36:46.13#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.13:36:46.25#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.13:36:46.25#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.13:36:46.27#ibcon#[25=USB\r\n] 2006.145.13:36:46.30#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.13:36:46.30#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.13:36:46.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.13:36:46.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.13:36:46.30$vck44/valo=6,814.99 2006.145.13:36:46.30#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.13:36:46.30#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.13:36:46.30#ibcon#ireg 17 cls_cnt 0 2006.145.13:36:46.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.13:36:46.30#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.13:36:46.30#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.13:36:46.32#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.13:36:46.36#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.13:36:46.36#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.13:36:46.36#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.13:36:46.36#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.13:36:46.36$vck44/va=6,4 2006.145.13:36:46.36#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.13:36:46.36#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.13:36:46.36#ibcon#ireg 11 cls_cnt 2 2006.145.13:36:46.36#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.13:36:46.42#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.13:36:46.42#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.13:36:46.44#ibcon#[25=AT06-04\r\n] 2006.145.13:36:46.47#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.13:36:46.47#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.13:36:46.47#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.13:36:46.47#ibcon#ireg 7 cls_cnt 0 2006.145.13:36:46.47#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.13:36:46.59#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.13:36:46.59#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.13:36:46.61#ibcon#[25=USB\r\n] 2006.145.13:36:46.64#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.13:36:46.64#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.13:36:46.64#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.13:36:46.64#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.13:36:46.64$vck44/valo=7,864.99 2006.145.13:36:46.64#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.13:36:46.64#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.13:36:46.64#ibcon#ireg 17 cls_cnt 0 2006.145.13:36:46.64#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.13:36:46.64#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.13:36:46.64#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.13:36:46.66#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.13:36:46.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.13:36:46.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.13:36:46.70#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.13:36:46.70#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.13:36:46.70$vck44/va=7,4 2006.145.13:36:46.70#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.13:36:46.70#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.13:36:46.70#ibcon#ireg 11 cls_cnt 2 2006.145.13:36:46.70#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.13:36:46.75#abcon#<5=/07 0.5 1.1 14.95 881020.8\r\n> 2006.145.13:36:46.76#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.13:36:46.76#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.13:36:46.77#abcon#{5=INTERFACE CLEAR} 2006.145.13:36:46.78#ibcon#[25=AT07-04\r\n] 2006.145.13:36:46.81#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.13:36:46.81#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.13:36:46.81#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.13:36:46.81#ibcon#ireg 7 cls_cnt 0 2006.145.13:36:46.81#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.13:36:46.83#abcon#[5=S1D000X0/0*\r\n] 2006.145.13:36:46.93#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.13:36:46.93#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.13:36:46.95#ibcon#[25=USB\r\n] 2006.145.13:36:46.98#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.13:36:46.98#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.13:36:46.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.13:36:46.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.13:36:46.98$vck44/valo=8,884.99 2006.145.13:36:46.98#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.13:36:46.98#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.13:36:46.98#ibcon#ireg 17 cls_cnt 0 2006.145.13:36:46.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.13:36:46.98#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.13:36:46.98#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.13:36:47.00#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.13:36:47.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.13:36:47.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.13:36:47.04#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.13:36:47.04#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.13:36:47.04$vck44/va=8,4 2006.145.13:36:47.04#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.13:36:47.04#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.13:36:47.04#ibcon#ireg 11 cls_cnt 2 2006.145.13:36:47.04#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.13:36:47.10#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.13:36:47.10#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.13:36:47.12#ibcon#[25=AT08-04\r\n] 2006.145.13:36:47.15#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.13:36:47.15#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.13:36:47.15#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.13:36:47.15#ibcon#ireg 7 cls_cnt 0 2006.145.13:36:47.15#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.13:36:47.27#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.13:36:47.27#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.13:36:47.29#ibcon#[25=USB\r\n] 2006.145.13:36:47.32#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.13:36:47.32#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.13:36:47.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.13:36:47.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.13:36:47.32$vck44/vblo=1,629.99 2006.145.13:36:47.32#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.13:36:47.32#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.13:36:47.32#ibcon#ireg 17 cls_cnt 0 2006.145.13:36:47.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.13:36:47.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.13:36:47.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.13:36:47.34#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.13:36:47.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.13:36:47.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.13:36:47.38#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.13:36:47.38#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.13:36:47.38$vck44/vb=1,3 2006.145.13:36:47.38#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.13:36:47.38#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.13:36:47.38#ibcon#ireg 11 cls_cnt 2 2006.145.13:36:47.38#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.13:36:47.38#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.13:36:47.38#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.13:36:47.40#ibcon#[27=AT01-03\r\n] 2006.145.13:36:47.43#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.13:36:47.43#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.13:36:47.43#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.13:36:47.43#ibcon#ireg 7 cls_cnt 0 2006.145.13:36:47.43#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.13:36:47.55#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.13:36:47.55#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.13:36:47.57#ibcon#[27=USB\r\n] 2006.145.13:36:47.60#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.13:36:47.60#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.13:36:47.60#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.13:36:47.60#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.13:36:47.60$vck44/vblo=2,634.99 2006.145.13:36:47.60#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.13:36:47.60#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.13:36:47.60#ibcon#ireg 17 cls_cnt 0 2006.145.13:36:47.60#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.13:36:47.60#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.13:36:47.60#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.13:36:47.62#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.13:36:47.66#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.13:36:47.66#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.13:36:47.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.13:36:47.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.13:36:47.66$vck44/vb=2,4 2006.145.13:36:47.66#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.13:36:47.66#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.13:36:47.66#ibcon#ireg 11 cls_cnt 2 2006.145.13:36:47.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.13:36:47.72#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.13:36:47.72#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.13:36:47.74#ibcon#[27=AT02-04\r\n] 2006.145.13:36:47.77#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.13:36:47.77#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.13:36:47.77#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.13:36:47.77#ibcon#ireg 7 cls_cnt 0 2006.145.13:36:47.77#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.13:36:47.89#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.13:36:47.89#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.13:36:47.91#ibcon#[27=USB\r\n] 2006.145.13:36:47.94#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.13:36:47.94#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.13:36:47.94#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.13:36:47.94#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.13:36:47.94$vck44/vblo=3,649.99 2006.145.13:36:47.94#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.13:36:47.94#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.13:36:47.94#ibcon#ireg 17 cls_cnt 0 2006.145.13:36:47.94#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.13:36:47.94#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.13:36:47.94#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.13:36:47.96#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.13:36:48.00#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.13:36:48.00#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.13:36:48.00#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.13:36:48.00#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.13:36:48.00$vck44/vb=3,4 2006.145.13:36:48.00#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.13:36:48.00#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.13:36:48.00#ibcon#ireg 11 cls_cnt 2 2006.145.13:36:48.00#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.13:36:48.06#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.13:36:48.06#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.13:36:48.08#ibcon#[27=AT03-04\r\n] 2006.145.13:36:48.11#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.13:36:48.11#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.13:36:48.11#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.13:36:48.11#ibcon#ireg 7 cls_cnt 0 2006.145.13:36:48.11#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.13:36:48.23#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.13:36:48.23#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.13:36:48.25#ibcon#[27=USB\r\n] 2006.145.13:36:48.28#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.13:36:48.28#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.13:36:48.28#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.13:36:48.28#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.13:36:48.28$vck44/vblo=4,679.99 2006.145.13:36:48.28#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.13:36:48.28#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.13:36:48.28#ibcon#ireg 17 cls_cnt 0 2006.145.13:36:48.28#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.13:36:48.28#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.13:36:48.28#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.13:36:48.30#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.13:36:48.34#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.13:36:48.34#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.13:36:48.34#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.13:36:48.34#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.13:36:48.34$vck44/vb=4,4 2006.145.13:36:48.34#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.13:36:48.34#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.13:36:48.34#ibcon#ireg 11 cls_cnt 2 2006.145.13:36:48.34#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.13:36:48.40#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.13:36:48.40#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.13:36:48.42#ibcon#[27=AT04-04\r\n] 2006.145.13:36:48.45#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.13:36:48.45#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.13:36:48.45#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.13:36:48.45#ibcon#ireg 7 cls_cnt 0 2006.145.13:36:48.45#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.13:36:48.57#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.13:36:48.57#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.13:36:48.59#ibcon#[27=USB\r\n] 2006.145.13:36:48.62#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.13:36:48.62#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.13:36:48.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.13:36:48.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.13:36:48.62$vck44/vblo=5,709.99 2006.145.13:36:48.62#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.13:36:48.62#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.13:36:48.62#ibcon#ireg 17 cls_cnt 0 2006.145.13:36:48.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.13:36:48.62#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.13:36:48.62#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.13:36:48.64#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.13:36:48.68#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.13:36:48.68#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.13:36:48.68#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.13:36:48.68#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.13:36:48.68$vck44/vb=5,4 2006.145.13:36:48.68#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.13:36:48.68#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.13:36:48.68#ibcon#ireg 11 cls_cnt 2 2006.145.13:36:48.68#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.13:36:48.74#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.13:36:48.74#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.13:36:48.76#ibcon#[27=AT05-04\r\n] 2006.145.13:36:48.79#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.13:36:48.79#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.13:36:48.79#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.13:36:48.79#ibcon#ireg 7 cls_cnt 0 2006.145.13:36:48.79#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.13:36:48.91#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.13:36:48.91#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.13:36:48.93#ibcon#[27=USB\r\n] 2006.145.13:36:48.96#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.13:36:48.96#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.13:36:48.96#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.13:36:48.96#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.13:36:48.96$vck44/vblo=6,719.99 2006.145.13:36:48.96#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.13:36:48.96#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.13:36:48.96#ibcon#ireg 17 cls_cnt 0 2006.145.13:36:48.96#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.13:36:48.96#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.13:36:48.96#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.13:36:48.98#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.13:36:49.02#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.13:36:49.02#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.13:36:49.02#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.13:36:49.02#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.13:36:49.02$vck44/vb=6,4 2006.145.13:36:49.02#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.13:36:49.02#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.13:36:49.02#ibcon#ireg 11 cls_cnt 2 2006.145.13:36:49.02#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.13:36:49.08#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.13:36:49.08#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.13:36:49.10#ibcon#[27=AT06-04\r\n] 2006.145.13:36:49.13#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.13:36:49.13#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.13:36:49.13#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.13:36:49.13#ibcon#ireg 7 cls_cnt 0 2006.145.13:36:49.13#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.13:36:49.25#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.13:36:49.25#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.13:36:49.27#ibcon#[27=USB\r\n] 2006.145.13:36:49.30#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.13:36:49.30#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.13:36:49.30#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.13:36:49.30#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.13:36:49.30$vck44/vblo=7,734.99 2006.145.13:36:49.30#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.13:36:49.30#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.13:36:49.30#ibcon#ireg 17 cls_cnt 0 2006.145.13:36:49.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.13:36:49.30#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.13:36:49.30#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.13:36:49.32#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.13:36:49.36#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.13:36:49.36#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.13:36:49.36#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.13:36:49.36#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.13:36:49.36$vck44/vb=7,4 2006.145.13:36:49.36#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.13:36:49.36#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.13:36:49.36#ibcon#ireg 11 cls_cnt 2 2006.145.13:36:49.36#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.13:36:49.42#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.13:36:49.42#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.13:36:49.44#ibcon#[27=AT07-04\r\n] 2006.145.13:36:49.47#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.13:36:49.47#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.13:36:49.47#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.13:36:49.47#ibcon#ireg 7 cls_cnt 0 2006.145.13:36:49.47#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.13:36:49.59#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.13:36:49.59#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.13:36:49.61#ibcon#[27=USB\r\n] 2006.145.13:36:49.64#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.13:36:49.64#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.13:36:49.64#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.13:36:49.64#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.13:36:49.64$vck44/vblo=8,744.99 2006.145.13:36:49.64#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.13:36:49.64#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.13:36:49.64#ibcon#ireg 17 cls_cnt 0 2006.145.13:36:49.64#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.13:36:49.64#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.13:36:49.64#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.13:36:49.66#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.13:36:49.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.13:36:49.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.13:36:49.70#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.13:36:49.70#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.13:36:49.70$vck44/vb=8,4 2006.145.13:36:49.70#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.13:36:49.70#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.13:36:49.70#ibcon#ireg 11 cls_cnt 2 2006.145.13:36:49.70#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.13:36:49.76#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.13:36:49.76#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.13:36:49.78#ibcon#[27=AT08-04\r\n] 2006.145.13:36:49.81#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.13:36:49.81#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.13:36:49.81#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.13:36:49.81#ibcon#ireg 7 cls_cnt 0 2006.145.13:36:49.81#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.13:36:49.93#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.13:36:49.93#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.13:36:49.95#ibcon#[27=USB\r\n] 2006.145.13:36:49.98#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.13:36:49.98#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.13:36:49.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.13:36:49.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.13:36:49.98$vck44/vabw=wide 2006.145.13:36:49.98#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.13:36:49.98#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.13:36:49.98#ibcon#ireg 8 cls_cnt 0 2006.145.13:36:49.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.13:36:49.98#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.13:36:49.98#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.13:36:50.00#ibcon#[25=BW32\r\n] 2006.145.13:36:50.03#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.13:36:50.03#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.13:36:50.03#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.13:36:50.03#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.13:36:50.03$vck44/vbbw=wide 2006.145.13:36:50.03#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.13:36:50.03#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.13:36:50.03#ibcon#ireg 8 cls_cnt 0 2006.145.13:36:50.03#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.13:36:50.10#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.13:36:50.10#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.13:36:50.12#ibcon#[27=BW32\r\n] 2006.145.13:36:50.15#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.13:36:50.15#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.13:36:50.15#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.13:36:50.15#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.13:36:50.15$setupk4/ifdk4 2006.145.13:36:50.15$ifdk4/lo= 2006.145.13:36:50.15$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.13:36:50.15$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.13:36:50.15$ifdk4/patch= 2006.145.13:36:50.15$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.13:36:50.15$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.13:36:50.15$setupk4/!*+20s 2006.145.13:36:56.92#abcon#<5=/07 0.5 1.1 14.95 881020.8\r\n> 2006.145.13:36:56.94#abcon#{5=INTERFACE CLEAR} 2006.145.13:36:57.00#abcon#[5=S1D000X0/0*\r\n] 2006.145.13:36:57.14#trakl#Source acquired 2006.145.13:36:57.14#flagr#flagr/antenna,acquired 2006.145.13:37:04.64$setupk4/"tpicd 2006.145.13:37:04.64$setupk4/echo=off 2006.145.13:37:04.64$setupk4/xlog=off 2006.145.13:37:04.64:!2006.145.13:40:59 2006.145.13:40:59.00:preob 2006.145.13:40:59.13/onsource/TRACKING 2006.145.13:40:59.13:!2006.145.13:41:09 2006.145.13:41:09.00:"tape 2006.145.13:41:09.00:"st=record 2006.145.13:41:09.00:data_valid=on 2006.145.13:41:09.00:midob 2006.145.13:41:09.13/onsource/TRACKING 2006.145.13:41:09.13/wx/14.93,1020.7,91 2006.145.13:41:09.29/cable/+6.5505E-03 2006.145.13:41:10.38/va/01,08,usb,yes,29,31 2006.145.13:41:10.38/va/02,07,usb,yes,31,31 2006.145.13:41:10.38/va/03,08,usb,yes,28,29 2006.145.13:41:10.38/va/04,07,usb,yes,32,33 2006.145.13:41:10.38/va/05,04,usb,yes,28,28 2006.145.13:41:10.38/va/06,04,usb,yes,31,31 2006.145.13:41:10.38/va/07,04,usb,yes,31,32 2006.145.13:41:10.38/va/08,04,usb,yes,27,32 2006.145.13:41:10.61/valo/01,524.99,yes,locked 2006.145.13:41:10.61/valo/02,534.99,yes,locked 2006.145.13:41:10.61/valo/03,564.99,yes,locked 2006.145.13:41:10.61/valo/04,624.99,yes,locked 2006.145.13:41:10.61/valo/05,734.99,yes,locked 2006.145.13:41:10.61/valo/06,814.99,yes,locked 2006.145.13:41:10.61/valo/07,864.99,yes,locked 2006.145.13:41:10.61/valo/08,884.99,yes,locked 2006.145.13:41:11.70/vb/01,03,usb,yes,36,33 2006.145.13:41:11.70/vb/02,04,usb,yes,31,31 2006.145.13:41:11.70/vb/03,04,usb,yes,28,31 2006.145.13:41:11.70/vb/04,04,usb,yes,33,32 2006.145.13:41:11.70/vb/05,04,usb,yes,25,28 2006.145.13:41:11.70/vb/06,04,usb,yes,30,26 2006.145.13:41:11.70/vb/07,04,usb,yes,29,29 2006.145.13:41:11.70/vb/08,04,usb,yes,27,30 2006.145.13:41:11.93/vblo/01,629.99,yes,locked 2006.145.13:41:11.93/vblo/02,634.99,yes,locked 2006.145.13:41:11.93/vblo/03,649.99,yes,locked 2006.145.13:41:11.93/vblo/04,679.99,yes,locked 2006.145.13:41:11.93/vblo/05,709.99,yes,locked 2006.145.13:41:11.93/vblo/06,719.99,yes,locked 2006.145.13:41:11.93/vblo/07,734.99,yes,locked 2006.145.13:41:11.93/vblo/08,744.99,yes,locked 2006.145.13:41:12.08/vabw/8 2006.145.13:41:12.23/vbbw/8 2006.145.13:41:12.32/xfe/off,on,14.7 2006.145.13:41:12.70/ifatt/23,28,28,28 2006.145.13:41:13.07/fmout-gps/S +5.0E-08 2006.145.13:41:13.11:!2006.145.13:42:49 2006.145.13:42:49.00:data_valid=off 2006.145.13:42:49.00:"et 2006.145.13:42:49.00:!+3s 2006.145.13:42:52.02:"tape 2006.145.13:42:52.02:postob 2006.145.13:42:52.14/cable/+6.5487E-03 2006.145.13:42:52.14/wx/14.94,1020.7,90 2006.145.13:42:53.07/fmout-gps/S +5.1E-08 2006.145.13:42:53.07:scan_name=145-1344,jd0605,40 2006.145.13:42:53.08:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.145.13:42:54.14#flagr#flagr/antenna,new-source 2006.145.13:42:54.14:checkk5 2006.145.13:42:54.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.13:42:55.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.13:42:55.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.13:42:55.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.13:42:56.32/chk_obsdata//k5ts1/T1451341??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.13:42:56.76/chk_obsdata//k5ts2/T1451341??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.13:42:57.21/chk_obsdata//k5ts3/T1451341??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.13:42:57.69/chk_obsdata//k5ts4/T1451341??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.13:42:58.45/k5log//k5ts1_log_newline 2006.145.13:42:59.20/k5log//k5ts2_log_newline 2006.145.13:42:59.94/k5log//k5ts3_log_newline 2006.145.13:43:00.70/k5log//k5ts4_log_newline 2006.145.13:43:00.72/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.13:43:00.72:setupk4=1 2006.145.13:43:00.72$setupk4/echo=on 2006.145.13:43:00.72$setupk4/pcalon 2006.145.13:43:00.72$pcalon/"no phase cal control is implemented here 2006.145.13:43:00.72$setupk4/"tpicd=stop 2006.145.13:43:00.72$setupk4/"rec=synch_on 2006.145.13:43:00.72$setupk4/"rec_mode=128 2006.145.13:43:00.72$setupk4/!* 2006.145.13:43:00.72$setupk4/recpk4 2006.145.13:43:00.72$recpk4/recpatch= 2006.145.13:43:00.72$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.13:43:00.72$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.13:43:00.72$setupk4/vck44 2006.145.13:43:00.72$vck44/valo=1,524.99 2006.145.13:43:00.72#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.13:43:00.72#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.13:43:00.72#ibcon#ireg 17 cls_cnt 0 2006.145.13:43:00.72#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:43:00.72#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:43:00.72#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:43:00.76#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.13:43:00.81#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:43:00.81#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:43:00.81#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.13:43:00.81#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.13:43:00.81$vck44/va=1,8 2006.145.13:43:00.81#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.13:43:00.81#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.13:43:00.81#ibcon#ireg 11 cls_cnt 2 2006.145.13:43:00.81#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:43:00.81#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:43:00.81#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:43:00.83#ibcon#[25=AT01-08\r\n] 2006.145.13:43:00.86#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:43:00.86#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:43:00.86#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.13:43:00.86#ibcon#ireg 7 cls_cnt 0 2006.145.13:43:00.86#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:43:00.98#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:43:00.98#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:43:01.00#ibcon#[25=USB\r\n] 2006.145.13:43:01.03#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:43:01.03#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:43:01.03#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.13:43:01.03#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.13:43:01.03$vck44/valo=2,534.99 2006.145.13:43:01.03#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.13:43:01.03#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.13:43:01.03#ibcon#ireg 17 cls_cnt 0 2006.145.13:43:01.03#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:43:01.03#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:43:01.03#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:43:01.05#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.13:43:01.09#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:43:01.09#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:43:01.09#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.13:43:01.09#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.13:43:01.09$vck44/va=2,7 2006.145.13:43:01.09#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.13:43:01.09#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.13:43:01.09#ibcon#ireg 11 cls_cnt 2 2006.145.13:43:01.09#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:43:01.15#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:43:01.15#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:43:01.17#ibcon#[25=AT02-07\r\n] 2006.145.13:43:01.20#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:43:01.20#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:43:01.20#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.13:43:01.20#ibcon#ireg 7 cls_cnt 0 2006.145.13:43:01.20#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:43:01.32#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:43:01.32#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:43:01.34#ibcon#[25=USB\r\n] 2006.145.13:43:01.37#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:43:01.37#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:43:01.37#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.13:43:01.37#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.13:43:01.37$vck44/valo=3,564.99 2006.145.13:43:01.37#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.13:43:01.37#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.13:43:01.37#ibcon#ireg 17 cls_cnt 0 2006.145.13:43:01.37#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:43:01.37#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:43:01.37#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:43:01.39#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.13:43:01.43#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:43:01.43#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:43:01.43#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.13:43:01.43#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.13:43:01.43$vck44/va=3,8 2006.145.13:43:01.43#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.13:43:01.43#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.13:43:01.43#ibcon#ireg 11 cls_cnt 2 2006.145.13:43:01.43#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:43:01.49#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:43:01.49#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:43:01.51#ibcon#[25=AT03-08\r\n] 2006.145.13:43:01.54#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:43:01.54#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:43:01.54#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.13:43:01.54#ibcon#ireg 7 cls_cnt 0 2006.145.13:43:01.54#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:43:01.66#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:43:01.66#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:43:01.68#ibcon#[25=USB\r\n] 2006.145.13:43:01.71#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:43:01.71#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:43:01.71#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.13:43:01.71#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.13:43:01.71$vck44/valo=4,624.99 2006.145.13:43:01.71#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.13:43:01.71#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.13:43:01.71#ibcon#ireg 17 cls_cnt 0 2006.145.13:43:01.71#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:43:01.71#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:43:01.71#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:43:01.73#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.13:43:01.77#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:43:01.77#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:43:01.77#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.13:43:01.77#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.13:43:01.77$vck44/va=4,7 2006.145.13:43:01.77#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.13:43:01.77#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.13:43:01.77#ibcon#ireg 11 cls_cnt 2 2006.145.13:43:01.77#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.13:43:01.83#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.13:43:01.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.13:43:01.85#ibcon#[25=AT04-07\r\n] 2006.145.13:43:01.88#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.13:43:01.88#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.13:43:01.88#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.13:43:01.88#ibcon#ireg 7 cls_cnt 0 2006.145.13:43:01.88#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.13:43:02.00#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.13:43:02.00#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.13:43:02.03#ibcon#[25=USB\r\n] 2006.145.13:43:02.06#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.13:43:02.06#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.13:43:02.06#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.13:43:02.06#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.13:43:02.06$vck44/valo=5,734.99 2006.145.13:43:02.06#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.13:43:02.06#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.13:43:02.06#ibcon#ireg 17 cls_cnt 0 2006.145.13:43:02.06#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.13:43:02.06#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.13:43:02.06#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.13:43:02.08#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.13:43:02.12#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.13:43:02.12#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.13:43:02.12#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.13:43:02.12#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.13:43:02.12$vck44/va=5,4 2006.145.13:43:02.12#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.13:43:02.12#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.13:43:02.12#ibcon#ireg 11 cls_cnt 2 2006.145.13:43:02.12#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.13:43:02.18#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.13:43:02.18#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.13:43:02.20#ibcon#[25=AT05-04\r\n] 2006.145.13:43:02.24#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.13:43:02.24#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.13:43:02.24#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.13:43:02.24#ibcon#ireg 7 cls_cnt 0 2006.145.13:43:02.24#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.13:43:02.35#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.13:43:02.35#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.13:43:02.37#ibcon#[25=USB\r\n] 2006.145.13:43:02.40#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.13:43:02.40#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.13:43:02.40#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.13:43:02.40#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.13:43:02.40$vck44/valo=6,814.99 2006.145.13:43:02.40#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.13:43:02.40#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.13:43:02.40#ibcon#ireg 17 cls_cnt 0 2006.145.13:43:02.40#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:43:02.40#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:43:02.40#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:43:02.42#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.13:43:02.46#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:43:02.46#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:43:02.46#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.13:43:02.46#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.13:43:02.46$vck44/va=6,4 2006.145.13:43:02.46#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.13:43:02.46#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.13:43:02.46#ibcon#ireg 11 cls_cnt 2 2006.145.13:43:02.46#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.13:43:02.52#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.13:43:02.52#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.13:43:02.54#ibcon#[25=AT06-04\r\n] 2006.145.13:43:02.57#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.13:43:02.57#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.13:43:02.57#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.13:43:02.57#ibcon#ireg 7 cls_cnt 0 2006.145.13:43:02.57#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.13:43:02.69#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.13:43:02.69#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.13:43:02.71#ibcon#[25=USB\r\n] 2006.145.13:43:02.74#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.13:43:02.74#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.13:43:02.74#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.13:43:02.74#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.13:43:02.74$vck44/valo=7,864.99 2006.145.13:43:02.74#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.13:43:02.74#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.13:43:02.74#ibcon#ireg 17 cls_cnt 0 2006.145.13:43:02.74#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:43:02.74#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:43:02.74#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:43:02.76#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.13:43:02.80#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:43:02.80#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:43:02.80#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.13:43:02.80#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.13:43:02.80$vck44/va=7,4 2006.145.13:43:02.80#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.13:43:02.80#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.13:43:02.80#ibcon#ireg 11 cls_cnt 2 2006.145.13:43:02.80#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.13:43:02.86#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.13:43:02.86#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.13:43:02.88#ibcon#[25=AT07-04\r\n] 2006.145.13:43:02.91#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.13:43:02.91#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.13:43:02.91#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.13:43:02.91#ibcon#ireg 7 cls_cnt 0 2006.145.13:43:02.91#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.13:43:03.03#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.13:43:03.03#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.13:43:03.05#ibcon#[25=USB\r\n] 2006.145.13:43:03.08#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.13:43:03.08#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.13:43:03.08#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.13:43:03.08#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.13:43:03.08$vck44/valo=8,884.99 2006.145.13:43:03.08#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.13:43:03.08#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.13:43:03.08#ibcon#ireg 17 cls_cnt 0 2006.145.13:43:03.08#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.13:43:03.08#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.13:43:03.08#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.13:43:03.10#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.13:43:03.14#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.13:43:03.14#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.13:43:03.14#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.13:43:03.14#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.13:43:03.14$vck44/va=8,4 2006.145.13:43:03.14#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.13:43:03.14#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.13:43:03.14#ibcon#ireg 11 cls_cnt 2 2006.145.13:43:03.14#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.13:43:03.20#abcon#<5=/06 0.7 1.6 14.94 901020.7\r\n> 2006.145.13:43:03.20#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.13:43:03.20#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.13:43:03.22#ibcon#[25=AT08-04\r\n] 2006.145.13:43:03.22#abcon#{5=INTERFACE CLEAR} 2006.145.13:43:03.25#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.13:43:03.25#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.13:43:03.25#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.13:43:03.25#ibcon#ireg 7 cls_cnt 0 2006.145.13:43:03.25#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.13:43:03.29#abcon#[5=S1D000X0/0*\r\n] 2006.145.13:43:03.37#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.13:43:03.37#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.13:43:03.39#ibcon#[25=USB\r\n] 2006.145.13:43:03.42#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.13:43:03.42#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.13:43:03.42#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.13:43:03.42#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.13:43:03.42$vck44/vblo=1,629.99 2006.145.13:43:03.42#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.13:43:03.42#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.13:43:03.42#ibcon#ireg 17 cls_cnt 0 2006.145.13:43:03.42#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:43:03.42#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:43:03.42#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:43:03.44#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.13:43:03.48#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:43:03.48#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.13:43:03.48#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.13:43:03.48#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.13:43:03.48$vck44/vb=1,3 2006.145.13:43:03.48#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.13:43:03.48#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.13:43:03.48#ibcon#ireg 11 cls_cnt 2 2006.145.13:43:03.48#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:43:03.48#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:43:03.48#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:43:03.50#ibcon#[27=AT01-03\r\n] 2006.145.13:43:03.53#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:43:03.53#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.13:43:03.53#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.13:43:03.53#ibcon#ireg 7 cls_cnt 0 2006.145.13:43:03.53#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:43:03.65#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:43:03.65#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:43:03.67#ibcon#[27=USB\r\n] 2006.145.13:43:03.70#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:43:03.70#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.13:43:03.70#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.13:43:03.70#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.13:43:03.70$vck44/vblo=2,634.99 2006.145.13:43:03.70#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.13:43:03.70#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.13:43:03.70#ibcon#ireg 17 cls_cnt 0 2006.145.13:43:03.70#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:43:03.70#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:43:03.70#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:43:03.72#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.13:43:03.76#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:43:03.76#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.13:43:03.76#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.13:43:03.76#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.13:43:03.76$vck44/vb=2,4 2006.145.13:43:03.76#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.13:43:03.76#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.13:43:03.76#ibcon#ireg 11 cls_cnt 2 2006.145.13:43:03.76#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:43:03.82#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:43:03.82#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:43:03.84#ibcon#[27=AT02-04\r\n] 2006.145.13:43:03.87#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:43:03.87#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.13:43:03.87#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.13:43:03.87#ibcon#ireg 7 cls_cnt 0 2006.145.13:43:03.87#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:43:03.99#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:43:03.99#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:43:04.01#ibcon#[27=USB\r\n] 2006.145.13:43:04.04#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:43:04.04#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.13:43:04.04#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.13:43:04.04#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.13:43:04.04$vck44/vblo=3,649.99 2006.145.13:43:04.04#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.13:43:04.04#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.13:43:04.04#ibcon#ireg 17 cls_cnt 0 2006.145.13:43:04.04#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:43:04.04#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:43:04.04#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:43:04.06#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.13:43:04.10#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:43:04.10#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.13:43:04.10#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.13:43:04.10#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.13:43:04.10$vck44/vb=3,4 2006.145.13:43:04.10#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.13:43:04.10#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.13:43:04.10#ibcon#ireg 11 cls_cnt 2 2006.145.13:43:04.10#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:43:04.16#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:43:04.16#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:43:04.18#ibcon#[27=AT03-04\r\n] 2006.145.13:43:04.21#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:43:04.21#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.13:43:04.21#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.13:43:04.21#ibcon#ireg 7 cls_cnt 0 2006.145.13:43:04.21#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:43:04.33#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:43:04.33#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:43:04.35#ibcon#[27=USB\r\n] 2006.145.13:43:04.38#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:43:04.38#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.13:43:04.38#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.13:43:04.38#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.13:43:04.38$vck44/vblo=4,679.99 2006.145.13:43:04.38#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.13:43:04.38#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.13:43:04.38#ibcon#ireg 17 cls_cnt 0 2006.145.13:43:04.38#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:43:04.38#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:43:04.38#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:43:04.40#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.13:43:04.44#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:43:04.44#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.13:43:04.44#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.13:43:04.44#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.13:43:04.44$vck44/vb=4,4 2006.145.13:43:04.44#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.13:43:04.44#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.13:43:04.44#ibcon#ireg 11 cls_cnt 2 2006.145.13:43:04.44#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.13:43:04.50#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.13:43:04.50#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.13:43:04.52#ibcon#[27=AT04-04\r\n] 2006.145.13:43:04.55#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.13:43:04.55#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.13:43:04.55#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.13:43:04.55#ibcon#ireg 7 cls_cnt 0 2006.145.13:43:04.55#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.13:43:04.67#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.13:43:04.67#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.13:43:04.69#ibcon#[27=USB\r\n] 2006.145.13:43:04.72#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.13:43:04.72#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.13:43:04.72#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.13:43:04.72#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.13:43:04.72$vck44/vblo=5,709.99 2006.145.13:43:04.72#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.13:43:04.72#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.13:43:04.72#ibcon#ireg 17 cls_cnt 0 2006.145.13:43:04.72#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.13:43:04.72#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.13:43:04.72#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.13:43:04.74#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.13:43:04.78#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.13:43:04.78#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.13:43:04.78#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.13:43:04.78#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.13:43:04.78$vck44/vb=5,4 2006.145.13:43:04.78#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.13:43:04.78#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.13:43:04.78#ibcon#ireg 11 cls_cnt 2 2006.145.13:43:04.78#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.13:43:04.84#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.13:43:04.84#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.13:43:04.86#ibcon#[27=AT05-04\r\n] 2006.145.13:43:04.89#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.13:43:04.89#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.13:43:04.89#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.13:43:04.89#ibcon#ireg 7 cls_cnt 0 2006.145.13:43:04.89#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.13:43:05.01#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.13:43:05.01#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.13:43:05.03#ibcon#[27=USB\r\n] 2006.145.13:43:05.06#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.13:43:05.06#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.13:43:05.06#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.13:43:05.06#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.13:43:05.06$vck44/vblo=6,719.99 2006.145.13:43:05.06#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.13:43:05.06#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.13:43:05.06#ibcon#ireg 17 cls_cnt 0 2006.145.13:43:05.06#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:43:05.06#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:43:05.06#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:43:05.08#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.13:43:05.12#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:43:05.12#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:43:05.12#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.13:43:05.12#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.13:43:05.12$vck44/vb=6,4 2006.145.13:43:05.12#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.13:43:05.12#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.13:43:05.12#ibcon#ireg 11 cls_cnt 2 2006.145.13:43:05.12#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.13:43:05.18#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.13:43:05.18#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.13:43:05.20#ibcon#[27=AT06-04\r\n] 2006.145.13:43:05.23#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.13:43:05.23#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.13:43:05.23#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.13:43:05.23#ibcon#ireg 7 cls_cnt 0 2006.145.13:43:05.23#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.13:43:05.35#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.13:43:05.35#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.13:43:05.37#ibcon#[27=USB\r\n] 2006.145.13:43:05.40#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.13:43:05.40#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.13:43:05.40#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.13:43:05.40#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.13:43:05.40$vck44/vblo=7,734.99 2006.145.13:43:05.40#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.13:43:05.40#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.13:43:05.40#ibcon#ireg 17 cls_cnt 0 2006.145.13:43:05.40#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:43:05.40#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:43:05.40#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:43:05.42#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.13:43:05.46#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:43:05.46#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.13:43:05.46#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.13:43:05.46#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.13:43:05.46$vck44/vb=7,4 2006.145.13:43:05.46#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.13:43:05.46#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.13:43:05.46#ibcon#ireg 11 cls_cnt 2 2006.145.13:43:05.46#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.13:43:05.52#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.13:43:05.52#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.13:43:05.54#ibcon#[27=AT07-04\r\n] 2006.145.13:43:05.57#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.13:43:05.57#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.13:43:05.57#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.13:43:05.57#ibcon#ireg 7 cls_cnt 0 2006.145.13:43:05.57#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.13:43:05.69#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.13:43:05.69#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.13:43:05.71#ibcon#[27=USB\r\n] 2006.145.13:43:05.74#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.13:43:05.74#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.13:43:05.74#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.13:43:05.74#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.13:43:05.74$vck44/vblo=8,744.99 2006.145.13:43:05.74#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.13:43:05.74#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.13:43:05.74#ibcon#ireg 17 cls_cnt 0 2006.145.13:43:05.74#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.13:43:05.74#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.13:43:05.74#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.13:43:05.76#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.13:43:05.80#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.13:43:05.80#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.13:43:05.80#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.13:43:05.80#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.13:43:05.80$vck44/vb=8,4 2006.145.13:43:05.80#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.13:43:05.80#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.13:43:05.80#ibcon#ireg 11 cls_cnt 2 2006.145.13:43:05.80#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.13:43:05.86#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.13:43:05.86#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.13:43:05.88#ibcon#[27=AT08-04\r\n] 2006.145.13:43:05.91#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.13:43:05.91#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.13:43:05.91#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.13:43:05.91#ibcon#ireg 7 cls_cnt 0 2006.145.13:43:05.91#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.13:43:06.03#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.13:43:06.03#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.13:43:06.05#ibcon#[27=USB\r\n] 2006.145.13:43:06.08#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.13:43:06.08#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.13:43:06.08#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.13:43:06.08#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.13:43:06.08$vck44/vabw=wide 2006.145.13:43:06.08#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.13:43:06.08#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.13:43:06.08#ibcon#ireg 8 cls_cnt 0 2006.145.13:43:06.08#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:43:06.08#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:43:06.08#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:43:06.10#ibcon#[25=BW32\r\n] 2006.145.13:43:06.13#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:43:06.13#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.13:43:06.13#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.13:43:06.13#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.13:43:06.13$vck44/vbbw=wide 2006.145.13:43:06.13#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.13:43:06.13#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.13:43:06.13#ibcon#ireg 8 cls_cnt 0 2006.145.13:43:06.13#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:43:06.20#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:43:06.20#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:43:06.22#ibcon#[27=BW32\r\n] 2006.145.13:43:06.25#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:43:06.25#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:43:06.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.13:43:06.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.13:43:06.25$setupk4/ifdk4 2006.145.13:43:06.25$ifdk4/lo= 2006.145.13:43:06.25$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.13:43:06.25$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.13:43:06.25$ifdk4/patch= 2006.145.13:43:06.25$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.13:43:06.25$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.13:43:06.25$setupk4/!*+20s 2006.145.13:43:13.38#abcon#<5=/06 0.7 1.6 14.94 901020.7\r\n> 2006.145.13:43:13.40#abcon#{5=INTERFACE CLEAR} 2006.145.13:43:13.46#abcon#[5=S1D000X0/0*\r\n] 2006.145.13:43:20.73$setupk4/"tpicd 2006.145.13:43:20.73$setupk4/echo=off 2006.145.13:43:20.73$setupk4/xlog=off 2006.145.13:43:20.73:!2006.145.13:44:19 2006.145.13:43:30.14#trakl#Source acquired 2006.145.13:43:31.14#flagr#flagr/antenna,acquired 2006.145.13:44:19.00:preob 2006.145.13:44:20.14/onsource/TRACKING 2006.145.13:44:20.14:!2006.145.13:44:29 2006.145.13:44:29.00:"tape 2006.145.13:44:29.00:"st=record 2006.145.13:44:29.00:data_valid=on 2006.145.13:44:29.00:midob 2006.145.13:44:29.14/onsource/TRACKING 2006.145.13:44:29.14/wx/14.94,1020.7,90 2006.145.13:44:29.30/cable/+6.5496E-03 2006.145.13:44:30.39/va/01,08,usb,yes,28,31 2006.145.13:44:30.39/va/02,07,usb,yes,30,31 2006.145.13:44:30.39/va/03,08,usb,yes,28,29 2006.145.13:44:30.39/va/04,07,usb,yes,32,33 2006.145.13:44:30.39/va/05,04,usb,yes,27,28 2006.145.13:44:30.39/va/06,04,usb,yes,31,31 2006.145.13:44:30.39/va/07,04,usb,yes,31,32 2006.145.13:44:30.39/va/08,04,usb,yes,27,32 2006.145.13:44:30.62/valo/01,524.99,yes,locked 2006.145.13:44:30.62/valo/02,534.99,yes,locked 2006.145.13:44:30.62/valo/03,564.99,yes,locked 2006.145.13:44:30.62/valo/04,624.99,yes,locked 2006.145.13:44:30.62/valo/05,734.99,yes,locked 2006.145.13:44:30.62/valo/06,814.99,yes,locked 2006.145.13:44:30.62/valo/07,864.99,yes,locked 2006.145.13:44:30.62/valo/08,884.99,yes,locked 2006.145.13:44:31.71/vb/01,03,usb,yes,36,34 2006.145.13:44:31.71/vb/02,04,usb,yes,32,31 2006.145.13:44:31.71/vb/03,04,usb,yes,29,31 2006.145.13:44:31.71/vb/04,04,usb,yes,33,32 2006.145.13:44:31.71/vb/05,04,usb,yes,25,28 2006.145.13:44:31.71/vb/06,04,usb,yes,30,26 2006.145.13:44:31.71/vb/07,04,usb,yes,29,29 2006.145.13:44:31.71/vb/08,04,usb,yes,27,30 2006.145.13:44:31.95/vblo/01,629.99,yes,locked 2006.145.13:44:31.95/vblo/02,634.99,yes,locked 2006.145.13:44:31.95/vblo/03,649.99,yes,locked 2006.145.13:44:31.95/vblo/04,679.99,yes,locked 2006.145.13:44:31.95/vblo/05,709.99,yes,locked 2006.145.13:44:31.95/vblo/06,719.99,yes,locked 2006.145.13:44:31.95/vblo/07,734.99,yes,locked 2006.145.13:44:31.95/vblo/08,744.99,yes,locked 2006.145.13:44:32.10/vabw/8 2006.145.13:44:32.25/vbbw/8 2006.145.13:44:32.42/xfe/off,on,14.0 2006.145.13:44:32.82/ifatt/23,28,28,28 2006.145.13:44:33.07/fmout-gps/S +5.0E-08 2006.145.13:44:33.11:!2006.145.13:45:09 2006.145.13:45:09.00:data_valid=off 2006.145.13:45:09.00:"et 2006.145.13:45:09.00:!+3s 2006.145.13:45:12.02:"tape 2006.145.13:45:12.02:postob 2006.145.13:45:12.18/cable/+6.5469E-03 2006.145.13:45:12.22/wx/14.93,1020.7,89 2006.145.13:45:13.08/fmout-gps/S +5.0E-08 2006.145.13:45:13.08:scan_name=145-1346,jd0605,784 2006.145.13:45:13.08:source=1749+096,175132.82,093900.7,2000.0,cw 2006.145.13:45:14.14#flagr#flagr/antenna,new-source 2006.145.13:45:14.14:checkk5 2006.145.13:45:14.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.13:45:15.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.13:45:15.43/chk_autoobs//k5ts3/ autoobs is running! 2006.145.13:45:15.86/chk_autoobs//k5ts4/ autoobs is running! 2006.145.13:45:16.28/chk_obsdata//k5ts1/T1451344??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.13:45:16.72/chk_obsdata//k5ts2/T1451344??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.13:45:17.16/chk_obsdata//k5ts3/T1451344??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.13:45:17.59/chk_obsdata//k5ts4/T1451344??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.13:45:18.35/k5log//k5ts1_log_newline 2006.145.13:45:19.10/k5log//k5ts2_log_newline 2006.145.13:45:19.84/k5log//k5ts3_log_newline 2006.145.13:45:20.58/k5log//k5ts4_log_newline 2006.145.13:45:20.61/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.13:45:20.61:setupk4=1 2006.145.13:45:20.61$setupk4/echo=on 2006.145.13:45:20.61$setupk4/pcalon 2006.145.13:45:20.61$pcalon/"no phase cal control is implemented here 2006.145.13:45:20.61$setupk4/"tpicd=stop 2006.145.13:45:20.61$setupk4/"rec=synch_on 2006.145.13:45:20.61$setupk4/"rec_mode=128 2006.145.13:45:20.61$setupk4/!* 2006.145.13:45:20.61$setupk4/recpk4 2006.145.13:45:20.61$recpk4/recpatch= 2006.145.13:45:20.61$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.13:45:20.61$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.13:45:20.61$setupk4/vck44 2006.145.13:45:20.61$vck44/valo=1,524.99 2006.145.13:45:20.61#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.13:45:20.61#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.13:45:20.61#ibcon#ireg 17 cls_cnt 0 2006.145.13:45:20.61#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.13:45:20.61#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.13:45:20.61#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.13:45:20.63#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.13:45:20.68#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.13:45:20.68#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.13:45:20.68#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.13:45:20.68#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.13:45:20.68$vck44/va=1,8 2006.145.13:45:20.68#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.13:45:20.68#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.13:45:20.68#ibcon#ireg 11 cls_cnt 2 2006.145.13:45:20.68#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.13:45:20.68#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.13:45:20.68#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.13:45:20.70#ibcon#[25=AT01-08\r\n] 2006.145.13:45:20.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.13:45:20.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.13:45:20.73#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.13:45:20.73#ibcon#ireg 7 cls_cnt 0 2006.145.13:45:20.73#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.13:45:20.85#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.13:45:20.85#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.13:45:20.87#ibcon#[25=USB\r\n] 2006.145.13:45:20.91#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.13:45:20.91#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.13:45:20.91#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.13:45:20.91#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.13:45:20.92$vck44/valo=2,534.99 2006.145.13:45:20.92#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.13:45:20.92#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.13:45:20.92#ibcon#ireg 17 cls_cnt 0 2006.145.13:45:20.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.13:45:20.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.13:45:20.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.13:45:20.93#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.13:45:20.97#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.13:45:20.97#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.13:45:20.97#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.13:45:20.97#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.13:45:20.97$vck44/va=2,7 2006.145.13:45:20.97#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.13:45:20.97#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.13:45:20.97#ibcon#ireg 11 cls_cnt 2 2006.145.13:45:20.97#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.13:45:21.03#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.13:45:21.03#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.13:45:21.05#ibcon#[25=AT02-07\r\n] 2006.145.13:45:21.08#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.13:45:21.08#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.13:45:21.08#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.13:45:21.08#ibcon#ireg 7 cls_cnt 0 2006.145.13:45:21.08#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.13:45:21.20#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.13:45:21.20#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.13:45:21.22#ibcon#[25=USB\r\n] 2006.145.13:45:21.25#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.13:45:21.25#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.13:45:21.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.13:45:21.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.13:45:21.25$vck44/valo=3,564.99 2006.145.13:45:21.25#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.13:45:21.25#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.13:45:21.25#ibcon#ireg 17 cls_cnt 0 2006.145.13:45:21.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.13:45:21.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.13:45:21.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.13:45:21.27#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.13:45:21.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.13:45:21.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.13:45:21.31#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.13:45:21.31#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.13:45:21.31$vck44/va=3,8 2006.145.13:45:21.31#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.13:45:21.31#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.13:45:21.31#ibcon#ireg 11 cls_cnt 2 2006.145.13:45:21.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.13:45:21.37#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.13:45:21.37#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.13:45:21.39#ibcon#[25=AT03-08\r\n] 2006.145.13:45:21.42#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.13:45:21.42#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.13:45:21.42#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.13:45:21.42#ibcon#ireg 7 cls_cnt 0 2006.145.13:45:21.42#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.13:45:21.54#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.13:45:21.54#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.13:45:21.56#ibcon#[25=USB\r\n] 2006.145.13:45:21.59#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.13:45:21.59#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.13:45:21.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.13:45:21.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.13:45:21.59$vck44/valo=4,624.99 2006.145.13:45:21.59#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.13:45:21.59#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.13:45:21.59#ibcon#ireg 17 cls_cnt 0 2006.145.13:45:21.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.13:45:21.59#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.13:45:21.59#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.13:45:21.61#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.13:45:21.65#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.13:45:21.65#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.13:45:21.65#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.13:45:21.65#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.13:45:21.65$vck44/va=4,7 2006.145.13:45:21.65#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.13:45:21.65#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.13:45:21.65#ibcon#ireg 11 cls_cnt 2 2006.145.13:45:21.65#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.13:45:21.71#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.13:45:21.71#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.13:45:21.73#ibcon#[25=AT04-07\r\n] 2006.145.13:45:21.76#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.13:45:21.76#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.13:45:21.76#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.13:45:21.76#ibcon#ireg 7 cls_cnt 0 2006.145.13:45:21.76#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.13:45:21.88#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.13:45:21.88#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.13:45:21.90#ibcon#[25=USB\r\n] 2006.145.13:45:21.93#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.13:45:21.93#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.13:45:21.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.13:45:21.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.13:45:21.93$vck44/valo=5,734.99 2006.145.13:45:21.93#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.13:45:21.93#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.13:45:21.93#ibcon#ireg 17 cls_cnt 0 2006.145.13:45:21.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.13:45:21.93#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.13:45:21.93#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.13:45:21.95#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.13:45:21.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.13:45:21.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.13:45:21.99#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.13:45:21.99#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.13:45:21.99$vck44/va=5,4 2006.145.13:45:21.99#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.13:45:21.99#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.13:45:21.99#ibcon#ireg 11 cls_cnt 2 2006.145.13:45:21.99#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.13:45:22.05#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.13:45:22.05#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.13:45:22.07#ibcon#[25=AT05-04\r\n] 2006.145.13:45:22.10#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.13:45:22.10#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.13:45:22.10#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.13:45:22.10#ibcon#ireg 7 cls_cnt 0 2006.145.13:45:22.10#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.13:45:22.22#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.13:45:22.22#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.13:45:22.24#ibcon#[25=USB\r\n] 2006.145.13:45:22.27#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.13:45:22.27#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.13:45:22.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.13:45:22.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.13:45:22.27$vck44/valo=6,814.99 2006.145.13:45:22.27#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.13:45:22.27#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.13:45:22.27#ibcon#ireg 17 cls_cnt 0 2006.145.13:45:22.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.13:45:22.27#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.13:45:22.27#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.13:45:22.30#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.13:45:22.34#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.13:45:22.34#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.13:45:22.34#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.13:45:22.34#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.13:45:22.34$vck44/va=6,4 2006.145.13:45:22.34#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.13:45:22.34#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.13:45:22.34#ibcon#ireg 11 cls_cnt 2 2006.145.13:45:22.34#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.13:45:22.39#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.13:45:22.39#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.13:45:22.41#ibcon#[25=AT06-04\r\n] 2006.145.13:45:22.44#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.13:45:22.44#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.13:45:22.44#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.13:45:22.44#ibcon#ireg 7 cls_cnt 0 2006.145.13:45:22.44#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.13:45:22.56#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.13:45:22.56#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.13:45:22.58#ibcon#[25=USB\r\n] 2006.145.13:45:22.61#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.13:45:22.61#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.13:45:22.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.13:45:22.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.13:45:22.61$vck44/valo=7,864.99 2006.145.13:45:22.61#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.13:45:22.61#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.13:45:22.61#ibcon#ireg 17 cls_cnt 0 2006.145.13:45:22.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.13:45:22.61#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.13:45:22.61#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.13:45:22.63#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.13:45:22.67#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.13:45:22.67#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.13:45:22.67#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.13:45:22.67#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.13:45:22.67$vck44/va=7,4 2006.145.13:45:22.67#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.13:45:22.67#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.13:45:22.67#ibcon#ireg 11 cls_cnt 2 2006.145.13:45:22.67#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.13:45:22.73#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.13:45:22.73#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.13:45:22.75#ibcon#[25=AT07-04\r\n] 2006.145.13:45:22.78#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.13:45:22.78#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.13:45:22.78#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.13:45:22.78#ibcon#ireg 7 cls_cnt 0 2006.145.13:45:22.78#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.13:45:22.90#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.13:45:22.90#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.13:45:22.92#ibcon#[25=USB\r\n] 2006.145.13:45:22.95#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.13:45:22.95#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.13:45:22.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.13:45:22.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.13:45:22.95$vck44/valo=8,884.99 2006.145.13:45:22.95#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.13:45:22.95#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.13:45:22.95#ibcon#ireg 17 cls_cnt 0 2006.145.13:45:22.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.13:45:22.95#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.13:45:22.95#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.13:45:22.97#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.13:45:23.01#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.13:45:23.01#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.13:45:23.01#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.13:45:23.01#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.13:45:23.01$vck44/va=8,4 2006.145.13:45:23.01#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.13:45:23.01#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.13:45:23.01#ibcon#ireg 11 cls_cnt 2 2006.145.13:45:23.01#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.13:45:23.07#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.13:45:23.07#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.13:45:23.09#ibcon#[25=AT08-04\r\n] 2006.145.13:45:23.12#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.13:45:23.12#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.13:45:23.12#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.13:45:23.12#ibcon#ireg 7 cls_cnt 0 2006.145.13:45:23.12#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.13:45:23.24#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.13:45:23.24#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.13:45:23.26#ibcon#[25=USB\r\n] 2006.145.13:45:23.29#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.13:45:23.29#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.13:45:23.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.13:45:23.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.13:45:23.29$vck44/vblo=1,629.99 2006.145.13:45:23.29#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.13:45:23.29#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.13:45:23.29#ibcon#ireg 17 cls_cnt 0 2006.145.13:45:23.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.13:45:23.29#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.13:45:23.29#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.13:45:23.31#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.13:45:23.35#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.13:45:23.35#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.13:45:23.35#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.13:45:23.35#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.13:45:23.35$vck44/vb=1,3 2006.145.13:45:23.35#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.13:45:23.35#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.13:45:23.35#ibcon#ireg 11 cls_cnt 2 2006.145.13:45:23.35#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.13:45:23.35#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.13:45:23.35#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.13:45:23.37#ibcon#[27=AT01-03\r\n] 2006.145.13:45:23.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.13:45:23.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.13:45:23.40#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.13:45:23.40#ibcon#ireg 7 cls_cnt 0 2006.145.13:45:23.40#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.13:45:23.52#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.13:45:23.52#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.13:45:23.54#ibcon#[27=USB\r\n] 2006.145.13:45:23.57#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.13:45:23.57#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.13:45:23.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.13:45:23.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.13:45:23.57$vck44/vblo=2,634.99 2006.145.13:45:23.57#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.13:45:23.57#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.13:45:23.57#ibcon#ireg 17 cls_cnt 0 2006.145.13:45:23.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.13:45:23.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.13:45:23.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.13:45:23.59#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.13:45:23.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.13:45:23.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.13:45:23.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.13:45:23.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.13:45:23.63$vck44/vb=2,4 2006.145.13:45:23.63#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.13:45:23.63#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.13:45:23.63#ibcon#ireg 11 cls_cnt 2 2006.145.13:45:23.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.13:45:23.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.13:45:23.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.13:45:23.71#ibcon#[27=AT02-04\r\n] 2006.145.13:45:23.74#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.13:45:23.74#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.13:45:23.74#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.13:45:23.74#ibcon#ireg 7 cls_cnt 0 2006.145.13:45:23.74#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.13:45:23.86#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.13:45:23.86#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.13:45:23.88#ibcon#[27=USB\r\n] 2006.145.13:45:23.91#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.13:45:23.91#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.13:45:23.91#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.13:45:23.91#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.13:45:23.91$vck44/vblo=3,649.99 2006.145.13:45:23.91#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.13:45:23.91#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.13:45:23.91#ibcon#ireg 17 cls_cnt 0 2006.145.13:45:23.91#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.13:45:23.91#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.13:45:23.91#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.13:45:23.93#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.13:45:23.97#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.13:45:23.97#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.13:45:23.97#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.13:45:23.97#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.13:45:23.97$vck44/vb=3,4 2006.145.13:45:23.97#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.13:45:23.97#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.13:45:23.97#ibcon#ireg 11 cls_cnt 2 2006.145.13:45:23.97#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.13:45:24.03#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.13:45:24.03#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.13:45:24.05#ibcon#[27=AT03-04\r\n] 2006.145.13:45:24.08#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.13:45:24.08#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.13:45:24.08#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.13:45:24.08#ibcon#ireg 7 cls_cnt 0 2006.145.13:45:24.08#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.13:45:24.20#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.13:45:24.20#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.13:45:24.22#ibcon#[27=USB\r\n] 2006.145.13:45:24.25#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.13:45:24.25#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.13:45:24.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.13:45:24.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.13:45:24.25$vck44/vblo=4,679.99 2006.145.13:45:24.25#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.13:45:24.25#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.13:45:24.25#ibcon#ireg 17 cls_cnt 0 2006.145.13:45:24.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.13:45:24.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.13:45:24.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.13:45:24.27#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.13:45:24.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.13:45:24.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.13:45:24.31#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.13:45:24.31#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.13:45:24.31$vck44/vb=4,4 2006.145.13:45:24.31#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.13:45:24.31#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.13:45:24.31#ibcon#ireg 11 cls_cnt 2 2006.145.13:45:24.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.13:45:24.37#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.13:45:24.37#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.13:45:24.39#ibcon#[27=AT04-04\r\n] 2006.145.13:45:24.42#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.13:45:24.42#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.13:45:24.42#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.13:45:24.42#ibcon#ireg 7 cls_cnt 0 2006.145.13:45:24.42#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.13:45:24.54#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.13:45:24.54#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.13:45:24.56#ibcon#[27=USB\r\n] 2006.145.13:45:24.59#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.13:45:24.59#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.13:45:24.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.13:45:24.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.13:45:24.59$vck44/vblo=5,709.99 2006.145.13:45:24.59#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.13:45:24.59#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.13:45:24.59#ibcon#ireg 17 cls_cnt 0 2006.145.13:45:24.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.13:45:24.59#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.13:45:24.59#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.13:45:24.61#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.13:45:24.65#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.13:45:24.65#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.13:45:24.65#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.13:45:24.65#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.13:45:24.65$vck44/vb=5,4 2006.145.13:45:24.65#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.13:45:24.65#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.13:45:24.65#ibcon#ireg 11 cls_cnt 2 2006.145.13:45:24.65#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.13:45:24.71#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.13:45:24.71#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.13:45:24.73#ibcon#[27=AT05-04\r\n] 2006.145.13:45:24.76#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.13:45:24.76#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.13:45:24.76#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.13:45:24.76#ibcon#ireg 7 cls_cnt 0 2006.145.13:45:24.76#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.13:45:24.88#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.13:45:24.88#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.13:45:24.90#ibcon#[27=USB\r\n] 2006.145.13:45:24.93#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.13:45:24.93#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.13:45:24.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.13:45:24.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.13:45:24.93$vck44/vblo=6,719.99 2006.145.13:45:24.93#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.13:45:24.93#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.13:45:24.93#ibcon#ireg 17 cls_cnt 0 2006.145.13:45:24.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.13:45:24.93#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.13:45:24.93#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.13:45:24.95#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.13:45:24.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.13:45:24.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.13:45:24.99#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.13:45:24.99#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.13:45:24.99$vck44/vb=6,4 2006.145.13:45:24.99#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.13:45:24.99#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.13:45:24.99#ibcon#ireg 11 cls_cnt 2 2006.145.13:45:24.99#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.13:45:25.05#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.13:45:25.05#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.13:45:25.07#ibcon#[27=AT06-04\r\n] 2006.145.13:45:25.10#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.13:45:25.10#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.13:45:25.10#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.13:45:25.10#ibcon#ireg 7 cls_cnt 0 2006.145.13:45:25.10#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.13:45:25.22#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.13:45:25.22#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.13:45:25.24#ibcon#[27=USB\r\n] 2006.145.13:45:25.27#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.13:45:25.27#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.13:45:25.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.13:45:25.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.13:45:25.27$vck44/vblo=7,734.99 2006.145.13:45:25.27#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.13:45:25.27#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.13:45:25.27#ibcon#ireg 17 cls_cnt 0 2006.145.13:45:25.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.13:45:25.27#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.13:45:25.27#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.13:45:25.29#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.13:45:25.33#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.13:45:25.33#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.13:45:25.33#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.13:45:25.33#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.13:45:25.33$vck44/vb=7,4 2006.145.13:45:25.33#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.13:45:25.33#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.13:45:25.33#ibcon#ireg 11 cls_cnt 2 2006.145.13:45:25.33#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.13:45:25.39#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.13:45:25.39#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.13:45:25.41#ibcon#[27=AT07-04\r\n] 2006.145.13:45:25.44#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.13:45:25.44#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.13:45:25.44#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.13:45:25.44#ibcon#ireg 7 cls_cnt 0 2006.145.13:45:25.44#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.13:45:25.56#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.13:45:25.56#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.13:45:25.58#ibcon#[27=USB\r\n] 2006.145.13:45:25.61#abcon#<5=/06 0.7 1.6 14.93 891020.7\r\n> 2006.145.13:45:25.61#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.13:45:25.61#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.13:45:25.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.13:45:25.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.13:45:25.61$vck44/vblo=8,744.99 2006.145.13:45:25.61#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.13:45:25.61#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.13:45:25.61#ibcon#ireg 17 cls_cnt 0 2006.145.13:45:25.61#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:45:25.61#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:45:25.61#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:45:25.63#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.13:45:25.63#abcon#{5=INTERFACE CLEAR} 2006.145.13:45:25.67#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:45:25.67#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:45:25.67#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.13:45:25.67#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.13:45:25.67$vck44/vb=8,4 2006.145.13:45:25.67#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.13:45:25.67#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.13:45:25.67#ibcon#ireg 11 cls_cnt 2 2006.145.13:45:25.67#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:45:25.69#abcon#[5=S1D000X0/0*\r\n] 2006.145.13:45:25.73#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:45:25.73#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:45:25.75#ibcon#[27=AT08-04\r\n] 2006.145.13:45:25.78#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:45:25.78#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:45:25.78#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.13:45:25.78#ibcon#ireg 7 cls_cnt 0 2006.145.13:45:25.78#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:45:25.90#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:45:25.90#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:45:25.92#ibcon#[27=USB\r\n] 2006.145.13:45:25.95#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:45:25.95#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:45:25.95#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.13:45:25.95#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.13:45:25.95$vck44/vabw=wide 2006.145.13:45:25.95#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.13:45:25.95#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.13:45:25.95#ibcon#ireg 8 cls_cnt 0 2006.145.13:45:25.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.13:45:25.95#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.13:45:25.95#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.13:45:25.97#ibcon#[25=BW32\r\n] 2006.145.13:45:26.00#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.13:45:26.00#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.13:45:26.00#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.13:45:26.00#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.13:45:26.00$vck44/vbbw=wide 2006.145.13:45:26.00#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.13:45:26.00#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.13:45:26.00#ibcon#ireg 8 cls_cnt 0 2006.145.13:45:26.00#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.13:45:26.07#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.13:45:26.07#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.13:45:26.09#ibcon#[27=BW32\r\n] 2006.145.13:45:26.12#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.13:45:26.12#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.13:45:26.12#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.13:45:26.12#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.13:45:26.12$setupk4/ifdk4 2006.145.13:45:26.12$ifdk4/lo= 2006.145.13:45:26.12$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.13:45:26.12$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.13:45:26.12$ifdk4/patch= 2006.145.13:45:26.12$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.13:45:26.12$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.13:45:26.12$setupk4/!*+20s 2006.145.13:45:28.14#trakl#Source acquired 2006.145.13:45:30.14#flagr#flagr/antenna,acquired 2006.145.13:45:35.78#abcon#<5=/06 0.7 1.6 14.93 891020.7\r\n> 2006.145.13:45:35.80#abcon#{5=INTERFACE CLEAR} 2006.145.13:45:35.86#abcon#[5=S1D000X0/0*\r\n] 2006.145.13:45:40.62$setupk4/"tpicd 2006.145.13:45:40.62$setupk4/echo=off 2006.145.13:45:40.62$setupk4/xlog=off 2006.145.13:45:40.62:!2006.145.13:45:55 2006.145.13:45:55.00:preob 2006.145.13:45:55.14/onsource/TRACKING 2006.145.13:45:55.14:!2006.145.13:46:05 2006.145.13:46:05.00:"tape 2006.145.13:46:05.00:"st=record 2006.145.13:46:05.00:data_valid=on 2006.145.13:46:05.00:midob 2006.145.13:46:06.14/onsource/TRACKING 2006.145.13:46:06.14/wx/14.92,1020.7,89 2006.145.13:46:06.25/cable/+6.5499E-03 2006.145.13:46:07.34/va/01,08,usb,yes,28,30 2006.145.13:46:07.34/va/02,07,usb,yes,30,31 2006.145.13:46:07.34/va/03,08,usb,yes,27,28 2006.145.13:46:07.34/va/04,07,usb,yes,31,33 2006.145.13:46:07.34/va/05,04,usb,yes,27,27 2006.145.13:46:07.34/va/06,04,usb,yes,30,30 2006.145.13:46:07.34/va/07,04,usb,yes,31,32 2006.145.13:46:07.34/va/08,04,usb,yes,26,31 2006.145.13:46:07.57/valo/01,524.99,yes,locked 2006.145.13:46:07.57/valo/02,534.99,yes,locked 2006.145.13:46:07.57/valo/03,564.99,yes,locked 2006.145.13:46:07.57/valo/04,624.99,yes,locked 2006.145.13:46:07.57/valo/05,734.99,yes,locked 2006.145.13:46:07.57/valo/06,814.99,yes,locked 2006.145.13:46:07.57/valo/07,864.99,yes,locked 2006.145.13:46:07.57/valo/08,884.99,yes,locked 2006.145.13:46:08.66/vb/01,03,usb,yes,35,33 2006.145.13:46:08.66/vb/02,04,usb,yes,31,31 2006.145.13:46:08.66/vb/03,04,usb,yes,28,31 2006.145.13:46:08.66/vb/04,04,usb,yes,32,31 2006.145.13:46:08.66/vb/05,04,usb,yes,25,27 2006.145.13:46:08.66/vb/06,04,usb,yes,29,26 2006.145.13:46:08.66/vb/07,04,usb,yes,29,29 2006.145.13:46:08.66/vb/08,04,usb,yes,27,30 2006.145.13:46:08.89/vblo/01,629.99,yes,locked 2006.145.13:46:08.89/vblo/02,634.99,yes,locked 2006.145.13:46:08.89/vblo/03,649.99,yes,locked 2006.145.13:46:08.89/vblo/04,679.99,yes,locked 2006.145.13:46:08.89/vblo/05,709.99,yes,locked 2006.145.13:46:08.89/vblo/06,719.99,yes,locked 2006.145.13:46:08.89/vblo/07,734.99,yes,locked 2006.145.13:46:08.89/vblo/08,744.99,yes,locked 2006.145.13:46:09.04/vabw/8 2006.145.13:46:09.19/vbbw/8 2006.145.13:46:09.28/xfe/off,on,14.7 2006.145.13:46:09.65/ifatt/23,28,28,28 2006.145.13:46:10.07/fmout-gps/S +4.9E-08 2006.145.13:46:10.11:!2006.145.13:59:09 2006.145.13:59:09.00:data_valid=off 2006.145.13:59:09.01:"et 2006.145.13:59:09.01:!+3s 2006.145.13:59:12.03:"tape 2006.145.13:59:12.04:postob 2006.145.13:59:12.12/cable/+6.5479E-03 2006.145.13:59:12.13/wx/14.94,1020.8,87 2006.145.13:59:12.20/fmout-gps/S +5.3E-08 2006.145.13:59:12.20:scan_name=145-1401,jd0605,80 2006.145.13:59:12.20:source=3c274,123049.42,122328.0,2000.0,cw 2006.145.13:59:14.13#flagr#flagr/antenna,new-source 2006.145.13:59:14.13:checkk5 2006.145.13:59:14.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.13:59:15.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.13:59:15.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.13:59:15.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.13:59:16.64/chk_obsdata//k5ts1/T1451346??a.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.13:59:17.38/chk_obsdata//k5ts2/T1451346??b.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.13:59:18.14/chk_obsdata//k5ts3/T1451346??c.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.13:59:18.88/chk_obsdata//k5ts4/T1451346??d.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.13:59:19.66/k5log//k5ts1_log_newline 2006.145.13:59:20.41/k5log//k5ts2_log_newline 2006.145.13:59:21.17/k5log//k5ts3_log_newline 2006.145.13:59:21.92/k5log//k5ts4_log_newline 2006.145.13:59:21.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.13:59:21.95:setupk4=1 2006.145.13:59:21.95$setupk4/echo=on 2006.145.13:59:21.95$setupk4/pcalon 2006.145.13:59:21.95$pcalon/"no phase cal control is implemented here 2006.145.13:59:21.95$setupk4/"tpicd=stop 2006.145.13:59:21.95$setupk4/"rec=synch_on 2006.145.13:59:21.95$setupk4/"rec_mode=128 2006.145.13:59:21.95$setupk4/!* 2006.145.13:59:21.95$setupk4/recpk4 2006.145.13:59:21.95$recpk4/recpatch= 2006.145.13:59:21.96$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.13:59:21.96$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.13:59:21.96$setupk4/vck44 2006.145.13:59:21.96$vck44/valo=1,524.99 2006.145.13:59:21.96#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.13:59:21.96#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.13:59:21.96#ibcon#ireg 17 cls_cnt 0 2006.145.13:59:21.96#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:59:21.96#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:59:21.96#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:59:21.99#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.13:59:22.03#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:59:22.03#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:59:22.03#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.13:59:22.03#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.13:59:22.03$vck44/va=1,8 2006.145.13:59:22.03#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.13:59:22.03#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.13:59:22.03#ibcon#ireg 11 cls_cnt 2 2006.145.13:59:22.03#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.13:59:22.03#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.13:59:22.03#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.13:59:22.05#ibcon#[25=AT01-08\r\n] 2006.145.13:59:22.08#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.13:59:22.08#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.13:59:22.08#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.13:59:22.08#ibcon#ireg 7 cls_cnt 0 2006.145.13:59:22.08#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.13:59:22.20#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.13:59:22.20#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.13:59:22.24#ibcon#[25=USB\r\n] 2006.145.13:59:22.27#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.13:59:22.27#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.13:59:22.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.13:59:22.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.13:59:22.27$vck44/valo=2,534.99 2006.145.13:59:22.27#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.13:59:22.27#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.13:59:22.27#ibcon#ireg 17 cls_cnt 0 2006.145.13:59:22.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:59:22.27#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:59:22.27#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:59:22.30#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.13:59:22.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:59:22.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:59:22.34#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.13:59:22.34#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.13:59:22.34$vck44/va=2,7 2006.145.13:59:22.34#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.13:59:22.34#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.13:59:22.34#ibcon#ireg 11 cls_cnt 2 2006.145.13:59:22.34#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.13:59:22.39#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.13:59:22.39#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.13:59:22.41#ibcon#[25=AT02-07\r\n] 2006.145.13:59:22.44#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.13:59:22.44#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.13:59:22.44#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.13:59:22.44#ibcon#ireg 7 cls_cnt 0 2006.145.13:59:22.44#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.13:59:22.56#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.13:59:22.56#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.13:59:22.58#ibcon#[25=USB\r\n] 2006.145.13:59:22.61#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.13:59:22.61#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.13:59:22.61#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.13:59:22.61#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.13:59:22.61$vck44/valo=3,564.99 2006.145.13:59:22.61#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.13:59:22.61#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.13:59:22.61#ibcon#ireg 17 cls_cnt 0 2006.145.13:59:22.61#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:59:22.61#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:59:22.61#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:59:22.63#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.13:59:22.67#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:59:22.67#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:59:22.67#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.13:59:22.67#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.13:59:22.67$vck44/va=3,8 2006.145.13:59:22.67#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.13:59:22.67#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.13:59:22.67#ibcon#ireg 11 cls_cnt 2 2006.145.13:59:22.67#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.13:59:22.73#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.13:59:22.73#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.13:59:22.75#ibcon#[25=AT03-08\r\n] 2006.145.13:59:22.78#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.13:59:22.78#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.13:59:22.78#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.13:59:22.78#ibcon#ireg 7 cls_cnt 0 2006.145.13:59:22.78#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.13:59:22.90#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.13:59:22.90#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.13:59:22.92#ibcon#[25=USB\r\n] 2006.145.13:59:22.95#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.13:59:22.95#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.13:59:22.95#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.13:59:22.95#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.13:59:22.95$vck44/valo=4,624.99 2006.145.13:59:22.95#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.13:59:22.95#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.13:59:22.95#ibcon#ireg 17 cls_cnt 0 2006.145.13:59:22.95#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:59:22.95#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:59:22.95#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:59:22.97#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.13:59:23.01#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:59:23.01#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:59:23.01#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.13:59:23.01#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.13:59:23.01$vck44/va=4,7 2006.145.13:59:23.01#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.13:59:23.01#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.13:59:23.01#ibcon#ireg 11 cls_cnt 2 2006.145.13:59:23.01#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:59:23.07#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:59:23.07#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:59:23.09#ibcon#[25=AT04-07\r\n] 2006.145.13:59:23.12#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:59:23.12#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:59:23.12#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.13:59:23.12#ibcon#ireg 7 cls_cnt 0 2006.145.13:59:23.12#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:59:23.24#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:59:23.24#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:59:23.26#ibcon#[25=USB\r\n] 2006.145.13:59:23.29#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:59:23.29#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:59:23.29#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.13:59:23.29#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.13:59:23.29$vck44/valo=5,734.99 2006.145.13:59:23.29#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.13:59:23.29#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.13:59:23.29#ibcon#ireg 17 cls_cnt 0 2006.145.13:59:23.29#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:59:23.29#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:59:23.29#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:59:23.32#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.13:59:23.35#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:59:23.35#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:59:23.35#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.13:59:23.35#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.13:59:23.35$vck44/va=5,4 2006.145.13:59:23.35#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.13:59:23.35#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.13:59:23.35#ibcon#ireg 11 cls_cnt 2 2006.145.13:59:23.35#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:59:23.41#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:59:23.41#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:59:23.43#ibcon#[25=AT05-04\r\n] 2006.145.13:59:23.46#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:59:23.46#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:59:23.46#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.13:59:23.46#ibcon#ireg 7 cls_cnt 0 2006.145.13:59:23.46#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:59:23.58#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:59:23.58#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:59:23.60#ibcon#[25=USB\r\n] 2006.145.13:59:23.63#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:59:23.63#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:59:23.63#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.13:59:23.63#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.13:59:23.63$vck44/valo=6,814.99 2006.145.13:59:23.63#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.13:59:23.63#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.13:59:23.63#ibcon#ireg 17 cls_cnt 0 2006.145.13:59:23.63#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:59:23.63#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:59:23.63#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:59:23.65#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.13:59:23.69#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:59:23.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:59:23.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.13:59:23.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.13:59:23.69$vck44/va=6,4 2006.145.13:59:23.69#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.13:59:23.69#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.13:59:23.69#ibcon#ireg 11 cls_cnt 2 2006.145.13:59:23.69#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:59:23.75#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:59:23.75#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:59:23.77#ibcon#[25=AT06-04\r\n] 2006.145.13:59:23.80#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:59:23.80#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:59:23.80#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.13:59:23.80#ibcon#ireg 7 cls_cnt 0 2006.145.13:59:23.80#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:59:23.92#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:59:23.92#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:59:23.94#ibcon#[25=USB\r\n] 2006.145.13:59:23.97#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:59:23.97#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:59:23.97#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.13:59:23.97#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.13:59:23.97$vck44/valo=7,864.99 2006.145.13:59:23.97#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.13:59:23.97#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.13:59:23.97#ibcon#ireg 17 cls_cnt 0 2006.145.13:59:23.97#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:59:23.97#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:59:23.97#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:59:23.99#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.13:59:24.03#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:59:24.03#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:59:24.03#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.13:59:24.03#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.13:59:24.03$vck44/va=7,4 2006.145.13:59:24.03#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.13:59:24.03#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.13:59:24.03#ibcon#ireg 11 cls_cnt 2 2006.145.13:59:24.03#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:59:24.09#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:59:24.09#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:59:24.11#ibcon#[25=AT07-04\r\n] 2006.145.13:59:24.14#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:59:24.14#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:59:24.14#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.13:59:24.14#ibcon#ireg 7 cls_cnt 0 2006.145.13:59:24.14#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:59:24.26#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:59:24.26#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:59:24.28#ibcon#[25=USB\r\n] 2006.145.13:59:24.31#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:59:24.31#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:59:24.31#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.13:59:24.31#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.13:59:24.31$vck44/valo=8,884.99 2006.145.13:59:24.31#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.13:59:24.31#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.13:59:24.31#ibcon#ireg 17 cls_cnt 0 2006.145.13:59:24.31#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:59:24.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:59:24.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:59:24.33#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.13:59:24.37#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:59:24.37#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:59:24.37#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.13:59:24.37#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.13:59:24.37$vck44/va=8,4 2006.145.13:59:24.37#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.13:59:24.37#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.13:59:24.37#ibcon#ireg 11 cls_cnt 2 2006.145.13:59:24.37#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.13:59:24.43#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.13:59:24.43#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.13:59:24.45#ibcon#[25=AT08-04\r\n] 2006.145.13:59:24.48#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.13:59:24.48#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.13:59:24.48#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.13:59:24.48#ibcon#ireg 7 cls_cnt 0 2006.145.13:59:24.48#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.13:59:24.60#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.13:59:24.60#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.13:59:24.62#ibcon#[25=USB\r\n] 2006.145.13:59:24.65#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.13:59:24.65#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.13:59:24.65#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.13:59:24.65#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.13:59:24.65$vck44/vblo=1,629.99 2006.145.13:59:24.65#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.13:59:24.65#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.13:59:24.65#ibcon#ireg 17 cls_cnt 0 2006.145.13:59:24.65#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:59:24.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:59:24.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:59:24.68#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.13:59:24.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:59:24.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.13:59:24.72#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.13:59:24.72#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.13:59:24.72$vck44/vb=1,3 2006.145.13:59:24.72#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.13:59:24.72#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.13:59:24.72#ibcon#ireg 11 cls_cnt 2 2006.145.13:59:24.72#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.13:59:24.72#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.13:59:24.72#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.13:59:24.74#ibcon#[27=AT01-03\r\n] 2006.145.13:59:24.77#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.13:59:24.77#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.13:59:24.77#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.13:59:24.77#ibcon#ireg 7 cls_cnt 0 2006.145.13:59:24.77#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.13:59:24.89#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.13:59:24.89#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.13:59:24.91#ibcon#[27=USB\r\n] 2006.145.13:59:24.94#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.13:59:24.94#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.13:59:24.94#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.13:59:24.94#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.13:59:24.94$vck44/vblo=2,634.99 2006.145.13:59:24.94#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.13:59:24.94#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.13:59:24.94#ibcon#ireg 17 cls_cnt 0 2006.145.13:59:24.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:59:24.94#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:59:24.94#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:59:24.96#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.13:59:25.00#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:59:25.00#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.13:59:25.00#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.13:59:25.00#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.13:59:25.00$vck44/vb=2,4 2006.145.13:59:25.00#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.13:59:25.00#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.13:59:25.00#ibcon#ireg 11 cls_cnt 2 2006.145.13:59:25.00#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.13:59:25.06#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.13:59:25.06#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.13:59:25.08#ibcon#[27=AT02-04\r\n] 2006.145.13:59:25.11#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.13:59:25.11#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.13:59:25.11#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.13:59:25.11#ibcon#ireg 7 cls_cnt 0 2006.145.13:59:25.11#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.13:59:25.23#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.13:59:25.23#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.13:59:25.25#ibcon#[27=USB\r\n] 2006.145.13:59:25.28#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.13:59:25.28#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.13:59:25.28#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.13:59:25.28#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.13:59:25.28$vck44/vblo=3,649.99 2006.145.13:59:25.28#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.13:59:25.28#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.13:59:25.28#ibcon#ireg 17 cls_cnt 0 2006.145.13:59:25.28#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:59:25.28#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:59:25.28#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:59:25.30#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.13:59:25.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:59:25.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.13:59:25.34#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.13:59:25.34#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.13:59:25.34$vck44/vb=3,4 2006.145.13:59:25.34#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.13:59:25.34#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.13:59:25.34#ibcon#ireg 11 cls_cnt 2 2006.145.13:59:25.34#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.13:59:25.40#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.13:59:25.40#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.13:59:25.42#ibcon#[27=AT03-04\r\n] 2006.145.13:59:25.45#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.13:59:25.45#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.13:59:25.45#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.13:59:25.45#ibcon#ireg 7 cls_cnt 0 2006.145.13:59:25.45#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.13:59:25.57#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.13:59:25.57#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.13:59:25.59#ibcon#[27=USB\r\n] 2006.145.13:59:25.62#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.13:59:25.62#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.13:59:25.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.13:59:25.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.13:59:25.62$vck44/vblo=4,679.99 2006.145.13:59:25.62#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.13:59:25.62#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.13:59:25.62#ibcon#ireg 17 cls_cnt 0 2006.145.13:59:25.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:59:25.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:59:25.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:59:25.64#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.13:59:25.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:59:25.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.13:59:25.68#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.13:59:25.68#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.13:59:25.68$vck44/vb=4,4 2006.145.13:59:25.68#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.13:59:25.68#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.13:59:25.68#ibcon#ireg 11 cls_cnt 2 2006.145.13:59:25.68#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.13:59:25.74#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.13:59:25.74#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.13:59:25.76#ibcon#[27=AT04-04\r\n] 2006.145.13:59:25.79#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.13:59:25.79#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.13:59:25.79#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.13:59:25.79#ibcon#ireg 7 cls_cnt 0 2006.145.13:59:25.79#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.13:59:25.91#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.13:59:25.91#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.13:59:25.93#ibcon#[27=USB\r\n] 2006.145.13:59:25.96#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.13:59:25.96#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.13:59:25.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.13:59:25.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.13:59:25.96$vck44/vblo=5,709.99 2006.145.13:59:25.96#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.13:59:25.96#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.13:59:25.96#ibcon#ireg 17 cls_cnt 0 2006.145.13:59:25.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:59:25.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:59:25.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:59:25.98#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.13:59:26.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:59:26.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.13:59:26.02#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.13:59:26.02#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.13:59:26.02$vck44/vb=5,4 2006.145.13:59:26.02#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.13:59:26.02#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.13:59:26.02#ibcon#ireg 11 cls_cnt 2 2006.145.13:59:26.02#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:59:26.08#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:59:26.08#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:59:26.10#ibcon#[27=AT05-04\r\n] 2006.145.13:59:26.13#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:59:26.13#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.13:59:26.13#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.13:59:26.13#ibcon#ireg 7 cls_cnt 0 2006.145.13:59:26.13#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:59:26.25#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:59:26.25#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:59:26.27#ibcon#[27=USB\r\n] 2006.145.13:59:26.30#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:59:26.30#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.13:59:26.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.13:59:26.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.13:59:26.30$vck44/vblo=6,719.99 2006.145.13:59:26.30#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.13:59:26.30#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.13:59:26.30#ibcon#ireg 17 cls_cnt 0 2006.145.13:59:26.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:59:26.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:59:26.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:59:26.32#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.13:59:26.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:59:26.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.13:59:26.36#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.13:59:26.36#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.13:59:26.36$vck44/vb=6,4 2006.145.13:59:26.36#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.13:59:26.36#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.13:59:26.36#ibcon#ireg 11 cls_cnt 2 2006.145.13:59:26.36#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:59:26.42#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:59:26.42#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:59:26.44#ibcon#[27=AT06-04\r\n] 2006.145.13:59:26.47#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:59:26.47#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.13:59:26.47#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.13:59:26.47#ibcon#ireg 7 cls_cnt 0 2006.145.13:59:26.47#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:59:26.59#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:59:26.59#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:59:26.61#ibcon#[27=USB\r\n] 2006.145.13:59:26.64#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:59:26.64#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.13:59:26.64#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.13:59:26.64#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.13:59:26.64$vck44/vblo=7,734.99 2006.145.13:59:26.64#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.13:59:26.64#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.13:59:26.64#ibcon#ireg 17 cls_cnt 0 2006.145.13:59:26.64#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:59:26.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:59:26.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:59:26.66#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.13:59:26.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:59:26.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.13:59:26.70#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.13:59:26.70#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.13:59:26.70$vck44/vb=7,4 2006.145.13:59:26.70#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.13:59:26.70#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.13:59:26.70#ibcon#ireg 11 cls_cnt 2 2006.145.13:59:26.70#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:59:26.76#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:59:26.76#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:59:26.78#ibcon#[27=AT07-04\r\n] 2006.145.13:59:26.81#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:59:26.81#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.13:59:26.81#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.13:59:26.81#ibcon#ireg 7 cls_cnt 0 2006.145.13:59:26.81#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:59:26.93#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:59:26.93#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:59:26.95#ibcon#[27=USB\r\n] 2006.145.13:59:26.98#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:59:26.98#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.13:59:26.98#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.13:59:26.98#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.13:59:26.98$vck44/vblo=8,744.99 2006.145.13:59:26.98#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.13:59:26.98#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.13:59:26.98#ibcon#ireg 17 cls_cnt 0 2006.145.13:59:26.98#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:59:26.98#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:59:26.98#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:59:27.00#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.13:59:27.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:59:27.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.13:59:27.04#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.13:59:27.04#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.13:59:27.04$vck44/vb=8,4 2006.145.13:59:27.04#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.13:59:27.04#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.13:59:27.04#ibcon#ireg 11 cls_cnt 2 2006.145.13:59:27.04#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:59:27.10#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:59:27.10#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:59:27.12#ibcon#[27=AT08-04\r\n] 2006.145.13:59:27.15#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:59:27.15#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.13:59:27.15#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.13:59:27.15#ibcon#ireg 7 cls_cnt 0 2006.145.13:59:27.15#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:59:27.27#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:59:27.27#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:59:27.29#ibcon#[27=USB\r\n] 2006.145.13:59:27.32#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:59:27.32#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.13:59:27.32#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.13:59:27.32#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.13:59:27.32$vck44/vabw=wide 2006.145.13:59:27.32#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.13:59:27.32#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.13:59:27.32#ibcon#ireg 8 cls_cnt 0 2006.145.13:59:27.32#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:59:27.32#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:59:27.32#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:59:27.34#ibcon#[25=BW32\r\n] 2006.145.13:59:27.37#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:59:27.37#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.13:59:27.37#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.13:59:27.37#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.13:59:27.37$vck44/vbbw=wide 2006.145.13:59:27.37#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.13:59:27.37#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.13:59:27.37#ibcon#ireg 8 cls_cnt 0 2006.145.13:59:27.37#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:59:27.44#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:59:27.44#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:59:27.46#ibcon#[27=BW32\r\n] 2006.145.13:59:27.49#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:59:27.49#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.13:59:27.49#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.13:59:27.49#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.13:59:27.49$setupk4/ifdk4 2006.145.13:59:27.49$ifdk4/lo= 2006.145.13:59:27.49$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.13:59:27.49$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.13:59:27.49$ifdk4/patch= 2006.145.13:59:27.49$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.13:59:27.49$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.13:59:27.49$setupk4/!*+20s 2006.145.13:59:29.85#abcon#<5=/07 0.8 1.5 14.95 871020.8\r\n> 2006.145.13:59:29.87#abcon#{5=INTERFACE CLEAR} 2006.145.13:59:29.93#abcon#[5=S1D000X0/0*\r\n] 2006.145.13:59:40.02#abcon#<5=/07 0.9 1.5 14.95 871020.8\r\n> 2006.145.13:59:40.04#abcon#{5=INTERFACE CLEAR} 2006.145.13:59:40.10#abcon#[5=S1D000X0/0*\r\n] 2006.145.13:59:41.96$setupk4/"tpicd 2006.145.13:59:41.96$setupk4/echo=off 2006.145.13:59:41.96$setupk4/xlog=off 2006.145.13:59:41.96:!2006.145.14:01:07 2006.145.14:00:04.14#trakl#Source acquired 2006.145.14:00:06.14#flagr#flagr/antenna,acquired 2006.145.14:01:07.00:preob 2006.145.14:01:07.14/onsource/TRACKING 2006.145.14:01:07.14:!2006.145.14:01:17 2006.145.14:01:17.00:"tape 2006.145.14:01:17.00:"st=record 2006.145.14:01:17.00:data_valid=on 2006.145.14:01:17.00:midob 2006.145.14:01:18.14/onsource/TRACKING 2006.145.14:01:18.14/wx/14.97,1020.8,88 2006.145.14:01:18.23/cable/+6.5505E-03 2006.145.14:01:19.32/va/01,08,usb,yes,31,33 2006.145.14:01:19.32/va/02,07,usb,yes,33,34 2006.145.14:01:19.32/va/03,08,usb,yes,30,32 2006.145.14:01:19.32/va/04,07,usb,yes,34,36 2006.145.14:01:19.32/va/05,04,usb,yes,30,30 2006.145.14:01:19.32/va/06,04,usb,yes,33,33 2006.145.14:01:19.32/va/07,04,usb,yes,34,35 2006.145.14:01:19.32/va/08,04,usb,yes,29,35 2006.145.14:01:19.55/valo/01,524.99,yes,locked 2006.145.14:01:19.55/valo/02,534.99,yes,locked 2006.145.14:01:19.55/valo/03,564.99,yes,locked 2006.145.14:01:19.55/valo/04,624.99,yes,locked 2006.145.14:01:19.55/valo/05,734.99,yes,locked 2006.145.14:01:19.55/valo/06,814.99,yes,locked 2006.145.14:01:19.55/valo/07,864.99,yes,locked 2006.145.14:01:19.55/valo/08,884.99,yes,locked 2006.145.14:01:20.64/vb/01,03,usb,yes,44,41 2006.145.14:01:20.64/vb/02,04,usb,yes,39,38 2006.145.14:01:20.64/vb/03,04,usb,yes,35,39 2006.145.14:01:20.64/vb/04,04,usb,yes,40,39 2006.145.14:01:20.64/vb/05,04,usb,yes,31,34 2006.145.14:01:20.64/vb/06,04,usb,yes,36,32 2006.145.14:01:20.64/vb/07,04,usb,yes,36,36 2006.145.14:01:20.64/vb/08,04,usb,yes,33,37 2006.145.14:01:20.87/vblo/01,629.99,yes,locked 2006.145.14:01:20.87/vblo/02,634.99,yes,locked 2006.145.14:01:20.87/vblo/03,649.99,yes,locked 2006.145.14:01:20.87/vblo/04,679.99,yes,locked 2006.145.14:01:20.87/vblo/05,709.99,yes,locked 2006.145.14:01:20.87/vblo/06,719.99,yes,locked 2006.145.14:01:20.87/vblo/07,734.99,yes,locked 2006.145.14:01:20.87/vblo/08,744.99,yes,locked 2006.145.14:01:21.02/vabw/8 2006.145.14:01:21.17/vbbw/8 2006.145.14:01:21.26/xfe/off,on,14.5 2006.145.14:01:21.65/ifatt/23,28,28,28 2006.145.14:01:22.07/fmout-gps/S +5.2E-08 2006.145.14:01:22.11:!2006.145.14:02:37 2006.145.14:02:37.01:data_valid=off 2006.145.14:02:37.02:"et 2006.145.14:02:37.02:!+3s 2006.145.14:02:40.03:"tape 2006.145.14:02:40.04:postob 2006.145.14:02:40.11/cable/+6.5501E-03 2006.145.14:02:40.12/wx/14.98,1020.8,88 2006.145.14:02:40.20/fmout-gps/S +5.2E-08 2006.145.14:02:40.20:scan_name=145-1406,jd0605,590 2006.145.14:02:40.20:source=0059+581,010245.76,582411.1,2000.0,cw 2006.145.14:02:41.14#flagr#flagr/antenna,new-source 2006.145.14:02:41.15:checkk5 2006.145.14:02:41.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.14:02:42.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.14:02:42.44/chk_autoobs//k5ts3/ autoobs is running! 2006.145.14:02:42.88/chk_autoobs//k5ts4/ autoobs is running! 2006.145.14:02:43.30/chk_obsdata//k5ts1/T1451401??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.14:02:43.73/chk_obsdata//k5ts2/T1451401??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.14:02:44.17/chk_obsdata//k5ts3/T1451401??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.14:02:44.60/chk_obsdata//k5ts4/T1451401??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.14:02:45.37/k5log//k5ts1_log_newline 2006.145.14:02:46.11/k5log//k5ts2_log_newline 2006.145.14:02:46.87/k5log//k5ts3_log_newline 2006.145.14:02:47.63/k5log//k5ts4_log_newline 2006.145.14:02:47.65/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.14:02:47.65:setupk4=1 2006.145.14:02:47.65$setupk4/echo=on 2006.145.14:02:47.65$setupk4/pcalon 2006.145.14:02:47.65$pcalon/"no phase cal control is implemented here 2006.145.14:02:47.65$setupk4/"tpicd=stop 2006.145.14:02:47.65$setupk4/"rec=synch_on 2006.145.14:02:47.65$setupk4/"rec_mode=128 2006.145.14:02:47.65$setupk4/!* 2006.145.14:02:47.65$setupk4/recpk4 2006.145.14:02:47.65$recpk4/recpatch= 2006.145.14:02:47.66$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.14:02:47.66$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.14:02:47.66$setupk4/vck44 2006.145.14:02:47.66$vck44/valo=1,524.99 2006.145.14:02:47.66#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.14:02:47.66#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.14:02:47.66#ibcon#ireg 17 cls_cnt 0 2006.145.14:02:47.66#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:02:47.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:02:47.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:02:47.70#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.14:02:47.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:02:47.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:02:47.74#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.14:02:47.74#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.14:02:47.74$vck44/va=1,8 2006.145.14:02:47.74#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.14:02:47.74#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.14:02:47.74#ibcon#ireg 11 cls_cnt 2 2006.145.14:02:47.74#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.14:02:47.74#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.14:02:47.74#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.14:02:47.76#ibcon#[25=AT01-08\r\n] 2006.145.14:02:47.79#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.14:02:47.79#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.14:02:47.79#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.14:02:47.79#ibcon#ireg 7 cls_cnt 0 2006.145.14:02:47.79#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.14:02:47.93#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.14:02:47.93#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.14:02:47.95#ibcon#[25=USB\r\n] 2006.145.14:02:47.98#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.14:02:47.98#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.14:02:47.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.14:02:47.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.14:02:47.98$vck44/valo=2,534.99 2006.145.14:02:47.98#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.14:02:47.98#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.14:02:47.98#ibcon#ireg 17 cls_cnt 0 2006.145.14:02:47.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.14:02:47.98#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.14:02:47.98#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.14:02:48.01#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.14:02:48.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.14:02:48.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.14:02:48.05#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.14:02:48.05#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.14:02:48.05$vck44/va=2,7 2006.145.14:02:48.05#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.14:02:48.05#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.14:02:48.05#ibcon#ireg 11 cls_cnt 2 2006.145.14:02:48.05#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.14:02:48.10#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.14:02:48.10#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.14:02:48.12#ibcon#[25=AT02-07\r\n] 2006.145.14:02:48.15#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.14:02:48.15#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.14:02:48.15#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.14:02:48.15#ibcon#ireg 7 cls_cnt 0 2006.145.14:02:48.15#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.14:02:48.27#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.14:02:48.27#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.14:02:48.29#ibcon#[25=USB\r\n] 2006.145.14:02:48.32#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.14:02:48.32#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.14:02:48.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.14:02:48.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.14:02:48.32$vck44/valo=3,564.99 2006.145.14:02:48.32#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.14:02:48.32#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.14:02:48.32#ibcon#ireg 17 cls_cnt 0 2006.145.14:02:48.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:02:48.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:02:48.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:02:48.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.14:02:48.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:02:48.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:02:48.38#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.14:02:48.38#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.14:02:48.38$vck44/va=3,8 2006.145.14:02:48.38#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.14:02:48.38#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.14:02:48.38#ibcon#ireg 11 cls_cnt 2 2006.145.14:02:48.38#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.14:02:48.44#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.14:02:48.44#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.14:02:48.46#ibcon#[25=AT03-08\r\n] 2006.145.14:02:48.49#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.14:02:48.49#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.14:02:48.49#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.14:02:48.49#ibcon#ireg 7 cls_cnt 0 2006.145.14:02:48.49#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.14:02:48.61#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.14:02:48.61#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.14:02:48.63#ibcon#[25=USB\r\n] 2006.145.14:02:48.66#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.14:02:48.66#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.14:02:48.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.14:02:48.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.14:02:48.66$vck44/valo=4,624.99 2006.145.14:02:48.66#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.14:02:48.66#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.14:02:48.66#ibcon#ireg 17 cls_cnt 0 2006.145.14:02:48.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:02:48.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:02:48.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:02:48.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.14:02:48.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:02:48.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:02:48.72#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.14:02:48.72#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.14:02:48.72$vck44/va=4,7 2006.145.14:02:48.72#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.14:02:48.72#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.14:02:48.72#ibcon#ireg 11 cls_cnt 2 2006.145.14:02:48.72#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:02:48.78#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:02:48.78#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:02:48.80#ibcon#[25=AT04-07\r\n] 2006.145.14:02:48.83#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:02:48.83#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:02:48.83#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.14:02:48.83#ibcon#ireg 7 cls_cnt 0 2006.145.14:02:48.83#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:02:48.95#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:02:48.95#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:02:48.97#ibcon#[25=USB\r\n] 2006.145.14:02:49.00#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:02:49.00#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:02:49.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.14:02:49.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.14:02:49.00$vck44/valo=5,734.99 2006.145.14:02:49.00#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.14:02:49.00#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.14:02:49.00#ibcon#ireg 17 cls_cnt 0 2006.145.14:02:49.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:02:49.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:02:49.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:02:49.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.14:02:49.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:02:49.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:02:49.06#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.14:02:49.06#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.14:02:49.06$vck44/va=5,4 2006.145.14:02:49.06#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.14:02:49.06#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.14:02:49.06#ibcon#ireg 11 cls_cnt 2 2006.145.14:02:49.06#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:02:49.12#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:02:49.12#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:02:49.14#ibcon#[25=AT05-04\r\n] 2006.145.14:02:49.17#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:02:49.17#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:02:49.17#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.14:02:49.17#ibcon#ireg 7 cls_cnt 0 2006.145.14:02:49.17#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:02:49.29#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:02:49.29#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:02:49.31#ibcon#[25=USB\r\n] 2006.145.14:02:49.34#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:02:49.34#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:02:49.34#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.14:02:49.34#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.14:02:49.34$vck44/valo=6,814.99 2006.145.14:02:49.34#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.14:02:49.34#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.14:02:49.34#ibcon#ireg 17 cls_cnt 0 2006.145.14:02:49.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:02:49.34#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:02:49.34#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:02:49.37#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.14:02:49.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:02:49.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:02:49.41#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.14:02:49.41#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.14:02:49.41$vck44/va=6,4 2006.145.14:02:49.41#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.14:02:49.41#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.14:02:49.41#ibcon#ireg 11 cls_cnt 2 2006.145.14:02:49.41#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.14:02:49.46#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.14:02:49.46#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.14:02:49.48#ibcon#[25=AT06-04\r\n] 2006.145.14:02:49.51#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.14:02:49.51#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.14:02:49.51#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.14:02:49.51#ibcon#ireg 7 cls_cnt 0 2006.145.14:02:49.51#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.14:02:49.63#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.14:02:49.63#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.14:02:49.65#ibcon#[25=USB\r\n] 2006.145.14:02:49.68#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.14:02:49.68#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.14:02:49.68#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.14:02:49.68#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.14:02:49.68$vck44/valo=7,864.99 2006.145.14:02:49.68#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.14:02:49.68#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.14:02:49.68#ibcon#ireg 17 cls_cnt 0 2006.145.14:02:49.68#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.14:02:49.68#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.14:02:49.68#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.14:02:49.70#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.14:02:49.74#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.14:02:49.74#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.14:02:49.74#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.14:02:49.74#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.14:02:49.74$vck44/va=7,4 2006.145.14:02:49.74#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.14:02:49.74#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.14:02:49.74#ibcon#ireg 11 cls_cnt 2 2006.145.14:02:49.74#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.14:02:49.80#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.14:02:49.80#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.14:02:49.82#ibcon#[25=AT07-04\r\n] 2006.145.14:02:49.85#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.14:02:49.85#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.14:02:49.85#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.14:02:49.85#ibcon#ireg 7 cls_cnt 0 2006.145.14:02:49.85#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.14:02:49.97#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.14:02:49.97#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.14:02:49.99#ibcon#[25=USB\r\n] 2006.145.14:02:50.02#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.14:02:50.02#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.14:02:50.02#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.14:02:50.02#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.14:02:50.02$vck44/valo=8,884.99 2006.145.14:02:50.02#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.14:02:50.02#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.14:02:50.02#ibcon#ireg 17 cls_cnt 0 2006.145.14:02:50.02#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:02:50.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:02:50.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:02:50.04#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.14:02:50.08#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:02:50.08#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:02:50.08#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.14:02:50.08#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.14:02:50.08$vck44/va=8,4 2006.145.14:02:50.08#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.14:02:50.08#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.14:02:50.08#ibcon#ireg 11 cls_cnt 2 2006.145.14:02:50.08#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.14:02:50.14#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.14:02:50.14#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.14:02:50.16#ibcon#[25=AT08-04\r\n] 2006.145.14:02:50.19#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.14:02:50.19#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.14:02:50.19#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.14:02:50.19#ibcon#ireg 7 cls_cnt 0 2006.145.14:02:50.19#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.14:02:50.31#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.14:02:50.31#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.14:02:50.33#ibcon#[25=USB\r\n] 2006.145.14:02:50.36#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.14:02:50.36#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.14:02:50.36#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.14:02:50.36#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.14:02:50.36$vck44/vblo=1,629.99 2006.145.14:02:50.36#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.14:02:50.36#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.14:02:50.36#ibcon#ireg 17 cls_cnt 0 2006.145.14:02:50.36#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.14:02:50.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.14:02:50.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.14:02:50.39#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.14:02:50.43#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.14:02:50.43#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.14:02:50.43#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.14:02:50.43#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.14:02:50.43$vck44/vb=1,3 2006.145.14:02:50.43#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.14:02:50.43#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.14:02:50.43#ibcon#ireg 11 cls_cnt 2 2006.145.14:02:50.43#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.14:02:50.43#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.14:02:50.43#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.14:02:50.45#ibcon#[27=AT01-03\r\n] 2006.145.14:02:50.48#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.14:02:50.48#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.14:02:50.48#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.14:02:50.48#ibcon#ireg 7 cls_cnt 0 2006.145.14:02:50.48#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.14:02:50.60#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.14:02:50.60#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.14:02:50.62#ibcon#[27=USB\r\n] 2006.145.14:02:50.65#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.14:02:50.65#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.14:02:50.65#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.14:02:50.65#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.14:02:50.65$vck44/vblo=2,634.99 2006.145.14:02:50.65#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.14:02:50.65#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.14:02:50.65#ibcon#ireg 17 cls_cnt 0 2006.145.14:02:50.65#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:02:50.65#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:02:50.65#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:02:50.67#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.14:02:50.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:02:50.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:02:50.71#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.14:02:50.71#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.14:02:50.71$vck44/vb=2,4 2006.145.14:02:50.71#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.14:02:50.71#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.14:02:50.71#ibcon#ireg 11 cls_cnt 2 2006.145.14:02:50.71#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.14:02:50.77#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.14:02:50.77#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.14:02:50.79#ibcon#[27=AT02-04\r\n] 2006.145.14:02:50.82#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.14:02:50.82#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.14:02:50.82#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.14:02:50.82#ibcon#ireg 7 cls_cnt 0 2006.145.14:02:50.82#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.14:02:50.94#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.14:02:50.94#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.14:02:50.96#ibcon#[27=USB\r\n] 2006.145.14:02:50.99#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.14:02:50.99#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.14:02:50.99#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.14:02:50.99#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.14:02:50.99$vck44/vblo=3,649.99 2006.145.14:02:50.99#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.14:02:50.99#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.14:02:50.99#ibcon#ireg 17 cls_cnt 0 2006.145.14:02:50.99#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.14:02:50.99#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.14:02:50.99#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.14:02:51.01#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.14:02:51.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.14:02:51.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.14:02:51.05#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.14:02:51.05#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.14:02:51.05$vck44/vb=3,4 2006.145.14:02:51.05#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.14:02:51.05#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.14:02:51.05#ibcon#ireg 11 cls_cnt 2 2006.145.14:02:51.05#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.14:02:51.11#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.14:02:51.11#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.14:02:51.13#ibcon#[27=AT03-04\r\n] 2006.145.14:02:51.16#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.14:02:51.16#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.14:02:51.16#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.14:02:51.16#ibcon#ireg 7 cls_cnt 0 2006.145.14:02:51.16#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.14:02:51.28#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.14:02:51.28#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.14:02:51.30#ibcon#[27=USB\r\n] 2006.145.14:02:51.33#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.14:02:51.33#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.14:02:51.33#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.14:02:51.33#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.14:02:51.33$vck44/vblo=4,679.99 2006.145.14:02:51.33#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.14:02:51.33#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.14:02:51.33#ibcon#ireg 17 cls_cnt 0 2006.145.14:02:51.33#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:02:51.33#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:02:51.33#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:02:51.35#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.14:02:51.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:02:51.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:02:51.39#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.14:02:51.39#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.14:02:51.39$vck44/vb=4,4 2006.145.14:02:51.39#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.14:02:51.39#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.14:02:51.39#ibcon#ireg 11 cls_cnt 2 2006.145.14:02:51.39#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.14:02:51.45#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.14:02:51.45#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.14:02:51.47#ibcon#[27=AT04-04\r\n] 2006.145.14:02:51.50#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.14:02:51.50#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.14:02:51.50#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.14:02:51.50#ibcon#ireg 7 cls_cnt 0 2006.145.14:02:51.50#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.14:02:51.62#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.14:02:51.62#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.14:02:51.64#ibcon#[27=USB\r\n] 2006.145.14:02:51.67#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.14:02:51.67#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.14:02:51.67#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.14:02:51.67#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.14:02:51.67$vck44/vblo=5,709.99 2006.145.14:02:51.67#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.14:02:51.67#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.14:02:51.67#ibcon#ireg 17 cls_cnt 0 2006.145.14:02:51.67#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:02:51.67#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:02:51.67#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:02:51.69#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.14:02:51.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:02:51.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:02:51.73#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.14:02:51.73#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.14:02:51.73$vck44/vb=5,4 2006.145.14:02:51.73#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.14:02:51.73#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.14:02:51.73#ibcon#ireg 11 cls_cnt 2 2006.145.14:02:51.73#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:02:51.79#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:02:51.79#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:02:51.81#ibcon#[27=AT05-04\r\n] 2006.145.14:02:51.84#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:02:51.84#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:02:51.84#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.14:02:51.84#ibcon#ireg 7 cls_cnt 0 2006.145.14:02:51.84#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:02:51.96#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:02:51.96#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:02:51.98#ibcon#[27=USB\r\n] 2006.145.14:02:52.01#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:02:52.01#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:02:52.01#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.14:02:52.01#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.14:02:52.01$vck44/vblo=6,719.99 2006.145.14:02:52.01#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.14:02:52.01#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.14:02:52.01#ibcon#ireg 17 cls_cnt 0 2006.145.14:02:52.01#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:02:52.01#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:02:52.01#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:02:52.03#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.14:02:52.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:02:52.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:02:52.07#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.14:02:52.07#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.14:02:52.07$vck44/vb=6,4 2006.145.14:02:52.07#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.14:02:52.07#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.14:02:52.07#ibcon#ireg 11 cls_cnt 2 2006.145.14:02:52.07#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:02:52.13#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:02:52.13#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:02:52.15#ibcon#[27=AT06-04\r\n] 2006.145.14:02:52.18#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:02:52.18#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:02:52.18#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.14:02:52.18#ibcon#ireg 7 cls_cnt 0 2006.145.14:02:52.18#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:02:52.30#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:02:52.30#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:02:52.32#ibcon#[27=USB\r\n] 2006.145.14:02:52.35#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:02:52.35#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:02:52.35#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.14:02:52.35#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.14:02:52.35$vck44/vblo=7,734.99 2006.145.14:02:52.35#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.14:02:52.35#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.14:02:52.35#ibcon#ireg 17 cls_cnt 0 2006.145.14:02:52.35#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:02:52.35#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:02:52.35#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:02:52.37#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.14:02:52.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:02:52.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:02:52.41#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.14:02:52.41#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.14:02:52.41$vck44/vb=7,4 2006.145.14:02:52.41#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.14:02:52.41#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.14:02:52.41#ibcon#ireg 11 cls_cnt 2 2006.145.14:02:52.41#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.14:02:52.47#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.14:02:52.47#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.14:02:52.49#ibcon#[27=AT07-04\r\n] 2006.145.14:02:52.52#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.14:02:52.52#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.14:02:52.52#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.14:02:52.52#ibcon#ireg 7 cls_cnt 0 2006.145.14:02:52.52#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.14:02:52.64#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.14:02:52.64#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.14:02:52.66#ibcon#[27=USB\r\n] 2006.145.14:02:52.69#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.14:02:52.69#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.14:02:52.69#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.14:02:52.69#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.14:02:52.69$vck44/vblo=8,744.99 2006.145.14:02:52.69#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.14:02:52.69#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.14:02:52.69#ibcon#ireg 17 cls_cnt 0 2006.145.14:02:52.69#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.14:02:52.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.14:02:52.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.14:02:52.71#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.14:02:52.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.14:02:52.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.14:02:52.75#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.14:02:52.75#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.14:02:52.75$vck44/vb=8,4 2006.145.14:02:52.75#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.14:02:52.75#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.14:02:52.75#ibcon#ireg 11 cls_cnt 2 2006.145.14:02:52.75#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.14:02:52.81#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.14:02:52.81#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.14:02:52.83#ibcon#[27=AT08-04\r\n] 2006.145.14:02:52.86#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.14:02:52.86#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.14:02:52.86#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.14:02:52.86#ibcon#ireg 7 cls_cnt 0 2006.145.14:02:52.86#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.14:02:52.98#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.14:02:52.98#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.14:02:53.00#ibcon#[27=USB\r\n] 2006.145.14:02:53.03#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.14:02:53.03#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.14:02:53.03#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.14:02:53.03#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.14:02:53.03$vck44/vabw=wide 2006.145.14:02:53.03#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.14:02:53.03#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.14:02:53.03#ibcon#ireg 8 cls_cnt 0 2006.145.14:02:53.03#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:02:53.03#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:02:53.03#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:02:53.05#ibcon#[25=BW32\r\n] 2006.145.14:02:53.08#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:02:53.08#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:02:53.08#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.14:02:53.08#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.14:02:53.08$vck44/vbbw=wide 2006.145.14:02:53.08#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.14:02:53.08#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.14:02:53.08#ibcon#ireg 8 cls_cnt 0 2006.145.14:02:53.08#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.14:02:53.15#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.14:02:53.15#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.14:02:53.17#ibcon#[27=BW32\r\n] 2006.145.14:02:53.20#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.14:02:53.20#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.14:02:53.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.14:02:53.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.14:02:53.20$setupk4/ifdk4 2006.145.14:02:53.20$ifdk4/lo= 2006.145.14:02:53.20$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.14:02:53.20$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.14:02:53.20$ifdk4/patch= 2006.145.14:02:53.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.14:02:53.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.14:02:53.20$setupk4/!*+20s 2006.145.14:02:53.36#abcon#<5=/07 0.7 1.5 14.99 881020.8\r\n> 2006.145.14:02:53.38#abcon#{5=INTERFACE CLEAR} 2006.145.14:02:53.44#abcon#[5=S1D000X0/0*\r\n] 2006.145.14:03:03.53#abcon#<5=/07 0.7 1.5 14.99 881020.8\r\n> 2006.145.14:03:03.55#abcon#{5=INTERFACE CLEAR} 2006.145.14:03:03.61#abcon#[5=S1D000X0/0*\r\n] 2006.145.14:03:07.66$setupk4/"tpicd 2006.145.14:03:07.66$setupk4/echo=off 2006.145.14:03:07.66$setupk4/xlog=off 2006.145.14:03:07.66:!2006.145.14:06:24 2006.145.14:04:02.14#trakl#Source acquired 2006.145.14:04:03.14#flagr#flagr/antenna,acquired 2006.145.14:06:24.00:preob 2006.145.14:06:25.13/onsource/TRACKING 2006.145.14:06:25.13:!2006.145.14:06:34 2006.145.14:06:34.00:"tape 2006.145.14:06:34.00:"st=record 2006.145.14:06:34.00:data_valid=on 2006.145.14:06:34.00:midob 2006.145.14:06:34.13/onsource/TRACKING 2006.145.14:06:34.13/wx/14.97,1020.8,88 2006.145.14:06:34.25/cable/+6.5490E-03 2006.145.14:06:35.34/va/01,08,usb,yes,33,35 2006.145.14:06:35.34/va/02,07,usb,yes,35,36 2006.145.14:06:35.34/va/03,08,usb,yes,32,34 2006.145.14:06:35.34/va/04,07,usb,yes,37,38 2006.145.14:06:35.34/va/05,04,usb,yes,32,33 2006.145.14:06:35.34/va/06,04,usb,yes,36,36 2006.145.14:06:35.34/va/07,04,usb,yes,36,37 2006.145.14:06:35.34/va/08,04,usb,yes,31,37 2006.145.14:06:35.57/valo/01,524.99,yes,locked 2006.145.14:06:35.57/valo/02,534.99,yes,locked 2006.145.14:06:35.57/valo/03,564.99,yes,locked 2006.145.14:06:35.57/valo/04,624.99,yes,locked 2006.145.14:06:35.57/valo/05,734.99,yes,locked 2006.145.14:06:35.57/valo/06,814.99,yes,locked 2006.145.14:06:35.57/valo/07,864.99,yes,locked 2006.145.14:06:35.57/valo/08,884.99,yes,locked 2006.145.14:06:36.66/vb/01,03,usb,yes,38,52 2006.145.14:06:36.66/vb/02,04,usb,yes,34,45 2006.145.14:06:36.66/vb/03,04,usb,yes,31,35 2006.145.14:06:36.66/vb/04,04,usb,yes,35,34 2006.145.14:06:36.66/vb/05,04,usb,yes,28,30 2006.145.14:06:36.66/vb/06,04,usb,yes,33,29 2006.145.14:06:36.66/vb/07,04,usb,yes,32,32 2006.145.14:06:36.66/vb/08,04,usb,yes,29,33 2006.145.14:06:36.90/vblo/01,629.99,yes,locked 2006.145.14:06:36.90/vblo/02,634.99,yes,locked 2006.145.14:06:36.90/vblo/03,649.99,yes,locked 2006.145.14:06:36.90/vblo/04,679.99,yes,locked 2006.145.14:06:36.90/vblo/05,709.99,yes,locked 2006.145.14:06:36.90/vblo/06,719.99,yes,locked 2006.145.14:06:36.90/vblo/07,734.99,yes,locked 2006.145.14:06:36.90/vblo/08,744.99,yes,locked 2006.145.14:06:37.05/vabw/8 2006.145.14:06:37.20/vbbw/8 2006.145.14:06:37.29/xfe/off,on,14.7 2006.145.14:06:37.68/ifatt/23,28,28,28 2006.145.14:06:38.07/fmout-gps/S +5.3E-08 2006.145.14:06:38.11:!2006.145.14:16:24 2006.145.14:16:24.00:data_valid=off 2006.145.14:16:24.00:"et 2006.145.14:16:24.01:!+3s 2006.145.14:16:27.02:"tape 2006.145.14:16:27.02:postob 2006.145.14:16:27.18/cable/+6.5483E-03 2006.145.14:16:27.18/wx/15.04,1020.7,88 2006.145.14:16:28.07/fmout-gps/S +5.6E-08 2006.145.14:16:28.07:scan_name=145-1417,jd0605,190 2006.145.14:16:28.08:source=2201+315,220314.98,314538.3,2000.0,cw 2006.145.14:16:29.12#flagr#flagr/antenna,new-source 2006.145.14:16:29.12:checkk5 2006.145.14:16:29.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.14:16:30.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.14:16:30.48/chk_autoobs//k5ts3/ autoobs is running! 2006.145.14:16:30.91/chk_autoobs//k5ts4/ autoobs is running! 2006.145.14:16:31.65/chk_obsdata//k5ts1/T1451406??a.dat file size is correct (nominal:2360MB, actual:2356MB). 2006.145.14:16:32.39/chk_obsdata//k5ts2/T1451406??b.dat file size is correct (nominal:2360MB, actual:2356MB). 2006.145.14:16:33.13/chk_obsdata//k5ts3/T1451406??c.dat file size is correct (nominal:2360MB, actual:2356MB). 2006.145.14:16:33.88/chk_obsdata//k5ts4/T1451406??d.dat file size is correct (nominal:2360MB, actual:2356MB). 2006.145.14:16:34.63/k5log//k5ts1_log_newline 2006.145.14:16:35.37/k5log//k5ts2_log_newline 2006.145.14:16:36.14/k5log//k5ts3_log_newline 2006.145.14:16:36.89/k5log//k5ts4_log_newline 2006.145.14:16:36.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.14:16:36.91:setupk4=1 2006.145.14:16:36.91$setupk4/echo=on 2006.145.14:16:36.91$setupk4/pcalon 2006.145.14:16:36.91$pcalon/"no phase cal control is implemented here 2006.145.14:16:36.91$setupk4/"tpicd=stop 2006.145.14:16:36.91$setupk4/"rec=synch_on 2006.145.14:16:36.91$setupk4/"rec_mode=128 2006.145.14:16:36.91$setupk4/!* 2006.145.14:16:36.91$setupk4/recpk4 2006.145.14:16:36.91$recpk4/recpatch= 2006.145.14:16:36.92$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.14:16:36.92$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.14:16:36.92$setupk4/vck44 2006.145.14:16:36.92$vck44/valo=1,524.99 2006.145.14:16:36.92#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.14:16:36.92#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.14:16:36.92#ibcon#ireg 17 cls_cnt 0 2006.145.14:16:36.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.14:16:36.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.14:16:36.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.14:16:36.96#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.14:16:37.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.14:16:37.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.14:16:37.00#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.14:16:37.00#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.14:16:37.00$vck44/va=1,8 2006.145.14:16:37.00#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.14:16:37.00#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.14:16:37.00#ibcon#ireg 11 cls_cnt 2 2006.145.14:16:37.00#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.14:16:37.00#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.14:16:37.00#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.14:16:37.02#ibcon#[25=AT01-08\r\n] 2006.145.14:16:37.05#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.14:16:37.05#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.14:16:37.05#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.14:16:37.05#ibcon#ireg 7 cls_cnt 0 2006.145.14:16:37.05#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.14:16:37.19#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.14:16:37.19#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.14:16:37.20#ibcon#[25=USB\r\n] 2006.145.14:16:37.23#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.14:16:37.23#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.14:16:37.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.14:16:37.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.14:16:37.23$vck44/valo=2,534.99 2006.145.14:16:37.23#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.14:16:37.23#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.14:16:37.23#ibcon#ireg 17 cls_cnt 0 2006.145.14:16:37.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.14:16:37.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.14:16:37.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.14:16:37.26#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.14:16:37.29#abcon#<5=/08 0.5 1.4 15.04 881020.7\r\n> 2006.145.14:16:37.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.14:16:37.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.14:16:37.31#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.14:16:37.31#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.14:16:37.31$vck44/va=2,7 2006.145.14:16:37.31#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.14:16:37.31#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.14:16:37.31#ibcon#ireg 11 cls_cnt 2 2006.145.14:16:37.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.14:16:37.31#abcon#{5=INTERFACE CLEAR} 2006.145.14:16:37.35#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.14:16:37.35#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.14:16:37.37#ibcon#[25=AT02-07\r\n] 2006.145.14:16:37.37#abcon#[5=S1D000X0/0*\r\n] 2006.145.14:16:37.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.14:16:37.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.14:16:37.40#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.14:16:37.40#ibcon#ireg 7 cls_cnt 0 2006.145.14:16:37.40#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.14:16:37.52#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.14:16:37.52#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.14:16:37.54#ibcon#[25=USB\r\n] 2006.145.14:16:37.57#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.14:16:37.57#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.14:16:37.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.14:16:37.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.14:16:37.57$vck44/valo=3,564.99 2006.145.14:16:37.57#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.14:16:37.57#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.14:16:37.57#ibcon#ireg 17 cls_cnt 0 2006.145.14:16:37.57#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.14:16:37.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.14:16:37.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.14:16:37.59#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.14:16:37.63#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.14:16:37.63#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.14:16:37.63#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.14:16:37.63#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.14:16:37.63$vck44/va=3,8 2006.145.14:16:37.63#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.14:16:37.63#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.14:16:37.63#ibcon#ireg 11 cls_cnt 2 2006.145.14:16:37.63#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.14:16:37.69#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.14:16:37.69#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.14:16:37.71#ibcon#[25=AT03-08\r\n] 2006.145.14:16:37.74#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.14:16:37.74#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.14:16:37.74#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.14:16:37.74#ibcon#ireg 7 cls_cnt 0 2006.145.14:16:37.74#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.14:16:37.86#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.14:16:37.86#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.14:16:37.88#ibcon#[25=USB\r\n] 2006.145.14:16:37.91#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.14:16:37.91#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.14:16:37.91#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.14:16:37.91#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.14:16:37.91$vck44/valo=4,624.99 2006.145.14:16:37.91#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.14:16:37.91#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.14:16:37.91#ibcon#ireg 17 cls_cnt 0 2006.145.14:16:37.91#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.14:16:37.91#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.14:16:37.91#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.14:16:37.93#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.14:16:37.97#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.14:16:37.97#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.14:16:37.97#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.14:16:37.97#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.14:16:37.97$vck44/va=4,7 2006.145.14:16:37.97#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.14:16:37.97#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.14:16:37.97#ibcon#ireg 11 cls_cnt 2 2006.145.14:16:37.97#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.14:16:38.03#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.14:16:38.03#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.14:16:38.05#ibcon#[25=AT04-07\r\n] 2006.145.14:16:38.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.14:16:38.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.14:16:38.08#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.14:16:38.08#ibcon#ireg 7 cls_cnt 0 2006.145.14:16:38.08#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.14:16:38.20#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.14:16:38.20#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.14:16:38.22#ibcon#[25=USB\r\n] 2006.145.14:16:38.25#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.14:16:38.25#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.14:16:38.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.14:16:38.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.14:16:38.25$vck44/valo=5,734.99 2006.145.14:16:38.25#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.14:16:38.25#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.14:16:38.25#ibcon#ireg 17 cls_cnt 0 2006.145.14:16:38.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.14:16:38.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.14:16:38.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.14:16:38.27#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.14:16:38.31#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.14:16:38.31#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.14:16:38.31#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.14:16:38.31#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.14:16:38.31$vck44/va=5,4 2006.145.14:16:38.31#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.14:16:38.31#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.14:16:38.31#ibcon#ireg 11 cls_cnt 2 2006.145.14:16:38.31#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.14:16:38.37#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.14:16:38.37#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.14:16:38.39#ibcon#[25=AT05-04\r\n] 2006.145.14:16:38.43#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.14:16:38.43#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.14:16:38.43#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.14:16:38.43#ibcon#ireg 7 cls_cnt 0 2006.145.14:16:38.43#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.14:16:38.54#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.14:16:38.54#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.14:16:38.56#ibcon#[25=USB\r\n] 2006.145.14:16:38.59#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.14:16:38.59#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.14:16:38.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.14:16:38.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.14:16:38.59$vck44/valo=6,814.99 2006.145.14:16:38.59#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.14:16:38.59#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.14:16:38.59#ibcon#ireg 17 cls_cnt 0 2006.145.14:16:38.59#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.14:16:38.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.14:16:38.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.14:16:38.61#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.14:16:38.65#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.14:16:38.65#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.14:16:38.65#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.14:16:38.65#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.14:16:38.65$vck44/va=6,4 2006.145.14:16:38.65#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.14:16:38.65#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.14:16:38.65#ibcon#ireg 11 cls_cnt 2 2006.145.14:16:38.65#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.14:16:38.71#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.14:16:38.71#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.14:16:38.73#ibcon#[25=AT06-04\r\n] 2006.145.14:16:38.76#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.14:16:38.76#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.14:16:38.76#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.14:16:38.76#ibcon#ireg 7 cls_cnt 0 2006.145.14:16:38.76#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.14:16:38.88#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.14:16:38.88#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.14:16:38.90#ibcon#[25=USB\r\n] 2006.145.14:16:38.93#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.14:16:38.93#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.14:16:38.93#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.14:16:38.93#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.14:16:38.93$vck44/valo=7,864.99 2006.145.14:16:38.93#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.14:16:38.93#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.14:16:38.93#ibcon#ireg 17 cls_cnt 0 2006.145.14:16:38.93#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.14:16:38.93#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.14:16:38.93#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.14:16:38.95#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.14:16:38.99#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.14:16:38.99#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.14:16:38.99#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.14:16:38.99#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.14:16:38.99$vck44/va=7,4 2006.145.14:16:38.99#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.14:16:38.99#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.14:16:38.99#ibcon#ireg 11 cls_cnt 2 2006.145.14:16:38.99#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.14:16:39.05#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.14:16:39.05#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.14:16:39.07#ibcon#[25=AT07-04\r\n] 2006.145.14:16:39.10#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.14:16:39.10#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.14:16:39.10#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.14:16:39.10#ibcon#ireg 7 cls_cnt 0 2006.145.14:16:39.10#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.14:16:39.22#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.14:16:39.22#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.14:16:39.24#ibcon#[25=USB\r\n] 2006.145.14:16:39.27#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.14:16:39.27#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.14:16:39.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.14:16:39.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.14:16:39.27$vck44/valo=8,884.99 2006.145.14:16:39.27#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.14:16:39.27#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.14:16:39.27#ibcon#ireg 17 cls_cnt 0 2006.145.14:16:39.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.14:16:39.27#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.14:16:39.27#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.14:16:39.29#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.14:16:39.33#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.14:16:39.33#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.14:16:39.33#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.14:16:39.33#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.14:16:39.33$vck44/va=8,4 2006.145.14:16:39.33#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.14:16:39.33#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.14:16:39.33#ibcon#ireg 11 cls_cnt 2 2006.145.14:16:39.33#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.14:16:39.39#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.14:16:39.39#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.14:16:39.41#ibcon#[25=AT08-04\r\n] 2006.145.14:16:39.44#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.14:16:39.44#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.14:16:39.44#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.14:16:39.44#ibcon#ireg 7 cls_cnt 0 2006.145.14:16:39.44#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.14:16:39.56#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.14:16:39.56#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.14:16:39.58#ibcon#[25=USB\r\n] 2006.145.14:16:39.61#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.14:16:39.61#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.14:16:39.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.14:16:39.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.14:16:39.61$vck44/vblo=1,629.99 2006.145.14:16:39.61#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.14:16:39.61#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.14:16:39.61#ibcon#ireg 17 cls_cnt 0 2006.145.14:16:39.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.14:16:39.61#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.14:16:39.61#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.14:16:39.63#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.14:16:39.67#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.14:16:39.67#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.14:16:39.67#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.14:16:39.67#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.14:16:39.67$vck44/vb=1,3 2006.145.14:16:39.67#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.14:16:39.67#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.14:16:39.67#ibcon#ireg 11 cls_cnt 2 2006.145.14:16:39.67#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.14:16:39.67#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.14:16:39.67#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.14:16:39.69#ibcon#[27=AT01-03\r\n] 2006.145.14:16:39.72#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.14:16:39.72#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.14:16:39.72#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.14:16:39.72#ibcon#ireg 7 cls_cnt 0 2006.145.14:16:39.72#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.14:16:39.84#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.14:16:39.84#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.14:16:39.86#ibcon#[27=USB\r\n] 2006.145.14:16:39.89#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.14:16:39.89#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.14:16:39.89#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.14:16:39.89#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.14:16:39.89$vck44/vblo=2,634.99 2006.145.14:16:39.89#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.14:16:39.89#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.14:16:39.89#ibcon#ireg 17 cls_cnt 0 2006.145.14:16:39.89#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.14:16:39.89#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.14:16:39.89#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.14:16:39.91#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.14:16:39.95#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.14:16:39.95#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.14:16:39.95#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.14:16:39.95#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.14:16:39.95$vck44/vb=2,4 2006.145.14:16:39.95#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.14:16:39.95#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.14:16:39.95#ibcon#ireg 11 cls_cnt 2 2006.145.14:16:39.95#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.14:16:40.01#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.14:16:40.01#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.14:16:40.03#ibcon#[27=AT02-04\r\n] 2006.145.14:16:40.06#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.14:16:40.06#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.14:16:40.06#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.14:16:40.06#ibcon#ireg 7 cls_cnt 0 2006.145.14:16:40.06#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.14:16:40.18#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.14:16:40.18#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.14:16:40.20#ibcon#[27=USB\r\n] 2006.145.14:16:40.23#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.14:16:40.23#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.14:16:40.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.14:16:40.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.14:16:40.23$vck44/vblo=3,649.99 2006.145.14:16:40.23#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.14:16:40.23#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.14:16:40.23#ibcon#ireg 17 cls_cnt 0 2006.145.14:16:40.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.14:16:40.23#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.14:16:40.23#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.14:16:40.25#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.14:16:40.29#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.14:16:40.29#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.14:16:40.29#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.14:16:40.29#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.14:16:40.29$vck44/vb=3,4 2006.145.14:16:40.29#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.14:16:40.29#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.14:16:40.29#ibcon#ireg 11 cls_cnt 2 2006.145.14:16:40.29#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.14:16:40.35#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.14:16:40.35#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.14:16:40.37#ibcon#[27=AT03-04\r\n] 2006.145.14:16:40.40#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.14:16:40.40#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.14:16:40.40#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.14:16:40.40#ibcon#ireg 7 cls_cnt 0 2006.145.14:16:40.40#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.14:16:40.52#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.14:16:40.52#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.14:16:40.54#ibcon#[27=USB\r\n] 2006.145.14:16:40.57#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.14:16:40.57#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.14:16:40.57#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.14:16:40.57#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.14:16:40.57$vck44/vblo=4,679.99 2006.145.14:16:40.57#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.14:16:40.57#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.14:16:40.57#ibcon#ireg 17 cls_cnt 0 2006.145.14:16:40.57#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.14:16:40.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.14:16:40.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.14:16:40.59#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.14:16:40.63#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.14:16:40.63#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.14:16:40.63#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.14:16:40.63#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.14:16:40.63$vck44/vb=4,4 2006.145.14:16:40.63#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.14:16:40.63#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.14:16:40.63#ibcon#ireg 11 cls_cnt 2 2006.145.14:16:40.63#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.14:16:40.69#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.14:16:40.69#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.14:16:40.71#ibcon#[27=AT04-04\r\n] 2006.145.14:16:40.74#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.14:16:40.74#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.14:16:40.74#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.14:16:40.74#ibcon#ireg 7 cls_cnt 0 2006.145.14:16:40.74#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.14:16:40.86#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.14:16:40.86#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.14:16:40.88#ibcon#[27=USB\r\n] 2006.145.14:16:40.91#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.14:16:40.91#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.14:16:40.91#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.14:16:40.91#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.14:16:40.91$vck44/vblo=5,709.99 2006.145.14:16:40.91#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.14:16:40.91#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.14:16:40.91#ibcon#ireg 17 cls_cnt 0 2006.145.14:16:40.91#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.14:16:40.91#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.14:16:40.91#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.14:16:40.93#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.14:16:40.97#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.14:16:40.97#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.14:16:40.97#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.14:16:40.97#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.14:16:40.97$vck44/vb=5,4 2006.145.14:16:40.97#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.14:16:40.97#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.14:16:40.97#ibcon#ireg 11 cls_cnt 2 2006.145.14:16:40.97#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.14:16:41.03#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.14:16:41.03#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.14:16:41.05#ibcon#[27=AT05-04\r\n] 2006.145.14:16:41.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.14:16:41.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.14:16:41.08#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.14:16:41.08#ibcon#ireg 7 cls_cnt 0 2006.145.14:16:41.08#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.14:16:41.20#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.14:16:41.20#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.14:16:41.22#ibcon#[27=USB\r\n] 2006.145.14:16:41.25#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.14:16:41.25#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.14:16:41.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.14:16:41.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.14:16:41.25$vck44/vblo=6,719.99 2006.145.14:16:41.25#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.14:16:41.25#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.14:16:41.25#ibcon#ireg 17 cls_cnt 0 2006.145.14:16:41.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.14:16:41.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.14:16:41.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.14:16:41.27#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.14:16:41.31#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.14:16:41.31#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.14:16:41.31#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.14:16:41.31#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.14:16:41.31$vck44/vb=6,4 2006.145.14:16:41.31#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.14:16:41.31#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.14:16:41.31#ibcon#ireg 11 cls_cnt 2 2006.145.14:16:41.31#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.14:16:41.37#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.14:16:41.37#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.14:16:41.39#ibcon#[27=AT06-04\r\n] 2006.145.14:16:41.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.14:16:41.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.14:16:41.42#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.14:16:41.42#ibcon#ireg 7 cls_cnt 0 2006.145.14:16:41.42#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.14:16:41.54#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.14:16:41.54#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.14:16:41.56#ibcon#[27=USB\r\n] 2006.145.14:16:41.59#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.14:16:41.59#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.14:16:41.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.14:16:41.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.14:16:41.59$vck44/vblo=7,734.99 2006.145.14:16:41.59#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.14:16:41.59#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.14:16:41.59#ibcon#ireg 17 cls_cnt 0 2006.145.14:16:41.59#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.14:16:41.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.14:16:41.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.14:16:41.61#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.14:16:41.65#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.14:16:41.65#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.14:16:41.65#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.14:16:41.65#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.14:16:41.65$vck44/vb=7,4 2006.145.14:16:41.65#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.14:16:41.65#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.14:16:41.65#ibcon#ireg 11 cls_cnt 2 2006.145.14:16:41.65#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.14:16:41.71#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.14:16:41.71#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.14:16:41.73#ibcon#[27=AT07-04\r\n] 2006.145.14:16:41.76#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.14:16:41.76#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.14:16:41.76#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.14:16:41.76#ibcon#ireg 7 cls_cnt 0 2006.145.14:16:41.76#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.14:16:41.88#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.14:16:41.88#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.14:16:41.90#ibcon#[27=USB\r\n] 2006.145.14:16:41.93#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.14:16:41.93#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.14:16:41.93#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.14:16:41.93#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.14:16:41.93$vck44/vblo=8,744.99 2006.145.14:16:41.93#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.14:16:41.93#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.14:16:41.93#ibcon#ireg 17 cls_cnt 0 2006.145.14:16:41.93#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.14:16:41.93#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.14:16:41.93#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.14:16:41.95#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.14:16:41.99#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.14:16:41.99#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.14:16:41.99#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.14:16:41.99#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.14:16:41.99$vck44/vb=8,4 2006.145.14:16:41.99#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.14:16:41.99#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.14:16:41.99#ibcon#ireg 11 cls_cnt 2 2006.145.14:16:41.99#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.14:16:42.05#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.14:16:42.05#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.14:16:42.07#ibcon#[27=AT08-04\r\n] 2006.145.14:16:42.10#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.14:16:42.10#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.14:16:42.10#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.14:16:42.10#ibcon#ireg 7 cls_cnt 0 2006.145.14:16:42.10#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.14:16:42.22#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.14:16:42.22#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.14:16:42.24#ibcon#[27=USB\r\n] 2006.145.14:16:42.27#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.14:16:42.27#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.14:16:42.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.14:16:42.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.14:16:42.27$vck44/vabw=wide 2006.145.14:16:42.27#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.14:16:42.27#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.14:16:42.27#ibcon#ireg 8 cls_cnt 0 2006.145.14:16:42.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.14:16:42.27#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.14:16:42.27#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.14:16:42.29#ibcon#[25=BW32\r\n] 2006.145.14:16:42.32#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.14:16:42.32#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.14:16:42.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.14:16:42.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.14:16:42.32$vck44/vbbw=wide 2006.145.14:16:42.32#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.14:16:42.32#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.14:16:42.32#ibcon#ireg 8 cls_cnt 0 2006.145.14:16:42.32#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:16:42.39#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:16:42.39#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:16:42.41#ibcon#[27=BW32\r\n] 2006.145.14:16:42.44#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:16:42.44#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:16:42.44#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.14:16:42.44#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.14:16:42.44$setupk4/ifdk4 2006.145.14:16:42.44$ifdk4/lo= 2006.145.14:16:42.44$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.14:16:42.44$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.14:16:42.44$ifdk4/patch= 2006.145.14:16:42.44$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.14:16:42.44$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.14:16:42.44$setupk4/!*+20s 2006.145.14:16:47.46#abcon#<5=/08 0.5 1.4 15.04 881020.8\r\n> 2006.145.14:16:47.48#abcon#{5=INTERFACE CLEAR} 2006.145.14:16:47.54#abcon#[5=S1D000X0/0*\r\n] 2006.145.14:16:51.14#trakl#Source acquired 2006.145.14:16:51.14#flagr#flagr/antenna,acquired 2006.145.14:16:56.92$setupk4/"tpicd 2006.145.14:16:56.92$setupk4/echo=off 2006.145.14:16:56.92$setupk4/xlog=off 2006.145.14:16:56.92:!2006.145.14:17:07 2006.145.14:17:07.00:preob 2006.145.14:17:07.14/onsource/TRACKING 2006.145.14:17:07.14:!2006.145.14:17:17 2006.145.14:17:17.00:"tape 2006.145.14:17:17.00:"st=record 2006.145.14:17:17.00:data_valid=on 2006.145.14:17:17.00:midob 2006.145.14:17:18.14/onsource/TRACKING 2006.145.14:17:18.14/wx/15.06,1020.8,88 2006.145.14:17:18.24/cable/+6.5510E-03 2006.145.14:17:19.33/va/01,08,usb,yes,31,33 2006.145.14:17:19.33/va/02,07,usb,yes,33,34 2006.145.14:17:19.33/va/03,08,usb,yes,30,31 2006.145.14:17:19.33/va/04,07,usb,yes,34,36 2006.145.14:17:19.33/va/05,04,usb,yes,30,30 2006.145.14:17:19.33/va/06,04,usb,yes,33,33 2006.145.14:17:19.33/va/07,04,usb,yes,34,35 2006.145.14:17:19.33/va/08,04,usb,yes,29,34 2006.145.14:17:19.56/valo/01,524.99,yes,locked 2006.145.14:17:19.56/valo/02,534.99,yes,locked 2006.145.14:17:19.56/valo/03,564.99,yes,locked 2006.145.14:17:19.56/valo/04,624.99,yes,locked 2006.145.14:17:19.56/valo/05,734.99,yes,locked 2006.145.14:17:19.56/valo/06,814.99,yes,locked 2006.145.14:17:19.56/valo/07,864.99,yes,locked 2006.145.14:17:19.56/valo/08,884.99,yes,locked 2006.145.14:17:20.65/vb/01,03,usb,yes,37,35 2006.145.14:17:20.65/vb/02,04,usb,yes,33,32 2006.145.14:17:20.65/vb/03,04,usb,yes,30,33 2006.145.14:17:20.65/vb/04,04,usb,yes,34,33 2006.145.14:17:20.65/vb/05,04,usb,yes,27,29 2006.145.14:17:20.65/vb/06,04,usb,yes,31,27 2006.145.14:17:20.65/vb/07,04,usb,yes,31,31 2006.145.14:17:20.65/vb/08,04,usb,yes,28,32 2006.145.14:17:20.89/vblo/01,629.99,yes,locked 2006.145.14:17:20.89/vblo/02,634.99,yes,locked 2006.145.14:17:20.89/vblo/03,649.99,yes,locked 2006.145.14:17:20.89/vblo/04,679.99,yes,locked 2006.145.14:17:20.89/vblo/05,709.99,yes,locked 2006.145.14:17:20.89/vblo/06,719.99,yes,locked 2006.145.14:17:20.89/vblo/07,734.99,yes,locked 2006.145.14:17:20.89/vblo/08,744.99,yes,locked 2006.145.14:17:21.04/vabw/8 2006.145.14:17:21.19/vbbw/8 2006.145.14:17:21.28/xfe/off,on,15.2 2006.145.14:17:21.66/ifatt/23,28,28,28 2006.145.14:17:22.07/fmout-gps/S +5.5E-08 2006.145.14:17:22.11:!2006.145.14:20:27 2006.145.14:20:27.00:data_valid=off 2006.145.14:20:27.00:"et 2006.145.14:20:27.01:!+3s 2006.145.14:20:30.02:"tape 2006.145.14:20:30.02:postob 2006.145.14:20:30.09/cable/+6.5486E-03 2006.145.14:20:30.10/wx/15.11,1020.7,88 2006.145.14:20:31.08/fmout-gps/S +5.4E-08 2006.145.14:20:31.08:scan_name=145-1421,jd0605,130 2006.145.14:20:31.09:source=2136+141,213901.31,142336.0,2000.0,cw 2006.145.14:20:32.14#flagr#flagr/antenna,new-source 2006.145.14:20:32.14:checkk5 2006.145.14:20:32.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.14:20:33.04/chk_autoobs//k5ts2/ autoobs is running! 2006.145.14:20:33.48/chk_autoobs//k5ts3/ autoobs is running! 2006.145.14:20:33.92/chk_autoobs//k5ts4/ autoobs is running! 2006.145.14:20:34.35/chk_obsdata//k5ts1/T1451417??a.dat file size is correct (nominal:760MB, actual:760MB). 2006.145.14:20:34.79/chk_obsdata//k5ts2/T1451417??b.dat file size is correct (nominal:760MB, actual:760MB). 2006.145.14:20:35.24/chk_obsdata//k5ts3/T1451417??c.dat file size is correct (nominal:760MB, actual:760MB). 2006.145.14:20:35.67/chk_obsdata//k5ts4/T1451417??d.dat file size is correct (nominal:760MB, actual:760MB). 2006.145.14:20:36.42/k5log//k5ts1_log_newline 2006.145.14:20:37.17/k5log//k5ts2_log_newline 2006.145.14:20:37.91/k5log//k5ts3_log_newline 2006.145.14:20:38.66/k5log//k5ts4_log_newline 2006.145.14:20:38.68/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.14:20:38.68:setupk4=1 2006.145.14:20:38.68$setupk4/echo=on 2006.145.14:20:38.68$setupk4/pcalon 2006.145.14:20:38.68$pcalon/"no phase cal control is implemented here 2006.145.14:20:38.68$setupk4/"tpicd=stop 2006.145.14:20:38.68$setupk4/"rec=synch_on 2006.145.14:20:38.68$setupk4/"rec_mode=128 2006.145.14:20:38.68$setupk4/!* 2006.145.14:20:38.68$setupk4/recpk4 2006.145.14:20:38.68$recpk4/recpatch= 2006.145.14:20:38.69$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.14:20:38.69$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.14:20:38.69$setupk4/vck44 2006.145.14:20:38.69$vck44/valo=1,524.99 2006.145.14:20:38.69#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.14:20:38.69#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.14:20:38.69#ibcon#ireg 17 cls_cnt 0 2006.145.14:20:38.69#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.14:20:38.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.14:20:38.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.14:20:38.73#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.14:20:38.78#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.14:20:38.78#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.14:20:38.78#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.14:20:38.78#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.14:20:38.78$vck44/va=1,8 2006.145.14:20:38.78#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.14:20:38.78#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.14:20:38.78#ibcon#ireg 11 cls_cnt 2 2006.145.14:20:38.78#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.14:20:38.78#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.14:20:38.78#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.14:20:38.80#ibcon#[25=AT01-08\r\n] 2006.145.14:20:38.83#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.14:20:38.83#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.14:20:38.83#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.14:20:38.83#ibcon#ireg 7 cls_cnt 0 2006.145.14:20:38.83#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.14:20:38.95#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.14:20:38.95#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.14:20:38.97#ibcon#[25=USB\r\n] 2006.145.14:20:39.00#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.14:20:39.00#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.14:20:39.00#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.14:20:39.00#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.14:20:39.00$vck44/valo=2,534.99 2006.145.14:20:39.00#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.14:20:39.00#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.14:20:39.00#ibcon#ireg 17 cls_cnt 0 2006.145.14:20:39.00#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.14:20:39.00#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.14:20:39.00#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.14:20:39.03#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.14:20:39.07#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.14:20:39.07#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.14:20:39.07#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.14:20:39.07#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.14:20:39.07$vck44/va=2,7 2006.145.14:20:39.07#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.14:20:39.07#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.14:20:39.07#ibcon#ireg 11 cls_cnt 2 2006.145.14:20:39.07#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.14:20:39.12#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.14:20:39.12#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.14:20:39.14#ibcon#[25=AT02-07\r\n] 2006.145.14:20:39.17#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.14:20:39.17#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.14:20:39.17#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.14:20:39.17#ibcon#ireg 7 cls_cnt 0 2006.145.14:20:39.17#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.14:20:39.29#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.14:20:39.29#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.14:20:39.31#ibcon#[25=USB\r\n] 2006.145.14:20:39.34#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.14:20:39.34#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.14:20:39.34#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.14:20:39.34#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.14:20:39.34$vck44/valo=3,564.99 2006.145.14:20:39.34#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.14:20:39.34#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.14:20:39.34#ibcon#ireg 17 cls_cnt 0 2006.145.14:20:39.34#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.14:20:39.34#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.14:20:39.34#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.14:20:39.36#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.14:20:39.40#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.14:20:39.40#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.14:20:39.40#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.14:20:39.40#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.14:20:39.40$vck44/va=3,8 2006.145.14:20:39.40#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.14:20:39.40#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.14:20:39.40#ibcon#ireg 11 cls_cnt 2 2006.145.14:20:39.40#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.14:20:39.46#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.14:20:39.46#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.14:20:39.48#ibcon#[25=AT03-08\r\n] 2006.145.14:20:39.51#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.14:20:39.51#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.14:20:39.51#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.14:20:39.51#ibcon#ireg 7 cls_cnt 0 2006.145.14:20:39.51#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.14:20:39.63#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.14:20:39.63#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.14:20:39.65#ibcon#[25=USB\r\n] 2006.145.14:20:39.68#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.14:20:39.68#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.14:20:39.68#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.14:20:39.68#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.14:20:39.68$vck44/valo=4,624.99 2006.145.14:20:39.68#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.14:20:39.68#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.14:20:39.68#ibcon#ireg 17 cls_cnt 0 2006.145.14:20:39.68#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.14:20:39.68#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.14:20:39.68#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.14:20:39.70#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.14:20:39.74#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.14:20:39.74#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.14:20:39.74#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.14:20:39.74#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.14:20:39.74$vck44/va=4,7 2006.145.14:20:39.74#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.14:20:39.74#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.14:20:39.74#ibcon#ireg 11 cls_cnt 2 2006.145.14:20:39.74#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.14:20:39.80#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.14:20:39.80#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.14:20:39.82#ibcon#[25=AT04-07\r\n] 2006.145.14:20:39.85#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.14:20:39.85#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.14:20:39.85#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.14:20:39.85#ibcon#ireg 7 cls_cnt 0 2006.145.14:20:39.85#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.14:20:39.97#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.14:20:39.97#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.14:20:39.99#ibcon#[25=USB\r\n] 2006.145.14:20:40.02#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.14:20:40.02#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.14:20:40.02#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.14:20:40.02#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.14:20:40.02$vck44/valo=5,734.99 2006.145.14:20:40.02#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.14:20:40.02#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.14:20:40.02#ibcon#ireg 17 cls_cnt 0 2006.145.14:20:40.02#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.14:20:40.02#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.14:20:40.02#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.14:20:40.04#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.14:20:40.08#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.14:20:40.08#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.14:20:40.08#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.14:20:40.08#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.14:20:40.08$vck44/va=5,4 2006.145.14:20:40.08#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.14:20:40.08#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.14:20:40.08#ibcon#ireg 11 cls_cnt 2 2006.145.14:20:40.08#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.14:20:40.14#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.14:20:40.14#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.14:20:40.16#ibcon#[25=AT05-04\r\n] 2006.145.14:20:40.19#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.14:20:40.19#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.14:20:40.19#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.14:20:40.19#ibcon#ireg 7 cls_cnt 0 2006.145.14:20:40.19#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.14:20:40.31#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.14:20:40.31#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.14:20:40.33#ibcon#[25=USB\r\n] 2006.145.14:20:40.36#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.14:20:40.36#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.14:20:40.36#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.14:20:40.36#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.14:20:40.36$vck44/valo=6,814.99 2006.145.14:20:40.36#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.14:20:40.36#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.14:20:40.36#ibcon#ireg 17 cls_cnt 0 2006.145.14:20:40.36#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.14:20:40.36#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.14:20:40.36#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.14:20:40.39#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.14:20:40.43#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.14:20:40.43#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.14:20:40.43#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.14:20:40.43#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.14:20:40.43$vck44/va=6,4 2006.145.14:20:40.43#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.14:20:40.43#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.14:20:40.43#ibcon#ireg 11 cls_cnt 2 2006.145.14:20:40.43#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.14:20:40.48#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.14:20:40.48#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.14:20:40.50#ibcon#[25=AT06-04\r\n] 2006.145.14:20:40.53#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.14:20:40.53#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.14:20:40.53#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.14:20:40.53#ibcon#ireg 7 cls_cnt 0 2006.145.14:20:40.53#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.14:20:40.65#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.14:20:40.65#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.14:20:40.67#ibcon#[25=USB\r\n] 2006.145.14:20:40.70#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.14:20:40.70#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.14:20:40.70#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.14:20:40.70#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.14:20:40.70$vck44/valo=7,864.99 2006.145.14:20:40.70#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.14:20:40.70#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.14:20:40.70#ibcon#ireg 17 cls_cnt 0 2006.145.14:20:40.70#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:20:40.70#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:20:40.70#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:20:40.72#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.14:20:40.76#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:20:40.76#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:20:40.76#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.14:20:40.76#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.14:20:40.76$vck44/va=7,4 2006.145.14:20:40.76#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.14:20:40.76#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.14:20:40.76#ibcon#ireg 11 cls_cnt 2 2006.145.14:20:40.76#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.14:20:40.82#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.14:20:40.82#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.14:20:40.84#ibcon#[25=AT07-04\r\n] 2006.145.14:20:40.87#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.14:20:40.87#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.14:20:40.87#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.14:20:40.87#ibcon#ireg 7 cls_cnt 0 2006.145.14:20:40.87#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.14:20:40.99#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.14:20:40.99#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.14:20:41.01#ibcon#[25=USB\r\n] 2006.145.14:20:41.04#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.14:20:41.04#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.14:20:41.04#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.14:20:41.04#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.14:20:41.04$vck44/valo=8,884.99 2006.145.14:20:41.04#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.14:20:41.04#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.14:20:41.04#ibcon#ireg 17 cls_cnt 0 2006.145.14:20:41.04#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.14:20:41.04#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.14:20:41.04#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.14:20:41.06#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.14:20:41.10#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.14:20:41.10#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.14:20:41.10#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.14:20:41.10#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.14:20:41.10$vck44/va=8,4 2006.145.14:20:41.10#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.14:20:41.10#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.14:20:41.10#ibcon#ireg 11 cls_cnt 2 2006.145.14:20:41.10#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.14:20:41.16#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.14:20:41.16#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.14:20:41.18#ibcon#[25=AT08-04\r\n] 2006.145.14:20:41.21#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.14:20:41.21#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.14:20:41.21#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.14:20:41.21#ibcon#ireg 7 cls_cnt 0 2006.145.14:20:41.21#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.14:20:41.33#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.14:20:41.33#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.14:20:41.35#ibcon#[25=USB\r\n] 2006.145.14:20:41.38#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.14:20:41.38#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.14:20:41.38#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.14:20:41.38#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.14:20:41.38$vck44/vblo=1,629.99 2006.145.14:20:41.38#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.14:20:41.38#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.14:20:41.38#ibcon#ireg 17 cls_cnt 0 2006.145.14:20:41.38#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.14:20:41.38#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.14:20:41.38#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.14:20:41.40#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.14:20:41.44#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.14:20:41.44#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.14:20:41.44#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.14:20:41.44#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.14:20:41.44$vck44/vb=1,3 2006.145.14:20:41.44#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.14:20:41.44#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.14:20:41.44#ibcon#ireg 11 cls_cnt 2 2006.145.14:20:41.44#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.14:20:41.44#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.14:20:41.44#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.14:20:41.46#ibcon#[27=AT01-03\r\n] 2006.145.14:20:41.49#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.14:20:41.49#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.14:20:41.49#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.14:20:41.49#ibcon#ireg 7 cls_cnt 0 2006.145.14:20:41.49#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.14:20:41.50#abcon#<5=/08 0.7 1.4 15.12 881020.7\r\n> 2006.145.14:20:41.52#abcon#{5=INTERFACE CLEAR} 2006.145.14:20:41.58#abcon#[5=S1D000X0/0*\r\n] 2006.145.14:20:41.61#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.14:20:41.61#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.14:20:41.63#ibcon#[27=USB\r\n] 2006.145.14:20:41.66#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.14:20:41.66#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.14:20:41.66#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.14:20:41.66#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.14:20:41.66$vck44/vblo=2,634.99 2006.145.14:20:41.66#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.14:20:41.66#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.14:20:41.66#ibcon#ireg 17 cls_cnt 0 2006.145.14:20:41.66#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.14:20:41.66#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.14:20:41.66#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.14:20:41.68#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.14:20:41.72#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.14:20:41.72#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.14:20:41.72#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.14:20:41.72#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.14:20:41.72$vck44/vb=2,4 2006.145.14:20:41.72#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.14:20:41.72#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.14:20:41.72#ibcon#ireg 11 cls_cnt 2 2006.145.14:20:41.72#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.14:20:41.78#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.14:20:41.78#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.14:20:41.80#ibcon#[27=AT02-04\r\n] 2006.145.14:20:41.83#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.14:20:41.83#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.14:20:41.83#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.14:20:41.83#ibcon#ireg 7 cls_cnt 0 2006.145.14:20:41.83#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.14:20:41.95#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.14:20:41.95#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.14:20:41.97#ibcon#[27=USB\r\n] 2006.145.14:20:42.00#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.14:20:42.00#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.14:20:42.00#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.14:20:42.00#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.14:20:42.00$vck44/vblo=3,649.99 2006.145.14:20:42.00#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.14:20:42.00#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.14:20:42.00#ibcon#ireg 17 cls_cnt 0 2006.145.14:20:42.00#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.14:20:42.00#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.14:20:42.00#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.14:20:42.02#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.14:20:42.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.14:20:42.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.14:20:42.06#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.14:20:42.06#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.14:20:42.06$vck44/vb=3,4 2006.145.14:20:42.06#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.14:20:42.06#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.14:20:42.06#ibcon#ireg 11 cls_cnt 2 2006.145.14:20:42.06#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.14:20:42.12#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.14:20:42.12#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.14:20:42.14#ibcon#[27=AT03-04\r\n] 2006.145.14:20:42.17#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.14:20:42.17#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.14:20:42.17#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.14:20:42.17#ibcon#ireg 7 cls_cnt 0 2006.145.14:20:42.17#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.14:20:42.29#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.14:20:42.29#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.14:20:42.31#ibcon#[27=USB\r\n] 2006.145.14:20:42.34#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.14:20:42.34#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.14:20:42.34#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.14:20:42.34#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.14:20:42.34$vck44/vblo=4,679.99 2006.145.14:20:42.34#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.14:20:42.34#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.14:20:42.34#ibcon#ireg 17 cls_cnt 0 2006.145.14:20:42.34#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.14:20:42.34#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.14:20:42.34#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.14:20:42.36#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.14:20:42.40#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.14:20:42.40#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.14:20:42.40#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.14:20:42.40#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.14:20:42.40$vck44/vb=4,4 2006.145.14:20:42.40#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.14:20:42.40#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.14:20:42.40#ibcon#ireg 11 cls_cnt 2 2006.145.14:20:42.40#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.14:20:42.46#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.14:20:42.46#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.14:20:42.48#ibcon#[27=AT04-04\r\n] 2006.145.14:20:42.51#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.14:20:42.51#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.14:20:42.51#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.14:20:42.51#ibcon#ireg 7 cls_cnt 0 2006.145.14:20:42.51#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.14:20:42.63#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.14:20:42.63#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.14:20:42.65#ibcon#[27=USB\r\n] 2006.145.14:20:42.68#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.14:20:42.68#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.14:20:42.68#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.14:20:42.68#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.14:20:42.68$vck44/vblo=5,709.99 2006.145.14:20:42.68#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.14:20:42.68#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.14:20:42.68#ibcon#ireg 17 cls_cnt 0 2006.145.14:20:42.68#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.14:20:42.68#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.14:20:42.68#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.14:20:42.70#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.14:20:42.74#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.14:20:42.74#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.14:20:42.74#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.14:20:42.74#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.14:20:42.74$vck44/vb=5,4 2006.145.14:20:42.74#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.14:20:42.74#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.14:20:42.74#ibcon#ireg 11 cls_cnt 2 2006.145.14:20:42.74#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.14:20:42.80#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.14:20:42.80#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.14:20:42.82#ibcon#[27=AT05-04\r\n] 2006.145.14:20:42.85#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.14:20:42.85#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.14:20:42.85#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.14:20:42.85#ibcon#ireg 7 cls_cnt 0 2006.145.14:20:42.85#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.14:20:42.97#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.14:20:42.97#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.14:20:42.99#ibcon#[27=USB\r\n] 2006.145.14:20:43.02#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.14:20:43.02#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.14:20:43.02#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.14:20:43.02#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.14:20:43.02$vck44/vblo=6,719.99 2006.145.14:20:43.02#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.14:20:43.02#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.14:20:43.02#ibcon#ireg 17 cls_cnt 0 2006.145.14:20:43.02#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.14:20:43.02#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.14:20:43.02#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.14:20:43.04#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.14:20:43.08#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.14:20:43.08#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.14:20:43.08#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.14:20:43.08#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.14:20:43.08$vck44/vb=6,4 2006.145.14:20:43.08#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.14:20:43.08#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.14:20:43.08#ibcon#ireg 11 cls_cnt 2 2006.145.14:20:43.08#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.14:20:43.14#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.14:20:43.14#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.14:20:43.16#ibcon#[27=AT06-04\r\n] 2006.145.14:20:43.19#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.14:20:43.19#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.14:20:43.19#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.14:20:43.19#ibcon#ireg 7 cls_cnt 0 2006.145.14:20:43.19#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.14:20:43.31#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.14:20:43.31#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.14:20:43.33#ibcon#[27=USB\r\n] 2006.145.14:20:43.36#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.14:20:43.36#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.14:20:43.36#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.14:20:43.36#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.14:20:43.36$vck44/vblo=7,734.99 2006.145.14:20:43.36#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.14:20:43.36#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.14:20:43.36#ibcon#ireg 17 cls_cnt 0 2006.145.14:20:43.36#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:20:43.36#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:20:43.36#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:20:43.38#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.14:20:43.42#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:20:43.42#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:20:43.42#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.14:20:43.42#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.14:20:43.42$vck44/vb=7,4 2006.145.14:20:43.42#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.14:20:43.42#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.14:20:43.42#ibcon#ireg 11 cls_cnt 2 2006.145.14:20:43.42#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.14:20:43.48#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.14:20:43.48#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.14:20:43.50#ibcon#[27=AT07-04\r\n] 2006.145.14:20:43.53#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.14:20:43.53#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.14:20:43.53#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.14:20:43.53#ibcon#ireg 7 cls_cnt 0 2006.145.14:20:43.53#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.14:20:43.65#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.14:20:43.65#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.14:20:43.67#ibcon#[27=USB\r\n] 2006.145.14:20:43.70#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.14:20:43.70#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.14:20:43.70#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.14:20:43.70#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.14:20:43.70$vck44/vblo=8,744.99 2006.145.14:20:43.70#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.14:20:43.70#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.14:20:43.70#ibcon#ireg 17 cls_cnt 0 2006.145.14:20:43.70#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.14:20:43.70#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.14:20:43.70#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.14:20:43.72#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.14:20:43.76#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.14:20:43.76#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.14:20:43.76#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.14:20:43.76#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.14:20:43.76$vck44/vb=8,4 2006.145.14:20:43.76#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.14:20:43.76#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.14:20:43.76#ibcon#ireg 11 cls_cnt 2 2006.145.14:20:43.76#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.14:20:43.82#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.14:20:43.82#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.14:20:43.84#ibcon#[27=AT08-04\r\n] 2006.145.14:20:43.87#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.14:20:43.87#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.14:20:43.87#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.14:20:43.87#ibcon#ireg 7 cls_cnt 0 2006.145.14:20:43.87#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.14:20:43.99#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.14:20:43.99#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.14:20:44.01#ibcon#[27=USB\r\n] 2006.145.14:20:44.04#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.14:20:44.04#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.14:20:44.04#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.14:20:44.04#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.14:20:44.04$vck44/vabw=wide 2006.145.14:20:44.04#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.14:20:44.04#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.14:20:44.04#ibcon#ireg 8 cls_cnt 0 2006.145.14:20:44.04#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.14:20:44.04#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.14:20:44.04#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.14:20:44.06#ibcon#[25=BW32\r\n] 2006.145.14:20:44.09#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.14:20:44.09#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.14:20:44.09#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.14:20:44.09#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.14:20:44.09$vck44/vbbw=wide 2006.145.14:20:44.09#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.14:20:44.09#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.14:20:44.09#ibcon#ireg 8 cls_cnt 0 2006.145.14:20:44.09#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:20:44.16#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:20:44.16#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:20:44.18#ibcon#[27=BW32\r\n] 2006.145.14:20:44.21#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:20:44.21#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:20:44.21#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.14:20:44.21#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.14:20:44.21$setupk4/ifdk4 2006.145.14:20:44.21$ifdk4/lo= 2006.145.14:20:44.21$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.14:20:44.21$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.14:20:44.21$ifdk4/patch= 2006.145.14:20:44.21$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.14:20:44.21$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.14:20:44.21$setupk4/!*+20s 2006.145.14:20:48.14#trakl#Source acquired 2006.145.14:20:48.14#flagr#flagr/antenna,acquired 2006.145.14:20:51.67#abcon#<5=/08 0.7 1.4 15.12 881020.7\r\n> 2006.145.14:20:51.69#abcon#{5=INTERFACE CLEAR} 2006.145.14:20:51.75#abcon#[5=S1D000X0/0*\r\n] 2006.145.14:20:58.69$setupk4/"tpicd 2006.145.14:20:58.69$setupk4/echo=off 2006.145.14:20:58.69$setupk4/xlog=off 2006.145.14:20:58.69:!2006.145.14:20:53 2006.145.14:20:58.69:preob 2006.145.14:20:59.14/onsource/TRACKING 2006.145.14:20:59.14:!2006.145.14:21:03 2006.145.14:21:03.00:"tape 2006.145.14:21:03.00:"st=record 2006.145.14:21:03.00:data_valid=on 2006.145.14:21:03.00:midob 2006.145.14:21:03.14/onsource/TRACKING 2006.145.14:21:03.14/wx/15.12,1020.7,88 2006.145.14:21:03.29/cable/+6.5476E-03 2006.145.14:21:04.38/va/01,08,usb,yes,32,35 2006.145.14:21:04.38/va/02,07,usb,yes,35,35 2006.145.14:21:04.38/va/03,08,usb,yes,32,33 2006.145.14:21:04.38/va/04,07,usb,yes,36,38 2006.145.14:21:04.38/va/05,04,usb,yes,31,32 2006.145.14:21:04.38/va/06,04,usb,yes,35,35 2006.145.14:21:04.38/va/07,04,usb,yes,35,37 2006.145.14:21:04.38/va/08,04,usb,yes,30,36 2006.145.14:21:04.61/valo/01,524.99,yes,locked 2006.145.14:21:04.61/valo/02,534.99,yes,locked 2006.145.14:21:04.61/valo/03,564.99,yes,locked 2006.145.14:21:04.61/valo/04,624.99,yes,locked 2006.145.14:21:04.61/valo/05,734.99,yes,locked 2006.145.14:21:04.61/valo/06,814.99,yes,locked 2006.145.14:21:04.61/valo/07,864.99,yes,locked 2006.145.14:21:04.61/valo/08,884.99,yes,locked 2006.145.14:21:05.70/vb/01,03,usb,yes,38,72 2006.145.14:21:05.70/vb/02,04,usb,yes,33,65 2006.145.14:21:05.70/vb/03,04,usb,yes,30,39 2006.145.14:21:05.70/vb/04,04,usb,yes,34,33 2006.145.14:21:05.70/vb/05,04,usb,yes,27,30 2006.145.14:21:05.70/vb/06,04,usb,yes,32,28 2006.145.14:21:05.70/vb/07,04,usb,yes,31,31 2006.145.14:21:05.70/vb/08,04,usb,yes,29,32 2006.145.14:21:05.93/vblo/01,629.99,yes,locked 2006.145.14:21:05.93/vblo/02,634.99,yes,locked 2006.145.14:21:05.93/vblo/03,649.99,yes,locked 2006.145.14:21:05.93/vblo/04,679.99,yes,locked 2006.145.14:21:05.93/vblo/05,709.99,yes,locked 2006.145.14:21:05.93/vblo/06,719.99,yes,locked 2006.145.14:21:05.93/vblo/07,734.99,yes,locked 2006.145.14:21:05.93/vblo/08,744.99,yes,locked 2006.145.14:21:06.08/vabw/8 2006.145.14:21:06.23/vbbw/8 2006.145.14:21:06.32/xfe/off,on,15.0 2006.145.14:21:06.71/ifatt/23,28,28,28 2006.145.14:21:07.07/fmout-gps/S +5.2E-08 2006.145.14:21:07.15:!2006.145.14:23:13 2006.145.14:23:13.00:data_valid=off 2006.145.14:23:13.00:"et 2006.145.14:23:13.00:!+3s 2006.145.14:23:16.02:"tape 2006.145.14:23:16.02:postob 2006.145.14:23:16.22/cable/+6.5483E-03 2006.145.14:23:16.22/wx/15.15,1020.7,88 2006.145.14:23:17.08/fmout-gps/S +5.0E-08 2006.145.14:23:17.08:scan_name=145-1424,jd0605,120 2006.145.14:23:17.08:source=1908-201,191109.65,-200655.1,2000.0,cw 2006.145.14:23:18.13#flagr#flagr/antenna,new-source 2006.145.14:23:18.13:checkk5 2006.145.14:23:18.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.14:23:19.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.14:23:19.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.14:23:19.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.14:23:20.32/chk_obsdata//k5ts1/T1451421??a.dat file size is correct (nominal:520MB, actual:516MB). 2006.145.14:23:20.75/chk_obsdata//k5ts2/T1451421??b.dat file size is correct (nominal:520MB, actual:516MB). 2006.145.14:23:21.20/chk_obsdata//k5ts3/T1451421??c.dat file size is correct (nominal:520MB, actual:516MB). 2006.145.14:23:21.63/chk_obsdata//k5ts4/T1451421??d.dat file size is correct (nominal:520MB, actual:516MB). 2006.145.14:23:22.38/k5log//k5ts1_log_newline 2006.145.14:23:23.12/k5log//k5ts2_log_newline 2006.145.14:23:23.86/k5log//k5ts3_log_newline 2006.145.14:23:24.62/k5log//k5ts4_log_newline 2006.145.14:23:24.64/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.14:23:24.64:setupk4=1 2006.145.14:23:24.64$setupk4/echo=on 2006.145.14:23:24.64$setupk4/pcalon 2006.145.14:23:24.64$pcalon/"no phase cal control is implemented here 2006.145.14:23:24.64$setupk4/"tpicd=stop 2006.145.14:23:24.64$setupk4/"rec=synch_on 2006.145.14:23:24.64$setupk4/"rec_mode=128 2006.145.14:23:24.64$setupk4/!* 2006.145.14:23:24.64$setupk4/recpk4 2006.145.14:23:24.64$recpk4/recpatch= 2006.145.14:23:24.65$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.14:23:24.65$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.14:23:24.65$setupk4/vck44 2006.145.14:23:24.65$vck44/valo=1,524.99 2006.145.14:23:24.65#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.14:23:24.65#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.14:23:24.65#ibcon#ireg 17 cls_cnt 0 2006.145.14:23:24.65#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.14:23:24.65#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.14:23:24.65#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.14:23:24.69#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.14:23:24.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.14:23:24.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.14:23:24.74#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.14:23:24.74#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.14:23:24.74$vck44/va=1,8 2006.145.14:23:24.74#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.14:23:24.74#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.14:23:24.74#ibcon#ireg 11 cls_cnt 2 2006.145.14:23:24.74#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.14:23:24.74#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.14:23:24.74#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.14:23:24.76#ibcon#[25=AT01-08\r\n] 2006.145.14:23:24.79#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.14:23:24.79#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.14:23:24.79#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.14:23:24.79#ibcon#ireg 7 cls_cnt 0 2006.145.14:23:24.79#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.14:23:24.91#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.14:23:24.91#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.14:23:24.93#ibcon#[25=USB\r\n] 2006.145.14:23:24.96#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.14:23:24.96#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.14:23:24.96#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.14:23:24.96#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.14:23:24.96$vck44/valo=2,534.99 2006.145.14:23:24.96#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.14:23:24.96#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.14:23:24.96#ibcon#ireg 17 cls_cnt 0 2006.145.14:23:24.96#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:23:24.96#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:23:24.96#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:23:24.99#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.14:23:25.03#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:23:25.03#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:23:25.03#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.14:23:25.03#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.14:23:25.03$vck44/va=2,7 2006.145.14:23:25.03#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.14:23:25.03#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.14:23:25.03#ibcon#ireg 11 cls_cnt 2 2006.145.14:23:25.03#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:23:25.08#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:23:25.08#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:23:25.10#ibcon#[25=AT02-07\r\n] 2006.145.14:23:25.13#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:23:25.13#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:23:25.13#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.14:23:25.13#ibcon#ireg 7 cls_cnt 0 2006.145.14:23:25.13#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:23:25.25#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:23:25.25#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:23:25.27#ibcon#[25=USB\r\n] 2006.145.14:23:25.30#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:23:25.30#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:23:25.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.14:23:25.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.14:23:25.30$vck44/valo=3,564.99 2006.145.14:23:25.30#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.14:23:25.30#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.14:23:25.30#ibcon#ireg 17 cls_cnt 0 2006.145.14:23:25.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:23:25.30#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:23:25.30#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:23:25.32#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.14:23:25.36#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:23:25.36#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:23:25.36#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.14:23:25.36#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.14:23:25.36$vck44/va=3,8 2006.145.14:23:25.36#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.14:23:25.36#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.14:23:25.36#ibcon#ireg 11 cls_cnt 2 2006.145.14:23:25.36#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:23:25.42#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:23:25.42#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:23:25.44#ibcon#[25=AT03-08\r\n] 2006.145.14:23:25.47#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:23:25.47#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:23:25.47#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.14:23:25.47#ibcon#ireg 7 cls_cnt 0 2006.145.14:23:25.47#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:23:25.59#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:23:25.59#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:23:25.61#ibcon#[25=USB\r\n] 2006.145.14:23:25.64#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:23:25.64#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:23:25.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.14:23:25.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.14:23:25.64$vck44/valo=4,624.99 2006.145.14:23:25.64#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.14:23:25.64#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.14:23:25.64#ibcon#ireg 17 cls_cnt 0 2006.145.14:23:25.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:23:25.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:23:25.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:23:25.66#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.14:23:25.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:23:25.70#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:23:25.70#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.14:23:25.70#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.14:23:25.70$vck44/va=4,7 2006.145.14:23:25.70#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.14:23:25.70#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.14:23:25.70#ibcon#ireg 11 cls_cnt 2 2006.145.14:23:25.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.14:23:25.76#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.14:23:25.76#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.14:23:25.78#ibcon#[25=AT04-07\r\n] 2006.145.14:23:25.81#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.14:23:25.81#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.14:23:25.81#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.14:23:25.81#ibcon#ireg 7 cls_cnt 0 2006.145.14:23:25.81#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.14:23:25.93#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.14:23:25.93#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.14:23:25.95#ibcon#[25=USB\r\n] 2006.145.14:23:25.98#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.14:23:25.98#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.14:23:25.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.14:23:25.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.14:23:25.98$vck44/valo=5,734.99 2006.145.14:23:25.98#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.14:23:25.98#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.14:23:25.98#ibcon#ireg 17 cls_cnt 0 2006.145.14:23:25.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:23:25.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:23:25.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:23:26.00#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.14:23:26.04#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:23:26.04#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:23:26.04#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.14:23:26.04#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.14:23:26.04$vck44/va=5,4 2006.145.14:23:26.04#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.14:23:26.04#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.14:23:26.04#ibcon#ireg 11 cls_cnt 2 2006.145.14:23:26.04#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:23:26.10#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:23:26.10#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:23:26.12#ibcon#[25=AT05-04\r\n] 2006.145.14:23:26.15#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:23:26.15#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:23:26.15#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.14:23:26.15#ibcon#ireg 7 cls_cnt 0 2006.145.14:23:26.15#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:23:26.27#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:23:26.27#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:23:26.29#ibcon#[25=USB\r\n] 2006.145.14:23:26.32#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:23:26.32#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:23:26.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.14:23:26.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.14:23:26.32$vck44/valo=6,814.99 2006.145.14:23:26.32#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.14:23:26.32#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.14:23:26.32#ibcon#ireg 17 cls_cnt 0 2006.145.14:23:26.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:23:26.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:23:26.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:23:26.34#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.14:23:26.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:23:26.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:23:26.38#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.14:23:26.38#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.14:23:26.38$vck44/va=6,4 2006.145.14:23:26.38#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.14:23:26.38#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.14:23:26.38#ibcon#ireg 11 cls_cnt 2 2006.145.14:23:26.38#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:23:26.44#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:23:26.44#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:23:26.46#ibcon#[25=AT06-04\r\n] 2006.145.14:23:26.49#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:23:26.49#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:23:26.49#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.14:23:26.49#ibcon#ireg 7 cls_cnt 0 2006.145.14:23:26.49#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:23:26.61#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:23:26.61#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:23:26.63#ibcon#[25=USB\r\n] 2006.145.14:23:26.66#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:23:26.66#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:23:26.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.14:23:26.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.14:23:26.66$vck44/valo=7,864.99 2006.145.14:23:26.66#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.14:23:26.66#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.14:23:26.66#ibcon#ireg 17 cls_cnt 0 2006.145.14:23:26.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:23:26.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:23:26.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:23:26.68#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.14:23:26.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:23:26.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:23:26.72#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.14:23:26.72#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.14:23:26.72$vck44/va=7,4 2006.145.14:23:26.72#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.14:23:26.72#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.14:23:26.72#ibcon#ireg 11 cls_cnt 2 2006.145.14:23:26.72#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:23:26.78#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:23:26.78#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:23:26.80#ibcon#[25=AT07-04\r\n] 2006.145.14:23:26.83#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:23:26.83#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:23:26.83#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.14:23:26.83#ibcon#ireg 7 cls_cnt 0 2006.145.14:23:26.83#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:23:26.95#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:23:26.95#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:23:26.97#ibcon#[25=USB\r\n] 2006.145.14:23:27.00#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:23:27.00#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:23:27.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.14:23:27.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.14:23:27.00$vck44/valo=8,884.99 2006.145.14:23:27.00#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.14:23:27.00#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.14:23:27.00#ibcon#ireg 17 cls_cnt 0 2006.145.14:23:27.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.14:23:27.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.14:23:27.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.14:23:27.02#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.14:23:27.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.14:23:27.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.14:23:27.06#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.14:23:27.06#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.14:23:27.06$vck44/va=8,4 2006.145.14:23:27.06#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.14:23:27.06#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.14:23:27.06#ibcon#ireg 11 cls_cnt 2 2006.145.14:23:27.06#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.14:23:27.12#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.14:23:27.12#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.14:23:27.14#ibcon#[25=AT08-04\r\n] 2006.145.14:23:27.17#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.14:23:27.17#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.14:23:27.17#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.14:23:27.17#ibcon#ireg 7 cls_cnt 0 2006.145.14:23:27.17#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.14:23:27.30#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.14:23:27.30#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.14:23:27.32#ibcon#[25=USB\r\n] 2006.145.14:23:27.35#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.14:23:27.35#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.14:23:27.35#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.14:23:27.35#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.14:23:27.35$vck44/vblo=1,629.99 2006.145.14:23:27.35#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.14:23:27.35#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.14:23:27.35#ibcon#ireg 17 cls_cnt 0 2006.145.14:23:27.35#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.14:23:27.35#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.14:23:27.35#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.14:23:27.38#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.14:23:27.42#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.14:23:27.42#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.14:23:27.42#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.14:23:27.42#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.14:23:27.42$vck44/vb=1,3 2006.145.14:23:27.42#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.14:23:27.42#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.14:23:27.42#ibcon#ireg 11 cls_cnt 2 2006.145.14:23:27.42#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.14:23:27.42#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.14:23:27.42#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.14:23:27.44#ibcon#[27=AT01-03\r\n] 2006.145.14:23:27.47#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.14:23:27.47#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.14:23:27.47#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.14:23:27.47#ibcon#ireg 7 cls_cnt 0 2006.145.14:23:27.47#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.14:23:27.59#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.14:23:27.59#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.14:23:27.61#ibcon#[27=USB\r\n] 2006.145.14:23:27.64#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.14:23:27.64#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.14:23:27.64#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.14:23:27.64#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.14:23:27.64$vck44/vblo=2,634.99 2006.145.14:23:27.64#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.14:23:27.64#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.14:23:27.64#ibcon#ireg 17 cls_cnt 0 2006.145.14:23:27.64#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.14:23:27.64#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.14:23:27.64#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.14:23:27.66#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.14:23:27.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.14:23:27.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.14:23:27.70#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.14:23:27.70#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.14:23:27.70$vck44/vb=2,4 2006.145.14:23:27.70#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.14:23:27.70#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.14:23:27.70#ibcon#ireg 11 cls_cnt 2 2006.145.14:23:27.70#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.14:23:27.76#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.14:23:27.76#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.14:23:27.78#ibcon#[27=AT02-04\r\n] 2006.145.14:23:27.81#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.14:23:27.81#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.14:23:27.81#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.14:23:27.81#ibcon#ireg 7 cls_cnt 0 2006.145.14:23:27.81#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.14:23:27.93#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.14:23:27.93#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.14:23:27.95#ibcon#[27=USB\r\n] 2006.145.14:23:27.98#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.14:23:27.98#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.14:23:27.98#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.14:23:27.98#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.14:23:27.98$vck44/vblo=3,649.99 2006.145.14:23:27.98#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.14:23:27.98#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.14:23:27.98#ibcon#ireg 17 cls_cnt 0 2006.145.14:23:27.98#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:23:27.98#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:23:27.98#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:23:28.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.14:23:28.04#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:23:28.04#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:23:28.04#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.14:23:28.04#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.14:23:28.04$vck44/vb=3,4 2006.145.14:23:28.04#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.14:23:28.04#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.14:23:28.04#ibcon#ireg 11 cls_cnt 2 2006.145.14:23:28.04#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:23:28.10#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:23:28.10#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:23:28.12#ibcon#[27=AT03-04\r\n] 2006.145.14:23:28.15#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:23:28.15#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:23:28.15#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.14:23:28.15#ibcon#ireg 7 cls_cnt 0 2006.145.14:23:28.15#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:23:28.27#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:23:28.27#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:23:28.29#ibcon#[27=USB\r\n] 2006.145.14:23:28.32#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:23:28.32#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:23:28.32#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.14:23:28.32#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.14:23:28.32$vck44/vblo=4,679.99 2006.145.14:23:28.32#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.14:23:28.32#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.14:23:28.32#ibcon#ireg 17 cls_cnt 0 2006.145.14:23:28.32#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:23:28.32#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:23:28.32#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:23:28.34#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.14:23:28.38#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:23:28.38#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:23:28.38#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.14:23:28.38#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.14:23:28.38$vck44/vb=4,4 2006.145.14:23:28.38#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.14:23:28.38#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.14:23:28.38#ibcon#ireg 11 cls_cnt 2 2006.145.14:23:28.38#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:23:28.44#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:23:28.44#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:23:28.46#ibcon#[27=AT04-04\r\n] 2006.145.14:23:28.49#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:23:28.49#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:23:28.49#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.14:23:28.49#ibcon#ireg 7 cls_cnt 0 2006.145.14:23:28.49#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:23:28.61#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:23:28.61#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:23:28.63#ibcon#[27=USB\r\n] 2006.145.14:23:28.66#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:23:28.66#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:23:28.66#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.14:23:28.66#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.14:23:28.66$vck44/vblo=5,709.99 2006.145.14:23:28.66#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.14:23:28.66#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.14:23:28.66#ibcon#ireg 17 cls_cnt 0 2006.145.14:23:28.66#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:23:28.66#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:23:28.66#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:23:28.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.14:23:28.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:23:28.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:23:28.72#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.14:23:28.72#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.14:23:28.72$vck44/vb=5,4 2006.145.14:23:28.72#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.14:23:28.72#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.14:23:28.72#ibcon#ireg 11 cls_cnt 2 2006.145.14:23:28.72#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.14:23:28.78#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.14:23:28.78#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.14:23:28.80#ibcon#[27=AT05-04\r\n] 2006.145.14:23:28.83#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.14:23:28.83#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.14:23:28.83#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.14:23:28.83#ibcon#ireg 7 cls_cnt 0 2006.145.14:23:28.83#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.14:23:28.95#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.14:23:28.95#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.14:23:28.97#ibcon#[27=USB\r\n] 2006.145.14:23:29.00#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.14:23:29.00#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.14:23:29.00#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.14:23:29.00#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.14:23:29.00$vck44/vblo=6,719.99 2006.145.14:23:29.00#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.14:23:29.00#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.14:23:29.00#ibcon#ireg 17 cls_cnt 0 2006.145.14:23:29.00#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:23:29.00#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:23:29.00#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:23:29.02#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.14:23:29.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:23:29.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:23:29.06#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.14:23:29.06#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.14:23:29.06$vck44/vb=6,4 2006.145.14:23:29.06#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.14:23:29.06#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.14:23:29.06#ibcon#ireg 11 cls_cnt 2 2006.145.14:23:29.06#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:23:29.12#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:23:29.12#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:23:29.14#ibcon#[27=AT06-04\r\n] 2006.145.14:23:29.17#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:23:29.17#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:23:29.17#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.14:23:29.17#ibcon#ireg 7 cls_cnt 0 2006.145.14:23:29.17#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:23:29.29#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:23:29.29#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:23:29.31#ibcon#[27=USB\r\n] 2006.145.14:23:29.34#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:23:29.34#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:23:29.34#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.14:23:29.34#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.14:23:29.34$vck44/vblo=7,734.99 2006.145.14:23:29.34#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.14:23:29.34#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.14:23:29.34#ibcon#ireg 17 cls_cnt 0 2006.145.14:23:29.34#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:23:29.34#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:23:29.34#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:23:29.36#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.14:23:29.40#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:23:29.40#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:23:29.40#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.14:23:29.40#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.14:23:29.40$vck44/vb=7,4 2006.145.14:23:29.40#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.14:23:29.40#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.14:23:29.40#ibcon#ireg 11 cls_cnt 2 2006.145.14:23:29.40#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:23:29.46#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:23:29.46#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:23:29.48#ibcon#[27=AT07-04\r\n] 2006.145.14:23:29.51#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:23:29.51#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:23:29.51#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.14:23:29.51#ibcon#ireg 7 cls_cnt 0 2006.145.14:23:29.51#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:23:29.63#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:23:29.63#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:23:29.65#ibcon#[27=USB\r\n] 2006.145.14:23:29.68#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:23:29.68#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:23:29.68#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.14:23:29.68#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.14:23:29.68$vck44/vblo=8,744.99 2006.145.14:23:29.68#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.14:23:29.68#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.14:23:29.68#ibcon#ireg 17 cls_cnt 0 2006.145.14:23:29.68#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:23:29.68#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:23:29.68#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:23:29.70#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.14:23:29.74#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:23:29.74#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:23:29.74#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.14:23:29.74#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.14:23:29.74$vck44/vb=8,4 2006.145.14:23:29.74#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.14:23:29.74#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.14:23:29.74#ibcon#ireg 11 cls_cnt 2 2006.145.14:23:29.74#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:23:29.80#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:23:29.80#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:23:29.82#ibcon#[27=AT08-04\r\n] 2006.145.14:23:29.85#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:23:29.85#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:23:29.85#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.14:23:29.85#ibcon#ireg 7 cls_cnt 0 2006.145.14:23:29.85#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:23:29.97#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:23:29.97#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:23:29.99#ibcon#[27=USB\r\n] 2006.145.14:23:30.02#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:23:30.02#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:23:30.02#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.14:23:30.02#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.14:23:30.02$vck44/vabw=wide 2006.145.14:23:30.02#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.14:23:30.02#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.14:23:30.02#ibcon#ireg 8 cls_cnt 0 2006.145.14:23:30.02#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.14:23:30.02#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.14:23:30.02#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.14:23:30.04#ibcon#[25=BW32\r\n] 2006.145.14:23:30.07#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.14:23:30.07#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.14:23:30.07#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.14:23:30.07#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.14:23:30.07$vck44/vbbw=wide 2006.145.14:23:30.07#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.14:23:30.07#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.14:23:30.07#ibcon#ireg 8 cls_cnt 0 2006.145.14:23:30.07#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.14:23:30.14#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.14:23:30.14#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.14:23:30.16#ibcon#[27=BW32\r\n] 2006.145.14:23:30.19#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.14:23:30.19#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.14:23:30.19#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.14:23:30.19#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.14:23:30.19$setupk4/ifdk4 2006.145.14:23:30.19$ifdk4/lo= 2006.145.14:23:30.19$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.14:23:30.19$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.14:23:30.19$ifdk4/patch= 2006.145.14:23:30.19$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.14:23:30.19$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.14:23:30.19$setupk4/!*+20s 2006.145.14:23:34.48#abcon#<5=/08 0.8 1.5 15.16 881020.7\r\n> 2006.145.14:23:34.50#abcon#{5=INTERFACE CLEAR} 2006.145.14:23:34.56#abcon#[5=S1D000X0/0*\r\n] 2006.145.14:23:44.13#trakl#Source acquired 2006.145.14:23:44.65#abcon#<5=/08 0.8 1.5 15.16 871020.7\r\n> 2006.145.14:23:44.65$setupk4/"tpicd 2006.145.14:23:44.65$setupk4/echo=off 2006.145.14:23:44.65$setupk4/xlog=off 2006.145.14:23:44.65:!2006.145.14:24:05 2006.145.14:23:44.67#abcon#{5=INTERFACE CLEAR} 2006.145.14:23:46.13#flagr#flagr/antenna,acquired 2006.145.14:24:05.00:preob 2006.145.14:24:05.13/onsource/TRACKING 2006.145.14:24:05.13:!2006.145.14:24:15 2006.145.14:24:15.00:"tape 2006.145.14:24:15.00:"st=record 2006.145.14:24:15.00:data_valid=on 2006.145.14:24:15.00:midob 2006.145.14:24:16.13/onsource/TRACKING 2006.145.14:24:16.13/wx/15.17,1020.7,87 2006.145.14:24:16.22/cable/+6.5488E-03 2006.145.14:24:17.31/va/01,08,usb,yes,30,32 2006.145.14:24:17.31/va/02,07,usb,yes,32,33 2006.145.14:24:17.31/va/03,08,usb,yes,30,31 2006.145.14:24:17.31/va/04,07,usb,yes,34,35 2006.145.14:24:17.31/va/05,04,usb,yes,29,30 2006.145.14:24:17.31/va/06,04,usb,yes,33,33 2006.145.14:24:17.31/va/07,04,usb,yes,33,34 2006.145.14:24:17.31/va/08,04,usb,yes,28,34 2006.145.14:24:17.54/valo/01,524.99,yes,locked 2006.145.14:24:17.54/valo/02,534.99,yes,locked 2006.145.14:24:17.54/valo/03,564.99,yes,locked 2006.145.14:24:17.54/valo/04,624.99,yes,locked 2006.145.14:24:17.54/valo/05,734.99,yes,locked 2006.145.14:24:17.54/valo/06,814.99,yes,locked 2006.145.14:24:17.54/valo/07,864.99,yes,locked 2006.145.14:24:17.54/valo/08,884.99,yes,locked 2006.145.14:24:18.63/vb/01,03,usb,yes,36,33 2006.145.14:24:18.63/vb/02,04,usb,yes,31,31 2006.145.14:24:18.63/vb/03,04,usb,yes,29,31 2006.145.14:24:18.63/vb/04,04,usb,yes,33,32 2006.145.14:24:18.63/vb/05,04,usb,yes,26,28 2006.145.14:24:18.63/vb/06,04,usb,yes,30,26 2006.145.14:24:18.63/vb/07,04,usb,yes,31,30 2006.145.14:24:18.63/vb/08,04,usb,yes,28,32 2006.145.14:24:18.87/vblo/01,629.99,yes,locked 2006.145.14:24:18.87/vblo/02,634.99,yes,locked 2006.145.14:24:18.87/vblo/03,649.99,yes,locked 2006.145.14:24:18.87/vblo/04,679.99,yes,locked 2006.145.14:24:18.87/vblo/05,709.99,yes,locked 2006.145.14:24:18.87/vblo/06,719.99,yes,locked 2006.145.14:24:18.87/vblo/07,734.99,yes,locked 2006.145.14:24:18.87/vblo/08,744.99,yes,locked 2006.145.14:24:19.02/vabw/8 2006.145.14:24:19.17/vbbw/8 2006.145.14:24:19.26/xfe/off,on,15.0 2006.145.14:24:19.63/ifatt/23,28,28,28 2006.145.14:24:20.07/fmout-gps/S +5.1E-08 2006.145.14:24:20.11:!2006.145.14:26:15 2006.145.14:26:15.00:data_valid=off 2006.145.14:26:15.00:"et 2006.145.14:26:15.00:!+3s 2006.145.14:26:18.02:"tape 2006.145.14:26:18.02:postob 2006.145.14:26:18.13/cable/+6.5487E-03 2006.145.14:26:18.13/wx/15.20,1020.7,87 2006.145.14:26:19.08/fmout-gps/S +5.0E-08 2006.145.14:26:19.08:scan_name=145-1432,jd0605,100 2006.145.14:26:19.08:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.145.14:26:19.14#flagr#flagr/antenna,new-source 2006.145.14:26:20.14:checkk5 2006.145.14:26:20.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.14:26:21.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.14:26:21.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.14:26:21.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.14:26:22.31/chk_obsdata//k5ts1/T1451424??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.14:26:22.76/chk_obsdata//k5ts2/T1451424??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.14:26:23.20/chk_obsdata//k5ts3/T1451424??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.14:26:23.64/chk_obsdata//k5ts4/T1451424??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.14:26:24.39/k5log//k5ts1_log_newline 2006.145.14:26:25.14/k5log//k5ts2_log_newline 2006.145.14:26:25.87/k5log//k5ts3_log_newline 2006.145.14:26:26.61/k5log//k5ts4_log_newline 2006.145.14:26:26.63/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.14:26:26.63:setupk4=1 2006.145.14:26:26.63$setupk4/echo=on 2006.145.14:26:26.63$setupk4/pcalon 2006.145.14:26:26.63$pcalon/"no phase cal control is implemented here 2006.145.14:26:26.63$setupk4/"tpicd=stop 2006.145.14:26:26.63$setupk4/"rec=synch_on 2006.145.14:26:26.63$setupk4/"rec_mode=128 2006.145.14:26:26.64$setupk4/!* 2006.145.14:26:26.64$setupk4/recpk4 2006.145.14:26:26.64$recpk4/recpatch= 2006.145.14:26:26.64$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.14:26:26.64$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.14:26:26.64$setupk4/vck44 2006.145.14:26:26.64$vck44/valo=1,524.99 2006.145.14:26:26.64#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.14:26:26.64#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.14:26:26.64#ibcon#ireg 17 cls_cnt 0 2006.145.14:26:26.64#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:26:26.64#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:26:26.64#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:26:26.68#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.14:26:26.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:26:26.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:26:26.73#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.14:26:26.73#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.14:26:26.73$vck44/va=1,8 2006.145.14:26:26.73#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.14:26:26.73#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.14:26:26.73#ibcon#ireg 11 cls_cnt 2 2006.145.14:26:26.73#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:26:26.73#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:26:26.73#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:26:26.75#ibcon#[25=AT01-08\r\n] 2006.145.14:26:26.78#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:26:26.78#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:26:26.78#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.14:26:26.78#ibcon#ireg 7 cls_cnt 0 2006.145.14:26:26.78#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:26:26.90#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:26:26.90#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:26:26.92#ibcon#[25=USB\r\n] 2006.145.14:26:26.96#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:26:26.96#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:26:26.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.14:26:26.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.14:26:26.96$vck44/valo=2,534.99 2006.145.14:26:26.96#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.14:26:26.96#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.14:26:26.96#ibcon#ireg 17 cls_cnt 0 2006.145.14:26:26.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:26:26.96#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:26:26.96#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:26:26.98#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.14:26:27.02#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:26:27.02#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:26:27.02#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.14:26:27.02#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.14:26:27.02$vck44/va=2,7 2006.145.14:26:27.02#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.14:26:27.02#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.14:26:27.02#ibcon#ireg 11 cls_cnt 2 2006.145.14:26:27.02#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:26:27.08#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:26:27.08#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:26:27.10#ibcon#[25=AT02-07\r\n] 2006.145.14:26:27.13#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:26:27.13#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:26:27.13#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.14:26:27.13#ibcon#ireg 7 cls_cnt 0 2006.145.14:26:27.13#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:26:27.25#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:26:27.25#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:26:27.27#ibcon#[25=USB\r\n] 2006.145.14:26:27.30#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:26:27.30#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:26:27.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.14:26:27.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.14:26:27.30$vck44/valo=3,564.99 2006.145.14:26:27.30#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.14:26:27.30#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.14:26:27.30#ibcon#ireg 17 cls_cnt 0 2006.145.14:26:27.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:26:27.30#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:26:27.30#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:26:27.32#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.14:26:27.36#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:26:27.36#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:26:27.36#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.14:26:27.36#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.14:26:27.36$vck44/va=3,8 2006.145.14:26:27.36#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.14:26:27.36#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.14:26:27.36#ibcon#ireg 11 cls_cnt 2 2006.145.14:26:27.36#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:26:27.38#abcon#<5=/08 0.8 1.4 15.21 871020.7\r\n> 2006.145.14:26:27.40#abcon#{5=INTERFACE CLEAR} 2006.145.14:26:27.42#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:26:27.42#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:26:27.44#ibcon#[25=AT03-08\r\n] 2006.145.14:26:27.46#abcon#[5=S1D000X0/0*\r\n] 2006.145.14:26:27.47#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:26:27.47#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:26:27.47#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.14:26:27.47#ibcon#ireg 7 cls_cnt 0 2006.145.14:26:27.47#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:26:27.59#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:26:27.59#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:26:27.61#ibcon#[25=USB\r\n] 2006.145.14:26:27.64#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:26:27.64#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:26:27.64#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.14:26:27.64#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.14:26:27.64$vck44/valo=4,624.99 2006.145.14:26:27.64#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.14:26:27.64#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.14:26:27.64#ibcon#ireg 17 cls_cnt 0 2006.145.14:26:27.64#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:26:27.64#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:26:27.64#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:26:27.66#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.14:26:27.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:26:27.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:26:27.70#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.14:26:27.70#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.14:26:27.70$vck44/va=4,7 2006.145.14:26:27.70#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.14:26:27.70#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.14:26:27.70#ibcon#ireg 11 cls_cnt 2 2006.145.14:26:27.70#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.14:26:27.76#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.14:26:27.76#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.14:26:27.78#ibcon#[25=AT04-07\r\n] 2006.145.14:26:27.81#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.14:26:27.81#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.14:26:27.81#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.14:26:27.81#ibcon#ireg 7 cls_cnt 0 2006.145.14:26:27.81#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.14:26:27.93#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.14:26:27.93#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.14:26:27.95#ibcon#[25=USB\r\n] 2006.145.14:26:27.98#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.14:26:27.98#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.14:26:27.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.14:26:27.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.14:26:27.98$vck44/valo=5,734.99 2006.145.14:26:27.98#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.14:26:27.98#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.14:26:27.98#ibcon#ireg 17 cls_cnt 0 2006.145.14:26:27.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.14:26:27.98#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.14:26:27.98#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.14:26:28.00#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.14:26:28.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.14:26:28.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.14:26:28.04#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.14:26:28.04#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.14:26:28.04$vck44/va=5,4 2006.145.14:26:28.04#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.14:26:28.04#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.14:26:28.04#ibcon#ireg 11 cls_cnt 2 2006.145.14:26:28.04#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.14:26:28.10#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.14:26:28.10#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.14:26:28.12#ibcon#[25=AT05-04\r\n] 2006.145.14:26:28.15#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.14:26:28.15#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.14:26:28.15#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.14:26:28.15#ibcon#ireg 7 cls_cnt 0 2006.145.14:26:28.15#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.14:26:28.27#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.14:26:28.27#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.14:26:28.29#ibcon#[25=USB\r\n] 2006.145.14:26:28.32#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.14:26:28.32#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.14:26:28.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.14:26:28.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.14:26:28.32$vck44/valo=6,814.99 2006.145.14:26:28.32#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.14:26:28.32#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.14:26:28.32#ibcon#ireg 17 cls_cnt 0 2006.145.14:26:28.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:26:28.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:26:28.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:26:28.34#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.14:26:28.39#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:26:28.39#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:26:28.39#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.14:26:28.39#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.14:26:28.39$vck44/va=6,4 2006.145.14:26:28.39#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.14:26:28.39#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.14:26:28.39#ibcon#ireg 11 cls_cnt 2 2006.145.14:26:28.39#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.14:26:28.45#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.14:26:28.45#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.14:26:28.47#ibcon#[25=AT06-04\r\n] 2006.145.14:26:28.50#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.14:26:28.50#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.14:26:28.50#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.14:26:28.50#ibcon#ireg 7 cls_cnt 0 2006.145.14:26:28.50#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.14:26:28.62#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.14:26:28.62#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.14:26:28.64#ibcon#[25=USB\r\n] 2006.145.14:26:28.67#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.14:26:28.67#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.14:26:28.67#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.14:26:28.67#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.14:26:28.67$vck44/valo=7,864.99 2006.145.14:26:28.67#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.14:26:28.67#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.14:26:28.67#ibcon#ireg 17 cls_cnt 0 2006.145.14:26:28.67#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.14:26:28.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.14:26:28.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.14:26:28.69#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.14:26:28.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.14:26:28.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.14:26:28.73#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.14:26:28.73#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.14:26:28.73$vck44/va=7,4 2006.145.14:26:28.73#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.14:26:28.73#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.14:26:28.73#ibcon#ireg 11 cls_cnt 2 2006.145.14:26:28.73#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.14:26:28.79#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.14:26:28.79#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.14:26:28.81#ibcon#[25=AT07-04\r\n] 2006.145.14:26:28.84#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.14:26:28.84#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.14:26:28.84#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.14:26:28.84#ibcon#ireg 7 cls_cnt 0 2006.145.14:26:28.84#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.14:26:28.96#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.14:26:28.96#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.14:26:28.98#ibcon#[25=USB\r\n] 2006.145.14:26:29.01#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.14:26:29.01#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.14:26:29.01#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.14:26:29.01#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.14:26:29.01$vck44/valo=8,884.99 2006.145.14:26:29.01#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.14:26:29.01#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.14:26:29.01#ibcon#ireg 17 cls_cnt 0 2006.145.14:26:29.01#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:26:29.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:26:29.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:26:29.03#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.14:26:29.07#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:26:29.07#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:26:29.07#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.14:26:29.07#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.14:26:29.07$vck44/va=8,4 2006.145.14:26:29.07#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.14:26:29.07#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.14:26:29.07#ibcon#ireg 11 cls_cnt 2 2006.145.14:26:29.07#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.14:26:29.13#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.14:26:29.13#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.14:26:29.15#ibcon#[25=AT08-04\r\n] 2006.145.14:26:29.18#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.14:26:29.18#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.14:26:29.18#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.14:26:29.18#ibcon#ireg 7 cls_cnt 0 2006.145.14:26:29.18#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.14:26:29.30#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.14:26:29.30#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.14:26:29.32#ibcon#[25=USB\r\n] 2006.145.14:26:29.35#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.14:26:29.35#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.14:26:29.35#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.14:26:29.35#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.14:26:29.35$vck44/vblo=1,629.99 2006.145.14:26:29.35#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.14:26:29.35#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.14:26:29.35#ibcon#ireg 17 cls_cnt 0 2006.145.14:26:29.35#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:26:29.35#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:26:29.35#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:26:29.37#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.14:26:29.41#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:26:29.41#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:26:29.41#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.14:26:29.41#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.14:26:29.41$vck44/vb=1,3 2006.145.14:26:29.41#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.14:26:29.41#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.14:26:29.41#ibcon#ireg 11 cls_cnt 2 2006.145.14:26:29.41#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:26:29.41#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:26:29.41#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:26:29.43#ibcon#[27=AT01-03\r\n] 2006.145.14:26:29.46#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:26:29.46#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:26:29.46#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.14:26:29.46#ibcon#ireg 7 cls_cnt 0 2006.145.14:26:29.46#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:26:29.58#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:26:29.58#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:26:29.60#ibcon#[27=USB\r\n] 2006.145.14:26:29.63#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:26:29.63#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:26:29.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.14:26:29.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.14:26:29.63$vck44/vblo=2,634.99 2006.145.14:26:29.63#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.14:26:29.63#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.14:26:29.63#ibcon#ireg 17 cls_cnt 0 2006.145.14:26:29.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:26:29.63#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:26:29.63#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:26:29.65#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.14:26:29.69#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:26:29.69#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:26:29.69#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.14:26:29.69#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.14:26:29.69$vck44/vb=2,4 2006.145.14:26:29.69#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.14:26:29.69#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.14:26:29.69#ibcon#ireg 11 cls_cnt 2 2006.145.14:26:29.69#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:26:29.75#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:26:29.75#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:26:29.77#ibcon#[27=AT02-04\r\n] 2006.145.14:26:29.80#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:26:29.80#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:26:29.80#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.14:26:29.80#ibcon#ireg 7 cls_cnt 0 2006.145.14:26:29.80#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:26:29.92#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:26:29.92#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:26:29.94#ibcon#[27=USB\r\n] 2006.145.14:26:29.97#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:26:29.97#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:26:29.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.14:26:29.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.14:26:29.97$vck44/vblo=3,649.99 2006.145.14:26:29.97#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.14:26:29.97#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.14:26:29.97#ibcon#ireg 17 cls_cnt 0 2006.145.14:26:29.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:26:29.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:26:29.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:26:29.99#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.14:26:30.03#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:26:30.03#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:26:30.03#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.14:26:30.03#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.14:26:30.03$vck44/vb=3,4 2006.145.14:26:30.03#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.14:26:30.03#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.14:26:30.03#ibcon#ireg 11 cls_cnt 2 2006.145.14:26:30.03#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.14:26:30.09#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.14:26:30.09#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.14:26:30.11#ibcon#[27=AT03-04\r\n] 2006.145.14:26:30.14#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.14:26:30.14#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.14:26:30.14#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.14:26:30.14#ibcon#ireg 7 cls_cnt 0 2006.145.14:26:30.14#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.14:26:30.26#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.14:26:30.26#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.14:26:30.28#ibcon#[27=USB\r\n] 2006.145.14:26:30.31#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.14:26:30.31#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.14:26:30.31#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.14:26:30.31#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.14:26:30.31$vck44/vblo=4,679.99 2006.145.14:26:30.31#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.14:26:30.31#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.14:26:30.31#ibcon#ireg 17 cls_cnt 0 2006.145.14:26:30.31#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.14:26:30.31#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.14:26:30.31#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.14:26:30.33#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.14:26:30.37#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.14:26:30.37#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.14:26:30.37#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.14:26:30.37#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.14:26:30.37$vck44/vb=4,4 2006.145.14:26:30.37#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.14:26:30.37#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.14:26:30.37#ibcon#ireg 11 cls_cnt 2 2006.145.14:26:30.37#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.14:26:30.43#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.14:26:30.43#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.14:26:30.45#ibcon#[27=AT04-04\r\n] 2006.145.14:26:30.48#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.14:26:30.48#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.14:26:30.48#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.14:26:30.48#ibcon#ireg 7 cls_cnt 0 2006.145.14:26:30.48#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.14:26:30.60#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.14:26:30.60#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.14:26:30.62#ibcon#[27=USB\r\n] 2006.145.14:26:30.65#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.14:26:30.65#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.14:26:30.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.14:26:30.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.14:26:30.65$vck44/vblo=5,709.99 2006.145.14:26:30.65#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.14:26:30.65#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.14:26:30.65#ibcon#ireg 17 cls_cnt 0 2006.145.14:26:30.65#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:26:30.65#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:26:30.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:26:30.67#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.14:26:30.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:26:30.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:26:30.71#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.14:26:30.71#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.14:26:30.71$vck44/vb=5,4 2006.145.14:26:30.71#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.14:26:30.71#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.14:26:30.71#ibcon#ireg 11 cls_cnt 2 2006.145.14:26:30.71#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.14:26:30.77#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.14:26:30.77#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.14:26:30.79#ibcon#[27=AT05-04\r\n] 2006.145.14:26:30.82#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.14:26:30.82#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.14:26:30.82#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.14:26:30.82#ibcon#ireg 7 cls_cnt 0 2006.145.14:26:30.82#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.14:26:30.94#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.14:26:30.94#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.14:26:30.96#ibcon#[27=USB\r\n] 2006.145.14:26:30.99#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.14:26:30.99#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.14:26:30.99#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.14:26:30.99#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.14:26:30.99$vck44/vblo=6,719.99 2006.145.14:26:30.99#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.14:26:30.99#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.14:26:30.99#ibcon#ireg 17 cls_cnt 0 2006.145.14:26:30.99#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.14:26:30.99#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.14:26:30.99#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.14:26:31.01#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.14:26:31.05#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.14:26:31.05#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.14:26:31.05#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.14:26:31.05#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.14:26:31.05$vck44/vb=6,4 2006.145.14:26:31.05#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.14:26:31.05#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.14:26:31.05#ibcon#ireg 11 cls_cnt 2 2006.145.14:26:31.05#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.14:26:31.11#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.14:26:31.11#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.14:26:31.13#ibcon#[27=AT06-04\r\n] 2006.145.14:26:31.16#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.14:26:31.16#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.14:26:31.16#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.14:26:31.16#ibcon#ireg 7 cls_cnt 0 2006.145.14:26:31.16#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.14:26:31.28#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.14:26:31.28#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.14:26:31.30#ibcon#[27=USB\r\n] 2006.145.14:26:31.33#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.14:26:31.33#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.14:26:31.33#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.14:26:31.33#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.14:26:31.33$vck44/vblo=7,734.99 2006.145.14:26:31.33#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.14:26:31.33#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.14:26:31.33#ibcon#ireg 17 cls_cnt 0 2006.145.14:26:31.33#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:26:31.33#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:26:31.33#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:26:31.35#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.14:26:31.39#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:26:31.39#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:26:31.39#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.14:26:31.39#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.14:26:31.39$vck44/vb=7,4 2006.145.14:26:31.39#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.14:26:31.39#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.14:26:31.39#ibcon#ireg 11 cls_cnt 2 2006.145.14:26:31.39#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.14:26:31.45#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.14:26:31.45#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.14:26:31.47#ibcon#[27=AT07-04\r\n] 2006.145.14:26:31.50#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.14:26:31.50#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.14:26:31.50#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.14:26:31.50#ibcon#ireg 7 cls_cnt 0 2006.145.14:26:31.50#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.14:26:31.62#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.14:26:31.62#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.14:26:31.64#ibcon#[27=USB\r\n] 2006.145.14:26:31.67#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.14:26:31.67#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.14:26:31.67#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.14:26:31.67#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.14:26:31.67$vck44/vblo=8,744.99 2006.145.14:26:31.67#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.14:26:31.67#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.14:26:31.67#ibcon#ireg 17 cls_cnt 0 2006.145.14:26:31.67#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.14:26:31.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.14:26:31.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.14:26:31.69#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.14:26:31.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.14:26:31.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.14:26:31.73#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.14:26:31.73#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.14:26:31.73$vck44/vb=8,4 2006.145.14:26:31.73#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.14:26:31.73#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.14:26:31.73#ibcon#ireg 11 cls_cnt 2 2006.145.14:26:31.73#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.14:26:31.79#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.14:26:31.79#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.14:26:31.81#ibcon#[27=AT08-04\r\n] 2006.145.14:26:31.84#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.14:26:31.84#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.14:26:31.84#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.14:26:31.84#ibcon#ireg 7 cls_cnt 0 2006.145.14:26:31.84#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.14:26:31.96#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.14:26:31.96#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.14:26:31.98#ibcon#[27=USB\r\n] 2006.145.14:26:32.01#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.14:26:32.01#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.14:26:32.01#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.14:26:32.01#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.14:26:32.01$vck44/vabw=wide 2006.145.14:26:32.01#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.14:26:32.01#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.14:26:32.01#ibcon#ireg 8 cls_cnt 0 2006.145.14:26:32.01#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:26:32.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:26:32.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:26:32.03#ibcon#[25=BW32\r\n] 2006.145.14:26:32.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:26:32.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:26:32.06#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.14:26:32.06#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.14:26:32.06$vck44/vbbw=wide 2006.145.14:26:32.06#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.14:26:32.06#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.14:26:32.06#ibcon#ireg 8 cls_cnt 0 2006.145.14:26:32.06#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:26:32.13#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:26:32.13#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:26:32.15#ibcon#[27=BW32\r\n] 2006.145.14:26:32.18#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:26:32.18#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:26:32.18#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.14:26:32.18#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.14:26:32.18$setupk4/ifdk4 2006.145.14:26:32.18$ifdk4/lo= 2006.145.14:26:32.18$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.14:26:32.18$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.14:26:32.18$ifdk4/patch= 2006.145.14:26:32.18$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.14:26:32.18$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.14:26:32.18$setupk4/!*+20s 2006.145.14:26:37.55#abcon#<5=/08 0.8 1.4 15.21 871020.7\r\n> 2006.145.14:26:37.57#abcon#{5=INTERFACE CLEAR} 2006.145.14:26:37.63#abcon#[5=S1D000X0/0*\r\n] 2006.145.14:26:46.65$setupk4/"tpicd 2006.145.14:26:46.65$setupk4/echo=off 2006.145.14:26:46.65$setupk4/xlog=off 2006.145.14:26:46.65:!2006.145.14:31:57 2006.145.14:26:58.14#trakl#Source acquired 2006.145.14:26:58.14#flagr#flagr/antenna,acquired 2006.145.14:31:57.00:preob 2006.145.14:31:57.13/onsource/TRACKING 2006.145.14:31:57.13:!2006.145.14:32:07 2006.145.14:32:07.00:"tape 2006.145.14:32:07.00:"st=record 2006.145.14:32:07.00:data_valid=on 2006.145.14:32:07.00:midob 2006.145.14:32:07.13/onsource/TRACKING 2006.145.14:32:07.14/wx/15.25,1020.7,88 2006.145.14:32:07.24/cable/+6.5515E-03 2006.145.14:32:08.33/va/01,08,usb,yes,29,31 2006.145.14:32:08.33/va/02,07,usb,yes,31,32 2006.145.14:32:08.33/va/03,08,usb,yes,28,29 2006.145.14:32:08.33/va/04,07,usb,yes,32,34 2006.145.14:32:08.33/va/05,04,usb,yes,28,28 2006.145.14:32:08.33/va/06,04,usb,yes,31,31 2006.145.14:32:08.33/va/07,04,usb,yes,32,33 2006.145.14:32:08.33/va/08,04,usb,yes,27,32 2006.145.14:32:08.56/valo/01,524.99,yes,locked 2006.145.14:32:08.56/valo/02,534.99,yes,locked 2006.145.14:32:08.56/valo/03,564.99,yes,locked 2006.145.14:32:08.56/valo/04,624.99,yes,locked 2006.145.14:32:08.56/valo/05,734.99,yes,locked 2006.145.14:32:08.56/valo/06,814.99,yes,locked 2006.145.14:32:08.56/valo/07,864.99,yes,locked 2006.145.14:32:08.56/valo/08,884.99,yes,locked 2006.145.14:32:09.65/vb/01,03,usb,yes,36,34 2006.145.14:32:09.65/vb/02,04,usb,yes,32,31 2006.145.14:32:09.65/vb/03,04,usb,yes,28,31 2006.145.14:32:09.65/vb/04,04,usb,yes,33,32 2006.145.14:32:09.65/vb/05,04,usb,yes,25,28 2006.145.14:32:09.65/vb/06,04,usb,yes,30,26 2006.145.14:32:09.65/vb/07,04,usb,yes,29,29 2006.145.14:32:09.65/vb/08,04,usb,yes,27,30 2006.145.14:32:09.89/vblo/01,629.99,yes,locked 2006.145.14:32:09.89/vblo/02,634.99,yes,locked 2006.145.14:32:09.89/vblo/03,649.99,yes,locked 2006.145.14:32:09.89/vblo/04,679.99,yes,locked 2006.145.14:32:09.89/vblo/05,709.99,yes,locked 2006.145.14:32:09.89/vblo/06,719.99,yes,locked 2006.145.14:32:09.89/vblo/07,734.99,yes,locked 2006.145.14:32:09.89/vblo/08,744.99,yes,locked 2006.145.14:32:10.04/vabw/8 2006.145.14:32:10.19/vbbw/8 2006.145.14:32:10.28/xfe/off,on,14.0 2006.145.14:32:10.68/ifatt/23,28,28,28 2006.145.14:32:11.07/fmout-gps/S +4.8E-08 2006.145.14:32:11.12:!2006.145.14:33:47 2006.145.14:33:47.01:data_valid=off 2006.145.14:33:47.02:"et 2006.145.14:33:47.02:!+3s 2006.145.14:33:50.05:"tape 2006.145.14:33:50.06:postob 2006.145.14:33:50.24/cable/+6.5483E-03 2006.145.14:33:50.25/wx/15.24,1020.8,88 2006.145.14:33:50.31/fmout-gps/S +4.8E-08 2006.145.14:33:50.31:scan_name=145-1435,jd0605,40 2006.145.14:33:50.31:source=1424-418,142756.30,-420619.4,2000.0,cw 2006.145.14:33:52.14#flagr#flagr/antenna,new-source 2006.145.14:33:52.15:checkk5 2006.145.14:33:52.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.14:33:53.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.14:33:53.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.14:33:53.92/chk_autoobs//k5ts4/ autoobs is running! 2006.145.14:33:54.35/chk_obsdata//k5ts1/T1451432??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.14:33:54.80/chk_obsdata//k5ts2/T1451432??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.14:33:55.22/chk_obsdata//k5ts3/T1451432??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.14:33:55.67/chk_obsdata//k5ts4/T1451432??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.14:33:56.43/k5log//k5ts1_log_newline 2006.145.14:33:57.18/k5log//k5ts2_log_newline 2006.145.14:33:57.91/k5log//k5ts3_log_newline 2006.145.14:33:58.65/k5log//k5ts4_log_newline 2006.145.14:33:58.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.14:33:58.67:setupk4=1 2006.145.14:33:58.67$setupk4/echo=on 2006.145.14:33:58.67$setupk4/pcalon 2006.145.14:33:58.67$pcalon/"no phase cal control is implemented here 2006.145.14:33:58.67$setupk4/"tpicd=stop 2006.145.14:33:58.67$setupk4/"rec=synch_on 2006.145.14:33:58.67$setupk4/"rec_mode=128 2006.145.14:33:58.68$setupk4/!* 2006.145.14:33:58.68$setupk4/recpk4 2006.145.14:33:58.68$recpk4/recpatch= 2006.145.14:33:58.68$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.14:33:58.68$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.14:33:58.68$setupk4/vck44 2006.145.14:33:58.68$vck44/valo=1,524.99 2006.145.14:33:58.68#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.14:33:58.68#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.14:33:58.68#ibcon#ireg 17 cls_cnt 0 2006.145.14:33:58.68#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.14:33:58.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.14:33:58.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.14:33:58.72#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.14:33:58.76#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.14:33:58.76#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.14:33:58.76#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.14:33:58.76#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.14:33:58.76$vck44/va=1,8 2006.145.14:33:58.76#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.14:33:58.76#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.14:33:58.76#ibcon#ireg 11 cls_cnt 2 2006.145.14:33:58.76#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.14:33:58.76#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.14:33:58.76#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.14:33:58.78#ibcon#[25=AT01-08\r\n] 2006.145.14:33:58.81#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.14:33:58.81#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.14:33:58.81#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.14:33:58.81#ibcon#ireg 7 cls_cnt 0 2006.145.14:33:58.81#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.14:33:58.94#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.14:33:58.94#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.14:33:58.95#ibcon#[25=USB\r\n] 2006.145.14:33:58.98#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.14:33:58.98#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.14:33:58.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.14:33:58.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.14:33:58.98$vck44/valo=2,534.99 2006.145.14:33:58.98#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.14:33:58.98#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.14:33:58.98#ibcon#ireg 17 cls_cnt 0 2006.145.14:33:58.98#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:33:58.98#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:33:58.98#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:33:59.02#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.14:33:59.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:33:59.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:33:59.05#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.14:33:59.05#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.14:33:59.05$vck44/va=2,7 2006.145.14:33:59.05#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.14:33:59.05#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.14:33:59.05#ibcon#ireg 11 cls_cnt 2 2006.145.14:33:59.05#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.14:33:59.10#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.14:33:59.10#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.14:33:59.12#ibcon#[25=AT02-07\r\n] 2006.145.14:33:59.15#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.14:33:59.15#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.14:33:59.15#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.14:33:59.15#ibcon#ireg 7 cls_cnt 0 2006.145.14:33:59.15#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.14:33:59.27#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.14:33:59.27#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.14:33:59.29#ibcon#[25=USB\r\n] 2006.145.14:33:59.32#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.14:33:59.32#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.14:33:59.32#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.14:33:59.32#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.14:33:59.32$vck44/valo=3,564.99 2006.145.14:33:59.32#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.14:33:59.32#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.14:33:59.32#ibcon#ireg 17 cls_cnt 0 2006.145.14:33:59.32#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.14:33:59.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.14:33:59.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.14:33:59.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.14:33:59.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.14:33:59.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.14:33:59.38#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.14:33:59.38#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.14:33:59.38$vck44/va=3,8 2006.145.14:33:59.38#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.14:33:59.38#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.14:33:59.38#ibcon#ireg 11 cls_cnt 2 2006.145.14:33:59.38#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.14:33:59.44#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.14:33:59.44#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.14:33:59.46#ibcon#[25=AT03-08\r\n] 2006.145.14:33:59.49#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.14:33:59.49#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.14:33:59.49#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.14:33:59.49#ibcon#ireg 7 cls_cnt 0 2006.145.14:33:59.49#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.14:33:59.61#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.14:33:59.61#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.14:33:59.63#ibcon#[25=USB\r\n] 2006.145.14:33:59.66#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.14:33:59.66#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.14:33:59.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.14:33:59.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.14:33:59.66$vck44/valo=4,624.99 2006.145.14:33:59.66#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.14:33:59.66#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.14:33:59.66#ibcon#ireg 17 cls_cnt 0 2006.145.14:33:59.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.14:33:59.66#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.14:33:59.66#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.14:33:59.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.14:33:59.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.14:33:59.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.14:33:59.72#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.14:33:59.72#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.14:33:59.72$vck44/va=4,7 2006.145.14:33:59.72#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.14:33:59.72#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.14:33:59.72#ibcon#ireg 11 cls_cnt 2 2006.145.14:33:59.72#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.14:33:59.78#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.14:33:59.78#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.14:33:59.80#ibcon#[25=AT04-07\r\n] 2006.145.14:33:59.83#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.14:33:59.83#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.14:33:59.83#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.14:33:59.83#ibcon#ireg 7 cls_cnt 0 2006.145.14:33:59.83#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.14:33:59.95#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.14:33:59.95#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.14:33:59.97#ibcon#[25=USB\r\n] 2006.145.14:34:00.00#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.14:34:00.00#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.14:34:00.00#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.14:34:00.00#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.14:34:00.00$vck44/valo=5,734.99 2006.145.14:34:00.00#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.14:34:00.00#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.14:34:00.00#ibcon#ireg 17 cls_cnt 0 2006.145.14:34:00.00#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.14:34:00.00#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.14:34:00.00#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.14:34:00.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.14:34:00.06#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.14:34:00.06#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.14:34:00.06#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.14:34:00.06#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.14:34:00.06$vck44/va=5,4 2006.145.14:34:00.06#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.14:34:00.06#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.14:34:00.06#ibcon#ireg 11 cls_cnt 2 2006.145.14:34:00.06#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.14:34:00.12#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.14:34:00.12#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.14:34:00.14#ibcon#[25=AT05-04\r\n] 2006.145.14:34:00.17#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.14:34:00.17#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.14:34:00.17#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.14:34:00.17#ibcon#ireg 7 cls_cnt 0 2006.145.14:34:00.17#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.14:34:00.29#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.14:34:00.29#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.14:34:00.31#ibcon#[25=USB\r\n] 2006.145.14:34:00.34#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.14:34:00.34#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.14:34:00.34#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.14:34:00.34#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.14:34:00.34$vck44/valo=6,814.99 2006.145.14:34:00.34#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.14:34:00.34#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.14:34:00.34#ibcon#ireg 17 cls_cnt 0 2006.145.14:34:00.34#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.14:34:00.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.14:34:00.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.14:34:00.36#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.14:34:00.40#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.14:34:00.40#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.14:34:00.40#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.14:34:00.40#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.14:34:00.40$vck44/va=6,4 2006.145.14:34:00.40#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.14:34:00.40#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.14:34:00.40#ibcon#ireg 11 cls_cnt 2 2006.145.14:34:00.40#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.14:34:00.46#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.14:34:00.46#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.14:34:00.48#ibcon#[25=AT06-04\r\n] 2006.145.14:34:00.51#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.14:34:00.51#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.14:34:00.51#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.14:34:00.51#ibcon#ireg 7 cls_cnt 0 2006.145.14:34:00.51#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.14:34:00.63#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.14:34:00.63#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.14:34:00.65#ibcon#[25=USB\r\n] 2006.145.14:34:00.68#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.14:34:00.68#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.14:34:00.68#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.14:34:00.68#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.14:34:00.68$vck44/valo=7,864.99 2006.145.14:34:00.68#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.14:34:00.68#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.14:34:00.68#ibcon#ireg 17 cls_cnt 0 2006.145.14:34:00.68#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.14:34:00.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.14:34:00.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.14:34:00.70#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.14:34:00.74#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.14:34:00.74#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.14:34:00.74#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.14:34:00.74#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.14:34:00.74$vck44/va=7,4 2006.145.14:34:00.74#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.14:34:00.74#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.14:34:00.74#ibcon#ireg 11 cls_cnt 2 2006.145.14:34:00.74#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.14:34:00.80#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.14:34:00.80#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.14:34:00.82#ibcon#[25=AT07-04\r\n] 2006.145.14:34:00.85#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.14:34:00.85#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.14:34:00.85#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.14:34:00.85#ibcon#ireg 7 cls_cnt 0 2006.145.14:34:00.85#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.14:34:00.97#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.14:34:00.97#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.14:34:00.99#ibcon#[25=USB\r\n] 2006.145.14:34:01.02#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.14:34:01.02#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.14:34:01.02#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.14:34:01.02#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.14:34:01.02$vck44/valo=8,884.99 2006.145.14:34:01.02#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.14:34:01.02#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.14:34:01.02#ibcon#ireg 17 cls_cnt 0 2006.145.14:34:01.02#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.14:34:01.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.14:34:01.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.14:34:01.04#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.14:34:01.08#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.14:34:01.08#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.14:34:01.08#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.14:34:01.08#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.14:34:01.08$vck44/va=8,4 2006.145.14:34:01.08#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.14:34:01.08#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.14:34:01.08#ibcon#ireg 11 cls_cnt 2 2006.145.14:34:01.08#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.14:34:01.14#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.14:34:01.14#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.14:34:01.16#ibcon#[25=AT08-04\r\n] 2006.145.14:34:01.19#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.14:34:01.19#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.14:34:01.19#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.14:34:01.19#ibcon#ireg 7 cls_cnt 0 2006.145.14:34:01.19#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.14:34:01.31#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.14:34:01.31#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.14:34:01.34#ibcon#[25=USB\r\n] 2006.145.14:34:01.36#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.14:34:01.36#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.14:34:01.36#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.14:34:01.36#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.14:34:01.36$vck44/vblo=1,629.99 2006.145.14:34:01.36#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.14:34:01.36#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.14:34:01.36#ibcon#ireg 17 cls_cnt 0 2006.145.14:34:01.36#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.14:34:01.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.14:34:01.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.14:34:01.38#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.14:34:01.43#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.14:34:01.43#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.14:34:01.43#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.14:34:01.43#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.14:34:01.43$vck44/vb=1,3 2006.145.14:34:01.43#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.14:34:01.43#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.14:34:01.43#ibcon#ireg 11 cls_cnt 2 2006.145.14:34:01.43#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.14:34:01.43#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.14:34:01.43#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.14:34:01.45#ibcon#[27=AT01-03\r\n] 2006.145.14:34:01.48#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.14:34:01.48#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.14:34:01.48#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.14:34:01.48#ibcon#ireg 7 cls_cnt 0 2006.145.14:34:01.48#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.14:34:01.60#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.14:34:01.60#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.14:34:01.62#ibcon#[27=USB\r\n] 2006.145.14:34:01.65#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.14:34:01.65#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.14:34:01.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.14:34:01.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.14:34:01.65$vck44/vblo=2,634.99 2006.145.14:34:01.65#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.14:34:01.65#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.14:34:01.65#ibcon#ireg 17 cls_cnt 0 2006.145.14:34:01.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.14:34:01.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.14:34:01.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.14:34:01.67#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.14:34:01.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.14:34:01.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.14:34:01.71#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.14:34:01.71#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.14:34:01.71$vck44/vb=2,4 2006.145.14:34:01.71#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.14:34:01.71#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.14:34:01.71#ibcon#ireg 11 cls_cnt 2 2006.145.14:34:01.71#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.14:34:01.77#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.14:34:01.77#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.14:34:01.79#ibcon#[27=AT02-04\r\n] 2006.145.14:34:01.82#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.14:34:01.82#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.14:34:01.82#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.14:34:01.82#ibcon#ireg 7 cls_cnt 0 2006.145.14:34:01.82#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.14:34:01.94#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.14:34:01.94#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.14:34:01.96#ibcon#[27=USB\r\n] 2006.145.14:34:01.99#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.14:34:01.99#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.14:34:01.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.14:34:01.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.14:34:01.99$vck44/vblo=3,649.99 2006.145.14:34:01.99#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.14:34:01.99#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.14:34:01.99#ibcon#ireg 17 cls_cnt 0 2006.145.14:34:01.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:34:01.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:34:01.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:34:02.01#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.14:34:02.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:34:02.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:34:02.05#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.14:34:02.05#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.14:34:02.05$vck44/vb=3,4 2006.145.14:34:02.05#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.14:34:02.05#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.14:34:02.05#ibcon#ireg 11 cls_cnt 2 2006.145.14:34:02.05#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.14:34:02.11#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.14:34:02.11#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.14:34:02.13#ibcon#[27=AT03-04\r\n] 2006.145.14:34:02.16#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.14:34:02.16#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.14:34:02.16#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.14:34:02.16#ibcon#ireg 7 cls_cnt 0 2006.145.14:34:02.16#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.14:34:02.28#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.14:34:02.28#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.14:34:02.30#ibcon#[27=USB\r\n] 2006.145.14:34:02.33#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.14:34:02.33#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.14:34:02.33#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.14:34:02.33#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.14:34:02.33$vck44/vblo=4,679.99 2006.145.14:34:02.33#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.14:34:02.33#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.14:34:02.33#ibcon#ireg 17 cls_cnt 0 2006.145.14:34:02.33#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.14:34:02.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.14:34:02.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.14:34:02.35#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.14:34:02.39#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.14:34:02.39#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.14:34:02.39#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.14:34:02.39#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.14:34:02.39$vck44/vb=4,4 2006.145.14:34:02.39#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.14:34:02.39#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.14:34:02.39#ibcon#ireg 11 cls_cnt 2 2006.145.14:34:02.39#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.14:34:02.45#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.14:34:02.45#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.14:34:02.47#ibcon#[27=AT04-04\r\n] 2006.145.14:34:02.50#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.14:34:02.50#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.14:34:02.50#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.14:34:02.50#ibcon#ireg 7 cls_cnt 0 2006.145.14:34:02.50#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.14:34:02.62#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.14:34:02.62#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.14:34:02.64#ibcon#[27=USB\r\n] 2006.145.14:34:02.67#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.14:34:02.67#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.14:34:02.67#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.14:34:02.67#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.14:34:02.67$vck44/vblo=5,709.99 2006.145.14:34:02.67#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.14:34:02.67#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.14:34:02.67#ibcon#ireg 17 cls_cnt 0 2006.145.14:34:02.67#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.14:34:02.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.14:34:02.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.14:34:02.69#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.14:34:02.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.14:34:02.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.14:34:02.73#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.14:34:02.73#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.14:34:02.73$vck44/vb=5,4 2006.145.14:34:02.73#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.14:34:02.73#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.14:34:02.73#ibcon#ireg 11 cls_cnt 2 2006.145.14:34:02.73#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.14:34:02.79#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.14:34:02.79#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.14:34:02.81#ibcon#[27=AT05-04\r\n] 2006.145.14:34:02.84#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.14:34:02.84#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.14:34:02.84#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.14:34:02.84#ibcon#ireg 7 cls_cnt 0 2006.145.14:34:02.84#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.14:34:02.96#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.14:34:02.96#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.14:34:02.98#ibcon#[27=USB\r\n] 2006.145.14:34:03.01#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.14:34:03.01#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.14:34:03.01#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.14:34:03.01#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.14:34:03.01$vck44/vblo=6,719.99 2006.145.14:34:03.01#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.14:34:03.01#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.14:34:03.01#ibcon#ireg 17 cls_cnt 0 2006.145.14:34:03.01#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.14:34:03.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.14:34:03.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.14:34:03.03#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.14:34:03.07#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.14:34:03.07#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.14:34:03.07#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.14:34:03.07#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.14:34:03.07$vck44/vb=6,4 2006.145.14:34:03.07#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.14:34:03.07#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.14:34:03.07#ibcon#ireg 11 cls_cnt 2 2006.145.14:34:03.07#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.14:34:03.13#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.14:34:03.13#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.14:34:03.15#ibcon#[27=AT06-04\r\n] 2006.145.14:34:03.18#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.14:34:03.18#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.14:34:03.18#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.14:34:03.18#ibcon#ireg 7 cls_cnt 0 2006.145.14:34:03.18#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.14:34:03.30#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.14:34:03.30#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.14:34:03.32#ibcon#[27=USB\r\n] 2006.145.14:34:03.35#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.14:34:03.35#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.14:34:03.35#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.14:34:03.35#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.14:34:03.35$vck44/vblo=7,734.99 2006.145.14:34:03.35#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.14:34:03.35#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.14:34:03.35#ibcon#ireg 17 cls_cnt 0 2006.145.14:34:03.35#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.14:34:03.35#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.14:34:03.35#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.14:34:03.37#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.14:34:03.41#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.14:34:03.41#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.14:34:03.41#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.14:34:03.41#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.14:34:03.41$vck44/vb=7,4 2006.145.14:34:03.41#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.14:34:03.41#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.14:34:03.41#ibcon#ireg 11 cls_cnt 2 2006.145.14:34:03.41#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.14:34:03.47#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.14:34:03.47#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.14:34:03.49#ibcon#[27=AT07-04\r\n] 2006.145.14:34:03.52#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.14:34:03.52#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.14:34:03.52#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.14:34:03.52#ibcon#ireg 7 cls_cnt 0 2006.145.14:34:03.52#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.14:34:03.64#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.14:34:03.64#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.14:34:03.66#ibcon#[27=USB\r\n] 2006.145.14:34:03.69#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.14:34:03.69#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.14:34:03.69#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.14:34:03.69#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.14:34:03.69$vck44/vblo=8,744.99 2006.145.14:34:03.69#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.14:34:03.69#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.14:34:03.69#ibcon#ireg 17 cls_cnt 0 2006.145.14:34:03.69#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.14:34:03.69#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.14:34:03.69#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.14:34:03.71#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.14:34:03.75#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.14:34:03.75#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.14:34:03.75#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.14:34:03.75#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.14:34:03.75$vck44/vb=8,4 2006.145.14:34:03.75#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.14:34:03.75#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.14:34:03.75#ibcon#ireg 11 cls_cnt 2 2006.145.14:34:03.75#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.14:34:03.81#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.14:34:03.81#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.14:34:03.83#ibcon#[27=AT08-04\r\n] 2006.145.14:34:03.86#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.14:34:03.86#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.14:34:03.86#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.14:34:03.86#ibcon#ireg 7 cls_cnt 0 2006.145.14:34:03.86#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.14:34:03.98#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.14:34:03.98#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.14:34:04.00#ibcon#[27=USB\r\n] 2006.145.14:34:04.03#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.14:34:04.03#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.14:34:04.03#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.14:34:04.03#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.14:34:04.03$vck44/vabw=wide 2006.145.14:34:04.03#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.14:34:04.03#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.14:34:04.03#ibcon#ireg 8 cls_cnt 0 2006.145.14:34:04.03#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.14:34:04.03#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.14:34:04.03#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.14:34:04.05#ibcon#[25=BW32\r\n] 2006.145.14:34:04.08#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.14:34:04.08#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.14:34:04.08#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.14:34:04.08#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.14:34:04.08$vck44/vbbw=wide 2006.145.14:34:04.08#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.14:34:04.08#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.14:34:04.08#ibcon#ireg 8 cls_cnt 0 2006.145.14:34:04.08#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:34:04.15#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:34:04.15#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:34:04.17#ibcon#[27=BW32\r\n] 2006.145.14:34:04.20#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:34:04.20#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:34:04.20#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.14:34:04.20#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.14:34:04.20$setupk4/ifdk4 2006.145.14:34:04.20$ifdk4/lo= 2006.145.14:34:04.20$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.14:34:04.20$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.14:34:04.20$ifdk4/patch= 2006.145.14:34:04.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.14:34:04.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.14:34:04.20$setupk4/!*+20s 2006.145.14:34:07.94#abcon#<5=/08 0.8 1.8 15.24 881020.8\r\n> 2006.145.14:34:07.96#abcon#{5=INTERFACE CLEAR} 2006.145.14:34:08.02#abcon#[5=S1D000X0/0*\r\n] 2006.145.14:34:11.14#trakl#Source acquired 2006.145.14:34:11.14#flagr#flagr/antenna,acquired 2006.145.14:34:18.11#abcon#<5=/08 0.8 1.8 15.24 881020.8\r\n> 2006.145.14:34:18.13#abcon#{5=INTERFACE CLEAR} 2006.145.14:34:18.19#abcon#[5=S1D000X0/0*\r\n] 2006.145.14:34:18.69$setupk4/"tpicd 2006.145.14:34:18.69$setupk4/echo=off 2006.145.14:34:18.69$setupk4/xlog=off 2006.145.14:34:18.69:!2006.145.14:35:13 2006.145.14:35:13.00:preob 2006.145.14:35:13.14/onsource/TRACKING 2006.145.14:35:13.14:!2006.145.14:35:23 2006.145.14:35:23.00:"tape 2006.145.14:35:23.00:"st=record 2006.145.14:35:23.00:data_valid=on 2006.145.14:35:23.00:midob 2006.145.14:35:23.14/onsource/TRACKING 2006.145.14:35:23.14/wx/15.23,1020.8,88 2006.145.14:35:23.31/cable/+6.5514E-03 2006.145.14:35:24.40/va/01,08,usb,yes,35,37 2006.145.14:35:24.40/va/02,07,usb,yes,37,38 2006.145.14:35:24.40/va/03,08,usb,yes,34,35 2006.145.14:35:24.40/va/04,07,usb,yes,38,40 2006.145.14:35:24.40/va/05,04,usb,yes,33,34 2006.145.14:35:24.40/va/06,04,usb,yes,37,37 2006.145.14:35:24.40/va/07,04,usb,yes,38,39 2006.145.14:35:24.40/va/08,04,usb,yes,32,39 2006.145.14:35:24.63/valo/01,524.99,yes,locked 2006.145.14:35:24.63/valo/02,534.99,yes,locked 2006.145.14:35:24.63/valo/03,564.99,yes,locked 2006.145.14:35:24.63/valo/04,624.99,yes,locked 2006.145.14:35:24.63/valo/05,734.99,yes,locked 2006.145.14:35:24.63/valo/06,814.99,yes,locked 2006.145.14:35:24.63/valo/07,864.99,yes,locked 2006.145.14:35:24.63/valo/08,884.99,yes,locked 2006.145.14:35:25.72/vb/01,03,usb,yes,40,37 2006.145.14:35:25.72/vb/02,04,usb,yes,35,35 2006.145.14:35:25.72/vb/03,04,usb,yes,32,35 2006.145.14:35:25.72/vb/04,04,usb,yes,36,35 2006.145.14:35:25.72/vb/05,04,usb,yes,31,32 2006.145.14:35:25.72/vb/06,04,usb,yes,33,32 2006.145.14:35:25.72/vb/07,04,usb,yes,33,34 2006.145.14:35:25.72/vb/08,04,usb,yes,30,34 2006.145.14:35:25.96/vblo/01,629.99,yes,locked 2006.145.14:35:25.96/vblo/02,634.99,yes,locked 2006.145.14:35:25.96/vblo/03,649.99,yes,locked 2006.145.14:35:25.96/vblo/04,679.99,yes,locked 2006.145.14:35:25.96/vblo/05,709.99,yes,locked 2006.145.14:35:25.96/vblo/06,719.99,yes,locked 2006.145.14:35:25.96/vblo/07,734.99,yes,locked 2006.145.14:35:25.96/vblo/08,744.99,yes,locked 2006.145.14:35:26.11/vabw/8 2006.145.14:35:26.26/vbbw/8 2006.145.14:35:26.35/xfe/off,on,15.5 2006.145.14:35:26.74/ifatt/23,28,28,28 2006.145.14:35:27.07/fmout-gps/S +4.7E-08 2006.145.14:35:27.11:!2006.145.14:36:03 2006.145.14:36:03.01:data_valid=off 2006.145.14:36:03.02:"et 2006.145.14:36:03.02:!+3s 2006.145.14:36:06.04:"tape 2006.145.14:36:06.05:postob 2006.145.14:36:06.16/cable/+6.5492E-03 2006.145.14:36:06.17/wx/15.23,1020.8,88 2006.145.14:36:06.22/fmout-gps/S +4.8E-08 2006.145.14:36:06.22:scan_name=145-1440,jd0605,40 2006.145.14:36:06.22:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.145.14:36:08.14#flagr#flagr/antenna,new-source 2006.145.14:36:08.14:checkk5 2006.145.14:36:08.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.14:36:09.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.14:36:09.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.14:36:09.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.14:36:10.33/chk_obsdata//k5ts1/T1451435??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.14:36:10.77/chk_obsdata//k5ts2/T1451435??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.14:36:11.21/chk_obsdata//k5ts3/T1451435??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.14:36:11.62/chk_obsdata//k5ts4/T1451435??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.14:36:12.38/k5log//k5ts1_log_newline 2006.145.14:36:13.13/k5log//k5ts2_log_newline 2006.145.14:36:13.87/k5log//k5ts3_log_newline 2006.145.14:36:14.61/k5log//k5ts4_log_newline 2006.145.14:36:14.64/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.14:36:14.64:setupk4=1 2006.145.14:36:14.64$setupk4/echo=on 2006.145.14:36:14.64$setupk4/pcalon 2006.145.14:36:14.64$pcalon/"no phase cal control is implemented here 2006.145.14:36:14.64$setupk4/"tpicd=stop 2006.145.14:36:14.64$setupk4/"rec=synch_on 2006.145.14:36:14.64$setupk4/"rec_mode=128 2006.145.14:36:14.64$setupk4/!* 2006.145.14:36:14.64$setupk4/recpk4 2006.145.14:36:14.64$recpk4/recpatch= 2006.145.14:36:14.64$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.14:36:14.64$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.14:36:14.64$setupk4/vck44 2006.145.14:36:14.64$vck44/valo=1,524.99 2006.145.14:36:14.64#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.14:36:14.64#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.14:36:14.64#ibcon#ireg 17 cls_cnt 0 2006.145.14:36:14.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:36:14.64#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:36:14.64#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:36:14.65#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.14:36:14.70#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:36:14.70#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:36:14.70#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.14:36:14.70#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.14:36:14.70$vck44/va=1,8 2006.145.14:36:14.70#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.14:36:14.70#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.14:36:14.70#ibcon#ireg 11 cls_cnt 2 2006.145.14:36:14.70#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:36:14.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:36:14.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:36:14.72#ibcon#[25=AT01-08\r\n] 2006.145.14:36:14.75#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:36:14.75#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:36:14.75#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.14:36:14.75#ibcon#ireg 7 cls_cnt 0 2006.145.14:36:14.75#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:36:14.87#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:36:14.87#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:36:14.89#ibcon#[25=USB\r\n] 2006.145.14:36:14.92#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:36:14.92#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:36:14.92#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.14:36:14.92#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.14:36:14.92$vck44/valo=2,534.99 2006.145.14:36:14.92#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.14:36:14.92#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.14:36:14.92#ibcon#ireg 17 cls_cnt 0 2006.145.14:36:14.92#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:36:14.92#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:36:14.92#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:36:14.96#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.14:36:14.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:36:14.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:36:14.99#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.14:36:14.99#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.14:36:14.99$vck44/va=2,7 2006.145.14:36:14.99#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.14:36:14.99#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.14:36:14.99#ibcon#ireg 11 cls_cnt 2 2006.145.14:36:14.99#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:36:15.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:36:15.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:36:15.06#ibcon#[25=AT02-07\r\n] 2006.145.14:36:15.09#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:36:15.09#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:36:15.09#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.14:36:15.09#ibcon#ireg 7 cls_cnt 0 2006.145.14:36:15.09#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:36:15.21#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:36:15.21#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:36:15.23#ibcon#[25=USB\r\n] 2006.145.14:36:15.26#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:36:15.26#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:36:15.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.14:36:15.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.14:36:15.26$vck44/valo=3,564.99 2006.145.14:36:15.26#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.14:36:15.26#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.14:36:15.26#ibcon#ireg 17 cls_cnt 0 2006.145.14:36:15.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:36:15.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:36:15.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:36:15.28#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.14:36:15.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:36:15.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:36:15.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.14:36:15.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.14:36:15.32$vck44/va=3,8 2006.145.14:36:15.32#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.14:36:15.32#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.14:36:15.32#ibcon#ireg 11 cls_cnt 2 2006.145.14:36:15.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.14:36:15.38#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.14:36:15.38#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.14:36:15.40#ibcon#[25=AT03-08\r\n] 2006.145.14:36:15.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.14:36:15.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.14:36:15.43#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.14:36:15.43#ibcon#ireg 7 cls_cnt 0 2006.145.14:36:15.43#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.14:36:15.55#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.14:36:15.55#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.14:36:15.57#ibcon#[25=USB\r\n] 2006.145.14:36:15.60#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.14:36:15.60#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.14:36:15.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.14:36:15.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.14:36:15.60$vck44/valo=4,624.99 2006.145.14:36:15.60#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.14:36:15.60#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.14:36:15.60#ibcon#ireg 17 cls_cnt 0 2006.145.14:36:15.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:36:15.60#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:36:15.60#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:36:15.62#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.14:36:15.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:36:15.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:36:15.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.14:36:15.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.14:36:15.66$vck44/va=4,7 2006.145.14:36:15.66#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.14:36:15.66#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.14:36:15.66#ibcon#ireg 11 cls_cnt 2 2006.145.14:36:15.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:36:15.72#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:36:15.72#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:36:15.74#ibcon#[25=AT04-07\r\n] 2006.145.14:36:15.77#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:36:15.77#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:36:15.77#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.14:36:15.77#ibcon#ireg 7 cls_cnt 0 2006.145.14:36:15.77#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:36:15.89#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:36:15.89#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:36:15.91#ibcon#[25=USB\r\n] 2006.145.14:36:15.94#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:36:15.94#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:36:15.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.14:36:15.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.14:36:15.94$vck44/valo=5,734.99 2006.145.14:36:15.94#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.14:36:15.94#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.14:36:15.94#ibcon#ireg 17 cls_cnt 0 2006.145.14:36:15.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:36:15.94#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:36:15.94#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:36:15.96#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.14:36:16.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:36:16.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:36:16.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.14:36:16.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.14:36:16.00$vck44/va=5,4 2006.145.14:36:16.00#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.14:36:16.00#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.14:36:16.00#ibcon#ireg 11 cls_cnt 2 2006.145.14:36:16.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:36:16.06#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:36:16.06#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:36:16.08#ibcon#[25=AT05-04\r\n] 2006.145.14:36:16.11#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:36:16.11#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:36:16.11#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.14:36:16.11#ibcon#ireg 7 cls_cnt 0 2006.145.14:36:16.11#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:36:16.23#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:36:16.23#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:36:16.25#ibcon#[25=USB\r\n] 2006.145.14:36:16.28#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:36:16.28#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:36:16.28#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.14:36:16.28#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.14:36:16.28$vck44/valo=6,814.99 2006.145.14:36:16.28#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.14:36:16.28#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.14:36:16.28#ibcon#ireg 17 cls_cnt 0 2006.145.14:36:16.28#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:36:16.28#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:36:16.28#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:36:16.31#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.14:36:16.35#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:36:16.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:36:16.35#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.14:36:16.35#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.14:36:16.35$vck44/va=6,4 2006.145.14:36:16.35#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.14:36:16.35#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.14:36:16.35#ibcon#ireg 11 cls_cnt 2 2006.145.14:36:16.35#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:36:16.40#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:36:16.40#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:36:16.42#ibcon#[25=AT06-04\r\n] 2006.145.14:36:16.45#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:36:16.45#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:36:16.45#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.14:36:16.45#ibcon#ireg 7 cls_cnt 0 2006.145.14:36:16.45#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:36:16.57#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:36:16.57#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:36:16.59#ibcon#[25=USB\r\n] 2006.145.14:36:16.62#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:36:16.62#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:36:16.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.14:36:16.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.14:36:16.62$vck44/valo=7,864.99 2006.145.14:36:16.62#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.14:36:16.62#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.14:36:16.62#ibcon#ireg 17 cls_cnt 0 2006.145.14:36:16.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.14:36:16.62#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.14:36:16.62#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.14:36:16.64#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.14:36:16.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.14:36:16.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.14:36:16.68#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.14:36:16.68#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.14:36:16.68$vck44/va=7,4 2006.145.14:36:16.68#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.14:36:16.68#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.14:36:16.68#ibcon#ireg 11 cls_cnt 2 2006.145.14:36:16.68#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.14:36:16.74#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.14:36:16.74#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.14:36:16.76#ibcon#[25=AT07-04\r\n] 2006.145.14:36:16.79#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.14:36:16.79#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.14:36:16.79#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.14:36:16.79#ibcon#ireg 7 cls_cnt 0 2006.145.14:36:16.79#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.14:36:16.91#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.14:36:16.91#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.14:36:16.93#ibcon#[25=USB\r\n] 2006.145.14:36:16.96#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.14:36:16.96#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.14:36:16.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.14:36:16.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.14:36:16.96$vck44/valo=8,884.99 2006.145.14:36:16.96#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.14:36:16.96#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.14:36:16.96#ibcon#ireg 17 cls_cnt 0 2006.145.14:36:16.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.14:36:16.96#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.14:36:16.96#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.14:36:16.98#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.14:36:17.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.14:36:17.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.14:36:17.02#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.14:36:17.02#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.14:36:17.02$vck44/va=8,4 2006.145.14:36:17.02#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.14:36:17.02#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.14:36:17.02#ibcon#ireg 11 cls_cnt 2 2006.145.14:36:17.02#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.14:36:17.08#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.14:36:17.08#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.14:36:17.10#ibcon#[25=AT08-04\r\n] 2006.145.14:36:17.13#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.14:36:17.13#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.14:36:17.13#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.14:36:17.13#ibcon#ireg 7 cls_cnt 0 2006.145.14:36:17.13#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.14:36:17.25#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.14:36:17.25#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.14:36:17.27#ibcon#[25=USB\r\n] 2006.145.14:36:17.30#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.14:36:17.30#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.14:36:17.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.14:36:17.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.14:36:17.30$vck44/vblo=1,629.99 2006.145.14:36:17.30#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.14:36:17.30#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.14:36:17.30#ibcon#ireg 17 cls_cnt 0 2006.145.14:36:17.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.14:36:17.30#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.14:36:17.30#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.14:36:17.32#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.14:36:17.36#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.14:36:17.36#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.14:36:17.36#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.14:36:17.36#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.14:36:17.36$vck44/vb=1,3 2006.145.14:36:17.36#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.14:36:17.36#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.14:36:17.36#ibcon#ireg 11 cls_cnt 2 2006.145.14:36:17.36#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.14:36:17.36#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.14:36:17.36#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.14:36:17.38#ibcon#[27=AT01-03\r\n] 2006.145.14:36:17.41#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.14:36:17.41#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.14:36:17.41#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.14:36:17.41#ibcon#ireg 7 cls_cnt 0 2006.145.14:36:17.41#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.14:36:17.53#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.14:36:17.53#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.14:36:17.55#ibcon#[27=USB\r\n] 2006.145.14:36:17.58#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.14:36:17.58#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.14:36:17.58#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.14:36:17.58#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.14:36:17.58$vck44/vblo=2,634.99 2006.145.14:36:17.58#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.14:36:17.58#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.14:36:17.58#ibcon#ireg 17 cls_cnt 0 2006.145.14:36:17.58#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:36:17.58#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:36:17.58#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:36:17.60#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.14:36:17.64#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:36:17.64#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:36:17.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.14:36:17.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.14:36:17.64$vck44/vb=2,4 2006.145.14:36:17.64#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.14:36:17.64#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.14:36:17.64#ibcon#ireg 11 cls_cnt 2 2006.145.14:36:17.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:36:17.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:36:17.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:36:17.72#ibcon#[27=AT02-04\r\n] 2006.145.14:36:17.75#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:36:17.75#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:36:17.75#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.14:36:17.75#ibcon#ireg 7 cls_cnt 0 2006.145.14:36:17.75#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:36:17.87#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:36:17.87#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:36:17.89#ibcon#[27=USB\r\n] 2006.145.14:36:17.92#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:36:17.92#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:36:17.92#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.14:36:17.92#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.14:36:17.92$vck44/vblo=3,649.99 2006.145.14:36:17.92#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.14:36:17.92#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.14:36:17.92#ibcon#ireg 17 cls_cnt 0 2006.145.14:36:17.92#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:36:17.92#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:36:17.92#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:36:17.94#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.14:36:17.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:36:17.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:36:17.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.14:36:17.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.14:36:17.98$vck44/vb=3,4 2006.145.14:36:17.98#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.14:36:17.98#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.14:36:17.98#ibcon#ireg 11 cls_cnt 2 2006.145.14:36:17.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:36:18.04#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:36:18.04#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:36:18.06#ibcon#[27=AT03-04\r\n] 2006.145.14:36:18.09#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:36:18.09#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:36:18.09#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.14:36:18.09#ibcon#ireg 7 cls_cnt 0 2006.145.14:36:18.09#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:36:18.21#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:36:18.21#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:36:18.23#ibcon#[27=USB\r\n] 2006.145.14:36:18.26#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:36:18.26#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:36:18.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.14:36:18.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.14:36:18.26$vck44/vblo=4,679.99 2006.145.14:36:18.26#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.14:36:18.26#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.14:36:18.26#ibcon#ireg 17 cls_cnt 0 2006.145.14:36:18.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:36:18.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:36:18.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:36:18.28#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.14:36:18.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:36:18.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:36:18.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.14:36:18.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.14:36:18.32$vck44/vb=4,4 2006.145.14:36:18.32#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.14:36:18.32#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.14:36:18.32#ibcon#ireg 11 cls_cnt 2 2006.145.14:36:18.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.14:36:18.38#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.14:36:18.38#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.14:36:18.40#ibcon#[27=AT04-04\r\n] 2006.145.14:36:18.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.14:36:18.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.14:36:18.43#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.14:36:18.43#ibcon#ireg 7 cls_cnt 0 2006.145.14:36:18.43#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.14:36:18.55#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.14:36:18.55#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.14:36:18.57#ibcon#[27=USB\r\n] 2006.145.14:36:18.60#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.14:36:18.60#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.14:36:18.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.14:36:18.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.14:36:18.60$vck44/vblo=5,709.99 2006.145.14:36:18.60#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.14:36:18.60#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.14:36:18.60#ibcon#ireg 17 cls_cnt 0 2006.145.14:36:18.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:36:18.60#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:36:18.60#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:36:18.62#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.14:36:18.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:36:18.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:36:18.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.14:36:18.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.14:36:18.66$vck44/vb=5,4 2006.145.14:36:18.66#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.14:36:18.66#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.14:36:18.66#ibcon#ireg 11 cls_cnt 2 2006.145.14:36:18.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:36:18.72#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:36:18.72#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:36:18.74#ibcon#[27=AT05-04\r\n] 2006.145.14:36:18.77#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:36:18.77#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:36:18.77#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.14:36:18.77#ibcon#ireg 7 cls_cnt 0 2006.145.14:36:18.77#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:36:18.89#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:36:18.89#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:36:18.91#ibcon#[27=USB\r\n] 2006.145.14:36:18.94#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:36:18.94#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:36:18.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.14:36:18.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.14:36:18.94$vck44/vblo=6,719.99 2006.145.14:36:18.94#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.14:36:18.94#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.14:36:18.94#ibcon#ireg 17 cls_cnt 0 2006.145.14:36:18.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:36:18.94#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:36:18.94#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:36:18.96#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.14:36:19.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:36:19.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:36:19.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.14:36:19.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.14:36:19.00$vck44/vb=6,4 2006.145.14:36:19.00#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.14:36:19.00#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.14:36:19.00#ibcon#ireg 11 cls_cnt 2 2006.145.14:36:19.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:36:19.06#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:36:19.06#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:36:19.08#ibcon#[27=AT06-04\r\n] 2006.145.14:36:19.11#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:36:19.11#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:36:19.11#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.14:36:19.11#ibcon#ireg 7 cls_cnt 0 2006.145.14:36:19.11#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:36:19.23#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:36:19.23#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:36:19.25#ibcon#[27=USB\r\n] 2006.145.14:36:19.28#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:36:19.28#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:36:19.28#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.14:36:19.28#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.14:36:19.28$vck44/vblo=7,734.99 2006.145.14:36:19.28#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.14:36:19.28#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.14:36:19.28#ibcon#ireg 17 cls_cnt 0 2006.145.14:36:19.28#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:36:19.28#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:36:19.28#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:36:19.30#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.14:36:19.34#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:36:19.34#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:36:19.34#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.14:36:19.34#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.14:36:19.34$vck44/vb=7,4 2006.145.14:36:19.34#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.14:36:19.34#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.14:36:19.34#ibcon#ireg 11 cls_cnt 2 2006.145.14:36:19.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:36:19.40#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:36:19.40#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:36:19.42#ibcon#[27=AT07-04\r\n] 2006.145.14:36:19.45#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:36:19.45#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:36:19.45#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.14:36:19.45#ibcon#ireg 7 cls_cnt 0 2006.145.14:36:19.45#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:36:19.57#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:36:19.57#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:36:19.59#ibcon#[27=USB\r\n] 2006.145.14:36:19.62#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:36:19.62#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:36:19.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.14:36:19.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.14:36:19.62$vck44/vblo=8,744.99 2006.145.14:36:19.62#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.14:36:19.62#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.14:36:19.62#ibcon#ireg 17 cls_cnt 0 2006.145.14:36:19.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.14:36:19.62#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.14:36:19.62#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.14:36:19.64#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.14:36:19.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.14:36:19.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.14:36:19.68#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.14:36:19.68#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.14:36:19.68$vck44/vb=8,4 2006.145.14:36:19.68#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.14:36:19.68#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.14:36:19.68#ibcon#ireg 11 cls_cnt 2 2006.145.14:36:19.68#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.14:36:19.74#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.14:36:19.74#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.14:36:19.76#ibcon#[27=AT08-04\r\n] 2006.145.14:36:19.79#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.14:36:19.79#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.14:36:19.79#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.14:36:19.79#ibcon#ireg 7 cls_cnt 0 2006.145.14:36:19.79#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.14:36:19.91#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.14:36:19.91#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.14:36:19.93#ibcon#[27=USB\r\n] 2006.145.14:36:19.96#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.14:36:19.96#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.14:36:19.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.14:36:19.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.14:36:19.96$vck44/vabw=wide 2006.145.14:36:19.96#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.14:36:19.96#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.14:36:19.96#ibcon#ireg 8 cls_cnt 0 2006.145.14:36:19.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.14:36:19.96#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.14:36:19.96#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.14:36:19.98#ibcon#[25=BW32\r\n] 2006.145.14:36:20.01#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.14:36:20.01#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.14:36:20.01#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.14:36:20.01#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.14:36:20.01$vck44/vbbw=wide 2006.145.14:36:20.01#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.14:36:20.01#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.14:36:20.01#ibcon#ireg 8 cls_cnt 0 2006.145.14:36:20.01#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.14:36:20.08#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.14:36:20.08#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.14:36:20.10#ibcon#[27=BW32\r\n] 2006.145.14:36:20.14#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.14:36:20.14#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.14:36:20.14#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.14:36:20.14#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.14:36:20.14$setupk4/ifdk4 2006.145.14:36:20.14$ifdk4/lo= 2006.145.14:36:20.14$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.14:36:20.14$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.14:36:20.14$ifdk4/patch= 2006.145.14:36:20.14$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.14:36:20.14$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.14:36:20.14$setupk4/!*+20s 2006.145.14:36:33.26#abcon#{5=INTERFACE CLEAR} 2006.145.14:36:33.32#abcon#[5=S1D000X0/0*\r\n] 2006.145.14:36:34.66$setupk4/"tpicd 2006.145.14:36:34.66$setupk4/echo=off 2006.145.14:36:34.66$setupk4/xlog=off 2006.145.14:36:34.66:!2006.145.14:40:39 2006.145.14:36:35.14#trakl#Source acquired 2006.145.14:36:36.14#flagr#flagr/antenna,acquired 2006.145.14:40:39.00:preob 2006.145.14:40:40.13/onsource/TRACKING 2006.145.14:40:40.13:!2006.145.14:40:49 2006.145.14:40:49.00:"tape 2006.145.14:40:49.00:"st=record 2006.145.14:40:49.00:data_valid=on 2006.145.14:40:49.00:midob 2006.145.14:40:49.13/onsource/TRACKING 2006.145.14:40:49.13/wx/15.21,1020.8,88 2006.145.14:40:49.24/cable/+6.5480E-03 2006.145.14:40:50.33/va/01,08,usb,yes,28,30 2006.145.14:40:50.33/va/02,07,usb,yes,30,31 2006.145.14:40:50.33/va/03,08,usb,yes,28,29 2006.145.14:40:50.33/va/04,07,usb,yes,31,33 2006.145.14:40:50.33/va/05,04,usb,yes,27,28 2006.145.14:40:50.33/va/06,04,usb,yes,31,30 2006.145.14:40:50.33/va/07,04,usb,yes,31,32 2006.145.14:40:50.33/va/08,04,usb,yes,26,32 2006.145.14:40:50.56/valo/01,524.99,yes,locked 2006.145.14:40:50.56/valo/02,534.99,yes,locked 2006.145.14:40:50.56/valo/03,564.99,yes,locked 2006.145.14:40:50.56/valo/04,624.99,yes,locked 2006.145.14:40:50.56/valo/05,734.99,yes,locked 2006.145.14:40:50.56/valo/06,814.99,yes,locked 2006.145.14:40:50.56/valo/07,864.99,yes,locked 2006.145.14:40:50.56/valo/08,884.99,yes,locked 2006.145.14:40:51.65/vb/01,03,usb,yes,36,33 2006.145.14:40:51.65/vb/02,04,usb,yes,31,31 2006.145.14:40:51.65/vb/03,04,usb,yes,28,31 2006.145.14:40:51.65/vb/04,04,usb,yes,32,31 2006.145.14:40:51.65/vb/05,04,usb,yes,25,27 2006.145.14:40:51.65/vb/06,04,usb,yes,29,26 2006.145.14:40:51.65/vb/07,04,usb,yes,29,29 2006.145.14:40:51.65/vb/08,04,usb,yes,27,30 2006.145.14:40:51.89/vblo/01,629.99,yes,locked 2006.145.14:40:51.89/vblo/02,634.99,yes,locked 2006.145.14:40:51.89/vblo/03,649.99,yes,locked 2006.145.14:40:51.89/vblo/04,679.99,yes,locked 2006.145.14:40:51.89/vblo/05,709.99,yes,locked 2006.145.14:40:51.89/vblo/06,719.99,yes,locked 2006.145.14:40:51.89/vblo/07,734.99,yes,locked 2006.145.14:40:51.89/vblo/08,744.99,yes,locked 2006.145.14:40:52.04/vabw/8 2006.145.14:40:52.19/vbbw/8 2006.145.14:40:52.28/xfe/off,on,14.5 2006.145.14:40:52.66/ifatt/23,28,28,28 2006.145.14:40:53.07/fmout-gps/S +4.7E-08 2006.145.14:40:53.11:!2006.145.14:41:29 2006.145.14:41:29.01:data_valid=off 2006.145.14:41:29.02:"et 2006.145.14:41:29.02:!+3s 2006.145.14:41:32.03:"tape 2006.145.14:41:32.04:postob 2006.145.14:41:32.12/cable/+6.5522E-03 2006.145.14:41:32.13/wx/15.21,1020.8,88 2006.145.14:41:32.20/fmout-gps/S +4.8E-08 2006.145.14:41:32.20:scan_name=145-1442,jd0605,784 2006.145.14:41:32.20:source=1749+096,175132.82,093900.7,2000.0,cw 2006.145.14:41:34.13#flagr#flagr/antenna,new-source 2006.145.14:41:34.14:checkk5 2006.145.14:41:34.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.14:41:35.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.14:41:35.44/chk_autoobs//k5ts3/ autoobs is running! 2006.145.14:41:35.93/chk_autoobs//k5ts4/ autoobs is running! 2006.145.14:41:36.35/chk_obsdata//k5ts1/T1451440??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.14:41:36.79/chk_obsdata//k5ts2/T1451440??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.14:41:37.24/chk_obsdata//k5ts3/T1451440??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.14:41:37.67/chk_obsdata//k5ts4/T1451440??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.14:41:38.45/k5log//k5ts1_log_newline 2006.145.14:41:39.20/k5log//k5ts2_log_newline 2006.145.14:41:39.93/k5log//k5ts3_log_newline 2006.145.14:41:40.68/k5log//k5ts4_log_newline 2006.145.14:41:40.70/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.14:41:40.70:setupk4=1 2006.145.14:41:40.70$setupk4/echo=on 2006.145.14:41:40.70$setupk4/pcalon 2006.145.14:41:40.71$pcalon/"no phase cal control is implemented here 2006.145.14:41:40.71$setupk4/"tpicd=stop 2006.145.14:41:40.71$setupk4/"rec=synch_on 2006.145.14:41:40.71$setupk4/"rec_mode=128 2006.145.14:41:40.71$setupk4/!* 2006.145.14:41:40.71$setupk4/recpk4 2006.145.14:41:40.71$recpk4/recpatch= 2006.145.14:41:40.71$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.14:41:40.71$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.14:41:40.71$setupk4/vck44 2006.145.14:41:40.71$vck44/valo=1,524.99 2006.145.14:41:40.71#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.14:41:40.71#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.14:41:40.71#ibcon#ireg 17 cls_cnt 0 2006.145.14:41:40.71#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.14:41:40.71#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.14:41:40.71#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.14:41:40.75#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.14:41:40.79#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.14:41:40.79#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.14:41:40.79#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.14:41:40.79#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.14:41:40.79$vck44/va=1,8 2006.145.14:41:40.79#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.14:41:40.79#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.14:41:40.79#ibcon#ireg 11 cls_cnt 2 2006.145.14:41:40.79#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.14:41:40.79#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.14:41:40.79#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.14:41:40.81#ibcon#[25=AT01-08\r\n] 2006.145.14:41:40.84#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.14:41:40.84#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.14:41:40.84#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.14:41:40.84#ibcon#ireg 7 cls_cnt 0 2006.145.14:41:40.84#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.14:41:40.97#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.14:41:40.97#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.14:41:40.98#ibcon#[25=USB\r\n] 2006.145.14:41:41.01#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.14:41:41.01#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.14:41:41.01#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.14:41:41.01#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.14:41:41.01$vck44/valo=2,534.99 2006.145.14:41:41.01#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.14:41:41.01#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.14:41:41.01#ibcon#ireg 17 cls_cnt 0 2006.145.14:41:41.01#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.14:41:41.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.14:41:41.01#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.14:41:41.04#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.14:41:41.08#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.14:41:41.08#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.14:41:41.08#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.14:41:41.08#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.14:41:41.08$vck44/va=2,7 2006.145.14:41:41.08#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.14:41:41.08#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.14:41:41.08#ibcon#ireg 11 cls_cnt 2 2006.145.14:41:41.08#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.14:41:41.13#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.14:41:41.13#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.14:41:41.15#ibcon#[25=AT02-07\r\n] 2006.145.14:41:41.18#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.14:41:41.18#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.14:41:41.18#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.14:41:41.18#ibcon#ireg 7 cls_cnt 0 2006.145.14:41:41.18#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.14:41:41.30#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.14:41:41.30#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.14:41:41.32#ibcon#[25=USB\r\n] 2006.145.14:41:41.35#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.14:41:41.35#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.14:41:41.35#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.14:41:41.35#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.14:41:41.35$vck44/valo=3,564.99 2006.145.14:41:41.35#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.14:41:41.35#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.14:41:41.35#ibcon#ireg 17 cls_cnt 0 2006.145.14:41:41.35#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.14:41:41.35#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.14:41:41.35#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.14:41:41.37#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.14:41:41.41#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.14:41:41.41#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.14:41:41.41#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.14:41:41.41#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.14:41:41.41$vck44/va=3,8 2006.145.14:41:41.41#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.14:41:41.41#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.14:41:41.41#ibcon#ireg 11 cls_cnt 2 2006.145.14:41:41.41#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.14:41:41.47#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.14:41:41.47#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.14:41:41.49#ibcon#[25=AT03-08\r\n] 2006.145.14:41:41.52#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.14:41:41.52#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.14:41:41.52#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.14:41:41.52#ibcon#ireg 7 cls_cnt 0 2006.145.14:41:41.52#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.14:41:41.64#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.14:41:41.64#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.14:41:41.66#ibcon#[25=USB\r\n] 2006.145.14:41:41.69#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.14:41:41.69#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.14:41:41.69#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.14:41:41.69#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.14:41:41.69$vck44/valo=4,624.99 2006.145.14:41:41.69#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.14:41:41.69#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.14:41:41.69#ibcon#ireg 17 cls_cnt 0 2006.145.14:41:41.69#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.14:41:41.69#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.14:41:41.69#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.14:41:41.71#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.14:41:41.75#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.14:41:41.75#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.14:41:41.75#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.14:41:41.75#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.14:41:41.75$vck44/va=4,7 2006.145.14:41:41.75#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.14:41:41.75#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.14:41:41.75#ibcon#ireg 11 cls_cnt 2 2006.145.14:41:41.75#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.14:41:41.81#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.14:41:41.81#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.14:41:41.83#ibcon#[25=AT04-07\r\n] 2006.145.14:41:41.86#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.14:41:41.86#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.14:41:41.86#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.14:41:41.86#ibcon#ireg 7 cls_cnt 0 2006.145.14:41:41.86#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.14:41:41.98#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.14:41:41.98#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.14:41:42.00#ibcon#[25=USB\r\n] 2006.145.14:41:42.03#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.14:41:42.03#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.14:41:42.03#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.14:41:42.03#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.14:41:42.03$vck44/valo=5,734.99 2006.145.14:41:42.03#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.14:41:42.03#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.14:41:42.03#ibcon#ireg 17 cls_cnt 0 2006.145.14:41:42.03#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.14:41:42.03#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.14:41:42.03#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.14:41:42.05#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.14:41:42.09#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.14:41:42.09#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.14:41:42.09#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.14:41:42.09#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.14:41:42.09$vck44/va=5,4 2006.145.14:41:42.09#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.14:41:42.09#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.14:41:42.09#ibcon#ireg 11 cls_cnt 2 2006.145.14:41:42.09#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.14:41:42.15#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.14:41:42.15#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.14:41:42.17#ibcon#[25=AT05-04\r\n] 2006.145.14:41:42.20#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.14:41:42.20#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.14:41:42.20#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.14:41:42.20#ibcon#ireg 7 cls_cnt 0 2006.145.14:41:42.20#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.14:41:42.32#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.14:41:42.32#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.14:41:42.34#ibcon#[25=USB\r\n] 2006.145.14:41:42.37#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.14:41:42.37#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.14:41:42.37#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.14:41:42.37#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.14:41:42.37$vck44/valo=6,814.99 2006.145.14:41:42.37#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.14:41:42.37#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.14:41:42.37#ibcon#ireg 17 cls_cnt 0 2006.145.14:41:42.37#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.14:41:42.37#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.14:41:42.37#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.14:41:42.39#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.14:41:42.43#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.14:41:42.43#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.14:41:42.43#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.14:41:42.43#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.14:41:42.43$vck44/va=6,4 2006.145.14:41:42.43#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.14:41:42.43#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.14:41:42.43#ibcon#ireg 11 cls_cnt 2 2006.145.14:41:42.43#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.14:41:42.49#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.14:41:42.49#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.14:41:42.51#ibcon#[25=AT06-04\r\n] 2006.145.14:41:42.54#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.14:41:42.54#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.14:41:42.54#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.14:41:42.54#ibcon#ireg 7 cls_cnt 0 2006.145.14:41:42.54#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.14:41:42.66#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.14:41:42.66#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.14:41:42.68#ibcon#[25=USB\r\n] 2006.145.14:41:42.71#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.14:41:42.71#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.14:41:42.71#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.14:41:42.71#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.14:41:42.71$vck44/valo=7,864.99 2006.145.14:41:42.71#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.14:41:42.71#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.14:41:42.71#ibcon#ireg 17 cls_cnt 0 2006.145.14:41:42.71#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.14:41:42.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.14:41:42.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.14:41:42.73#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.14:41:42.77#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.14:41:42.77#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.14:41:42.77#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.14:41:42.77#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.14:41:42.77$vck44/va=7,4 2006.145.14:41:42.77#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.14:41:42.77#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.14:41:42.77#ibcon#ireg 11 cls_cnt 2 2006.145.14:41:42.77#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.14:41:42.83#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.14:41:42.83#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.14:41:42.85#ibcon#[25=AT07-04\r\n] 2006.145.14:41:42.88#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.14:41:42.88#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.14:41:42.88#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.14:41:42.88#ibcon#ireg 7 cls_cnt 0 2006.145.14:41:42.88#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.14:41:43.00#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.14:41:43.00#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.14:41:43.02#ibcon#[25=USB\r\n] 2006.145.14:41:43.05#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.14:41:43.05#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.14:41:43.05#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.14:41:43.05#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.14:41:43.05$vck44/valo=8,884.99 2006.145.14:41:43.05#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.14:41:43.05#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.14:41:43.05#ibcon#ireg 17 cls_cnt 0 2006.145.14:41:43.05#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.14:41:43.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.14:41:43.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.14:41:43.07#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.14:41:43.11#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.14:41:43.11#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.14:41:43.11#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.14:41:43.11#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.14:41:43.11$vck44/va=8,4 2006.145.14:41:43.11#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.14:41:43.11#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.14:41:43.11#ibcon#ireg 11 cls_cnt 2 2006.145.14:41:43.11#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.14:41:43.17#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.14:41:43.17#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.14:41:43.19#ibcon#[25=AT08-04\r\n] 2006.145.14:41:43.22#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.14:41:43.22#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.14:41:43.22#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.14:41:43.22#ibcon#ireg 7 cls_cnt 0 2006.145.14:41:43.22#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.14:41:43.34#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.14:41:43.34#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.14:41:43.36#ibcon#[25=USB\r\n] 2006.145.14:41:43.39#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.14:41:43.39#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.14:41:43.39#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.14:41:43.39#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.14:41:43.39$vck44/vblo=1,629.99 2006.145.14:41:43.39#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.14:41:43.39#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.14:41:43.39#ibcon#ireg 17 cls_cnt 0 2006.145.14:41:43.39#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.14:41:43.39#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.14:41:43.39#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.14:41:43.41#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.14:41:43.45#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.14:41:43.45#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.14:41:43.45#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.14:41:43.45#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.14:41:43.45$vck44/vb=1,3 2006.145.14:41:43.45#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.14:41:43.45#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.14:41:43.45#ibcon#ireg 11 cls_cnt 2 2006.145.14:41:43.45#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.14:41:43.45#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.14:41:43.45#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.14:41:43.47#ibcon#[27=AT01-03\r\n] 2006.145.14:41:43.50#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.14:41:43.50#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.14:41:43.50#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.14:41:43.50#ibcon#ireg 7 cls_cnt 0 2006.145.14:41:43.50#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.14:41:43.62#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.14:41:43.62#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.14:41:43.64#ibcon#[27=USB\r\n] 2006.145.14:41:43.67#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.14:41:43.67#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.14:41:43.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.14:41:43.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.14:41:43.67$vck44/vblo=2,634.99 2006.145.14:41:43.67#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.14:41:43.67#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.14:41:43.67#ibcon#ireg 17 cls_cnt 0 2006.145.14:41:43.67#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.14:41:43.67#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.14:41:43.67#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.14:41:43.69#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.14:41:43.73#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.14:41:43.73#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.14:41:43.73#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.14:41:43.73#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.14:41:43.73$vck44/vb=2,4 2006.145.14:41:43.73#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.14:41:43.73#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.14:41:43.73#ibcon#ireg 11 cls_cnt 2 2006.145.14:41:43.73#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.14:41:43.79#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.14:41:43.79#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.14:41:43.81#ibcon#[27=AT02-04\r\n] 2006.145.14:41:43.84#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.14:41:43.84#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.14:41:43.84#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.14:41:43.84#ibcon#ireg 7 cls_cnt 0 2006.145.14:41:43.84#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.14:41:43.96#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.14:41:43.96#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.14:41:43.98#ibcon#[27=USB\r\n] 2006.145.14:41:44.01#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.14:41:44.01#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.14:41:44.01#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.14:41:44.01#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.14:41:44.01$vck44/vblo=3,649.99 2006.145.14:41:44.01#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.14:41:44.01#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.14:41:44.01#ibcon#ireg 17 cls_cnt 0 2006.145.14:41:44.01#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.14:41:44.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.14:41:44.01#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.14:41:44.03#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.14:41:44.07#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.14:41:44.07#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.14:41:44.07#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.14:41:44.07#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.14:41:44.07$vck44/vb=3,4 2006.145.14:41:44.07#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.14:41:44.07#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.14:41:44.07#ibcon#ireg 11 cls_cnt 2 2006.145.14:41:44.07#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.14:41:44.13#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.14:41:44.13#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.14:41:44.15#ibcon#[27=AT03-04\r\n] 2006.145.14:41:44.18#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.14:41:44.18#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.14:41:44.18#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.14:41:44.18#ibcon#ireg 7 cls_cnt 0 2006.145.14:41:44.18#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.14:41:44.30#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.14:41:44.30#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.14:41:44.32#ibcon#[27=USB\r\n] 2006.145.14:41:44.35#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.14:41:44.35#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.14:41:44.35#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.14:41:44.35#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.14:41:44.35$vck44/vblo=4,679.99 2006.145.14:41:44.35#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.14:41:44.35#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.14:41:44.35#ibcon#ireg 17 cls_cnt 0 2006.145.14:41:44.35#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.14:41:44.35#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.14:41:44.35#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.14:41:44.37#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.14:41:44.41#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.14:41:44.41#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.14:41:44.41#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.14:41:44.41#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.14:41:44.41$vck44/vb=4,4 2006.145.14:41:44.41#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.14:41:44.41#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.14:41:44.41#ibcon#ireg 11 cls_cnt 2 2006.145.14:41:44.41#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.14:41:44.47#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.14:41:44.47#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.14:41:44.49#ibcon#[27=AT04-04\r\n] 2006.145.14:41:44.52#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.14:41:44.52#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.14:41:44.52#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.14:41:44.52#ibcon#ireg 7 cls_cnt 0 2006.145.14:41:44.52#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.14:41:44.64#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.14:41:44.64#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.14:41:44.66#ibcon#[27=USB\r\n] 2006.145.14:41:44.69#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.14:41:44.69#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.14:41:44.69#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.14:41:44.69#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.14:41:44.69$vck44/vblo=5,709.99 2006.145.14:41:44.69#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.14:41:44.69#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.14:41:44.69#ibcon#ireg 17 cls_cnt 0 2006.145.14:41:44.69#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.14:41:44.69#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.14:41:44.69#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.14:41:44.71#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.14:41:44.75#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.14:41:44.75#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.14:41:44.75#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.14:41:44.75#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.14:41:44.75$vck44/vb=5,4 2006.145.14:41:44.75#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.14:41:44.75#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.14:41:44.75#ibcon#ireg 11 cls_cnt 2 2006.145.14:41:44.75#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.14:41:44.81#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.14:41:44.81#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.14:41:44.83#ibcon#[27=AT05-04\r\n] 2006.145.14:41:44.86#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.14:41:44.86#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.14:41:44.86#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.14:41:44.86#ibcon#ireg 7 cls_cnt 0 2006.145.14:41:44.86#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.14:41:44.98#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.14:41:44.98#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.14:41:45.00#ibcon#[27=USB\r\n] 2006.145.14:41:45.03#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.14:41:45.03#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.14:41:45.03#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.14:41:45.03#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.14:41:45.03$vck44/vblo=6,719.99 2006.145.14:41:45.03#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.14:41:45.03#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.14:41:45.03#ibcon#ireg 17 cls_cnt 0 2006.145.14:41:45.03#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.14:41:45.03#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.14:41:45.03#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.14:41:45.05#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.14:41:45.09#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.14:41:45.09#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.14:41:45.09#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.14:41:45.09#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.14:41:45.09$vck44/vb=6,4 2006.145.14:41:45.09#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.14:41:45.09#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.14:41:45.09#ibcon#ireg 11 cls_cnt 2 2006.145.14:41:45.09#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.14:41:45.15#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.14:41:45.15#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.14:41:45.17#ibcon#[27=AT06-04\r\n] 2006.145.14:41:45.20#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.14:41:45.20#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.14:41:45.20#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.14:41:45.20#ibcon#ireg 7 cls_cnt 0 2006.145.14:41:45.20#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.14:41:45.32#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.14:41:45.32#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.14:41:45.34#ibcon#[27=USB\r\n] 2006.145.14:41:45.37#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.14:41:45.37#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.14:41:45.37#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.14:41:45.37#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.14:41:45.37$vck44/vblo=7,734.99 2006.145.14:41:45.37#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.14:41:45.37#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.14:41:45.37#ibcon#ireg 17 cls_cnt 0 2006.145.14:41:45.37#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.14:41:45.37#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.14:41:45.37#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.14:41:45.39#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.14:41:45.43#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.14:41:45.43#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.14:41:45.43#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.14:41:45.43#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.14:41:45.43$vck44/vb=7,4 2006.145.14:41:45.43#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.14:41:45.43#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.14:41:45.43#ibcon#ireg 11 cls_cnt 2 2006.145.14:41:45.43#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.14:41:45.49#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.14:41:45.49#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.14:41:45.51#ibcon#[27=AT07-04\r\n] 2006.145.14:41:45.54#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.14:41:45.54#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.14:41:45.54#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.14:41:45.54#ibcon#ireg 7 cls_cnt 0 2006.145.14:41:45.54#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.14:41:45.66#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.14:41:45.66#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.14:41:45.68#ibcon#[27=USB\r\n] 2006.145.14:41:45.71#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.14:41:45.71#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.14:41:45.71#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.14:41:45.71#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.14:41:45.71$vck44/vblo=8,744.99 2006.145.14:41:45.71#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.14:41:45.71#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.14:41:45.71#ibcon#ireg 17 cls_cnt 0 2006.145.14:41:45.71#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.14:41:45.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.14:41:45.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.14:41:45.73#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.14:41:45.77#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.14:41:45.77#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.14:41:45.77#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.14:41:45.77#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.14:41:45.77$vck44/vb=8,4 2006.145.14:41:45.77#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.14:41:45.77#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.14:41:45.77#ibcon#ireg 11 cls_cnt 2 2006.145.14:41:45.77#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.14:41:45.83#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.14:41:45.83#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.14:41:45.85#ibcon#[27=AT08-04\r\n] 2006.145.14:41:45.88#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.14:41:45.88#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.14:41:45.88#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.14:41:45.88#ibcon#ireg 7 cls_cnt 0 2006.145.14:41:45.88#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.14:41:46.00#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.14:41:46.00#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.14:41:46.02#ibcon#[27=USB\r\n] 2006.145.14:41:46.05#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.14:41:46.05#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.14:41:46.05#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.14:41:46.05#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.14:41:46.05$vck44/vabw=wide 2006.145.14:41:46.05#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.14:41:46.05#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.14:41:46.05#ibcon#ireg 8 cls_cnt 0 2006.145.14:41:46.05#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.14:41:46.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.14:41:46.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.14:41:46.07#ibcon#[25=BW32\r\n] 2006.145.14:41:46.10#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.14:41:46.10#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.14:41:46.10#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.14:41:46.10#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.14:41:46.10$vck44/vbbw=wide 2006.145.14:41:46.10#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.14:41:46.10#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.14:41:46.10#ibcon#ireg 8 cls_cnt 0 2006.145.14:41:46.10#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:41:46.17#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:41:46.17#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:41:46.19#ibcon#[27=BW32\r\n] 2006.145.14:41:46.22#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:41:46.22#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:41:46.22#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.14:41:46.22#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.14:41:46.22$setupk4/ifdk4 2006.145.14:41:46.22$ifdk4/lo= 2006.145.14:41:46.22$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.14:41:46.22$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.14:41:46.22$ifdk4/patch= 2006.145.14:41:46.22$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.14:41:46.22$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.14:41:46.22$setupk4/!*+20s 2006.145.14:41:48.14#trakl#Source acquired 2006.145.14:41:48.61#abcon#<5=/08 0.8 1.7 15.22 881020.8\r\n> 2006.145.14:41:48.63#abcon#{5=INTERFACE CLEAR} 2006.145.14:41:48.69#abcon#[5=S1D000X0/0*\r\n] 2006.145.14:41:50.14#flagr#flagr/antenna,acquired 2006.145.14:41:58.78#abcon#<5=/08 0.8 1.7 15.22 881020.8\r\n> 2006.145.14:41:58.80#abcon#{5=INTERFACE CLEAR} 2006.145.14:41:58.86#abcon#[5=S1D000X0/0*\r\n] 2006.145.14:42:00.72$setupk4/"tpicd 2006.145.14:42:00.72$setupk4/echo=off 2006.145.14:42:00.72$setupk4/xlog=off 2006.145.14:42:00.72:!2006.145.14:42:15 2006.145.14:42:15.00:preob 2006.145.14:42:15.14/onsource/TRACKING 2006.145.14:42:15.14:!2006.145.14:42:25 2006.145.14:42:25.00:"tape 2006.145.14:42:25.00:"st=record 2006.145.14:42:25.00:data_valid=on 2006.145.14:42:25.00:midob 2006.145.14:42:26.14/onsource/TRACKING 2006.145.14:42:26.14/wx/15.22,1020.8,88 2006.145.14:42:26.25/cable/+6.5498E-03 2006.145.14:42:27.34/va/01,08,usb,yes,28,30 2006.145.14:42:27.34/va/02,07,usb,yes,30,31 2006.145.14:42:27.34/va/03,08,usb,yes,27,28 2006.145.14:42:27.34/va/04,07,usb,yes,31,32 2006.145.14:42:27.34/va/05,04,usb,yes,27,27 2006.145.14:42:27.34/va/06,04,usb,yes,30,30 2006.145.14:42:27.34/va/07,04,usb,yes,30,32 2006.145.14:42:27.34/va/08,04,usb,yes,26,31 2006.145.14:42:27.57/valo/01,524.99,yes,locked 2006.145.14:42:27.57/valo/02,534.99,yes,locked 2006.145.14:42:27.57/valo/03,564.99,yes,locked 2006.145.14:42:27.57/valo/04,624.99,yes,locked 2006.145.14:42:27.57/valo/05,734.99,yes,locked 2006.145.14:42:27.57/valo/06,814.99,yes,locked 2006.145.14:42:27.57/valo/07,864.99,yes,locked 2006.145.14:42:27.57/valo/08,884.99,yes,locked 2006.145.14:42:28.66/vb/01,03,usb,yes,35,33 2006.145.14:42:28.66/vb/02,04,usb,yes,31,31 2006.145.14:42:28.66/vb/03,04,usb,yes,28,31 2006.145.14:42:28.66/vb/04,04,usb,yes,32,31 2006.145.14:42:28.66/vb/05,04,usb,yes,25,27 2006.145.14:42:28.66/vb/06,04,usb,yes,29,25 2006.145.14:42:28.66/vb/07,04,usb,yes,29,28 2006.145.14:42:28.66/vb/08,04,usb,yes,26,30 2006.145.14:42:28.89/vblo/01,629.99,yes,locked 2006.145.14:42:28.89/vblo/02,634.99,yes,locked 2006.145.14:42:28.89/vblo/03,649.99,yes,locked 2006.145.14:42:28.89/vblo/04,679.99,yes,locked 2006.145.14:42:28.89/vblo/05,709.99,yes,locked 2006.145.14:42:28.89/vblo/06,719.99,yes,locked 2006.145.14:42:28.89/vblo/07,734.99,yes,locked 2006.145.14:42:28.89/vblo/08,744.99,yes,locked 2006.145.14:42:29.04/vabw/8 2006.145.14:42:29.19/vbbw/8 2006.145.14:42:29.28/xfe/off,on,15.2 2006.145.14:42:29.70/ifatt/23,28,28,28 2006.145.14:42:30.07/fmout-gps/S +4.7E-08 2006.145.14:42:30.15:!2006.145.14:55:29 2006.145.14:55:29.00:data_valid=off 2006.145.14:55:29.00:"et 2006.145.14:55:29.01:!+3s 2006.145.14:55:32.02:"tape 2006.145.14:55:32.02:postob 2006.145.14:55:32.17/cable/+6.5472E-03 2006.145.14:55:32.17/wx/15.29,1020.7,87 2006.145.14:55:33.08/fmout-gps/S +4.7E-08 2006.145.14:55:33.08:scan_name=145-1457,jd0605,90 2006.145.14:55:33.09:source=3c274,123049.42,122328.0,2000.0,cw 2006.145.14:55:34.13#flagr#flagr/antenna,new-source 2006.145.14:55:34.13:checkk5 2006.145.14:55:34.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.14:55:35.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.14:55:35.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.14:55:35.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.14:55:36.61/chk_obsdata//k5ts1/T1451442??a.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.14:55:37.36/chk_obsdata//k5ts2/T1451442??b.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.14:55:38.11/chk_obsdata//k5ts3/T1451442??c.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.14:55:38.85/chk_obsdata//k5ts4/T1451442??d.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.14:55:39.62/k5log//k5ts1_log_newline 2006.145.14:55:40.37/k5log//k5ts2_log_newline 2006.145.14:55:41.11/k5log//k5ts3_log_newline 2006.145.14:55:41.85/k5log//k5ts4_log_newline 2006.145.14:55:41.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.14:55:41.88:setupk4=1 2006.145.14:55:41.88$setupk4/echo=on 2006.145.14:55:41.88$setupk4/pcalon 2006.145.14:55:41.88$pcalon/"no phase cal control is implemented here 2006.145.14:55:41.88$setupk4/"tpicd=stop 2006.145.14:55:41.88$setupk4/"rec=synch_on 2006.145.14:55:41.88$setupk4/"rec_mode=128 2006.145.14:55:41.88$setupk4/!* 2006.145.14:55:41.88$setupk4/recpk4 2006.145.14:55:41.88$recpk4/recpatch= 2006.145.14:55:41.89$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.14:55:41.89$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.14:55:41.89$setupk4/vck44 2006.145.14:55:41.89$vck44/valo=1,524.99 2006.145.14:55:41.89#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.14:55:41.89#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.14:55:41.89#ibcon#ireg 17 cls_cnt 0 2006.145.14:55:41.89#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:55:41.89#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:55:41.89#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:55:41.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.14:55:41.97#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:55:41.97#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:55:41.97#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.14:55:41.97#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.14:55:41.97$vck44/va=1,8 2006.145.14:55:41.97#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.14:55:41.97#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.14:55:41.97#ibcon#ireg 11 cls_cnt 2 2006.145.14:55:41.97#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:55:41.97#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:55:41.97#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:55:41.99#ibcon#[25=AT01-08\r\n] 2006.145.14:55:42.02#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:55:42.02#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:55:42.02#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.14:55:42.02#ibcon#ireg 7 cls_cnt 0 2006.145.14:55:42.02#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:55:42.16#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:55:42.16#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:55:42.18#ibcon#[25=USB\r\n] 2006.145.14:55:42.21#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:55:42.21#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:55:42.21#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.14:55:42.21#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.14:55:42.21$vck44/valo=2,534.99 2006.145.14:55:42.21#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.14:55:42.21#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.14:55:42.21#ibcon#ireg 17 cls_cnt 0 2006.145.14:55:42.21#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:55:42.21#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:55:42.21#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:55:42.23#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.14:55:42.27#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:55:42.27#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:55:42.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.14:55:42.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.14:55:42.27$vck44/va=2,7 2006.145.14:55:42.27#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.14:55:42.27#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.14:55:42.27#ibcon#ireg 11 cls_cnt 2 2006.145.14:55:42.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:55:42.33#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:55:42.33#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:55:42.35#ibcon#[25=AT02-07\r\n] 2006.145.14:55:42.38#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:55:42.38#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:55:42.38#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.14:55:42.38#ibcon#ireg 7 cls_cnt 0 2006.145.14:55:42.38#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:55:42.50#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:55:42.50#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:55:42.52#ibcon#[25=USB\r\n] 2006.145.14:55:42.55#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:55:42.55#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:55:42.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.14:55:42.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.14:55:42.55$vck44/valo=3,564.99 2006.145.14:55:42.55#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.14:55:42.55#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.14:55:42.55#ibcon#ireg 17 cls_cnt 0 2006.145.14:55:42.55#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:55:42.55#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:55:42.55#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:55:42.57#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.14:55:42.61#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:55:42.61#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:55:42.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.14:55:42.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.14:55:42.61$vck44/va=3,8 2006.145.14:55:42.61#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.14:55:42.61#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.14:55:42.61#ibcon#ireg 11 cls_cnt 2 2006.145.14:55:42.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:55:42.67#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:55:42.67#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:55:42.69#ibcon#[25=AT03-08\r\n] 2006.145.14:55:42.72#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:55:42.72#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:55:42.72#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.14:55:42.72#ibcon#ireg 7 cls_cnt 0 2006.145.14:55:42.72#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:55:42.84#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:55:42.84#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:55:42.86#ibcon#[25=USB\r\n] 2006.145.14:55:42.89#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:55:42.89#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:55:42.89#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.14:55:42.89#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.14:55:42.89$vck44/valo=4,624.99 2006.145.14:55:42.89#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.14:55:42.89#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.14:55:42.89#ibcon#ireg 17 cls_cnt 0 2006.145.14:55:42.89#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.14:55:42.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.14:55:42.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.14:55:42.91#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.14:55:42.95#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.14:55:42.95#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.14:55:42.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.14:55:42.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.14:55:42.95$vck44/va=4,7 2006.145.14:55:42.95#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.14:55:42.95#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.14:55:42.95#ibcon#ireg 11 cls_cnt 2 2006.145.14:55:42.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.14:55:43.01#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.14:55:43.01#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.14:55:43.03#ibcon#[25=AT04-07\r\n] 2006.145.14:55:43.06#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.14:55:43.06#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.14:55:43.06#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.14:55:43.06#ibcon#ireg 7 cls_cnt 0 2006.145.14:55:43.06#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.14:55:43.18#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.14:55:43.18#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.14:55:43.20#ibcon#[25=USB\r\n] 2006.145.14:55:43.23#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.14:55:43.23#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.14:55:43.23#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.14:55:43.23#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.14:55:43.23$vck44/valo=5,734.99 2006.145.14:55:43.23#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.14:55:43.23#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.14:55:43.23#ibcon#ireg 17 cls_cnt 0 2006.145.14:55:43.23#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.14:55:43.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.14:55:43.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.14:55:43.25#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.14:55:43.29#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.14:55:43.29#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.14:55:43.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.14:55:43.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.14:55:43.29$vck44/va=5,4 2006.145.14:55:43.29#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.14:55:43.29#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.14:55:43.29#ibcon#ireg 11 cls_cnt 2 2006.145.14:55:43.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.14:55:43.35#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.14:55:43.35#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.14:55:43.37#ibcon#[25=AT05-04\r\n] 2006.145.14:55:43.41#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.14:55:43.41#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.14:55:43.41#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.14:55:43.41#ibcon#ireg 7 cls_cnt 0 2006.145.14:55:43.41#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.14:55:43.53#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.14:55:43.53#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.14:55:43.55#ibcon#[25=USB\r\n] 2006.145.14:55:43.58#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.14:55:43.58#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.14:55:43.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.14:55:43.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.14:55:43.58$vck44/valo=6,814.99 2006.145.14:55:43.58#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.14:55:43.58#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.14:55:43.58#ibcon#ireg 17 cls_cnt 0 2006.145.14:55:43.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.14:55:43.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.14:55:43.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.14:55:43.60#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.14:55:43.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.14:55:43.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.14:55:43.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.14:55:43.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.14:55:43.64$vck44/va=6,4 2006.145.14:55:43.64#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.14:55:43.64#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.14:55:43.64#ibcon#ireg 11 cls_cnt 2 2006.145.14:55:43.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.14:55:43.70#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.14:55:43.70#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.14:55:43.72#ibcon#[25=AT06-04\r\n] 2006.145.14:55:43.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.14:55:43.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.14:55:43.75#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.14:55:43.75#ibcon#ireg 7 cls_cnt 0 2006.145.14:55:43.75#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.14:55:43.87#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.14:55:43.87#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.14:55:43.89#ibcon#[25=USB\r\n] 2006.145.14:55:43.92#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.14:55:43.92#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.14:55:43.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.14:55:43.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.14:55:43.92$vck44/valo=7,864.99 2006.145.14:55:43.92#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.14:55:43.92#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.14:55:43.92#ibcon#ireg 17 cls_cnt 0 2006.145.14:55:43.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:55:43.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:55:43.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:55:43.94#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.14:55:43.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:55:43.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:55:43.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.14:55:43.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.14:55:43.98$vck44/va=7,4 2006.145.14:55:43.98#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.14:55:43.98#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.14:55:43.98#ibcon#ireg 11 cls_cnt 2 2006.145.14:55:43.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:55:44.04#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:55:44.04#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:55:44.06#ibcon#[25=AT07-04\r\n] 2006.145.14:55:44.09#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:55:44.09#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:55:44.09#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.14:55:44.09#ibcon#ireg 7 cls_cnt 0 2006.145.14:55:44.09#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:55:44.21#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:55:44.21#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:55:44.23#ibcon#[25=USB\r\n] 2006.145.14:55:44.26#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:55:44.26#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:55:44.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.14:55:44.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.14:55:44.26$vck44/valo=8,884.99 2006.145.14:55:44.26#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.14:55:44.26#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.14:55:44.26#ibcon#ireg 17 cls_cnt 0 2006.145.14:55:44.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:55:44.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:55:44.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:55:44.28#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.14:55:44.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:55:44.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:55:44.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.14:55:44.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.14:55:44.32$vck44/va=8,4 2006.145.14:55:44.32#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.14:55:44.32#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.14:55:44.32#ibcon#ireg 11 cls_cnt 2 2006.145.14:55:44.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:55:44.38#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:55:44.38#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:55:44.40#ibcon#[25=AT08-04\r\n] 2006.145.14:55:44.43#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:55:44.43#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:55:44.43#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.14:55:44.43#ibcon#ireg 7 cls_cnt 0 2006.145.14:55:44.43#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:55:44.55#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:55:44.55#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:55:44.57#ibcon#[25=USB\r\n] 2006.145.14:55:44.60#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:55:44.60#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:55:44.60#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.14:55:44.60#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.14:55:44.60$vck44/vblo=1,629.99 2006.145.14:55:44.60#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.14:55:44.60#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.14:55:44.60#ibcon#ireg 17 cls_cnt 0 2006.145.14:55:44.60#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:55:44.60#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:55:44.60#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:55:44.62#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.14:55:44.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:55:44.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:55:44.66#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.14:55:44.66#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.14:55:44.66$vck44/vb=1,3 2006.145.14:55:44.66#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.14:55:44.66#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.14:55:44.66#ibcon#ireg 11 cls_cnt 2 2006.145.14:55:44.66#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.14:55:44.66#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.14:55:44.66#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.14:55:44.68#ibcon#[27=AT01-03\r\n] 2006.145.14:55:44.71#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.14:55:44.71#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.14:55:44.71#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.14:55:44.71#ibcon#ireg 7 cls_cnt 0 2006.145.14:55:44.71#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.14:55:44.83#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.14:55:44.83#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.14:55:44.85#ibcon#[27=USB\r\n] 2006.145.14:55:44.88#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.14:55:44.88#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.14:55:44.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.14:55:44.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.14:55:44.88$vck44/vblo=2,634.99 2006.145.14:55:44.88#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.14:55:44.88#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.14:55:44.88#ibcon#ireg 17 cls_cnt 0 2006.145.14:55:44.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:55:44.88#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:55:44.88#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:55:44.90#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.14:55:44.94#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:55:44.94#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.14:55:44.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.14:55:44.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.14:55:44.94$vck44/vb=2,4 2006.145.14:55:44.94#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.14:55:44.94#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.14:55:44.94#ibcon#ireg 11 cls_cnt 2 2006.145.14:55:44.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:55:45.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:55:45.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:55:45.02#ibcon#[27=AT02-04\r\n] 2006.145.14:55:45.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:55:45.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.14:55:45.05#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.14:55:45.05#ibcon#ireg 7 cls_cnt 0 2006.145.14:55:45.05#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:55:45.17#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:55:45.17#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:55:45.19#ibcon#[27=USB\r\n] 2006.145.14:55:45.22#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:55:45.22#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.14:55:45.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.14:55:45.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.14:55:45.22$vck44/vblo=3,649.99 2006.145.14:55:45.22#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.14:55:45.22#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.14:55:45.22#ibcon#ireg 17 cls_cnt 0 2006.145.14:55:45.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:55:45.22#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:55:45.22#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:55:45.24#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.14:55:45.28#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:55:45.28#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.14:55:45.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.14:55:45.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.14:55:45.28$vck44/vb=3,4 2006.145.14:55:45.28#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.14:55:45.28#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.14:55:45.28#ibcon#ireg 11 cls_cnt 2 2006.145.14:55:45.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:55:45.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:55:45.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:55:45.36#ibcon#[27=AT03-04\r\n] 2006.145.14:55:45.39#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:55:45.39#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.14:55:45.39#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.14:55:45.39#ibcon#ireg 7 cls_cnt 0 2006.145.14:55:45.39#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:55:45.51#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:55:45.51#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:55:45.53#ibcon#[27=USB\r\n] 2006.145.14:55:45.56#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:55:45.56#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.14:55:45.56#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.14:55:45.56#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.14:55:45.56$vck44/vblo=4,679.99 2006.145.14:55:45.56#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.14:55:45.56#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.14:55:45.56#ibcon#ireg 17 cls_cnt 0 2006.145.14:55:45.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:55:45.56#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:55:45.56#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:55:45.58#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.14:55:45.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:55:45.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.14:55:45.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.14:55:45.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.14:55:45.62$vck44/vb=4,4 2006.145.14:55:45.62#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.14:55:45.62#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.14:55:45.62#ibcon#ireg 11 cls_cnt 2 2006.145.14:55:45.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:55:45.68#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:55:45.68#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:55:45.70#ibcon#[27=AT04-04\r\n] 2006.145.14:55:45.73#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:55:45.73#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.14:55:45.73#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.14:55:45.73#ibcon#ireg 7 cls_cnt 0 2006.145.14:55:45.73#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:55:45.85#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:55:45.85#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:55:45.87#ibcon#[27=USB\r\n] 2006.145.14:55:45.90#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:55:45.90#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.14:55:45.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.14:55:45.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.14:55:45.90$vck44/vblo=5,709.99 2006.145.14:55:45.90#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.14:55:45.90#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.14:55:45.90#ibcon#ireg 17 cls_cnt 0 2006.145.14:55:45.90#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:55:45.90#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:55:45.90#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:55:45.92#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.14:55:45.92#abcon#<5=/07 1.0 1.5 15.29 871020.7\r\n> 2006.145.14:55:45.94#abcon#{5=INTERFACE CLEAR} 2006.145.14:55:45.96#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:55:45.96#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.14:55:45.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.14:55:45.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.14:55:45.96$vck44/vb=5,4 2006.145.14:55:45.96#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.14:55:45.96#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.14:55:45.96#ibcon#ireg 11 cls_cnt 2 2006.145.14:55:45.96#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:55:46.00#abcon#[5=S1D000X0/0*\r\n] 2006.145.14:55:46.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:55:46.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:55:46.04#ibcon#[27=AT05-04\r\n] 2006.145.14:55:46.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:55:46.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:55:46.07#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.14:55:46.07#ibcon#ireg 7 cls_cnt 0 2006.145.14:55:46.07#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:55:46.19#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:55:46.19#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:55:46.21#ibcon#[27=USB\r\n] 2006.145.14:55:46.24#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:55:46.24#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:55:46.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.14:55:46.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.14:55:46.24$vck44/vblo=6,719.99 2006.145.14:55:46.24#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.14:55:46.24#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.14:55:46.24#ibcon#ireg 17 cls_cnt 0 2006.145.14:55:46.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.14:55:46.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.14:55:46.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.14:55:46.26#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.14:55:46.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.14:55:46.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.14:55:46.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.14:55:46.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.14:55:46.30$vck44/vb=6,4 2006.145.14:55:46.30#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.14:55:46.30#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.14:55:46.30#ibcon#ireg 11 cls_cnt 2 2006.145.14:55:46.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.14:55:46.36#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.14:55:46.36#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.14:55:46.38#ibcon#[27=AT06-04\r\n] 2006.145.14:55:46.41#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.14:55:46.41#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.14:55:46.41#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.14:55:46.41#ibcon#ireg 7 cls_cnt 0 2006.145.14:55:46.41#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.14:55:46.53#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.14:55:46.53#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.14:55:46.55#ibcon#[27=USB\r\n] 2006.145.14:55:46.58#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.14:55:46.58#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.14:55:46.58#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.14:55:46.58#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.14:55:46.58$vck44/vblo=7,734.99 2006.145.14:55:46.58#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.14:55:46.58#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.14:55:46.58#ibcon#ireg 17 cls_cnt 0 2006.145.14:55:46.58#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:55:46.58#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:55:46.58#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:55:46.60#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.14:55:46.64#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:55:46.64#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.14:55:46.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.14:55:46.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.14:55:46.64$vck44/vb=7,4 2006.145.14:55:46.64#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.14:55:46.64#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.14:55:46.64#ibcon#ireg 11 cls_cnt 2 2006.145.14:55:46.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:55:46.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:55:46.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:55:46.72#ibcon#[27=AT07-04\r\n] 2006.145.14:55:46.75#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:55:46.75#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.14:55:46.75#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.14:55:46.75#ibcon#ireg 7 cls_cnt 0 2006.145.14:55:46.75#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:55:46.87#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:55:46.87#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:55:46.89#ibcon#[27=USB\r\n] 2006.145.14:55:46.92#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:55:46.92#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.14:55:46.92#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.14:55:46.92#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.14:55:46.92$vck44/vblo=8,744.99 2006.145.14:55:46.92#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.14:55:46.92#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.14:55:46.92#ibcon#ireg 17 cls_cnt 0 2006.145.14:55:46.92#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:55:46.92#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:55:46.92#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:55:46.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.14:55:46.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:55:46.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.14:55:46.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.14:55:46.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.14:55:46.98$vck44/vb=8,4 2006.145.14:55:46.98#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.14:55:46.98#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.14:55:46.98#ibcon#ireg 11 cls_cnt 2 2006.145.14:55:46.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:55:47.04#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:55:47.04#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:55:47.06#ibcon#[27=AT08-04\r\n] 2006.145.14:55:47.09#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:55:47.09#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.14:55:47.09#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.14:55:47.09#ibcon#ireg 7 cls_cnt 0 2006.145.14:55:47.09#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:55:47.21#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:55:47.21#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:55:47.23#ibcon#[27=USB\r\n] 2006.145.14:55:47.26#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:55:47.26#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.14:55:47.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.14:55:47.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.14:55:47.26$vck44/vabw=wide 2006.145.14:55:47.26#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.14:55:47.26#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.14:55:47.26#ibcon#ireg 8 cls_cnt 0 2006.145.14:55:47.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:55:47.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:55:47.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:55:47.28#ibcon#[25=BW32\r\n] 2006.145.14:55:47.31#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:55:47.31#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.14:55:47.31#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.14:55:47.31#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.14:55:47.31$vck44/vbbw=wide 2006.145.14:55:47.31#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.14:55:47.31#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.14:55:47.31#ibcon#ireg 8 cls_cnt 0 2006.145.14:55:47.31#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.14:55:47.38#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.14:55:47.38#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.14:55:47.40#ibcon#[27=BW32\r\n] 2006.145.14:55:47.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.14:55:47.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.14:55:47.43#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.14:55:47.43#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.14:55:47.43$setupk4/ifdk4 2006.145.14:55:47.43$ifdk4/lo= 2006.145.14:55:47.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.14:55:47.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.14:55:47.43$ifdk4/patch= 2006.145.14:55:47.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.14:55:47.43$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.14:55:47.43$setupk4/!*+20s 2006.145.14:55:56.09#abcon#<5=/07 1.0 1.5 15.30 871020.7\r\n> 2006.145.14:55:56.11#abcon#{5=INTERFACE CLEAR} 2006.145.14:55:56.17#abcon#[5=S1D000X0/0*\r\n] 2006.145.14:56:01.89$setupk4/"tpicd 2006.145.14:56:01.89$setupk4/echo=off 2006.145.14:56:01.89$setupk4/xlog=off 2006.145.14:56:01.89:!2006.145.14:57:20 2006.145.14:56:21.13#trakl#Source acquired 2006.145.14:56:23.13#flagr#flagr/antenna,acquired 2006.145.14:57:20.00:preob 2006.145.14:57:21.13/onsource/TRACKING 2006.145.14:57:21.13:!2006.145.14:57:30 2006.145.14:57:30.00:"tape 2006.145.14:57:30.00:"st=record 2006.145.14:57:30.00:data_valid=on 2006.145.14:57:30.00:midob 2006.145.14:57:30.13/onsource/TRACKING 2006.145.14:57:30.13/wx/15.31,1020.7,87 2006.145.14:57:30.34/cable/+6.5495E-03 2006.145.14:57:31.43/va/01,08,usb,yes,32,34 2006.145.14:57:31.43/va/02,07,usb,yes,34,35 2006.145.14:57:31.43/va/03,08,usb,yes,31,32 2006.145.14:57:31.43/va/04,07,usb,yes,35,37 2006.145.14:57:31.43/va/05,04,usb,yes,30,31 2006.145.14:57:31.43/va/06,04,usb,yes,34,34 2006.145.14:57:31.43/va/07,04,usb,yes,34,36 2006.145.14:57:31.43/va/08,04,usb,yes,29,35 2006.145.14:57:31.66/valo/01,524.99,yes,locked 2006.145.14:57:31.66/valo/02,534.99,yes,locked 2006.145.14:57:31.66/valo/03,564.99,yes,locked 2006.145.14:57:31.66/valo/04,624.99,yes,locked 2006.145.14:57:31.66/valo/05,734.99,yes,locked 2006.145.14:57:31.66/valo/06,814.99,yes,locked 2006.145.14:57:31.66/valo/07,864.99,yes,locked 2006.145.14:57:31.66/valo/08,884.99,yes,locked 2006.145.14:57:32.75/vb/01,03,usb,yes,44,41 2006.145.14:57:32.75/vb/02,04,usb,yes,39,38 2006.145.14:57:32.75/vb/03,04,usb,yes,35,39 2006.145.14:57:32.75/vb/04,04,usb,yes,40,39 2006.145.14:57:32.75/vb/05,04,usb,yes,31,34 2006.145.14:57:32.75/vb/06,04,usb,yes,36,32 2006.145.14:57:32.75/vb/07,04,usb,yes,36,36 2006.145.14:57:32.75/vb/08,04,usb,yes,33,37 2006.145.14:57:32.98/vblo/01,629.99,yes,locked 2006.145.14:57:32.98/vblo/02,634.99,yes,locked 2006.145.14:57:32.98/vblo/03,649.99,yes,locked 2006.145.14:57:32.98/vblo/04,679.99,yes,locked 2006.145.14:57:32.98/vblo/05,709.99,yes,locked 2006.145.14:57:32.98/vblo/06,719.99,yes,locked 2006.145.14:57:32.98/vblo/07,734.99,yes,locked 2006.145.14:57:32.98/vblo/08,744.99,yes,locked 2006.145.14:57:33.13/vabw/8 2006.145.14:57:33.28/vbbw/8 2006.145.14:57:33.37/xfe/off,on,15.2 2006.145.14:57:33.75/ifatt/23,28,28,28 2006.145.14:57:34.08/fmout-gps/S +4.7E-08 2006.145.14:57:34.12:!2006.145.14:59:00 2006.145.14:59:00.00:data_valid=off 2006.145.14:59:00.00:"et 2006.145.14:59:00.00:!+3s 2006.145.14:59:03.02:"tape 2006.145.14:59:03.02:postob 2006.145.14:59:03.16/cable/+6.5487E-03 2006.145.14:59:03.16/wx/15.33,1020.6,87 2006.145.14:59:04.08/fmout-gps/S +4.6E-08 2006.145.14:59:04.08:scan_name=145-1503,jd0605,190 2006.145.14:59:04.08:source=1044+719,104827.62,714335.9,2000.0,cw 2006.145.14:59:04.14#flagr#flagr/antenna,new-source 2006.145.14:59:05.14:checkk5 2006.145.14:59:05.57/chk_autoobs//k5ts1/ autoobs is running! 2006.145.14:59:06.00/chk_autoobs//k5ts2/ autoobs is running! 2006.145.14:59:06.43/chk_autoobs//k5ts3/ autoobs is running! 2006.145.14:59:06.87/chk_autoobs//k5ts4/ autoobs is running! 2006.145.14:59:07.30/chk_obsdata//k5ts1/T1451457??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.14:59:07.72/chk_obsdata//k5ts2/T1451457??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.14:59:08.16/chk_obsdata//k5ts3/T1451457??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.14:59:08.60/chk_obsdata//k5ts4/T1451457??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.14:59:09.36/k5log//k5ts1_log_newline 2006.145.14:59:10.11/k5log//k5ts2_log_newline 2006.145.14:59:10.85/k5log//k5ts3_log_newline 2006.145.14:59:11.59/k5log//k5ts4_log_newline 2006.145.14:59:11.62/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.14:59:11.62:setupk4=1 2006.145.14:59:11.62$setupk4/echo=on 2006.145.14:59:11.62$setupk4/pcalon 2006.145.14:59:11.62$pcalon/"no phase cal control is implemented here 2006.145.14:59:11.62$setupk4/"tpicd=stop 2006.145.14:59:11.62$setupk4/"rec=synch_on 2006.145.14:59:11.62$setupk4/"rec_mode=128 2006.145.14:59:11.62$setupk4/!* 2006.145.14:59:11.62$setupk4/recpk4 2006.145.14:59:11.62$recpk4/recpatch= 2006.145.14:59:11.62$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.14:59:11.62$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.14:59:11.62$setupk4/vck44 2006.145.14:59:11.62$vck44/valo=1,524.99 2006.145.14:59:11.62#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.14:59:11.62#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.14:59:11.62#ibcon#ireg 17 cls_cnt 0 2006.145.14:59:11.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:59:11.62#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:59:11.62#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:59:11.66#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.14:59:11.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:59:11.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:59:11.71#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.14:59:11.71#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.14:59:11.71$vck44/va=1,8 2006.145.14:59:11.71#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.14:59:11.71#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.14:59:11.71#ibcon#ireg 11 cls_cnt 2 2006.145.14:59:11.71#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.14:59:11.71#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.14:59:11.71#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.14:59:11.73#ibcon#[25=AT01-08\r\n] 2006.145.14:59:11.76#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.14:59:11.76#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.14:59:11.76#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.14:59:11.76#ibcon#ireg 7 cls_cnt 0 2006.145.14:59:11.76#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.14:59:11.88#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.14:59:11.88#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.14:59:11.90#ibcon#[25=USB\r\n] 2006.145.14:59:11.93#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.14:59:11.93#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.14:59:11.93#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.14:59:11.93#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.14:59:11.93$vck44/valo=2,534.99 2006.145.14:59:11.93#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.14:59:11.93#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.14:59:11.93#ibcon#ireg 17 cls_cnt 0 2006.145.14:59:11.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:59:11.93#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:59:11.93#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:59:11.96#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.14:59:12.00#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:59:12.00#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:59:12.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.14:59:12.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.14:59:12.00$vck44/va=2,7 2006.145.14:59:12.00#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.14:59:12.00#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.14:59:12.00#ibcon#ireg 11 cls_cnt 2 2006.145.14:59:12.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:59:12.05#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:59:12.05#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:59:12.07#ibcon#[25=AT02-07\r\n] 2006.145.14:59:12.10#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:59:12.10#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:59:12.10#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.14:59:12.10#ibcon#ireg 7 cls_cnt 0 2006.145.14:59:12.10#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:59:12.22#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:59:12.22#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:59:12.24#ibcon#[25=USB\r\n] 2006.145.14:59:12.27#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:59:12.27#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:59:12.27#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.14:59:12.27#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.14:59:12.27$vck44/valo=3,564.99 2006.145.14:59:12.27#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.14:59:12.27#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.14:59:12.27#ibcon#ireg 17 cls_cnt 0 2006.145.14:59:12.27#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:59:12.27#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:59:12.27#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:59:12.29#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.14:59:12.33#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:59:12.33#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:59:12.33#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.14:59:12.33#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.14:59:12.33$vck44/va=3,8 2006.145.14:59:12.33#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.14:59:12.33#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.14:59:12.33#ibcon#ireg 11 cls_cnt 2 2006.145.14:59:12.33#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:59:12.39#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:59:12.39#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:59:12.41#ibcon#[25=AT03-08\r\n] 2006.145.14:59:12.44#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:59:12.44#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:59:12.44#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.14:59:12.44#ibcon#ireg 7 cls_cnt 0 2006.145.14:59:12.44#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:59:12.56#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:59:12.56#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:59:12.58#ibcon#[25=USB\r\n] 2006.145.14:59:12.61#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:59:12.61#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:59:12.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.14:59:12.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.14:59:12.61$vck44/valo=4,624.99 2006.145.14:59:12.61#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.14:59:12.61#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.14:59:12.61#ibcon#ireg 17 cls_cnt 0 2006.145.14:59:12.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:59:12.61#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:59:12.61#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:59:12.63#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.14:59:12.67#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:59:12.67#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:59:12.67#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.14:59:12.67#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.14:59:12.67$vck44/va=4,7 2006.145.14:59:12.67#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.14:59:12.67#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.14:59:12.67#ibcon#ireg 11 cls_cnt 2 2006.145.14:59:12.67#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.14:59:12.73#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.14:59:12.73#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.14:59:12.75#ibcon#[25=AT04-07\r\n] 2006.145.14:59:12.78#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.14:59:12.78#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.14:59:12.78#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.14:59:12.78#ibcon#ireg 7 cls_cnt 0 2006.145.14:59:12.78#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.14:59:12.90#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.14:59:12.90#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.14:59:12.92#ibcon#[25=USB\r\n] 2006.145.14:59:12.95#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.14:59:12.95#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.14:59:12.95#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.14:59:12.95#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.14:59:12.95$vck44/valo=5,734.99 2006.145.14:59:12.95#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.14:59:12.95#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.14:59:12.95#ibcon#ireg 17 cls_cnt 0 2006.145.14:59:12.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.14:59:12.95#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.14:59:12.95#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.14:59:12.97#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.14:59:13.01#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.14:59:13.01#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.14:59:13.01#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.14:59:13.01#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.14:59:13.01$vck44/va=5,4 2006.145.14:59:13.01#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.14:59:13.01#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.14:59:13.01#ibcon#ireg 11 cls_cnt 2 2006.145.14:59:13.01#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.14:59:13.07#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.14:59:13.07#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.14:59:13.09#ibcon#[25=AT05-04\r\n] 2006.145.14:59:13.13#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.14:59:13.13#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.14:59:13.13#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.14:59:13.13#ibcon#ireg 7 cls_cnt 0 2006.145.14:59:13.13#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.14:59:13.25#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.14:59:13.25#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.14:59:13.27#ibcon#[25=USB\r\n] 2006.145.14:59:13.30#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.14:59:13.30#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.14:59:13.30#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.14:59:13.30#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.14:59:13.30$vck44/valo=6,814.99 2006.145.14:59:13.30#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.14:59:13.30#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.14:59:13.30#ibcon#ireg 17 cls_cnt 0 2006.145.14:59:13.30#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:59:13.30#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:59:13.30#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:59:13.32#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.14:59:13.36#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:59:13.36#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:59:13.36#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.14:59:13.36#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.14:59:13.36$vck44/va=6,4 2006.145.14:59:13.36#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.14:59:13.36#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.14:59:13.36#ibcon#ireg 11 cls_cnt 2 2006.145.14:59:13.36#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.14:59:13.42#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.14:59:13.42#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.14:59:13.44#ibcon#[25=AT06-04\r\n] 2006.145.14:59:13.47#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.14:59:13.47#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.14:59:13.47#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.14:59:13.47#ibcon#ireg 7 cls_cnt 0 2006.145.14:59:13.47#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.14:59:13.59#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.14:59:13.59#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.14:59:13.61#ibcon#[25=USB\r\n] 2006.145.14:59:13.64#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.14:59:13.64#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.14:59:13.64#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.14:59:13.64#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.14:59:13.64$vck44/valo=7,864.99 2006.145.14:59:13.64#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.14:59:13.64#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.14:59:13.64#ibcon#ireg 17 cls_cnt 0 2006.145.14:59:13.64#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.14:59:13.64#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.14:59:13.64#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.14:59:13.66#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.14:59:13.70#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.14:59:13.70#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.14:59:13.70#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.14:59:13.70#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.14:59:13.70$vck44/va=7,4 2006.145.14:59:13.70#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.14:59:13.70#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.14:59:13.70#ibcon#ireg 11 cls_cnt 2 2006.145.14:59:13.70#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.14:59:13.76#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.14:59:13.76#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.14:59:13.78#ibcon#[25=AT07-04\r\n] 2006.145.14:59:13.81#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.14:59:13.81#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.14:59:13.81#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.14:59:13.81#ibcon#ireg 7 cls_cnt 0 2006.145.14:59:13.81#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.14:59:13.93#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.14:59:13.93#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.14:59:13.95#ibcon#[25=USB\r\n] 2006.145.14:59:13.98#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.14:59:13.98#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.14:59:13.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.14:59:13.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.14:59:13.98$vck44/valo=8,884.99 2006.145.14:59:13.98#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.14:59:13.98#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.14:59:13.98#ibcon#ireg 17 cls_cnt 0 2006.145.14:59:13.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:59:13.98#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:59:13.98#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:59:14.00#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.14:59:14.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:59:14.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:59:14.04#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.14:59:14.04#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.14:59:14.04$vck44/va=8,4 2006.145.14:59:14.04#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.14:59:14.04#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.14:59:14.04#ibcon#ireg 11 cls_cnt 2 2006.145.14:59:14.04#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.14:59:14.10#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.14:59:14.10#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.14:59:14.12#ibcon#[25=AT08-04\r\n] 2006.145.14:59:14.15#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.14:59:14.15#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.14:59:14.15#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.14:59:14.15#ibcon#ireg 7 cls_cnt 0 2006.145.14:59:14.15#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.14:59:14.27#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.14:59:14.27#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.14:59:14.29#ibcon#[25=USB\r\n] 2006.145.14:59:14.33#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.14:59:14.33#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.14:59:14.33#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.14:59:14.33#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.14:59:14.33$vck44/vblo=1,629.99 2006.145.14:59:14.33#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.14:59:14.33#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.14:59:14.33#ibcon#ireg 17 cls_cnt 0 2006.145.14:59:14.33#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.14:59:14.33#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.14:59:14.33#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.14:59:14.35#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.14:59:14.39#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.14:59:14.39#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.14:59:14.39#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.14:59:14.39#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.14:59:14.39$vck44/vb=1,3 2006.145.14:59:14.39#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.14:59:14.39#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.14:59:14.39#ibcon#ireg 11 cls_cnt 2 2006.145.14:59:14.39#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.14:59:14.39#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.14:59:14.39#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.14:59:14.41#ibcon#[27=AT01-03\r\n] 2006.145.14:59:14.44#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.14:59:14.44#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.14:59:14.44#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.14:59:14.44#ibcon#ireg 7 cls_cnt 0 2006.145.14:59:14.44#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.14:59:14.56#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.14:59:14.56#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.14:59:14.58#ibcon#[27=USB\r\n] 2006.145.14:59:14.61#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.14:59:14.61#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.14:59:14.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.14:59:14.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.14:59:14.61$vck44/vblo=2,634.99 2006.145.14:59:14.61#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.14:59:14.61#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.14:59:14.61#ibcon#ireg 17 cls_cnt 0 2006.145.14:59:14.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:59:14.61#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:59:14.61#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:59:14.63#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.14:59:14.67#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:59:14.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.14:59:14.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.14:59:14.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.14:59:14.67$vck44/vb=2,4 2006.145.14:59:14.67#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.14:59:14.67#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.14:59:14.67#ibcon#ireg 11 cls_cnt 2 2006.145.14:59:14.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.14:59:14.73#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.14:59:14.73#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.14:59:14.75#ibcon#[27=AT02-04\r\n] 2006.145.14:59:14.78#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.14:59:14.78#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.14:59:14.78#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.14:59:14.78#ibcon#ireg 7 cls_cnt 0 2006.145.14:59:14.78#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.14:59:14.90#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.14:59:14.90#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.14:59:14.92#ibcon#[27=USB\r\n] 2006.145.14:59:14.95#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.14:59:14.95#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.14:59:14.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.14:59:14.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.14:59:14.95$vck44/vblo=3,649.99 2006.145.14:59:14.95#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.14:59:14.95#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.14:59:14.95#ibcon#ireg 17 cls_cnt 0 2006.145.14:59:14.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:59:14.95#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:59:14.95#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:59:14.97#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.14:59:15.01#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:59:15.01#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.14:59:15.01#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.14:59:15.01#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.14:59:15.01$vck44/vb=3,4 2006.145.14:59:15.01#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.14:59:15.01#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.14:59:15.01#ibcon#ireg 11 cls_cnt 2 2006.145.14:59:15.01#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:59:15.07#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:59:15.07#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:59:15.09#ibcon#[27=AT03-04\r\n] 2006.145.14:59:15.12#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:59:15.12#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.14:59:15.12#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.14:59:15.12#ibcon#ireg 7 cls_cnt 0 2006.145.14:59:15.12#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:59:15.24#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:59:15.24#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:59:15.26#ibcon#[27=USB\r\n] 2006.145.14:59:15.29#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:59:15.29#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.14:59:15.29#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.14:59:15.29#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.14:59:15.29$vck44/vblo=4,679.99 2006.145.14:59:15.29#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.14:59:15.29#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.14:59:15.29#ibcon#ireg 17 cls_cnt 0 2006.145.14:59:15.29#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:59:15.29#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:59:15.29#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:59:15.31#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.14:59:15.35#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:59:15.35#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.14:59:15.35#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.14:59:15.35#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.14:59:15.35$vck44/vb=4,4 2006.145.14:59:15.35#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.14:59:15.35#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.14:59:15.35#ibcon#ireg 11 cls_cnt 2 2006.145.14:59:15.35#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:59:15.41#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:59:15.41#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:59:15.43#ibcon#[27=AT04-04\r\n] 2006.145.14:59:15.46#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:59:15.46#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.14:59:15.46#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.14:59:15.46#ibcon#ireg 7 cls_cnt 0 2006.145.14:59:15.46#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:59:15.58#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:59:15.58#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:59:15.60#ibcon#[27=USB\r\n] 2006.145.14:59:15.63#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:59:15.63#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.14:59:15.63#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.14:59:15.63#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.14:59:15.63$vck44/vblo=5,709.99 2006.145.14:59:15.63#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.14:59:15.63#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.14:59:15.63#ibcon#ireg 17 cls_cnt 0 2006.145.14:59:15.63#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:59:15.63#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:59:15.63#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:59:15.65#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.14:59:15.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:59:15.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.14:59:15.69#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.14:59:15.69#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.14:59:15.69$vck44/vb=5,4 2006.145.14:59:15.69#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.14:59:15.69#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.14:59:15.69#ibcon#ireg 11 cls_cnt 2 2006.145.14:59:15.69#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.14:59:15.75#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.14:59:15.75#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.14:59:15.77#ibcon#[27=AT05-04\r\n] 2006.145.14:59:15.80#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.14:59:15.80#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.14:59:15.80#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.14:59:15.80#ibcon#ireg 7 cls_cnt 0 2006.145.14:59:15.80#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.14:59:15.92#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.14:59:15.92#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.14:59:15.94#ibcon#[27=USB\r\n] 2006.145.14:59:15.97#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.14:59:15.97#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.14:59:15.97#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.14:59:15.97#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.14:59:15.97$vck44/vblo=6,719.99 2006.145.14:59:15.97#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.14:59:15.97#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.14:59:15.97#ibcon#ireg 17 cls_cnt 0 2006.145.14:59:15.97#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.14:59:15.97#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.14:59:15.97#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.14:59:15.99#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.14:59:16.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.14:59:16.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.14:59:16.03#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.14:59:16.03#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.14:59:16.03$vck44/vb=6,4 2006.145.14:59:16.03#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.14:59:16.03#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.14:59:16.03#ibcon#ireg 11 cls_cnt 2 2006.145.14:59:16.03#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.14:59:16.09#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.14:59:16.09#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.14:59:16.11#ibcon#[27=AT06-04\r\n] 2006.145.14:59:16.14#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.14:59:16.14#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.14:59:16.14#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.14:59:16.14#ibcon#ireg 7 cls_cnt 0 2006.145.14:59:16.14#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.14:59:16.26#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.14:59:16.26#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.14:59:16.28#ibcon#[27=USB\r\n] 2006.145.14:59:16.31#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.14:59:16.31#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.14:59:16.31#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.14:59:16.31#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.14:59:16.31$vck44/vblo=7,734.99 2006.145.14:59:16.31#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.14:59:16.31#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.14:59:16.31#ibcon#ireg 17 cls_cnt 0 2006.145.14:59:16.31#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:59:16.31#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:59:16.31#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:59:16.33#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.14:59:16.37#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:59:16.37#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.14:59:16.37#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.14:59:16.37#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.14:59:16.37$vck44/vb=7,4 2006.145.14:59:16.37#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.14:59:16.37#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.14:59:16.37#ibcon#ireg 11 cls_cnt 2 2006.145.14:59:16.37#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.14:59:16.43#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.14:59:16.43#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.14:59:16.45#ibcon#[27=AT07-04\r\n] 2006.145.14:59:16.48#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.14:59:16.48#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.14:59:16.48#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.14:59:16.48#ibcon#ireg 7 cls_cnt 0 2006.145.14:59:16.48#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.14:59:16.60#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.14:59:16.60#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.14:59:16.62#ibcon#[27=USB\r\n] 2006.145.14:59:16.65#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.14:59:16.65#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.14:59:16.65#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.14:59:16.65#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.14:59:16.65$vck44/vblo=8,744.99 2006.145.14:59:16.65#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.14:59:16.65#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.14:59:16.65#ibcon#ireg 17 cls_cnt 0 2006.145.14:59:16.65#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.14:59:16.65#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.14:59:16.65#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.14:59:16.67#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.14:59:16.71#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.14:59:16.71#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.14:59:16.71#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.14:59:16.71#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.14:59:16.71$vck44/vb=8,4 2006.145.14:59:16.71#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.14:59:16.71#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.14:59:16.71#ibcon#ireg 11 cls_cnt 2 2006.145.14:59:16.71#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.14:59:16.77#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.14:59:16.77#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.14:59:16.79#ibcon#[27=AT08-04\r\n] 2006.145.14:59:16.82#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.14:59:16.82#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.14:59:16.82#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.14:59:16.82#ibcon#ireg 7 cls_cnt 0 2006.145.14:59:16.82#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.14:59:16.94#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.14:59:16.94#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.14:59:16.96#ibcon#[27=USB\r\n] 2006.145.14:59:16.99#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.14:59:16.99#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.14:59:16.99#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.14:59:16.99#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.14:59:16.99$vck44/vabw=wide 2006.145.14:59:16.99#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.14:59:16.99#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.14:59:16.99#ibcon#ireg 8 cls_cnt 0 2006.145.14:59:16.99#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:59:16.99#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:59:16.99#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:59:17.01#ibcon#[25=BW32\r\n] 2006.145.14:59:17.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:59:17.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.14:59:17.04#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.14:59:17.04#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.14:59:17.04$vck44/vbbw=wide 2006.145.14:59:17.04#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.14:59:17.04#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.14:59:17.04#ibcon#ireg 8 cls_cnt 0 2006.145.14:59:17.04#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.14:59:17.11#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.14:59:17.11#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.14:59:17.13#ibcon#[27=BW32\r\n] 2006.145.14:59:17.16#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.14:59:17.16#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.14:59:17.16#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.14:59:17.16#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.14:59:17.16$setupk4/ifdk4 2006.145.14:59:17.16$ifdk4/lo= 2006.145.14:59:17.16$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.14:59:17.16$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.14:59:17.16$ifdk4/patch= 2006.145.14:59:17.16$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.14:59:17.16$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.14:59:17.16$setupk4/!*+20s 2006.145.14:59:19.50#abcon#<5=/07 1.0 1.5 15.33 871020.6\r\n> 2006.145.14:59:19.52#abcon#{5=INTERFACE CLEAR} 2006.145.14:59:19.58#abcon#[5=S1D000X0/0*\r\n] 2006.145.14:59:29.67#abcon#<5=/07 1.0 1.5 15.33 871020.6\r\n> 2006.145.14:59:29.69#abcon#{5=INTERFACE CLEAR} 2006.145.14:59:29.75#abcon#[5=S1D000X0/0*\r\n] 2006.145.14:59:31.63$setupk4/"tpicd 2006.145.14:59:31.63$setupk4/echo=off 2006.145.14:59:31.63$setupk4/xlog=off 2006.145.14:59:31.63:!2006.145.15:02:57 2006.145.14:59:38.14#trakl#Source acquired 2006.145.14:59:40.14#flagr#flagr/antenna,acquired 2006.145.15:02:57.00:preob 2006.145.15:02:57.14/onsource/TRACKING 2006.145.15:02:57.14:!2006.145.15:03:07 2006.145.15:03:07.00:"tape 2006.145.15:03:07.00:"st=record 2006.145.15:03:07.00:data_valid=on 2006.145.15:03:07.00:midob 2006.145.15:03:07.14/onsource/TRACKING 2006.145.15:03:07.14/wx/15.38,1020.5,88 2006.145.15:03:07.29/cable/+6.5481E-03 2006.145.15:03:08.38/va/01,08,usb,yes,29,31 2006.145.15:03:08.38/va/02,07,usb,yes,31,31 2006.145.15:03:08.38/va/03,08,usb,yes,28,29 2006.145.15:03:08.38/va/04,07,usb,yes,32,33 2006.145.15:03:08.38/va/05,04,usb,yes,28,28 2006.145.15:03:08.38/va/06,04,usb,yes,31,31 2006.145.15:03:08.38/va/07,04,usb,yes,31,32 2006.145.15:03:08.38/va/08,04,usb,yes,27,32 2006.145.15:03:08.61/valo/01,524.99,yes,locked 2006.145.15:03:08.61/valo/02,534.99,yes,locked 2006.145.15:03:08.61/valo/03,564.99,yes,locked 2006.145.15:03:08.61/valo/04,624.99,yes,locked 2006.145.15:03:08.61/valo/05,734.99,yes,locked 2006.145.15:03:08.61/valo/06,814.99,yes,locked 2006.145.15:03:08.61/valo/07,864.99,yes,locked 2006.145.15:03:08.61/valo/08,884.99,yes,locked 2006.145.15:03:09.70/vb/01,03,usb,yes,36,33 2006.145.15:03:09.70/vb/02,04,usb,yes,31,31 2006.145.15:03:09.70/vb/03,04,usb,yes,28,31 2006.145.15:03:09.70/vb/04,04,usb,yes,32,31 2006.145.15:03:09.70/vb/05,04,usb,yes,25,28 2006.145.15:03:09.70/vb/06,04,usb,yes,30,26 2006.145.15:03:09.70/vb/07,04,usb,yes,29,29 2006.145.15:03:09.70/vb/08,04,usb,yes,27,30 2006.145.15:03:09.93/vblo/01,629.99,yes,locked 2006.145.15:03:09.93/vblo/02,634.99,yes,locked 2006.145.15:03:09.93/vblo/03,649.99,yes,locked 2006.145.15:03:09.93/vblo/04,679.99,yes,locked 2006.145.15:03:09.93/vblo/05,709.99,yes,locked 2006.145.15:03:09.93/vblo/06,719.99,yes,locked 2006.145.15:03:09.93/vblo/07,734.99,yes,locked 2006.145.15:03:09.93/vblo/08,744.99,yes,locked 2006.145.15:03:10.08/vabw/8 2006.145.15:03:10.23/vbbw/8 2006.145.15:03:10.32/xfe/off,on,15.2 2006.145.15:03:10.71/ifatt/23,28,28,28 2006.145.15:03:11.08/fmout-gps/S +4.5E-08 2006.145.15:03:11.12:!2006.145.15:06:17 2006.145.15:06:17.02:data_valid=off 2006.145.15:06:17.02:"et 2006.145.15:06:17.02:!+3s 2006.145.15:06:20.06:"tape 2006.145.15:06:20.06:postob 2006.145.15:06:20.25/cable/+6.5496E-03 2006.145.15:06:20.26/wx/15.40,1020.6,87 2006.145.15:06:20.34/fmout-gps/S +4.6E-08 2006.145.15:06:20.35:scan_name=145-1510,jd0605,90 2006.145.15:06:20.35:source=2136+141,213901.31,142336.0,2000.0,cw 2006.145.15:06:22.14#flagr#flagr/antenna,new-source 2006.145.15:06:22.14:checkk5 2006.145.15:06:22.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.15:06:23.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.15:06:23.48/chk_autoobs//k5ts3/ autoobs is running! 2006.145.15:06:23.92/chk_autoobs//k5ts4/ autoobs is running! 2006.145.15:06:24.35/chk_obsdata//k5ts1/T1451503??a.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.15:06:24.79/chk_obsdata//k5ts2/T1451503??b.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.15:06:25.24/chk_obsdata//k5ts3/T1451503??c.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.15:06:25.69/chk_obsdata//k5ts4/T1451503??d.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.15:06:26.48/k5log//k5ts1_log_newline 2006.145.15:06:27.22/k5log//k5ts2_log_newline 2006.145.15:06:27.95/k5log//k5ts3_log_newline 2006.145.15:06:28.70/k5log//k5ts4_log_newline 2006.145.15:06:28.72/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.15:06:28.72:setupk4=1 2006.145.15:06:28.72$setupk4/echo=on 2006.145.15:06:28.72$setupk4/pcalon 2006.145.15:06:28.72$pcalon/"no phase cal control is implemented here 2006.145.15:06:28.72$setupk4/"tpicd=stop 2006.145.15:06:28.72$setupk4/"rec=synch_on 2006.145.15:06:28.72$setupk4/"rec_mode=128 2006.145.15:06:28.72$setupk4/!* 2006.145.15:06:28.72$setupk4/recpk4 2006.145.15:06:28.72$recpk4/recpatch= 2006.145.15:06:28.73$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.15:06:28.73$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.15:06:28.73$setupk4/vck44 2006.145.15:06:28.73$vck44/valo=1,524.99 2006.145.15:06:28.73#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.15:06:28.73#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.15:06:28.73#ibcon#ireg 17 cls_cnt 0 2006.145.15:06:28.73#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:06:28.73#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:06:28.73#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:06:28.77#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.15:06:28.81#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:06:28.81#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:06:28.81#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.15:06:28.81#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.15:06:28.81$vck44/va=1,8 2006.145.15:06:28.82#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.15:06:28.82#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.15:06:28.82#ibcon#ireg 11 cls_cnt 2 2006.145.15:06:28.82#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.15:06:28.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.15:06:28.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.15:06:28.83#ibcon#[25=AT01-08\r\n] 2006.145.15:06:28.86#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.15:06:28.86#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.15:06:28.86#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.15:06:28.86#ibcon#ireg 7 cls_cnt 0 2006.145.15:06:28.86#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.15:06:28.98#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.15:06:28.98#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.15:06:29.00#ibcon#[25=USB\r\n] 2006.145.15:06:29.03#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.15:06:29.03#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.15:06:29.03#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.15:06:29.03#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.15:06:29.03$vck44/valo=2,534.99 2006.145.15:06:29.04#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.15:06:29.04#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.15:06:29.04#ibcon#ireg 17 cls_cnt 0 2006.145.15:06:29.04#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.15:06:29.04#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.15:06:29.04#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.15:06:29.07#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.15:06:29.10#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.15:06:29.10#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.15:06:29.10#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.15:06:29.10#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.15:06:29.10$vck44/va=2,7 2006.145.15:06:29.11#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.15:06:29.11#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.15:06:29.11#ibcon#ireg 11 cls_cnt 2 2006.145.15:06:29.11#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.15:06:29.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.15:06:29.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.15:06:29.16#ibcon#[25=AT02-07\r\n] 2006.145.15:06:29.19#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.15:06:29.19#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.15:06:29.19#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.15:06:29.19#ibcon#ireg 7 cls_cnt 0 2006.145.15:06:29.19#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.15:06:29.31#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.15:06:29.31#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.15:06:29.33#ibcon#[25=USB\r\n] 2006.145.15:06:29.36#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.15:06:29.36#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.15:06:29.36#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.15:06:29.36#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.15:06:29.36$vck44/valo=3,564.99 2006.145.15:06:29.37#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.15:06:29.37#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.15:06:29.37#ibcon#ireg 17 cls_cnt 0 2006.145.15:06:29.37#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.15:06:29.37#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.15:06:29.37#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.15:06:29.38#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.15:06:29.42#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.15:06:29.42#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.15:06:29.42#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.15:06:29.42#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.15:06:29.42$vck44/va=3,8 2006.145.15:06:29.43#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.15:06:29.43#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.15:06:29.43#ibcon#ireg 11 cls_cnt 2 2006.145.15:06:29.43#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.15:06:29.47#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.15:06:29.47#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.15:06:29.49#ibcon#[25=AT03-08\r\n] 2006.145.15:06:29.52#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.15:06:29.52#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.15:06:29.52#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.15:06:29.52#ibcon#ireg 7 cls_cnt 0 2006.145.15:06:29.52#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.15:06:29.64#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.15:06:29.64#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.15:06:29.66#ibcon#[25=USB\r\n] 2006.145.15:06:29.69#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.15:06:29.69#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.15:06:29.69#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.15:06:29.69#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.15:06:29.69$vck44/valo=4,624.99 2006.145.15:06:29.69#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.15:06:29.70#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.15:06:29.70#ibcon#ireg 17 cls_cnt 0 2006.145.15:06:29.70#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.15:06:29.70#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.15:06:29.70#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.15:06:29.71#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.15:06:29.75#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.15:06:29.75#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.15:06:29.75#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.15:06:29.75#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.15:06:29.75$vck44/va=4,7 2006.145.15:06:29.76#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.15:06:29.76#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.15:06:29.76#ibcon#ireg 11 cls_cnt 2 2006.145.15:06:29.76#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.15:06:29.80#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.15:06:29.80#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.15:06:29.82#ibcon#[25=AT04-07\r\n] 2006.145.15:06:29.85#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.15:06:29.85#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.15:06:29.85#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.15:06:29.85#ibcon#ireg 7 cls_cnt 0 2006.145.15:06:29.85#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.15:06:29.97#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.15:06:29.97#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.15:06:29.99#ibcon#[25=USB\r\n] 2006.145.15:06:30.02#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.15:06:30.02#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.15:06:30.02#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.15:06:30.02#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.15:06:30.02$vck44/valo=5,734.99 2006.145.15:06:30.03#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.15:06:30.03#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.15:06:30.03#ibcon#ireg 17 cls_cnt 0 2006.145.15:06:30.03#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.15:06:30.03#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.15:06:30.03#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.15:06:30.04#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.15:06:30.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.15:06:30.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.15:06:30.08#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.15:06:30.08#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.15:06:30.08$vck44/va=5,4 2006.145.15:06:30.09#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.15:06:30.09#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.15:06:30.09#ibcon#ireg 11 cls_cnt 2 2006.145.15:06:30.09#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.15:06:30.13#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.15:06:30.13#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.15:06:30.15#ibcon#[25=AT05-04\r\n] 2006.145.15:06:30.18#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.15:06:30.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.15:06:30.18#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.15:06:30.18#ibcon#ireg 7 cls_cnt 0 2006.145.15:06:30.18#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.15:06:30.32#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.15:06:30.32#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.15:06:30.33#ibcon#[25=USB\r\n] 2006.145.15:06:30.36#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.15:06:30.36#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.15:06:30.36#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.15:06:30.36#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.15:06:30.36$vck44/valo=6,814.99 2006.145.15:06:30.37#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.15:06:30.37#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.15:06:30.37#ibcon#ireg 17 cls_cnt 0 2006.145.15:06:30.37#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.15:06:30.37#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.15:06:30.37#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.15:06:30.40#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.15:06:30.43#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.15:06:30.43#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.15:06:30.43#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.15:06:30.43#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.15:06:30.44$vck44/va=6,4 2006.145.15:06:30.44#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.15:06:30.44#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.15:06:30.44#ibcon#ireg 11 cls_cnt 2 2006.145.15:06:30.44#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.15:06:30.47#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.15:06:30.47#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.15:06:30.49#ibcon#[25=AT06-04\r\n] 2006.145.15:06:30.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.15:06:30.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.15:06:30.52#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.15:06:30.52#ibcon#ireg 7 cls_cnt 0 2006.145.15:06:30.52#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.15:06:30.64#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.15:06:30.64#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.15:06:30.66#ibcon#[25=USB\r\n] 2006.145.15:06:30.69#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.15:06:30.69#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.15:06:30.69#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.15:06:30.69#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.15:06:30.69$vck44/valo=7,864.99 2006.145.15:06:30.70#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.15:06:30.70#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.15:06:30.70#ibcon#ireg 17 cls_cnt 0 2006.145.15:06:30.70#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.15:06:30.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.15:06:30.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.15:06:30.71#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.15:06:30.75#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.15:06:30.75#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.15:06:30.75#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.15:06:30.75#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.15:06:30.75$vck44/va=7,4 2006.145.15:06:30.76#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.15:06:30.76#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.15:06:30.76#ibcon#ireg 11 cls_cnt 2 2006.145.15:06:30.76#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.15:06:30.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.15:06:30.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.15:06:30.82#ibcon#[25=AT07-04\r\n] 2006.145.15:06:30.85#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.15:06:30.85#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.15:06:30.85#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.15:06:30.85#ibcon#ireg 7 cls_cnt 0 2006.145.15:06:30.85#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.15:06:30.97#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.15:06:30.97#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.15:06:30.99#ibcon#[25=USB\r\n] 2006.145.15:06:31.02#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.15:06:31.02#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.15:06:31.02#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.15:06:31.02#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.15:06:31.02$vck44/valo=8,884.99 2006.145.15:06:31.03#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.15:06:31.03#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.15:06:31.03#ibcon#ireg 17 cls_cnt 0 2006.145.15:06:31.03#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.15:06:31.03#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.15:06:31.03#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.15:06:31.04#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.15:06:31.08#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.15:06:31.08#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.15:06:31.08#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.15:06:31.08#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.15:06:31.08$vck44/va=8,4 2006.145.15:06:31.09#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.15:06:31.09#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.15:06:31.09#ibcon#ireg 11 cls_cnt 2 2006.145.15:06:31.09#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.15:06:31.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.15:06:31.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.15:06:31.15#ibcon#[25=AT08-04\r\n] 2006.145.15:06:31.18#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.15:06:31.18#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.15:06:31.18#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.15:06:31.18#ibcon#ireg 7 cls_cnt 0 2006.145.15:06:31.18#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.15:06:31.30#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.15:06:31.30#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.15:06:31.32#ibcon#[25=USB\r\n] 2006.145.15:06:31.35#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.15:06:31.35#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.15:06:31.35#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.15:06:31.35#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.15:06:31.35$vck44/vblo=1,629.99 2006.145.15:06:31.36#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.15:06:31.36#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.15:06:31.36#ibcon#ireg 17 cls_cnt 0 2006.145.15:06:31.36#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.15:06:31.36#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.15:06:31.36#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.15:06:31.37#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.15:06:31.41#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.15:06:31.41#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.15:06:31.41#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.15:06:31.41#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.15:06:31.41$vck44/vb=1,3 2006.145.15:06:31.42#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.15:06:31.42#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.15:06:31.42#ibcon#ireg 11 cls_cnt 2 2006.145.15:06:31.42#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.15:06:31.42#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.15:06:31.42#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.15:06:31.46#ibcon#[27=AT01-03\r\n] 2006.145.15:06:31.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.15:06:31.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.15:06:31.49#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.15:06:31.49#ibcon#ireg 7 cls_cnt 0 2006.145.15:06:31.49#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.15:06:31.61#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.15:06:31.61#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.15:06:31.63#ibcon#[27=USB\r\n] 2006.145.15:06:31.66#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.15:06:31.66#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.15:06:31.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.15:06:31.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.15:06:31.66$vck44/vblo=2,634.99 2006.145.15:06:31.67#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.15:06:31.67#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.15:06:31.67#ibcon#ireg 17 cls_cnt 0 2006.145.15:06:31.67#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:06:31.67#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:06:31.67#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:06:31.68#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.15:06:31.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:06:31.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:06:31.72#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.15:06:31.72#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.15:06:31.72$vck44/vb=2,4 2006.145.15:06:31.73#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.15:06:31.73#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.15:06:31.73#ibcon#ireg 11 cls_cnt 2 2006.145.15:06:31.73#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.15:06:31.77#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.15:06:31.77#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.15:06:31.79#ibcon#[27=AT02-04\r\n] 2006.145.15:06:31.82#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.15:06:31.82#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.15:06:31.82#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.15:06:31.82#ibcon#ireg 7 cls_cnt 0 2006.145.15:06:31.82#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.15:06:31.94#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.15:06:31.94#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.15:06:31.96#ibcon#[27=USB\r\n] 2006.145.15:06:31.99#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.15:06:31.99#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.15:06:31.99#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.15:06:31.99#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.15:06:31.99$vck44/vblo=3,649.99 2006.145.15:06:32.00#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.15:06:32.00#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.15:06:32.00#ibcon#ireg 17 cls_cnt 0 2006.145.15:06:32.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.15:06:32.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.15:06:32.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.15:06:32.01#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.15:06:32.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.15:06:32.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.15:06:32.05#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.15:06:32.05#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.15:06:32.05$vck44/vb=3,4 2006.145.15:06:32.06#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.15:06:32.06#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.15:06:32.06#ibcon#ireg 11 cls_cnt 2 2006.145.15:06:32.06#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.15:06:32.10#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.15:06:32.10#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.15:06:32.12#ibcon#[27=AT03-04\r\n] 2006.145.15:06:32.15#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.15:06:32.15#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.15:06:32.15#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.15:06:32.15#ibcon#ireg 7 cls_cnt 0 2006.145.15:06:32.15#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.15:06:32.27#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.15:06:32.27#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.15:06:32.29#ibcon#[27=USB\r\n] 2006.145.15:06:32.32#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.15:06:32.32#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.15:06:32.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.15:06:32.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.15:06:32.33$vck44/vblo=4,679.99 2006.145.15:06:32.33#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.15:06:32.33#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.15:06:32.33#ibcon#ireg 17 cls_cnt 0 2006.145.15:06:32.33#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.15:06:32.33#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.15:06:32.33#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.15:06:32.34#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.15:06:32.38#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.15:06:32.38#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.15:06:32.38#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.15:06:32.38#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.15:06:32.39$vck44/vb=4,4 2006.145.15:06:32.39#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.15:06:32.39#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.15:06:32.39#ibcon#ireg 11 cls_cnt 2 2006.145.15:06:32.39#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.15:06:32.43#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.15:06:32.43#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.15:06:32.45#ibcon#[27=AT04-04\r\n] 2006.145.15:06:32.48#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.15:06:32.48#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.15:06:32.48#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.15:06:32.48#ibcon#ireg 7 cls_cnt 0 2006.145.15:06:32.48#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.15:06:32.60#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.15:06:32.60#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.15:06:32.62#ibcon#[27=USB\r\n] 2006.145.15:06:32.65#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.15:06:32.65#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.15:06:32.65#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.15:06:32.65#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.15:06:32.65$vck44/vblo=5,709.99 2006.145.15:06:32.66#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.15:06:32.66#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.15:06:32.66#ibcon#ireg 17 cls_cnt 0 2006.145.15:06:32.66#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.15:06:32.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.15:06:32.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.15:06:32.67#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.15:06:32.71#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.15:06:32.71#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.15:06:32.71#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.15:06:32.71#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.15:06:32.71$vck44/vb=5,4 2006.145.15:06:32.72#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.15:06:32.72#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.15:06:32.72#ibcon#ireg 11 cls_cnt 2 2006.145.15:06:32.72#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.15:06:32.76#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.15:06:32.76#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.15:06:32.78#ibcon#[27=AT05-04\r\n] 2006.145.15:06:32.81#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.15:06:32.81#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.15:06:32.81#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.15:06:32.81#ibcon#ireg 7 cls_cnt 0 2006.145.15:06:32.81#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.15:06:32.93#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.15:06:32.93#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.15:06:32.95#ibcon#[27=USB\r\n] 2006.145.15:06:32.98#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.15:06:32.98#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.15:06:32.98#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.15:06:32.98#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.15:06:32.98$vck44/vblo=6,719.99 2006.145.15:06:32.99#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.15:06:32.99#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.15:06:32.99#ibcon#ireg 17 cls_cnt 0 2006.145.15:06:32.99#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.15:06:32.99#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.15:06:32.99#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.15:06:33.00#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.15:06:33.04#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.15:06:33.04#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.15:06:33.04#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.15:06:33.04#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.15:06:33.05$vck44/vb=6,4 2006.145.15:06:33.05#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.15:06:33.05#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.15:06:33.05#ibcon#ireg 11 cls_cnt 2 2006.145.15:06:33.05#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.15:06:33.09#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.15:06:33.09#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.15:06:33.11#ibcon#[27=AT06-04\r\n] 2006.145.15:06:33.14#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.15:06:33.14#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.15:06:33.14#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.15:06:33.14#ibcon#ireg 7 cls_cnt 0 2006.145.15:06:33.14#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.15:06:33.26#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.15:06:33.26#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.15:06:33.28#ibcon#[27=USB\r\n] 2006.145.15:06:33.31#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.15:06:33.31#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.15:06:33.31#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.15:06:33.31#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.15:06:33.31$vck44/vblo=7,734.99 2006.145.15:06:33.32#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.15:06:33.32#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.15:06:33.32#ibcon#ireg 17 cls_cnt 0 2006.145.15:06:33.32#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.15:06:33.32#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.15:06:33.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.15:06:33.33#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.15:06:33.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.15:06:33.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.15:06:33.37#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.15:06:33.37#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.15:06:33.37$vck44/vb=7,4 2006.145.15:06:33.38#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.15:06:33.38#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.15:06:33.38#ibcon#ireg 11 cls_cnt 2 2006.145.15:06:33.38#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.15:06:33.42#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.15:06:33.42#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.15:06:33.44#ibcon#[27=AT07-04\r\n] 2006.145.15:06:33.47#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.15:06:33.47#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.15:06:33.47#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.15:06:33.47#ibcon#ireg 7 cls_cnt 0 2006.145.15:06:33.47#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.15:06:33.59#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.15:06:33.59#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.15:06:33.61#ibcon#[27=USB\r\n] 2006.145.15:06:33.64#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.15:06:33.64#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.15:06:33.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.15:06:33.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.15:06:33.64$vck44/vblo=8,744.99 2006.145.15:06:33.65#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.15:06:33.65#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.15:06:33.65#ibcon#ireg 17 cls_cnt 0 2006.145.15:06:33.65#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.15:06:33.65#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.15:06:33.65#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.15:06:33.66#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.15:06:33.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.15:06:33.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.15:06:33.70#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.15:06:33.70#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.15:06:33.70$vck44/vb=8,4 2006.145.15:06:33.71#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.15:06:33.71#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.15:06:33.71#ibcon#ireg 11 cls_cnt 2 2006.145.15:06:33.71#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.15:06:33.75#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.15:06:33.75#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.15:06:33.77#ibcon#[27=AT08-04\r\n] 2006.145.15:06:33.80#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.15:06:33.80#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.15:06:33.80#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.15:06:33.80#ibcon#ireg 7 cls_cnt 0 2006.145.15:06:33.80#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.15:06:33.92#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.15:06:33.92#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.15:06:33.94#ibcon#[27=USB\r\n] 2006.145.15:06:33.97#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.15:06:33.97#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.15:06:33.97#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.15:06:33.97#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.15:06:33.97$vck44/vabw=wide 2006.145.15:06:33.98#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.15:06:33.98#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.15:06:33.98#ibcon#ireg 8 cls_cnt 0 2006.145.15:06:33.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.15:06:33.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.15:06:33.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.15:06:33.99#ibcon#[25=BW32\r\n] 2006.145.15:06:34.02#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.15:06:34.02#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.15:06:34.02#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.15:06:34.02#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.15:06:34.03$vck44/vbbw=wide 2006.145.15:06:34.03#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.15:06:34.03#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.15:06:34.03#ibcon#ireg 8 cls_cnt 0 2006.145.15:06:34.03#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.15:06:34.08#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.15:06:34.08#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.15:06:34.10#ibcon#[27=BW32\r\n] 2006.145.15:06:34.13#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.15:06:34.13#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.15:06:34.13#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.15:06:34.13#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.15:06:34.14$setupk4/ifdk4 2006.145.15:06:34.14$ifdk4/lo= 2006.145.15:06:34.14$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.15:06:34.14$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.15:06:34.14$ifdk4/patch= 2006.145.15:06:34.14$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.15:06:34.14$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.15:06:34.14$setupk4/!*+20s 2006.145.15:06:36.92#abcon#<5=/07 1.0 1.9 15.41 871020.6\r\n> 2006.145.15:06:36.94#abcon#{5=INTERFACE CLEAR} 2006.145.15:06:37.00#abcon#[5=S1D000X0/0*\r\n] 2006.145.15:06:47.09#abcon#<5=/07 1.0 1.9 15.41 871020.6\r\n> 2006.145.15:06:47.11#abcon#{5=INTERFACE CLEAR} 2006.145.15:06:47.17#abcon#[5=S1D000X0/0*\r\n] 2006.145.15:06:48.74$setupk4/"tpicd 2006.145.15:06:48.74$setupk4/echo=off 2006.145.15:06:48.74$setupk4/xlog=off 2006.145.15:06:48.75:!2006.145.15:10:22 2006.145.15:07:49.14#trakl#Source acquired 2006.145.15:07:50.14#flagr#flagr/antenna,acquired 2006.145.15:10:22.01:preob 2006.145.15:10:23.14/onsource/TRACKING 2006.145.15:10:23.14:!2006.145.15:10:32 2006.145.15:10:32.00:"tape 2006.145.15:10:32.00:"st=record 2006.145.15:10:32.00:data_valid=on 2006.145.15:10:32.00:midob 2006.145.15:10:32.14/onsource/TRACKING 2006.145.15:10:32.14/wx/15.44,1020.6,87 2006.145.15:10:32.24/cable/+6.5482E-03 2006.145.15:10:33.33/va/01,08,usb,yes,30,32 2006.145.15:10:33.33/va/02,07,usb,yes,32,33 2006.145.15:10:33.33/va/03,08,usb,yes,29,30 2006.145.15:10:33.33/va/04,07,usb,yes,33,35 2006.145.15:10:33.33/va/05,04,usb,yes,29,29 2006.145.15:10:33.33/va/06,04,usb,yes,32,32 2006.145.15:10:33.33/va/07,04,usb,yes,33,34 2006.145.15:10:33.33/va/08,04,usb,yes,28,33 2006.145.15:10:33.56/valo/01,524.99,yes,locked 2006.145.15:10:33.56/valo/02,534.99,yes,locked 2006.145.15:10:33.56/valo/03,564.99,yes,locked 2006.145.15:10:33.56/valo/04,624.99,yes,locked 2006.145.15:10:33.56/valo/05,734.99,yes,locked 2006.145.15:10:33.56/valo/06,814.99,yes,locked 2006.145.15:10:33.56/valo/07,864.99,yes,locked 2006.145.15:10:33.56/valo/08,884.99,yes,locked 2006.145.15:10:34.65/vb/01,03,usb,yes,37,34 2006.145.15:10:34.65/vb/02,04,usb,yes,32,32 2006.145.15:10:34.65/vb/03,04,usb,yes,29,32 2006.145.15:10:34.65/vb/04,04,usb,yes,33,32 2006.145.15:10:34.65/vb/05,04,usb,yes,26,28 2006.145.15:10:34.65/vb/06,04,usb,yes,31,27 2006.145.15:10:34.65/vb/07,04,usb,yes,30,30 2006.145.15:10:34.65/vb/08,04,usb,yes,28,31 2006.145.15:10:34.89/vblo/01,629.99,yes,locked 2006.145.15:10:34.89/vblo/02,634.99,yes,locked 2006.145.15:10:34.89/vblo/03,649.99,yes,locked 2006.145.15:10:34.89/vblo/04,679.99,yes,locked 2006.145.15:10:34.89/vblo/05,709.99,yes,locked 2006.145.15:10:34.89/vblo/06,719.99,yes,locked 2006.145.15:10:34.89/vblo/07,734.99,yes,locked 2006.145.15:10:34.89/vblo/08,744.99,yes,locked 2006.145.15:10:35.04/vabw/8 2006.145.15:10:35.19/vbbw/8 2006.145.15:10:35.28/xfe/off,on,15.2 2006.145.15:10:35.66/ifatt/23,28,28,28 2006.145.15:10:36.07/fmout-gps/S +4.5E-08 2006.145.15:10:36.12:!2006.145.15:12:02 2006.145.15:12:02.01:data_valid=off 2006.145.15:12:02.02:"et 2006.145.15:12:02.02:!+3s 2006.145.15:12:05.05:"tape 2006.145.15:12:05.06:postob 2006.145.15:12:05.14/cable/+6.5514E-03 2006.145.15:12:05.15/wx/15.45,1020.5,87 2006.145.15:12:05.22/fmout-gps/S +4.5E-08 2006.145.15:12:05.23:scan_name=145-1517,jd0605,510 2006.145.15:12:05.23:source=0059+581,010245.76,582411.1,2000.0,cw 2006.145.15:12:07.14#flagr#flagr/antenna,new-source 2006.145.15:12:07.15:checkk5 2006.145.15:12:07.62/chk_autoobs//k5ts1/ autoobs is running! 2006.145.15:12:08.05/chk_autoobs//k5ts2/ autoobs is running! 2006.145.15:12:08.49/chk_autoobs//k5ts3/ autoobs is running! 2006.145.15:12:08.92/chk_autoobs//k5ts4/ autoobs is running! 2006.145.15:12:09.34/chk_obsdata//k5ts1/T1451510??a.dat file size is correct (nominal:360MB, actual:360MB). 2006.145.15:12:09.77/chk_obsdata//k5ts2/T1451510??b.dat file size is correct (nominal:360MB, actual:360MB). 2006.145.15:12:10.22/chk_obsdata//k5ts3/T1451510??c.dat file size is correct (nominal:360MB, actual:360MB). 2006.145.15:12:10.66/chk_obsdata//k5ts4/T1451510??d.dat file size is correct (nominal:360MB, actual:360MB). 2006.145.15:12:11.42/k5log//k5ts1_log_newline 2006.145.15:12:12.18/k5log//k5ts2_log_newline 2006.145.15:12:12.94/k5log//k5ts3_log_newline 2006.145.15:12:13.69/k5log//k5ts4_log_newline 2006.145.15:12:13.71/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.15:12:13.71:setupk4=1 2006.145.15:12:13.71$setupk4/echo=on 2006.145.15:12:13.71$setupk4/pcalon 2006.145.15:12:13.71$pcalon/"no phase cal control is implemented here 2006.145.15:12:13.71$setupk4/"tpicd=stop 2006.145.15:12:13.71$setupk4/"rec=synch_on 2006.145.15:12:13.71$setupk4/"rec_mode=128 2006.145.15:12:13.71$setupk4/!* 2006.145.15:12:13.71$setupk4/recpk4 2006.145.15:12:13.71$recpk4/recpatch= 2006.145.15:12:13.72$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.15:12:13.72$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.15:12:13.72$setupk4/vck44 2006.145.15:12:13.72$vck44/valo=1,524.99 2006.145.15:12:13.72#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.15:12:13.72#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.15:12:13.72#ibcon#ireg 17 cls_cnt 0 2006.145.15:12:13.72#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.15:12:13.72#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.15:12:13.72#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.15:12:13.76#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.15:12:13.80#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.15:12:13.80#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.15:12:13.80#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.15:12:13.80#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.15:12:13.80$vck44/va=1,8 2006.145.15:12:13.80#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.15:12:13.80#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.15:12:13.80#ibcon#ireg 11 cls_cnt 2 2006.145.15:12:13.80#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.15:12:13.80#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.15:12:13.80#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.15:12:13.82#ibcon#[25=AT01-08\r\n] 2006.145.15:12:13.85#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.15:12:13.85#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.15:12:13.85#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.15:12:13.85#ibcon#ireg 7 cls_cnt 0 2006.145.15:12:13.85#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.15:12:13.97#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.15:12:13.97#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.15:12:13.99#ibcon#[25=USB\r\n] 2006.145.15:12:14.04#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.15:12:14.04#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.15:12:14.04#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.15:12:14.04#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.15:12:14.04$vck44/valo=2,534.99 2006.145.15:12:14.04#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.15:12:14.04#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.15:12:14.04#ibcon#ireg 17 cls_cnt 0 2006.145.15:12:14.04#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.15:12:14.04#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.15:12:14.04#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.15:12:14.05#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.15:12:14.09#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.15:12:14.09#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.15:12:14.09#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.15:12:14.09#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.15:12:14.09$vck44/va=2,7 2006.145.15:12:14.09#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.15:12:14.09#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.15:12:14.09#ibcon#ireg 11 cls_cnt 2 2006.145.15:12:14.09#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.15:12:14.16#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.15:12:14.16#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.15:12:14.18#ibcon#[25=AT02-07\r\n] 2006.145.15:12:14.21#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.15:12:14.21#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.15:12:14.21#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.15:12:14.21#ibcon#ireg 7 cls_cnt 0 2006.145.15:12:14.21#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.15:12:14.33#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.15:12:14.33#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.15:12:14.35#ibcon#[25=USB\r\n] 2006.145.15:12:14.38#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.15:12:14.38#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.15:12:14.38#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.15:12:14.38#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.15:12:14.38$vck44/valo=3,564.99 2006.145.15:12:14.38#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.15:12:14.38#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.15:12:14.38#ibcon#ireg 17 cls_cnt 0 2006.145.15:12:14.38#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.15:12:14.38#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.15:12:14.38#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.15:12:14.40#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.15:12:14.44#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.15:12:14.44#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.15:12:14.44#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.15:12:14.44#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.15:12:14.44$vck44/va=3,8 2006.145.15:12:14.44#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.15:12:14.44#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.15:12:14.44#ibcon#ireg 11 cls_cnt 2 2006.145.15:12:14.44#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.15:12:14.50#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.15:12:14.50#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.15:12:14.52#ibcon#[25=AT03-08\r\n] 2006.145.15:12:14.55#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.15:12:14.55#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.15:12:14.55#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.15:12:14.55#ibcon#ireg 7 cls_cnt 0 2006.145.15:12:14.55#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.15:12:14.67#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.15:12:14.67#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.15:12:14.69#ibcon#[25=USB\r\n] 2006.145.15:12:14.72#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.15:12:14.72#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.15:12:14.72#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.15:12:14.72#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.15:12:14.72$vck44/valo=4,624.99 2006.145.15:12:14.72#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.15:12:14.72#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.15:12:14.72#ibcon#ireg 17 cls_cnt 0 2006.145.15:12:14.72#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.15:12:14.72#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.15:12:14.72#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.15:12:14.74#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.15:12:14.78#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.15:12:14.78#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.15:12:14.78#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.15:12:14.78#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.15:12:14.78$vck44/va=4,7 2006.145.15:12:14.78#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.15:12:14.78#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.15:12:14.78#ibcon#ireg 11 cls_cnt 2 2006.145.15:12:14.78#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.15:12:14.84#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.15:12:14.84#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.15:12:14.86#ibcon#[25=AT04-07\r\n] 2006.145.15:12:14.89#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.15:12:14.89#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.15:12:14.89#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.15:12:14.89#ibcon#ireg 7 cls_cnt 0 2006.145.15:12:14.89#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.15:12:15.01#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.15:12:15.01#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.15:12:15.03#ibcon#[25=USB\r\n] 2006.145.15:12:15.06#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.15:12:15.06#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.15:12:15.06#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.15:12:15.06#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.15:12:15.06$vck44/valo=5,734.99 2006.145.15:12:15.06#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.15:12:15.06#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.15:12:15.06#ibcon#ireg 17 cls_cnt 0 2006.145.15:12:15.06#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.15:12:15.06#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.15:12:15.06#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.15:12:15.08#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.15:12:15.12#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.15:12:15.12#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.15:12:15.12#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.15:12:15.12#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.15:12:15.12$vck44/va=5,4 2006.145.15:12:15.12#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.15:12:15.12#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.15:12:15.12#ibcon#ireg 11 cls_cnt 2 2006.145.15:12:15.12#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.15:12:15.21#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.15:12:15.21#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.15:12:15.22#ibcon#[25=AT05-04\r\n] 2006.145.15:12:15.25#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.15:12:15.25#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.15:12:15.25#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.15:12:15.25#ibcon#ireg 7 cls_cnt 0 2006.145.15:12:15.25#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.15:12:15.38#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.15:12:15.38#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.15:12:15.39#ibcon#[25=USB\r\n] 2006.145.15:12:15.42#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.15:12:15.42#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.15:12:15.42#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.15:12:15.42#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.15:12:15.42$vck44/valo=6,814.99 2006.145.15:12:15.42#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.15:12:15.42#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.15:12:15.42#ibcon#ireg 17 cls_cnt 0 2006.145.15:12:15.42#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.15:12:15.42#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.15:12:15.42#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.15:12:15.45#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.15:12:15.49#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.15:12:15.49#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.15:12:15.49#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.15:12:15.49#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.15:12:15.49$vck44/va=6,4 2006.145.15:12:15.49#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.15:12:15.49#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.15:12:15.49#ibcon#ireg 11 cls_cnt 2 2006.145.15:12:15.49#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.15:12:15.54#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.15:12:15.54#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.15:12:15.56#ibcon#[25=AT06-04\r\n] 2006.145.15:12:15.59#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.15:12:15.59#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.15:12:15.59#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.15:12:15.59#ibcon#ireg 7 cls_cnt 0 2006.145.15:12:15.59#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.15:12:15.71#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.15:12:15.71#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.15:12:15.73#ibcon#[25=USB\r\n] 2006.145.15:12:15.76#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.15:12:15.76#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.15:12:15.76#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.15:12:15.76#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.15:12:15.76$vck44/valo=7,864.99 2006.145.15:12:15.76#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.15:12:15.76#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.15:12:15.76#ibcon#ireg 17 cls_cnt 0 2006.145.15:12:15.76#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.15:12:15.76#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.15:12:15.76#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.15:12:15.78#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.15:12:15.82#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.15:12:15.82#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.15:12:15.82#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.15:12:15.82#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.15:12:15.82$vck44/va=7,4 2006.145.15:12:15.82#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.15:12:15.82#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.15:12:15.82#ibcon#ireg 11 cls_cnt 2 2006.145.15:12:15.82#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.15:12:15.88#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.15:12:15.88#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.15:12:15.90#ibcon#[25=AT07-04\r\n] 2006.145.15:12:15.93#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.15:12:15.93#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.15:12:15.93#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.15:12:15.93#ibcon#ireg 7 cls_cnt 0 2006.145.15:12:15.93#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.15:12:16.05#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.15:12:16.05#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.15:12:16.07#ibcon#[25=USB\r\n] 2006.145.15:12:16.10#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.15:12:16.10#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.15:12:16.10#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.15:12:16.10#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.15:12:16.10$vck44/valo=8,884.99 2006.145.15:12:16.10#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.15:12:16.10#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.15:12:16.10#ibcon#ireg 17 cls_cnt 0 2006.145.15:12:16.10#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.15:12:16.10#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.15:12:16.10#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.15:12:16.12#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.15:12:16.16#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.15:12:16.16#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.15:12:16.16#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.15:12:16.16#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.15:12:16.16$vck44/va=8,4 2006.145.15:12:16.16#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.15:12:16.16#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.15:12:16.16#ibcon#ireg 11 cls_cnt 2 2006.145.15:12:16.16#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.15:12:16.22#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.15:12:16.22#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.15:12:16.24#ibcon#[25=AT08-04\r\n] 2006.145.15:12:16.27#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.15:12:16.27#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.15:12:16.27#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.15:12:16.27#ibcon#ireg 7 cls_cnt 0 2006.145.15:12:16.27#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.15:12:16.39#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.15:12:16.39#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.15:12:16.41#ibcon#[25=USB\r\n] 2006.145.15:12:16.44#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.15:12:16.44#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.15:12:16.44#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.15:12:16.44#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.15:12:16.44$vck44/vblo=1,629.99 2006.145.15:12:16.44#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.15:12:16.44#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.15:12:16.44#ibcon#ireg 17 cls_cnt 0 2006.145.15:12:16.44#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.15:12:16.44#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.15:12:16.44#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.15:12:16.46#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.15:12:16.50#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.15:12:16.50#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.15:12:16.50#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.15:12:16.50#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.15:12:16.50$vck44/vb=1,3 2006.145.15:12:16.50#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.15:12:16.50#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.15:12:16.50#ibcon#ireg 11 cls_cnt 2 2006.145.15:12:16.50#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.15:12:16.50#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.15:12:16.50#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.15:12:16.52#ibcon#[27=AT01-03\r\n] 2006.145.15:12:16.55#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.15:12:16.55#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.15:12:16.55#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.15:12:16.55#ibcon#ireg 7 cls_cnt 0 2006.145.15:12:16.55#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.15:12:16.67#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.15:12:16.67#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.15:12:16.69#ibcon#[27=USB\r\n] 2006.145.15:12:16.72#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.15:12:16.72#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.15:12:16.72#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.15:12:16.72#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.15:12:16.72$vck44/vblo=2,634.99 2006.145.15:12:16.72#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.15:12:16.72#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.15:12:16.72#ibcon#ireg 17 cls_cnt 0 2006.145.15:12:16.72#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.15:12:16.72#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.15:12:16.72#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.15:12:16.74#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.15:12:16.78#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.15:12:16.78#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.15:12:16.78#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.15:12:16.78#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.15:12:16.78$vck44/vb=2,4 2006.145.15:12:16.78#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.15:12:16.78#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.15:12:16.78#ibcon#ireg 11 cls_cnt 2 2006.145.15:12:16.78#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.15:12:16.84#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.15:12:16.84#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.15:12:16.86#ibcon#[27=AT02-04\r\n] 2006.145.15:12:16.89#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.15:12:16.89#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.15:12:16.89#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.15:12:16.89#ibcon#ireg 7 cls_cnt 0 2006.145.15:12:16.89#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.15:12:17.01#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.15:12:17.01#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.15:12:17.03#ibcon#[27=USB\r\n] 2006.145.15:12:17.06#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.15:12:17.06#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.15:12:17.06#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.15:12:17.06#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.15:12:17.06$vck44/vblo=3,649.99 2006.145.15:12:17.06#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.15:12:17.06#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.15:12:17.06#ibcon#ireg 17 cls_cnt 0 2006.145.15:12:17.06#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.15:12:17.06#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.15:12:17.06#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.15:12:17.08#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.15:12:17.12#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.15:12:17.12#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.15:12:17.12#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.15:12:17.12#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.15:12:17.12$vck44/vb=3,4 2006.145.15:12:17.12#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.15:12:17.12#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.15:12:17.12#ibcon#ireg 11 cls_cnt 2 2006.145.15:12:17.12#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.15:12:17.18#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.15:12:17.18#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.15:12:17.20#ibcon#[27=AT03-04\r\n] 2006.145.15:12:17.23#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.15:12:17.23#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.15:12:17.23#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.15:12:17.23#ibcon#ireg 7 cls_cnt 0 2006.145.15:12:17.23#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.15:12:17.35#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.15:12:17.35#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.15:12:17.37#ibcon#[27=USB\r\n] 2006.145.15:12:17.40#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.15:12:17.40#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.15:12:17.40#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.15:12:17.40#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.15:12:17.40$vck44/vblo=4,679.99 2006.145.15:12:17.40#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.15:12:17.40#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.15:12:17.40#ibcon#ireg 17 cls_cnt 0 2006.145.15:12:17.40#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.15:12:17.40#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.15:12:17.40#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.15:12:17.42#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.15:12:17.46#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.15:12:17.46#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.15:12:17.46#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.15:12:17.46#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.15:12:17.46$vck44/vb=4,4 2006.145.15:12:17.46#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.15:12:17.46#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.15:12:17.46#ibcon#ireg 11 cls_cnt 2 2006.145.15:12:17.46#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.15:12:17.52#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.15:12:17.52#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.15:12:17.54#ibcon#[27=AT04-04\r\n] 2006.145.15:12:17.57#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.15:12:17.57#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.15:12:17.57#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.15:12:17.57#ibcon#ireg 7 cls_cnt 0 2006.145.15:12:17.57#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.15:12:17.69#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.15:12:17.69#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.15:12:17.71#ibcon#[27=USB\r\n] 2006.145.15:12:17.74#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.15:12:17.74#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.15:12:17.74#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.15:12:17.74#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.15:12:17.74$vck44/vblo=5,709.99 2006.145.15:12:17.74#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.15:12:17.74#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.15:12:17.74#ibcon#ireg 17 cls_cnt 0 2006.145.15:12:17.74#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.15:12:17.74#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.15:12:17.74#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.15:12:17.76#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.15:12:17.80#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.15:12:17.80#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.15:12:17.80#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.15:12:17.80#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.15:12:17.80$vck44/vb=5,4 2006.145.15:12:17.80#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.15:12:17.80#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.15:12:17.80#ibcon#ireg 11 cls_cnt 2 2006.145.15:12:17.80#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.15:12:17.86#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.15:12:17.86#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.15:12:17.88#ibcon#[27=AT05-04\r\n] 2006.145.15:12:17.91#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.15:12:17.91#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.15:12:17.91#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.15:12:17.91#ibcon#ireg 7 cls_cnt 0 2006.145.15:12:17.91#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.15:12:18.03#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.15:12:18.03#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.15:12:18.05#ibcon#[27=USB\r\n] 2006.145.15:12:18.08#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.15:12:18.08#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.15:12:18.08#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.15:12:18.08#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.15:12:18.08$vck44/vblo=6,719.99 2006.145.15:12:18.08#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.15:12:18.08#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.15:12:18.08#ibcon#ireg 17 cls_cnt 0 2006.145.15:12:18.08#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.15:12:18.08#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.15:12:18.08#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.15:12:18.10#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.15:12:18.14#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.15:12:18.14#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.15:12:18.14#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.15:12:18.14#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.15:12:18.14$vck44/vb=6,4 2006.145.15:12:18.14#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.15:12:18.14#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.15:12:18.14#ibcon#ireg 11 cls_cnt 2 2006.145.15:12:18.14#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.15:12:18.20#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.15:12:18.20#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.15:12:18.22#ibcon#[27=AT06-04\r\n] 2006.145.15:12:18.25#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.15:12:18.25#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.15:12:18.25#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.15:12:18.25#ibcon#ireg 7 cls_cnt 0 2006.145.15:12:18.25#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.15:12:18.37#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.15:12:18.37#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.15:12:18.39#ibcon#[27=USB\r\n] 2006.145.15:12:18.42#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.15:12:18.42#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.15:12:18.42#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.15:12:18.42#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.15:12:18.42$vck44/vblo=7,734.99 2006.145.15:12:18.42#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.15:12:18.42#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.15:12:18.42#ibcon#ireg 17 cls_cnt 0 2006.145.15:12:18.42#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.15:12:18.42#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.15:12:18.42#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.15:12:18.44#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.15:12:18.48#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.15:12:18.48#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.15:12:18.48#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.15:12:18.48#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.15:12:18.48$vck44/vb=7,4 2006.145.15:12:18.48#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.15:12:18.48#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.15:12:18.48#ibcon#ireg 11 cls_cnt 2 2006.145.15:12:18.48#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.15:12:18.54#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.15:12:18.54#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.15:12:18.56#ibcon#[27=AT07-04\r\n] 2006.145.15:12:18.59#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.15:12:18.59#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.15:12:18.59#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.15:12:18.59#ibcon#ireg 7 cls_cnt 0 2006.145.15:12:18.59#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.15:12:18.71#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.15:12:18.71#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.15:12:18.73#ibcon#[27=USB\r\n] 2006.145.15:12:18.76#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.15:12:18.76#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.15:12:18.76#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.15:12:18.76#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.15:12:18.76$vck44/vblo=8,744.99 2006.145.15:12:18.76#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.15:12:18.76#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.15:12:18.76#ibcon#ireg 17 cls_cnt 0 2006.145.15:12:18.76#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.15:12:18.76#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.15:12:18.76#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.15:12:18.78#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.15:12:18.82#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.15:12:18.82#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.15:12:18.82#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.15:12:18.82#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.15:12:18.82$vck44/vb=8,4 2006.145.15:12:18.82#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.15:12:18.82#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.15:12:18.82#ibcon#ireg 11 cls_cnt 2 2006.145.15:12:18.82#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.15:12:18.88#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.15:12:18.88#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.15:12:18.90#ibcon#[27=AT08-04\r\n] 2006.145.15:12:18.93#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.15:12:18.93#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.15:12:18.93#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.15:12:18.93#ibcon#ireg 7 cls_cnt 0 2006.145.15:12:18.93#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.15:12:19.05#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.15:12:19.05#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.15:12:19.07#ibcon#[27=USB\r\n] 2006.145.15:12:19.10#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.15:12:19.10#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.15:12:19.10#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.15:12:19.10#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.15:12:19.10$vck44/vabw=wide 2006.145.15:12:19.10#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.15:12:19.10#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.15:12:19.10#ibcon#ireg 8 cls_cnt 0 2006.145.15:12:19.10#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.15:12:19.10#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.15:12:19.10#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.15:12:19.12#ibcon#[25=BW32\r\n] 2006.145.15:12:19.15#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.15:12:19.15#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.15:12:19.15#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.15:12:19.15#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.15:12:19.15$vck44/vbbw=wide 2006.145.15:12:19.15#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.15:12:19.15#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.15:12:19.15#ibcon#ireg 8 cls_cnt 0 2006.145.15:12:19.15#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.15:12:19.22#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.15:12:19.22#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.15:12:19.24#ibcon#[27=BW32\r\n] 2006.145.15:12:19.27#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.15:12:19.27#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.15:12:19.27#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.15:12:19.27#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.15:12:19.27$setupk4/ifdk4 2006.145.15:12:19.27$ifdk4/lo= 2006.145.15:12:19.27$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.15:12:19.27$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.15:12:19.27$ifdk4/patch= 2006.145.15:12:19.27$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.15:12:19.27$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.15:12:19.27$setupk4/!*+20s 2006.145.15:12:22.85#abcon#<5=/07 0.8 1.6 15.45 871020.5\r\n> 2006.145.15:12:22.87#abcon#{5=INTERFACE CLEAR} 2006.145.15:12:22.93#abcon#[5=S1D000X0/0*\r\n] 2006.145.15:12:33.02#abcon#<5=/07 0.8 1.6 15.45 871020.5\r\n> 2006.145.15:12:33.04#abcon#{5=INTERFACE CLEAR} 2006.145.15:12:33.10#abcon#[5=S1D000X0/0*\r\n] 2006.145.15:12:33.72$setupk4/"tpicd 2006.145.15:12:33.72$setupk4/echo=off 2006.145.15:12:33.72$setupk4/xlog=off 2006.145.15:12:33.72:!2006.145.15:17:48 2006.145.15:12:36.14#trakl#Source acquired 2006.145.15:12:38.14#flagr#flagr/antenna,acquired 2006.145.15:17:48.00:preob 2006.145.15:17:48.14/onsource/TRACKING 2006.145.15:17:48.14:!2006.145.15:17:58 2006.145.15:17:58.00:"tape 2006.145.15:17:58.00:"st=record 2006.145.15:17:58.00:data_valid=on 2006.145.15:17:58.00:midob 2006.145.15:17:59.14/onsource/TRACKING 2006.145.15:17:59.14/wx/15.47,1020.4,88 2006.145.15:17:59.25/cable/+6.5497E-03 2006.145.15:18:00.34/va/01,08,usb,yes,31,33 2006.145.15:18:00.34/va/02,07,usb,yes,33,34 2006.145.15:18:00.34/va/03,08,usb,yes,30,31 2006.145.15:18:00.34/va/04,07,usb,yes,34,36 2006.145.15:18:00.34/va/05,04,usb,yes,30,30 2006.145.15:18:00.34/va/06,04,usb,yes,33,33 2006.145.15:18:00.34/va/07,04,usb,yes,34,35 2006.145.15:18:00.34/va/08,04,usb,yes,29,34 2006.145.15:18:00.57/valo/01,524.99,yes,locked 2006.145.15:18:00.57/valo/02,534.99,yes,locked 2006.145.15:18:00.57/valo/03,564.99,yes,locked 2006.145.15:18:00.57/valo/04,624.99,yes,locked 2006.145.15:18:00.57/valo/05,734.99,yes,locked 2006.145.15:18:00.57/valo/06,814.99,yes,locked 2006.145.15:18:00.57/valo/07,864.99,yes,locked 2006.145.15:18:00.57/valo/08,884.99,yes,locked 2006.145.15:18:01.66/vb/01,03,usb,yes,38,35 2006.145.15:18:01.66/vb/02,04,usb,yes,33,33 2006.145.15:18:01.66/vb/03,04,usb,yes,30,33 2006.145.15:18:01.66/vb/04,04,usb,yes,34,33 2006.145.15:18:01.66/vb/05,04,usb,yes,27,29 2006.145.15:18:01.66/vb/06,04,usb,yes,32,28 2006.145.15:18:01.66/vb/07,04,usb,yes,31,31 2006.145.15:18:01.66/vb/08,04,usb,yes,29,32 2006.145.15:18:01.89/vblo/01,629.99,yes,locked 2006.145.15:18:01.89/vblo/02,634.99,yes,locked 2006.145.15:18:01.89/vblo/03,649.99,yes,locked 2006.145.15:18:01.89/vblo/04,679.99,yes,locked 2006.145.15:18:01.89/vblo/05,709.99,yes,locked 2006.145.15:18:01.89/vblo/06,719.99,yes,locked 2006.145.15:18:01.89/vblo/07,734.99,yes,locked 2006.145.15:18:01.89/vblo/08,744.99,yes,locked 2006.145.15:18:02.04/vabw/8 2006.145.15:18:02.19/vbbw/8 2006.145.15:18:02.28/xfe/off,on,15.0 2006.145.15:18:02.66/ifatt/23,28,28,28 2006.145.15:18:03.07/fmout-gps/S +4.4E-08 2006.145.15:18:03.11:!2006.145.15:26:28 2006.145.15:26:28.00:data_valid=off 2006.145.15:26:28.00:"et 2006.145.15:26:28.01:!+3s 2006.145.15:26:31.02:"tape 2006.145.15:26:31.02:postob 2006.145.15:26:31.09/cable/+6.5460E-03 2006.145.15:26:31.09/wx/15.49,1020.3,87 2006.145.15:26:32.08/fmout-gps/S +4.4E-08 2006.145.15:26:32.08:scan_name=145-1527,jd0605,150 2006.145.15:26:32.09:source=2201+315,220314.98,314538.3,2000.0,cw 2006.145.15:26:32.15#flagr#flagr/antenna,new-source 2006.145.15:26:33.13:checkk5 2006.145.15:26:33.56/chk_autoobs//k5ts1/ autoobs is running! 2006.145.15:26:34.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.15:26:34.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.15:26:34.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.15:26:35.62/chk_obsdata//k5ts1/T1451517??a.dat file size is correct (nominal:2040MB, actual:2036MB). 2006.145.15:26:36.38/chk_obsdata//k5ts2/T1451517??b.dat file size is correct (nominal:2040MB, actual:2036MB). 2006.145.15:26:37.16/chk_obsdata//k5ts3/T1451517??c.dat file size is correct (nominal:2040MB, actual:2036MB). 2006.145.15:26:37.92/chk_obsdata//k5ts4/T1451517??d.dat file size is correct (nominal:2040MB, actual:2036MB). 2006.145.15:26:38.68/k5log//k5ts1_log_newline 2006.145.15:26:39.44/k5log//k5ts2_log_newline 2006.145.15:26:40.20/k5log//k5ts3_log_newline 2006.145.15:26:40.95/k5log//k5ts4_log_newline 2006.145.15:26:40.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.15:26:40.97:setupk4=1 2006.145.15:26:40.97$setupk4/echo=on 2006.145.15:26:40.97$setupk4/pcalon 2006.145.15:26:40.97$pcalon/"no phase cal control is implemented here 2006.145.15:26:40.97$setupk4/"tpicd=stop 2006.145.15:26:40.97$setupk4/"rec=synch_on 2006.145.15:26:40.97$setupk4/"rec_mode=128 2006.145.15:26:40.97$setupk4/!* 2006.145.15:26:40.97$setupk4/recpk4 2006.145.15:26:40.97$recpk4/recpatch= 2006.145.15:26:40.97$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.15:26:40.97$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.15:26:40.97$setupk4/vck44 2006.145.15:26:40.97$vck44/valo=1,524.99 2006.145.15:26:40.97#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.15:26:40.97#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.15:26:40.97#ibcon#ireg 17 cls_cnt 0 2006.145.15:26:40.97#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.15:26:40.97#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.15:26:40.97#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.15:26:40.99#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.15:26:41.04#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.15:26:41.04#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.15:26:41.04#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.15:26:41.04#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.15:26:41.04$vck44/va=1,8 2006.145.15:26:41.04#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.15:26:41.04#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.15:26:41.04#ibcon#ireg 11 cls_cnt 2 2006.145.15:26:41.04#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.15:26:41.04#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.15:26:41.04#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.15:26:41.06#ibcon#[25=AT01-08\r\n] 2006.145.15:26:41.09#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.15:26:41.09#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.15:26:41.09#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.15:26:41.09#ibcon#ireg 7 cls_cnt 0 2006.145.15:26:41.09#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.15:26:41.21#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.15:26:41.21#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.15:26:41.23#ibcon#[25=USB\r\n] 2006.145.15:26:41.26#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.15:26:41.26#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.15:26:41.26#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.15:26:41.26#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.15:26:41.26$vck44/valo=2,534.99 2006.145.15:26:41.26#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.15:26:41.26#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.15:26:41.26#ibcon#ireg 17 cls_cnt 0 2006.145.15:26:41.26#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.15:26:41.26#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.15:26:41.26#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.15:26:41.28#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.15:26:41.32#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.15:26:41.32#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.15:26:41.32#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.15:26:41.32#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.15:26:41.32$vck44/va=2,7 2006.145.15:26:41.32#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.15:26:41.32#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.15:26:41.32#ibcon#ireg 11 cls_cnt 2 2006.145.15:26:41.32#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.15:26:41.38#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.15:26:41.38#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.15:26:41.40#ibcon#[25=AT02-07\r\n] 2006.145.15:26:41.44#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.15:26:41.44#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.15:26:41.44#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.15:26:41.44#ibcon#ireg 7 cls_cnt 0 2006.145.15:26:41.44#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.15:26:41.56#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.15:26:41.56#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.15:26:41.58#ibcon#[25=USB\r\n] 2006.145.15:26:41.61#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.15:26:41.61#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.15:26:41.61#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.15:26:41.61#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.15:26:41.61$vck44/valo=3,564.99 2006.145.15:26:41.61#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.15:26:41.61#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.15:26:41.61#ibcon#ireg 17 cls_cnt 0 2006.145.15:26:41.61#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.15:26:41.61#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.15:26:41.61#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.15:26:41.63#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.15:26:41.67#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.15:26:41.67#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.15:26:41.67#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.15:26:41.67#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.15:26:41.67$vck44/va=3,8 2006.145.15:26:41.67#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.15:26:41.67#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.15:26:41.67#ibcon#ireg 11 cls_cnt 2 2006.145.15:26:41.67#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.15:26:41.73#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.15:26:41.73#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.15:26:41.75#ibcon#[25=AT03-08\r\n] 2006.145.15:26:41.78#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.15:26:41.78#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.15:26:41.78#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.15:26:41.78#ibcon#ireg 7 cls_cnt 0 2006.145.15:26:41.78#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.15:26:41.90#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.15:26:41.90#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.15:26:41.92#ibcon#[25=USB\r\n] 2006.145.15:26:41.95#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.15:26:41.95#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.15:26:41.95#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.15:26:41.95#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.15:26:41.95$vck44/valo=4,624.99 2006.145.15:26:41.95#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.15:26:41.95#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.15:26:41.95#ibcon#ireg 17 cls_cnt 0 2006.145.15:26:41.95#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.15:26:41.95#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.15:26:41.95#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.15:26:41.97#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.15:26:42.01#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.15:26:42.01#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.15:26:42.01#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.15:26:42.01#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.15:26:42.01$vck44/va=4,7 2006.145.15:26:42.01#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.15:26:42.01#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.15:26:42.01#ibcon#ireg 11 cls_cnt 2 2006.145.15:26:42.01#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.15:26:42.07#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.15:26:42.07#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.15:26:42.09#ibcon#[25=AT04-07\r\n] 2006.145.15:26:42.12#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.15:26:42.12#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.15:26:42.12#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.15:26:42.12#ibcon#ireg 7 cls_cnt 0 2006.145.15:26:42.12#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.15:26:42.24#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.15:26:42.24#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.15:26:42.26#ibcon#[25=USB\r\n] 2006.145.15:26:42.29#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.15:26:42.29#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.15:26:42.29#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.15:26:42.29#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.15:26:42.29$vck44/valo=5,734.99 2006.145.15:26:42.29#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.15:26:42.29#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.15:26:42.29#ibcon#ireg 17 cls_cnt 0 2006.145.15:26:42.29#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.15:26:42.29#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.15:26:42.29#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.15:26:42.31#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.15:26:42.35#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.15:26:42.35#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.15:26:42.35#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.15:26:42.35#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.15:26:42.35$vck44/va=5,4 2006.145.15:26:42.35#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.15:26:42.35#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.15:26:42.35#ibcon#ireg 11 cls_cnt 2 2006.145.15:26:42.35#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.15:26:42.41#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.15:26:42.41#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.15:26:42.43#ibcon#[25=AT05-04\r\n] 2006.145.15:26:42.46#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.15:26:42.46#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.15:26:42.46#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.15:26:42.46#ibcon#ireg 7 cls_cnt 0 2006.145.15:26:42.46#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.15:26:42.58#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.15:26:42.58#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.15:26:42.60#ibcon#[25=USB\r\n] 2006.145.15:26:42.63#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.15:26:42.63#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.15:26:42.63#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.15:26:42.63#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.15:26:42.63$vck44/valo=6,814.99 2006.145.15:26:42.63#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.15:26:42.63#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.15:26:42.63#ibcon#ireg 17 cls_cnt 0 2006.145.15:26:42.63#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.15:26:42.63#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.15:26:42.63#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.15:26:42.66#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.15:26:42.70#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.15:26:42.70#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.15:26:42.70#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.15:26:42.70#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.15:26:42.70$vck44/va=6,4 2006.145.15:26:42.70#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.15:26:42.70#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.15:26:42.70#ibcon#ireg 11 cls_cnt 2 2006.145.15:26:42.70#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.15:26:42.75#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.15:26:42.75#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.15:26:42.77#ibcon#[25=AT06-04\r\n] 2006.145.15:26:42.80#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.15:26:42.80#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.15:26:42.80#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.15:26:42.80#ibcon#ireg 7 cls_cnt 0 2006.145.15:26:42.80#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.15:26:42.92#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.15:26:42.92#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.15:26:42.94#ibcon#[25=USB\r\n] 2006.145.15:26:42.97#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.15:26:42.97#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.15:26:42.97#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.15:26:42.97#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.15:26:42.97$vck44/valo=7,864.99 2006.145.15:26:42.97#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.15:26:42.97#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.15:26:42.97#ibcon#ireg 17 cls_cnt 0 2006.145.15:26:42.97#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.15:26:42.97#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.15:26:42.97#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.15:26:42.99#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.15:26:43.03#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.15:26:43.03#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.15:26:43.03#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.15:26:43.03#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.15:26:43.03$vck44/va=7,4 2006.145.15:26:43.03#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.15:26:43.03#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.15:26:43.03#ibcon#ireg 11 cls_cnt 2 2006.145.15:26:43.03#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.15:26:43.09#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.15:26:43.09#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.15:26:43.11#ibcon#[25=AT07-04\r\n] 2006.145.15:26:43.14#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.15:26:43.14#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.15:26:43.14#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.15:26:43.14#ibcon#ireg 7 cls_cnt 0 2006.145.15:26:43.14#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.15:26:43.26#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.15:26:43.26#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.15:26:43.28#ibcon#[25=USB\r\n] 2006.145.15:26:43.31#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.15:26:43.31#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.15:26:43.31#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.15:26:43.31#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.15:26:43.31$vck44/valo=8,884.99 2006.145.15:26:43.31#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.15:26:43.31#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.15:26:43.31#ibcon#ireg 17 cls_cnt 0 2006.145.15:26:43.31#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.15:26:43.31#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.15:26:43.31#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.15:26:43.33#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.15:26:43.37#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.15:26:43.37#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.15:26:43.37#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.15:26:43.37#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.15:26:43.37$vck44/va=8,4 2006.145.15:26:43.37#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.15:26:43.37#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.15:26:43.37#ibcon#ireg 11 cls_cnt 2 2006.145.15:26:43.37#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.15:26:43.43#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.15:26:43.43#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.15:26:43.45#ibcon#[25=AT08-04\r\n] 2006.145.15:26:43.48#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.15:26:43.48#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.15:26:43.48#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.15:26:43.48#ibcon#ireg 7 cls_cnt 0 2006.145.15:26:43.48#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.15:26:43.60#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.15:26:43.60#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.15:26:43.62#ibcon#[25=USB\r\n] 2006.145.15:26:43.65#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.15:26:43.65#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.15:26:43.65#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.15:26:43.65#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.15:26:43.65$vck44/vblo=1,629.99 2006.145.15:26:43.65#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.15:26:43.65#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.15:26:43.65#ibcon#ireg 17 cls_cnt 0 2006.145.15:26:43.65#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.15:26:43.65#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.15:26:43.65#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.15:26:43.67#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.15:26:43.71#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.15:26:43.71#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.15:26:43.71#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.15:26:43.71#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.15:26:43.71$vck44/vb=1,3 2006.145.15:26:43.71#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.15:26:43.71#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.15:26:43.71#ibcon#ireg 11 cls_cnt 2 2006.145.15:26:43.71#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.15:26:43.71#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.15:26:43.71#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.15:26:43.73#ibcon#[27=AT01-03\r\n] 2006.145.15:26:43.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.15:26:43.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.15:26:43.76#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.15:26:43.76#ibcon#ireg 7 cls_cnt 0 2006.145.15:26:43.76#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.15:26:43.88#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.15:26:43.88#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.15:26:43.90#ibcon#[27=USB\r\n] 2006.145.15:26:43.93#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.15:26:43.93#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.15:26:43.93#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.15:26:43.93#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.15:26:43.93$vck44/vblo=2,634.99 2006.145.15:26:43.93#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.15:26:43.93#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.15:26:43.93#ibcon#ireg 17 cls_cnt 0 2006.145.15:26:43.93#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.15:26:43.93#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.15:26:43.93#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.15:26:43.95#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.15:26:43.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.15:26:43.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.15:26:43.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.15:26:43.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.15:26:43.99$vck44/vb=2,4 2006.145.15:26:43.99#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.15:26:43.99#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.15:26:43.99#ibcon#ireg 11 cls_cnt 2 2006.145.15:26:43.99#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.15:26:44.05#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.15:26:44.05#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.15:26:44.07#ibcon#[27=AT02-04\r\n] 2006.145.15:26:44.10#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.15:26:44.10#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.15:26:44.10#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.15:26:44.10#ibcon#ireg 7 cls_cnt 0 2006.145.15:26:44.10#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.15:26:44.22#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.15:26:44.22#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.15:26:44.24#ibcon#[27=USB\r\n] 2006.145.15:26:44.27#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.15:26:44.27#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.15:26:44.27#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.15:26:44.27#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.15:26:44.27$vck44/vblo=3,649.99 2006.145.15:26:44.27#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.15:26:44.27#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.15:26:44.27#ibcon#ireg 17 cls_cnt 0 2006.145.15:26:44.27#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.15:26:44.27#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.15:26:44.27#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.15:26:44.29#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.15:26:44.33#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.15:26:44.33#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.15:26:44.33#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.15:26:44.33#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.15:26:44.33$vck44/vb=3,4 2006.145.15:26:44.33#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.15:26:44.33#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.15:26:44.33#ibcon#ireg 11 cls_cnt 2 2006.145.15:26:44.33#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.15:26:44.39#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.15:26:44.39#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.15:26:44.41#ibcon#[27=AT03-04\r\n] 2006.145.15:26:44.44#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.15:26:44.44#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.15:26:44.44#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.15:26:44.44#ibcon#ireg 7 cls_cnt 0 2006.145.15:26:44.44#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.15:26:44.56#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.15:26:44.56#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.15:26:44.58#ibcon#[27=USB\r\n] 2006.145.15:26:44.61#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.15:26:44.61#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.15:26:44.61#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.15:26:44.61#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.15:26:44.61$vck44/vblo=4,679.99 2006.145.15:26:44.61#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.15:26:44.61#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.15:26:44.61#ibcon#ireg 17 cls_cnt 0 2006.145.15:26:44.61#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.15:26:44.61#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.15:26:44.61#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.15:26:44.63#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.15:26:44.67#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.15:26:44.67#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.15:26:44.67#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.15:26:44.67#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.15:26:44.67$vck44/vb=4,4 2006.145.15:26:44.67#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.15:26:44.67#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.15:26:44.67#ibcon#ireg 11 cls_cnt 2 2006.145.15:26:44.67#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.15:26:44.73#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.15:26:44.73#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.15:26:44.75#ibcon#[27=AT04-04\r\n] 2006.145.15:26:44.78#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.15:26:44.78#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.15:26:44.78#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.15:26:44.78#ibcon#ireg 7 cls_cnt 0 2006.145.15:26:44.78#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.15:26:44.90#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.15:26:44.90#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.15:26:44.92#ibcon#[27=USB\r\n] 2006.145.15:26:44.95#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.15:26:44.95#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.15:26:44.95#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.15:26:44.95#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.15:26:44.95$vck44/vblo=5,709.99 2006.145.15:26:44.95#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.15:26:44.95#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.15:26:44.95#ibcon#ireg 17 cls_cnt 0 2006.145.15:26:44.95#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.15:26:44.95#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.15:26:44.95#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.15:26:44.97#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.15:26:45.01#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.15:26:45.01#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.15:26:45.01#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.15:26:45.01#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.15:26:45.01$vck44/vb=5,4 2006.145.15:26:45.01#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.15:26:45.01#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.15:26:45.01#ibcon#ireg 11 cls_cnt 2 2006.145.15:26:45.01#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.15:26:45.07#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.15:26:45.07#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.15:26:45.09#ibcon#[27=AT05-04\r\n] 2006.145.15:26:45.12#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.15:26:45.12#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.15:26:45.12#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.15:26:45.12#ibcon#ireg 7 cls_cnt 0 2006.145.15:26:45.12#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.15:26:45.24#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.15:26:45.24#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.15:26:45.26#ibcon#[27=USB\r\n] 2006.145.15:26:45.29#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.15:26:45.29#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.15:26:45.29#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.15:26:45.29#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.15:26:45.29$vck44/vblo=6,719.99 2006.145.15:26:45.29#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.15:26:45.29#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.15:26:45.29#ibcon#ireg 17 cls_cnt 0 2006.145.15:26:45.29#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.15:26:45.29#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.15:26:45.29#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.15:26:45.31#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.15:26:45.35#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.15:26:45.35#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.15:26:45.35#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.15:26:45.35#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.15:26:45.35$vck44/vb=6,4 2006.145.15:26:45.35#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.15:26:45.35#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.15:26:45.35#ibcon#ireg 11 cls_cnt 2 2006.145.15:26:45.35#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.15:26:45.41#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.15:26:45.41#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.15:26:45.43#ibcon#[27=AT06-04\r\n] 2006.145.15:26:45.46#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.15:26:45.46#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.15:26:45.46#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.15:26:45.46#ibcon#ireg 7 cls_cnt 0 2006.145.15:26:45.46#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.15:26:45.58#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.15:26:45.58#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.15:26:45.60#ibcon#[27=USB\r\n] 2006.145.15:26:45.63#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.15:26:45.63#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.15:26:45.63#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.15:26:45.63#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.15:26:45.63$vck44/vblo=7,734.99 2006.145.15:26:45.63#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.15:26:45.63#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.15:26:45.63#ibcon#ireg 17 cls_cnt 0 2006.145.15:26:45.63#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.15:26:45.63#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.15:26:45.63#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.15:26:45.65#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.15:26:45.69#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.15:26:45.69#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.15:26:45.69#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.15:26:45.69#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.15:26:45.69$vck44/vb=7,4 2006.145.15:26:45.69#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.15:26:45.69#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.15:26:45.69#ibcon#ireg 11 cls_cnt 2 2006.145.15:26:45.69#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.15:26:45.75#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.15:26:45.75#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.15:26:45.77#ibcon#[27=AT07-04\r\n] 2006.145.15:26:45.80#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.15:26:45.80#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.15:26:45.80#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.15:26:45.80#ibcon#ireg 7 cls_cnt 0 2006.145.15:26:45.80#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.15:26:45.92#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.15:26:45.92#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.15:26:45.94#ibcon#[27=USB\r\n] 2006.145.15:26:45.97#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.15:26:45.97#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.15:26:45.97#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.15:26:45.97#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.15:26:45.97$vck44/vblo=8,744.99 2006.145.15:26:45.97#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.15:26:45.97#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.15:26:45.97#ibcon#ireg 17 cls_cnt 0 2006.145.15:26:45.97#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.15:26:45.97#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.15:26:45.97#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.15:26:45.99#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.15:26:46.03#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.15:26:46.03#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.15:26:46.03#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.15:26:46.03#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.15:26:46.03$vck44/vb=8,4 2006.145.15:26:46.03#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.15:26:46.03#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.15:26:46.03#ibcon#ireg 11 cls_cnt 2 2006.145.15:26:46.03#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.15:26:46.09#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.15:26:46.09#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.15:26:46.11#ibcon#[27=AT08-04\r\n] 2006.145.15:26:46.14#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.15:26:46.14#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.15:26:46.14#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.15:26:46.14#ibcon#ireg 7 cls_cnt 0 2006.145.15:26:46.14#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.15:26:46.26#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.15:26:46.26#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.15:26:46.28#ibcon#[27=USB\r\n] 2006.145.15:26:46.31#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.15:26:46.31#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.15:26:46.31#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.15:26:46.31#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.15:26:46.31$vck44/vabw=wide 2006.145.15:26:46.31#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.15:26:46.31#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.15:26:46.31#ibcon#ireg 8 cls_cnt 0 2006.145.15:26:46.31#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.15:26:46.31#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.15:26:46.31#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.15:26:46.33#ibcon#[25=BW32\r\n] 2006.145.15:26:46.36#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.15:26:46.36#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.15:26:46.36#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.15:26:46.36#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.15:26:46.36$vck44/vbbw=wide 2006.145.15:26:46.36#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.15:26:46.36#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.15:26:46.36#ibcon#ireg 8 cls_cnt 0 2006.145.15:26:46.36#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:26:46.43#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:26:46.43#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:26:46.45#ibcon#[27=BW32\r\n] 2006.145.15:26:46.48#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:26:46.48#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:26:46.48#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.15:26:46.48#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.15:26:46.48$setupk4/ifdk4 2006.145.15:26:46.48$ifdk4/lo= 2006.145.15:26:46.48$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.15:26:46.48$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.15:26:46.48$ifdk4/patch= 2006.145.15:26:46.48$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.15:26:46.48$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.15:26:46.48$setupk4/!*+20s 2006.145.15:26:47.63#abcon#<5=/07 1.0 1.9 15.49 871020.3\r\n> 2006.145.15:26:47.65#abcon#{5=INTERFACE CLEAR} 2006.145.15:26:47.71#abcon#[5=S1D000X0/0*\r\n] 2006.145.15:26:56.14#trakl#Source acquired 2006.145.15:26:56.14#flagr#flagr/antenna,acquired 2006.145.15:26:57.80#abcon#<5=/07 1.0 2.0 15.50 871020.3\r\n> 2006.145.15:26:57.82#abcon#{5=INTERFACE CLEAR} 2006.145.15:26:57.88#abcon#[5=S1D000X0/0*\r\n] 2006.145.15:27:00.98$setupk4/"tpicd 2006.145.15:27:00.98$setupk4/echo=off 2006.145.15:27:00.98$setupk4/xlog=off 2006.145.15:27:00.98:!2006.145.15:27:13 2006.145.15:27:13.00:preob 2006.145.15:27:13.14/onsource/TRACKING 2006.145.15:27:13.14:!2006.145.15:27:23 2006.145.15:27:23.00:"tape 2006.145.15:27:23.00:"st=record 2006.145.15:27:23.00:data_valid=on 2006.145.15:27:23.00:midob 2006.145.15:27:23.14/onsource/TRACKING 2006.145.15:27:23.14/wx/15.50,1020.3,87 2006.145.15:27:23.28/cable/+6.5492E-03 2006.145.15:27:24.37/va/01,08,usb,yes,29,31 2006.145.15:27:24.37/va/02,07,usb,yes,31,32 2006.145.15:27:24.37/va/03,08,usb,yes,28,29 2006.145.15:27:24.37/va/04,07,usb,yes,32,34 2006.145.15:27:24.37/va/05,04,usb,yes,28,28 2006.145.15:27:24.37/va/06,04,usb,yes,31,31 2006.145.15:27:24.37/va/07,04,usb,yes,32,33 2006.145.15:27:24.37/va/08,04,usb,yes,27,32 2006.145.15:27:24.60/valo/01,524.99,yes,locked 2006.145.15:27:24.60/valo/02,534.99,yes,locked 2006.145.15:27:24.60/valo/03,564.99,yes,locked 2006.145.15:27:24.60/valo/04,624.99,yes,locked 2006.145.15:27:24.60/valo/05,734.99,yes,locked 2006.145.15:27:24.60/valo/06,814.99,yes,locked 2006.145.15:27:24.60/valo/07,864.99,yes,locked 2006.145.15:27:24.60/valo/08,884.99,yes,locked 2006.145.15:27:25.69/vb/01,03,usb,yes,36,34 2006.145.15:27:25.69/vb/02,04,usb,yes,32,31 2006.145.15:27:25.69/vb/03,04,usb,yes,29,31 2006.145.15:27:25.69/vb/04,04,usb,yes,33,32 2006.145.15:27:25.69/vb/05,04,usb,yes,25,28 2006.145.15:27:25.69/vb/06,04,usb,yes,30,26 2006.145.15:27:25.69/vb/07,04,usb,yes,30,29 2006.145.15:27:25.69/vb/08,04,usb,yes,27,31 2006.145.15:27:25.92/vblo/01,629.99,yes,locked 2006.145.15:27:25.92/vblo/02,634.99,yes,locked 2006.145.15:27:25.92/vblo/03,649.99,yes,locked 2006.145.15:27:25.92/vblo/04,679.99,yes,locked 2006.145.15:27:25.92/vblo/05,709.99,yes,locked 2006.145.15:27:25.92/vblo/06,719.99,yes,locked 2006.145.15:27:25.92/vblo/07,734.99,yes,locked 2006.145.15:27:25.92/vblo/08,744.99,yes,locked 2006.145.15:27:26.07/vabw/8 2006.145.15:27:26.22/vbbw/8 2006.145.15:27:26.31/xfe/off,on,14.2 2006.145.15:27:26.69/ifatt/23,28,28,28 2006.145.15:27:27.07/fmout-gps/S +4.4E-08 2006.145.15:27:27.11:!2006.145.15:29:53 2006.145.15:29:53.01:data_valid=off 2006.145.15:29:53.01:"et 2006.145.15:29:53.02:!+3s 2006.145.15:29:56.03:"tape 2006.145.15:29:56.03:postob 2006.145.15:29:56.12/cable/+6.5489E-03 2006.145.15:29:56.12/wx/15.51,1020.4,87 2006.145.15:29:56.21/fmout-gps/S +4.2E-08 2006.145.15:29:56.21:scan_name=145-1538,jd0605,100 2006.145.15:29:56.21:source=1908-201,191109.65,-200655.1,2000.0,cw 2006.145.15:29:57.13#flagr#flagr/antenna,new-source 2006.145.15:29:57.13:checkk5 2006.145.15:29:57.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.15:29:58.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.15:29:58.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.15:29:58.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.15:29:59.32/chk_obsdata//k5ts1/T1451527??a.dat file size is correct (nominal:600MB, actual:596MB). 2006.145.15:29:59.76/chk_obsdata//k5ts2/T1451527??b.dat file size is correct (nominal:600MB, actual:596MB). 2006.145.15:30:00.21/chk_obsdata//k5ts3/T1451527??c.dat file size is correct (nominal:600MB, actual:596MB). 2006.145.15:30:00.65/chk_obsdata//k5ts4/T1451527??d.dat file size is correct (nominal:600MB, actual:596MB). 2006.145.15:30:01.41/k5log//k5ts1_log_newline 2006.145.15:30:02.16/k5log//k5ts2_log_newline 2006.145.15:30:02.90/k5log//k5ts3_log_newline 2006.145.15:30:03.64/k5log//k5ts4_log_newline 2006.145.15:30:03.66/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.15:30:03.66:setupk4=1 2006.145.15:30:03.66$setupk4/echo=on 2006.145.15:30:03.66$setupk4/pcalon 2006.145.15:30:03.66$pcalon/"no phase cal control is implemented here 2006.145.15:30:03.66$setupk4/"tpicd=stop 2006.145.15:30:03.66$setupk4/"rec=synch_on 2006.145.15:30:03.66$setupk4/"rec_mode=128 2006.145.15:30:03.66$setupk4/!* 2006.145.15:30:03.66$setupk4/recpk4 2006.145.15:30:03.66$recpk4/recpatch= 2006.145.15:30:03.66$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.15:30:03.66$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.15:30:03.66$setupk4/vck44 2006.145.15:30:03.66$vck44/valo=1,524.99 2006.145.15:30:03.66#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.15:30:03.66#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.15:30:03.66#ibcon#ireg 17 cls_cnt 0 2006.145.15:30:03.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.15:30:03.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.15:30:03.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.15:30:03.68#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.15:30:03.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.15:30:03.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.15:30:03.73#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.15:30:03.73#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.15:30:03.73$vck44/va=1,8 2006.145.15:30:03.73#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.15:30:03.73#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.15:30:03.73#ibcon#ireg 11 cls_cnt 2 2006.145.15:30:03.73#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.15:30:03.73#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.15:30:03.73#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.15:30:03.75#ibcon#[25=AT01-08\r\n] 2006.145.15:30:03.78#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.15:30:03.78#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.15:30:03.78#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.15:30:03.78#ibcon#ireg 7 cls_cnt 0 2006.145.15:30:03.78#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.15:30:03.90#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.15:30:03.90#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.15:30:03.92#ibcon#[25=USB\r\n] 2006.145.15:30:03.97#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.15:30:03.97#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.15:30:03.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.15:30:03.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.15:30:03.97$vck44/valo=2,534.99 2006.145.15:30:03.97#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.15:30:03.97#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.15:30:03.97#ibcon#ireg 17 cls_cnt 0 2006.145.15:30:03.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.15:30:03.97#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.15:30:03.97#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.15:30:03.98#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.15:30:04.02#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.15:30:04.02#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.15:30:04.02#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.15:30:04.02#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.15:30:04.02$vck44/va=2,7 2006.145.15:30:04.02#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.15:30:04.02#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.15:30:04.02#ibcon#ireg 11 cls_cnt 2 2006.145.15:30:04.02#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.15:30:04.09#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.15:30:04.09#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.15:30:04.11#ibcon#[25=AT02-07\r\n] 2006.145.15:30:04.14#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.15:30:04.14#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.15:30:04.14#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.15:30:04.14#ibcon#ireg 7 cls_cnt 0 2006.145.15:30:04.14#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.15:30:04.26#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.15:30:04.26#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.15:30:04.28#ibcon#[25=USB\r\n] 2006.145.15:30:04.31#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.15:30:04.31#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.15:30:04.31#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.15:30:04.31#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.15:30:04.31$vck44/valo=3,564.99 2006.145.15:30:04.31#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.15:30:04.31#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.15:30:04.31#ibcon#ireg 17 cls_cnt 0 2006.145.15:30:04.31#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.15:30:04.31#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.15:30:04.31#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.15:30:04.33#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.15:30:04.37#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.15:30:04.37#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.15:30:04.37#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.15:30:04.37#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.15:30:04.37$vck44/va=3,8 2006.145.15:30:04.37#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.15:30:04.37#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.15:30:04.37#ibcon#ireg 11 cls_cnt 2 2006.145.15:30:04.37#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.15:30:04.43#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.15:30:04.43#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.15:30:04.45#ibcon#[25=AT03-08\r\n] 2006.145.15:30:04.48#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.15:30:04.48#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.15:30:04.48#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.15:30:04.48#ibcon#ireg 7 cls_cnt 0 2006.145.15:30:04.48#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.15:30:04.60#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.15:30:04.60#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.15:30:04.62#ibcon#[25=USB\r\n] 2006.145.15:30:04.65#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.15:30:04.65#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.15:30:04.65#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.15:30:04.65#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.15:30:04.65$vck44/valo=4,624.99 2006.145.15:30:04.65#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.15:30:04.65#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.15:30:04.65#ibcon#ireg 17 cls_cnt 0 2006.145.15:30:04.65#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.15:30:04.65#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.15:30:04.65#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.15:30:04.67#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.15:30:04.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.15:30:04.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.15:30:04.71#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.15:30:04.71#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.15:30:04.71$vck44/va=4,7 2006.145.15:30:04.71#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.15:30:04.71#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.15:30:04.71#ibcon#ireg 11 cls_cnt 2 2006.145.15:30:04.71#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.15:30:04.77#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.15:30:04.77#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.15:30:04.79#ibcon#[25=AT04-07\r\n] 2006.145.15:30:04.82#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.15:30:04.82#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.15:30:04.82#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.15:30:04.82#ibcon#ireg 7 cls_cnt 0 2006.145.15:30:04.82#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.15:30:04.94#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.15:30:04.94#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.15:30:04.96#ibcon#[25=USB\r\n] 2006.145.15:30:04.99#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.15:30:04.99#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.15:30:04.99#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.15:30:04.99#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.15:30:04.99$vck44/valo=5,734.99 2006.145.15:30:04.99#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.15:30:04.99#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.15:30:04.99#ibcon#ireg 17 cls_cnt 0 2006.145.15:30:04.99#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.15:30:04.99#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.15:30:04.99#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.15:30:05.01#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.15:30:05.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.15:30:05.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.15:30:05.06#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.15:30:05.06#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.15:30:05.06$vck44/va=5,4 2006.145.15:30:05.06#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.15:30:05.06#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.15:30:05.06#ibcon#ireg 11 cls_cnt 2 2006.145.15:30:05.06#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.15:30:05.10#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.15:30:05.10#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.15:30:05.12#ibcon#[25=AT05-04\r\n] 2006.145.15:30:05.16#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.15:30:05.16#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.15:30:05.16#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.15:30:05.16#ibcon#ireg 7 cls_cnt 0 2006.145.15:30:05.16#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.15:30:05.27#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.15:30:05.27#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.15:30:05.29#ibcon#[25=USB\r\n] 2006.145.15:30:05.32#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.15:30:05.32#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.15:30:05.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.15:30:05.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.15:30:05.32$vck44/valo=6,814.99 2006.145.15:30:05.32#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.15:30:05.32#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.15:30:05.32#ibcon#ireg 17 cls_cnt 0 2006.145.15:30:05.32#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.15:30:05.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.15:30:05.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.15:30:05.35#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.15:30:05.39#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.15:30:05.39#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.15:30:05.39#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.15:30:05.39#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.15:30:05.39$vck44/va=6,4 2006.145.15:30:05.39#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.15:30:05.39#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.15:30:05.39#ibcon#ireg 11 cls_cnt 2 2006.145.15:30:05.39#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.15:30:05.44#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.15:30:05.44#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.15:30:05.46#ibcon#[25=AT06-04\r\n] 2006.145.15:30:05.49#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.15:30:05.49#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.15:30:05.49#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.15:30:05.49#ibcon#ireg 7 cls_cnt 0 2006.145.15:30:05.49#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.15:30:05.61#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.15:30:05.61#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.15:30:05.63#ibcon#[25=USB\r\n] 2006.145.15:30:05.66#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.15:30:05.66#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.15:30:05.66#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.15:30:05.66#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.15:30:05.66$vck44/valo=7,864.99 2006.145.15:30:05.66#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.15:30:05.66#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.15:30:05.66#ibcon#ireg 17 cls_cnt 0 2006.145.15:30:05.66#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.15:30:05.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.15:30:05.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.15:30:05.68#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.15:30:05.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.15:30:05.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.15:30:05.72#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.15:30:05.72#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.15:30:05.72$vck44/va=7,4 2006.145.15:30:05.72#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.15:30:05.72#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.15:30:05.72#ibcon#ireg 11 cls_cnt 2 2006.145.15:30:05.72#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.15:30:05.78#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.15:30:05.78#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.15:30:05.80#ibcon#[25=AT07-04\r\n] 2006.145.15:30:05.83#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.15:30:05.83#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.15:30:05.83#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.15:30:05.83#ibcon#ireg 7 cls_cnt 0 2006.145.15:30:05.83#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.15:30:05.95#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.15:30:05.95#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.15:30:05.97#ibcon#[25=USB\r\n] 2006.145.15:30:06.00#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.15:30:06.00#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.15:30:06.00#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.15:30:06.00#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.15:30:06.00$vck44/valo=8,884.99 2006.145.15:30:06.00#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.15:30:06.00#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.15:30:06.00#ibcon#ireg 17 cls_cnt 0 2006.145.15:30:06.00#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.15:30:06.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.15:30:06.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.15:30:06.02#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.15:30:06.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.15:30:06.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.15:30:06.06#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.15:30:06.06#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.15:30:06.06$vck44/va=8,4 2006.145.15:30:06.06#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.15:30:06.06#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.15:30:06.06#ibcon#ireg 11 cls_cnt 2 2006.145.15:30:06.06#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.15:30:06.12#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.15:30:06.12#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.15:30:06.14#ibcon#[25=AT08-04\r\n] 2006.145.15:30:06.17#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.15:30:06.17#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.15:30:06.17#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.15:30:06.17#ibcon#ireg 7 cls_cnt 0 2006.145.15:30:06.17#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.15:30:06.29#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.15:30:06.29#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.15:30:06.31#ibcon#[25=USB\r\n] 2006.145.15:30:06.34#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.15:30:06.34#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.15:30:06.34#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.15:30:06.34#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.15:30:06.34$vck44/vblo=1,629.99 2006.145.15:30:06.34#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.15:30:06.34#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.15:30:06.34#ibcon#ireg 17 cls_cnt 0 2006.145.15:30:06.34#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.15:30:06.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.15:30:06.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.15:30:06.36#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.15:30:06.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.15:30:06.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.15:30:06.40#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.15:30:06.40#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.15:30:06.40$vck44/vb=1,3 2006.145.15:30:06.40#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.15:30:06.40#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.15:30:06.40#ibcon#ireg 11 cls_cnt 2 2006.145.15:30:06.40#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.15:30:06.40#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.15:30:06.40#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.15:30:06.42#ibcon#[27=AT01-03\r\n] 2006.145.15:30:06.45#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.15:30:06.45#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.15:30:06.45#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.15:30:06.45#ibcon#ireg 7 cls_cnt 0 2006.145.15:30:06.45#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.15:30:06.57#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.15:30:06.57#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.15:30:06.59#ibcon#[27=USB\r\n] 2006.145.15:30:06.62#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.15:30:06.62#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.15:30:06.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.15:30:06.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.15:30:06.62$vck44/vblo=2,634.99 2006.145.15:30:06.62#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.15:30:06.62#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.15:30:06.62#ibcon#ireg 17 cls_cnt 0 2006.145.15:30:06.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.15:30:06.62#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.15:30:06.62#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.15:30:06.64#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.15:30:06.68#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.15:30:06.68#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.15:30:06.68#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.15:30:06.68#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.15:30:06.68$vck44/vb=2,4 2006.145.15:30:06.68#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.15:30:06.68#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.15:30:06.68#ibcon#ireg 11 cls_cnt 2 2006.145.15:30:06.68#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.15:30:06.74#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.15:30:06.74#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.15:30:06.76#ibcon#[27=AT02-04\r\n] 2006.145.15:30:06.79#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.15:30:06.79#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.15:30:06.79#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.15:30:06.79#ibcon#ireg 7 cls_cnt 0 2006.145.15:30:06.79#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.15:30:06.91#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.15:30:06.91#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.15:30:06.93#ibcon#[27=USB\r\n] 2006.145.15:30:06.96#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.15:30:06.96#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.15:30:06.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.15:30:06.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.15:30:06.96$vck44/vblo=3,649.99 2006.145.15:30:06.96#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.15:30:06.96#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.15:30:06.96#ibcon#ireg 17 cls_cnt 0 2006.145.15:30:06.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.15:30:06.96#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.15:30:06.96#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.15:30:06.98#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.15:30:07.02#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.15:30:07.02#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.15:30:07.02#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.15:30:07.02#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.15:30:07.02$vck44/vb=3,4 2006.145.15:30:07.02#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.15:30:07.02#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.15:30:07.02#ibcon#ireg 11 cls_cnt 2 2006.145.15:30:07.02#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.15:30:07.08#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.15:30:07.08#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.15:30:07.10#ibcon#[27=AT03-04\r\n] 2006.145.15:30:07.13#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.15:30:07.13#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.15:30:07.13#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.15:30:07.13#ibcon#ireg 7 cls_cnt 0 2006.145.15:30:07.13#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.15:30:07.25#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.15:30:07.25#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.15:30:07.27#ibcon#[27=USB\r\n] 2006.145.15:30:07.30#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.15:30:07.30#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.15:30:07.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.15:30:07.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.15:30:07.30$vck44/vblo=4,679.99 2006.145.15:30:07.30#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.15:30:07.30#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.15:30:07.30#ibcon#ireg 17 cls_cnt 0 2006.145.15:30:07.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.15:30:07.30#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.15:30:07.30#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.15:30:07.32#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.15:30:07.36#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.15:30:07.36#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.15:30:07.36#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.15:30:07.36#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.15:30:07.36$vck44/vb=4,4 2006.145.15:30:07.36#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.15:30:07.36#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.15:30:07.36#ibcon#ireg 11 cls_cnt 2 2006.145.15:30:07.36#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.15:30:07.42#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.15:30:07.42#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.15:30:07.44#ibcon#[27=AT04-04\r\n] 2006.145.15:30:07.47#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.15:30:07.47#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.15:30:07.47#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.15:30:07.47#ibcon#ireg 7 cls_cnt 0 2006.145.15:30:07.47#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.15:30:07.59#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.15:30:07.59#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.15:30:07.61#ibcon#[27=USB\r\n] 2006.145.15:30:07.64#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.15:30:07.64#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.15:30:07.64#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.15:30:07.64#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.15:30:07.64$vck44/vblo=5,709.99 2006.145.15:30:07.64#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.15:30:07.64#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.15:30:07.64#ibcon#ireg 17 cls_cnt 0 2006.145.15:30:07.64#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.15:30:07.64#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.15:30:07.64#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.15:30:07.66#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.15:30:07.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.15:30:07.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.15:30:07.70#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.15:30:07.70#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.15:30:07.70$vck44/vb=5,4 2006.145.15:30:07.70#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.15:30:07.70#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.15:30:07.70#ibcon#ireg 11 cls_cnt 2 2006.145.15:30:07.70#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.15:30:07.76#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.15:30:07.76#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.15:30:07.78#ibcon#[27=AT05-04\r\n] 2006.145.15:30:07.81#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.15:30:07.81#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.15:30:07.81#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.15:30:07.81#ibcon#ireg 7 cls_cnt 0 2006.145.15:30:07.81#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.15:30:07.93#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.15:30:07.93#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.15:30:07.95#ibcon#[27=USB\r\n] 2006.145.15:30:07.98#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.15:30:07.98#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.15:30:07.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.15:30:07.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.15:30:07.98$vck44/vblo=6,719.99 2006.145.15:30:07.98#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.15:30:07.98#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.15:30:07.98#ibcon#ireg 17 cls_cnt 0 2006.145.15:30:07.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.15:30:07.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.15:30:07.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.15:30:08.00#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.15:30:08.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.15:30:08.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.15:30:08.04#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.15:30:08.04#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.15:30:08.04$vck44/vb=6,4 2006.145.15:30:08.04#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.15:30:08.04#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.15:30:08.04#ibcon#ireg 11 cls_cnt 2 2006.145.15:30:08.04#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.15:30:08.10#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.15:30:08.10#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.15:30:08.12#ibcon#[27=AT06-04\r\n] 2006.145.15:30:08.15#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.15:30:08.15#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.15:30:08.15#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.15:30:08.15#ibcon#ireg 7 cls_cnt 0 2006.145.15:30:08.15#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.15:30:08.27#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.15:30:08.27#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.15:30:08.29#ibcon#[27=USB\r\n] 2006.145.15:30:08.32#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.15:30:08.32#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.15:30:08.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.15:30:08.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.15:30:08.32$vck44/vblo=7,734.99 2006.145.15:30:08.32#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.15:30:08.32#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.15:30:08.32#ibcon#ireg 17 cls_cnt 0 2006.145.15:30:08.32#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.15:30:08.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.15:30:08.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.15:30:08.34#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.15:30:08.38#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.15:30:08.38#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.15:30:08.38#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.15:30:08.38#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.15:30:08.38$vck44/vb=7,4 2006.145.15:30:08.38#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.15:30:08.38#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.15:30:08.38#ibcon#ireg 11 cls_cnt 2 2006.145.15:30:08.38#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.15:30:08.44#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.15:30:08.44#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.15:30:08.46#ibcon#[27=AT07-04\r\n] 2006.145.15:30:08.49#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.15:30:08.49#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.15:30:08.49#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.15:30:08.49#ibcon#ireg 7 cls_cnt 0 2006.145.15:30:08.49#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.15:30:08.61#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.15:30:08.61#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.15:30:08.63#ibcon#[27=USB\r\n] 2006.145.15:30:08.66#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.15:30:08.66#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.15:30:08.66#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.15:30:08.66#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.15:30:08.66$vck44/vblo=8,744.99 2006.145.15:30:08.66#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.15:30:08.66#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.15:30:08.66#ibcon#ireg 17 cls_cnt 0 2006.145.15:30:08.66#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.15:30:08.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.15:30:08.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.15:30:08.68#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.15:30:08.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.15:30:08.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.15:30:08.72#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.15:30:08.72#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.15:30:08.72$vck44/vb=8,4 2006.145.15:30:08.72#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.15:30:08.72#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.15:30:08.72#ibcon#ireg 11 cls_cnt 2 2006.145.15:30:08.72#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.15:30:08.78#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.15:30:08.78#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.15:30:08.80#ibcon#[27=AT08-04\r\n] 2006.145.15:30:08.83#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.15:30:08.83#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.15:30:08.83#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.15:30:08.83#ibcon#ireg 7 cls_cnt 0 2006.145.15:30:08.83#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.15:30:08.95#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.15:30:08.95#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.15:30:08.97#ibcon#[27=USB\r\n] 2006.145.15:30:09.00#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.15:30:09.00#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.15:30:09.00#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.15:30:09.00#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.15:30:09.00$vck44/vabw=wide 2006.145.15:30:09.00#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.15:30:09.00#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.15:30:09.00#ibcon#ireg 8 cls_cnt 0 2006.145.15:30:09.00#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.15:30:09.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.15:30:09.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.15:30:09.02#ibcon#[25=BW32\r\n] 2006.145.15:30:09.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.15:30:09.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.15:30:09.05#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.15:30:09.05#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.15:30:09.05$vck44/vbbw=wide 2006.145.15:30:09.05#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.15:30:09.05#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.15:30:09.05#ibcon#ireg 8 cls_cnt 0 2006.145.15:30:09.05#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.15:30:09.12#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.15:30:09.12#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.15:30:09.14#ibcon#[27=BW32\r\n] 2006.145.15:30:09.17#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.15:30:09.17#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.15:30:09.17#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.15:30:09.17#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.15:30:09.17$setupk4/ifdk4 2006.145.15:30:09.17$ifdk4/lo= 2006.145.15:30:09.17$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.15:30:09.17$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.15:30:09.17$ifdk4/patch= 2006.145.15:30:09.17$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.15:30:09.17$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.15:30:09.17$setupk4/!*+20s 2006.145.15:30:11.15#abcon#<5=/07 1.0 2.0 15.52 871020.4\r\n> 2006.145.15:30:11.17#abcon#{5=INTERFACE CLEAR} 2006.145.15:30:11.23#abcon#[5=S1D000X0/0*\r\n] 2006.145.15:30:21.32#abcon#<5=/07 1.0 2.0 15.52 871020.4\r\n> 2006.145.15:30:21.34#abcon#{5=INTERFACE CLEAR} 2006.145.15:30:21.40#abcon#[5=S1D000X0/0*\r\n] 2006.145.15:30:23.67$setupk4/"tpicd 2006.145.15:30:23.67$setupk4/echo=off 2006.145.15:30:23.67$setupk4/xlog=off 2006.145.15:30:23.67:!2006.145.15:38:40 2006.145.15:30:30.13#trakl#Source acquired 2006.145.15:30:32.13#flagr#flagr/antenna,acquired 2006.145.15:38:40.00:preob 2006.145.15:38:40.13/onsource/TRACKING 2006.145.15:38:40.13:!2006.145.15:38:50 2006.145.15:38:50.00:"tape 2006.145.15:38:50.00:"st=record 2006.145.15:38:50.00:data_valid=on 2006.145.15:38:50.00:midob 2006.145.15:38:50.13/onsource/TRACKING 2006.145.15:38:50.13/wx/15.67,1020.3,86 2006.145.15:38:50.20/cable/+6.5508E-03 2006.145.15:38:51.29/va/01,08,usb,yes,29,31 2006.145.15:38:51.29/va/02,07,usb,yes,31,32 2006.145.15:38:51.29/va/03,08,usb,yes,28,30 2006.145.15:38:51.29/va/04,07,usb,yes,32,34 2006.145.15:38:51.29/va/05,04,usb,yes,28,29 2006.145.15:38:51.29/va/06,04,usb,yes,32,31 2006.145.15:38:51.29/va/07,04,usb,yes,32,33 2006.145.15:38:51.29/va/08,04,usb,yes,27,33 2006.145.15:38:51.52/valo/01,524.99,yes,locked 2006.145.15:38:51.52/valo/02,534.99,yes,locked 2006.145.15:38:51.52/valo/03,564.99,yes,locked 2006.145.15:38:51.52/valo/04,624.99,yes,locked 2006.145.15:38:51.52/valo/05,734.99,yes,locked 2006.145.15:38:51.52/valo/06,814.99,yes,locked 2006.145.15:38:51.52/valo/07,864.99,yes,locked 2006.145.15:38:51.52/valo/08,884.99,yes,locked 2006.145.15:38:52.61/vb/01,03,usb,yes,36,34 2006.145.15:38:52.61/vb/02,04,usb,yes,32,32 2006.145.15:38:52.61/vb/03,04,usb,yes,29,32 2006.145.15:38:52.61/vb/04,04,usb,yes,33,32 2006.145.15:38:52.61/vb/05,04,usb,yes,26,28 2006.145.15:38:52.61/vb/06,04,usb,yes,30,26 2006.145.15:38:52.61/vb/07,04,usb,yes,30,30 2006.145.15:38:52.61/vb/08,04,usb,yes,28,31 2006.145.15:38:52.85/vblo/01,629.99,yes,locked 2006.145.15:38:52.85/vblo/02,634.99,yes,locked 2006.145.15:38:52.85/vblo/03,649.99,yes,locked 2006.145.15:38:52.85/vblo/04,679.99,yes,locked 2006.145.15:38:52.85/vblo/05,709.99,yes,locked 2006.145.15:38:52.85/vblo/06,719.99,yes,locked 2006.145.15:38:52.85/vblo/07,734.99,yes,locked 2006.145.15:38:52.85/vblo/08,744.99,yes,locked 2006.145.15:38:53.00/vabw/8 2006.145.15:38:53.15/vbbw/8 2006.145.15:38:53.28/xfe/off,on,14.7 2006.145.15:38:53.66/ifatt/23,28,28,28 2006.145.15:38:54.07/fmout-gps/S +4.0E-08 2006.145.15:38:54.11:!2006.145.15:40:30 2006.145.15:40:30.00:data_valid=off 2006.145.15:40:30.00:"et 2006.145.15:40:30.00:!+3s 2006.145.15:40:33.02:"tape 2006.145.15:40:33.02:postob 2006.145.15:40:33.10/cable/+6.5486E-03 2006.145.15:40:33.10/wx/15.71,1020.3,86 2006.145.15:40:34.07/fmout-gps/S +4.0E-08 2006.145.15:40:34.07:scan_name=145-1545,jd0605,120 2006.145.15:40:34.07:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.145.15:40:35.14#flagr#flagr/antenna,new-source 2006.145.15:40:35.14:checkk5 2006.145.15:40:35.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.15:40:36.08/chk_autoobs//k5ts2/ autoobs is running! 2006.145.15:40:36.51/chk_autoobs//k5ts3/ autoobs is running! 2006.145.15:40:36.95/chk_autoobs//k5ts4/ autoobs is running! 2006.145.15:40:37.37/chk_obsdata//k5ts1/T1451538??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.15:40:37.80/chk_obsdata//k5ts2/T1451538??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.15:40:38.23/chk_obsdata//k5ts3/T1451538??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.15:40:38.67/chk_obsdata//k5ts4/T1451538??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.15:40:39.42/k5log//k5ts1_log_newline 2006.145.15:40:40.16/k5log//k5ts2_log_newline 2006.145.15:40:40.91/k5log//k5ts3_log_newline 2006.145.15:40:41.65/k5log//k5ts4_log_newline 2006.145.15:40:41.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.15:40:41.67:setupk4=1 2006.145.15:40:41.67$setupk4/echo=on 2006.145.15:40:41.67$setupk4/pcalon 2006.145.15:40:41.67$pcalon/"no phase cal control is implemented here 2006.145.15:40:41.67$setupk4/"tpicd=stop 2006.145.15:40:41.67$setupk4/"rec=synch_on 2006.145.15:40:41.67$setupk4/"rec_mode=128 2006.145.15:40:41.67$setupk4/!* 2006.145.15:40:41.67$setupk4/recpk4 2006.145.15:40:41.67$recpk4/recpatch= 2006.145.15:40:41.68$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.15:40:41.68$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.15:40:41.68$setupk4/vck44 2006.145.15:40:41.68$vck44/valo=1,524.99 2006.145.15:40:41.68#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.15:40:41.68#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.15:40:41.68#ibcon#ireg 17 cls_cnt 0 2006.145.15:40:41.68#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.15:40:41.68#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.15:40:41.68#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.15:40:41.72#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.15:40:41.77#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.15:40:41.77#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.15:40:41.77#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.15:40:41.77#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.15:40:41.77$vck44/va=1,8 2006.145.15:40:41.77#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.15:40:41.77#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.15:40:41.77#ibcon#ireg 11 cls_cnt 2 2006.145.15:40:41.77#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.15:40:41.77#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.15:40:41.77#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.15:40:41.79#ibcon#[25=AT01-08\r\n] 2006.145.15:40:41.82#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.15:40:41.82#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.15:40:41.82#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.15:40:41.82#ibcon#ireg 7 cls_cnt 0 2006.145.15:40:41.82#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.15:40:41.84#abcon#<5=/08 0.9 1.8 15.71 861020.3\r\n> 2006.145.15:40:41.86#abcon#{5=INTERFACE CLEAR} 2006.145.15:40:41.92#abcon#[5=S1D000X0/0*\r\n] 2006.145.15:40:41.94#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.15:40:41.94#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.15:40:41.96#ibcon#[25=USB\r\n] 2006.145.15:40:41.99#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.15:40:41.99#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.15:40:41.99#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.15:40:41.99#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.15:40:41.99$vck44/valo=2,534.99 2006.145.15:40:41.99#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.15:40:41.99#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.15:40:41.99#ibcon#ireg 17 cls_cnt 0 2006.145.15:40:41.99#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.15:40:41.99#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.15:40:41.99#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.15:40:42.01#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.15:40:42.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.15:40:42.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.15:40:42.05#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.15:40:42.05#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.15:40:42.05$vck44/va=2,7 2006.145.15:40:42.05#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.15:40:42.05#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.15:40:42.05#ibcon#ireg 11 cls_cnt 2 2006.145.15:40:42.05#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.15:40:42.11#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.15:40:42.11#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.15:40:42.13#ibcon#[25=AT02-07\r\n] 2006.145.15:40:42.16#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.15:40:42.16#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.15:40:42.16#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.15:40:42.16#ibcon#ireg 7 cls_cnt 0 2006.145.15:40:42.16#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.15:40:42.28#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.15:40:42.28#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.15:40:42.30#ibcon#[25=USB\r\n] 2006.145.15:40:42.33#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.15:40:42.33#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.15:40:42.33#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.15:40:42.33#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.15:40:42.33$vck44/valo=3,564.99 2006.145.15:40:42.33#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.15:40:42.33#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.15:40:42.33#ibcon#ireg 17 cls_cnt 0 2006.145.15:40:42.33#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.15:40:42.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.15:40:42.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.15:40:42.35#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.15:40:42.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.15:40:42.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.15:40:42.39#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.15:40:42.39#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.15:40:42.39$vck44/va=3,8 2006.145.15:40:42.39#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.15:40:42.39#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.15:40:42.39#ibcon#ireg 11 cls_cnt 2 2006.145.15:40:42.39#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.15:40:42.45#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.15:40:42.45#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.15:40:42.47#ibcon#[25=AT03-08\r\n] 2006.145.15:40:42.50#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.15:40:42.50#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.15:40:42.50#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.15:40:42.50#ibcon#ireg 7 cls_cnt 0 2006.145.15:40:42.50#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.15:40:42.62#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.15:40:42.62#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.15:40:42.64#ibcon#[25=USB\r\n] 2006.145.15:40:42.67#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.15:40:42.67#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.15:40:42.67#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.15:40:42.67#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.15:40:42.67$vck44/valo=4,624.99 2006.145.15:40:42.67#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.15:40:42.67#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.15:40:42.67#ibcon#ireg 17 cls_cnt 0 2006.145.15:40:42.67#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.15:40:42.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.15:40:42.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.15:40:42.69#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.15:40:42.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.15:40:42.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.15:40:42.73#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.15:40:42.73#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.15:40:42.73$vck44/va=4,7 2006.145.15:40:42.73#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.15:40:42.73#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.15:40:42.73#ibcon#ireg 11 cls_cnt 2 2006.145.15:40:42.73#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.15:40:42.79#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.15:40:42.79#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.15:40:42.81#ibcon#[25=AT04-07\r\n] 2006.145.15:40:42.84#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.15:40:42.84#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.15:40:42.84#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.15:40:42.84#ibcon#ireg 7 cls_cnt 0 2006.145.15:40:42.84#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.15:40:42.96#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.15:40:42.96#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.15:40:42.98#ibcon#[25=USB\r\n] 2006.145.15:40:43.01#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.15:40:43.01#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.15:40:43.01#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.15:40:43.01#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.15:40:43.01$vck44/valo=5,734.99 2006.145.15:40:43.01#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.15:40:43.01#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.15:40:43.01#ibcon#ireg 17 cls_cnt 0 2006.145.15:40:43.01#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.15:40:43.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.15:40:43.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.15:40:43.03#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.15:40:43.07#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.15:40:43.07#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.15:40:43.07#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.15:40:43.07#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.15:40:43.07$vck44/va=5,4 2006.145.15:40:43.07#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.15:40:43.07#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.15:40:43.07#ibcon#ireg 11 cls_cnt 2 2006.145.15:40:43.07#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.15:40:43.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.15:40:43.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.15:40:43.15#ibcon#[25=AT05-04\r\n] 2006.145.15:40:43.18#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.15:40:43.18#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.15:40:43.18#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.15:40:43.18#ibcon#ireg 7 cls_cnt 0 2006.145.15:40:43.18#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.15:40:43.30#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.15:40:43.30#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.15:40:43.32#ibcon#[25=USB\r\n] 2006.145.15:40:43.35#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.15:40:43.35#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.15:40:43.35#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.15:40:43.35#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.15:40:43.35$vck44/valo=6,814.99 2006.145.15:40:43.35#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.15:40:43.35#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.15:40:43.35#ibcon#ireg 17 cls_cnt 0 2006.145.15:40:43.35#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.15:40:43.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.15:40:43.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.15:40:43.37#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.15:40:43.41#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.15:40:43.41#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.15:40:43.41#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.15:40:43.41#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.15:40:43.41$vck44/va=6,4 2006.145.15:40:43.41#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.15:40:43.41#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.15:40:43.41#ibcon#ireg 11 cls_cnt 2 2006.145.15:40:43.41#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.15:40:43.47#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.15:40:43.47#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.15:40:43.49#ibcon#[25=AT06-04\r\n] 2006.145.15:40:43.52#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.15:40:43.52#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.15:40:43.52#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.15:40:43.52#ibcon#ireg 7 cls_cnt 0 2006.145.15:40:43.52#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.15:40:43.64#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.15:40:43.64#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.15:40:43.66#ibcon#[25=USB\r\n] 2006.145.15:40:43.69#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.15:40:43.69#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.15:40:43.69#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.15:40:43.69#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.15:40:43.69$vck44/valo=7,864.99 2006.145.15:40:43.69#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.15:40:43.69#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.15:40:43.69#ibcon#ireg 17 cls_cnt 0 2006.145.15:40:43.69#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:40:43.69#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:40:43.69#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:40:43.71#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.15:40:43.75#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:40:43.75#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:40:43.75#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.15:40:43.75#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.15:40:43.75$vck44/va=7,4 2006.145.15:40:43.75#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.15:40:43.75#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.15:40:43.75#ibcon#ireg 11 cls_cnt 2 2006.145.15:40:43.75#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.15:40:43.81#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.15:40:43.81#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.15:40:43.83#ibcon#[25=AT07-04\r\n] 2006.145.15:40:43.86#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.15:40:43.86#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.15:40:43.86#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.15:40:43.86#ibcon#ireg 7 cls_cnt 0 2006.145.15:40:43.86#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.15:40:43.98#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.15:40:43.98#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.15:40:44.00#ibcon#[25=USB\r\n] 2006.145.15:40:44.03#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.15:40:44.03#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.15:40:44.03#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.15:40:44.03#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.15:40:44.03$vck44/valo=8,884.99 2006.145.15:40:44.03#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.15:40:44.03#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.15:40:44.03#ibcon#ireg 17 cls_cnt 0 2006.145.15:40:44.03#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.15:40:44.03#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.15:40:44.03#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.15:40:44.05#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.15:40:44.09#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.15:40:44.09#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.15:40:44.09#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.15:40:44.09#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.15:40:44.09$vck44/va=8,4 2006.145.15:40:44.09#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.15:40:44.09#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.15:40:44.09#ibcon#ireg 11 cls_cnt 2 2006.145.15:40:44.09#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.15:40:44.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.15:40:44.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.15:40:44.17#ibcon#[25=AT08-04\r\n] 2006.145.15:40:44.20#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.15:40:44.20#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.15:40:44.20#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.15:40:44.20#ibcon#ireg 7 cls_cnt 0 2006.145.15:40:44.20#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.15:40:44.32#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.15:40:44.32#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.15:40:44.34#ibcon#[25=USB\r\n] 2006.145.15:40:44.37#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.15:40:44.37#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.15:40:44.37#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.15:40:44.37#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.15:40:44.37$vck44/vblo=1,629.99 2006.145.15:40:44.37#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.15:40:44.37#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.15:40:44.37#ibcon#ireg 17 cls_cnt 0 2006.145.15:40:44.37#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.15:40:44.37#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.15:40:44.37#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.15:40:44.39#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.15:40:44.43#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.15:40:44.43#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.15:40:44.43#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.15:40:44.43#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.15:40:44.43$vck44/vb=1,3 2006.145.15:40:44.43#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.15:40:44.43#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.15:40:44.43#ibcon#ireg 11 cls_cnt 2 2006.145.15:40:44.43#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.15:40:44.43#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.15:40:44.43#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.15:40:44.45#ibcon#[27=AT01-03\r\n] 2006.145.15:40:44.48#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.15:40:44.48#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.15:40:44.48#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.15:40:44.48#ibcon#ireg 7 cls_cnt 0 2006.145.15:40:44.48#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.15:40:44.60#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.15:40:44.60#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.15:40:44.62#ibcon#[27=USB\r\n] 2006.145.15:40:44.65#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.15:40:44.65#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.15:40:44.65#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.15:40:44.65#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.15:40:44.65$vck44/vblo=2,634.99 2006.145.15:40:44.65#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.15:40:44.65#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.15:40:44.65#ibcon#ireg 17 cls_cnt 0 2006.145.15:40:44.65#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.15:40:44.65#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.15:40:44.65#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.15:40:44.67#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.15:40:44.71#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.15:40:44.71#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.15:40:44.71#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.15:40:44.71#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.15:40:44.71$vck44/vb=2,4 2006.145.15:40:44.71#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.15:40:44.71#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.15:40:44.71#ibcon#ireg 11 cls_cnt 2 2006.145.15:40:44.71#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.15:40:44.77#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.15:40:44.77#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.15:40:44.79#ibcon#[27=AT02-04\r\n] 2006.145.15:40:44.82#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.15:40:44.82#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.15:40:44.82#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.15:40:44.82#ibcon#ireg 7 cls_cnt 0 2006.145.15:40:44.82#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.15:40:44.94#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.15:40:44.94#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.15:40:44.96#ibcon#[27=USB\r\n] 2006.145.15:40:44.99#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.15:40:44.99#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.15:40:44.99#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.15:40:44.99#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.15:40:44.99$vck44/vblo=3,649.99 2006.145.15:40:44.99#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.15:40:44.99#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.15:40:44.99#ibcon#ireg 17 cls_cnt 0 2006.145.15:40:44.99#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.15:40:44.99#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.15:40:44.99#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.15:40:45.01#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.15:40:45.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.15:40:45.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.15:40:45.05#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.15:40:45.05#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.15:40:45.05$vck44/vb=3,4 2006.145.15:40:45.05#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.15:40:45.05#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.15:40:45.05#ibcon#ireg 11 cls_cnt 2 2006.145.15:40:45.05#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.15:40:45.11#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.15:40:45.11#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.15:40:45.13#ibcon#[27=AT03-04\r\n] 2006.145.15:40:45.16#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.15:40:45.16#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.15:40:45.16#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.15:40:45.16#ibcon#ireg 7 cls_cnt 0 2006.145.15:40:45.16#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.15:40:45.28#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.15:40:45.28#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.15:40:45.30#ibcon#[27=USB\r\n] 2006.145.15:40:45.33#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.15:40:45.33#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.15:40:45.33#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.15:40:45.33#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.15:40:45.33$vck44/vblo=4,679.99 2006.145.15:40:45.33#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.15:40:45.33#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.15:40:45.33#ibcon#ireg 17 cls_cnt 0 2006.145.15:40:45.33#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.15:40:45.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.15:40:45.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.15:40:45.35#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.15:40:45.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.15:40:45.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.15:40:45.39#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.15:40:45.39#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.15:40:45.39$vck44/vb=4,4 2006.145.15:40:45.39#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.15:40:45.39#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.15:40:45.39#ibcon#ireg 11 cls_cnt 2 2006.145.15:40:45.39#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.15:40:45.45#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.15:40:45.45#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.15:40:45.47#ibcon#[27=AT04-04\r\n] 2006.145.15:40:45.50#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.15:40:45.50#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.15:40:45.50#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.15:40:45.50#ibcon#ireg 7 cls_cnt 0 2006.145.15:40:45.50#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.15:40:45.62#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.15:40:45.62#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.15:40:45.64#ibcon#[27=USB\r\n] 2006.145.15:40:45.67#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.15:40:45.67#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.15:40:45.67#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.15:40:45.67#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.15:40:45.67$vck44/vblo=5,709.99 2006.145.15:40:45.67#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.15:40:45.67#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.15:40:45.67#ibcon#ireg 17 cls_cnt 0 2006.145.15:40:45.67#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.15:40:45.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.15:40:45.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.15:40:45.69#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.15:40:45.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.15:40:45.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.15:40:45.73#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.15:40:45.73#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.15:40:45.73$vck44/vb=5,4 2006.145.15:40:45.73#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.15:40:45.73#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.15:40:45.73#ibcon#ireg 11 cls_cnt 2 2006.145.15:40:45.73#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.15:40:45.79#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.15:40:45.79#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.15:40:45.81#ibcon#[27=AT05-04\r\n] 2006.145.15:40:45.84#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.15:40:45.84#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.15:40:45.84#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.15:40:45.84#ibcon#ireg 7 cls_cnt 0 2006.145.15:40:45.84#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.15:40:45.96#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.15:40:45.96#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.15:40:45.98#ibcon#[27=USB\r\n] 2006.145.15:40:46.01#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.15:40:46.01#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.15:40:46.01#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.15:40:46.01#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.15:40:46.01$vck44/vblo=6,719.99 2006.145.15:40:46.01#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.15:40:46.01#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.15:40:46.01#ibcon#ireg 17 cls_cnt 0 2006.145.15:40:46.01#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.15:40:46.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.15:40:46.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.15:40:46.03#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.15:40:46.07#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.15:40:46.07#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.15:40:46.07#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.15:40:46.07#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.15:40:46.07$vck44/vb=6,4 2006.145.15:40:46.07#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.15:40:46.07#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.15:40:46.07#ibcon#ireg 11 cls_cnt 2 2006.145.15:40:46.07#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.15:40:46.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.15:40:46.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.15:40:46.15#ibcon#[27=AT06-04\r\n] 2006.145.15:40:46.18#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.15:40:46.18#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.15:40:46.18#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.15:40:46.18#ibcon#ireg 7 cls_cnt 0 2006.145.15:40:46.18#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.15:40:46.30#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.15:40:46.30#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.15:40:46.32#ibcon#[27=USB\r\n] 2006.145.15:40:46.35#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.15:40:46.35#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.15:40:46.35#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.15:40:46.35#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.15:40:46.35$vck44/vblo=7,734.99 2006.145.15:40:46.35#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.15:40:46.35#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.15:40:46.35#ibcon#ireg 17 cls_cnt 0 2006.145.15:40:46.35#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.15:40:46.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.15:40:46.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.15:40:46.37#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.15:40:46.41#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.15:40:46.41#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.15:40:46.41#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.15:40:46.41#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.15:40:46.41$vck44/vb=7,4 2006.145.15:40:46.41#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.15:40:46.41#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.15:40:46.41#ibcon#ireg 11 cls_cnt 2 2006.145.15:40:46.41#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.15:40:46.47#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.15:40:46.47#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.15:40:46.49#ibcon#[27=AT07-04\r\n] 2006.145.15:40:46.52#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.15:40:46.52#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.15:40:46.52#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.15:40:46.52#ibcon#ireg 7 cls_cnt 0 2006.145.15:40:46.52#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.15:40:46.64#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.15:40:46.64#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.15:40:46.66#ibcon#[27=USB\r\n] 2006.145.15:40:46.69#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.15:40:46.69#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.15:40:46.69#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.15:40:46.69#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.15:40:46.69$vck44/vblo=8,744.99 2006.145.15:40:46.69#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.15:40:46.69#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.15:40:46.69#ibcon#ireg 17 cls_cnt 0 2006.145.15:40:46.69#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:40:46.69#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:40:46.69#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:40:46.71#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.15:40:46.75#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:40:46.75#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:40:46.75#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.15:40:46.75#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.15:40:46.75$vck44/vb=8,4 2006.145.15:40:46.75#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.15:40:46.75#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.15:40:46.75#ibcon#ireg 11 cls_cnt 2 2006.145.15:40:46.75#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.15:40:46.81#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.15:40:46.81#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.15:40:46.83#ibcon#[27=AT08-04\r\n] 2006.145.15:40:46.86#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.15:40:46.86#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.15:40:46.86#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.15:40:46.86#ibcon#ireg 7 cls_cnt 0 2006.145.15:40:46.86#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.15:40:46.98#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.15:40:46.98#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.15:40:47.00#ibcon#[27=USB\r\n] 2006.145.15:40:47.03#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.15:40:47.03#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.15:40:47.03#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.15:40:47.03#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.15:40:47.03$vck44/vabw=wide 2006.145.15:40:47.03#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.15:40:47.03#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.15:40:47.03#ibcon#ireg 8 cls_cnt 0 2006.145.15:40:47.03#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.15:40:47.03#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.15:40:47.03#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.15:40:47.05#ibcon#[25=BW32\r\n] 2006.145.15:40:47.08#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.15:40:47.08#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.15:40:47.08#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.15:40:47.08#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.15:40:47.08$vck44/vbbw=wide 2006.145.15:40:47.08#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.15:40:47.08#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.15:40:47.08#ibcon#ireg 8 cls_cnt 0 2006.145.15:40:47.08#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.15:40:47.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.15:40:47.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.15:40:47.17#ibcon#[27=BW32\r\n] 2006.145.15:40:47.20#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.15:40:47.20#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.15:40:47.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.15:40:47.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.15:40:47.20$setupk4/ifdk4 2006.145.15:40:47.20$ifdk4/lo= 2006.145.15:40:47.20$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.15:40:47.20$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.15:40:47.20$ifdk4/patch= 2006.145.15:40:47.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.15:40:47.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.15:40:47.20$setupk4/!*+20s 2006.145.15:40:52.01#abcon#<5=/08 0.9 1.8 15.71 861020.4\r\n> 2006.145.15:40:52.03#abcon#{5=INTERFACE CLEAR} 2006.145.15:40:52.09#abcon#[5=S1D000X0/0*\r\n] 2006.145.15:41:01.68$setupk4/"tpicd 2006.145.15:41:01.68$setupk4/echo=off 2006.145.15:41:01.68$setupk4/xlog=off 2006.145.15:41:01.68:!2006.145.15:44:51 2006.145.15:41:12.14#trakl#Source acquired 2006.145.15:41:12.14#flagr#flagr/antenna,acquired 2006.145.15:44:51.02:preob 2006.145.15:44:52.15/onsource/TRACKING 2006.145.15:44:52.15:!2006.145.15:45:01 2006.145.15:45:01.02:"tape 2006.145.15:45:01.02:"st=record 2006.145.15:45:01.02:data_valid=on 2006.145.15:45:01.02:midob 2006.145.15:45:02.15/onsource/TRACKING 2006.145.15:45:02.15/wx/15.77,1020.4,86 2006.145.15:45:02.32/cable/+6.5494E-03 2006.145.15:45:03.41/va/01,08,usb,yes,30,32 2006.145.15:45:03.41/va/02,07,usb,yes,32,33 2006.145.15:45:03.41/va/03,08,usb,yes,29,31 2006.145.15:45:03.41/va/04,07,usb,yes,34,35 2006.145.15:45:03.41/va/05,04,usb,yes,29,30 2006.145.15:45:03.41/va/06,04,usb,yes,33,33 2006.145.15:45:03.41/va/07,04,usb,yes,33,34 2006.145.15:45:03.41/va/08,04,usb,yes,28,34 2006.145.15:45:03.64/valo/01,524.99,yes,locked 2006.145.15:45:03.64/valo/02,534.99,yes,locked 2006.145.15:45:03.64/valo/03,564.99,yes,locked 2006.145.15:45:03.64/valo/04,624.99,yes,locked 2006.145.15:45:03.64/valo/05,734.99,yes,locked 2006.145.15:45:03.64/valo/06,814.99,yes,locked 2006.145.15:45:03.64/valo/07,864.99,yes,locked 2006.145.15:45:03.64/valo/08,884.99,yes,locked 2006.145.15:45:04.73/vb/01,03,usb,yes,37,35 2006.145.15:45:04.73/vb/02,04,usb,yes,33,33 2006.145.15:45:04.73/vb/03,04,usb,yes,29,32 2006.145.15:45:04.73/vb/04,04,usb,yes,34,33 2006.145.15:45:04.73/vb/05,04,usb,yes,26,29 2006.145.15:45:04.73/vb/06,04,usb,yes,31,27 2006.145.15:45:04.73/vb/07,04,usb,yes,31,30 2006.145.15:45:04.73/vb/08,04,usb,yes,28,31 2006.145.15:45:04.96/vblo/01,629.99,yes,locked 2006.145.15:45:04.96/vblo/02,634.99,yes,locked 2006.145.15:45:04.96/vblo/03,649.99,yes,locked 2006.145.15:45:04.96/vblo/04,679.99,yes,locked 2006.145.15:45:04.96/vblo/05,709.99,yes,locked 2006.145.15:45:04.96/vblo/06,719.99,yes,locked 2006.145.15:45:04.96/vblo/07,734.99,yes,locked 2006.145.15:45:04.96/vblo/08,744.99,yes,locked 2006.145.15:45:05.11/vabw/8 2006.145.15:45:05.26/vbbw/8 2006.145.15:45:05.35/xfe/off,on,14.2 2006.145.15:45:05.72/ifatt/23,28,28,28 2006.145.15:45:06.07/fmout-gps/S +3.7E-08 2006.145.15:45:06.12:!2006.145.15:47:01 2006.145.15:47:01.01:data_valid=off 2006.145.15:47:01.02:"et 2006.145.15:47:01.02:!+3s 2006.145.15:47:04.05:"tape 2006.145.15:47:04.09:postob 2006.145.15:47:04.25/cable/+6.5494E-03 2006.145.15:47:04.26/wx/15.77,1020.4,86 2006.145.15:47:04.34/fmout-gps/S +3.7E-08 2006.145.15:47:04.35:scan_name=145-1548,jd0605,430 2006.145.15:47:04.35:source=1308+326,131028.66,322043.8,2000.0,cw 2006.145.15:47:05.13#flagr#flagr/antenna,new-source 2006.145.15:47:05.14:checkk5 2006.145.15:47:05.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.15:47:06.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.15:47:06.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.15:47:06.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.15:47:07.32/chk_obsdata//k5ts1/T1451545??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.15:47:07.74/chk_obsdata//k5ts2/T1451545??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.15:47:08.20/chk_obsdata//k5ts3/T1451545??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.15:47:08.63/chk_obsdata//k5ts4/T1451545??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.15:47:09.39/k5log//k5ts1_log_newline 2006.145.15:47:10.13/k5log//k5ts2_log_newline 2006.145.15:47:10.87/k5log//k5ts3_log_newline 2006.145.15:47:11.62/k5log//k5ts4_log_newline 2006.145.15:47:11.64/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.15:47:11.64:setupk4=1 2006.145.15:47:11.64$setupk4/echo=on 2006.145.15:47:11.65$setupk4/pcalon 2006.145.15:47:11.65$pcalon/"no phase cal control is implemented here 2006.145.15:47:11.65$setupk4/"tpicd=stop 2006.145.15:47:11.65$setupk4/"rec=synch_on 2006.145.15:47:11.65$setupk4/"rec_mode=128 2006.145.15:47:11.65$setupk4/!* 2006.145.15:47:11.65$setupk4/recpk4 2006.145.15:47:11.65$recpk4/recpatch= 2006.145.15:47:11.65$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.15:47:11.65$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.15:47:11.65$setupk4/vck44 2006.145.15:47:11.65$vck44/valo=1,524.99 2006.145.15:47:11.65#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.15:47:11.65#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.15:47:11.65#ibcon#ireg 17 cls_cnt 0 2006.145.15:47:11.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.15:47:11.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.15:47:11.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.15:47:11.69#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.15:47:11.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.15:47:11.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.15:47:11.73#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.15:47:11.73#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.15:47:11.73$vck44/va=1,8 2006.145.15:47:11.73#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.15:47:11.73#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.15:47:11.73#ibcon#ireg 11 cls_cnt 2 2006.145.15:47:11.73#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.15:47:11.73#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.15:47:11.73#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.15:47:11.75#ibcon#[25=AT01-08\r\n] 2006.145.15:47:11.78#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.15:47:11.78#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.15:47:11.78#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.15:47:11.78#ibcon#ireg 7 cls_cnt 0 2006.145.15:47:11.78#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.15:47:11.91#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.15:47:11.91#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.15:47:11.92#ibcon#[25=USB\r\n] 2006.145.15:47:11.95#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.15:47:11.95#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.15:47:11.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.15:47:11.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.15:47:11.95$vck44/valo=2,534.99 2006.145.15:47:11.95#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.15:47:11.95#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.15:47:11.95#ibcon#ireg 17 cls_cnt 0 2006.145.15:47:11.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.15:47:11.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.15:47:11.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.15:47:11.98#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.15:47:12.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.15:47:12.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.15:47:12.02#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.15:47:12.02#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.15:47:12.02$vck44/va=2,7 2006.145.15:47:12.02#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.15:47:12.02#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.15:47:12.02#ibcon#ireg 11 cls_cnt 2 2006.145.15:47:12.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.15:47:12.07#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.15:47:12.07#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.15:47:12.09#ibcon#[25=AT02-07\r\n] 2006.145.15:47:12.12#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.15:47:12.12#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.15:47:12.12#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.15:47:12.12#ibcon#ireg 7 cls_cnt 0 2006.145.15:47:12.12#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.15:47:12.24#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.15:47:12.24#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.15:47:12.26#ibcon#[25=USB\r\n] 2006.145.15:47:12.29#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.15:47:12.29#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.15:47:12.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.15:47:12.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.15:47:12.29$vck44/valo=3,564.99 2006.145.15:47:12.29#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.15:47:12.29#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.15:47:12.29#ibcon#ireg 17 cls_cnt 0 2006.145.15:47:12.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.15:47:12.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.15:47:12.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.15:47:12.31#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.15:47:12.35#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.15:47:12.35#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.15:47:12.35#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.15:47:12.35#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.15:47:12.35$vck44/va=3,8 2006.145.15:47:12.35#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.15:47:12.35#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.15:47:12.35#ibcon#ireg 11 cls_cnt 2 2006.145.15:47:12.35#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.15:47:12.41#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.15:47:12.41#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.15:47:12.43#ibcon#[25=AT03-08\r\n] 2006.145.15:47:12.46#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.15:47:12.46#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.15:47:12.46#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.15:47:12.46#ibcon#ireg 7 cls_cnt 0 2006.145.15:47:12.46#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.15:47:12.58#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.15:47:12.58#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.15:47:12.60#ibcon#[25=USB\r\n] 2006.145.15:47:12.63#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.15:47:12.63#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.15:47:12.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.15:47:12.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.15:47:12.63$vck44/valo=4,624.99 2006.145.15:47:12.63#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.15:47:12.63#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.15:47:12.63#ibcon#ireg 17 cls_cnt 0 2006.145.15:47:12.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.15:47:12.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.15:47:12.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.15:47:12.65#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.15:47:12.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.15:47:12.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.15:47:12.69#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.15:47:12.69#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.15:47:12.69$vck44/va=4,7 2006.145.15:47:12.69#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.15:47:12.69#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.15:47:12.69#ibcon#ireg 11 cls_cnt 2 2006.145.15:47:12.69#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.15:47:12.75#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.15:47:12.75#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.15:47:12.77#ibcon#[25=AT04-07\r\n] 2006.145.15:47:12.80#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.15:47:12.80#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.15:47:12.80#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.15:47:12.80#ibcon#ireg 7 cls_cnt 0 2006.145.15:47:12.80#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.15:47:12.92#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.15:47:12.92#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.15:47:12.94#ibcon#[25=USB\r\n] 2006.145.15:47:12.97#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.15:47:12.97#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.15:47:12.97#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.15:47:12.97#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.15:47:12.97$vck44/valo=5,734.99 2006.145.15:47:12.97#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.15:47:12.97#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.15:47:12.97#ibcon#ireg 17 cls_cnt 0 2006.145.15:47:12.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.15:47:12.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.15:47:12.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.15:47:12.99#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.15:47:13.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.15:47:13.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.15:47:13.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.15:47:13.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.15:47:13.03$vck44/va=5,4 2006.145.15:47:13.03#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.15:47:13.03#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.15:47:13.03#ibcon#ireg 11 cls_cnt 2 2006.145.15:47:13.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.15:47:13.09#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.15:47:13.09#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.15:47:13.11#ibcon#[25=AT05-04\r\n] 2006.145.15:47:13.15#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.15:47:13.15#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.15:47:13.15#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.15:47:13.15#ibcon#ireg 7 cls_cnt 0 2006.145.15:47:13.15#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.15:47:13.26#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.15:47:13.26#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.15:47:13.28#ibcon#[25=USB\r\n] 2006.145.15:47:13.31#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.15:47:13.31#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.15:47:13.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.15:47:13.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.15:47:13.31$vck44/valo=6,814.99 2006.145.15:47:13.31#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.15:47:13.31#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.15:47:13.31#ibcon#ireg 17 cls_cnt 0 2006.145.15:47:13.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.15:47:13.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.15:47:13.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.15:47:13.33#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.15:47:13.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.15:47:13.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.15:47:13.37#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.15:47:13.37#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.15:47:13.37$vck44/va=6,4 2006.145.15:47:13.37#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.15:47:13.37#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.15:47:13.37#ibcon#ireg 11 cls_cnt 2 2006.145.15:47:13.37#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.15:47:13.43#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.15:47:13.43#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.15:47:13.45#ibcon#[25=AT06-04\r\n] 2006.145.15:47:13.48#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.15:47:13.48#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.15:47:13.48#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.15:47:13.48#ibcon#ireg 7 cls_cnt 0 2006.145.15:47:13.48#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.15:47:13.60#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.15:47:13.60#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.15:47:13.62#ibcon#[25=USB\r\n] 2006.145.15:47:13.65#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.15:47:13.65#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.15:47:13.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.15:47:13.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.15:47:13.65$vck44/valo=7,864.99 2006.145.15:47:13.65#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.15:47:13.65#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.15:47:13.65#ibcon#ireg 17 cls_cnt 0 2006.145.15:47:13.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.15:47:13.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.15:47:13.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.15:47:13.67#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.15:47:13.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.15:47:13.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.15:47:13.71#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.15:47:13.71#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.15:47:13.71$vck44/va=7,4 2006.145.15:47:13.71#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.15:47:13.71#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.15:47:13.71#ibcon#ireg 11 cls_cnt 2 2006.145.15:47:13.71#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.15:47:13.77#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.15:47:13.77#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.15:47:13.79#ibcon#[25=AT07-04\r\n] 2006.145.15:47:13.82#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.15:47:13.82#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.15:47:13.82#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.15:47:13.82#ibcon#ireg 7 cls_cnt 0 2006.145.15:47:13.82#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.15:47:13.94#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.15:47:13.94#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.15:47:13.96#ibcon#[25=USB\r\n] 2006.145.15:47:13.99#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.15:47:13.99#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.15:47:13.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.15:47:13.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.15:47:13.99$vck44/valo=8,884.99 2006.145.15:47:13.99#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.15:47:13.99#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.15:47:13.99#ibcon#ireg 17 cls_cnt 0 2006.145.15:47:13.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.15:47:13.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.15:47:13.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.15:47:14.01#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.15:47:14.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.15:47:14.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.15:47:14.05#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.15:47:14.05#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.15:47:14.05$vck44/va=8,4 2006.145.15:47:14.05#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.15:47:14.05#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.15:47:14.05#ibcon#ireg 11 cls_cnt 2 2006.145.15:47:14.05#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.15:47:14.11#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.15:47:14.11#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.15:47:14.13#ibcon#[25=AT08-04\r\n] 2006.145.15:47:14.16#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.15:47:14.16#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.15:47:14.16#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.15:47:14.16#ibcon#ireg 7 cls_cnt 0 2006.145.15:47:14.16#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.15:47:14.28#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.15:47:14.28#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.15:47:14.31#ibcon#[25=USB\r\n] 2006.145.15:47:14.33#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.15:47:14.33#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.15:47:14.33#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.15:47:14.33#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.15:47:14.33$vck44/vblo=1,629.99 2006.145.15:47:14.33#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.15:47:14.33#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.15:47:14.33#ibcon#ireg 17 cls_cnt 0 2006.145.15:47:14.33#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.15:47:14.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.15:47:14.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.15:47:14.35#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.15:47:14.40#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.15:47:14.40#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.15:47:14.40#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.15:47:14.40#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.15:47:14.40$vck44/vb=1,3 2006.145.15:47:14.40#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.15:47:14.40#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.15:47:14.40#ibcon#ireg 11 cls_cnt 2 2006.145.15:47:14.40#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.15:47:14.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.15:47:14.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.15:47:14.41#ibcon#[27=AT01-03\r\n] 2006.145.15:47:14.44#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.15:47:14.44#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.15:47:14.44#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.15:47:14.44#ibcon#ireg 7 cls_cnt 0 2006.145.15:47:14.44#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.15:47:14.56#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.15:47:14.56#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.15:47:14.58#ibcon#[27=USB\r\n] 2006.145.15:47:14.61#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.15:47:14.61#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.15:47:14.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.15:47:14.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.15:47:14.61$vck44/vblo=2,634.99 2006.145.15:47:14.61#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.15:47:14.61#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.15:47:14.61#ibcon#ireg 17 cls_cnt 0 2006.145.15:47:14.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.15:47:14.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.15:47:14.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.15:47:14.63#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.15:47:14.67#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.15:47:14.67#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.15:47:14.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.15:47:14.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.15:47:14.67$vck44/vb=2,4 2006.145.15:47:14.67#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.15:47:14.67#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.15:47:14.67#ibcon#ireg 11 cls_cnt 2 2006.145.15:47:14.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.15:47:14.73#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.15:47:14.73#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.15:47:14.75#ibcon#[27=AT02-04\r\n] 2006.145.15:47:14.78#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.15:47:14.78#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.15:47:14.78#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.15:47:14.78#ibcon#ireg 7 cls_cnt 0 2006.145.15:47:14.78#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.15:47:14.90#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.15:47:14.90#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.15:47:14.92#ibcon#[27=USB\r\n] 2006.145.15:47:14.95#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.15:47:14.95#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.15:47:14.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.15:47:14.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.15:47:14.95$vck44/vblo=3,649.99 2006.145.15:47:14.95#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.15:47:14.95#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.15:47:14.95#ibcon#ireg 17 cls_cnt 0 2006.145.15:47:14.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.15:47:14.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.15:47:14.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.15:47:14.97#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.15:47:15.01#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.15:47:15.01#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.15:47:15.01#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.15:47:15.01#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.15:47:15.01$vck44/vb=3,4 2006.145.15:47:15.01#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.15:47:15.01#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.15:47:15.01#ibcon#ireg 11 cls_cnt 2 2006.145.15:47:15.01#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.15:47:15.07#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.15:47:15.07#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.15:47:15.09#ibcon#[27=AT03-04\r\n] 2006.145.15:47:15.12#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.15:47:15.12#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.15:47:15.12#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.15:47:15.12#ibcon#ireg 7 cls_cnt 0 2006.145.15:47:15.12#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.15:47:15.24#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.15:47:15.24#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.15:47:15.26#ibcon#[27=USB\r\n] 2006.145.15:47:15.29#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.15:47:15.29#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.15:47:15.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.15:47:15.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.15:47:15.29$vck44/vblo=4,679.99 2006.145.15:47:15.29#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.15:47:15.29#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.15:47:15.29#ibcon#ireg 17 cls_cnt 0 2006.145.15:47:15.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.15:47:15.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.15:47:15.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.15:47:15.31#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.15:47:15.35#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.15:47:15.35#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.15:47:15.35#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.15:47:15.35#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.15:47:15.35$vck44/vb=4,4 2006.145.15:47:15.35#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.15:47:15.35#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.15:47:15.35#ibcon#ireg 11 cls_cnt 2 2006.145.15:47:15.35#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.15:47:15.41#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.15:47:15.41#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.15:47:15.43#ibcon#[27=AT04-04\r\n] 2006.145.15:47:15.46#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.15:47:15.46#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.15:47:15.46#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.15:47:15.46#ibcon#ireg 7 cls_cnt 0 2006.145.15:47:15.46#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.15:47:15.58#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.15:47:15.58#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.15:47:15.60#ibcon#[27=USB\r\n] 2006.145.15:47:15.63#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.15:47:15.63#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.15:47:15.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.15:47:15.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.15:47:15.63$vck44/vblo=5,709.99 2006.145.15:47:15.63#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.15:47:15.63#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.15:47:15.63#ibcon#ireg 17 cls_cnt 0 2006.145.15:47:15.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.15:47:15.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.15:47:15.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.15:47:15.65#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.15:47:15.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.15:47:15.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.15:47:15.69#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.15:47:15.69#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.15:47:15.69$vck44/vb=5,4 2006.145.15:47:15.69#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.15:47:15.69#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.15:47:15.69#ibcon#ireg 11 cls_cnt 2 2006.145.15:47:15.69#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.15:47:15.75#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.15:47:15.75#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.15:47:15.77#ibcon#[27=AT05-04\r\n] 2006.145.15:47:15.80#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.15:47:15.80#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.15:47:15.80#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.15:47:15.80#ibcon#ireg 7 cls_cnt 0 2006.145.15:47:15.80#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.15:47:15.92#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.15:47:15.92#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.15:47:15.94#ibcon#[27=USB\r\n] 2006.145.15:47:15.97#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.15:47:15.97#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.15:47:15.97#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.15:47:15.97#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.15:47:15.97$vck44/vblo=6,719.99 2006.145.15:47:15.97#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.15:47:15.97#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.15:47:15.97#ibcon#ireg 17 cls_cnt 0 2006.145.15:47:15.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.15:47:15.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.15:47:15.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.15:47:15.99#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.15:47:16.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.15:47:16.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.15:47:16.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.15:47:16.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.15:47:16.03$vck44/vb=6,4 2006.145.15:47:16.03#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.15:47:16.03#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.15:47:16.03#ibcon#ireg 11 cls_cnt 2 2006.145.15:47:16.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.15:47:16.09#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.15:47:16.09#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.15:47:16.11#ibcon#[27=AT06-04\r\n] 2006.145.15:47:16.14#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.15:47:16.14#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.15:47:16.14#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.15:47:16.14#ibcon#ireg 7 cls_cnt 0 2006.145.15:47:16.14#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.15:47:16.26#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.15:47:16.26#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.15:47:16.28#ibcon#[27=USB\r\n] 2006.145.15:47:16.31#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.15:47:16.31#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.15:47:16.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.15:47:16.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.15:47:16.31$vck44/vblo=7,734.99 2006.145.15:47:16.31#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.15:47:16.31#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.15:47:16.31#ibcon#ireg 17 cls_cnt 0 2006.145.15:47:16.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.15:47:16.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.15:47:16.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.15:47:16.33#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.15:47:16.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.15:47:16.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.15:47:16.37#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.15:47:16.37#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.15:47:16.37$vck44/vb=7,4 2006.145.15:47:16.37#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.15:47:16.37#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.15:47:16.37#ibcon#ireg 11 cls_cnt 2 2006.145.15:47:16.37#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.15:47:16.43#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.15:47:16.43#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.15:47:16.45#ibcon#[27=AT07-04\r\n] 2006.145.15:47:16.48#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.15:47:16.48#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.15:47:16.48#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.15:47:16.48#ibcon#ireg 7 cls_cnt 0 2006.145.15:47:16.48#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.15:47:16.60#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.15:47:16.60#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.15:47:16.62#ibcon#[27=USB\r\n] 2006.145.15:47:16.65#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.15:47:16.65#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.15:47:16.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.15:47:16.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.15:47:16.65$vck44/vblo=8,744.99 2006.145.15:47:16.65#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.15:47:16.65#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.15:47:16.65#ibcon#ireg 17 cls_cnt 0 2006.145.15:47:16.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.15:47:16.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.15:47:16.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.15:47:16.67#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.15:47:16.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.15:47:16.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.15:47:16.71#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.15:47:16.71#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.15:47:16.71$vck44/vb=8,4 2006.145.15:47:16.71#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.15:47:16.71#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.15:47:16.71#ibcon#ireg 11 cls_cnt 2 2006.145.15:47:16.71#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.15:47:16.77#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.15:47:16.77#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.15:47:16.79#ibcon#[27=AT08-04\r\n] 2006.145.15:47:16.82#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.15:47:16.82#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.15:47:16.82#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.15:47:16.82#ibcon#ireg 7 cls_cnt 0 2006.145.15:47:16.82#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.15:47:16.94#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.15:47:16.94#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.15:47:16.96#ibcon#[27=USB\r\n] 2006.145.15:47:16.99#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.15:47:16.99#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.15:47:16.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.15:47:16.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.15:47:16.99$vck44/vabw=wide 2006.145.15:47:16.99#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.15:47:16.99#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.15:47:16.99#ibcon#ireg 8 cls_cnt 0 2006.145.15:47:16.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.15:47:16.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.15:47:16.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.15:47:17.01#ibcon#[25=BW32\r\n] 2006.145.15:47:17.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.15:47:17.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.15:47:17.04#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.15:47:17.04#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.15:47:17.04$vck44/vbbw=wide 2006.145.15:47:17.04#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.15:47:17.04#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.15:47:17.04#ibcon#ireg 8 cls_cnt 0 2006.145.15:47:17.04#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.15:47:17.11#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.15:47:17.11#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.15:47:17.13#ibcon#[27=BW32\r\n] 2006.145.15:47:17.16#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.15:47:17.16#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.15:47:17.16#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.15:47:17.16#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.15:47:17.16$setupk4/ifdk4 2006.145.15:47:17.16$ifdk4/lo= 2006.145.15:47:17.16$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.15:47:17.16$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.15:47:17.16$ifdk4/patch= 2006.145.15:47:17.17$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.15:47:17.17$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.15:47:17.17$setupk4/!*+20s 2006.145.15:47:18.47#abcon#<5=/08 0.7 1.8 15.77 861020.4\r\n> 2006.145.15:47:18.49#abcon#{5=INTERFACE CLEAR} 2006.145.15:47:18.55#abcon#[5=S1D000X0/0*\r\n] 2006.145.15:47:28.64#abcon#<5=/08 0.7 1.8 15.77 861020.4\r\n> 2006.145.15:47:28.66#abcon#{5=INTERFACE CLEAR} 2006.145.15:47:28.72#abcon#[5=S1D000X0/0*\r\n] 2006.145.15:47:29.13#trakl#Source acquired 2006.145.15:47:30.13#flagr#flagr/antenna,acquired 2006.145.15:47:31.67$setupk4/"tpicd 2006.145.15:47:31.67$setupk4/echo=off 2006.145.15:47:31.67$setupk4/xlog=off 2006.145.15:47:31.67:!2006.145.15:48:17 2006.145.15:48:17.00:preob 2006.145.15:48:17.13/onsource/TRACKING 2006.145.15:48:17.13:!2006.145.15:48:27 2006.145.15:48:27.00:"tape 2006.145.15:48:27.00:"st=record 2006.145.15:48:27.00:data_valid=on 2006.145.15:48:27.00:midob 2006.145.15:48:27.13/onsource/TRACKING 2006.145.15:48:27.14/wx/15.77,1020.4,86 2006.145.15:48:27.24/cable/+6.5507E-03 2006.145.15:48:28.33/va/01,08,usb,yes,28,30 2006.145.15:48:28.33/va/02,07,usb,yes,30,31 2006.145.15:48:28.33/va/03,08,usb,yes,28,29 2006.145.15:48:28.33/va/04,07,usb,yes,32,33 2006.145.15:48:28.33/va/05,04,usb,yes,27,28 2006.145.15:48:28.33/va/06,04,usb,yes,31,31 2006.145.15:48:28.33/va/07,04,usb,yes,31,32 2006.145.15:48:28.33/va/08,04,usb,yes,27,32 2006.145.15:48:28.56/valo/01,524.99,yes,locked 2006.145.15:48:28.56/valo/02,534.99,yes,locked 2006.145.15:48:28.56/valo/03,564.99,yes,locked 2006.145.15:48:28.56/valo/04,624.99,yes,locked 2006.145.15:48:28.56/valo/05,734.99,yes,locked 2006.145.15:48:28.56/valo/06,814.99,yes,locked 2006.145.15:48:28.56/valo/07,864.99,yes,locked 2006.145.15:48:28.56/valo/08,884.99,yes,locked 2006.145.15:48:29.65/vb/01,03,usb,yes,35,33 2006.145.15:48:29.65/vb/02,04,usb,yes,31,31 2006.145.15:48:29.65/vb/03,04,usb,yes,28,31 2006.145.15:48:29.65/vb/04,04,usb,yes,32,31 2006.145.15:48:29.65/vb/05,04,usb,yes,25,27 2006.145.15:48:29.65/vb/06,04,usb,yes,29,26 2006.145.15:48:29.65/vb/07,04,usb,yes,29,29 2006.145.15:48:29.65/vb/08,04,usb,yes,27,30 2006.145.15:48:29.88/vblo/01,629.99,yes,locked 2006.145.15:48:29.88/vblo/02,634.99,yes,locked 2006.145.15:48:29.88/vblo/03,649.99,yes,locked 2006.145.15:48:29.88/vblo/04,679.99,yes,locked 2006.145.15:48:29.88/vblo/05,709.99,yes,locked 2006.145.15:48:29.88/vblo/06,719.99,yes,locked 2006.145.15:48:29.88/vblo/07,734.99,yes,locked 2006.145.15:48:29.88/vblo/08,744.99,yes,locked 2006.145.15:48:30.03/vabw/8 2006.145.15:48:30.18/vbbw/8 2006.145.15:48:30.27/xfe/off,on,15.0 2006.145.15:48:30.66/ifatt/23,28,28,28 2006.145.15:48:31.07/fmout-gps/S +3.8E-08 2006.145.15:48:31.12:!2006.145.15:55:37 2006.145.15:55:37.00:data_valid=off 2006.145.15:55:37.01:"et 2006.145.15:55:37.01:!+3s 2006.145.15:55:40.02:"tape 2006.145.15:55:40.03:postob 2006.145.15:55:40.17/cable/+6.5496E-03 2006.145.15:55:40.21/wx/15.76,1020.3,87 2006.145.15:55:40.29/fmout-gps/S +4.4E-08 2006.145.15:55:40.29:scan_name=145-1601,jd0605,110 2006.145.15:55:40.30:source=3c274,123049.42,122328.0,2000.0,cw 2006.145.15:55:42.13#flagr#flagr/antenna,new-source 2006.145.15:55:42.14:checkk5 2006.145.15:55:42.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.15:55:43.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.15:55:43.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.15:55:43.91/chk_autoobs//k5ts4/ autoobs is running! 2006.145.15:55:44.34/chk_obsdata//k5ts1/T1451548??a.dat file size is correct (nominal:1720MB, actual:1716MB). 2006.145.15:55:44.79/chk_obsdata//k5ts2/T1451548??b.dat file size is correct (nominal:1720MB, actual:1716MB). 2006.145.15:55:45.22/chk_obsdata//k5ts3/T1451548??c.dat file size is correct (nominal:1720MB, actual:1716MB). 2006.145.15:55:45.66/chk_obsdata//k5ts4/T1451548??d.dat file size is correct (nominal:1720MB, actual:1716MB). 2006.145.15:55:46.42/k5log//k5ts1_log_newline 2006.145.15:55:47.16/k5log//k5ts2_log_newline 2006.145.15:55:47.91/k5log//k5ts3_log_newline 2006.145.15:55:48.66/k5log//k5ts4_log_newline 2006.145.15:55:48.68/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.15:55:48.68:setupk4=1 2006.145.15:55:48.68$setupk4/echo=on 2006.145.15:55:48.68$setupk4/pcalon 2006.145.15:55:48.69$pcalon/"no phase cal control is implemented here 2006.145.15:55:48.69$setupk4/"tpicd=stop 2006.145.15:55:48.69$setupk4/"rec=synch_on 2006.145.15:55:48.69$setupk4/"rec_mode=128 2006.145.15:55:48.69$setupk4/!* 2006.145.15:55:48.69$setupk4/recpk4 2006.145.15:55:48.69$recpk4/recpatch= 2006.145.15:55:48.69$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.15:55:48.69$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.15:55:48.69$setupk4/vck44 2006.145.15:55:48.69$vck44/valo=1,524.99 2006.145.15:55:48.69#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.15:55:48.69#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.15:55:48.69#ibcon#ireg 17 cls_cnt 0 2006.145.15:55:48.69#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.15:55:48.69#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.15:55:48.69#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.15:55:48.73#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.15:55:48.77#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.15:55:48.77#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.15:55:48.77#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.15:55:48.77#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.15:55:48.77$vck44/va=1,8 2006.145.15:55:48.77#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.15:55:48.77#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.15:55:48.77#ibcon#ireg 11 cls_cnt 2 2006.145.15:55:48.77#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.15:55:48.77#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.15:55:48.77#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.15:55:48.79#ibcon#[25=AT01-08\r\n] 2006.145.15:55:48.82#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.15:55:48.82#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.15:55:48.82#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.15:55:48.82#ibcon#ireg 7 cls_cnt 0 2006.145.15:55:48.82#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.15:55:48.94#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.15:55:48.94#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.15:55:48.96#ibcon#[25=USB\r\n] 2006.145.15:55:48.99#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.15:55:48.99#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.15:55:48.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.15:55:48.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.15:55:48.99$vck44/valo=2,534.99 2006.145.15:55:48.99#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.15:55:48.99#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.15:55:48.99#ibcon#ireg 17 cls_cnt 0 2006.145.15:55:48.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.15:55:48.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.15:55:48.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.15:55:49.02#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.15:55:49.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.15:55:49.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.15:55:49.06#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.15:55:49.06#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.15:55:49.06$vck44/va=2,7 2006.145.15:55:49.06#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.15:55:49.06#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.15:55:49.06#ibcon#ireg 11 cls_cnt 2 2006.145.15:55:49.06#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.15:55:49.11#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.15:55:49.11#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.15:55:49.13#ibcon#[25=AT02-07\r\n] 2006.145.15:55:49.16#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.15:55:49.16#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.15:55:49.16#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.15:55:49.16#ibcon#ireg 7 cls_cnt 0 2006.145.15:55:49.16#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.15:55:49.28#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.15:55:49.28#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.15:55:49.30#ibcon#[25=USB\r\n] 2006.145.15:55:49.33#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.15:55:49.33#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.15:55:49.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.15:55:49.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.15:55:49.33$vck44/valo=3,564.99 2006.145.15:55:49.33#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.15:55:49.33#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.15:55:49.33#ibcon#ireg 17 cls_cnt 0 2006.145.15:55:49.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.15:55:49.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.15:55:49.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.15:55:49.35#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.15:55:49.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.15:55:49.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.15:55:49.39#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.15:55:49.39#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.15:55:49.39$vck44/va=3,8 2006.145.15:55:49.39#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.15:55:49.39#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.15:55:49.39#ibcon#ireg 11 cls_cnt 2 2006.145.15:55:49.39#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.15:55:49.45#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.15:55:49.45#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.15:55:49.47#ibcon#[25=AT03-08\r\n] 2006.145.15:55:49.50#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.15:55:49.50#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.15:55:49.50#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.15:55:49.50#ibcon#ireg 7 cls_cnt 0 2006.145.15:55:49.50#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.15:55:49.62#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.15:55:49.62#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.15:55:49.64#ibcon#[25=USB\r\n] 2006.145.15:55:49.67#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.15:55:49.67#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.15:55:49.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.15:55:49.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.15:55:49.67$vck44/valo=4,624.99 2006.145.15:55:49.67#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.15:55:49.67#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.15:55:49.67#ibcon#ireg 17 cls_cnt 0 2006.145.15:55:49.67#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.15:55:49.67#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.15:55:49.67#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.15:55:49.69#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.15:55:49.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.15:55:49.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.15:55:49.73#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.15:55:49.73#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.15:55:49.73$vck44/va=4,7 2006.145.15:55:49.73#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.15:55:49.73#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.15:55:49.73#ibcon#ireg 11 cls_cnt 2 2006.145.15:55:49.73#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.15:55:49.79#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.15:55:49.79#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.15:55:49.81#ibcon#[25=AT04-07\r\n] 2006.145.15:55:49.84#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.15:55:49.84#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.15:55:49.84#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.15:55:49.84#ibcon#ireg 7 cls_cnt 0 2006.145.15:55:49.84#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.15:55:49.96#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.15:55:49.96#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.15:55:49.98#ibcon#[25=USB\r\n] 2006.145.15:55:50.01#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.15:55:50.01#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.15:55:50.01#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.15:55:50.01#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.15:55:50.01$vck44/valo=5,734.99 2006.145.15:55:50.01#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.15:55:50.01#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.15:55:50.01#ibcon#ireg 17 cls_cnt 0 2006.145.15:55:50.01#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.15:55:50.01#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.15:55:50.01#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.15:55:50.03#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.15:55:50.07#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.15:55:50.07#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.15:55:50.07#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.15:55:50.07#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.15:55:50.07$vck44/va=5,4 2006.145.15:55:50.07#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.15:55:50.07#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.15:55:50.07#ibcon#ireg 11 cls_cnt 2 2006.145.15:55:50.07#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.15:55:50.13#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.15:55:50.13#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.15:55:50.16#ibcon#[25=AT05-04\r\n] 2006.145.15:55:50.19#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.15:55:50.19#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.15:55:50.19#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.15:55:50.19#ibcon#ireg 7 cls_cnt 0 2006.145.15:55:50.19#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.15:55:50.31#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.15:55:50.31#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.15:55:50.33#ibcon#[25=USB\r\n] 2006.145.15:55:50.36#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.15:55:50.36#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.15:55:50.36#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.15:55:50.36#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.15:55:50.36$vck44/valo=6,814.99 2006.145.15:55:50.36#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.15:55:50.36#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.15:55:50.36#ibcon#ireg 17 cls_cnt 0 2006.145.15:55:50.36#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.15:55:50.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.15:55:50.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.15:55:50.38#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.15:55:50.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.15:55:50.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.15:55:50.42#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.15:55:50.42#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.15:55:50.42$vck44/va=6,4 2006.145.15:55:50.42#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.15:55:50.42#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.15:55:50.42#ibcon#ireg 11 cls_cnt 2 2006.145.15:55:50.42#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.15:55:50.48#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.15:55:50.48#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.15:55:50.50#ibcon#[25=AT06-04\r\n] 2006.145.15:55:50.53#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.15:55:50.53#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.15:55:50.53#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.15:55:50.53#ibcon#ireg 7 cls_cnt 0 2006.145.15:55:50.53#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.15:55:50.65#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.15:55:50.65#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.15:55:50.67#ibcon#[25=USB\r\n] 2006.145.15:55:50.70#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.15:55:50.70#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.15:55:50.70#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.15:55:50.70#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.15:55:50.70$vck44/valo=7,864.99 2006.145.15:55:50.70#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.15:55:50.70#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.15:55:50.70#ibcon#ireg 17 cls_cnt 0 2006.145.15:55:50.70#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.15:55:50.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.15:55:50.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.15:55:50.72#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.15:55:50.76#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.15:55:50.76#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.15:55:50.76#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.15:55:50.76#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.15:55:50.76$vck44/va=7,4 2006.145.15:55:50.76#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.15:55:50.76#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.15:55:50.76#ibcon#ireg 11 cls_cnt 2 2006.145.15:55:50.76#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.15:55:50.82#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.15:55:50.82#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.15:55:50.84#ibcon#[25=AT07-04\r\n] 2006.145.15:55:50.87#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.15:55:50.87#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.15:55:50.87#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.15:55:50.87#ibcon#ireg 7 cls_cnt 0 2006.145.15:55:50.87#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.15:55:50.99#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.15:55:50.99#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.15:55:51.01#ibcon#[25=USB\r\n] 2006.145.15:55:51.04#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.15:55:51.04#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.15:55:51.04#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.15:55:51.04#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.15:55:51.04$vck44/valo=8,884.99 2006.145.15:55:51.04#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.15:55:51.04#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.15:55:51.04#ibcon#ireg 17 cls_cnt 0 2006.145.15:55:51.04#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.15:55:51.04#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.15:55:51.04#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.15:55:51.06#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.15:55:51.10#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.15:55:51.10#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.15:55:51.10#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.15:55:51.10#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.15:55:51.10$vck44/va=8,4 2006.145.15:55:51.10#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.15:55:51.10#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.15:55:51.10#ibcon#ireg 11 cls_cnt 2 2006.145.15:55:51.10#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.15:55:51.16#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.15:55:51.16#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.15:55:51.18#ibcon#[25=AT08-04\r\n] 2006.145.15:55:51.23#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.15:55:51.24#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.15:55:51.24#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.15:55:51.24#ibcon#ireg 7 cls_cnt 0 2006.145.15:55:51.24#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.15:55:51.35#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.15:55:51.35#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.15:55:51.37#ibcon#[25=USB\r\n] 2006.145.15:55:51.40#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.15:55:51.40#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.15:55:51.40#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.15:55:51.40#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.15:55:51.40$vck44/vblo=1,629.99 2006.145.15:55:51.40#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.15:55:51.40#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.15:55:51.40#ibcon#ireg 17 cls_cnt 0 2006.145.15:55:51.40#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.15:55:51.40#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.15:55:51.40#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.15:55:51.43#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.15:55:51.47#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.15:55:51.47#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.15:55:51.47#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.15:55:51.47#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.15:55:51.47$vck44/vb=1,3 2006.145.15:55:51.47#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.15:55:51.47#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.15:55:51.47#ibcon#ireg 11 cls_cnt 2 2006.145.15:55:51.47#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.15:55:51.47#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.15:55:51.47#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.15:55:51.49#ibcon#[27=AT01-03\r\n] 2006.145.15:55:51.52#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.15:55:51.52#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.15:55:51.52#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.15:55:51.52#ibcon#ireg 7 cls_cnt 0 2006.145.15:55:51.52#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.15:55:51.64#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.15:55:51.64#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.15:55:51.66#ibcon#[27=USB\r\n] 2006.145.15:55:51.69#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.15:55:51.69#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.15:55:51.69#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.15:55:51.69#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.15:55:51.69$vck44/vblo=2,634.99 2006.145.15:55:51.69#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.15:55:51.69#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.15:55:51.69#ibcon#ireg 17 cls_cnt 0 2006.145.15:55:51.69#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.15:55:51.69#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.15:55:51.69#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.15:55:51.71#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.15:55:51.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.15:55:51.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.15:55:51.75#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.15:55:51.75#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.15:55:51.75$vck44/vb=2,4 2006.145.15:55:51.75#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.15:55:51.75#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.15:55:51.75#ibcon#ireg 11 cls_cnt 2 2006.145.15:55:51.75#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.15:55:51.81#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.15:55:51.81#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.15:55:51.83#ibcon#[27=AT02-04\r\n] 2006.145.15:55:51.86#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.15:55:51.86#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.15:55:51.86#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.15:55:51.86#ibcon#ireg 7 cls_cnt 0 2006.145.15:55:51.86#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.15:55:51.98#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.15:55:51.98#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.15:55:52.00#ibcon#[27=USB\r\n] 2006.145.15:55:52.03#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.15:55:52.03#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.15:55:52.03#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.15:55:52.03#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.15:55:52.03$vck44/vblo=3,649.99 2006.145.15:55:52.03#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.15:55:52.03#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.15:55:52.03#ibcon#ireg 17 cls_cnt 0 2006.145.15:55:52.03#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.15:55:52.03#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.15:55:52.03#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.15:55:52.05#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.15:55:52.09#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.15:55:52.09#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.15:55:52.09#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.15:55:52.09#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.15:55:52.09$vck44/vb=3,4 2006.145.15:55:52.09#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.15:55:52.09#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.15:55:52.09#ibcon#ireg 11 cls_cnt 2 2006.145.15:55:52.09#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.15:55:52.15#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.15:55:52.15#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.15:55:52.17#ibcon#[27=AT03-04\r\n] 2006.145.15:55:52.20#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.15:55:52.20#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.15:55:52.20#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.15:55:52.20#ibcon#ireg 7 cls_cnt 0 2006.145.15:55:52.20#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.15:55:52.32#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.15:55:52.32#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.15:55:52.34#ibcon#[27=USB\r\n] 2006.145.15:55:52.37#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.15:55:52.37#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.15:55:52.37#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.15:55:52.37#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.15:55:52.37$vck44/vblo=4,679.99 2006.145.15:55:52.37#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.15:55:52.37#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.15:55:52.37#ibcon#ireg 17 cls_cnt 0 2006.145.15:55:52.37#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.15:55:52.37#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.15:55:52.37#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.15:55:52.39#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.15:55:52.43#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.15:55:52.43#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.15:55:52.43#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.15:55:52.43#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.15:55:52.43$vck44/vb=4,4 2006.145.15:55:52.43#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.15:55:52.43#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.15:55:52.43#ibcon#ireg 11 cls_cnt 2 2006.145.15:55:52.43#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.15:55:52.49#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.15:55:52.49#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.15:55:52.51#ibcon#[27=AT04-04\r\n] 2006.145.15:55:52.54#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.15:55:52.54#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.15:55:52.54#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.15:55:52.54#ibcon#ireg 7 cls_cnt 0 2006.145.15:55:52.54#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.15:55:52.66#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.15:55:52.66#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.15:55:52.68#ibcon#[27=USB\r\n] 2006.145.15:55:52.71#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.15:55:52.71#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.15:55:52.71#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.15:55:52.71#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.15:55:52.71$vck44/vblo=5,709.99 2006.145.15:55:52.71#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.15:55:52.71#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.15:55:52.71#ibcon#ireg 17 cls_cnt 0 2006.145.15:55:52.71#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.15:55:52.71#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.15:55:52.71#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.15:55:52.73#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.15:55:52.77#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.15:55:52.77#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.15:55:52.77#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.15:55:52.77#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.15:55:52.77$vck44/vb=5,4 2006.145.15:55:52.77#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.15:55:52.77#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.15:55:52.77#ibcon#ireg 11 cls_cnt 2 2006.145.15:55:52.77#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.15:55:52.83#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.15:55:52.83#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.15:55:52.85#ibcon#[27=AT05-04\r\n] 2006.145.15:55:52.88#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.15:55:52.88#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.15:55:52.88#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.15:55:52.88#ibcon#ireg 7 cls_cnt 0 2006.145.15:55:52.88#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.15:55:53.00#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.15:55:53.00#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.15:55:53.02#ibcon#[27=USB\r\n] 2006.145.15:55:53.05#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.15:55:53.05#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.15:55:53.05#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.15:55:53.05#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.15:55:53.05$vck44/vblo=6,719.99 2006.145.15:55:53.05#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.15:55:53.05#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.15:55:53.05#ibcon#ireg 17 cls_cnt 0 2006.145.15:55:53.05#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.15:55:53.05#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.15:55:53.05#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.15:55:53.07#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.15:55:53.11#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.15:55:53.11#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.15:55:53.11#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.15:55:53.11#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.15:55:53.11$vck44/vb=6,4 2006.145.15:55:53.11#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.15:55:53.11#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.15:55:53.11#ibcon#ireg 11 cls_cnt 2 2006.145.15:55:53.11#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.15:55:53.17#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.15:55:53.17#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.15:55:53.19#ibcon#[27=AT06-04\r\n] 2006.145.15:55:53.22#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.15:55:53.22#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.15:55:53.22#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.15:55:53.22#ibcon#ireg 7 cls_cnt 0 2006.145.15:55:53.22#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.15:55:53.34#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.15:55:53.34#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.15:55:53.36#ibcon#[27=USB\r\n] 2006.145.15:55:53.39#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.15:55:53.39#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.15:55:53.39#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.15:55:53.39#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.15:55:53.39$vck44/vblo=7,734.99 2006.145.15:55:53.39#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.15:55:53.39#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.15:55:53.39#ibcon#ireg 17 cls_cnt 0 2006.145.15:55:53.39#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.15:55:53.39#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.15:55:53.39#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.15:55:53.41#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.15:55:53.45#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.15:55:53.45#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.15:55:53.45#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.15:55:53.45#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.15:55:53.45$vck44/vb=7,4 2006.145.15:55:53.45#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.15:55:53.45#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.15:55:53.45#ibcon#ireg 11 cls_cnt 2 2006.145.15:55:53.45#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.15:55:53.51#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.15:55:53.51#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.15:55:53.53#ibcon#[27=AT07-04\r\n] 2006.145.15:55:53.56#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.15:55:53.56#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.15:55:53.56#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.15:55:53.56#ibcon#ireg 7 cls_cnt 0 2006.145.15:55:53.56#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.15:55:53.68#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.15:55:53.68#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.15:55:53.70#ibcon#[27=USB\r\n] 2006.145.15:55:53.73#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.15:55:53.73#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.15:55:53.73#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.15:55:53.73#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.15:55:53.73$vck44/vblo=8,744.99 2006.145.15:55:53.73#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.15:55:53.73#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.15:55:53.73#ibcon#ireg 17 cls_cnt 0 2006.145.15:55:53.73#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.15:55:53.73#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.15:55:53.73#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.15:55:53.75#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.15:55:53.79#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.15:55:53.79#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.15:55:53.79#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.15:55:53.79#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.15:55:53.79$vck44/vb=8,4 2006.145.15:55:53.79#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.15:55:53.79#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.15:55:53.79#ibcon#ireg 11 cls_cnt 2 2006.145.15:55:53.79#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.15:55:53.85#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.15:55:53.85#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.15:55:53.87#ibcon#[27=AT08-04\r\n] 2006.145.15:55:53.90#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.15:55:53.90#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.15:55:53.90#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.15:55:53.90#ibcon#ireg 7 cls_cnt 0 2006.145.15:55:53.90#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.15:55:54.02#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.15:55:54.02#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.15:55:54.04#ibcon#[27=USB\r\n] 2006.145.15:55:54.07#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.15:55:54.07#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.15:55:54.07#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.15:55:54.07#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.15:55:54.07$vck44/vabw=wide 2006.145.15:55:54.07#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.15:55:54.07#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.15:55:54.07#ibcon#ireg 8 cls_cnt 0 2006.145.15:55:54.07#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.15:55:54.07#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.15:55:54.07#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.15:55:54.09#ibcon#[25=BW32\r\n] 2006.145.15:55:54.12#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.15:55:54.12#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.15:55:54.12#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.15:55:54.12#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.15:55:54.12$vck44/vbbw=wide 2006.145.15:55:54.12#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.15:55:54.12#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.15:55:54.12#ibcon#ireg 8 cls_cnt 0 2006.145.15:55:54.12#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:55:54.19#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:55:54.19#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:55:54.21#ibcon#[27=BW32\r\n] 2006.145.15:55:54.24#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:55:54.24#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.15:55:54.24#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.15:55:54.24#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.15:55:54.24$setupk4/ifdk4 2006.145.15:55:54.24$ifdk4/lo= 2006.145.15:55:54.24$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.15:55:54.24$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.15:55:54.24$ifdk4/patch= 2006.145.15:55:54.24$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.15:55:54.24$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.15:55:54.24$setupk4/!*+20s 2006.145.15:55:57.46#abcon#<5=/08 0.6 1.5 15.76 871020.3\r\n> 2006.145.15:55:57.48#abcon#{5=INTERFACE CLEAR} 2006.145.15:55:57.54#abcon#[5=S1D000X0/0*\r\n] 2006.145.15:56:00.13#trakl#Source acquired 2006.145.15:56:01.13#flagr#flagr/antenna,acquired 2006.145.15:56:07.63#abcon#<5=/08 0.6 1.5 15.76 871020.3\r\n> 2006.145.15:56:07.65#abcon#{5=INTERFACE CLEAR} 2006.145.15:56:07.71#abcon#[5=S1D000X0/0*\r\n] 2006.145.15:56:08.70$setupk4/"tpicd 2006.145.15:56:08.70$setupk4/echo=off 2006.145.15:56:08.70$setupk4/xlog=off 2006.145.15:56:08.70:!2006.145.16:01:13 2006.145.16:01:13.00:preob 2006.145.16:01:14.14/onsource/TRACKING 2006.145.16:01:14.14:!2006.145.16:01:23 2006.145.16:01:23.00:"tape 2006.145.16:01:23.00:"st=record 2006.145.16:01:23.00:data_valid=on 2006.145.16:01:23.00:midob 2006.145.16:01:23.14/onsource/TRACKING 2006.145.16:01:23.14/wx/15.72,1020.3,87 2006.145.16:01:23.21/cable/+6.5483E-03 2006.145.16:01:24.30/va/01,08,usb,yes,33,35 2006.145.16:01:24.30/va/02,07,usb,yes,35,36 2006.145.16:01:24.30/va/03,08,usb,yes,32,33 2006.145.16:01:24.30/va/04,07,usb,yes,36,38 2006.145.16:01:24.30/va/05,04,usb,yes,32,32 2006.145.16:01:24.30/va/06,04,usb,yes,35,35 2006.145.16:01:24.30/va/07,04,usb,yes,36,37 2006.145.16:01:24.30/va/08,04,usb,yes,31,36 2006.145.16:01:24.53/valo/01,524.99,yes,locked 2006.145.16:01:24.53/valo/02,534.99,yes,locked 2006.145.16:01:24.53/valo/03,564.99,yes,locked 2006.145.16:01:24.53/valo/04,624.99,yes,locked 2006.145.16:01:24.53/valo/05,734.99,yes,locked 2006.145.16:01:24.53/valo/06,814.99,yes,locked 2006.145.16:01:24.53/valo/07,864.99,yes,locked 2006.145.16:01:24.53/valo/08,884.99,yes,locked 2006.145.16:01:25.62/vb/01,03,usb,yes,45,42 2006.145.16:01:25.62/vb/02,04,usb,yes,40,39 2006.145.16:01:25.62/vb/03,04,usb,yes,36,40 2006.145.16:01:25.62/vb/04,04,usb,yes,41,40 2006.145.16:01:25.62/vb/05,04,usb,yes,32,35 2006.145.16:01:25.62/vb/06,04,usb,yes,37,33 2006.145.16:01:25.62/vb/07,04,usb,yes,37,37 2006.145.16:01:25.62/vb/08,04,usb,yes,34,38 2006.145.16:01:25.86/vblo/01,629.99,yes,locked 2006.145.16:01:25.86/vblo/02,634.99,yes,locked 2006.145.16:01:25.86/vblo/03,649.99,yes,locked 2006.145.16:01:25.86/vblo/04,679.99,yes,locked 2006.145.16:01:25.86/vblo/05,709.99,yes,locked 2006.145.16:01:25.86/vblo/06,719.99,yes,locked 2006.145.16:01:25.86/vblo/07,734.99,yes,locked 2006.145.16:01:25.86/vblo/08,744.99,yes,locked 2006.145.16:01:26.01/vabw/8 2006.145.16:01:26.16/vbbw/8 2006.145.16:01:26.25/xfe/off,on,15.2 2006.145.16:01:26.63/ifatt/23,28,28,28 2006.145.16:01:27.07/fmout-gps/S +4.6E-08 2006.145.16:01:27.11:!2006.145.16:03:13 2006.145.16:03:13.01:data_valid=off 2006.145.16:03:13.01:"et 2006.145.16:03:13.02:!+3s 2006.145.16:03:16.03:"tape 2006.145.16:03:16.03:postob 2006.145.16:03:16.16/cable/+6.5476E-03 2006.145.16:03:16.16/wx/15.70,1020.3,88 2006.145.16:03:16.22/fmout-gps/S +4.7E-08 2006.145.16:03:16.22:scan_name=145-1608,jd0605,270 2006.145.16:03:16.22:source=3c446,222547.26,-045701.4,2000.0,cw 2006.145.16:03:17.13#flagr#flagr/antenna,new-source 2006.145.16:03:17.13:checkk5 2006.145.16:03:17.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.16:03:18.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.16:03:18.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.16:03:18.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.16:03:19.31/chk_obsdata//k5ts1/T1451601??a.dat file size is correct (nominal:440MB, actual:436MB). 2006.145.16:03:19.75/chk_obsdata//k5ts2/T1451601??b.dat file size is correct (nominal:440MB, actual:436MB). 2006.145.16:03:20.20/chk_obsdata//k5ts3/T1451601??c.dat file size is correct (nominal:440MB, actual:436MB). 2006.145.16:03:20.63/chk_obsdata//k5ts4/T1451601??d.dat file size is correct (nominal:440MB, actual:436MB). 2006.145.16:03:21.41/k5log//k5ts1_log_newline 2006.145.16:03:22.15/k5log//k5ts2_log_newline 2006.145.16:03:22.88/k5log//k5ts3_log_newline 2006.145.16:03:23.62/k5log//k5ts4_log_newline 2006.145.16:03:23.65/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.16:03:23.65:setupk4=1 2006.145.16:03:23.65$setupk4/echo=on 2006.145.16:03:23.65$setupk4/pcalon 2006.145.16:03:23.65$pcalon/"no phase cal control is implemented here 2006.145.16:03:23.65$setupk4/"tpicd=stop 2006.145.16:03:23.65$setupk4/"rec=synch_on 2006.145.16:03:23.65$setupk4/"rec_mode=128 2006.145.16:03:23.65$setupk4/!* 2006.145.16:03:23.65$setupk4/recpk4 2006.145.16:03:23.65$recpk4/recpatch= 2006.145.16:03:23.65$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.16:03:23.65$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.16:03:23.65$setupk4/vck44 2006.145.16:03:23.65$vck44/valo=1,524.99 2006.145.16:03:23.65#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.16:03:23.65#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.16:03:23.65#ibcon#ireg 17 cls_cnt 0 2006.145.16:03:23.65#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.16:03:23.65#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.16:03:23.65#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.16:03:23.69#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.16:03:23.74#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.16:03:23.74#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.16:03:23.74#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.16:03:23.74#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.16:03:23.74$vck44/va=1,8 2006.145.16:03:23.74#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.16:03:23.74#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.16:03:23.74#ibcon#ireg 11 cls_cnt 2 2006.145.16:03:23.74#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.16:03:23.74#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.16:03:23.74#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.16:03:23.76#ibcon#[25=AT01-08\r\n] 2006.145.16:03:23.79#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.16:03:23.79#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.16:03:23.79#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.16:03:23.79#ibcon#ireg 7 cls_cnt 0 2006.145.16:03:23.79#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.16:03:23.92#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.16:03:23.92#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.16:03:23.93#ibcon#[25=USB\r\n] 2006.145.16:03:23.96#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.16:03:23.96#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.16:03:23.96#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.16:03:23.96#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.16:03:23.96$vck44/valo=2,534.99 2006.145.16:03:23.96#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.16:03:23.96#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.16:03:23.96#ibcon#ireg 17 cls_cnt 0 2006.145.16:03:23.96#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.16:03:23.96#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.16:03:23.96#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.16:03:23.99#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.16:03:24.03#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.16:03:24.03#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.16:03:24.03#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.16:03:24.03#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.16:03:24.03$vck44/va=2,7 2006.145.16:03:24.03#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.16:03:24.03#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.16:03:24.03#ibcon#ireg 11 cls_cnt 2 2006.145.16:03:24.03#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.16:03:24.08#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.16:03:24.08#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.16:03:24.10#ibcon#[25=AT02-07\r\n] 2006.145.16:03:24.13#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.16:03:24.13#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.16:03:24.13#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.16:03:24.13#ibcon#ireg 7 cls_cnt 0 2006.145.16:03:24.13#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.16:03:24.25#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.16:03:24.25#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.16:03:24.27#ibcon#[25=USB\r\n] 2006.145.16:03:24.30#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.16:03:24.30#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.16:03:24.30#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.16:03:24.30#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.16:03:24.30$vck44/valo=3,564.99 2006.145.16:03:24.30#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.16:03:24.30#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.16:03:24.30#ibcon#ireg 17 cls_cnt 0 2006.145.16:03:24.30#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.16:03:24.30#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.16:03:24.30#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.16:03:24.32#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.16:03:24.36#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.16:03:24.36#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.16:03:24.36#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.16:03:24.36#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.16:03:24.36$vck44/va=3,8 2006.145.16:03:24.36#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.16:03:24.36#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.16:03:24.36#ibcon#ireg 11 cls_cnt 2 2006.145.16:03:24.36#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.16:03:24.42#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.16:03:24.42#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.16:03:24.44#ibcon#[25=AT03-08\r\n] 2006.145.16:03:24.47#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.16:03:24.47#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.16:03:24.47#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.16:03:24.47#ibcon#ireg 7 cls_cnt 0 2006.145.16:03:24.47#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.16:03:24.59#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.16:03:24.59#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.16:03:24.61#ibcon#[25=USB\r\n] 2006.145.16:03:24.64#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.16:03:24.64#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.16:03:24.64#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.16:03:24.64#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.16:03:24.64$vck44/valo=4,624.99 2006.145.16:03:24.64#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.16:03:24.64#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.16:03:24.64#ibcon#ireg 17 cls_cnt 0 2006.145.16:03:24.64#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.16:03:24.64#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.16:03:24.64#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.16:03:24.66#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.16:03:24.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.16:03:24.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.16:03:24.70#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.16:03:24.70#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.16:03:24.70$vck44/va=4,7 2006.145.16:03:24.70#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.16:03:24.70#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.16:03:24.70#ibcon#ireg 11 cls_cnt 2 2006.145.16:03:24.70#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.16:03:24.76#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.16:03:24.76#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.16:03:24.78#ibcon#[25=AT04-07\r\n] 2006.145.16:03:24.81#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.16:03:24.81#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.16:03:24.81#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.16:03:24.81#ibcon#ireg 7 cls_cnt 0 2006.145.16:03:24.81#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.16:03:24.93#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.16:03:24.93#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.16:03:24.95#ibcon#[25=USB\r\n] 2006.145.16:03:24.98#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.16:03:24.98#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.16:03:24.98#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.16:03:24.98#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.16:03:24.98$vck44/valo=5,734.99 2006.145.16:03:24.98#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.16:03:24.98#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.16:03:24.98#ibcon#ireg 17 cls_cnt 0 2006.145.16:03:24.98#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.16:03:24.98#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.16:03:24.98#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.16:03:25.00#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.16:03:25.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.16:03:25.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.16:03:25.04#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.16:03:25.04#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.16:03:25.04$vck44/va=5,4 2006.145.16:03:25.04#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.16:03:25.04#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.16:03:25.04#ibcon#ireg 11 cls_cnt 2 2006.145.16:03:25.04#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.16:03:25.10#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.16:03:25.10#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.16:03:25.13#ibcon#[25=AT05-04\r\n] 2006.145.16:03:25.16#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.16:03:25.16#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.16:03:25.16#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.16:03:25.16#ibcon#ireg 7 cls_cnt 0 2006.145.16:03:25.16#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.16:03:25.28#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.16:03:25.28#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.16:03:25.30#ibcon#[25=USB\r\n] 2006.145.16:03:25.33#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.16:03:25.33#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.16:03:25.33#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.16:03:25.33#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.16:03:25.33$vck44/valo=6,814.99 2006.145.16:03:25.33#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.16:03:25.33#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.16:03:25.33#ibcon#ireg 17 cls_cnt 0 2006.145.16:03:25.33#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.16:03:25.33#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.16:03:25.33#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.16:03:25.35#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.16:03:25.39#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.16:03:25.39#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.16:03:25.39#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.16:03:25.39#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.16:03:25.39$vck44/va=6,4 2006.145.16:03:25.39#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.16:03:25.39#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.16:03:25.39#ibcon#ireg 11 cls_cnt 2 2006.145.16:03:25.39#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.16:03:25.45#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.16:03:25.45#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.16:03:25.47#ibcon#[25=AT06-04\r\n] 2006.145.16:03:25.50#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.16:03:25.50#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.16:03:25.50#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.16:03:25.50#ibcon#ireg 7 cls_cnt 0 2006.145.16:03:25.50#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.16:03:25.62#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.16:03:25.62#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.16:03:25.64#ibcon#[25=USB\r\n] 2006.145.16:03:25.67#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.16:03:25.67#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.16:03:25.67#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.16:03:25.67#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.16:03:25.67$vck44/valo=7,864.99 2006.145.16:03:25.67#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.16:03:25.67#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.16:03:25.67#ibcon#ireg 17 cls_cnt 0 2006.145.16:03:25.67#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.16:03:25.67#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.16:03:25.67#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.16:03:25.69#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.16:03:25.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.16:03:25.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.16:03:25.73#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.16:03:25.73#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.16:03:25.73$vck44/va=7,4 2006.145.16:03:25.73#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.16:03:25.73#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.16:03:25.73#ibcon#ireg 11 cls_cnt 2 2006.145.16:03:25.73#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.16:03:25.79#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.16:03:25.79#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.16:03:25.81#ibcon#[25=AT07-04\r\n] 2006.145.16:03:25.84#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.16:03:25.84#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.16:03:25.84#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.16:03:25.84#ibcon#ireg 7 cls_cnt 0 2006.145.16:03:25.84#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.16:03:25.96#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.16:03:25.96#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.16:03:25.98#ibcon#[25=USB\r\n] 2006.145.16:03:26.01#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.16:03:26.01#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.16:03:26.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.16:03:26.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.16:03:26.01$vck44/valo=8,884.99 2006.145.16:03:26.01#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.16:03:26.01#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.16:03:26.01#ibcon#ireg 17 cls_cnt 0 2006.145.16:03:26.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.16:03:26.01#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.16:03:26.01#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.16:03:26.03#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.16:03:26.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.16:03:26.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.16:03:26.07#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.16:03:26.07#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.16:03:26.07$vck44/va=8,4 2006.145.16:03:26.07#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.16:03:26.07#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.16:03:26.07#ibcon#ireg 11 cls_cnt 2 2006.145.16:03:26.07#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.16:03:26.13#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.16:03:26.13#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.16:03:26.15#ibcon#[25=AT08-04\r\n] 2006.145.16:03:26.18#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.16:03:26.18#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.16:03:26.18#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.16:03:26.18#ibcon#ireg 7 cls_cnt 0 2006.145.16:03:26.18#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.16:03:26.30#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.16:03:26.30#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.16:03:26.32#ibcon#[25=USB\r\n] 2006.145.16:03:26.35#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.16:03:26.35#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.16:03:26.35#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.16:03:26.35#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.16:03:26.35$vck44/vblo=1,629.99 2006.145.16:03:26.35#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.16:03:26.35#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.16:03:26.35#ibcon#ireg 17 cls_cnt 0 2006.145.16:03:26.35#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.16:03:26.35#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.16:03:26.35#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.16:03:26.38#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.16:03:26.42#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.16:03:26.42#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.16:03:26.42#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.16:03:26.42#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.16:03:26.42$vck44/vb=1,3 2006.145.16:03:26.42#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.16:03:26.42#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.16:03:26.42#ibcon#ireg 11 cls_cnt 2 2006.145.16:03:26.42#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.16:03:26.42#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.16:03:26.42#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.16:03:26.44#ibcon#[27=AT01-03\r\n] 2006.145.16:03:26.47#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.16:03:26.47#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.16:03:26.47#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.16:03:26.47#ibcon#ireg 7 cls_cnt 0 2006.145.16:03:26.47#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.16:03:26.59#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.16:03:26.59#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.16:03:26.61#ibcon#[27=USB\r\n] 2006.145.16:03:26.64#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.16:03:26.64#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.16:03:26.64#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.16:03:26.64#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.16:03:26.64$vck44/vblo=2,634.99 2006.145.16:03:26.64#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.16:03:26.64#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.16:03:26.64#ibcon#ireg 17 cls_cnt 0 2006.145.16:03:26.64#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.16:03:26.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.16:03:26.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.16:03:26.66#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.16:03:26.70#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.16:03:26.70#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.16:03:26.70#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.16:03:26.70#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.16:03:26.70$vck44/vb=2,4 2006.145.16:03:26.70#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.16:03:26.70#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.16:03:26.70#ibcon#ireg 11 cls_cnt 2 2006.145.16:03:26.70#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.16:03:26.76#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.16:03:26.76#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.16:03:26.78#ibcon#[27=AT02-04\r\n] 2006.145.16:03:26.81#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.16:03:26.81#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.16:03:26.81#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.16:03:26.81#ibcon#ireg 7 cls_cnt 0 2006.145.16:03:26.81#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.16:03:26.93#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.16:03:26.93#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.16:03:26.95#ibcon#[27=USB\r\n] 2006.145.16:03:26.98#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.16:03:26.98#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.16:03:26.98#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.16:03:26.98#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.16:03:26.98$vck44/vblo=3,649.99 2006.145.16:03:26.98#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.16:03:26.98#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.16:03:26.98#ibcon#ireg 17 cls_cnt 0 2006.145.16:03:26.98#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.16:03:26.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.16:03:26.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.16:03:27.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.16:03:27.04#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.16:03:27.04#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.16:03:27.04#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.16:03:27.04#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.16:03:27.04$vck44/vb=3,4 2006.145.16:03:27.04#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.16:03:27.04#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.16:03:27.04#ibcon#ireg 11 cls_cnt 2 2006.145.16:03:27.04#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.16:03:27.10#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.16:03:27.10#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.16:03:27.12#ibcon#[27=AT03-04\r\n] 2006.145.16:03:27.15#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.16:03:27.15#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.16:03:27.15#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.16:03:27.15#ibcon#ireg 7 cls_cnt 0 2006.145.16:03:27.15#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.16:03:27.27#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.16:03:27.27#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.16:03:27.29#ibcon#[27=USB\r\n] 2006.145.16:03:27.32#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.16:03:27.32#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.16:03:27.32#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.16:03:27.32#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.16:03:27.32$vck44/vblo=4,679.99 2006.145.16:03:27.32#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.16:03:27.32#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.16:03:27.32#ibcon#ireg 17 cls_cnt 0 2006.145.16:03:27.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.16:03:27.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.16:03:27.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.16:03:27.34#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.16:03:27.38#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.16:03:27.38#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.16:03:27.38#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.16:03:27.38#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.16:03:27.38$vck44/vb=4,4 2006.145.16:03:27.38#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.16:03:27.38#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.16:03:27.38#ibcon#ireg 11 cls_cnt 2 2006.145.16:03:27.38#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.16:03:27.44#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.16:03:27.44#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.16:03:27.46#ibcon#[27=AT04-04\r\n] 2006.145.16:03:27.49#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.16:03:27.49#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.16:03:27.49#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.16:03:27.49#ibcon#ireg 7 cls_cnt 0 2006.145.16:03:27.49#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.16:03:27.61#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.16:03:27.61#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.16:03:27.63#ibcon#[27=USB\r\n] 2006.145.16:03:27.66#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.16:03:27.66#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.16:03:27.66#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.16:03:27.66#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.16:03:27.66$vck44/vblo=5,709.99 2006.145.16:03:27.66#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.16:03:27.66#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.16:03:27.66#ibcon#ireg 17 cls_cnt 0 2006.145.16:03:27.66#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.16:03:27.66#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.16:03:27.66#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.16:03:27.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.16:03:27.72#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.16:03:27.72#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.16:03:27.72#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.16:03:27.72#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.16:03:27.72$vck44/vb=5,4 2006.145.16:03:27.72#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.16:03:27.72#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.16:03:27.72#ibcon#ireg 11 cls_cnt 2 2006.145.16:03:27.72#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.16:03:27.78#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.16:03:27.78#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.16:03:27.80#ibcon#[27=AT05-04\r\n] 2006.145.16:03:27.83#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.16:03:27.83#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.16:03:27.83#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.16:03:27.83#ibcon#ireg 7 cls_cnt 0 2006.145.16:03:27.83#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.16:03:27.88#abcon#<5=/07 0.9 1.5 15.70 871020.3\r\n> 2006.145.16:03:27.90#abcon#{5=INTERFACE CLEAR} 2006.145.16:03:27.95#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.16:03:27.95#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.16:03:27.96#abcon#[5=S1D000X0/0*\r\n] 2006.145.16:03:27.97#ibcon#[27=USB\r\n] 2006.145.16:03:28.00#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.16:03:28.00#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.16:03:28.00#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.16:03:28.00#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.16:03:28.00$vck44/vblo=6,719.99 2006.145.16:03:28.00#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.16:03:28.00#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.16:03:28.00#ibcon#ireg 17 cls_cnt 0 2006.145.16:03:28.00#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.16:03:28.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.16:03:28.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.16:03:28.02#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.16:03:28.06#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.16:03:28.06#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.16:03:28.06#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.16:03:28.06#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.16:03:28.06$vck44/vb=6,4 2006.145.16:03:28.06#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.16:03:28.06#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.16:03:28.06#ibcon#ireg 11 cls_cnt 2 2006.145.16:03:28.06#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.16:03:28.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.16:03:28.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.16:03:28.14#ibcon#[27=AT06-04\r\n] 2006.145.16:03:28.17#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.16:03:28.17#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.16:03:28.17#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.16:03:28.17#ibcon#ireg 7 cls_cnt 0 2006.145.16:03:28.17#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.16:03:28.29#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.16:03:28.29#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.16:03:28.31#ibcon#[27=USB\r\n] 2006.145.16:03:28.34#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.16:03:28.34#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.16:03:28.34#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.16:03:28.34#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.16:03:28.34$vck44/vblo=7,734.99 2006.145.16:03:28.34#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.16:03:28.34#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.16:03:28.34#ibcon#ireg 17 cls_cnt 0 2006.145.16:03:28.34#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.16:03:28.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.16:03:28.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.16:03:28.36#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.16:03:28.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.16:03:28.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.16:03:28.40#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.16:03:28.40#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.16:03:28.40$vck44/vb=7,4 2006.145.16:03:28.40#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.16:03:28.40#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.16:03:28.40#ibcon#ireg 11 cls_cnt 2 2006.145.16:03:28.40#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.16:03:28.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.16:03:28.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.16:03:28.48#ibcon#[27=AT07-04\r\n] 2006.145.16:03:28.51#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.16:03:28.51#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.16:03:28.51#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.16:03:28.51#ibcon#ireg 7 cls_cnt 0 2006.145.16:03:28.51#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.16:03:28.63#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.16:03:28.63#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.16:03:28.65#ibcon#[27=USB\r\n] 2006.145.16:03:28.68#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.16:03:28.68#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.16:03:28.68#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.16:03:28.68#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.16:03:28.68$vck44/vblo=8,744.99 2006.145.16:03:28.68#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.16:03:28.68#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.16:03:28.68#ibcon#ireg 17 cls_cnt 0 2006.145.16:03:28.68#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.16:03:28.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.16:03:28.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.16:03:28.70#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.16:03:28.74#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.16:03:28.74#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.16:03:28.74#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.16:03:28.74#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.16:03:28.74$vck44/vb=8,4 2006.145.16:03:28.74#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.16:03:28.74#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.16:03:28.74#ibcon#ireg 11 cls_cnt 2 2006.145.16:03:28.74#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.16:03:28.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.16:03:28.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.16:03:28.82#ibcon#[27=AT08-04\r\n] 2006.145.16:03:28.85#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.16:03:28.85#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.16:03:28.85#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.16:03:28.85#ibcon#ireg 7 cls_cnt 0 2006.145.16:03:28.85#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.16:03:28.97#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.16:03:28.97#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.16:03:28.99#ibcon#[27=USB\r\n] 2006.145.16:03:29.02#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.16:03:29.02#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.16:03:29.02#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.16:03:29.02#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.16:03:29.02$vck44/vabw=wide 2006.145.16:03:29.02#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.16:03:29.02#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.16:03:29.02#ibcon#ireg 8 cls_cnt 0 2006.145.16:03:29.02#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.16:03:29.02#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.16:03:29.02#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.16:03:29.04#ibcon#[25=BW32\r\n] 2006.145.16:03:29.07#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.16:03:29.07#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.16:03:29.07#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.16:03:29.07#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.16:03:29.07$vck44/vbbw=wide 2006.145.16:03:29.07#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.16:03:29.07#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.16:03:29.07#ibcon#ireg 8 cls_cnt 0 2006.145.16:03:29.07#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.16:03:29.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.16:03:29.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.16:03:29.16#ibcon#[27=BW32\r\n] 2006.145.16:03:29.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.16:03:29.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.16:03:29.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.16:03:29.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.16:03:29.19$setupk4/ifdk4 2006.145.16:03:29.19$ifdk4/lo= 2006.145.16:03:29.19$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.16:03:29.19$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.16:03:29.19$ifdk4/patch= 2006.145.16:03:29.19$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.16:03:29.19$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.16:03:29.19$setupk4/!*+20s 2006.145.16:03:38.05#abcon#<5=/07 0.9 1.5 15.70 871020.2\r\n> 2006.145.16:03:38.07#abcon#{5=INTERFACE CLEAR} 2006.145.16:03:38.13#abcon#[5=S1D000X0/0*\r\n] 2006.145.16:03:43.66$setupk4/"tpicd 2006.145.16:03:43.66$setupk4/echo=off 2006.145.16:03:43.66$setupk4/xlog=off 2006.145.16:03:43.66:!2006.145.16:08:41 2006.145.16:04:18.13#trakl#Source acquired 2006.145.16:04:18.13#flagr#flagr/antenna,acquired 2006.145.16:08:41.00:preob 2006.145.16:08:41.14/onsource/TRACKING 2006.145.16:08:41.14:!2006.145.16:08:51 2006.145.16:08:51.00:"tape 2006.145.16:08:51.00:"st=record 2006.145.16:08:51.00:data_valid=on 2006.145.16:08:51.00:midob 2006.145.16:08:51.14/onsource/TRACKING 2006.145.16:08:51.14/wx/15.71,1020.1,87 2006.145.16:08:51.25/cable/+6.5494E-03 2006.145.16:08:52.34/va/01,08,usb,yes,32,34 2006.145.16:08:52.34/va/02,07,usb,yes,34,35 2006.145.16:08:52.34/va/03,08,usb,yes,31,33 2006.145.16:08:52.34/va/04,07,usb,yes,36,37 2006.145.16:08:52.34/va/05,04,usb,yes,31,32 2006.145.16:08:52.34/va/06,04,usb,yes,35,35 2006.145.16:08:52.34/va/07,04,usb,yes,35,36 2006.145.16:08:52.34/va/08,04,usb,yes,30,36 2006.145.16:08:52.57/valo/01,524.99,yes,locked 2006.145.16:08:52.57/valo/02,534.99,yes,locked 2006.145.16:08:52.57/valo/03,564.99,yes,locked 2006.145.16:08:52.57/valo/04,624.99,yes,locked 2006.145.16:08:52.57/valo/05,734.99,yes,locked 2006.145.16:08:52.57/valo/06,814.99,yes,locked 2006.145.16:08:52.57/valo/07,864.99,yes,locked 2006.145.16:08:52.57/valo/08,884.99,yes,locked 2006.145.16:08:53.66/vb/01,03,usb,yes,39,36 2006.145.16:08:53.66/vb/02,04,usb,yes,34,34 2006.145.16:08:53.66/vb/03,04,usb,yes,31,34 2006.145.16:08:53.66/vb/04,04,usb,yes,35,34 2006.145.16:08:53.66/vb/05,04,usb,yes,28,30 2006.145.16:08:53.66/vb/06,04,usb,yes,32,28 2006.145.16:08:53.66/vb/07,04,usb,yes,32,32 2006.145.16:08:53.66/vb/08,04,usb,yes,29,33 2006.145.16:08:53.89/vblo/01,629.99,yes,locked 2006.145.16:08:53.89/vblo/02,634.99,yes,locked 2006.145.16:08:53.89/vblo/03,649.99,yes,locked 2006.145.16:08:53.89/vblo/04,679.99,yes,locked 2006.145.16:08:53.89/vblo/05,709.99,yes,locked 2006.145.16:08:53.89/vblo/06,719.99,yes,locked 2006.145.16:08:53.89/vblo/07,734.99,yes,locked 2006.145.16:08:53.89/vblo/08,744.99,yes,locked 2006.145.16:08:54.04/vabw/8 2006.145.16:08:54.19/vbbw/8 2006.145.16:08:54.28/xfe/off,on,15.2 2006.145.16:08:54.66/ifatt/23,28,28,28 2006.145.16:08:55.08/fmout-gps/S +4.7E-08 2006.145.16:08:55.12:!2006.145.16:13:21 2006.145.16:13:21.00:data_valid=off 2006.145.16:13:21.00:"et 2006.145.16:13:21.01:!+3s 2006.145.16:13:24.02:"tape 2006.145.16:13:24.02:postob 2006.145.16:13:24.13/cable/+6.5487E-03 2006.145.16:13:24.13/wx/15.78,1020.2,87 2006.145.16:13:25.08/fmout-gps/S +4.4E-08 2006.145.16:13:25.08:scan_name=145-1616,jd0605,40 2006.145.16:13:25.09:source=1954-388,195800.00,-384506.4,2000.0,cw 2006.145.16:13:25.13#flagr#flagr/antenna,new-source 2006.145.16:13:26.13:checkk5 2006.145.16:13:26.55/chk_autoobs//k5ts1/ autoobs is running! 2006.145.16:13:26.98/chk_autoobs//k5ts2/ autoobs is running! 2006.145.16:13:27.42/chk_autoobs//k5ts3/ autoobs is running! 2006.145.16:13:27.86/chk_autoobs//k5ts4/ autoobs is running! 2006.145.16:13:28.31/chk_obsdata//k5ts1/T1451608??a.dat file size is correct (nominal:1080MB, actual:1076MB). 2006.145.16:13:28.77/chk_obsdata//k5ts2/T1451608??b.dat file size is correct (nominal:1080MB, actual:1076MB). 2006.145.16:13:29.21/chk_obsdata//k5ts3/T1451608??c.dat file size is correct (nominal:1080MB, actual:1076MB). 2006.145.16:13:29.66/chk_obsdata//k5ts4/T1451608??d.dat file size is correct (nominal:1080MB, actual:1076MB). 2006.145.16:13:30.39/k5log//k5ts1_log_newline 2006.145.16:13:31.14/k5log//k5ts2_log_newline 2006.145.16:13:31.88/k5log//k5ts3_log_newline 2006.145.16:13:32.61/k5log//k5ts4_log_newline 2006.145.16:13:32.64/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.16:13:32.64:setupk4=1 2006.145.16:13:32.64$setupk4/echo=on 2006.145.16:13:32.64$setupk4/pcalon 2006.145.16:13:32.64$pcalon/"no phase cal control is implemented here 2006.145.16:13:32.64$setupk4/"tpicd=stop 2006.145.16:13:32.64$setupk4/"rec=synch_on 2006.145.16:13:32.64$setupk4/"rec_mode=128 2006.145.16:13:32.64$setupk4/!* 2006.145.16:13:32.64$setupk4/recpk4 2006.145.16:13:32.64$recpk4/recpatch= 2006.145.16:13:32.64$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.16:13:32.64$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.16:13:32.64$setupk4/vck44 2006.145.16:13:32.64$vck44/valo=1,524.99 2006.145.16:13:32.64#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.16:13:32.64#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.16:13:32.64#ibcon#ireg 17 cls_cnt 0 2006.145.16:13:32.64#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.16:13:32.64#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.16:13:32.64#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.16:13:32.68#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.16:13:32.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.16:13:32.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.16:13:32.73#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.16:13:32.73#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.16:13:32.73$vck44/va=1,8 2006.145.16:13:32.73#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.16:13:32.73#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.16:13:32.73#ibcon#ireg 11 cls_cnt 2 2006.145.16:13:32.73#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.16:13:32.73#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.16:13:32.73#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.16:13:32.75#ibcon#[25=AT01-08\r\n] 2006.145.16:13:32.78#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.16:13:32.78#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.16:13:32.78#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.16:13:32.78#ibcon#ireg 7 cls_cnt 0 2006.145.16:13:32.78#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.16:13:32.90#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.16:13:32.90#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.16:13:32.92#ibcon#[25=USB\r\n] 2006.145.16:13:32.95#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.16:13:32.95#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.16:13:32.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.16:13:32.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.16:13:32.95$vck44/valo=2,534.99 2006.145.16:13:32.95#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.16:13:32.95#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.16:13:32.95#ibcon#ireg 17 cls_cnt 0 2006.145.16:13:32.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.16:13:32.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.16:13:32.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.16:13:32.98#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.16:13:33.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.16:13:33.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.16:13:33.02#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.16:13:33.02#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.16:13:33.02$vck44/va=2,7 2006.145.16:13:33.02#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.16:13:33.02#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.16:13:33.02#ibcon#ireg 11 cls_cnt 2 2006.145.16:13:33.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.16:13:33.07#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.16:13:33.07#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.16:13:33.09#ibcon#[25=AT02-07\r\n] 2006.145.16:13:33.12#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.16:13:33.12#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.16:13:33.12#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.16:13:33.12#ibcon#ireg 7 cls_cnt 0 2006.145.16:13:33.12#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.16:13:33.24#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.16:13:33.24#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.16:13:33.26#ibcon#[25=USB\r\n] 2006.145.16:13:33.29#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.16:13:33.29#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.16:13:33.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.16:13:33.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.16:13:33.29$vck44/valo=3,564.99 2006.145.16:13:33.29#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.16:13:33.29#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.16:13:33.29#ibcon#ireg 17 cls_cnt 0 2006.145.16:13:33.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.16:13:33.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.16:13:33.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.16:13:33.31#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.16:13:33.35#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.16:13:33.35#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.16:13:33.35#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.16:13:33.35#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.16:13:33.35$vck44/va=3,8 2006.145.16:13:33.35#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.16:13:33.35#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.16:13:33.35#ibcon#ireg 11 cls_cnt 2 2006.145.16:13:33.35#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.16:13:33.41#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.16:13:33.41#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.16:13:33.43#ibcon#[25=AT03-08\r\n] 2006.145.16:13:33.46#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.16:13:33.46#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.16:13:33.46#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.16:13:33.46#ibcon#ireg 7 cls_cnt 0 2006.145.16:13:33.46#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.16:13:33.58#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.16:13:33.58#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.16:13:33.60#ibcon#[25=USB\r\n] 2006.145.16:13:33.63#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.16:13:33.63#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.16:13:33.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.16:13:33.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.16:13:33.63$vck44/valo=4,624.99 2006.145.16:13:33.63#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.16:13:33.63#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.16:13:33.63#ibcon#ireg 17 cls_cnt 0 2006.145.16:13:33.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.16:13:33.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.16:13:33.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.16:13:33.65#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.16:13:33.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.16:13:33.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.16:13:33.69#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.16:13:33.69#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.16:13:33.69$vck44/va=4,7 2006.145.16:13:33.69#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.16:13:33.69#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.16:13:33.69#ibcon#ireg 11 cls_cnt 2 2006.145.16:13:33.69#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.16:13:33.75#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.16:13:33.75#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.16:13:33.77#ibcon#[25=AT04-07\r\n] 2006.145.16:13:33.80#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.16:13:33.80#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.16:13:33.80#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.16:13:33.80#ibcon#ireg 7 cls_cnt 0 2006.145.16:13:33.80#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.16:13:33.92#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.16:13:33.92#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.16:13:33.94#ibcon#[25=USB\r\n] 2006.145.16:13:33.97#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.16:13:33.97#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.16:13:33.97#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.16:13:33.97#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.16:13:33.97$vck44/valo=5,734.99 2006.145.16:13:33.97#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.16:13:33.97#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.16:13:33.97#ibcon#ireg 17 cls_cnt 0 2006.145.16:13:33.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.16:13:33.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.16:13:33.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.16:13:33.99#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.16:13:34.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.16:13:34.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.16:13:34.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.16:13:34.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.16:13:34.03$vck44/va=5,4 2006.145.16:13:34.03#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.16:13:34.03#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.16:13:34.03#ibcon#ireg 11 cls_cnt 2 2006.145.16:13:34.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.16:13:34.09#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.16:13:34.09#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.16:13:34.11#ibcon#[25=AT05-04\r\n] 2006.145.16:13:34.14#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.16:13:34.14#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.16:13:34.14#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.16:13:34.14#ibcon#ireg 7 cls_cnt 0 2006.145.16:13:34.14#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.16:13:34.26#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.16:13:34.26#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.16:13:34.28#ibcon#[25=USB\r\n] 2006.145.16:13:34.31#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.16:13:34.31#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.16:13:34.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.16:13:34.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.16:13:34.31$vck44/valo=6,814.99 2006.145.16:13:34.31#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.16:13:34.31#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.16:13:34.31#ibcon#ireg 17 cls_cnt 0 2006.145.16:13:34.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.16:13:34.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.16:13:34.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.16:13:34.33#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.16:13:34.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.16:13:34.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.16:13:34.37#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.16:13:34.37#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.16:13:34.37$vck44/va=6,4 2006.145.16:13:34.37#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.16:13:34.37#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.16:13:34.37#ibcon#ireg 11 cls_cnt 2 2006.145.16:13:34.37#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.16:13:34.43#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.16:13:34.43#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.16:13:34.45#ibcon#[25=AT06-04\r\n] 2006.145.16:13:34.48#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.16:13:34.48#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.16:13:34.48#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.16:13:34.48#ibcon#ireg 7 cls_cnt 0 2006.145.16:13:34.48#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.16:13:34.60#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.16:13:34.60#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.16:13:34.62#ibcon#[25=USB\r\n] 2006.145.16:13:34.65#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.16:13:34.65#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.16:13:34.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.16:13:34.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.16:13:34.65$vck44/valo=7,864.99 2006.145.16:13:34.65#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.16:13:34.65#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.16:13:34.65#ibcon#ireg 17 cls_cnt 0 2006.145.16:13:34.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.16:13:34.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.16:13:34.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.16:13:34.67#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.16:13:34.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.16:13:34.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.16:13:34.71#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.16:13:34.71#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.16:13:34.71$vck44/va=7,4 2006.145.16:13:34.71#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.16:13:34.71#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.16:13:34.71#ibcon#ireg 11 cls_cnt 2 2006.145.16:13:34.71#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.16:13:34.77#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.16:13:34.77#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.16:13:34.79#ibcon#[25=AT07-04\r\n] 2006.145.16:13:34.82#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.16:13:34.82#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.16:13:34.82#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.16:13:34.82#ibcon#ireg 7 cls_cnt 0 2006.145.16:13:34.82#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.16:13:34.94#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.16:13:34.94#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.16:13:34.96#ibcon#[25=USB\r\n] 2006.145.16:13:34.99#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.16:13:34.99#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.16:13:34.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.16:13:34.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.16:13:34.99$vck44/valo=8,884.99 2006.145.16:13:34.99#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.16:13:34.99#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.16:13:34.99#ibcon#ireg 17 cls_cnt 0 2006.145.16:13:34.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.16:13:34.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.16:13:34.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.16:13:35.01#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.16:13:35.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.16:13:35.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.16:13:35.05#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.16:13:35.05#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.16:13:35.05$vck44/va=8,4 2006.145.16:13:35.05#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.16:13:35.05#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.16:13:35.05#ibcon#ireg 11 cls_cnt 2 2006.145.16:13:35.05#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.16:13:35.11#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.16:13:35.11#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.16:13:35.13#ibcon#[25=AT08-04\r\n] 2006.145.16:13:35.16#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.16:13:35.16#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.16:13:35.16#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.16:13:35.16#ibcon#ireg 7 cls_cnt 0 2006.145.16:13:35.16#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.16:13:35.28#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.16:13:35.28#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.16:13:35.30#ibcon#[25=USB\r\n] 2006.145.16:13:35.33#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.16:13:35.33#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.16:13:35.33#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.16:13:35.33#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.16:13:35.33$vck44/vblo=1,629.99 2006.145.16:13:35.33#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.16:13:35.33#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.16:13:35.33#ibcon#ireg 17 cls_cnt 0 2006.145.16:13:35.33#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.16:13:35.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.16:13:35.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.16:13:35.35#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.16:13:35.39#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.16:13:35.39#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.16:13:35.39#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.16:13:35.39#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.16:13:35.39$vck44/vb=1,3 2006.145.16:13:35.39#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.16:13:35.39#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.16:13:35.39#ibcon#ireg 11 cls_cnt 2 2006.145.16:13:35.39#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.16:13:35.39#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.16:13:35.39#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.16:13:35.41#ibcon#[27=AT01-03\r\n] 2006.145.16:13:35.44#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.16:13:35.44#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.16:13:35.44#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.16:13:35.44#ibcon#ireg 7 cls_cnt 0 2006.145.16:13:35.44#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.16:13:35.56#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.16:13:35.56#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.16:13:35.58#ibcon#[27=USB\r\n] 2006.145.16:13:35.61#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.16:13:35.61#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.16:13:35.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.16:13:35.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.16:13:35.61$vck44/vblo=2,634.99 2006.145.16:13:35.61#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.16:13:35.61#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.16:13:35.61#ibcon#ireg 17 cls_cnt 0 2006.145.16:13:35.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.16:13:35.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.16:13:35.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.16:13:35.63#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.16:13:35.67#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.16:13:35.67#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.16:13:35.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.16:13:35.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.16:13:35.67$vck44/vb=2,4 2006.145.16:13:35.67#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.16:13:35.67#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.16:13:35.67#ibcon#ireg 11 cls_cnt 2 2006.145.16:13:35.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.16:13:35.73#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.16:13:35.73#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.16:13:35.75#ibcon#[27=AT02-04\r\n] 2006.145.16:13:35.78#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.16:13:35.78#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.16:13:35.78#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.16:13:35.78#ibcon#ireg 7 cls_cnt 0 2006.145.16:13:35.78#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.16:13:35.90#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.16:13:35.90#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.16:13:35.92#ibcon#[27=USB\r\n] 2006.145.16:13:35.95#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.16:13:35.95#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.16:13:35.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.16:13:35.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.16:13:35.95$vck44/vblo=3,649.99 2006.145.16:13:35.95#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.16:13:35.95#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.16:13:35.95#ibcon#ireg 17 cls_cnt 0 2006.145.16:13:35.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.16:13:35.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.16:13:35.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.16:13:35.97#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.16:13:36.01#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.16:13:36.01#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.16:13:36.01#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.16:13:36.01#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.16:13:36.01$vck44/vb=3,4 2006.145.16:13:36.01#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.16:13:36.01#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.16:13:36.01#ibcon#ireg 11 cls_cnt 2 2006.145.16:13:36.01#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.16:13:36.07#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.16:13:36.07#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.16:13:36.09#ibcon#[27=AT03-04\r\n] 2006.145.16:13:36.12#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.16:13:36.12#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.16:13:36.12#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.16:13:36.12#ibcon#ireg 7 cls_cnt 0 2006.145.16:13:36.12#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.16:13:36.24#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.16:13:36.24#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.16:13:36.26#ibcon#[27=USB\r\n] 2006.145.16:13:36.29#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.16:13:36.29#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.16:13:36.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.16:13:36.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.16:13:36.29$vck44/vblo=4,679.99 2006.145.16:13:36.29#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.16:13:36.29#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.16:13:36.29#ibcon#ireg 17 cls_cnt 0 2006.145.16:13:36.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.16:13:36.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.16:13:36.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.16:13:36.31#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.16:13:36.35#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.16:13:36.35#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.16:13:36.35#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.16:13:36.35#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.16:13:36.35$vck44/vb=4,4 2006.145.16:13:36.35#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.16:13:36.35#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.16:13:36.35#ibcon#ireg 11 cls_cnt 2 2006.145.16:13:36.35#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.16:13:36.41#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.16:13:36.41#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.16:13:36.43#ibcon#[27=AT04-04\r\n] 2006.145.16:13:36.46#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.16:13:36.46#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.16:13:36.46#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.16:13:36.46#ibcon#ireg 7 cls_cnt 0 2006.145.16:13:36.46#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.16:13:36.58#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.16:13:36.58#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.16:13:36.60#ibcon#[27=USB\r\n] 2006.145.16:13:36.63#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.16:13:36.63#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.16:13:36.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.16:13:36.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.16:13:36.63$vck44/vblo=5,709.99 2006.145.16:13:36.63#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.16:13:36.63#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.16:13:36.63#ibcon#ireg 17 cls_cnt 0 2006.145.16:13:36.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.16:13:36.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.16:13:36.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.16:13:36.65#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.16:13:36.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.16:13:36.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.16:13:36.69#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.16:13:36.69#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.16:13:36.69$vck44/vb=5,4 2006.145.16:13:36.69#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.16:13:36.69#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.16:13:36.69#ibcon#ireg 11 cls_cnt 2 2006.145.16:13:36.69#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.16:13:36.75#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.16:13:36.75#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.16:13:36.77#ibcon#[27=AT05-04\r\n] 2006.145.16:13:36.80#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.16:13:36.80#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.16:13:36.80#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.16:13:36.80#ibcon#ireg 7 cls_cnt 0 2006.145.16:13:36.80#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.16:13:36.92#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.16:13:36.92#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.16:13:36.94#ibcon#[27=USB\r\n] 2006.145.16:13:36.97#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.16:13:36.97#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.16:13:36.97#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.16:13:36.97#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.16:13:36.97$vck44/vblo=6,719.99 2006.145.16:13:36.97#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.16:13:36.97#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.16:13:36.97#ibcon#ireg 17 cls_cnt 0 2006.145.16:13:36.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.16:13:36.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.16:13:36.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.16:13:36.99#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.16:13:37.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.16:13:37.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.16:13:37.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.16:13:37.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.16:13:37.03$vck44/vb=6,4 2006.145.16:13:37.03#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.16:13:37.03#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.16:13:37.03#ibcon#ireg 11 cls_cnt 2 2006.145.16:13:37.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.16:13:37.09#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.16:13:37.09#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.16:13:37.11#ibcon#[27=AT06-04\r\n] 2006.145.16:13:37.14#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.16:13:37.14#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.16:13:37.14#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.16:13:37.14#ibcon#ireg 7 cls_cnt 0 2006.145.16:13:37.14#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.16:13:37.26#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.16:13:37.26#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.16:13:37.28#ibcon#[27=USB\r\n] 2006.145.16:13:37.31#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.16:13:37.31#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.16:13:37.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.16:13:37.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.16:13:37.31$vck44/vblo=7,734.99 2006.145.16:13:37.31#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.16:13:37.31#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.16:13:37.31#ibcon#ireg 17 cls_cnt 0 2006.145.16:13:37.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.16:13:37.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.16:13:37.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.16:13:37.33#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.16:13:37.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.16:13:37.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.16:13:37.37#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.16:13:37.37#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.16:13:37.37$vck44/vb=7,4 2006.145.16:13:37.37#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.16:13:37.37#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.16:13:37.37#ibcon#ireg 11 cls_cnt 2 2006.145.16:13:37.37#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.16:13:37.43#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.16:13:37.43#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.16:13:37.45#ibcon#[27=AT07-04\r\n] 2006.145.16:13:37.48#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.16:13:37.48#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.16:13:37.48#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.16:13:37.48#ibcon#ireg 7 cls_cnt 0 2006.145.16:13:37.48#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.16:13:37.60#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.16:13:37.60#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.16:13:37.62#ibcon#[27=USB\r\n] 2006.145.16:13:37.65#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.16:13:37.65#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.16:13:37.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.16:13:37.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.16:13:37.65$vck44/vblo=8,744.99 2006.145.16:13:37.65#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.16:13:37.65#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.16:13:37.65#ibcon#ireg 17 cls_cnt 0 2006.145.16:13:37.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.16:13:37.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.16:13:37.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.16:13:37.67#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.16:13:37.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.16:13:37.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.16:13:37.71#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.16:13:37.71#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.16:13:37.71$vck44/vb=8,4 2006.145.16:13:37.71#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.16:13:37.71#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.16:13:37.71#ibcon#ireg 11 cls_cnt 2 2006.145.16:13:37.71#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.16:13:37.77#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.16:13:37.77#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.16:13:37.79#ibcon#[27=AT08-04\r\n] 2006.145.16:13:37.82#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.16:13:37.82#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.16:13:37.82#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.16:13:37.82#ibcon#ireg 7 cls_cnt 0 2006.145.16:13:37.82#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.16:13:37.94#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.16:13:37.94#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.16:13:37.96#ibcon#[27=USB\r\n] 2006.145.16:13:37.99#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.16:13:37.99#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.16:13:37.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.16:13:37.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.16:13:37.99$vck44/vabw=wide 2006.145.16:13:37.99#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.16:13:37.99#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.16:13:37.99#ibcon#ireg 8 cls_cnt 0 2006.145.16:13:37.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.16:13:37.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.16:13:37.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.16:13:38.01#ibcon#[25=BW32\r\n] 2006.145.16:13:38.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.16:13:38.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.16:13:38.04#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.16:13:38.04#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.16:13:38.04$vck44/vbbw=wide 2006.145.16:13:38.04#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.16:13:38.04#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.16:13:38.04#ibcon#ireg 8 cls_cnt 0 2006.145.16:13:38.04#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.16:13:38.11#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.16:13:38.11#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.16:13:38.13#ibcon#[27=BW32\r\n] 2006.145.16:13:38.16#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.16:13:38.16#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.16:13:38.16#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.16:13:38.16#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.16:13:38.16$setupk4/ifdk4 2006.145.16:13:38.16$ifdk4/lo= 2006.145.16:13:38.16$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.16:13:38.16$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.16:13:38.16$ifdk4/patch= 2006.145.16:13:38.16$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.16:13:38.16$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.16:13:38.16$setupk4/!*+20s 2006.145.16:13:38.29#abcon#<5=/07 1.0 1.9 15.78 871020.2\r\n> 2006.145.16:13:38.31#abcon#{5=INTERFACE CLEAR} 2006.145.16:13:38.37#abcon#[5=S1D000X0/0*\r\n] 2006.145.16:13:48.46#abcon#<5=/07 1.1 1.9 15.78 871020.2\r\n> 2006.145.16:13:48.48#abcon#{5=INTERFACE CLEAR} 2006.145.16:13:48.54#abcon#[5=S1D000X0/0*\r\n] 2006.145.16:13:51.14#trakl#Source acquired 2006.145.16:13:52.14#flagr#flagr/antenna,acquired 2006.145.16:13:52.65$setupk4/"tpicd 2006.145.16:13:52.65$setupk4/echo=off 2006.145.16:13:52.65$setupk4/xlog=off 2006.145.16:13:52.65:!2006.145.16:16:17 2006.145.16:16:17.00:preob 2006.145.16:16:17.14/onsource/TRACKING 2006.145.16:16:17.14:!2006.145.16:16:27 2006.145.16:16:27.00:"tape 2006.145.16:16:27.00:"st=record 2006.145.16:16:27.00:data_valid=on 2006.145.16:16:27.00:midob 2006.145.16:16:28.14/onsource/TRACKING 2006.145.16:16:28.14/wx/15.83,1020.2,86 2006.145.16:16:28.21/cable/+6.5497E-03 2006.145.16:16:29.30/va/01,08,usb,yes,34,36 2006.145.16:16:29.30/va/02,07,usb,yes,36,37 2006.145.16:16:29.30/va/03,08,usb,yes,33,34 2006.145.16:16:29.30/va/04,07,usb,yes,37,39 2006.145.16:16:29.30/va/05,04,usb,yes,32,33 2006.145.16:16:29.30/va/06,04,usb,yes,36,36 2006.145.16:16:29.30/va/07,04,usb,yes,37,38 2006.145.16:16:29.30/va/08,04,usb,yes,31,37 2006.145.16:16:29.53/valo/01,524.99,yes,locked 2006.145.16:16:29.53/valo/02,534.99,yes,locked 2006.145.16:16:29.53/valo/03,564.99,yes,locked 2006.145.16:16:29.53/valo/04,624.99,yes,locked 2006.145.16:16:29.53/valo/05,734.99,yes,locked 2006.145.16:16:29.53/valo/06,814.99,yes,locked 2006.145.16:16:29.53/valo/07,864.99,yes,locked 2006.145.16:16:29.53/valo/08,884.99,yes,locked 2006.145.16:16:30.62/vb/01,03,usb,yes,39,36 2006.145.16:16:30.62/vb/02,04,usb,yes,34,34 2006.145.16:16:30.62/vb/03,04,usb,yes,31,34 2006.145.16:16:30.62/vb/04,04,usb,yes,36,35 2006.145.16:16:30.62/vb/05,04,usb,yes,28,31 2006.145.16:16:30.62/vb/06,04,usb,yes,33,29 2006.145.16:16:30.62/vb/07,04,usb,yes,32,32 2006.145.16:16:30.62/vb/08,04,usb,yes,30,33 2006.145.16:16:30.86/vblo/01,629.99,yes,locked 2006.145.16:16:30.86/vblo/02,634.99,yes,locked 2006.145.16:16:30.86/vblo/03,649.99,yes,locked 2006.145.16:16:30.86/vblo/04,679.99,yes,locked 2006.145.16:16:30.86/vblo/05,709.99,yes,locked 2006.145.16:16:30.86/vblo/06,719.99,yes,locked 2006.145.16:16:30.86/vblo/07,734.99,yes,locked 2006.145.16:16:30.86/vblo/08,744.99,yes,locked 2006.145.16:16:31.01/vabw/8 2006.145.16:16:31.16/vbbw/8 2006.145.16:16:31.25/xfe/off,on,15.2 2006.145.16:16:31.63/ifatt/23,28,28,28 2006.145.16:16:32.08/fmout-gps/S +4.5E-08 2006.145.16:16:32.12:!2006.145.16:17:07 2006.145.16:17:07.00:data_valid=off 2006.145.16:17:07.00:"et 2006.145.16:17:07.00:!+3s 2006.145.16:17:10.02:"tape 2006.145.16:17:10.02:postob 2006.145.16:17:10.10/cable/+6.5506E-03 2006.145.16:17:10.10/wx/15.83,1020.2,86 2006.145.16:17:11.08/fmout-gps/S +4.4E-08 2006.145.16:17:11.08:scan_name=145-1622,jd0605,40 2006.145.16:17:11.08:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.145.16:17:12.14#flagr#flagr/antenna,new-source 2006.145.16:17:12.14:checkk5 2006.145.16:17:12.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.16:17:13.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.16:17:13.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.16:17:13.91/chk_autoobs//k5ts4/ autoobs is running! 2006.145.16:17:14.33/chk_obsdata//k5ts1/T1451616??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.16:17:14.77/chk_obsdata//k5ts2/T1451616??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.16:17:15.21/chk_obsdata//k5ts3/T1451616??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.16:17:15.63/chk_obsdata//k5ts4/T1451616??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.16:17:16.40/k5log//k5ts1_log_newline 2006.145.16:17:17.14/k5log//k5ts2_log_newline 2006.145.16:17:17.90/k5log//k5ts3_log_newline 2006.145.16:17:18.64/k5log//k5ts4_log_newline 2006.145.16:17:18.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.16:17:18.67:setupk4=1 2006.145.16:17:18.67$setupk4/echo=on 2006.145.16:17:18.67$setupk4/pcalon 2006.145.16:17:18.67$pcalon/"no phase cal control is implemented here 2006.145.16:17:18.67$setupk4/"tpicd=stop 2006.145.16:17:18.67$setupk4/"rec=synch_on 2006.145.16:17:18.67$setupk4/"rec_mode=128 2006.145.16:17:18.67$setupk4/!* 2006.145.16:17:18.67$setupk4/recpk4 2006.145.16:17:18.67$recpk4/recpatch= 2006.145.16:17:18.67$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.16:17:18.67$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.16:17:18.67$setupk4/vck44 2006.145.16:17:18.67$vck44/valo=1,524.99 2006.145.16:17:18.67#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.16:17:18.67#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.16:17:18.67#ibcon#ireg 17 cls_cnt 0 2006.145.16:17:18.67#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.16:17:18.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.16:17:18.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.16:17:18.69#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.16:17:18.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.16:17:18.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.16:17:18.74#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.16:17:18.74#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.16:17:18.74$vck44/va=1,8 2006.145.16:17:18.74#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.16:17:18.74#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.16:17:18.74#ibcon#ireg 11 cls_cnt 2 2006.145.16:17:18.74#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.16:17:18.74#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.16:17:18.74#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.16:17:18.76#ibcon#[25=AT01-08\r\n] 2006.145.16:17:18.79#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.16:17:18.79#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.16:17:18.79#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.16:17:18.79#ibcon#ireg 7 cls_cnt 0 2006.145.16:17:18.79#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.16:17:18.91#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.16:17:18.91#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.16:17:18.93#ibcon#[25=USB\r\n] 2006.145.16:17:18.96#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.16:17:18.96#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.16:17:18.96#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.16:17:18.96#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.16:17:18.96$vck44/valo=2,534.99 2006.145.16:17:18.96#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.16:17:18.96#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.16:17:18.96#ibcon#ireg 17 cls_cnt 0 2006.145.16:17:18.96#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.16:17:18.96#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.16:17:18.96#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.16:17:18.99#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.16:17:19.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.16:17:19.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.16:17:19.03#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.16:17:19.03#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.16:17:19.03$vck44/va=2,7 2006.145.16:17:19.03#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.16:17:19.03#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.16:17:19.03#ibcon#ireg 11 cls_cnt 2 2006.145.16:17:19.03#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.16:17:19.08#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.16:17:19.08#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.16:17:19.10#ibcon#[25=AT02-07\r\n] 2006.145.16:17:19.13#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.16:17:19.13#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.16:17:19.13#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.16:17:19.13#ibcon#ireg 7 cls_cnt 0 2006.145.16:17:19.13#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.16:17:19.25#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.16:17:19.25#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.16:17:19.27#ibcon#[25=USB\r\n] 2006.145.16:17:19.30#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.16:17:19.30#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.16:17:19.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.16:17:19.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.16:17:19.30$vck44/valo=3,564.99 2006.145.16:17:19.30#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.16:17:19.30#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.16:17:19.30#ibcon#ireg 17 cls_cnt 0 2006.145.16:17:19.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.16:17:19.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.16:17:19.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.16:17:19.32#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.16:17:19.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.16:17:19.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.16:17:19.36#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.16:17:19.36#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.16:17:19.36$vck44/va=3,8 2006.145.16:17:19.36#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.16:17:19.36#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.16:17:19.36#ibcon#ireg 11 cls_cnt 2 2006.145.16:17:19.36#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.16:17:19.42#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.16:17:19.42#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.16:17:19.44#ibcon#[25=AT03-08\r\n] 2006.145.16:17:19.47#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.16:17:19.47#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.16:17:19.47#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.16:17:19.47#ibcon#ireg 7 cls_cnt 0 2006.145.16:17:19.47#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.16:17:19.59#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.16:17:19.59#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.16:17:19.61#ibcon#[25=USB\r\n] 2006.145.16:17:19.64#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.16:17:19.64#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.16:17:19.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.16:17:19.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.16:17:19.64$vck44/valo=4,624.99 2006.145.16:17:19.64#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.16:17:19.64#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.16:17:19.64#ibcon#ireg 17 cls_cnt 0 2006.145.16:17:19.64#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.16:17:19.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.16:17:19.64#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.16:17:19.66#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.16:17:19.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.16:17:19.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.16:17:19.70#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.16:17:19.70#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.16:17:19.70$vck44/va=4,7 2006.145.16:17:19.70#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.16:17:19.70#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.16:17:19.70#ibcon#ireg 11 cls_cnt 2 2006.145.16:17:19.70#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.16:17:19.76#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.16:17:19.76#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.16:17:19.78#ibcon#[25=AT04-07\r\n] 2006.145.16:17:19.81#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.16:17:19.81#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.16:17:19.81#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.16:17:19.81#ibcon#ireg 7 cls_cnt 0 2006.145.16:17:19.81#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.16:17:19.93#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.16:17:19.93#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.16:17:19.95#ibcon#[25=USB\r\n] 2006.145.16:17:19.98#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.16:17:19.98#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.16:17:19.98#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.16:17:19.98#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.16:17:19.98$vck44/valo=5,734.99 2006.145.16:17:19.98#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.16:17:19.98#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.16:17:19.98#ibcon#ireg 17 cls_cnt 0 2006.145.16:17:19.98#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.16:17:19.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.16:17:19.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.16:17:20.00#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.16:17:20.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.16:17:20.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.16:17:20.04#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.16:17:20.04#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.16:17:20.04$vck44/va=5,4 2006.145.16:17:20.04#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.16:17:20.04#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.16:17:20.04#ibcon#ireg 11 cls_cnt 2 2006.145.16:17:20.04#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.16:17:20.10#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.16:17:20.10#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.16:17:20.12#ibcon#[25=AT05-04\r\n] 2006.145.16:17:20.15#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.16:17:20.15#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.16:17:20.15#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.16:17:20.15#ibcon#ireg 7 cls_cnt 0 2006.145.16:17:20.15#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.16:17:20.27#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.16:17:20.27#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.16:17:20.29#ibcon#[25=USB\r\n] 2006.145.16:17:20.32#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.16:17:20.32#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.16:17:20.32#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.16:17:20.32#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.16:17:20.32$vck44/valo=6,814.99 2006.145.16:17:20.32#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.16:17:20.32#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.16:17:20.32#ibcon#ireg 17 cls_cnt 0 2006.145.16:17:20.32#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:17:20.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:17:20.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:17:20.35#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.16:17:20.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:17:20.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:17:20.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.16:17:20.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.16:17:20.39$vck44/va=6,4 2006.145.16:17:20.39#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.16:17:20.39#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.16:17:20.39#ibcon#ireg 11 cls_cnt 2 2006.145.16:17:20.39#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.16:17:20.44#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.16:17:20.44#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.16:17:20.46#ibcon#[25=AT06-04\r\n] 2006.145.16:17:20.49#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.16:17:20.49#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.16:17:20.49#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.16:17:20.49#ibcon#ireg 7 cls_cnt 0 2006.145.16:17:20.49#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.16:17:20.61#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.16:17:20.61#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.16:17:20.63#ibcon#[25=USB\r\n] 2006.145.16:17:20.66#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.16:17:20.66#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.16:17:20.66#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.16:17:20.66#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.16:17:20.66$vck44/valo=7,864.99 2006.145.16:17:20.66#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.16:17:20.66#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.16:17:20.66#ibcon#ireg 17 cls_cnt 0 2006.145.16:17:20.66#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.16:17:20.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.16:17:20.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.16:17:20.68#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.16:17:20.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.16:17:20.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.16:17:20.72#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.16:17:20.72#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.16:17:20.72$vck44/va=7,4 2006.145.16:17:20.72#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.16:17:20.72#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.16:17:20.72#ibcon#ireg 11 cls_cnt 2 2006.145.16:17:20.72#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.16:17:20.78#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.16:17:20.78#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.16:17:20.80#ibcon#[25=AT07-04\r\n] 2006.145.16:17:20.83#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.16:17:20.83#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.16:17:20.83#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.16:17:20.83#ibcon#ireg 7 cls_cnt 0 2006.145.16:17:20.83#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.16:17:20.95#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.16:17:20.95#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.16:17:20.97#ibcon#[25=USB\r\n] 2006.145.16:17:21.00#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.16:17:21.00#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.16:17:21.00#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.16:17:21.00#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.16:17:21.00$vck44/valo=8,884.99 2006.145.16:17:21.00#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.16:17:21.00#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.16:17:21.00#ibcon#ireg 17 cls_cnt 0 2006.145.16:17:21.00#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.16:17:21.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.16:17:21.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.16:17:21.02#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.16:17:21.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.16:17:21.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.16:17:21.06#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.16:17:21.06#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.16:17:21.06$vck44/va=8,4 2006.145.16:17:21.06#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.16:17:21.06#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.16:17:21.06#ibcon#ireg 11 cls_cnt 2 2006.145.16:17:21.06#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.16:17:21.12#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.16:17:21.12#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.16:17:21.14#ibcon#[25=AT08-04\r\n] 2006.145.16:17:21.17#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.16:17:21.17#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.16:17:21.17#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.16:17:21.17#ibcon#ireg 7 cls_cnt 0 2006.145.16:17:21.17#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.16:17:21.29#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.16:17:21.29#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.16:17:21.31#ibcon#[25=USB\r\n] 2006.145.16:17:21.34#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.16:17:21.34#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.16:17:21.34#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.16:17:21.34#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.16:17:21.34$vck44/vblo=1,629.99 2006.145.16:17:21.34#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.16:17:21.34#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.16:17:21.34#ibcon#ireg 17 cls_cnt 0 2006.145.16:17:21.34#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.16:17:21.34#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.16:17:21.34#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.16:17:21.36#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.16:17:21.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.16:17:21.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.16:17:21.40#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.16:17:21.40#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.16:17:21.40$vck44/vb=1,3 2006.145.16:17:21.40#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.16:17:21.40#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.16:17:21.40#ibcon#ireg 11 cls_cnt 2 2006.145.16:17:21.40#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.16:17:21.40#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.16:17:21.40#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.16:17:21.42#ibcon#[27=AT01-03\r\n] 2006.145.16:17:21.45#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.16:17:21.45#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.16:17:21.45#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.16:17:21.45#ibcon#ireg 7 cls_cnt 0 2006.145.16:17:21.45#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.16:17:21.57#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.16:17:21.57#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.16:17:21.59#ibcon#[27=USB\r\n] 2006.145.16:17:21.62#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.16:17:21.62#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.16:17:21.62#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.16:17:21.62#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.16:17:21.62$vck44/vblo=2,634.99 2006.145.16:17:21.62#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.16:17:21.62#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.16:17:21.62#ibcon#ireg 17 cls_cnt 0 2006.145.16:17:21.62#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.16:17:21.62#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.16:17:21.62#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.16:17:21.64#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.16:17:21.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.16:17:21.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.16:17:21.68#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.16:17:21.68#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.16:17:21.68$vck44/vb=2,4 2006.145.16:17:21.68#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.16:17:21.68#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.16:17:21.68#ibcon#ireg 11 cls_cnt 2 2006.145.16:17:21.68#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.16:17:21.74#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.16:17:21.74#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.16:17:21.76#ibcon#[27=AT02-04\r\n] 2006.145.16:17:21.79#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.16:17:21.79#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.16:17:21.79#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.16:17:21.79#ibcon#ireg 7 cls_cnt 0 2006.145.16:17:21.79#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.16:17:21.91#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.16:17:21.91#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.16:17:21.93#ibcon#[27=USB\r\n] 2006.145.16:17:21.96#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.16:17:21.96#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.16:17:21.96#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.16:17:21.96#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.16:17:21.96$vck44/vblo=3,649.99 2006.145.16:17:21.96#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.16:17:21.96#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.16:17:21.96#ibcon#ireg 17 cls_cnt 0 2006.145.16:17:21.96#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.16:17:21.96#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.16:17:21.96#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.16:17:21.98#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.16:17:22.02#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.16:17:22.02#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.16:17:22.02#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.16:17:22.02#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.16:17:22.02$vck44/vb=3,4 2006.145.16:17:22.02#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.16:17:22.02#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.16:17:22.02#ibcon#ireg 11 cls_cnt 2 2006.145.16:17:22.02#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.16:17:22.08#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.16:17:22.08#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.16:17:22.10#ibcon#[27=AT03-04\r\n] 2006.145.16:17:22.13#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.16:17:22.13#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.16:17:22.13#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.16:17:22.13#ibcon#ireg 7 cls_cnt 0 2006.145.16:17:22.13#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.16:17:22.25#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.16:17:22.25#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.16:17:22.27#ibcon#[27=USB\r\n] 2006.145.16:17:22.30#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.16:17:22.30#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.16:17:22.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.16:17:22.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.16:17:22.30$vck44/vblo=4,679.99 2006.145.16:17:22.30#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.16:17:22.30#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.16:17:22.30#ibcon#ireg 17 cls_cnt 0 2006.145.16:17:22.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.16:17:22.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.16:17:22.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.16:17:22.32#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.16:17:22.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.16:17:22.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.16:17:22.36#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.16:17:22.36#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.16:17:22.36$vck44/vb=4,4 2006.145.16:17:22.36#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.16:17:22.36#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.16:17:22.36#ibcon#ireg 11 cls_cnt 2 2006.145.16:17:22.36#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.16:17:22.42#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.16:17:22.42#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.16:17:22.44#ibcon#[27=AT04-04\r\n] 2006.145.16:17:22.47#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.16:17:22.47#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.16:17:22.47#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.16:17:22.47#ibcon#ireg 7 cls_cnt 0 2006.145.16:17:22.47#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.16:17:22.53#abcon#<5=/06 1.4 2.7 15.84 861020.2\r\n> 2006.145.16:17:22.55#abcon#{5=INTERFACE CLEAR} 2006.145.16:17:22.59#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.16:17:22.59#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.16:17:22.61#ibcon#[27=USB\r\n] 2006.145.16:17:22.61#abcon#[5=S1D000X0/0*\r\n] 2006.145.16:17:22.64#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.16:17:22.64#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.16:17:22.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.16:17:22.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.16:17:22.64$vck44/vblo=5,709.99 2006.145.16:17:22.64#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.16:17:22.64#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.16:17:22.64#ibcon#ireg 17 cls_cnt 0 2006.145.16:17:22.64#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.16:17:22.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.16:17:22.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.16:17:22.66#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.16:17:22.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.16:17:22.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.16:17:22.70#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.16:17:22.70#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.16:17:22.70$vck44/vb=5,4 2006.145.16:17:22.70#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.16:17:22.70#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.16:17:22.70#ibcon#ireg 11 cls_cnt 2 2006.145.16:17:22.70#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.16:17:22.76#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.16:17:22.76#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.16:17:22.78#ibcon#[27=AT05-04\r\n] 2006.145.16:17:22.81#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.16:17:22.81#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.16:17:22.81#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.16:17:22.81#ibcon#ireg 7 cls_cnt 0 2006.145.16:17:22.81#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.16:17:22.93#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.16:17:22.93#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.16:17:22.95#ibcon#[27=USB\r\n] 2006.145.16:17:22.98#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.16:17:22.98#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.16:17:22.98#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.16:17:22.98#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.16:17:22.98$vck44/vblo=6,719.99 2006.145.16:17:22.98#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.16:17:22.98#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.16:17:22.98#ibcon#ireg 17 cls_cnt 0 2006.145.16:17:22.98#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:17:22.98#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:17:22.98#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:17:23.00#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.16:17:23.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:17:23.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:17:23.04#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.16:17:23.04#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.16:17:23.04$vck44/vb=6,4 2006.145.16:17:23.04#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.16:17:23.04#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.16:17:23.04#ibcon#ireg 11 cls_cnt 2 2006.145.16:17:23.04#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.16:17:23.10#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.16:17:23.10#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.16:17:23.12#ibcon#[27=AT06-04\r\n] 2006.145.16:17:23.15#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.16:17:23.15#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.16:17:23.15#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.16:17:23.15#ibcon#ireg 7 cls_cnt 0 2006.145.16:17:23.15#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.16:17:23.27#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.16:17:23.27#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.16:17:23.29#ibcon#[27=USB\r\n] 2006.145.16:17:23.32#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.16:17:23.32#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.16:17:23.32#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.16:17:23.32#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.16:17:23.32$vck44/vblo=7,734.99 2006.145.16:17:23.32#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.16:17:23.32#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.16:17:23.32#ibcon#ireg 17 cls_cnt 0 2006.145.16:17:23.32#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.16:17:23.32#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.16:17:23.32#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.16:17:23.34#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.16:17:23.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.16:17:23.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.16:17:23.38#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.16:17:23.38#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.16:17:23.38$vck44/vb=7,4 2006.145.16:17:23.38#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.16:17:23.38#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.16:17:23.38#ibcon#ireg 11 cls_cnt 2 2006.145.16:17:23.38#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.16:17:23.44#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.16:17:23.44#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.16:17:23.46#ibcon#[27=AT07-04\r\n] 2006.145.16:17:23.49#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.16:17:23.49#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.16:17:23.49#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.16:17:23.49#ibcon#ireg 7 cls_cnt 0 2006.145.16:17:23.49#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.16:17:23.61#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.16:17:23.61#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.16:17:23.63#ibcon#[27=USB\r\n] 2006.145.16:17:23.66#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.16:17:23.66#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.16:17:23.66#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.16:17:23.66#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.16:17:23.66$vck44/vblo=8,744.99 2006.145.16:17:23.66#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.16:17:23.66#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.16:17:23.66#ibcon#ireg 17 cls_cnt 0 2006.145.16:17:23.66#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.16:17:23.66#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.16:17:23.66#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.16:17:23.68#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.16:17:23.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.16:17:23.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.16:17:23.72#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.16:17:23.72#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.16:17:23.72$vck44/vb=8,4 2006.145.16:17:23.72#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.16:17:23.72#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.16:17:23.72#ibcon#ireg 11 cls_cnt 2 2006.145.16:17:23.72#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.16:17:23.78#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.16:17:23.78#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.16:17:23.80#ibcon#[27=AT08-04\r\n] 2006.145.16:17:23.83#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.16:17:23.83#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.16:17:23.83#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.16:17:23.83#ibcon#ireg 7 cls_cnt 0 2006.145.16:17:23.83#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.16:17:23.95#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.16:17:23.95#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.16:17:23.97#ibcon#[27=USB\r\n] 2006.145.16:17:24.00#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.16:17:24.00#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.16:17:24.00#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.16:17:24.00#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.16:17:24.00$vck44/vabw=wide 2006.145.16:17:24.00#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.16:17:24.00#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.16:17:24.00#ibcon#ireg 8 cls_cnt 0 2006.145.16:17:24.00#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.16:17:24.00#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.16:17:24.00#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.16:17:24.02#ibcon#[25=BW32\r\n] 2006.145.16:17:24.05#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.16:17:24.05#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.16:17:24.05#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.16:17:24.05#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.16:17:24.05$vck44/vbbw=wide 2006.145.16:17:24.05#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.16:17:24.05#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.16:17:24.05#ibcon#ireg 8 cls_cnt 0 2006.145.16:17:24.05#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.16:17:24.12#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.16:17:24.12#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.16:17:24.14#ibcon#[27=BW32\r\n] 2006.145.16:17:24.17#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.16:17:24.17#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.16:17:24.17#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.16:17:24.17#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.16:17:24.17$setupk4/ifdk4 2006.145.16:17:24.17$ifdk4/lo= 2006.145.16:17:24.17$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.16:17:24.17$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.16:17:24.17$ifdk4/patch= 2006.145.16:17:24.17$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.16:17:24.17$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.16:17:24.17$setupk4/!*+20s 2006.145.16:17:32.70#abcon#<5=/06 1.4 2.7 15.84 861020.2\r\n> 2006.145.16:17:32.72#abcon#{5=INTERFACE CLEAR} 2006.145.16:17:32.80#abcon#[5=S1D000X0/0*\r\n] 2006.145.16:17:36.14#trakl#Source acquired 2006.145.16:17:37.14#flagr#flagr/antenna,acquired 2006.145.16:17:38.68$setupk4/"tpicd 2006.145.16:17:38.68$setupk4/echo=off 2006.145.16:17:38.68$setupk4/xlog=off 2006.145.16:17:38.68:!2006.145.16:22:43 2006.145.16:22:43.00:preob 2006.145.16:22:44.15/onsource/TRACKING 2006.145.16:22:44.15:!2006.145.16:22:53 2006.145.16:22:53.02:"tape 2006.145.16:22:53.02:"st=record 2006.145.16:22:53.02:data_valid=on 2006.145.16:22:53.02:midob 2006.145.16:22:54.15/onsource/TRACKING 2006.145.16:22:54.15/wx/15.87,1020.1,87 2006.145.16:22:54.21/cable/+6.5495E-03 2006.145.16:22:55.30/va/01,08,usb,yes,28,30 2006.145.16:22:55.30/va/02,07,usb,yes,30,31 2006.145.16:22:55.30/va/03,08,usb,yes,28,29 2006.145.16:22:55.30/va/04,07,usb,yes,31,33 2006.145.16:22:55.30/va/05,04,usb,yes,27,28 2006.145.16:22:55.30/va/06,04,usb,yes,31,30 2006.145.16:22:55.30/va/07,04,usb,yes,31,32 2006.145.16:22:55.30/va/08,04,usb,yes,26,32 2006.145.16:22:55.53/valo/01,524.99,yes,locked 2006.145.16:22:55.53/valo/02,534.99,yes,locked 2006.145.16:22:55.53/valo/03,564.99,yes,locked 2006.145.16:22:55.53/valo/04,624.99,yes,locked 2006.145.16:22:55.53/valo/05,734.99,yes,locked 2006.145.16:22:55.53/valo/06,814.99,yes,locked 2006.145.16:22:55.53/valo/07,864.99,yes,locked 2006.145.16:22:55.53/valo/08,884.99,yes,locked 2006.145.16:22:56.62/vb/01,03,usb,yes,37,33 2006.145.16:22:56.62/vb/02,04,usb,yes,31,32 2006.145.16:22:56.62/vb/03,04,usb,yes,28,31 2006.145.16:22:56.62/vb/04,04,usb,yes,33,31 2006.145.16:22:56.62/vb/05,04,usb,yes,25,28 2006.145.16:22:56.62/vb/06,04,usb,yes,29,26 2006.145.16:22:56.62/vb/07,04,usb,yes,29,29 2006.145.16:22:56.62/vb/08,04,usb,yes,27,30 2006.145.16:22:56.85/vblo/01,629.99,yes,locked 2006.145.16:22:56.85/vblo/02,634.99,yes,locked 2006.145.16:22:56.85/vblo/03,649.99,yes,locked 2006.145.16:22:56.85/vblo/04,679.99,yes,locked 2006.145.16:22:56.85/vblo/05,709.99,yes,locked 2006.145.16:22:56.85/vblo/06,719.99,yes,locked 2006.145.16:22:56.85/vblo/07,734.99,yes,locked 2006.145.16:22:56.85/vblo/08,744.99,yes,locked 2006.145.16:22:57.00/vabw/8 2006.145.16:22:57.15/vbbw/8 2006.145.16:22:57.35/xfe/off,on,14.7 2006.145.16:22:57.74/ifatt/23,28,28,28 2006.145.16:22:58.07/fmout-gps/S +4.3E-08 2006.145.16:22:58.12:!2006.145.16:23:33 2006.145.16:23:33.02:data_valid=off 2006.145.16:23:33.02:"et 2006.145.16:23:33.02:!+3s 2006.145.16:23:36.05:"tape 2006.145.16:23:36.06:postob 2006.145.16:23:36.28/cable/+6.5484E-03 2006.145.16:23:36.29/wx/15.87,1020.1,87 2006.145.16:23:36.36/fmout-gps/S +4.3E-08 2006.145.16:23:36.36:scan_name=145-1625,jd0605,140 2006.145.16:23:36.36:source=2201+315,220314.98,314538.3,2000.0,cw 2006.145.16:23:37.15#flagr#flagr/antenna,new-source 2006.145.16:23:37.15:checkk5 2006.145.16:23:37.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.16:23:38.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.16:23:38.44/chk_autoobs//k5ts3/ autoobs is running! 2006.145.16:23:38.87/chk_autoobs//k5ts4/ autoobs is running! 2006.145.16:23:39.30/chk_obsdata//k5ts1/T1451622??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.16:23:39.74/chk_obsdata//k5ts2/T1451622??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.16:23:40.18/chk_obsdata//k5ts3/T1451622??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.16:23:40.63/chk_obsdata//k5ts4/T1451622??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.16:23:41.37/k5log//k5ts1_log_newline 2006.145.16:23:42.13/k5log//k5ts2_log_newline 2006.145.16:23:42.88/k5log//k5ts3_log_newline 2006.145.16:23:43.61/k5log//k5ts4_log_newline 2006.145.16:23:43.64/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.16:23:43.64:setupk4=1 2006.145.16:23:43.64$setupk4/echo=on 2006.145.16:23:43.64$setupk4/pcalon 2006.145.16:23:43.64$pcalon/"no phase cal control is implemented here 2006.145.16:23:43.64$setupk4/"tpicd=stop 2006.145.16:23:43.64$setupk4/"rec=synch_on 2006.145.16:23:43.64$setupk4/"rec_mode=128 2006.145.16:23:43.64$setupk4/!* 2006.145.16:23:43.64$setupk4/recpk4 2006.145.16:23:43.64$recpk4/recpatch= 2006.145.16:23:43.65$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.16:23:43.65$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.16:23:43.65$setupk4/vck44 2006.145.16:23:43.65$vck44/valo=1,524.99 2006.145.16:23:43.65#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.16:23:43.65#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.16:23:43.65#ibcon#ireg 17 cls_cnt 0 2006.145.16:23:43.65#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.16:23:43.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.16:23:43.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.16:23:43.68#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.16:23:43.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.16:23:43.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.16:23:43.73#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.16:23:43.73#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.16:23:43.73$vck44/va=1,8 2006.145.16:23:43.73#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.16:23:43.73#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.16:23:43.73#ibcon#ireg 11 cls_cnt 2 2006.145.16:23:43.73#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.16:23:43.73#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.16:23:43.73#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.16:23:43.75#ibcon#[25=AT01-08\r\n] 2006.145.16:23:43.78#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.16:23:43.78#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.16:23:43.78#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.16:23:43.78#ibcon#ireg 7 cls_cnt 0 2006.145.16:23:43.78#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.16:23:43.90#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.16:23:43.90#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.16:23:43.92#ibcon#[25=USB\r\n] 2006.145.16:23:43.97#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.16:23:43.97#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.16:23:43.97#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.16:23:43.97#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.16:23:43.97$vck44/valo=2,534.99 2006.145.16:23:43.97#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.16:23:43.97#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.16:23:43.97#ibcon#ireg 17 cls_cnt 0 2006.145.16:23:43.97#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.16:23:43.97#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.16:23:43.97#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.16:23:43.99#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.16:23:44.02#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.16:23:44.02#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.16:23:44.02#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.16:23:44.02#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.16:23:44.02$vck44/va=2,7 2006.145.16:23:44.02#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.16:23:44.02#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.16:23:44.02#ibcon#ireg 11 cls_cnt 2 2006.145.16:23:44.02#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.16:23:44.09#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.16:23:44.09#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.16:23:44.11#ibcon#[25=AT02-07\r\n] 2006.145.16:23:44.14#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.16:23:44.14#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.16:23:44.14#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.16:23:44.14#ibcon#ireg 7 cls_cnt 0 2006.145.16:23:44.14#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.16:23:44.26#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.16:23:44.26#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.16:23:44.28#ibcon#[25=USB\r\n] 2006.145.16:23:44.31#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.16:23:44.31#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.16:23:44.31#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.16:23:44.31#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.16:23:44.31$vck44/valo=3,564.99 2006.145.16:23:44.31#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.16:23:44.31#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.16:23:44.31#ibcon#ireg 17 cls_cnt 0 2006.145.16:23:44.31#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.16:23:44.31#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.16:23:44.31#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.16:23:44.33#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.16:23:44.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.16:23:44.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.16:23:44.37#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.16:23:44.37#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.16:23:44.37$vck44/va=3,8 2006.145.16:23:44.37#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.16:23:44.37#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.16:23:44.37#ibcon#ireg 11 cls_cnt 2 2006.145.16:23:44.37#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.16:23:44.43#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.16:23:44.43#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.16:23:44.45#ibcon#[25=AT03-08\r\n] 2006.145.16:23:44.48#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.16:23:44.48#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.16:23:44.48#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.16:23:44.48#ibcon#ireg 7 cls_cnt 0 2006.145.16:23:44.48#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.16:23:44.60#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.16:23:44.60#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.16:23:44.62#ibcon#[25=USB\r\n] 2006.145.16:23:44.65#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.16:23:44.65#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.16:23:44.65#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.16:23:44.65#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.16:23:44.65$vck44/valo=4,624.99 2006.145.16:23:44.65#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.16:23:44.65#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.16:23:44.65#ibcon#ireg 17 cls_cnt 0 2006.145.16:23:44.65#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.16:23:44.65#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.16:23:44.65#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.16:23:44.67#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.16:23:44.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.16:23:44.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.16:23:44.71#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.16:23:44.71#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.16:23:44.71$vck44/va=4,7 2006.145.16:23:44.71#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.16:23:44.71#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.16:23:44.71#ibcon#ireg 11 cls_cnt 2 2006.145.16:23:44.71#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.16:23:44.77#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.16:23:44.77#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.16:23:44.79#ibcon#[25=AT04-07\r\n] 2006.145.16:23:44.82#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.16:23:44.82#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.16:23:44.82#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.16:23:44.82#ibcon#ireg 7 cls_cnt 0 2006.145.16:23:44.82#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.16:23:44.94#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.16:23:44.94#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.16:23:44.96#ibcon#[25=USB\r\n] 2006.145.16:23:44.99#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.16:23:44.99#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.16:23:44.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.16:23:44.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.16:23:44.99$vck44/valo=5,734.99 2006.145.16:23:44.99#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.16:23:44.99#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.16:23:44.99#ibcon#ireg 17 cls_cnt 0 2006.145.16:23:44.99#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.16:23:44.99#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.16:23:44.99#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.16:23:45.01#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.16:23:45.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.16:23:45.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.16:23:45.05#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.16:23:45.05#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.16:23:45.05$vck44/va=5,4 2006.145.16:23:45.05#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.16:23:45.05#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.16:23:45.05#ibcon#ireg 11 cls_cnt 2 2006.145.16:23:45.05#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.16:23:45.11#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.16:23:45.11#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.16:23:45.14#ibcon#[25=AT05-04\r\n] 2006.145.16:23:45.16#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.16:23:45.16#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.16:23:45.16#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.16:23:45.16#ibcon#ireg 7 cls_cnt 0 2006.145.16:23:45.16#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.16:23:45.28#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.16:23:45.28#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.16:23:45.30#ibcon#[25=USB\r\n] 2006.145.16:23:45.33#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.16:23:45.33#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.16:23:45.33#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.16:23:45.33#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.16:23:45.33$vck44/valo=6,814.99 2006.145.16:23:45.33#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.16:23:45.33#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.16:23:45.33#ibcon#ireg 17 cls_cnt 0 2006.145.16:23:45.33#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.16:23:45.33#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.16:23:45.33#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.16:23:45.35#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.16:23:45.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.16:23:45.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.16:23:45.39#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.16:23:45.39#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.16:23:45.39$vck44/va=6,4 2006.145.16:23:45.39#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.16:23:45.39#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.16:23:45.39#ibcon#ireg 11 cls_cnt 2 2006.145.16:23:45.39#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.16:23:45.45#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.16:23:45.45#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.16:23:45.47#ibcon#[25=AT06-04\r\n] 2006.145.16:23:45.50#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.16:23:45.50#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.16:23:45.50#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.16:23:45.50#ibcon#ireg 7 cls_cnt 0 2006.145.16:23:45.50#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.16:23:45.62#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.16:23:45.62#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.16:23:45.64#ibcon#[25=USB\r\n] 2006.145.16:23:45.67#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.16:23:45.67#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.16:23:45.67#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.16:23:45.67#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.16:23:45.67$vck44/valo=7,864.99 2006.145.16:23:45.67#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.16:23:45.67#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.16:23:45.67#ibcon#ireg 17 cls_cnt 0 2006.145.16:23:45.67#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.16:23:45.67#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.16:23:45.67#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.16:23:45.69#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.16:23:45.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.16:23:45.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.16:23:45.73#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.16:23:45.73#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.16:23:45.73$vck44/va=7,4 2006.145.16:23:45.73#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.16:23:45.73#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.16:23:45.73#ibcon#ireg 11 cls_cnt 2 2006.145.16:23:45.73#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.16:23:45.79#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.16:23:45.79#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.16:23:45.81#ibcon#[25=AT07-04\r\n] 2006.145.16:23:45.84#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.16:23:45.84#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.16:23:45.84#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.16:23:45.84#ibcon#ireg 7 cls_cnt 0 2006.145.16:23:45.84#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.16:23:45.96#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.16:23:45.96#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.16:23:45.98#ibcon#[25=USB\r\n] 2006.145.16:23:46.01#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.16:23:46.01#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.16:23:46.01#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.16:23:46.01#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.16:23:46.01$vck44/valo=8,884.99 2006.145.16:23:46.01#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.16:23:46.01#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.16:23:46.01#ibcon#ireg 17 cls_cnt 0 2006.145.16:23:46.01#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.16:23:46.01#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.16:23:46.01#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.16:23:46.03#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.16:23:46.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.16:23:46.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.16:23:46.07#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.16:23:46.07#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.16:23:46.07$vck44/va=8,4 2006.145.16:23:46.07#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.16:23:46.07#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.16:23:46.07#ibcon#ireg 11 cls_cnt 2 2006.145.16:23:46.07#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.16:23:46.13#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.16:23:46.13#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.16:23:46.15#ibcon#[25=AT08-04\r\n] 2006.145.16:23:46.18#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.16:23:46.18#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.16:23:46.18#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.16:23:46.18#ibcon#ireg 7 cls_cnt 0 2006.145.16:23:46.18#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.16:23:46.30#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.16:23:46.30#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.16:23:46.32#ibcon#[25=USB\r\n] 2006.145.16:23:46.36#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.16:23:46.36#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.16:23:46.36#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.16:23:46.36#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.16:23:46.36$vck44/vblo=1,629.99 2006.145.16:23:46.36#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.16:23:46.36#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.16:23:46.36#ibcon#ireg 17 cls_cnt 0 2006.145.16:23:46.36#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.16:23:46.36#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.16:23:46.36#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.16:23:46.37#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.16:23:46.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.16:23:46.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.16:23:46.41#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.16:23:46.41#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.16:23:46.41$vck44/vb=1,3 2006.145.16:23:46.41#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.16:23:46.41#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.16:23:46.41#ibcon#ireg 11 cls_cnt 2 2006.145.16:23:46.41#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.16:23:46.41#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.16:23:46.41#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.16:23:46.43#ibcon#[27=AT01-03\r\n] 2006.145.16:23:46.46#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.16:23:46.46#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.16:23:46.46#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.16:23:46.46#ibcon#ireg 7 cls_cnt 0 2006.145.16:23:46.46#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.16:23:46.58#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.16:23:46.58#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.16:23:46.60#ibcon#[27=USB\r\n] 2006.145.16:23:46.63#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.16:23:46.63#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.16:23:46.63#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.16:23:46.63#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.16:23:46.63$vck44/vblo=2,634.99 2006.145.16:23:46.63#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.16:23:46.63#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.16:23:46.63#ibcon#ireg 17 cls_cnt 0 2006.145.16:23:46.63#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.16:23:46.63#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.16:23:46.63#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.16:23:46.65#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.16:23:46.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.16:23:46.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.16:23:46.69#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.16:23:46.69#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.16:23:46.69$vck44/vb=2,4 2006.145.16:23:46.69#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.16:23:46.69#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.16:23:46.69#ibcon#ireg 11 cls_cnt 2 2006.145.16:23:46.69#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.16:23:46.75#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.16:23:46.75#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.16:23:46.77#ibcon#[27=AT02-04\r\n] 2006.145.16:23:46.80#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.16:23:46.80#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.16:23:46.80#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.16:23:46.80#ibcon#ireg 7 cls_cnt 0 2006.145.16:23:46.80#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.16:23:46.92#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.16:23:46.92#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.16:23:46.94#ibcon#[27=USB\r\n] 2006.145.16:23:46.97#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.16:23:46.97#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.16:23:46.97#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.16:23:46.97#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.16:23:46.97$vck44/vblo=3,649.99 2006.145.16:23:46.97#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.16:23:46.97#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.16:23:46.97#ibcon#ireg 17 cls_cnt 0 2006.145.16:23:46.97#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.16:23:46.97#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.16:23:46.97#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.16:23:46.99#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.16:23:47.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.16:23:47.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.16:23:47.03#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.16:23:47.03#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.16:23:47.03$vck44/vb=3,4 2006.145.16:23:47.03#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.16:23:47.03#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.16:23:47.03#ibcon#ireg 11 cls_cnt 2 2006.145.16:23:47.03#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.16:23:47.09#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.16:23:47.09#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.16:23:47.11#ibcon#[27=AT03-04\r\n] 2006.145.16:23:47.14#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.16:23:47.14#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.16:23:47.14#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.16:23:47.14#ibcon#ireg 7 cls_cnt 0 2006.145.16:23:47.14#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.16:23:47.26#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.16:23:47.26#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.16:23:47.28#ibcon#[27=USB\r\n] 2006.145.16:23:47.31#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.16:23:47.31#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.16:23:47.31#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.16:23:47.31#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.16:23:47.31$vck44/vblo=4,679.99 2006.145.16:23:47.31#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.16:23:47.31#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.16:23:47.31#ibcon#ireg 17 cls_cnt 0 2006.145.16:23:47.31#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.16:23:47.31#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.16:23:47.31#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.16:23:47.33#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.16:23:47.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.16:23:47.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.16:23:47.37#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.16:23:47.37#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.16:23:47.37$vck44/vb=4,4 2006.145.16:23:47.37#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.16:23:47.37#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.16:23:47.37#ibcon#ireg 11 cls_cnt 2 2006.145.16:23:47.37#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.16:23:47.43#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.16:23:47.43#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.16:23:47.45#ibcon#[27=AT04-04\r\n] 2006.145.16:23:47.48#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.16:23:47.48#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.16:23:47.48#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.16:23:47.48#ibcon#ireg 7 cls_cnt 0 2006.145.16:23:47.48#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.16:23:47.60#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.16:23:47.60#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.16:23:47.62#ibcon#[27=USB\r\n] 2006.145.16:23:47.65#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.16:23:47.65#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.16:23:47.65#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.16:23:47.65#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.16:23:47.65$vck44/vblo=5,709.99 2006.145.16:23:47.65#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.16:23:47.65#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.16:23:47.65#ibcon#ireg 17 cls_cnt 0 2006.145.16:23:47.65#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.16:23:47.65#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.16:23:47.65#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.16:23:47.67#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.16:23:47.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.16:23:47.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.16:23:47.71#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.16:23:47.71#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.16:23:47.71$vck44/vb=5,4 2006.145.16:23:47.71#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.16:23:47.71#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.16:23:47.71#ibcon#ireg 11 cls_cnt 2 2006.145.16:23:47.71#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.16:23:47.77#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.16:23:47.77#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.16:23:47.79#ibcon#[27=AT05-04\r\n] 2006.145.16:23:47.82#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.16:23:47.82#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.16:23:47.82#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.16:23:47.82#ibcon#ireg 7 cls_cnt 0 2006.145.16:23:47.82#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.16:23:47.94#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.16:23:47.94#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.16:23:47.96#ibcon#[27=USB\r\n] 2006.145.16:23:47.99#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.16:23:47.99#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.16:23:47.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.16:23:47.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.16:23:47.99$vck44/vblo=6,719.99 2006.145.16:23:47.99#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.16:23:47.99#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.16:23:47.99#ibcon#ireg 17 cls_cnt 0 2006.145.16:23:47.99#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.16:23:47.99#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.16:23:47.99#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.16:23:48.01#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.16:23:48.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.16:23:48.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.16:23:48.05#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.16:23:48.05#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.16:23:48.05$vck44/vb=6,4 2006.145.16:23:48.05#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.16:23:48.05#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.16:23:48.05#ibcon#ireg 11 cls_cnt 2 2006.145.16:23:48.05#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.16:23:48.11#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.16:23:48.11#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.16:23:48.13#ibcon#[27=AT06-04\r\n] 2006.145.16:23:48.16#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.16:23:48.16#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.16:23:48.16#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.16:23:48.16#ibcon#ireg 7 cls_cnt 0 2006.145.16:23:48.16#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.16:23:48.28#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.16:23:48.28#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.16:23:48.30#ibcon#[27=USB\r\n] 2006.145.16:23:48.33#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.16:23:48.33#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.16:23:48.33#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.16:23:48.33#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.16:23:48.33$vck44/vblo=7,734.99 2006.145.16:23:48.33#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.16:23:48.33#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.16:23:48.33#ibcon#ireg 17 cls_cnt 0 2006.145.16:23:48.33#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.16:23:48.33#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.16:23:48.33#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.16:23:48.35#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.16:23:48.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.16:23:48.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.16:23:48.39#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.16:23:48.39#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.16:23:48.39$vck44/vb=7,4 2006.145.16:23:48.39#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.16:23:48.39#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.16:23:48.39#ibcon#ireg 11 cls_cnt 2 2006.145.16:23:48.39#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.16:23:48.45#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.16:23:48.45#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.16:23:48.47#ibcon#[27=AT07-04\r\n] 2006.145.16:23:48.50#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.16:23:48.50#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.16:23:48.50#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.16:23:48.50#ibcon#ireg 7 cls_cnt 0 2006.145.16:23:48.50#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.16:23:48.62#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.16:23:48.62#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.16:23:48.64#ibcon#[27=USB\r\n] 2006.145.16:23:48.67#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.16:23:48.67#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.16:23:48.67#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.16:23:48.67#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.16:23:48.67$vck44/vblo=8,744.99 2006.145.16:23:48.67#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.16:23:48.67#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.16:23:48.67#ibcon#ireg 17 cls_cnt 0 2006.145.16:23:48.67#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.16:23:48.67#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.16:23:48.67#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.16:23:48.69#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.16:23:48.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.16:23:48.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.16:23:48.73#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.16:23:48.73#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.16:23:48.73$vck44/vb=8,4 2006.145.16:23:48.73#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.16:23:48.73#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.16:23:48.73#ibcon#ireg 11 cls_cnt 2 2006.145.16:23:48.73#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.16:23:48.79#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.16:23:48.79#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.16:23:48.81#ibcon#[27=AT08-04\r\n] 2006.145.16:23:48.84#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.16:23:48.84#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.16:23:48.84#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.16:23:48.84#ibcon#ireg 7 cls_cnt 0 2006.145.16:23:48.84#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.16:23:48.96#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.16:23:48.96#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.16:23:48.98#ibcon#[27=USB\r\n] 2006.145.16:23:49.01#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.16:23:49.01#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.16:23:49.01#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.16:23:49.01#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.16:23:49.01$vck44/vabw=wide 2006.145.16:23:49.01#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.16:23:49.01#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.16:23:49.01#ibcon#ireg 8 cls_cnt 0 2006.145.16:23:49.01#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.16:23:49.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.16:23:49.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.16:23:49.03#ibcon#[25=BW32\r\n] 2006.145.16:23:49.04#abcon#<5=/06 1.5 2.7 15.87 871020.1\r\n> 2006.145.16:23:49.06#abcon#{5=INTERFACE CLEAR} 2006.145.16:23:49.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.16:23:49.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.16:23:49.06#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.16:23:49.06#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.16:23:49.06$vck44/vbbw=wide 2006.145.16:23:49.06#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.16:23:49.06#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.16:23:49.06#ibcon#ireg 8 cls_cnt 0 2006.145.16:23:49.07#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.16:23:49.12#abcon#[5=S1D000X0/0*\r\n] 2006.145.16:23:49.12#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.16:23:49.12#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.16:23:49.14#ibcon#[27=BW32\r\n] 2006.145.16:23:49.17#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.16:23:49.17#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.16:23:49.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.16:23:49.17#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.16:23:49.17$setupk4/ifdk4 2006.145.16:23:49.17$ifdk4/lo= 2006.145.16:23:49.17$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.16:23:49.18$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.16:23:49.18$ifdk4/patch= 2006.145.16:23:49.18$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.16:23:49.18$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.16:23:49.18$setupk4/!*+20s 2006.145.16:23:59.21#abcon#<5=/07 1.5 2.8 15.87 871020.1\r\n> 2006.145.16:23:59.23#abcon#{5=INTERFACE CLEAR} 2006.145.16:23:59.29#abcon#[5=S1D000X0/0*\r\n] 2006.145.16:24:03.66$setupk4/"tpicd 2006.145.16:24:03.66$setupk4/echo=off 2006.145.16:24:03.66$setupk4/xlog=off 2006.145.16:24:03.66:!2006.145.16:25:17 2006.145.16:24:20.14#trakl#Source acquired 2006.145.16:24:21.14#flagr#flagr/antenna,acquired 2006.145.16:25:17.00:preob 2006.145.16:25:17.14/onsource/TRACKING 2006.145.16:25:17.14:!2006.145.16:25:27 2006.145.16:25:27.00:"tape 2006.145.16:25:27.00:"st=record 2006.145.16:25:27.00:data_valid=on 2006.145.16:25:27.00:midob 2006.145.16:25:27.14/onsource/TRACKING 2006.145.16:25:27.15/wx/15.86,1020.0,86 2006.145.16:25:27.28/cable/+6.5471E-03 2006.145.16:25:28.37/va/01,08,usb,yes,28,30 2006.145.16:25:28.37/va/02,07,usb,yes,30,31 2006.145.16:25:28.37/va/03,08,usb,yes,28,29 2006.145.16:25:28.37/va/04,07,usb,yes,31,33 2006.145.16:25:28.37/va/05,04,usb,yes,27,28 2006.145.16:25:28.37/va/06,04,usb,yes,31,31 2006.145.16:25:28.37/va/07,04,usb,yes,31,32 2006.145.16:25:28.37/va/08,04,usb,yes,27,32 2006.145.16:25:28.60/valo/01,524.99,yes,locked 2006.145.16:25:28.60/valo/02,534.99,yes,locked 2006.145.16:25:28.60/valo/03,564.99,yes,locked 2006.145.16:25:28.60/valo/04,624.99,yes,locked 2006.145.16:25:28.60/valo/05,734.99,yes,locked 2006.145.16:25:28.60/valo/06,814.99,yes,locked 2006.145.16:25:28.60/valo/07,864.99,yes,locked 2006.145.16:25:28.60/valo/08,884.99,yes,locked 2006.145.16:25:29.69/vb/01,03,usb,yes,36,33 2006.145.16:25:29.69/vb/02,04,usb,yes,31,31 2006.145.16:25:29.69/vb/03,04,usb,yes,28,31 2006.145.16:25:29.69/vb/04,04,usb,yes,33,31 2006.145.16:25:29.69/vb/05,04,usb,yes,25,28 2006.145.16:25:29.69/vb/06,04,usb,yes,30,26 2006.145.16:25:29.69/vb/07,04,usb,yes,29,29 2006.145.16:25:29.69/vb/08,04,usb,yes,27,30 2006.145.16:25:29.92/vblo/01,629.99,yes,locked 2006.145.16:25:29.92/vblo/02,634.99,yes,locked 2006.145.16:25:29.92/vblo/03,649.99,yes,locked 2006.145.16:25:29.92/vblo/04,679.99,yes,locked 2006.145.16:25:29.92/vblo/05,709.99,yes,locked 2006.145.16:25:29.92/vblo/06,719.99,yes,locked 2006.145.16:25:29.92/vblo/07,734.99,yes,locked 2006.145.16:25:29.92/vblo/08,744.99,yes,locked 2006.145.16:25:30.07/vabw/8 2006.145.16:25:30.22/vbbw/8 2006.145.16:25:30.31/xfe/off,on,15.0 2006.145.16:25:30.68/ifatt/23,28,28,28 2006.145.16:25:31.06/fmout-gps/S +4.2E-08 2006.145.16:25:31.15:!2006.145.16:27:47 2006.145.16:27:47.01:data_valid=off 2006.145.16:27:47.02:"et 2006.145.16:27:47.02:!+3s 2006.145.16:27:50.05:"tape 2006.145.16:27:50.06:postob 2006.145.16:27:50.20/cable/+6.5484E-03 2006.145.16:27:50.21/wx/15.86,1020.0,87 2006.145.16:27:50.31/fmout-gps/S +4.2E-08 2006.145.16:27:50.31:scan_name=145-1634,jd0605,90 2006.145.16:27:50.31:source=1908-201,191109.65,-200655.1,2000.0,cw 2006.145.16:27:51.14#flagr#flagr/antenna,new-source 2006.145.16:27:51.15:checkk5 2006.145.16:27:51.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.16:27:52.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.16:27:52.44/chk_autoobs//k5ts3/ autoobs is running! 2006.145.16:27:52.87/chk_autoobs//k5ts4/ autoobs is running! 2006.145.16:27:53.31/chk_obsdata//k5ts1/T1451625??a.dat file size is correct (nominal:560MB, actual:556MB). 2006.145.16:27:53.74/chk_obsdata//k5ts2/T1451625??b.dat file size is correct (nominal:560MB, actual:556MB). 2006.145.16:27:54.19/chk_obsdata//k5ts3/T1451625??c.dat file size is correct (nominal:560MB, actual:556MB). 2006.145.16:27:54.64/chk_obsdata//k5ts4/T1451625??d.dat file size is correct (nominal:560MB, actual:556MB). 2006.145.16:27:55.40/k5log//k5ts1_log_newline 2006.145.16:27:56.15/k5log//k5ts2_log_newline 2006.145.16:27:56.89/k5log//k5ts3_log_newline 2006.145.16:27:57.65/k5log//k5ts4_log_newline 2006.145.16:27:57.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.16:27:57.67:setupk4=1 2006.145.16:27:57.67$setupk4/echo=on 2006.145.16:27:57.67$setupk4/pcalon 2006.145.16:27:57.67$pcalon/"no phase cal control is implemented here 2006.145.16:27:57.67$setupk4/"tpicd=stop 2006.145.16:27:57.67$setupk4/"rec=synch_on 2006.145.16:27:57.67$setupk4/"rec_mode=128 2006.145.16:27:57.67$setupk4/!* 2006.145.16:27:57.67$setupk4/recpk4 2006.145.16:27:57.67$recpk4/recpatch= 2006.145.16:27:57.68$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.16:27:57.68$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.16:27:57.68$setupk4/vck44 2006.145.16:27:57.68$vck44/valo=1,524.99 2006.145.16:27:57.68#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.16:27:57.68#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.16:27:57.68#ibcon#ireg 17 cls_cnt 0 2006.145.16:27:57.68#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.16:27:57.68#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.16:27:57.68#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.16:27:57.71#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.16:27:57.76#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.16:27:57.76#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.16:27:57.76#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.16:27:57.76#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.16:27:57.76$vck44/va=1,8 2006.145.16:27:57.76#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.16:27:57.76#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.16:27:57.76#ibcon#ireg 11 cls_cnt 2 2006.145.16:27:57.76#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.16:27:57.76#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.16:27:57.76#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.16:27:57.78#ibcon#[25=AT01-08\r\n] 2006.145.16:27:57.81#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.16:27:57.81#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.16:27:57.81#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.16:27:57.81#ibcon#ireg 7 cls_cnt 0 2006.145.16:27:57.81#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.16:27:57.94#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.16:27:57.94#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.16:27:57.95#ibcon#[25=USB\r\n] 2006.145.16:27:57.98#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.16:27:57.98#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.16:27:57.98#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.16:27:57.98#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.16:27:57.98$vck44/valo=2,534.99 2006.145.16:27:57.98#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.16:27:57.98#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.16:27:57.98#ibcon#ireg 17 cls_cnt 0 2006.145.16:27:57.98#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.16:27:57.98#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.16:27:57.98#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.16:27:58.01#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.16:27:58.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.16:27:58.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.16:27:58.05#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.16:27:58.05#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.16:27:58.05$vck44/va=2,7 2006.145.16:27:58.05#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.16:27:58.05#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.16:27:58.05#ibcon#ireg 11 cls_cnt 2 2006.145.16:27:58.05#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.16:27:58.10#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.16:27:58.10#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.16:27:58.12#ibcon#[25=AT02-07\r\n] 2006.145.16:27:58.15#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.16:27:58.15#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.16:27:58.15#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.16:27:58.15#ibcon#ireg 7 cls_cnt 0 2006.145.16:27:58.15#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.16:27:58.27#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.16:27:58.27#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.16:27:58.29#ibcon#[25=USB\r\n] 2006.145.16:27:58.32#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.16:27:58.32#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.16:27:58.32#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.16:27:58.32#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.16:27:58.32$vck44/valo=3,564.99 2006.145.16:27:58.32#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.16:27:58.32#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.16:27:58.32#ibcon#ireg 17 cls_cnt 0 2006.145.16:27:58.32#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.16:27:58.32#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.16:27:58.32#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.16:27:58.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.16:27:58.38#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.16:27:58.38#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.16:27:58.38#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.16:27:58.38#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.16:27:58.38$vck44/va=3,8 2006.145.16:27:58.38#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.16:27:58.38#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.16:27:58.38#ibcon#ireg 11 cls_cnt 2 2006.145.16:27:58.38#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.16:27:58.44#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.16:27:58.44#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.16:27:58.46#ibcon#[25=AT03-08\r\n] 2006.145.16:27:58.49#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.16:27:58.49#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.16:27:58.49#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.16:27:58.49#ibcon#ireg 7 cls_cnt 0 2006.145.16:27:58.49#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.16:27:58.61#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.16:27:58.61#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.16:27:58.63#ibcon#[25=USB\r\n] 2006.145.16:27:58.66#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.16:27:58.66#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.16:27:58.66#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.16:27:58.66#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.16:27:58.66$vck44/valo=4,624.99 2006.145.16:27:58.66#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.16:27:58.66#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.16:27:58.66#ibcon#ireg 17 cls_cnt 0 2006.145.16:27:58.66#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.16:27:58.66#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.16:27:58.66#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.16:27:58.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.16:27:58.72#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.16:27:58.72#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.16:27:58.72#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.16:27:58.72#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.16:27:58.72$vck44/va=4,7 2006.145.16:27:58.72#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.16:27:58.72#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.16:27:58.72#ibcon#ireg 11 cls_cnt 2 2006.145.16:27:58.72#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.16:27:58.78#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.16:27:58.78#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.16:27:58.80#ibcon#[25=AT04-07\r\n] 2006.145.16:27:58.83#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.16:27:58.83#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.16:27:58.83#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.16:27:58.83#ibcon#ireg 7 cls_cnt 0 2006.145.16:27:58.83#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.16:27:58.95#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.16:27:58.95#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.16:27:58.97#ibcon#[25=USB\r\n] 2006.145.16:27:59.00#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.16:27:59.00#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.16:27:59.00#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.16:27:59.00#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.16:27:59.00$vck44/valo=5,734.99 2006.145.16:27:59.00#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.16:27:59.00#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.16:27:59.00#ibcon#ireg 17 cls_cnt 0 2006.145.16:27:59.00#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.16:27:59.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.16:27:59.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.16:27:59.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.16:27:59.06#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.16:27:59.06#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.16:27:59.06#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.16:27:59.06#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.16:27:59.06$vck44/va=5,4 2006.145.16:27:59.06#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.16:27:59.06#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.16:27:59.06#ibcon#ireg 11 cls_cnt 2 2006.145.16:27:59.06#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.16:27:59.12#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.16:27:59.12#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.16:27:59.15#ibcon#[25=AT05-04\r\n] 2006.145.16:27:59.18#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.16:27:59.18#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.16:27:59.18#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.16:27:59.18#ibcon#ireg 7 cls_cnt 0 2006.145.16:27:59.18#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.16:27:59.30#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.16:27:59.30#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.16:27:59.32#ibcon#[25=USB\r\n] 2006.145.16:27:59.35#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.16:27:59.35#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.16:27:59.35#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.16:27:59.35#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.16:27:59.35$vck44/valo=6,814.99 2006.145.16:27:59.35#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.16:27:59.35#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.16:27:59.35#ibcon#ireg 17 cls_cnt 0 2006.145.16:27:59.35#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.16:27:59.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.16:27:59.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.16:27:59.37#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.16:27:59.41#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.16:27:59.41#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.16:27:59.41#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.16:27:59.41#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.16:27:59.41$vck44/va=6,4 2006.145.16:27:59.41#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.16:27:59.41#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.16:27:59.41#ibcon#ireg 11 cls_cnt 2 2006.145.16:27:59.41#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.16:27:59.47#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.16:27:59.47#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.16:27:59.49#ibcon#[25=AT06-04\r\n] 2006.145.16:27:59.52#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.16:27:59.52#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.16:27:59.52#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.16:27:59.52#ibcon#ireg 7 cls_cnt 0 2006.145.16:27:59.52#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.16:27:59.64#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.16:27:59.64#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.16:27:59.66#ibcon#[25=USB\r\n] 2006.145.16:27:59.69#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.16:27:59.69#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.16:27:59.69#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.16:27:59.69#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.16:27:59.69$vck44/valo=7,864.99 2006.145.16:27:59.69#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.16:27:59.69#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.16:27:59.69#ibcon#ireg 17 cls_cnt 0 2006.145.16:27:59.69#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.16:27:59.69#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.16:27:59.69#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.16:27:59.71#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.16:27:59.75#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.16:27:59.75#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.16:27:59.75#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.16:27:59.75#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.16:27:59.75$vck44/va=7,4 2006.145.16:27:59.75#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.16:27:59.75#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.16:27:59.75#ibcon#ireg 11 cls_cnt 2 2006.145.16:27:59.75#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.16:27:59.81#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.16:27:59.81#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.16:27:59.83#ibcon#[25=AT07-04\r\n] 2006.145.16:27:59.86#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.16:27:59.86#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.16:27:59.86#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.16:27:59.86#ibcon#ireg 7 cls_cnt 0 2006.145.16:27:59.86#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.16:27:59.98#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.16:27:59.98#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.16:28:00.00#ibcon#[25=USB\r\n] 2006.145.16:28:00.03#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.16:28:00.03#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.16:28:00.03#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.16:28:00.03#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.16:28:00.03$vck44/valo=8,884.99 2006.145.16:28:00.03#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.16:28:00.03#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.16:28:00.03#ibcon#ireg 17 cls_cnt 0 2006.145.16:28:00.03#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.16:28:00.03#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.16:28:00.03#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.16:28:00.05#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.16:28:00.09#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.16:28:00.09#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.16:28:00.09#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.16:28:00.09#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.16:28:00.09$vck44/va=8,4 2006.145.16:28:00.09#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.16:28:00.09#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.16:28:00.09#ibcon#ireg 11 cls_cnt 2 2006.145.16:28:00.09#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.16:28:00.15#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.16:28:00.15#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.16:28:00.17#ibcon#[25=AT08-04\r\n] 2006.145.16:28:00.20#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.16:28:00.20#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.16:28:00.20#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.16:28:00.20#ibcon#ireg 7 cls_cnt 0 2006.145.16:28:00.20#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.16:28:00.32#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.16:28:00.32#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.16:28:00.34#ibcon#[25=USB\r\n] 2006.145.16:28:00.37#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.16:28:00.37#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.16:28:00.37#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.16:28:00.37#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.16:28:00.37$vck44/vblo=1,629.99 2006.145.16:28:00.37#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.16:28:00.37#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.16:28:00.37#ibcon#ireg 17 cls_cnt 0 2006.145.16:28:00.37#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.16:28:00.37#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.16:28:00.37#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.16:28:00.39#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.16:28:00.43#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.16:28:00.43#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.16:28:00.43#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.16:28:00.43#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.16:28:00.43$vck44/vb=1,3 2006.145.16:28:00.43#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.16:28:00.43#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.16:28:00.43#ibcon#ireg 11 cls_cnt 2 2006.145.16:28:00.43#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.16:28:00.43#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.16:28:00.43#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.16:28:00.45#ibcon#[27=AT01-03\r\n] 2006.145.16:28:00.48#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.16:28:00.48#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.16:28:00.48#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.16:28:00.48#ibcon#ireg 7 cls_cnt 0 2006.145.16:28:00.48#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.16:28:00.60#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.16:28:00.60#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.16:28:00.62#ibcon#[27=USB\r\n] 2006.145.16:28:00.65#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.16:28:00.65#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.16:28:00.65#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.16:28:00.65#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.16:28:00.65$vck44/vblo=2,634.99 2006.145.16:28:00.65#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.16:28:00.65#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.16:28:00.65#ibcon#ireg 17 cls_cnt 0 2006.145.16:28:00.65#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.16:28:00.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.16:28:00.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.16:28:00.67#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.16:28:00.71#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.16:28:00.71#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.16:28:00.71#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.16:28:00.71#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.16:28:00.71$vck44/vb=2,4 2006.145.16:28:00.71#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.16:28:00.71#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.16:28:00.71#ibcon#ireg 11 cls_cnt 2 2006.145.16:28:00.71#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.16:28:00.77#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.16:28:00.77#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.16:28:00.79#ibcon#[27=AT02-04\r\n] 2006.145.16:28:00.82#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.16:28:00.82#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.16:28:00.82#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.16:28:00.82#ibcon#ireg 7 cls_cnt 0 2006.145.16:28:00.82#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.16:28:00.94#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.16:28:00.94#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.16:28:00.96#ibcon#[27=USB\r\n] 2006.145.16:28:00.99#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.16:28:00.99#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.16:28:00.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.16:28:00.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.16:28:00.99$vck44/vblo=3,649.99 2006.145.16:28:00.99#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.16:28:00.99#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.16:28:00.99#ibcon#ireg 17 cls_cnt 0 2006.145.16:28:00.99#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.16:28:00.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.16:28:00.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.16:28:01.01#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.16:28:01.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.16:28:01.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.16:28:01.05#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.16:28:01.05#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.16:28:01.05$vck44/vb=3,4 2006.145.16:28:01.05#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.16:28:01.05#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.16:28:01.05#ibcon#ireg 11 cls_cnt 2 2006.145.16:28:01.05#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.16:28:01.11#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.16:28:01.11#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.16:28:01.13#ibcon#[27=AT03-04\r\n] 2006.145.16:28:01.16#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.16:28:01.16#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.16:28:01.16#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.16:28:01.16#ibcon#ireg 7 cls_cnt 0 2006.145.16:28:01.16#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.16:28:01.28#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.16:28:01.28#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.16:28:01.30#ibcon#[27=USB\r\n] 2006.145.16:28:01.33#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.16:28:01.33#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.16:28:01.33#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.16:28:01.33#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.16:28:01.33$vck44/vblo=4,679.99 2006.145.16:28:01.33#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.16:28:01.33#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.16:28:01.33#ibcon#ireg 17 cls_cnt 0 2006.145.16:28:01.33#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.16:28:01.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.16:28:01.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.16:28:01.35#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.16:28:01.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.16:28:01.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.16:28:01.39#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.16:28:01.39#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.16:28:01.39$vck44/vb=4,4 2006.145.16:28:01.39#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.16:28:01.39#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.16:28:01.39#ibcon#ireg 11 cls_cnt 2 2006.145.16:28:01.39#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.16:28:01.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.16:28:01.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.16:28:01.47#ibcon#[27=AT04-04\r\n] 2006.145.16:28:01.50#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.16:28:01.50#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.16:28:01.50#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.16:28:01.50#ibcon#ireg 7 cls_cnt 0 2006.145.16:28:01.50#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.16:28:01.62#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.16:28:01.62#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.16:28:01.64#ibcon#[27=USB\r\n] 2006.145.16:28:01.67#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.16:28:01.67#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.16:28:01.67#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.16:28:01.67#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.16:28:01.67$vck44/vblo=5,709.99 2006.145.16:28:01.67#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.16:28:01.67#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.16:28:01.67#ibcon#ireg 17 cls_cnt 0 2006.145.16:28:01.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.16:28:01.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.16:28:01.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.16:28:01.69#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.16:28:01.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.16:28:01.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.16:28:01.73#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.16:28:01.73#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.16:28:01.73$vck44/vb=5,4 2006.145.16:28:01.73#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.16:28:01.73#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.16:28:01.73#ibcon#ireg 11 cls_cnt 2 2006.145.16:28:01.73#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.16:28:01.79#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.16:28:01.79#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.16:28:01.81#ibcon#[27=AT05-04\r\n] 2006.145.16:28:01.84#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.16:28:01.84#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.16:28:01.84#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.16:28:01.84#ibcon#ireg 7 cls_cnt 0 2006.145.16:28:01.84#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.16:28:01.96#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.16:28:01.96#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.16:28:01.98#ibcon#[27=USB\r\n] 2006.145.16:28:02.01#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.16:28:02.01#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.16:28:02.01#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.16:28:02.01#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.16:28:02.01$vck44/vblo=6,719.99 2006.145.16:28:02.01#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.16:28:02.01#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.16:28:02.01#ibcon#ireg 17 cls_cnt 0 2006.145.16:28:02.01#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.16:28:02.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.16:28:02.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.16:28:02.03#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.16:28:02.07#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.16:28:02.07#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.16:28:02.07#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.16:28:02.07#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.16:28:02.07$vck44/vb=6,4 2006.145.16:28:02.07#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.16:28:02.07#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.16:28:02.07#ibcon#ireg 11 cls_cnt 2 2006.145.16:28:02.07#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.16:28:02.13#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.16:28:02.13#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.16:28:02.15#ibcon#[27=AT06-04\r\n] 2006.145.16:28:02.18#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.16:28:02.18#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.16:28:02.18#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.16:28:02.18#ibcon#ireg 7 cls_cnt 0 2006.145.16:28:02.18#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.16:28:02.30#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.16:28:02.30#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.16:28:02.32#ibcon#[27=USB\r\n] 2006.145.16:28:02.35#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.16:28:02.35#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.16:28:02.35#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.16:28:02.35#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.16:28:02.35$vck44/vblo=7,734.99 2006.145.16:28:02.35#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.16:28:02.35#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.16:28:02.35#ibcon#ireg 17 cls_cnt 0 2006.145.16:28:02.35#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.16:28:02.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.16:28:02.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.16:28:02.37#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.16:28:02.41#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.16:28:02.41#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.16:28:02.41#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.16:28:02.41#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.16:28:02.41$vck44/vb=7,4 2006.145.16:28:02.41#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.16:28:02.41#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.16:28:02.41#ibcon#ireg 11 cls_cnt 2 2006.145.16:28:02.41#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.16:28:02.47#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.16:28:02.47#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.16:28:02.49#ibcon#[27=AT07-04\r\n] 2006.145.16:28:02.52#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.16:28:02.52#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.16:28:02.52#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.16:28:02.52#ibcon#ireg 7 cls_cnt 0 2006.145.16:28:02.52#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.16:28:02.64#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.16:28:02.64#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.16:28:02.66#ibcon#[27=USB\r\n] 2006.145.16:28:02.69#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.16:28:02.69#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.16:28:02.69#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.16:28:02.69#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.16:28:02.69$vck44/vblo=8,744.99 2006.145.16:28:02.69#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.16:28:02.69#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.16:28:02.69#ibcon#ireg 17 cls_cnt 0 2006.145.16:28:02.69#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.16:28:02.69#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.16:28:02.69#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.16:28:02.71#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.16:28:02.75#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.16:28:02.75#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.16:28:02.75#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.16:28:02.75#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.16:28:02.75$vck44/vb=8,4 2006.145.16:28:02.75#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.16:28:02.75#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.16:28:02.75#ibcon#ireg 11 cls_cnt 2 2006.145.16:28:02.75#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.16:28:02.81#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.16:28:02.81#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.16:28:02.83#ibcon#[27=AT08-04\r\n] 2006.145.16:28:02.86#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.16:28:02.86#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.16:28:02.86#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.16:28:02.86#ibcon#ireg 7 cls_cnt 0 2006.145.16:28:02.86#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.16:28:02.98#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.16:28:02.98#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.16:28:03.00#ibcon#[27=USB\r\n] 2006.145.16:28:03.03#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.16:28:03.03#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.16:28:03.03#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.16:28:03.03#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.16:28:03.03$vck44/vabw=wide 2006.145.16:28:03.03#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.16:28:03.03#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.16:28:03.03#ibcon#ireg 8 cls_cnt 0 2006.145.16:28:03.03#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.16:28:03.03#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.16:28:03.03#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.16:28:03.05#ibcon#[25=BW32\r\n] 2006.145.16:28:03.08#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.16:28:03.08#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.16:28:03.08#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.16:28:03.08#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.16:28:03.08$vck44/vbbw=wide 2006.145.16:28:03.08#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.16:28:03.08#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.16:28:03.08#ibcon#ireg 8 cls_cnt 0 2006.145.16:28:03.08#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.16:28:03.15#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.16:28:03.15#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.16:28:03.17#ibcon#[27=BW32\r\n] 2006.145.16:28:03.20#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.16:28:03.20#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.16:28:03.20#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.16:28:03.20#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.16:28:03.20$setupk4/ifdk4 2006.145.16:28:03.20$ifdk4/lo= 2006.145.16:28:03.20$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.16:28:03.20$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.16:28:03.20$ifdk4/patch= 2006.145.16:28:03.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.16:28:03.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.16:28:03.20$setupk4/!*+20s 2006.145.16:28:06.12#abcon#<5=/07 1.3 2.4 15.86 871020.0\r\n> 2006.145.16:28:06.14#abcon#{5=INTERFACE CLEAR} 2006.145.16:28:06.22#abcon#[5=S1D000X0/0*\r\n] 2006.145.16:28:16.31#abcon#<5=/07 1.3 2.4 15.86 871020.0\r\n> 2006.145.16:28:16.33#abcon#{5=INTERFACE CLEAR} 2006.145.16:28:16.39#abcon#[5=S1D000X0/0*\r\n] 2006.145.16:28:17.68$setupk4/"tpicd 2006.145.16:28:17.68$setupk4/echo=off 2006.145.16:28:17.68$setupk4/xlog=off 2006.145.16:28:17.68:!2006.145.16:34:38 2006.145.16:28:27.13#trakl#Source acquired 2006.145.16:28:28.13#flagr#flagr/antenna,acquired 2006.145.16:34:38.00:preob 2006.145.16:34:38.14/onsource/TRACKING 2006.145.16:34:38.14:!2006.145.16:34:48 2006.145.16:34:48.00:"tape 2006.145.16:34:48.00:"st=record 2006.145.16:34:48.00:data_valid=on 2006.145.16:34:48.00:midob 2006.145.16:34:49.14/onsource/TRACKING 2006.145.16:34:49.14/wx/15.91,1020.0,87 2006.145.16:34:49.23/cable/+6.5481E-03 2006.145.16:34:50.31/va/01,08,usb,yes,29,31 2006.145.16:34:50.31/va/02,07,usb,yes,31,32 2006.145.16:34:50.31/va/03,08,usb,yes,28,29 2006.145.16:34:50.31/va/04,07,usb,yes,32,34 2006.145.16:34:50.31/va/05,04,usb,yes,28,28 2006.145.16:34:50.31/va/06,04,usb,yes,31,31 2006.145.16:34:50.31/va/07,04,usb,yes,31,33 2006.145.16:34:50.31/va/08,04,usb,yes,27,32 2006.145.16:34:50.54/valo/01,524.99,yes,locked 2006.145.16:34:50.54/valo/02,534.99,yes,locked 2006.145.16:34:50.54/valo/03,564.99,yes,locked 2006.145.16:34:50.54/valo/04,624.99,yes,locked 2006.145.16:34:50.54/valo/05,734.99,yes,locked 2006.145.16:34:50.54/valo/06,814.99,yes,locked 2006.145.16:34:50.54/valo/07,864.99,yes,locked 2006.145.16:34:50.54/valo/08,884.99,yes,locked 2006.145.16:34:51.63/vb/01,03,usb,yes,36,33 2006.145.16:34:51.63/vb/02,04,usb,yes,31,31 2006.145.16:34:51.63/vb/03,04,usb,yes,28,31 2006.145.16:34:51.63/vb/04,04,usb,yes,33,32 2006.145.16:34:51.63/vb/05,04,usb,yes,25,28 2006.145.16:34:51.63/vb/06,04,usb,yes,30,26 2006.145.16:34:51.63/vb/07,04,usb,yes,29,29 2006.145.16:34:51.63/vb/08,04,usb,yes,27,30 2006.145.16:34:51.86/vblo/01,629.99,yes,locked 2006.145.16:34:51.86/vblo/02,634.99,yes,locked 2006.145.16:34:51.86/vblo/03,649.99,yes,locked 2006.145.16:34:51.86/vblo/04,679.99,yes,locked 2006.145.16:34:51.86/vblo/05,709.99,yes,locked 2006.145.16:34:51.86/vblo/06,719.99,yes,locked 2006.145.16:34:51.86/vblo/07,734.99,yes,locked 2006.145.16:34:51.86/vblo/08,744.99,yes,locked 2006.145.16:34:52.01/vabw/8 2006.145.16:34:52.16/vbbw/8 2006.145.16:34:52.25/xfe/off,on,15.0 2006.145.16:34:52.64/ifatt/23,28,28,28 2006.145.16:34:53.07/fmout-gps/S +4.2E-08 2006.145.16:34:53.11:!2006.145.16:36:18 2006.145.16:36:18.01:data_valid=off 2006.145.16:36:18.02:"et 2006.145.16:36:18.02:!+3s 2006.145.16:36:21.03:"tape 2006.145.16:36:21.03:postob 2006.145.16:36:21.16/cable/+6.5504E-03 2006.145.16:36:21.17/wx/15.94,1020.0,86 2006.145.16:36:21.23/fmout-gps/S +4.1E-08 2006.145.16:36:21.23:scan_name=145-1640,jd0605,40 2006.145.16:36:21.23:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.145.16:36:22.14#flagr#flagr/antenna,new-source 2006.145.16:36:22.15:checkk5 2006.145.16:36:22.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.16:36:23.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.16:36:23.44/chk_autoobs//k5ts3/ autoobs is running! 2006.145.16:36:23.87/chk_autoobs//k5ts4/ autoobs is running! 2006.145.16:36:24.30/chk_obsdata//k5ts1/T1451634??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.16:36:24.75/chk_obsdata//k5ts2/T1451634??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.16:36:25.20/chk_obsdata//k5ts3/T1451634??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.16:36:25.63/chk_obsdata//k5ts4/T1451634??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.16:36:26.38/k5log//k5ts1_log_newline 2006.145.16:36:27.12/k5log//k5ts2_log_newline 2006.145.16:36:27.87/k5log//k5ts3_log_newline 2006.145.16:36:28.62/k5log//k5ts4_log_newline 2006.145.16:36:28.64/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.16:36:28.64:setupk4=1 2006.145.16:36:28.64$setupk4/echo=on 2006.145.16:36:28.64$setupk4/pcalon 2006.145.16:36:28.64$pcalon/"no phase cal control is implemented here 2006.145.16:36:28.64$setupk4/"tpicd=stop 2006.145.16:36:28.64$setupk4/"rec=synch_on 2006.145.16:36:28.64$setupk4/"rec_mode=128 2006.145.16:36:28.64$setupk4/!* 2006.145.16:36:28.64$setupk4/recpk4 2006.145.16:36:28.64$recpk4/recpatch= 2006.145.16:36:28.65$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.16:36:28.65$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.16:36:28.65$setupk4/vck44 2006.145.16:36:28.65$vck44/valo=1,524.99 2006.145.16:36:28.65#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.16:36:28.65#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.16:36:28.65#ibcon#ireg 17 cls_cnt 0 2006.145.16:36:28.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.16:36:28.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.16:36:28.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.16:36:28.68#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.16:36:28.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.16:36:28.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.16:36:28.73#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.16:36:28.73#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.16:36:28.73$vck44/va=1,8 2006.145.16:36:28.73#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.16:36:28.73#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.16:36:28.73#ibcon#ireg 11 cls_cnt 2 2006.145.16:36:28.73#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.16:36:28.73#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.16:36:28.73#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.16:36:28.75#ibcon#[25=AT01-08\r\n] 2006.145.16:36:28.78#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.16:36:28.78#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.16:36:28.78#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.16:36:28.78#ibcon#ireg 7 cls_cnt 0 2006.145.16:36:28.78#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.16:36:28.90#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.16:36:28.90#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.16:36:28.92#ibcon#[25=USB\r\n] 2006.145.16:36:28.95#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.16:36:28.95#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.16:36:28.95#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.16:36:28.95#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.16:36:28.95$vck44/valo=2,534.99 2006.145.16:36:28.95#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.16:36:28.95#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.16:36:28.95#ibcon#ireg 17 cls_cnt 0 2006.145.16:36:28.95#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.16:36:28.95#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.16:36:28.95#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.16:36:28.98#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.16:36:29.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.16:36:29.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.16:36:29.02#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.16:36:29.02#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.16:36:29.02$vck44/va=2,7 2006.145.16:36:29.02#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.16:36:29.02#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.16:36:29.02#ibcon#ireg 11 cls_cnt 2 2006.145.16:36:29.02#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.16:36:29.07#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.16:36:29.07#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.16:36:29.09#ibcon#[25=AT02-07\r\n] 2006.145.16:36:29.12#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.16:36:29.12#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.16:36:29.12#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.16:36:29.12#ibcon#ireg 7 cls_cnt 0 2006.145.16:36:29.12#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.16:36:29.24#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.16:36:29.24#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.16:36:29.26#ibcon#[25=USB\r\n] 2006.145.16:36:29.29#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.16:36:29.29#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.16:36:29.29#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.16:36:29.29#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.16:36:29.29$vck44/valo=3,564.99 2006.145.16:36:29.29#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.16:36:29.29#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.16:36:29.29#ibcon#ireg 17 cls_cnt 0 2006.145.16:36:29.29#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:36:29.29#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:36:29.29#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:36:29.31#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.16:36:29.35#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:36:29.35#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:36:29.35#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.16:36:29.35#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.16:36:29.35$vck44/va=3,8 2006.145.16:36:29.35#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.16:36:29.35#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.16:36:29.35#ibcon#ireg 11 cls_cnt 2 2006.145.16:36:29.35#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.16:36:29.41#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.16:36:29.41#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.16:36:29.43#ibcon#[25=AT03-08\r\n] 2006.145.16:36:29.46#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.16:36:29.46#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.16:36:29.46#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.16:36:29.46#ibcon#ireg 7 cls_cnt 0 2006.145.16:36:29.46#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.16:36:29.58#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.16:36:29.58#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.16:36:29.60#ibcon#[25=USB\r\n] 2006.145.16:36:29.63#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.16:36:29.63#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.16:36:29.63#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.16:36:29.63#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.16:36:29.63$vck44/valo=4,624.99 2006.145.16:36:29.63#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.16:36:29.63#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.16:36:29.63#ibcon#ireg 17 cls_cnt 0 2006.145.16:36:29.63#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.16:36:29.63#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.16:36:29.63#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.16:36:29.65#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.16:36:29.69#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.16:36:29.69#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.16:36:29.69#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.16:36:29.69#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.16:36:29.69$vck44/va=4,7 2006.145.16:36:29.69#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.16:36:29.69#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.16:36:29.69#ibcon#ireg 11 cls_cnt 2 2006.145.16:36:29.69#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.16:36:29.75#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.16:36:29.75#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.16:36:29.77#ibcon#[25=AT04-07\r\n] 2006.145.16:36:29.80#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.16:36:29.80#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.16:36:29.80#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.16:36:29.80#ibcon#ireg 7 cls_cnt 0 2006.145.16:36:29.80#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.16:36:29.92#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.16:36:29.92#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.16:36:29.94#ibcon#[25=USB\r\n] 2006.145.16:36:29.97#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.16:36:29.97#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.16:36:29.97#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.16:36:29.97#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.16:36:29.97$vck44/valo=5,734.99 2006.145.16:36:29.97#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.16:36:29.97#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.16:36:29.97#ibcon#ireg 17 cls_cnt 0 2006.145.16:36:29.97#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.16:36:29.97#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.16:36:29.97#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.16:36:29.99#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.16:36:30.03#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.16:36:30.03#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.16:36:30.04#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.16:36:30.04#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.16:36:30.04$vck44/va=5,4 2006.145.16:36:30.04#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.16:36:30.04#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.16:36:30.04#ibcon#ireg 11 cls_cnt 2 2006.145.16:36:30.04#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.16:36:30.08#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.16:36:30.08#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.16:36:30.10#ibcon#[25=AT05-04\r\n] 2006.145.16:36:30.13#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.16:36:30.13#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.16:36:30.13#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.16:36:30.13#ibcon#ireg 7 cls_cnt 0 2006.145.16:36:30.13#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.16:36:30.25#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.16:36:30.25#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.16:36:30.27#ibcon#[25=USB\r\n] 2006.145.16:36:30.30#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.16:36:30.30#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.16:36:30.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.16:36:30.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.16:36:30.30$vck44/valo=6,814.99 2006.145.16:36:30.30#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.16:36:30.30#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.16:36:30.30#ibcon#ireg 17 cls_cnt 0 2006.145.16:36:30.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.16:36:30.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.16:36:30.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.16:36:30.33#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.16:36:30.37#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.16:36:30.37#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.16:36:30.37#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.16:36:30.37#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.16:36:30.37$vck44/va=6,4 2006.145.16:36:30.37#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.16:36:30.37#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.16:36:30.37#ibcon#ireg 11 cls_cnt 2 2006.145.16:36:30.37#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.16:36:30.42#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.16:36:30.42#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.16:36:30.44#ibcon#[25=AT06-04\r\n] 2006.145.16:36:30.47#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.16:36:30.47#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.16:36:30.47#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.16:36:30.47#ibcon#ireg 7 cls_cnt 0 2006.145.16:36:30.47#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.16:36:30.59#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.16:36:30.59#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.16:36:30.61#ibcon#[25=USB\r\n] 2006.145.16:36:30.64#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.16:36:30.64#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.16:36:30.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.16:36:30.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.16:36:30.64$vck44/valo=7,864.99 2006.145.16:36:30.64#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.16:36:30.64#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.16:36:30.64#ibcon#ireg 17 cls_cnt 0 2006.145.16:36:30.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.16:36:30.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.16:36:30.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.16:36:30.66#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.16:36:30.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.16:36:30.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.16:36:30.70#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.16:36:30.70#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.16:36:30.70$vck44/va=7,4 2006.145.16:36:30.70#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.16:36:30.70#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.16:36:30.70#ibcon#ireg 11 cls_cnt 2 2006.145.16:36:30.70#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.16:36:30.76#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.16:36:30.76#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.16:36:30.78#ibcon#[25=AT07-04\r\n] 2006.145.16:36:30.81#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.16:36:30.81#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.16:36:30.81#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.16:36:30.81#ibcon#ireg 7 cls_cnt 0 2006.145.16:36:30.81#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.16:36:30.93#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.16:36:30.93#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.16:36:30.95#ibcon#[25=USB\r\n] 2006.145.16:36:30.98#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.16:36:30.98#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.16:36:30.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.16:36:30.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.16:36:30.98$vck44/valo=8,884.99 2006.145.16:36:30.98#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.16:36:30.98#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.16:36:30.98#ibcon#ireg 17 cls_cnt 0 2006.145.16:36:30.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.16:36:30.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.16:36:30.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.16:36:31.00#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.16:36:31.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.16:36:31.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.16:36:31.04#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.16:36:31.04#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.16:36:31.04$vck44/va=8,4 2006.145.16:36:31.04#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.16:36:31.04#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.16:36:31.04#ibcon#ireg 11 cls_cnt 2 2006.145.16:36:31.04#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.16:36:31.10#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.16:36:31.10#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.16:36:31.12#ibcon#[25=AT08-04\r\n] 2006.145.16:36:31.15#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.16:36:31.15#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.16:36:31.15#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.16:36:31.15#ibcon#ireg 7 cls_cnt 0 2006.145.16:36:31.15#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.16:36:31.27#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.16:36:31.27#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.16:36:31.29#ibcon#[25=USB\r\n] 2006.145.16:36:31.32#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.16:36:31.32#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.16:36:31.32#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.16:36:31.32#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.16:36:31.32$vck44/vblo=1,629.99 2006.145.16:36:31.32#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.16:36:31.32#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.16:36:31.32#ibcon#ireg 17 cls_cnt 0 2006.145.16:36:31.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.16:36:31.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.16:36:31.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.16:36:31.34#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.16:36:31.38#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.16:36:31.38#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.16:36:31.38#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.16:36:31.38#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.16:36:31.38$vck44/vb=1,3 2006.145.16:36:31.38#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.16:36:31.38#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.16:36:31.38#ibcon#ireg 11 cls_cnt 2 2006.145.16:36:31.38#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.16:36:31.38#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.16:36:31.38#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.16:36:31.40#ibcon#[27=AT01-03\r\n] 2006.145.16:36:31.43#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.16:36:31.43#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.16:36:31.43#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.16:36:31.43#ibcon#ireg 7 cls_cnt 0 2006.145.16:36:31.43#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.16:36:31.55#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.16:36:31.55#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.16:36:31.57#ibcon#[27=USB\r\n] 2006.145.16:36:31.60#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.16:36:31.60#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.16:36:31.60#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.16:36:31.60#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.16:36:31.60$vck44/vblo=2,634.99 2006.145.16:36:31.60#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.16:36:31.60#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.16:36:31.60#ibcon#ireg 17 cls_cnt 0 2006.145.16:36:31.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.16:36:31.60#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.16:36:31.60#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.16:36:31.62#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.16:36:31.66#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.16:36:31.66#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.16:36:31.66#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.16:36:31.66#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.16:36:31.66$vck44/vb=2,4 2006.145.16:36:31.66#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.16:36:31.66#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.16:36:31.66#ibcon#ireg 11 cls_cnt 2 2006.145.16:36:31.66#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.16:36:31.72#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.16:36:31.72#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.16:36:31.74#ibcon#[27=AT02-04\r\n] 2006.145.16:36:31.77#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.16:36:31.77#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.16:36:31.77#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.16:36:31.77#ibcon#ireg 7 cls_cnt 0 2006.145.16:36:31.77#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.16:36:31.89#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.16:36:31.89#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.16:36:31.91#ibcon#[27=USB\r\n] 2006.145.16:36:31.94#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.16:36:31.94#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.16:36:31.94#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.16:36:31.94#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.16:36:31.94$vck44/vblo=3,649.99 2006.145.16:36:31.94#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.16:36:31.94#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.16:36:31.94#ibcon#ireg 17 cls_cnt 0 2006.145.16:36:31.94#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.16:36:31.94#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.16:36:31.94#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.16:36:31.96#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.16:36:32.00#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.16:36:32.00#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.16:36:32.00#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.16:36:32.00#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.16:36:32.00$vck44/vb=3,4 2006.145.16:36:32.00#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.16:36:32.00#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.16:36:32.00#ibcon#ireg 11 cls_cnt 2 2006.145.16:36:32.00#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.16:36:32.06#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.16:36:32.06#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.16:36:32.08#ibcon#[27=AT03-04\r\n] 2006.145.16:36:32.11#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.16:36:32.11#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.16:36:32.11#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.16:36:32.11#ibcon#ireg 7 cls_cnt 0 2006.145.16:36:32.11#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.16:36:32.23#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.16:36:32.23#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.16:36:32.25#ibcon#[27=USB\r\n] 2006.145.16:36:32.28#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.16:36:32.28#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.16:36:32.28#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.16:36:32.28#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.16:36:32.28$vck44/vblo=4,679.99 2006.145.16:36:32.28#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.16:36:32.28#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.16:36:32.28#ibcon#ireg 17 cls_cnt 0 2006.145.16:36:32.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:36:32.28#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:36:32.28#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:36:32.30#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.16:36:32.34#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:36:32.34#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:36:32.34#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.16:36:32.34#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.16:36:32.34$vck44/vb=4,4 2006.145.16:36:32.34#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.16:36:32.34#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.16:36:32.34#ibcon#ireg 11 cls_cnt 2 2006.145.16:36:32.34#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.16:36:32.40#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.16:36:32.40#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.16:36:32.42#ibcon#[27=AT04-04\r\n] 2006.145.16:36:32.45#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.16:36:32.45#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.16:36:32.45#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.16:36:32.45#ibcon#ireg 7 cls_cnt 0 2006.145.16:36:32.45#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.16:36:32.57#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.16:36:32.57#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.16:36:32.59#ibcon#[27=USB\r\n] 2006.145.16:36:32.62#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.16:36:32.62#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.16:36:32.62#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.16:36:32.62#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.16:36:32.62$vck44/vblo=5,709.99 2006.145.16:36:32.62#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.16:36:32.62#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.16:36:32.62#ibcon#ireg 17 cls_cnt 0 2006.145.16:36:32.62#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.16:36:32.62#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.16:36:32.62#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.16:36:32.64#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.16:36:32.68#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.16:36:32.68#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.16:36:32.68#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.16:36:32.68#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.16:36:32.68$vck44/vb=5,4 2006.145.16:36:32.68#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.16:36:32.68#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.16:36:32.68#ibcon#ireg 11 cls_cnt 2 2006.145.16:36:32.68#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.16:36:32.74#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.16:36:32.74#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.16:36:32.76#ibcon#[27=AT05-04\r\n] 2006.145.16:36:32.79#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.16:36:32.79#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.16:36:32.79#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.16:36:32.79#ibcon#ireg 7 cls_cnt 0 2006.145.16:36:32.79#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.16:36:32.91#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.16:36:32.91#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.16:36:32.93#ibcon#[27=USB\r\n] 2006.145.16:36:32.96#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.16:36:32.96#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.16:36:32.96#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.16:36:32.96#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.16:36:32.96$vck44/vblo=6,719.99 2006.145.16:36:32.96#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.16:36:32.96#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.16:36:32.96#ibcon#ireg 17 cls_cnt 0 2006.145.16:36:32.96#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.16:36:32.96#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.16:36:32.96#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.16:36:32.98#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.16:36:33.02#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.16:36:33.02#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.16:36:33.02#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.16:36:33.02#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.16:36:33.02$vck44/vb=6,4 2006.145.16:36:33.02#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.16:36:33.02#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.16:36:33.02#ibcon#ireg 11 cls_cnt 2 2006.145.16:36:33.02#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.16:36:33.08#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.16:36:33.08#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.16:36:33.10#ibcon#[27=AT06-04\r\n] 2006.145.16:36:33.13#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.16:36:33.13#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.16:36:33.13#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.16:36:33.13#ibcon#ireg 7 cls_cnt 0 2006.145.16:36:33.13#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.16:36:33.25#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.16:36:33.25#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.16:36:33.27#ibcon#[27=USB\r\n] 2006.145.16:36:33.30#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.16:36:33.30#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.16:36:33.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.16:36:33.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.16:36:33.30$vck44/vblo=7,734.99 2006.145.16:36:33.30#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.16:36:33.30#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.16:36:33.30#ibcon#ireg 17 cls_cnt 0 2006.145.16:36:33.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.16:36:33.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.16:36:33.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.16:36:33.32#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.16:36:33.36#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.16:36:33.36#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.16:36:33.36#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.16:36:33.36#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.16:36:33.36$vck44/vb=7,4 2006.145.16:36:33.36#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.16:36:33.36#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.16:36:33.36#ibcon#ireg 11 cls_cnt 2 2006.145.16:36:33.36#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.16:36:33.42#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.16:36:33.42#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.16:36:33.44#ibcon#[27=AT07-04\r\n] 2006.145.16:36:33.47#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.16:36:33.47#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.16:36:33.47#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.16:36:33.47#ibcon#ireg 7 cls_cnt 0 2006.145.16:36:33.47#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.16:36:33.59#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.16:36:33.59#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.16:36:33.61#ibcon#[27=USB\r\n] 2006.145.16:36:33.64#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.16:36:33.64#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.16:36:33.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.16:36:33.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.16:36:33.64$vck44/vblo=8,744.99 2006.145.16:36:33.64#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.16:36:33.64#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.16:36:33.64#ibcon#ireg 17 cls_cnt 0 2006.145.16:36:33.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.16:36:33.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.16:36:33.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.16:36:33.66#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.16:36:33.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.16:36:33.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.16:36:33.70#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.16:36:33.70#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.16:36:33.70$vck44/vb=8,4 2006.145.16:36:33.70#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.16:36:33.70#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.16:36:33.70#ibcon#ireg 11 cls_cnt 2 2006.145.16:36:33.70#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.16:36:33.76#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.16:36:33.76#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.16:36:33.78#ibcon#[27=AT08-04\r\n] 2006.145.16:36:33.81#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.16:36:33.81#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.16:36:33.81#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.16:36:33.81#ibcon#ireg 7 cls_cnt 0 2006.145.16:36:33.81#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.16:36:33.93#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.16:36:33.93#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.16:36:33.95#ibcon#[27=USB\r\n] 2006.145.16:36:33.98#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.16:36:33.98#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.16:36:33.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.16:36:33.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.16:36:33.98$vck44/vabw=wide 2006.145.16:36:33.98#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.16:36:33.98#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.16:36:33.98#ibcon#ireg 8 cls_cnt 0 2006.145.16:36:33.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.16:36:33.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.16:36:33.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.16:36:34.00#ibcon#[25=BW32\r\n] 2006.145.16:36:34.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.16:36:34.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.16:36:34.03#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.16:36:34.03#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.16:36:34.03$vck44/vbbw=wide 2006.145.16:36:34.03#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.16:36:34.03#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.16:36:34.03#ibcon#ireg 8 cls_cnt 0 2006.145.16:36:34.03#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.16:36:34.10#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.16:36:34.10#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.16:36:34.12#ibcon#[27=BW32\r\n] 2006.145.16:36:34.15#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.16:36:34.15#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.16:36:34.15#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.16:36:34.15#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.16:36:34.15$setupk4/ifdk4 2006.145.16:36:34.15$ifdk4/lo= 2006.145.16:36:34.15$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.16:36:34.15$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.16:36:34.15$ifdk4/patch= 2006.145.16:36:34.15$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.16:36:34.15$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.16:36:34.15$setupk4/!*+20s 2006.145.16:36:34.74#abcon#<5=/07 1.3 2.6 15.94 861019.9\r\n> 2006.145.16:36:34.76#abcon#{5=INTERFACE CLEAR} 2006.145.16:36:34.82#abcon#[5=S1D000X0/0*\r\n] 2006.145.16:36:44.91#abcon#<5=/07 1.3 2.6 15.94 861020.0\r\n> 2006.145.16:36:44.93#abcon#{5=INTERFACE CLEAR} 2006.145.16:36:44.99#abcon#[5=S1D000X0/0*\r\n] 2006.145.16:36:48.65$setupk4/"tpicd 2006.145.16:36:48.65$setupk4/echo=off 2006.145.16:36:48.65$setupk4/xlog=off 2006.145.16:36:48.65:!2006.145.16:40:28 2006.145.16:36:57.13#trakl#Source acquired 2006.145.16:36:57.13#flagr#flagr/antenna,acquired 2006.145.16:40:28.00:preob 2006.145.16:40:28.14/onsource/TRACKING 2006.145.16:40:28.14:!2006.145.16:40:38 2006.145.16:40:38.00:"tape 2006.145.16:40:38.00:"st=record 2006.145.16:40:38.00:data_valid=on 2006.145.16:40:38.00:midob 2006.145.16:40:39.14/onsource/TRACKING 2006.145.16:40:39.14/wx/15.99,1019.9,86 2006.145.16:40:39.24/cable/+6.5518E-03 2006.145.16:40:40.33/va/01,08,usb,yes,34,36 2006.145.16:40:40.33/va/02,07,usb,yes,36,37 2006.145.16:40:40.33/va/03,08,usb,yes,33,35 2006.145.16:40:40.33/va/04,07,usb,yes,38,40 2006.145.16:40:40.33/va/05,04,usb,yes,33,34 2006.145.16:40:40.33/va/06,04,usb,yes,37,37 2006.145.16:40:40.33/va/07,04,usb,yes,37,39 2006.145.16:40:40.33/va/08,04,usb,yes,32,38 2006.145.16:40:40.56/valo/01,524.99,yes,locked 2006.145.16:40:40.56/valo/02,534.99,yes,locked 2006.145.16:40:40.56/valo/03,564.99,yes,locked 2006.145.16:40:40.56/valo/04,624.99,yes,locked 2006.145.16:40:40.56/valo/05,734.99,yes,locked 2006.145.16:40:40.56/valo/06,814.99,yes,locked 2006.145.16:40:40.56/valo/07,864.99,yes,locked 2006.145.16:40:40.56/valo/08,884.99,yes,locked 2006.145.16:40:41.65/vb/01,03,usb,yes,40,37 2006.145.16:40:41.65/vb/02,04,usb,yes,35,34 2006.145.16:40:41.65/vb/03,04,usb,yes,31,35 2006.145.16:40:41.65/vb/04,04,usb,yes,36,35 2006.145.16:40:41.65/vb/05,04,usb,yes,28,31 2006.145.16:40:41.65/vb/06,04,usb,yes,33,29 2006.145.16:40:41.65/vb/07,04,usb,yes,33,32 2006.145.16:40:41.65/vb/08,04,usb,yes,30,34 2006.145.16:40:41.89/vblo/01,629.99,yes,locked 2006.145.16:40:41.89/vblo/02,634.99,yes,locked 2006.145.16:40:41.89/vblo/03,649.99,yes,locked 2006.145.16:40:41.89/vblo/04,679.99,yes,locked 2006.145.16:40:41.89/vblo/05,709.99,yes,locked 2006.145.16:40:41.89/vblo/06,719.99,yes,locked 2006.145.16:40:41.89/vblo/07,734.99,yes,locked 2006.145.16:40:41.89/vblo/08,744.99,yes,locked 2006.145.16:40:42.04/vabw/8 2006.145.16:40:42.19/vbbw/8 2006.145.16:40:42.28/xfe/off,on,14.5 2006.145.16:40:42.65/ifatt/23,28,28,28 2006.145.16:40:43.07/fmout-gps/S +4.2E-08 2006.145.16:40:43.11:!2006.145.16:41:18 2006.145.16:41:18.01:data_valid=off 2006.145.16:41:18.01:"et 2006.145.16:41:18.02:!+3s 2006.145.16:41:21.03:"tape 2006.145.16:41:21.03:postob 2006.145.16:41:21.24/cable/+6.5498E-03 2006.145.16:41:21.24/wx/16.00,1019.9,86 2006.145.16:41:21.33/fmout-gps/S +4.3E-08 2006.145.16:41:21.33:scan_name=145-1645,jd0605,410 2006.145.16:41:21.34:source=1418+546,141946.60,542314.8,2000.0,cw 2006.145.16:41:23.14#flagr#flagr/antenna,new-source 2006.145.16:41:23.14:checkk5 2006.145.16:41:23.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.16:41:24.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.16:41:24.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.16:41:24.88/chk_autoobs//k5ts4/ autoobs is running! 2006.145.16:41:25.32/chk_obsdata//k5ts1/T1451640??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.16:41:25.75/chk_obsdata//k5ts2/T1451640??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.16:41:26.18/chk_obsdata//k5ts3/T1451640??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.16:41:26.62/chk_obsdata//k5ts4/T1451640??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.16:41:27.39/k5log//k5ts1_log_newline 2006.145.16:41:28.14/k5log//k5ts2_log_newline 2006.145.16:41:28.89/k5log//k5ts3_log_newline 2006.145.16:41:29.64/k5log//k5ts4_log_newline 2006.145.16:41:29.66/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.16:41:29.66:setupk4=1 2006.145.16:41:29.66$setupk4/echo=on 2006.145.16:41:29.66$setupk4/pcalon 2006.145.16:41:29.66$pcalon/"no phase cal control is implemented here 2006.145.16:41:29.66$setupk4/"tpicd=stop 2006.145.16:41:29.66$setupk4/"rec=synch_on 2006.145.16:41:29.66$setupk4/"rec_mode=128 2006.145.16:41:29.66$setupk4/!* 2006.145.16:41:29.66$setupk4/recpk4 2006.145.16:41:29.66$recpk4/recpatch= 2006.145.16:41:29.66$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.16:41:29.66$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.16:41:29.66$setupk4/vck44 2006.145.16:41:29.66$vck44/valo=1,524.99 2006.145.16:41:29.66#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.16:41:29.66#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.16:41:29.66#ibcon#ireg 17 cls_cnt 0 2006.145.16:41:29.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:41:29.66#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:41:29.66#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:41:29.68#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.16:41:29.71#abcon#{5=INTERFACE CLEAR} 2006.145.16:41:29.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:41:29.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:41:29.73#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.16:41:29.73#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.16:41:29.73$vck44/va=1,8 2006.145.16:41:29.73#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.16:41:29.73#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.16:41:29.73#ibcon#ireg 11 cls_cnt 2 2006.145.16:41:29.73#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.16:41:29.73#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.16:41:29.73#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.16:41:29.75#ibcon#[25=AT01-08\r\n] 2006.145.16:41:29.76#abcon#[5=S1D000X0/0*\r\n] 2006.145.16:41:29.78#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.16:41:29.78#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.16:41:29.78#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.16:41:29.78#ibcon#ireg 7 cls_cnt 0 2006.145.16:41:29.78#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.16:41:29.90#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.16:41:29.90#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.16:41:29.92#ibcon#[25=USB\r\n] 2006.145.16:41:29.95#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.16:41:29.95#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.16:41:29.95#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.16:41:29.95#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.16:41:29.95$vck44/valo=2,534.99 2006.145.16:41:29.95#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.16:41:29.95#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.16:41:29.95#ibcon#ireg 17 cls_cnt 0 2006.145.16:41:29.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.16:41:29.95#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.16:41:29.95#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.16:41:29.98#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.16:41:30.02#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.16:41:30.02#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.16:41:30.02#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.16:41:30.02#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.16:41:30.02$vck44/va=2,7 2006.145.16:41:30.02#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.16:41:30.02#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.16:41:30.02#ibcon#ireg 11 cls_cnt 2 2006.145.16:41:30.02#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.16:41:30.07#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.16:41:30.07#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.16:41:30.09#ibcon#[25=AT02-07\r\n] 2006.145.16:41:30.12#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.16:41:30.12#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.16:41:30.12#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.16:41:30.12#ibcon#ireg 7 cls_cnt 0 2006.145.16:41:30.12#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.16:41:30.24#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.16:41:30.24#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.16:41:30.26#ibcon#[25=USB\r\n] 2006.145.16:41:30.29#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.16:41:30.29#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.16:41:30.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.16:41:30.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.16:41:30.29$vck44/valo=3,564.99 2006.145.16:41:30.29#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.16:41:30.29#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.16:41:30.29#ibcon#ireg 17 cls_cnt 0 2006.145.16:41:30.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.16:41:30.29#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.16:41:30.29#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.16:41:30.31#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.16:41:30.35#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.16:41:30.35#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.16:41:30.35#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.16:41:30.35#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.16:41:30.35$vck44/va=3,8 2006.145.16:41:30.35#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.16:41:30.35#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.16:41:30.35#ibcon#ireg 11 cls_cnt 2 2006.145.16:41:30.35#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.16:41:30.41#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.16:41:30.41#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.16:41:30.43#ibcon#[25=AT03-08\r\n] 2006.145.16:41:30.46#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.16:41:30.46#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.16:41:30.46#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.16:41:30.46#ibcon#ireg 7 cls_cnt 0 2006.145.16:41:30.46#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.16:41:30.58#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.16:41:30.58#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.16:41:30.60#ibcon#[25=USB\r\n] 2006.145.16:41:30.63#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.16:41:30.63#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.16:41:30.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.16:41:30.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.16:41:30.63$vck44/valo=4,624.99 2006.145.16:41:30.63#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.16:41:30.63#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.16:41:30.63#ibcon#ireg 17 cls_cnt 0 2006.145.16:41:30.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.16:41:30.63#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.16:41:30.63#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.16:41:30.65#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.16:41:30.69#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.16:41:30.69#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.16:41:30.69#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.16:41:30.69#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.16:41:30.69$vck44/va=4,7 2006.145.16:41:30.69#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.16:41:30.69#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.16:41:30.69#ibcon#ireg 11 cls_cnt 2 2006.145.16:41:30.69#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.16:41:30.75#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.16:41:30.75#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.16:41:30.77#ibcon#[25=AT04-07\r\n] 2006.145.16:41:30.80#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.16:41:30.80#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.16:41:30.80#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.16:41:30.80#ibcon#ireg 7 cls_cnt 0 2006.145.16:41:30.80#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.16:41:30.92#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.16:41:30.92#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.16:41:30.94#ibcon#[25=USB\r\n] 2006.145.16:41:30.97#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.16:41:30.97#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.16:41:30.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.16:41:30.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.16:41:30.97$vck44/valo=5,734.99 2006.145.16:41:30.97#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.16:41:30.97#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.16:41:30.97#ibcon#ireg 17 cls_cnt 0 2006.145.16:41:30.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.16:41:30.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.16:41:30.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.16:41:30.99#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.16:41:31.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.16:41:31.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.16:41:31.03#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.16:41:31.03#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.16:41:31.03$vck44/va=5,4 2006.145.16:41:31.03#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.16:41:31.03#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.16:41:31.03#ibcon#ireg 11 cls_cnt 2 2006.145.16:41:31.03#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.16:41:31.09#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.16:41:31.09#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.16:41:31.11#ibcon#[25=AT05-04\r\n] 2006.145.16:41:31.14#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.16:41:31.14#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.16:41:31.14#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.16:41:31.14#ibcon#ireg 7 cls_cnt 0 2006.145.16:41:31.14#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.16:41:31.26#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.16:41:31.26#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.16:41:31.28#ibcon#[25=USB\r\n] 2006.145.16:41:31.31#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.16:41:31.31#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.16:41:31.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.16:41:31.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.16:41:31.31$vck44/valo=6,814.99 2006.145.16:41:31.31#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.16:41:31.31#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.16:41:31.31#ibcon#ireg 17 cls_cnt 0 2006.145.16:41:31.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.16:41:31.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.16:41:31.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.16:41:31.33#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.16:41:31.37#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.16:41:31.37#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.16:41:31.37#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.16:41:31.37#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.16:41:31.37$vck44/va=6,4 2006.145.16:41:31.37#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.16:41:31.37#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.16:41:31.37#ibcon#ireg 11 cls_cnt 2 2006.145.16:41:31.37#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.16:41:31.43#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.16:41:31.43#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.16:41:31.45#ibcon#[25=AT06-04\r\n] 2006.145.16:41:31.48#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.16:41:31.48#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.16:41:31.48#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.16:41:31.48#ibcon#ireg 7 cls_cnt 0 2006.145.16:41:31.48#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.16:41:31.60#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.16:41:31.60#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.16:41:31.62#ibcon#[25=USB\r\n] 2006.145.16:41:31.65#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.16:41:31.65#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.16:41:31.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.16:41:31.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.16:41:31.65$vck44/valo=7,864.99 2006.145.16:41:31.65#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.16:41:31.65#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.16:41:31.65#ibcon#ireg 17 cls_cnt 0 2006.145.16:41:31.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.16:41:31.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.16:41:31.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.16:41:31.67#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.16:41:31.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.16:41:31.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.16:41:31.71#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.16:41:31.71#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.16:41:31.71$vck44/va=7,4 2006.145.16:41:31.71#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.16:41:31.71#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.16:41:31.71#ibcon#ireg 11 cls_cnt 2 2006.145.16:41:31.71#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.16:41:31.77#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.16:41:31.77#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.16:41:31.79#ibcon#[25=AT07-04\r\n] 2006.145.16:41:31.82#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.16:41:31.82#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.16:41:31.82#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.16:41:31.82#ibcon#ireg 7 cls_cnt 0 2006.145.16:41:31.82#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.16:41:31.94#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.16:41:31.94#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.16:41:31.96#ibcon#[25=USB\r\n] 2006.145.16:41:31.99#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.16:41:31.99#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.16:41:31.99#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.16:41:31.99#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.16:41:31.99$vck44/valo=8,884.99 2006.145.16:41:31.99#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.16:41:31.99#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.16:41:31.99#ibcon#ireg 17 cls_cnt 0 2006.145.16:41:31.99#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.16:41:31.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.16:41:31.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.16:41:32.01#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.16:41:32.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.16:41:32.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.16:41:32.05#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.16:41:32.05#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.16:41:32.05$vck44/va=8,4 2006.145.16:41:32.05#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.16:41:32.05#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.16:41:32.05#ibcon#ireg 11 cls_cnt 2 2006.145.16:41:32.05#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.16:41:32.11#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.16:41:32.11#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.16:41:32.13#ibcon#[25=AT08-04\r\n] 2006.145.16:41:32.16#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.16:41:32.16#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.16:41:32.16#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.16:41:32.16#ibcon#ireg 7 cls_cnt 0 2006.145.16:41:32.16#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.16:41:32.28#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.16:41:32.28#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.16:41:32.30#ibcon#[25=USB\r\n] 2006.145.16:41:32.33#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.16:41:32.33#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.16:41:32.33#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.16:41:32.33#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.16:41:32.33$vck44/vblo=1,629.99 2006.145.16:41:32.33#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.16:41:32.33#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.16:41:32.33#ibcon#ireg 17 cls_cnt 0 2006.145.16:41:32.33#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.16:41:32.33#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.16:41:32.33#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.16:41:32.35#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.16:41:32.39#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.16:41:32.39#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.16:41:32.39#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.16:41:32.39#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.16:41:32.39$vck44/vb=1,3 2006.145.16:41:32.39#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.16:41:32.39#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.16:41:32.39#ibcon#ireg 11 cls_cnt 2 2006.145.16:41:32.39#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.16:41:32.39#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.16:41:32.39#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.16:41:32.41#ibcon#[27=AT01-03\r\n] 2006.145.16:41:32.44#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.16:41:32.44#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.16:41:32.44#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.16:41:32.44#ibcon#ireg 7 cls_cnt 0 2006.145.16:41:32.44#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.16:41:32.56#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.16:41:32.56#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.16:41:32.58#ibcon#[27=USB\r\n] 2006.145.16:41:32.61#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.16:41:32.61#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.16:41:32.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.16:41:32.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.16:41:32.61$vck44/vblo=2,634.99 2006.145.16:41:32.61#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.16:41:32.61#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.16:41:32.61#ibcon#ireg 17 cls_cnt 0 2006.145.16:41:32.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.16:41:32.61#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.16:41:32.61#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.16:41:32.63#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.16:41:32.67#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.16:41:32.67#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.16:41:32.67#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.16:41:32.67#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.16:41:32.67$vck44/vb=2,4 2006.145.16:41:32.67#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.16:41:32.67#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.16:41:32.67#ibcon#ireg 11 cls_cnt 2 2006.145.16:41:32.67#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.16:41:32.73#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.16:41:32.73#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.16:41:32.75#ibcon#[27=AT02-04\r\n] 2006.145.16:41:32.78#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.16:41:32.78#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.16:41:32.78#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.16:41:32.78#ibcon#ireg 7 cls_cnt 0 2006.145.16:41:32.78#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.16:41:32.90#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.16:41:32.90#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.16:41:32.92#ibcon#[27=USB\r\n] 2006.145.16:41:32.95#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.16:41:32.95#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.16:41:32.95#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.16:41:32.95#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.16:41:32.95$vck44/vblo=3,649.99 2006.145.16:41:32.95#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.16:41:32.95#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.16:41:32.95#ibcon#ireg 17 cls_cnt 0 2006.145.16:41:32.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.16:41:32.95#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.16:41:32.95#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.16:41:32.97#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.16:41:33.01#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.16:41:33.01#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.16:41:33.01#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.16:41:33.01#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.16:41:33.01$vck44/vb=3,4 2006.145.16:41:33.01#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.16:41:33.01#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.16:41:33.01#ibcon#ireg 11 cls_cnt 2 2006.145.16:41:33.01#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.16:41:33.07#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.16:41:33.07#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.16:41:33.09#ibcon#[27=AT03-04\r\n] 2006.145.16:41:33.12#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.16:41:33.12#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.16:41:33.12#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.16:41:33.12#ibcon#ireg 7 cls_cnt 0 2006.145.16:41:33.12#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.16:41:33.24#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.16:41:33.24#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.16:41:33.26#ibcon#[27=USB\r\n] 2006.145.16:41:33.29#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.16:41:33.29#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.16:41:33.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.16:41:33.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.16:41:33.29$vck44/vblo=4,679.99 2006.145.16:41:33.29#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.16:41:33.29#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.16:41:33.29#ibcon#ireg 17 cls_cnt 0 2006.145.16:41:33.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.16:41:33.29#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.16:41:33.29#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.16:41:33.31#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.16:41:33.35#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.16:41:33.35#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.16:41:33.35#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.16:41:33.35#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.16:41:33.35$vck44/vb=4,4 2006.145.16:41:33.35#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.16:41:33.35#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.16:41:33.35#ibcon#ireg 11 cls_cnt 2 2006.145.16:41:33.35#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.16:41:33.41#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.16:41:33.41#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.16:41:33.43#ibcon#[27=AT04-04\r\n] 2006.145.16:41:33.46#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.16:41:33.46#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.16:41:33.46#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.16:41:33.46#ibcon#ireg 7 cls_cnt 0 2006.145.16:41:33.46#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.16:41:33.58#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.16:41:33.58#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.16:41:33.60#ibcon#[27=USB\r\n] 2006.145.16:41:33.63#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.16:41:33.63#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.16:41:33.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.16:41:33.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.16:41:33.63$vck44/vblo=5,709.99 2006.145.16:41:33.63#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.16:41:33.63#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.16:41:33.63#ibcon#ireg 17 cls_cnt 0 2006.145.16:41:33.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.16:41:33.63#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.16:41:33.63#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.16:41:33.65#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.16:41:33.69#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.16:41:33.69#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.16:41:33.69#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.16:41:33.69#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.16:41:33.69$vck44/vb=5,4 2006.145.16:41:33.69#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.16:41:33.69#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.16:41:33.69#ibcon#ireg 11 cls_cnt 2 2006.145.16:41:33.69#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.16:41:33.75#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.16:41:33.75#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.16:41:33.77#ibcon#[27=AT05-04\r\n] 2006.145.16:41:33.80#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.16:41:33.80#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.16:41:33.80#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.16:41:33.80#ibcon#ireg 7 cls_cnt 0 2006.145.16:41:33.80#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.16:41:33.92#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.16:41:33.92#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.16:41:33.94#ibcon#[27=USB\r\n] 2006.145.16:41:33.97#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.16:41:33.97#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.16:41:33.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.16:41:33.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.16:41:33.97$vck44/vblo=6,719.99 2006.145.16:41:33.97#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.16:41:33.97#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.16:41:33.97#ibcon#ireg 17 cls_cnt 0 2006.145.16:41:33.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.16:41:33.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.16:41:33.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.16:41:33.99#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.16:41:34.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.16:41:34.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.16:41:34.03#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.16:41:34.03#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.16:41:34.03$vck44/vb=6,4 2006.145.16:41:34.03#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.16:41:34.03#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.16:41:34.03#ibcon#ireg 11 cls_cnt 2 2006.145.16:41:34.03#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.16:41:34.09#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.16:41:34.09#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.16:41:34.11#ibcon#[27=AT06-04\r\n] 2006.145.16:41:34.14#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.16:41:34.14#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.16:41:34.14#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.16:41:34.14#ibcon#ireg 7 cls_cnt 0 2006.145.16:41:34.14#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.16:41:34.26#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.16:41:34.26#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.16:41:34.28#ibcon#[27=USB\r\n] 2006.145.16:41:34.31#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.16:41:34.31#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.16:41:34.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.16:41:34.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.16:41:34.31$vck44/vblo=7,734.99 2006.145.16:41:34.31#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.16:41:34.31#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.16:41:34.31#ibcon#ireg 17 cls_cnt 0 2006.145.16:41:34.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.16:41:34.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.16:41:34.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.16:41:34.33#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.16:41:34.37#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.16:41:34.37#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.16:41:34.37#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.16:41:34.37#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.16:41:34.37$vck44/vb=7,4 2006.145.16:41:34.37#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.16:41:34.37#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.16:41:34.37#ibcon#ireg 11 cls_cnt 2 2006.145.16:41:34.37#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.16:41:34.43#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.16:41:34.43#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.16:41:34.45#ibcon#[27=AT07-04\r\n] 2006.145.16:41:34.48#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.16:41:34.48#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.16:41:34.48#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.16:41:34.48#ibcon#ireg 7 cls_cnt 0 2006.145.16:41:34.48#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.16:41:34.60#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.16:41:34.60#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.16:41:34.62#ibcon#[27=USB\r\n] 2006.145.16:41:34.65#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.16:41:34.65#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.16:41:34.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.16:41:34.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.16:41:34.65$vck44/vblo=8,744.99 2006.145.16:41:34.65#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.16:41:34.65#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.16:41:34.65#ibcon#ireg 17 cls_cnt 0 2006.145.16:41:34.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.16:41:34.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.16:41:34.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.16:41:34.67#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.16:41:34.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.16:41:34.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.16:41:34.71#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.16:41:34.71#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.16:41:34.71$vck44/vb=8,4 2006.145.16:41:34.71#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.16:41:34.71#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.16:41:34.71#ibcon#ireg 11 cls_cnt 2 2006.145.16:41:34.71#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.16:41:34.77#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.16:41:34.77#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.16:41:34.79#ibcon#[27=AT08-04\r\n] 2006.145.16:41:34.82#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.16:41:34.82#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.16:41:34.82#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.16:41:34.82#ibcon#ireg 7 cls_cnt 0 2006.145.16:41:34.82#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.16:41:34.94#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.16:41:34.94#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.16:41:34.96#ibcon#[27=USB\r\n] 2006.145.16:41:34.99#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.16:41:34.99#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.16:41:34.99#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.16:41:34.99#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.16:41:34.99$vck44/vabw=wide 2006.145.16:41:34.99#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.16:41:34.99#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.16:41:34.99#ibcon#ireg 8 cls_cnt 0 2006.145.16:41:34.99#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.16:41:34.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.16:41:34.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.16:41:35.01#ibcon#[25=BW32\r\n] 2006.145.16:41:35.04#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.16:41:35.04#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.16:41:35.04#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.16:41:35.04#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.16:41:35.04$vck44/vbbw=wide 2006.145.16:41:35.04#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.16:41:35.04#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.16:41:35.04#ibcon#ireg 8 cls_cnt 0 2006.145.16:41:35.04#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.16:41:35.11#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.16:41:35.11#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.16:41:35.13#ibcon#[27=BW32\r\n] 2006.145.16:41:35.16#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.16:41:35.16#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.16:41:35.16#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.16:41:35.16#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.16:41:35.16$setupk4/ifdk4 2006.145.16:41:35.16$ifdk4/lo= 2006.145.16:41:35.16$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.16:41:35.16$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.16:41:35.16$ifdk4/patch= 2006.145.16:41:35.16$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.16:41:35.16$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.16:41:35.16$setupk4/!*+20s 2006.145.16:41:39.85#abcon#<5=/08 1.0 2.4 16.00 861019.9\r\n> 2006.145.16:41:39.87#abcon#{5=INTERFACE CLEAR} 2006.145.16:41:39.93#abcon#[5=S1D000X0/0*\r\n] 2006.145.16:41:49.67$setupk4/"tpicd 2006.145.16:41:49.67$setupk4/echo=off 2006.145.16:41:49.67$setupk4/xlog=off 2006.145.16:41:49.67:!2006.145.16:45:04 2006.145.16:41:53.14#trakl#Source acquired 2006.145.16:41:54.14#flagr#flagr/antenna,acquired 2006.145.16:45:04.00:preob 2006.145.16:45:04.14/onsource/TRACKING 2006.145.16:45:04.14:!2006.145.16:45:14 2006.145.16:45:14.00:"tape 2006.145.16:45:14.00:"st=record 2006.145.16:45:14.00:data_valid=on 2006.145.16:45:14.00:midob 2006.145.16:45:15.13/onsource/TRACKING 2006.145.16:45:15.13/wx/16.02,1019.9,86 2006.145.16:45:15.26/cable/+6.5492E-03 2006.145.16:45:16.35/va/01,08,usb,yes,28,30 2006.145.16:45:16.35/va/02,07,usb,yes,30,31 2006.145.16:45:16.35/va/03,08,usb,yes,27,29 2006.145.16:45:16.35/va/04,07,usb,yes,31,33 2006.145.16:45:16.35/va/05,04,usb,yes,27,28 2006.145.16:45:16.35/va/06,04,usb,yes,30,30 2006.145.16:45:16.35/va/07,04,usb,yes,31,32 2006.145.16:45:16.35/va/08,04,usb,yes,26,32 2006.145.16:45:16.58/valo/01,524.99,yes,locked 2006.145.16:45:16.58/valo/02,534.99,yes,locked 2006.145.16:45:16.58/valo/03,564.99,yes,locked 2006.145.16:45:16.58/valo/04,624.99,yes,locked 2006.145.16:45:16.58/valo/05,734.99,yes,locked 2006.145.16:45:16.58/valo/06,814.99,yes,locked 2006.145.16:45:16.58/valo/07,864.99,yes,locked 2006.145.16:45:16.58/valo/08,884.99,yes,locked 2006.145.16:45:17.67/vb/01,03,usb,yes,35,33 2006.145.16:45:17.67/vb/02,04,usb,yes,31,31 2006.145.16:45:17.67/vb/03,04,usb,yes,28,31 2006.145.16:45:17.67/vb/04,04,usb,yes,32,31 2006.145.16:45:17.67/vb/05,04,usb,yes,25,27 2006.145.16:45:17.67/vb/06,04,usb,yes,29,26 2006.145.16:45:17.67/vb/07,04,usb,yes,29,29 2006.145.16:45:17.67/vb/08,04,usb,yes,27,30 2006.145.16:45:17.90/vblo/01,629.99,yes,locked 2006.145.16:45:17.90/vblo/02,634.99,yes,locked 2006.145.16:45:17.90/vblo/03,649.99,yes,locked 2006.145.16:45:17.90/vblo/04,679.99,yes,locked 2006.145.16:45:17.90/vblo/05,709.99,yes,locked 2006.145.16:45:17.90/vblo/06,719.99,yes,locked 2006.145.16:45:17.90/vblo/07,734.99,yes,locked 2006.145.16:45:17.90/vblo/08,744.99,yes,locked 2006.145.16:45:18.05/vabw/8 2006.145.16:45:18.20/vbbw/8 2006.145.16:45:18.29/xfe/off,on,16.0 2006.145.16:45:18.69/ifatt/23,28,28,28 2006.145.16:45:19.07/fmout-gps/S +4.4E-08 2006.145.16:45:19.11:!2006.145.16:52:04 2006.145.16:52:04.00:data_valid=off 2006.145.16:52:04.00:"et 2006.145.16:52:04.00:!+3s 2006.145.16:52:07.02:"tape 2006.145.16:52:07.02:postob 2006.145.16:52:07.16/cable/+6.5482E-03 2006.145.16:52:07.16/wx/16.05,1019.8,87 2006.145.16:52:08.07/fmout-gps/S +4.3E-08 2006.145.16:52:08.07:scan_name=145-1658,jd0605,470 2006.145.16:52:08.08:source=1308+326,131028.66,322043.8,2000.0,cw 2006.145.16:52:09.14#flagr#flagr/antenna,new-source 2006.145.16:52:09.14:checkk5 2006.145.16:52:09.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.16:52:10.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.16:52:10.49/chk_autoobs//k5ts3/ autoobs is running! 2006.145.16:52:10.93/chk_autoobs//k5ts4/ autoobs is running! 2006.145.16:52:11.34/chk_obsdata//k5ts1/T1451645??a.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.145.16:52:11.77/chk_obsdata//k5ts2/T1451645??b.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.145.16:52:12.21/chk_obsdata//k5ts3/T1451645??c.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.145.16:52:12.64/chk_obsdata//k5ts4/T1451645??d.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.145.16:52:13.40/k5log//k5ts1_log_newline 2006.145.16:52:14.15/k5log//k5ts2_log_newline 2006.145.16:52:14.90/k5log//k5ts3_log_newline 2006.145.16:52:15.64/k5log//k5ts4_log_newline 2006.145.16:52:15.66/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.16:52:15.66:setupk4=1 2006.145.16:52:15.66$setupk4/echo=on 2006.145.16:52:15.66$setupk4/pcalon 2006.145.16:52:15.66$pcalon/"no phase cal control is implemented here 2006.145.16:52:15.66$setupk4/"tpicd=stop 2006.145.16:52:15.66$setupk4/"rec=synch_on 2006.145.16:52:15.66$setupk4/"rec_mode=128 2006.145.16:52:15.66$setupk4/!* 2006.145.16:52:15.66$setupk4/recpk4 2006.145.16:52:15.66$recpk4/recpatch= 2006.145.16:52:15.67$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.16:52:15.67$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.16:52:15.67$setupk4/vck44 2006.145.16:52:15.67$vck44/valo=1,524.99 2006.145.16:52:15.67#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.16:52:15.67#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.16:52:15.67#ibcon#ireg 17 cls_cnt 0 2006.145.16:52:15.67#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.16:52:15.67#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.16:52:15.67#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.16:52:15.71#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.16:52:15.76#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.16:52:15.76#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.16:52:15.76#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.16:52:15.76#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.16:52:15.76$vck44/va=1,8 2006.145.16:52:15.76#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.16:52:15.76#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.16:52:15.76#ibcon#ireg 11 cls_cnt 2 2006.145.16:52:15.76#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.16:52:15.76#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.16:52:15.76#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.16:52:15.78#ibcon#[25=AT01-08\r\n] 2006.145.16:52:15.81#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.16:52:15.81#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.16:52:15.81#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.16:52:15.81#ibcon#ireg 7 cls_cnt 0 2006.145.16:52:15.81#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.16:52:15.93#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.16:52:15.93#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.16:52:15.95#ibcon#[25=USB\r\n] 2006.145.16:52:15.98#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.16:52:15.98#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.16:52:15.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.16:52:15.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.16:52:15.98$vck44/valo=2,534.99 2006.145.16:52:15.98#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.16:52:15.98#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.16:52:15.98#ibcon#ireg 17 cls_cnt 0 2006.145.16:52:15.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.16:52:15.98#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.16:52:15.98#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.16:52:16.01#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.16:52:16.05#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.16:52:16.05#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.16:52:16.05#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.16:52:16.05#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.16:52:16.05$vck44/va=2,7 2006.145.16:52:16.05#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.16:52:16.05#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.16:52:16.05#ibcon#ireg 11 cls_cnt 2 2006.145.16:52:16.05#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.16:52:16.10#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.16:52:16.10#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.16:52:16.12#ibcon#[25=AT02-07\r\n] 2006.145.16:52:16.15#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.16:52:16.15#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.16:52:16.15#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.16:52:16.15#ibcon#ireg 7 cls_cnt 0 2006.145.16:52:16.15#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.16:52:16.27#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.16:52:16.27#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.16:52:16.29#ibcon#[25=USB\r\n] 2006.145.16:52:16.32#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.16:52:16.32#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.16:52:16.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.16:52:16.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.16:52:16.32$vck44/valo=3,564.99 2006.145.16:52:16.32#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.16:52:16.32#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.16:52:16.32#ibcon#ireg 17 cls_cnt 0 2006.145.16:52:16.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.16:52:16.32#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.16:52:16.32#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.16:52:16.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.16:52:16.38#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.16:52:16.38#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.16:52:16.38#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.16:52:16.38#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.16:52:16.38$vck44/va=3,8 2006.145.16:52:16.38#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.16:52:16.38#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.16:52:16.38#ibcon#ireg 11 cls_cnt 2 2006.145.16:52:16.38#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.16:52:16.44#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.16:52:16.44#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.16:52:16.46#ibcon#[25=AT03-08\r\n] 2006.145.16:52:16.49#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.16:52:16.49#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.16:52:16.49#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.16:52:16.49#ibcon#ireg 7 cls_cnt 0 2006.145.16:52:16.49#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.16:52:16.61#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.16:52:16.61#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.16:52:16.63#ibcon#[25=USB\r\n] 2006.145.16:52:16.66#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.16:52:16.66#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.16:52:16.66#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.16:52:16.66#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.16:52:16.66$vck44/valo=4,624.99 2006.145.16:52:16.66#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.16:52:16.66#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.16:52:16.66#ibcon#ireg 17 cls_cnt 0 2006.145.16:52:16.66#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.16:52:16.66#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.16:52:16.66#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.16:52:16.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.16:52:16.72#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.16:52:16.72#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.16:52:16.72#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.16:52:16.72#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.16:52:16.72$vck44/va=4,7 2006.145.16:52:16.72#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.16:52:16.72#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.16:52:16.72#ibcon#ireg 11 cls_cnt 2 2006.145.16:52:16.72#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.16:52:16.78#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.16:52:16.78#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.16:52:16.80#ibcon#[25=AT04-07\r\n] 2006.145.16:52:16.83#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.16:52:16.83#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.16:52:16.83#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.16:52:16.83#ibcon#ireg 7 cls_cnt 0 2006.145.16:52:16.83#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.16:52:16.95#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.16:52:16.95#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.16:52:16.97#ibcon#[25=USB\r\n] 2006.145.16:52:17.00#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.16:52:17.00#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.16:52:17.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.16:52:17.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.16:52:17.00$vck44/valo=5,734.99 2006.145.16:52:17.00#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.16:52:17.00#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.16:52:17.00#ibcon#ireg 17 cls_cnt 0 2006.145.16:52:17.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.16:52:17.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.16:52:17.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.16:52:17.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.16:52:17.06#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.16:52:17.06#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.16:52:17.06#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.16:52:17.06#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.16:52:17.06$vck44/va=5,4 2006.145.16:52:17.06#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.16:52:17.06#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.16:52:17.06#ibcon#ireg 11 cls_cnt 2 2006.145.16:52:17.06#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.16:52:17.12#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.16:52:17.12#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.16:52:17.14#ibcon#[25=AT05-04\r\n] 2006.145.16:52:17.17#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.16:52:17.17#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.16:52:17.17#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.16:52:17.17#ibcon#ireg 7 cls_cnt 0 2006.145.16:52:17.17#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.16:52:17.29#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.16:52:17.29#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.16:52:17.31#ibcon#[25=USB\r\n] 2006.145.16:52:17.34#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.16:52:17.34#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.16:52:17.34#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.16:52:17.34#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.16:52:17.34$vck44/valo=6,814.99 2006.145.16:52:17.34#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.16:52:17.34#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.16:52:17.34#ibcon#ireg 17 cls_cnt 0 2006.145.16:52:17.34#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.16:52:17.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.16:52:17.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.16:52:17.37#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.16:52:17.41#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.16:52:17.41#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.16:52:17.41#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.16:52:17.41#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.16:52:17.41$vck44/va=6,4 2006.145.16:52:17.41#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.16:52:17.41#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.16:52:17.41#ibcon#ireg 11 cls_cnt 2 2006.145.16:52:17.41#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.16:52:17.46#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.16:52:17.46#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.16:52:17.48#ibcon#[25=AT06-04\r\n] 2006.145.16:52:17.51#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.16:52:17.51#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.16:52:17.51#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.16:52:17.51#ibcon#ireg 7 cls_cnt 0 2006.145.16:52:17.51#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.16:52:17.63#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.16:52:17.63#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.16:52:17.65#ibcon#[25=USB\r\n] 2006.145.16:52:17.68#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.16:52:17.68#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.16:52:17.68#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.16:52:17.68#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.16:52:17.68$vck44/valo=7,864.99 2006.145.16:52:17.68#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.16:52:17.68#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.16:52:17.68#ibcon#ireg 17 cls_cnt 0 2006.145.16:52:17.68#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.16:52:17.68#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.16:52:17.68#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.16:52:17.70#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.16:52:17.74#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.16:52:17.74#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.16:52:17.74#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.16:52:17.74#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.16:52:17.74$vck44/va=7,4 2006.145.16:52:17.74#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.16:52:17.74#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.16:52:17.74#ibcon#ireg 11 cls_cnt 2 2006.145.16:52:17.74#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.16:52:17.80#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.16:52:17.80#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.16:52:17.82#ibcon#[25=AT07-04\r\n] 2006.145.16:52:17.85#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.16:52:17.85#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.16:52:17.85#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.16:52:17.85#ibcon#ireg 7 cls_cnt 0 2006.145.16:52:17.85#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.16:52:17.97#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.16:52:17.97#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.16:52:17.99#ibcon#[25=USB\r\n] 2006.145.16:52:18.02#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.16:52:18.02#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.16:52:18.02#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.16:52:18.02#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.16:52:18.02$vck44/valo=8,884.99 2006.145.16:52:18.02#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.16:52:18.02#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.16:52:18.02#ibcon#ireg 17 cls_cnt 0 2006.145.16:52:18.02#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.16:52:18.02#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.16:52:18.02#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.16:52:18.04#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.16:52:18.08#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.16:52:18.08#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.16:52:18.08#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.16:52:18.08#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.16:52:18.08$vck44/va=8,4 2006.145.16:52:18.08#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.16:52:18.08#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.16:52:18.08#ibcon#ireg 11 cls_cnt 2 2006.145.16:52:18.08#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.16:52:18.14#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.16:52:18.14#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.16:52:18.16#ibcon#[25=AT08-04\r\n] 2006.145.16:52:18.19#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.16:52:18.19#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.16:52:18.19#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.16:52:18.19#ibcon#ireg 7 cls_cnt 0 2006.145.16:52:18.19#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.16:52:18.31#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.16:52:18.31#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.16:52:18.33#ibcon#[25=USB\r\n] 2006.145.16:52:18.36#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.16:52:18.36#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.16:52:18.36#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.16:52:18.36#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.16:52:18.36$vck44/vblo=1,629.99 2006.145.16:52:18.36#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.16:52:18.36#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.16:52:18.36#ibcon#ireg 17 cls_cnt 0 2006.145.16:52:18.36#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.16:52:18.36#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.16:52:18.36#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.16:52:18.38#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.16:52:18.42#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.16:52:18.42#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.16:52:18.42#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.16:52:18.42#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.16:52:18.42$vck44/vb=1,3 2006.145.16:52:18.42#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.16:52:18.42#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.16:52:18.42#ibcon#ireg 11 cls_cnt 2 2006.145.16:52:18.42#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.16:52:18.42#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.16:52:18.42#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.16:52:18.44#ibcon#[27=AT01-03\r\n] 2006.145.16:52:18.47#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.16:52:18.47#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.16:52:18.47#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.16:52:18.47#ibcon#ireg 7 cls_cnt 0 2006.145.16:52:18.47#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.16:52:18.59#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.16:52:18.59#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.16:52:18.61#ibcon#[27=USB\r\n] 2006.145.16:52:18.64#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.16:52:18.64#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.16:52:18.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.16:52:18.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.16:52:18.64$vck44/vblo=2,634.99 2006.145.16:52:18.64#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.16:52:18.64#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.16:52:18.64#ibcon#ireg 17 cls_cnt 0 2006.145.16:52:18.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.16:52:18.64#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.16:52:18.64#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.16:52:18.66#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.16:52:18.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.16:52:18.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.16:52:18.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.16:52:18.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.16:52:18.70$vck44/vb=2,4 2006.145.16:52:18.70#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.16:52:18.70#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.16:52:18.70#ibcon#ireg 11 cls_cnt 2 2006.145.16:52:18.70#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.16:52:18.76#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.16:52:18.76#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.16:52:18.78#ibcon#[27=AT02-04\r\n] 2006.145.16:52:18.81#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.16:52:18.81#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.16:52:18.81#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.16:52:18.81#ibcon#ireg 7 cls_cnt 0 2006.145.16:52:18.81#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.16:52:18.93#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.16:52:18.93#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.16:52:18.95#ibcon#[27=USB\r\n] 2006.145.16:52:18.98#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.16:52:18.98#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.16:52:18.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.16:52:18.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.16:52:18.98$vck44/vblo=3,649.99 2006.145.16:52:18.98#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.16:52:18.98#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.16:52:18.98#ibcon#ireg 17 cls_cnt 0 2006.145.16:52:18.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.16:52:18.98#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.16:52:18.98#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.16:52:19.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.16:52:19.04#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.16:52:19.04#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.16:52:19.04#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.16:52:19.04#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.16:52:19.04$vck44/vb=3,4 2006.145.16:52:19.04#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.16:52:19.04#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.16:52:19.04#ibcon#ireg 11 cls_cnt 2 2006.145.16:52:19.04#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.16:52:19.10#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.16:52:19.10#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.16:52:19.12#ibcon#[27=AT03-04\r\n] 2006.145.16:52:19.15#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.16:52:19.15#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.16:52:19.15#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.16:52:19.15#ibcon#ireg 7 cls_cnt 0 2006.145.16:52:19.15#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.16:52:19.27#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.16:52:19.27#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.16:52:19.29#ibcon#[27=USB\r\n] 2006.145.16:52:19.32#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.16:52:19.32#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.16:52:19.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.16:52:19.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.16:52:19.32$vck44/vblo=4,679.99 2006.145.16:52:19.32#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.16:52:19.32#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.16:52:19.32#ibcon#ireg 17 cls_cnt 0 2006.145.16:52:19.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.16:52:19.32#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.16:52:19.32#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.16:52:19.34#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.16:52:19.38#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.16:52:19.38#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.16:52:19.38#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.16:52:19.38#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.16:52:19.38$vck44/vb=4,4 2006.145.16:52:19.38#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.16:52:19.38#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.16:52:19.38#ibcon#ireg 11 cls_cnt 2 2006.145.16:52:19.38#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.16:52:19.44#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.16:52:19.44#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.16:52:19.46#ibcon#[27=AT04-04\r\n] 2006.145.16:52:19.49#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.16:52:19.49#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.16:52:19.49#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.16:52:19.49#ibcon#ireg 7 cls_cnt 0 2006.145.16:52:19.49#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.16:52:19.61#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.16:52:19.61#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.16:52:19.63#ibcon#[27=USB\r\n] 2006.145.16:52:19.66#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.16:52:19.66#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.16:52:19.66#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.16:52:19.66#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.16:52:19.66$vck44/vblo=5,709.99 2006.145.16:52:19.66#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.16:52:19.66#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.16:52:19.66#ibcon#ireg 17 cls_cnt 0 2006.145.16:52:19.66#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.16:52:19.66#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.16:52:19.66#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.16:52:19.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.16:52:19.72#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.16:52:19.72#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.16:52:19.72#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.16:52:19.72#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.16:52:19.72$vck44/vb=5,4 2006.145.16:52:19.72#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.16:52:19.72#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.16:52:19.72#ibcon#ireg 11 cls_cnt 2 2006.145.16:52:19.72#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.16:52:19.78#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.16:52:19.78#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.16:52:19.80#ibcon#[27=AT05-04\r\n] 2006.145.16:52:19.83#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.16:52:19.83#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.16:52:19.83#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.16:52:19.83#ibcon#ireg 7 cls_cnt 0 2006.145.16:52:19.83#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.16:52:19.95#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.16:52:19.95#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.16:52:19.97#ibcon#[27=USB\r\n] 2006.145.16:52:20.00#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.16:52:20.00#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.16:52:20.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.16:52:20.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.16:52:20.00$vck44/vblo=6,719.99 2006.145.16:52:20.00#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.16:52:20.00#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.16:52:20.00#ibcon#ireg 17 cls_cnt 0 2006.145.16:52:20.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.16:52:20.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.16:52:20.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.16:52:20.02#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.16:52:20.06#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.16:52:20.06#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.16:52:20.06#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.16:52:20.06#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.16:52:20.06$vck44/vb=6,4 2006.145.16:52:20.06#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.16:52:20.06#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.16:52:20.06#ibcon#ireg 11 cls_cnt 2 2006.145.16:52:20.06#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.16:52:20.12#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.16:52:20.12#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.16:52:20.14#ibcon#[27=AT06-04\r\n] 2006.145.16:52:20.17#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.16:52:20.17#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.16:52:20.17#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.16:52:20.17#ibcon#ireg 7 cls_cnt 0 2006.145.16:52:20.17#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.16:52:20.29#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.16:52:20.29#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.16:52:20.31#ibcon#[27=USB\r\n] 2006.145.16:52:20.34#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.16:52:20.34#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.16:52:20.34#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.16:52:20.34#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.16:52:20.34$vck44/vblo=7,734.99 2006.145.16:52:20.34#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.16:52:20.34#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.16:52:20.34#ibcon#ireg 17 cls_cnt 0 2006.145.16:52:20.34#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.16:52:20.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.16:52:20.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.16:52:20.36#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.16:52:20.40#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.16:52:20.40#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.16:52:20.40#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.16:52:20.40#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.16:52:20.40$vck44/vb=7,4 2006.145.16:52:20.40#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.16:52:20.40#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.16:52:20.40#ibcon#ireg 11 cls_cnt 2 2006.145.16:52:20.40#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.16:52:20.46#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.16:52:20.46#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.16:52:20.48#ibcon#[27=AT07-04\r\n] 2006.145.16:52:20.51#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.16:52:20.51#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.16:52:20.51#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.16:52:20.51#ibcon#ireg 7 cls_cnt 0 2006.145.16:52:20.51#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.16:52:20.63#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.16:52:20.63#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.16:52:20.65#ibcon#[27=USB\r\n] 2006.145.16:52:20.68#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.16:52:20.68#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.16:52:20.68#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.16:52:20.68#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.16:52:20.68$vck44/vblo=8,744.99 2006.145.16:52:20.68#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.16:52:20.68#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.16:52:20.68#ibcon#ireg 17 cls_cnt 0 2006.145.16:52:20.68#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.16:52:20.68#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.16:52:20.68#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.16:52:20.70#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.16:52:20.74#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.16:52:20.74#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.16:52:20.74#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.16:52:20.74#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.16:52:20.74$vck44/vb=8,4 2006.145.16:52:20.74#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.16:52:20.74#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.16:52:20.74#ibcon#ireg 11 cls_cnt 2 2006.145.16:52:20.74#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.16:52:20.80#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.16:52:20.80#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.16:52:20.81#abcon#<5=/07 0.9 2.1 16.05 871019.8\r\n> 2006.145.16:52:20.82#ibcon#[27=AT08-04\r\n] 2006.145.16:52:20.83#abcon#{5=INTERFACE CLEAR} 2006.145.16:52:20.85#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.16:52:20.85#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.16:52:20.85#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.16:52:20.85#ibcon#ireg 7 cls_cnt 0 2006.145.16:52:20.85#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.16:52:20.89#abcon#[5=S1D000X0/0*\r\n] 2006.145.16:52:20.97#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.16:52:20.97#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.16:52:20.99#ibcon#[27=USB\r\n] 2006.145.16:52:21.02#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.16:52:21.02#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.16:52:21.02#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.16:52:21.02#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.16:52:21.02$vck44/vabw=wide 2006.145.16:52:21.02#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.16:52:21.02#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.16:52:21.02#ibcon#ireg 8 cls_cnt 0 2006.145.16:52:21.02#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.16:52:21.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.16:52:21.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.16:52:21.04#ibcon#[25=BW32\r\n] 2006.145.16:52:21.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.16:52:21.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.16:52:21.07#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.16:52:21.07#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.16:52:21.07$vck44/vbbw=wide 2006.145.16:52:21.07#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.16:52:21.07#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.16:52:21.07#ibcon#ireg 8 cls_cnt 0 2006.145.16:52:21.07#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:52:21.14#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:52:21.14#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:52:21.16#ibcon#[27=BW32\r\n] 2006.145.16:52:21.19#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:52:21.19#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.16:52:21.19#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.16:52:21.19#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.16:52:21.19$setupk4/ifdk4 2006.145.16:52:21.19$ifdk4/lo= 2006.145.16:52:21.19$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.16:52:21.19$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.16:52:21.19$ifdk4/patch= 2006.145.16:52:21.19$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.16:52:21.19$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.16:52:21.19$setupk4/!*+20s 2006.145.16:52:27.14#trakl#Source acquired 2006.145.16:52:29.14#flagr#flagr/antenna,acquired 2006.145.16:52:30.98#abcon#<5=/07 0.9 2.1 16.05 871019.8\r\n> 2006.145.16:52:31.00#abcon#{5=INTERFACE CLEAR} 2006.145.16:52:31.06#abcon#[5=S1D000X0/0*\r\n] 2006.145.16:52:35.67$setupk4/"tpicd 2006.145.16:52:35.67$setupk4/echo=off 2006.145.16:52:35.67$setupk4/xlog=off 2006.145.16:52:35.67:!2006.145.16:58:44 2006.145.16:58:44.02:preob 2006.145.16:58:45.14/onsource/TRACKING 2006.145.16:58:45.14:!2006.145.16:58:54 2006.145.16:58:54.02:"tape 2006.145.16:58:54.02:"st=record 2006.145.16:58:54.02:data_valid=on 2006.145.16:58:54.02:midob 2006.145.16:58:55.14/onsource/TRACKING 2006.145.16:58:55.14/wx/16.02,1019.8,87 2006.145.16:58:55.21/cable/+6.5488E-03 2006.145.16:58:56.30/va/01,08,usb,yes,29,31 2006.145.16:58:56.30/va/02,07,usb,yes,31,32 2006.145.16:58:56.30/va/03,08,usb,yes,28,30 2006.145.16:58:56.30/va/04,07,usb,yes,32,34 2006.145.16:58:56.30/va/05,04,usb,yes,28,29 2006.145.16:58:56.30/va/06,04,usb,yes,32,31 2006.145.16:58:56.30/va/07,04,usb,yes,32,33 2006.145.16:58:56.30/va/08,04,usb,yes,27,33 2006.145.16:58:56.53/valo/01,524.99,yes,locked 2006.145.16:58:56.53/valo/02,534.99,yes,locked 2006.145.16:58:56.53/valo/03,564.99,yes,locked 2006.145.16:58:56.53/valo/04,624.99,yes,locked 2006.145.16:58:56.53/valo/05,734.99,yes,locked 2006.145.16:58:56.53/valo/06,814.99,yes,locked 2006.145.16:58:56.53/valo/07,864.99,yes,locked 2006.145.16:58:56.53/valo/08,884.99,yes,locked 2006.145.16:58:57.62/vb/01,03,usb,yes,36,34 2006.145.16:58:57.62/vb/02,04,usb,yes,32,31 2006.145.16:58:57.62/vb/03,04,usb,yes,29,31 2006.145.16:58:57.62/vb/04,04,usb,yes,33,32 2006.145.16:58:57.62/vb/05,04,usb,yes,25,28 2006.145.16:58:57.62/vb/06,04,usb,yes,30,26 2006.145.16:58:57.62/vb/07,04,usb,yes,30,29 2006.145.16:58:57.62/vb/08,04,usb,yes,27,30 2006.145.16:58:57.85/vblo/01,629.99,yes,locked 2006.145.16:58:57.85/vblo/02,634.99,yes,locked 2006.145.16:58:57.85/vblo/03,649.99,yes,locked 2006.145.16:58:57.85/vblo/04,679.99,yes,locked 2006.145.16:58:57.85/vblo/05,709.99,yes,locked 2006.145.16:58:57.85/vblo/06,719.99,yes,locked 2006.145.16:58:57.85/vblo/07,734.99,yes,locked 2006.145.16:58:57.85/vblo/08,744.99,yes,locked 2006.145.16:58:58.00/vabw/8 2006.145.16:58:58.15/vbbw/8 2006.145.16:58:58.27/xfe/off,on,14.0 2006.145.16:58:58.64/ifatt/23,28,28,28 2006.145.16:58:59.08/fmout-gps/S +4.5E-08 2006.145.16:58:59.12:!2006.145.17:06:44 2006.145.17:06:44.00:data_valid=off 2006.145.17:06:44.01:"et 2006.145.17:06:44.01:!+3s 2006.145.17:06:47.04:"tape 2006.145.17:06:47.05:postob 2006.145.17:06:47.16/cable/+6.5482E-03 2006.145.17:06:47.17/wx/15.99,1019.8,87 2006.145.17:06:47.23/fmout-gps/S +4.6E-08 2006.145.17:06:47.23:scan_name=145-1713,jd0605,210 2006.145.17:06:47.23:source=3c446,222547.26,-045701.4,2000.0,cw 2006.145.17:06:49.14#flagr#flagr/antenna,new-source 2006.145.17:06:49.15:checkk5 2006.145.17:06:49.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.17:06:50.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.17:06:50.44/chk_autoobs//k5ts3/ autoobs is running! 2006.145.17:06:50.87/chk_autoobs//k5ts4/ autoobs is running! 2006.145.17:06:51.31/chk_obsdata//k5ts1/T1451658??a.dat file size is correct (nominal:1880MB, actual:1880MB). 2006.145.17:06:51.75/chk_obsdata//k5ts2/T1451658??b.dat file size is correct (nominal:1880MB, actual:1880MB). 2006.145.17:06:52.18/chk_obsdata//k5ts3/T1451658??c.dat file size is correct (nominal:1880MB, actual:1880MB). 2006.145.17:06:52.61/chk_obsdata//k5ts4/T1451658??d.dat file size is correct (nominal:1880MB, actual:1880MB). 2006.145.17:06:53.38/k5log//k5ts1_log_newline 2006.145.17:06:54.13/k5log//k5ts2_log_newline 2006.145.17:06:54.89/k5log//k5ts3_log_newline 2006.145.17:06:55.64/k5log//k5ts4_log_newline 2006.145.17:06:55.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.17:06:55.67:setupk4=1 2006.145.17:06:55.67$setupk4/echo=on 2006.145.17:06:55.67$setupk4/pcalon 2006.145.17:06:55.67$pcalon/"no phase cal control is implemented here 2006.145.17:06:55.67$setupk4/"tpicd=stop 2006.145.17:06:55.67$setupk4/"rec=synch_on 2006.145.17:06:55.67$setupk4/"rec_mode=128 2006.145.17:06:55.67$setupk4/!* 2006.145.17:06:55.67$setupk4/recpk4 2006.145.17:06:55.67$recpk4/recpatch= 2006.145.17:06:55.68$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.17:06:55.68$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.17:06:55.68$setupk4/vck44 2006.145.17:06:55.68$vck44/valo=1,524.99 2006.145.17:06:55.68#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.17:06:55.68#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.17:06:55.68#ibcon#ireg 17 cls_cnt 0 2006.145.17:06:55.68#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.17:06:55.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.17:06:55.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.17:06:55.71#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.17:06:55.76#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.17:06:55.76#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.17:06:55.76#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.17:06:55.76#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.17:06:55.76$vck44/va=1,8 2006.145.17:06:55.76#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.17:06:55.76#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.17:06:55.76#ibcon#ireg 11 cls_cnt 2 2006.145.17:06:55.76#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.17:06:55.76#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.17:06:55.76#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.17:06:55.78#ibcon#[25=AT01-08\r\n] 2006.145.17:06:55.81#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.17:06:55.81#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.17:06:55.81#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.17:06:55.81#ibcon#ireg 7 cls_cnt 0 2006.145.17:06:55.81#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.17:06:55.96#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.17:06:55.96#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.17:06:55.97#ibcon#[25=USB\r\n] 2006.145.17:06:56.00#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.17:06:56.00#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.17:06:56.00#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.17:06:56.00#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.17:06:56.00$vck44/valo=2,534.99 2006.145.17:06:56.00#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.17:06:56.00#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.17:06:56.00#ibcon#ireg 17 cls_cnt 0 2006.145.17:06:56.00#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:06:56.00#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:06:56.00#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:06:56.04#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.17:06:56.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:06:56.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:06:56.08#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.17:06:56.08#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.17:06:56.08$vck44/va=2,7 2006.145.17:06:56.08#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.17:06:56.08#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.17:06:56.08#ibcon#ireg 11 cls_cnt 2 2006.145.17:06:56.08#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:06:56.13#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:06:56.13#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:06:56.14#ibcon#[25=AT02-07\r\n] 2006.145.17:06:56.17#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:06:56.17#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:06:56.17#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.17:06:56.17#ibcon#ireg 7 cls_cnt 0 2006.145.17:06:56.17#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:06:56.29#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:06:56.29#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:06:56.31#ibcon#[25=USB\r\n] 2006.145.17:06:56.34#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:06:56.34#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:06:56.34#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.17:06:56.34#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.17:06:56.34$vck44/valo=3,564.99 2006.145.17:06:56.34#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.17:06:56.34#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.17:06:56.34#ibcon#ireg 17 cls_cnt 0 2006.145.17:06:56.34#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:06:56.34#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:06:56.34#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:06:56.36#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.17:06:56.40#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:06:56.40#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:06:56.40#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.17:06:56.40#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.17:06:56.40$vck44/va=3,8 2006.145.17:06:56.40#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.17:06:56.40#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.17:06:56.40#ibcon#ireg 11 cls_cnt 2 2006.145.17:06:56.40#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:06:56.46#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:06:56.46#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:06:56.48#ibcon#[25=AT03-08\r\n] 2006.145.17:06:56.51#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:06:56.51#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:06:56.51#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.17:06:56.51#ibcon#ireg 7 cls_cnt 0 2006.145.17:06:56.51#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:06:56.63#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:06:56.63#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:06:56.65#ibcon#[25=USB\r\n] 2006.145.17:06:56.68#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:06:56.68#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:06:56.68#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.17:06:56.68#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.17:06:56.68$vck44/valo=4,624.99 2006.145.17:06:56.68#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.17:06:56.68#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.17:06:56.68#ibcon#ireg 17 cls_cnt 0 2006.145.17:06:56.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:06:56.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:06:56.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:06:56.70#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.17:06:56.74#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:06:56.74#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:06:56.74#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.17:06:56.74#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.17:06:56.74$vck44/va=4,7 2006.145.17:06:56.74#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.17:06:56.74#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.17:06:56.74#ibcon#ireg 11 cls_cnt 2 2006.145.17:06:56.74#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.17:06:56.80#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.17:06:56.80#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.17:06:56.82#ibcon#[25=AT04-07\r\n] 2006.145.17:06:56.85#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.17:06:56.85#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.17:06:56.85#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.17:06:56.85#ibcon#ireg 7 cls_cnt 0 2006.145.17:06:56.85#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.17:06:56.97#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.17:06:56.97#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.17:06:56.99#ibcon#[25=USB\r\n] 2006.145.17:06:57.02#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.17:06:57.02#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.17:06:57.02#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.17:06:57.02#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.17:06:57.02$vck44/valo=5,734.99 2006.145.17:06:57.02#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.17:06:57.02#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.17:06:57.02#ibcon#ireg 17 cls_cnt 0 2006.145.17:06:57.02#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.17:06:57.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.17:06:57.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.17:06:57.04#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.17:06:57.08#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.17:06:57.08#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.17:06:57.08#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.17:06:57.08#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.17:06:57.08$vck44/va=5,4 2006.145.17:06:57.08#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.17:06:57.08#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.17:06:57.08#ibcon#ireg 11 cls_cnt 2 2006.145.17:06:57.08#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.17:06:57.17#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.17:06:57.17#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.17:06:57.18#ibcon#[25=AT05-04\r\n] 2006.145.17:06:57.21#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.17:06:57.21#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.17:06:57.21#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.17:06:57.21#ibcon#ireg 7 cls_cnt 0 2006.145.17:06:57.21#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.17:06:57.33#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.17:06:57.33#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.17:06:57.35#ibcon#[25=USB\r\n] 2006.145.17:06:57.38#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.17:06:57.38#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.17:06:57.38#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.17:06:57.38#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.17:06:57.38$vck44/valo=6,814.99 2006.145.17:06:57.38#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.17:06:57.38#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.17:06:57.38#ibcon#ireg 17 cls_cnt 0 2006.145.17:06:57.38#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:06:57.38#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:06:57.38#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:06:57.41#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.17:06:57.45#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:06:57.45#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:06:57.45#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.17:06:57.45#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.17:06:57.45$vck44/va=6,4 2006.145.17:06:57.45#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.17:06:57.45#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.17:06:57.45#ibcon#ireg 11 cls_cnt 2 2006.145.17:06:57.45#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:06:57.50#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:06:57.50#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:06:57.52#ibcon#[25=AT06-04\r\n] 2006.145.17:06:57.55#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:06:57.55#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:06:57.55#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.17:06:57.55#ibcon#ireg 7 cls_cnt 0 2006.145.17:06:57.55#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:06:57.67#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:06:57.67#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:06:57.69#ibcon#[25=USB\r\n] 2006.145.17:06:57.72#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:06:57.72#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:06:57.72#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.17:06:57.72#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.17:06:57.72$vck44/valo=7,864.99 2006.145.17:06:57.72#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.17:06:57.72#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.17:06:57.72#ibcon#ireg 17 cls_cnt 0 2006.145.17:06:57.72#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:06:57.72#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:06:57.72#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:06:57.74#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.17:06:57.78#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:06:57.78#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:06:57.78#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.17:06:57.78#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.17:06:57.78$vck44/va=7,4 2006.145.17:06:57.78#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.17:06:57.78#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.17:06:57.78#ibcon#ireg 11 cls_cnt 2 2006.145.17:06:57.78#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.17:06:57.84#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.17:06:57.84#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.17:06:57.86#ibcon#[25=AT07-04\r\n] 2006.145.17:06:57.89#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.17:06:57.89#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.17:06:57.89#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.17:06:57.89#ibcon#ireg 7 cls_cnt 0 2006.145.17:06:57.89#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.17:06:58.01#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.17:06:58.01#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.17:06:58.03#ibcon#[25=USB\r\n] 2006.145.17:06:58.06#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.17:06:58.06#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.17:06:58.06#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.17:06:58.06#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.17:06:58.06$vck44/valo=8,884.99 2006.145.17:06:58.06#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.17:06:58.06#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.17:06:58.06#ibcon#ireg 17 cls_cnt 0 2006.145.17:06:58.06#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:06:58.06#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:06:58.06#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:06:58.08#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.17:06:58.12#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:06:58.12#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:06:58.12#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.17:06:58.12#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.17:06:58.12$vck44/va=8,4 2006.145.17:06:58.12#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.17:06:58.12#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.17:06:58.12#ibcon#ireg 11 cls_cnt 2 2006.145.17:06:58.12#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:06:58.18#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:06:58.18#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:06:58.20#ibcon#[25=AT08-04\r\n] 2006.145.17:06:58.23#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:06:58.23#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:06:58.23#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.17:06:58.23#ibcon#ireg 7 cls_cnt 0 2006.145.17:06:58.23#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:06:58.34#abcon#<5=/08 0.7 1.4 15.98 871019.8\r\n> 2006.145.17:06:58.35#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:06:58.35#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:06:58.36#abcon#{5=INTERFACE CLEAR} 2006.145.17:06:58.37#ibcon#[25=USB\r\n] 2006.145.17:06:58.40#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:06:58.40#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:06:58.40#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.17:06:58.40#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.17:06:58.40$vck44/vblo=1,629.99 2006.145.17:06:58.40#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.17:06:58.40#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.17:06:58.40#ibcon#ireg 17 cls_cnt 0 2006.145.17:06:58.40#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.17:06:58.40#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.17:06:58.40#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.17:06:58.42#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.17:06:58.42#abcon#[5=S1D000X0/0*\r\n] 2006.145.17:06:58.46#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.17:06:58.46#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.17:06:58.46#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.17:06:58.46#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.17:06:58.46$vck44/vb=1,3 2006.145.17:06:58.46#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.17:06:58.46#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.17:06:58.46#ibcon#ireg 11 cls_cnt 2 2006.145.17:06:58.46#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.17:06:58.46#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.17:06:58.46#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.17:06:58.48#ibcon#[27=AT01-03\r\n] 2006.145.17:06:58.51#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.17:06:58.51#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.17:06:58.51#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.17:06:58.51#ibcon#ireg 7 cls_cnt 0 2006.145.17:06:58.51#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.17:06:58.63#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.17:06:58.63#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.17:06:58.65#ibcon#[27=USB\r\n] 2006.145.17:06:58.68#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.17:06:58.68#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.17:06:58.68#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.17:06:58.68#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.17:06:58.68$vck44/vblo=2,634.99 2006.145.17:06:58.68#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.17:06:58.68#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.17:06:58.68#ibcon#ireg 17 cls_cnt 0 2006.145.17:06:58.68#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:06:58.68#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:06:58.68#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:06:58.70#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.17:06:58.74#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:06:58.74#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:06:58.74#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.17:06:58.74#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.17:06:58.74$vck44/vb=2,4 2006.145.17:06:58.74#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.17:06:58.74#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.17:06:58.74#ibcon#ireg 11 cls_cnt 2 2006.145.17:06:58.74#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:06:58.80#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:06:58.80#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:06:58.82#ibcon#[27=AT02-04\r\n] 2006.145.17:06:58.85#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:06:58.85#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:06:58.85#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.17:06:58.85#ibcon#ireg 7 cls_cnt 0 2006.145.17:06:58.85#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:06:58.97#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:06:58.97#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:06:58.99#ibcon#[27=USB\r\n] 2006.145.17:06:59.02#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:06:59.02#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:06:59.02#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.17:06:59.02#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.17:06:59.02$vck44/vblo=3,649.99 2006.145.17:06:59.02#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.17:06:59.02#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.17:06:59.02#ibcon#ireg 17 cls_cnt 0 2006.145.17:06:59.02#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:06:59.02#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:06:59.02#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:06:59.04#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.17:06:59.08#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:06:59.08#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:06:59.08#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.17:06:59.08#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.17:06:59.08$vck44/vb=3,4 2006.145.17:06:59.08#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.17:06:59.08#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.17:06:59.08#ibcon#ireg 11 cls_cnt 2 2006.145.17:06:59.08#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:06:59.14#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:06:59.14#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:06:59.16#ibcon#[27=AT03-04\r\n] 2006.145.17:06:59.19#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:06:59.19#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:06:59.19#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.17:06:59.19#ibcon#ireg 7 cls_cnt 0 2006.145.17:06:59.19#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:06:59.31#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:06:59.31#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:06:59.33#ibcon#[27=USB\r\n] 2006.145.17:06:59.36#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:06:59.36#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:06:59.36#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.17:06:59.36#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.17:06:59.36$vck44/vblo=4,679.99 2006.145.17:06:59.36#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.17:06:59.36#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.17:06:59.36#ibcon#ireg 17 cls_cnt 0 2006.145.17:06:59.36#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:06:59.36#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:06:59.36#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:06:59.38#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.17:06:59.42#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:06:59.42#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:06:59.42#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.17:06:59.42#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.17:06:59.42$vck44/vb=4,4 2006.145.17:06:59.42#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.17:06:59.42#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.17:06:59.42#ibcon#ireg 11 cls_cnt 2 2006.145.17:06:59.42#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.17:06:59.48#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.17:06:59.48#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.17:06:59.50#ibcon#[27=AT04-04\r\n] 2006.145.17:06:59.53#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.17:06:59.53#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.17:06:59.53#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.17:06:59.53#ibcon#ireg 7 cls_cnt 0 2006.145.17:06:59.53#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.17:06:59.65#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.17:06:59.65#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.17:06:59.67#ibcon#[27=USB\r\n] 2006.145.17:06:59.70#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.17:06:59.70#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.17:06:59.70#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.17:06:59.70#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.17:06:59.70$vck44/vblo=5,709.99 2006.145.17:06:59.70#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.17:06:59.70#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.17:06:59.70#ibcon#ireg 17 cls_cnt 0 2006.145.17:06:59.70#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.17:06:59.70#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.17:06:59.70#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.17:06:59.72#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.17:06:59.76#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.17:06:59.76#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.17:06:59.76#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.17:06:59.76#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.17:06:59.76$vck44/vb=5,4 2006.145.17:06:59.76#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.17:06:59.76#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.17:06:59.76#ibcon#ireg 11 cls_cnt 2 2006.145.17:06:59.76#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.17:06:59.82#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.17:06:59.82#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.17:06:59.84#ibcon#[27=AT05-04\r\n] 2006.145.17:06:59.87#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.17:06:59.87#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.17:06:59.87#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.17:06:59.87#ibcon#ireg 7 cls_cnt 0 2006.145.17:06:59.87#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.17:06:59.99#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.17:06:59.99#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.17:07:00.01#ibcon#[27=USB\r\n] 2006.145.17:07:00.04#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.17:07:00.04#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.17:07:00.04#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.17:07:00.04#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.17:07:00.04$vck44/vblo=6,719.99 2006.145.17:07:00.04#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.17:07:00.04#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.17:07:00.04#ibcon#ireg 17 cls_cnt 0 2006.145.17:07:00.04#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:07:00.04#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:07:00.04#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:07:00.06#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.17:07:00.10#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:07:00.10#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:07:00.10#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.17:07:00.10#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.17:07:00.10$vck44/vb=6,4 2006.145.17:07:00.10#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.17:07:00.10#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.17:07:00.10#ibcon#ireg 11 cls_cnt 2 2006.145.17:07:00.10#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:07:00.16#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:07:00.16#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:07:00.18#ibcon#[27=AT06-04\r\n] 2006.145.17:07:00.21#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:07:00.21#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:07:00.21#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.17:07:00.21#ibcon#ireg 7 cls_cnt 0 2006.145.17:07:00.21#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:07:00.33#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:07:00.33#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:07:00.35#ibcon#[27=USB\r\n] 2006.145.17:07:00.38#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:07:00.38#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:07:00.38#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.17:07:00.38#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.17:07:00.38$vck44/vblo=7,734.99 2006.145.17:07:00.38#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.17:07:00.38#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.17:07:00.38#ibcon#ireg 17 cls_cnt 0 2006.145.17:07:00.38#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:07:00.38#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:07:00.38#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:07:00.40#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.17:07:00.44#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:07:00.44#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:07:00.44#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.17:07:00.44#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.17:07:00.44$vck44/vb=7,4 2006.145.17:07:00.44#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.17:07:00.44#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.17:07:00.44#ibcon#ireg 11 cls_cnt 2 2006.145.17:07:00.44#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.17:07:00.50#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.17:07:00.50#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.17:07:00.52#ibcon#[27=AT07-04\r\n] 2006.145.17:07:00.55#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.17:07:00.55#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.17:07:00.55#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.17:07:00.55#ibcon#ireg 7 cls_cnt 0 2006.145.17:07:00.55#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.17:07:00.67#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.17:07:00.67#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.17:07:00.69#ibcon#[27=USB\r\n] 2006.145.17:07:00.72#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.17:07:00.72#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.17:07:00.72#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.17:07:00.72#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.17:07:00.72$vck44/vblo=8,744.99 2006.145.17:07:00.72#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.17:07:00.72#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.17:07:00.72#ibcon#ireg 17 cls_cnt 0 2006.145.17:07:00.72#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:07:00.72#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:07:00.72#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:07:00.74#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.17:07:00.78#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:07:00.78#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:07:00.78#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.17:07:00.78#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.17:07:00.78$vck44/vb=8,4 2006.145.17:07:00.78#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.17:07:00.78#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.17:07:00.78#ibcon#ireg 11 cls_cnt 2 2006.145.17:07:00.78#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:07:00.84#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:07:00.84#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:07:00.86#ibcon#[27=AT08-04\r\n] 2006.145.17:07:00.89#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:07:00.89#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:07:00.89#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.17:07:00.89#ibcon#ireg 7 cls_cnt 0 2006.145.17:07:00.89#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:07:01.01#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:07:01.01#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:07:01.03#ibcon#[27=USB\r\n] 2006.145.17:07:01.06#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:07:01.06#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:07:01.06#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.17:07:01.06#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.17:07:01.06$vck44/vabw=wide 2006.145.17:07:01.06#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.17:07:01.06#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.17:07:01.06#ibcon#ireg 8 cls_cnt 0 2006.145.17:07:01.06#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.17:07:01.06#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.17:07:01.06#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.17:07:01.08#ibcon#[25=BW32\r\n] 2006.145.17:07:01.11#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.17:07:01.11#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.17:07:01.11#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.17:07:01.11#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.17:07:01.11$vck44/vbbw=wide 2006.145.17:07:01.11#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.17:07:01.11#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.17:07:01.11#ibcon#ireg 8 cls_cnt 0 2006.145.17:07:01.11#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:07:01.18#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:07:01.18#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:07:01.20#ibcon#[27=BW32\r\n] 2006.145.17:07:01.23#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:07:01.23#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:07:01.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.17:07:01.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.17:07:01.23$setupk4/ifdk4 2006.145.17:07:01.23$ifdk4/lo= 2006.145.17:07:01.23$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.17:07:01.23$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.17:07:01.23$ifdk4/patch= 2006.145.17:07:01.23$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.17:07:01.23$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.17:07:01.23$setupk4/!*+20s 2006.145.17:07:08.51#abcon#<5=/08 0.7 1.4 15.99 871019.8\r\n> 2006.145.17:07:08.53#abcon#{5=INTERFACE CLEAR} 2006.145.17:07:08.59#abcon#[5=S1D000X0/0*\r\n] 2006.145.17:07:15.68$setupk4/"tpicd 2006.145.17:07:15.68$setupk4/echo=off 2006.145.17:07:15.68$setupk4/xlog=off 2006.145.17:07:15.68:!2006.145.17:13:00 2006.145.17:07:56.14#trakl#Source acquired 2006.145.17:07:56.14#flagr#flagr/antenna,acquired 2006.145.17:13:00.00:preob 2006.145.17:13:00.14/onsource/TRACKING 2006.145.17:13:00.14:!2006.145.17:13:10 2006.145.17:13:10.00:"tape 2006.145.17:13:10.00:"st=record 2006.145.17:13:10.00:data_valid=on 2006.145.17:13:10.00:midob 2006.145.17:13:11.14/onsource/TRACKING 2006.145.17:13:11.14/wx/16.01,1019.7,88 2006.145.17:13:11.24/cable/+6.5498E-03 2006.145.17:13:12.33/va/01,08,usb,yes,30,32 2006.145.17:13:12.33/va/02,07,usb,yes,32,32 2006.145.17:13:12.33/va/03,08,usb,yes,29,30 2006.145.17:13:12.33/va/04,07,usb,yes,33,34 2006.145.17:13:12.33/va/05,04,usb,yes,28,29 2006.145.17:13:12.33/va/06,04,usb,yes,32,32 2006.145.17:13:12.33/va/07,04,usb,yes,32,33 2006.145.17:13:12.33/va/08,04,usb,yes,28,33 2006.145.17:13:12.56/valo/01,524.99,yes,locked 2006.145.17:13:12.56/valo/02,534.99,yes,locked 2006.145.17:13:12.56/valo/03,564.99,yes,locked 2006.145.17:13:12.56/valo/04,624.99,yes,locked 2006.145.17:13:12.56/valo/05,734.99,yes,locked 2006.145.17:13:12.56/valo/06,814.99,yes,locked 2006.145.17:13:12.56/valo/07,864.99,yes,locked 2006.145.17:13:12.56/valo/08,884.99,yes,locked 2006.145.17:13:13.65/vb/01,03,usb,yes,37,34 2006.145.17:13:13.65/vb/02,04,usb,yes,32,32 2006.145.17:13:13.65/vb/03,04,usb,yes,29,32 2006.145.17:13:13.65/vb/04,04,usb,yes,33,32 2006.145.17:13:13.65/vb/05,04,usb,yes,26,28 2006.145.17:13:13.65/vb/06,04,usb,yes,30,27 2006.145.17:13:13.65/vb/07,04,usb,yes,30,30 2006.145.17:13:13.65/vb/08,04,usb,yes,28,31 2006.145.17:13:13.88/vblo/01,629.99,yes,locked 2006.145.17:13:13.88/vblo/02,634.99,yes,locked 2006.145.17:13:13.88/vblo/03,649.99,yes,locked 2006.145.17:13:13.88/vblo/04,679.99,yes,locked 2006.145.17:13:13.88/vblo/05,709.99,yes,locked 2006.145.17:13:13.88/vblo/06,719.99,yes,locked 2006.145.17:13:13.88/vblo/07,734.99,yes,locked 2006.145.17:13:13.88/vblo/08,744.99,yes,locked 2006.145.17:13:14.03/vabw/8 2006.145.17:13:14.18/vbbw/8 2006.145.17:13:14.27/xfe/off,on,15.2 2006.145.17:13:14.67/ifatt/23,28,28,28 2006.145.17:13:15.07/fmout-gps/S +4.3E-08 2006.145.17:13:15.15:!2006.145.17:16:40 2006.145.17:16:40.01:data_valid=off 2006.145.17:16:40.02:"et 2006.145.17:16:40.02:!+3s 2006.145.17:16:43.03:"tape 2006.145.17:16:43.03:postob 2006.145.17:16:43.17/cable/+6.5480E-03 2006.145.17:16:43.18/wx/16.03,1019.7,88 2006.145.17:16:43.24/fmout-gps/S +4.3E-08 2006.145.17:16:43.24:scan_name=145-1719,jd0605,40 2006.145.17:16:43.24:source=3c454.3,225357.75,160853.6,2000.0,cw 2006.145.17:16:44.14#flagr#flagr/antenna,new-source 2006.145.17:16:44.15:checkk5 2006.145.17:16:44.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.17:16:45.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.17:16:45.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.17:16:45.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.17:16:46.31/chk_obsdata//k5ts1/T1451713??a.dat file size is correct (nominal:840MB, actual:840MB). 2006.145.17:16:46.73/chk_obsdata//k5ts2/T1451713??b.dat file size is correct (nominal:840MB, actual:840MB). 2006.145.17:16:47.18/chk_obsdata//k5ts3/T1451713??c.dat file size is correct (nominal:840MB, actual:840MB). 2006.145.17:16:47.62/chk_obsdata//k5ts4/T1451713??d.dat file size is correct (nominal:840MB, actual:840MB). 2006.145.17:16:48.40/k5log//k5ts1_log_newline 2006.145.17:16:49.15/k5log//k5ts2_log_newline 2006.145.17:16:49.89/k5log//k5ts3_log_newline 2006.145.17:16:50.64/k5log//k5ts4_log_newline 2006.145.17:16:50.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.17:16:50.67:setupk4=1 2006.145.17:16:50.67$setupk4/echo=on 2006.145.17:16:50.67$setupk4/pcalon 2006.145.17:16:50.67$pcalon/"no phase cal control is implemented here 2006.145.17:16:50.67$setupk4/"tpicd=stop 2006.145.17:16:50.67$setupk4/"rec=synch_on 2006.145.17:16:50.67$setupk4/"rec_mode=128 2006.145.17:16:50.67$setupk4/!* 2006.145.17:16:50.67$setupk4/recpk4 2006.145.17:16:50.67$recpk4/recpatch= 2006.145.17:16:50.67$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.17:16:50.67$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.17:16:50.67$setupk4/vck44 2006.145.17:16:50.67$vck44/valo=1,524.99 2006.145.17:16:50.67#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.17:16:50.67#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.17:16:50.67#ibcon#ireg 17 cls_cnt 0 2006.145.17:16:50.67#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.17:16:50.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.17:16:50.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.17:16:50.71#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.17:16:50.76#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.17:16:50.76#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.17:16:50.76#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.17:16:50.76#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.17:16:50.76$vck44/va=1,8 2006.145.17:16:50.76#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.17:16:50.76#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.17:16:50.76#ibcon#ireg 11 cls_cnt 2 2006.145.17:16:50.76#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.17:16:50.76#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.17:16:50.76#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.17:16:50.78#ibcon#[25=AT01-08\r\n] 2006.145.17:16:50.81#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.17:16:50.81#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.17:16:50.81#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.17:16:50.81#ibcon#ireg 7 cls_cnt 0 2006.145.17:16:50.81#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.17:16:50.93#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.17:16:50.93#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.17:16:50.95#ibcon#[25=USB\r\n] 2006.145.17:16:50.98#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.17:16:50.98#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.17:16:50.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.17:16:50.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.17:16:50.98$vck44/valo=2,534.99 2006.145.17:16:50.98#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.17:16:50.98#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.17:16:50.98#ibcon#ireg 17 cls_cnt 0 2006.145.17:16:50.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.17:16:50.98#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.17:16:50.98#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.17:16:51.00#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.17:16:51.04#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.17:16:51.04#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.17:16:51.04#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.17:16:51.04#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.17:16:51.04$vck44/va=2,7 2006.145.17:16:51.04#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.17:16:51.04#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.17:16:51.04#ibcon#ireg 11 cls_cnt 2 2006.145.17:16:51.04#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.17:16:51.10#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.17:16:51.10#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.17:16:51.12#ibcon#[25=AT02-07\r\n] 2006.145.17:16:51.15#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.17:16:51.15#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.17:16:51.15#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.17:16:51.15#ibcon#ireg 7 cls_cnt 0 2006.145.17:16:51.15#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.17:16:51.27#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.17:16:51.27#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.17:16:51.29#ibcon#[25=USB\r\n] 2006.145.17:16:51.32#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.17:16:51.32#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.17:16:51.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.17:16:51.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.17:16:51.32$vck44/valo=3,564.99 2006.145.17:16:51.32#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.17:16:51.32#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.17:16:51.32#ibcon#ireg 17 cls_cnt 0 2006.145.17:16:51.32#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.17:16:51.32#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.17:16:51.32#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.17:16:51.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.17:16:51.38#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.17:16:51.38#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.17:16:51.38#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.17:16:51.38#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.17:16:51.38$vck44/va=3,8 2006.145.17:16:51.38#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.17:16:51.38#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.17:16:51.38#ibcon#ireg 11 cls_cnt 2 2006.145.17:16:51.38#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.17:16:51.44#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.17:16:51.44#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.17:16:51.46#ibcon#[25=AT03-08\r\n] 2006.145.17:16:51.49#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.17:16:51.49#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.17:16:51.49#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.17:16:51.49#ibcon#ireg 7 cls_cnt 0 2006.145.17:16:51.49#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.17:16:51.61#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.17:16:51.61#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.17:16:51.63#ibcon#[25=USB\r\n] 2006.145.17:16:51.66#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.17:16:51.66#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.17:16:51.66#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.17:16:51.66#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.17:16:51.66$vck44/valo=4,624.99 2006.145.17:16:51.66#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.17:16:51.66#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.17:16:51.66#ibcon#ireg 17 cls_cnt 0 2006.145.17:16:51.66#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.17:16:51.66#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.17:16:51.66#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.17:16:51.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.17:16:51.72#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.17:16:51.72#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.17:16:51.72#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.17:16:51.72#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.17:16:51.72$vck44/va=4,7 2006.145.17:16:51.72#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.17:16:51.72#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.17:16:51.72#ibcon#ireg 11 cls_cnt 2 2006.145.17:16:51.72#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.17:16:51.78#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.17:16:51.78#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.17:16:51.80#ibcon#[25=AT04-07\r\n] 2006.145.17:16:51.83#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.17:16:51.83#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.17:16:51.83#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.17:16:51.83#ibcon#ireg 7 cls_cnt 0 2006.145.17:16:51.83#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.17:16:51.95#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.17:16:51.95#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.17:16:51.97#ibcon#[25=USB\r\n] 2006.145.17:16:52.00#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.17:16:52.00#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.17:16:52.00#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.17:16:52.00#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.17:16:52.00$vck44/valo=5,734.99 2006.145.17:16:52.00#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.17:16:52.00#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.17:16:52.00#ibcon#ireg 17 cls_cnt 0 2006.145.17:16:52.00#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.17:16:52.00#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.17:16:52.00#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.17:16:52.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.17:16:52.06#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.17:16:52.06#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.17:16:52.06#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.17:16:52.06#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.17:16:52.06$vck44/va=5,4 2006.145.17:16:52.06#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.17:16:52.06#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.17:16:52.06#ibcon#ireg 11 cls_cnt 2 2006.145.17:16:52.06#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.17:16:52.12#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.17:16:52.12#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.17:16:52.14#ibcon#[25=AT05-04\r\n] 2006.145.17:16:52.17#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.17:16:52.17#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.17:16:52.17#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.17:16:52.17#ibcon#ireg 7 cls_cnt 0 2006.145.17:16:52.17#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.17:16:52.29#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.17:16:52.29#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.17:16:52.31#ibcon#[25=USB\r\n] 2006.145.17:16:52.34#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.17:16:52.34#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.17:16:52.34#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.17:16:52.34#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.17:16:52.34$vck44/valo=6,814.99 2006.145.17:16:52.34#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.17:16:52.34#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.17:16:52.34#ibcon#ireg 17 cls_cnt 0 2006.145.17:16:52.34#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.17:16:52.34#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.17:16:52.34#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.17:16:52.36#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.17:16:52.40#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.17:16:52.40#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.17:16:52.40#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.17:16:52.40#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.17:16:52.40$vck44/va=6,4 2006.145.17:16:52.40#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.17:16:52.40#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.17:16:52.40#ibcon#ireg 11 cls_cnt 2 2006.145.17:16:52.40#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.17:16:52.46#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.17:16:52.46#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.17:16:52.48#ibcon#[25=AT06-04\r\n] 2006.145.17:16:52.51#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.17:16:52.51#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.17:16:52.51#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.17:16:52.51#ibcon#ireg 7 cls_cnt 0 2006.145.17:16:52.51#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.17:16:52.63#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.17:16:52.63#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.17:16:52.65#ibcon#[25=USB\r\n] 2006.145.17:16:52.68#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.17:16:52.68#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.17:16:52.68#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.17:16:52.68#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.17:16:52.68$vck44/valo=7,864.99 2006.145.17:16:52.68#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.17:16:52.68#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.17:16:52.68#ibcon#ireg 17 cls_cnt 0 2006.145.17:16:52.68#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.17:16:52.68#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.17:16:52.68#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.17:16:52.70#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.17:16:52.74#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.17:16:52.74#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.17:16:52.74#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.17:16:52.74#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.17:16:52.74$vck44/va=7,4 2006.145.17:16:52.74#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.17:16:52.74#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.17:16:52.74#ibcon#ireg 11 cls_cnt 2 2006.145.17:16:52.74#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.17:16:52.80#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.17:16:52.80#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.17:16:52.82#ibcon#[25=AT07-04\r\n] 2006.145.17:16:52.85#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.17:16:52.85#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.17:16:52.85#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.17:16:52.85#ibcon#ireg 7 cls_cnt 0 2006.145.17:16:52.85#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.17:16:52.97#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.17:16:52.97#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.17:16:52.99#ibcon#[25=USB\r\n] 2006.145.17:16:53.02#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.17:16:53.02#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.17:16:53.02#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.17:16:53.02#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.17:16:53.02$vck44/valo=8,884.99 2006.145.17:16:53.02#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.17:16:53.02#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.17:16:53.02#ibcon#ireg 17 cls_cnt 0 2006.145.17:16:53.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.17:16:53.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.17:16:53.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.17:16:53.04#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.17:16:53.08#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.17:16:53.08#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.17:16:53.08#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.17:16:53.08#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.17:16:53.08$vck44/va=8,4 2006.145.17:16:53.08#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.17:16:53.08#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.17:16:53.08#ibcon#ireg 11 cls_cnt 2 2006.145.17:16:53.08#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.17:16:53.14#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.17:16:53.14#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.17:16:53.16#ibcon#[25=AT08-04\r\n] 2006.145.17:16:53.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.17:16:53.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.17:16:53.19#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.17:16:53.19#ibcon#ireg 7 cls_cnt 0 2006.145.17:16:53.19#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.17:16:53.31#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.17:16:53.31#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.17:16:53.33#ibcon#[25=USB\r\n] 2006.145.17:16:53.36#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.17:16:53.36#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.17:16:53.36#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.17:16:53.36#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.17:16:53.36$vck44/vblo=1,629.99 2006.145.17:16:53.36#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.17:16:53.36#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.17:16:53.36#ibcon#ireg 17 cls_cnt 0 2006.145.17:16:53.36#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.17:16:53.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.17:16:53.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.17:16:53.38#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.17:16:53.42#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.17:16:53.42#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.17:16:53.42#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.17:16:53.42#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.17:16:53.42$vck44/vb=1,3 2006.145.17:16:53.42#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.17:16:53.42#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.17:16:53.42#ibcon#ireg 11 cls_cnt 2 2006.145.17:16:53.42#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.17:16:53.42#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.17:16:53.42#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.17:16:53.44#ibcon#[27=AT01-03\r\n] 2006.145.17:16:53.47#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.17:16:53.47#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.17:16:53.47#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.17:16:53.47#ibcon#ireg 7 cls_cnt 0 2006.145.17:16:53.47#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.17:16:53.59#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.17:16:53.59#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.17:16:53.61#ibcon#[27=USB\r\n] 2006.145.17:16:53.64#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.17:16:53.64#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.17:16:53.64#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.17:16:53.64#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.17:16:53.64$vck44/vblo=2,634.99 2006.145.17:16:53.64#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.17:16:53.64#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.17:16:53.64#ibcon#ireg 17 cls_cnt 0 2006.145.17:16:53.64#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.17:16:53.64#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.17:16:53.64#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.17:16:53.66#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.17:16:53.70#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.17:16:53.70#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.17:16:53.70#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.17:16:53.70#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.17:16:53.70$vck44/vb=2,4 2006.145.17:16:53.70#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.17:16:53.70#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.17:16:53.70#ibcon#ireg 11 cls_cnt 2 2006.145.17:16:53.70#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.17:16:53.76#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.17:16:53.76#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.17:16:53.78#ibcon#[27=AT02-04\r\n] 2006.145.17:16:53.81#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.17:16:53.81#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.17:16:53.81#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.17:16:53.81#ibcon#ireg 7 cls_cnt 0 2006.145.17:16:53.81#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.17:16:53.93#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.17:16:53.93#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.17:16:53.95#ibcon#[27=USB\r\n] 2006.145.17:16:53.98#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.17:16:53.98#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.17:16:53.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.17:16:53.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.17:16:53.98$vck44/vblo=3,649.99 2006.145.17:16:53.98#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.17:16:53.98#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.17:16:53.98#ibcon#ireg 17 cls_cnt 0 2006.145.17:16:53.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.17:16:53.98#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.17:16:53.98#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.17:16:54.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.17:16:54.04#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.17:16:54.04#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.17:16:54.04#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.17:16:54.04#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.17:16:54.04$vck44/vb=3,4 2006.145.17:16:54.04#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.17:16:54.04#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.17:16:54.04#ibcon#ireg 11 cls_cnt 2 2006.145.17:16:54.04#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.17:16:54.10#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.17:16:54.10#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.17:16:54.12#ibcon#[27=AT03-04\r\n] 2006.145.17:16:54.15#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.17:16:54.15#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.17:16:54.15#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.17:16:54.15#ibcon#ireg 7 cls_cnt 0 2006.145.17:16:54.15#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.17:16:54.27#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.17:16:54.27#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.17:16:54.29#ibcon#[27=USB\r\n] 2006.145.17:16:54.32#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.17:16:54.32#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.17:16:54.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.17:16:54.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.17:16:54.32$vck44/vblo=4,679.99 2006.145.17:16:54.32#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.17:16:54.32#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.17:16:54.32#ibcon#ireg 17 cls_cnt 0 2006.145.17:16:54.32#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.17:16:54.32#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.17:16:54.32#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.17:16:54.34#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.17:16:54.38#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.17:16:54.38#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.17:16:54.38#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.17:16:54.38#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.17:16:54.38$vck44/vb=4,4 2006.145.17:16:54.38#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.17:16:54.38#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.17:16:54.38#ibcon#ireg 11 cls_cnt 2 2006.145.17:16:54.38#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.17:16:54.44#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.17:16:54.44#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.17:16:54.46#ibcon#[27=AT04-04\r\n] 2006.145.17:16:54.49#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.17:16:54.49#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.17:16:54.49#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.17:16:54.49#ibcon#ireg 7 cls_cnt 0 2006.145.17:16:54.49#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.17:16:54.61#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.17:16:54.61#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.17:16:54.63#ibcon#[27=USB\r\n] 2006.145.17:16:54.66#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.17:16:54.66#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.17:16:54.66#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.17:16:54.66#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.17:16:54.66$vck44/vblo=5,709.99 2006.145.17:16:54.66#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.17:16:54.66#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.17:16:54.66#ibcon#ireg 17 cls_cnt 0 2006.145.17:16:54.66#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.17:16:54.66#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.17:16:54.66#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.17:16:54.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.17:16:54.72#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.17:16:54.72#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.17:16:54.72#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.17:16:54.72#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.17:16:54.72$vck44/vb=5,4 2006.145.17:16:54.72#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.17:16:54.72#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.17:16:54.72#ibcon#ireg 11 cls_cnt 2 2006.145.17:16:54.72#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.17:16:54.78#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.17:16:54.78#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.17:16:54.80#ibcon#[27=AT05-04\r\n] 2006.145.17:16:54.83#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.17:16:54.83#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.17:16:54.83#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.17:16:54.83#ibcon#ireg 7 cls_cnt 0 2006.145.17:16:54.83#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.17:16:54.95#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.17:16:54.95#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.17:16:54.97#ibcon#[27=USB\r\n] 2006.145.17:16:55.00#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.17:16:55.00#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.17:16:55.00#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.17:16:55.00#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.17:16:55.00$vck44/vblo=6,719.99 2006.145.17:16:55.00#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.17:16:55.00#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.17:16:55.00#ibcon#ireg 17 cls_cnt 0 2006.145.17:16:55.00#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.17:16:55.00#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.17:16:55.00#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.17:16:55.02#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.17:16:55.06#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.17:16:55.06#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.17:16:55.06#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.17:16:55.06#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.17:16:55.06$vck44/vb=6,4 2006.145.17:16:55.06#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.17:16:55.06#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.17:16:55.06#ibcon#ireg 11 cls_cnt 2 2006.145.17:16:55.06#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.17:16:55.12#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.17:16:55.12#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.17:16:55.14#ibcon#[27=AT06-04\r\n] 2006.145.17:16:55.17#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.17:16:55.17#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.17:16:55.17#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.17:16:55.17#ibcon#ireg 7 cls_cnt 0 2006.145.17:16:55.17#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.17:16:55.29#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.17:16:55.29#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.17:16:55.31#ibcon#[27=USB\r\n] 2006.145.17:16:55.34#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.17:16:55.34#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.17:16:55.34#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.17:16:55.34#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.17:16:55.34$vck44/vblo=7,734.99 2006.145.17:16:55.34#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.17:16:55.34#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.17:16:55.34#ibcon#ireg 17 cls_cnt 0 2006.145.17:16:55.34#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.17:16:55.34#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.17:16:55.34#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.17:16:55.36#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.17:16:55.40#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.17:16:55.40#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.17:16:55.40#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.17:16:55.40#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.17:16:55.40$vck44/vb=7,4 2006.145.17:16:55.40#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.17:16:55.40#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.17:16:55.40#ibcon#ireg 11 cls_cnt 2 2006.145.17:16:55.40#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.17:16:55.46#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.17:16:55.46#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.17:16:55.48#ibcon#[27=AT07-04\r\n] 2006.145.17:16:55.51#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.17:16:55.51#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.17:16:55.51#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.17:16:55.51#ibcon#ireg 7 cls_cnt 0 2006.145.17:16:55.51#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.17:16:55.63#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.17:16:55.63#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.17:16:55.65#ibcon#[27=USB\r\n] 2006.145.17:16:55.68#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.17:16:55.68#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.17:16:55.68#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.17:16:55.68#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.17:16:55.68$vck44/vblo=8,744.99 2006.145.17:16:55.68#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.17:16:55.68#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.17:16:55.68#ibcon#ireg 17 cls_cnt 0 2006.145.17:16:55.68#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.17:16:55.68#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.17:16:55.68#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.17:16:55.70#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.17:16:55.74#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.17:16:55.74#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.17:16:55.74#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.17:16:55.74#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.17:16:55.74$vck44/vb=8,4 2006.145.17:16:55.74#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.17:16:55.74#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.17:16:55.74#ibcon#ireg 11 cls_cnt 2 2006.145.17:16:55.74#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.17:16:55.80#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.17:16:55.80#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.17:16:55.82#ibcon#[27=AT08-04\r\n] 2006.145.17:16:55.85#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.17:16:55.85#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.17:16:55.85#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.17:16:55.85#ibcon#ireg 7 cls_cnt 0 2006.145.17:16:55.85#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.17:16:55.97#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.17:16:55.97#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.17:16:55.99#ibcon#[27=USB\r\n] 2006.145.17:16:56.02#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.17:16:56.02#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.17:16:56.02#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.17:16:56.02#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.17:16:56.02$vck44/vabw=wide 2006.145.17:16:56.02#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.17:16:56.02#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.17:16:56.02#ibcon#ireg 8 cls_cnt 0 2006.145.17:16:56.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.17:16:56.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.17:16:56.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.17:16:56.04#ibcon#[25=BW32\r\n] 2006.145.17:16:56.07#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.17:16:56.07#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.17:16:56.07#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.17:16:56.07#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.17:16:56.07$vck44/vbbw=wide 2006.145.17:16:56.07#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.17:16:56.07#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.17:16:56.07#ibcon#ireg 8 cls_cnt 0 2006.145.17:16:56.07#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.17:16:56.14#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.17:16:56.14#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.17:16:56.16#ibcon#[27=BW32\r\n] 2006.145.17:16:56.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.17:16:56.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.17:16:56.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.17:16:56.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.17:16:56.19$setupk4/ifdk4 2006.145.17:16:56.19$ifdk4/lo= 2006.145.17:16:56.19$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.17:16:56.19$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.17:16:56.19$ifdk4/patch= 2006.145.17:16:56.19$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.17:16:56.19$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.17:16:56.19$setupk4/!*+20s 2006.145.17:16:58.46#abcon#<5=/06 0.5 1.1 16.03 881019.7\r\n> 2006.145.17:16:58.48#abcon#{5=INTERFACE CLEAR} 2006.145.17:16:58.54#abcon#[5=S1D000X0/0*\r\n] 2006.145.17:17:01.14#trakl#Source acquired 2006.145.17:17:01.14#flagr#flagr/antenna,acquired 2006.145.17:17:08.63#abcon#<5=/06 0.5 1.1 16.03 881019.7\r\n> 2006.145.17:17:08.65#abcon#{5=INTERFACE CLEAR} 2006.145.17:17:08.71#abcon#[5=S1D000X0/0*\r\n] 2006.145.17:17:10.68$setupk4/"tpicd 2006.145.17:17:10.68$setupk4/echo=off 2006.145.17:17:10.68$setupk4/xlog=off 2006.145.17:17:10.68:!2006.145.17:19:06 2006.145.17:19:06.00:preob 2006.145.17:19:06.13/onsource/TRACKING 2006.145.17:19:06.13:!2006.145.17:19:16 2006.145.17:19:16.00:"tape 2006.145.17:19:16.00:"st=record 2006.145.17:19:16.00:data_valid=on 2006.145.17:19:16.00:midob 2006.145.17:19:16.13/onsource/TRACKING 2006.145.17:19:16.13/wx/16.03,1019.7,88 2006.145.17:19:16.36/cable/+6.5479E-03 2006.145.17:19:17.45/va/01,08,usb,yes,29,31 2006.145.17:19:17.45/va/02,07,usb,yes,31,32 2006.145.17:19:17.45/va/03,08,usb,yes,29,30 2006.145.17:19:17.45/va/04,07,usb,yes,32,34 2006.145.17:19:17.45/va/05,04,usb,yes,28,29 2006.145.17:19:17.45/va/06,04,usb,yes,32,32 2006.145.17:19:17.45/va/07,04,usb,yes,32,33 2006.145.17:19:17.45/va/08,04,usb,yes,27,33 2006.145.17:19:17.68/valo/01,524.99,yes,locked 2006.145.17:19:17.68/valo/02,534.99,yes,locked 2006.145.17:19:17.68/valo/03,564.99,yes,locked 2006.145.17:19:17.68/valo/04,624.99,yes,locked 2006.145.17:19:17.68/valo/05,734.99,yes,locked 2006.145.17:19:17.68/valo/06,814.99,yes,locked 2006.145.17:19:17.68/valo/07,864.99,yes,locked 2006.145.17:19:17.68/valo/08,884.99,yes,locked 2006.145.17:19:18.77/vb/01,03,usb,yes,37,34 2006.145.17:19:18.77/vb/02,04,usb,yes,32,32 2006.145.17:19:18.77/vb/03,04,usb,yes,29,32 2006.145.17:19:18.77/vb/04,04,usb,yes,33,32 2006.145.17:19:18.77/vb/05,04,usb,yes,26,28 2006.145.17:19:18.77/vb/06,04,usb,yes,30,27 2006.145.17:19:18.77/vb/07,04,usb,yes,30,30 2006.145.17:19:18.77/vb/08,04,usb,yes,28,31 2006.145.17:19:19.00/vblo/01,629.99,yes,locked 2006.145.17:19:19.00/vblo/02,634.99,yes,locked 2006.145.17:19:19.00/vblo/03,649.99,yes,locked 2006.145.17:19:19.00/vblo/04,679.99,yes,locked 2006.145.17:19:19.00/vblo/05,709.99,yes,locked 2006.145.17:19:19.00/vblo/06,719.99,yes,locked 2006.145.17:19:19.00/vblo/07,734.99,yes,locked 2006.145.17:19:19.00/vblo/08,744.99,yes,locked 2006.145.17:19:19.15/vabw/8 2006.145.17:19:19.30/vbbw/8 2006.145.17:19:19.39/xfe/off,on,15.5 2006.145.17:19:19.78/ifatt/23,28,28,28 2006.145.17:19:20.07/fmout-gps/S +4.4E-08 2006.145.17:19:20.11:!2006.145.17:19:56 2006.145.17:19:56.01:data_valid=off 2006.145.17:19:56.01:"et 2006.145.17:19:56.02:!+3s 2006.145.17:19:59.03:"tape 2006.145.17:19:59.03:postob 2006.145.17:19:59.10/cable/+6.5486E-03 2006.145.17:19:59.10/wx/16.03,1019.7,88 2006.145.17:19:59.19/fmout-gps/S +4.4E-08 2006.145.17:19:59.19:scan_name=145-1720,jd0605,784 2006.145.17:19:59.19:source=0133+476,013658.59,475129.1,2000.0,cw 2006.145.17:20:01.13#flagr#flagr/antenna,new-source 2006.145.17:20:01.13:checkk5 2006.145.17:20:01.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.17:20:02.04/chk_autoobs//k5ts2/ autoobs is running! 2006.145.17:20:02.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.17:20:02.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.17:20:03.32/chk_obsdata//k5ts1/T1451719??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.17:20:03.76/chk_obsdata//k5ts2/T1451719??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.17:20:04.20/chk_obsdata//k5ts3/T1451719??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.17:20:04.64/chk_obsdata//k5ts4/T1451719??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.17:20:05.41/k5log//k5ts1_log_newline 2006.145.17:20:06.16/k5log//k5ts2_log_newline 2006.145.17:20:06.90/k5log//k5ts3_log_newline 2006.145.17:20:07.65/k5log//k5ts4_log_newline 2006.145.17:20:07.68/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.17:20:07.68:setupk4=1 2006.145.17:20:07.68$setupk4/echo=on 2006.145.17:20:07.68$setupk4/pcalon 2006.145.17:20:07.68$pcalon/"no phase cal control is implemented here 2006.145.17:20:07.68$setupk4/"tpicd=stop 2006.145.17:20:07.68$setupk4/"rec=synch_on 2006.145.17:20:07.68$setupk4/"rec_mode=128 2006.145.17:20:07.68$setupk4/!* 2006.145.17:20:07.68$setupk4/recpk4 2006.145.17:20:07.68$recpk4/recpatch= 2006.145.17:20:07.69$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.17:20:07.69$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.17:20:07.69$setupk4/vck44 2006.145.17:20:07.69$vck44/valo=1,524.99 2006.145.17:20:07.69#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.17:20:07.69#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.17:20:07.69#ibcon#ireg 17 cls_cnt 0 2006.145.17:20:07.69#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.17:20:07.69#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.17:20:07.69#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.17:20:07.72#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.17:20:07.77#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.17:20:07.77#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.17:20:07.77#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.17:20:07.77#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.17:20:07.77$vck44/va=1,8 2006.145.17:20:07.77#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.17:20:07.77#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.17:20:07.77#ibcon#ireg 11 cls_cnt 2 2006.145.17:20:07.77#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.17:20:07.77#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.17:20:07.77#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.17:20:07.79#ibcon#[25=AT01-08\r\n] 2006.145.17:20:07.82#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.17:20:07.82#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.17:20:07.82#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.17:20:07.82#ibcon#ireg 7 cls_cnt 0 2006.145.17:20:07.82#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.17:20:07.94#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.17:20:07.94#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.17:20:07.96#ibcon#[25=USB\r\n] 2006.145.17:20:07.99#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.17:20:07.99#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.17:20:07.99#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.17:20:07.99#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.17:20:07.99$vck44/valo=2,534.99 2006.145.17:20:07.99#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.17:20:07.99#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.17:20:07.99#ibcon#ireg 17 cls_cnt 0 2006.145.17:20:07.99#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.17:20:07.99#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.17:20:07.99#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.17:20:08.02#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.17:20:08.06#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.17:20:08.06#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.17:20:08.06#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.17:20:08.06#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.17:20:08.06$vck44/va=2,7 2006.145.17:20:08.06#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.17:20:08.06#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.17:20:08.06#ibcon#ireg 11 cls_cnt 2 2006.145.17:20:08.06#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.17:20:08.11#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.17:20:08.11#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.17:20:08.14#ibcon#[25=AT02-07\r\n] 2006.145.17:20:08.17#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.17:20:08.17#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.17:20:08.17#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.17:20:08.17#ibcon#ireg 7 cls_cnt 0 2006.145.17:20:08.17#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.17:20:08.29#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.17:20:08.29#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.17:20:08.31#ibcon#[25=USB\r\n] 2006.145.17:20:08.34#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.17:20:08.34#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.17:20:08.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.17:20:08.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.17:20:08.34$vck44/valo=3,564.99 2006.145.17:20:08.34#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.17:20:08.34#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.17:20:08.34#ibcon#ireg 17 cls_cnt 0 2006.145.17:20:08.34#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.17:20:08.34#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.17:20:08.34#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.17:20:08.36#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.17:20:08.40#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.17:20:08.40#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.17:20:08.40#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.17:20:08.40#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.17:20:08.40$vck44/va=3,8 2006.145.17:20:08.40#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.17:20:08.40#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.17:20:08.40#ibcon#ireg 11 cls_cnt 2 2006.145.17:20:08.40#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.17:20:08.46#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.17:20:08.46#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.17:20:08.48#ibcon#[25=AT03-08\r\n] 2006.145.17:20:08.51#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.17:20:08.51#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.17:20:08.51#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.17:20:08.51#ibcon#ireg 7 cls_cnt 0 2006.145.17:20:08.51#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.17:20:08.63#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.17:20:08.63#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.17:20:08.65#ibcon#[25=USB\r\n] 2006.145.17:20:08.68#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.17:20:08.68#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.17:20:08.68#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.17:20:08.68#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.17:20:08.68$vck44/valo=4,624.99 2006.145.17:20:08.68#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.17:20:08.68#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.17:20:08.68#ibcon#ireg 17 cls_cnt 0 2006.145.17:20:08.68#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:20:08.68#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:20:08.68#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:20:08.70#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.17:20:08.74#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:20:08.74#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:20:08.74#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.17:20:08.74#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.17:20:08.74$vck44/va=4,7 2006.145.17:20:08.74#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.17:20:08.74#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.17:20:08.74#ibcon#ireg 11 cls_cnt 2 2006.145.17:20:08.74#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.17:20:08.80#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.17:20:08.80#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.17:20:08.82#ibcon#[25=AT04-07\r\n] 2006.145.17:20:08.85#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.17:20:08.85#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.17:20:08.85#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.17:20:08.85#ibcon#ireg 7 cls_cnt 0 2006.145.17:20:08.85#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.17:20:08.97#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.17:20:08.97#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.17:20:08.99#ibcon#[25=USB\r\n] 2006.145.17:20:09.02#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.17:20:09.02#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.17:20:09.02#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.17:20:09.02#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.17:20:09.02$vck44/valo=5,734.99 2006.145.17:20:09.02#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.17:20:09.02#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.17:20:09.02#ibcon#ireg 17 cls_cnt 0 2006.145.17:20:09.02#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.17:20:09.02#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.17:20:09.02#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.17:20:09.04#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.17:20:09.08#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.17:20:09.08#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.17:20:09.08#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.17:20:09.08#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.17:20:09.08$vck44/va=5,4 2006.145.17:20:09.08#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.17:20:09.08#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.17:20:09.08#ibcon#ireg 11 cls_cnt 2 2006.145.17:20:09.08#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.17:20:09.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.17:20:09.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.17:20:09.18#ibcon#[25=AT05-04\r\n] 2006.145.17:20:09.21#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.17:20:09.21#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.17:20:09.21#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.17:20:09.21#ibcon#ireg 7 cls_cnt 0 2006.145.17:20:09.21#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.17:20:09.35#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.17:20:09.35#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.17:20:09.36#ibcon#[25=USB\r\n] 2006.145.17:20:09.39#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.17:20:09.39#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.17:20:09.39#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.17:20:09.39#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.17:20:09.39$vck44/valo=6,814.99 2006.145.17:20:09.39#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.17:20:09.39#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.17:20:09.39#ibcon#ireg 17 cls_cnt 0 2006.145.17:20:09.39#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.17:20:09.39#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.17:20:09.39#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.17:20:09.42#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.17:20:09.46#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.17:20:09.46#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.17:20:09.46#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.17:20:09.46#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.17:20:09.46$vck44/va=6,4 2006.145.17:20:09.46#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.17:20:09.46#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.17:20:09.46#ibcon#ireg 11 cls_cnt 2 2006.145.17:20:09.46#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.17:20:09.52#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.17:20:09.52#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.17:20:09.54#ibcon#[25=AT06-04\r\n] 2006.145.17:20:09.57#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.17:20:09.57#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.17:20:09.57#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.17:20:09.57#ibcon#ireg 7 cls_cnt 0 2006.145.17:20:09.57#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.17:20:09.69#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.17:20:09.69#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.17:20:09.71#ibcon#[25=USB\r\n] 2006.145.17:20:09.74#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.17:20:09.74#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.17:20:09.74#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.17:20:09.74#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.17:20:09.74$vck44/valo=7,864.99 2006.145.17:20:09.74#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.17:20:09.74#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.17:20:09.74#ibcon#ireg 17 cls_cnt 0 2006.145.17:20:09.74#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.17:20:09.74#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.17:20:09.74#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.17:20:09.76#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.17:20:09.80#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.17:20:09.80#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.17:20:09.80#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.17:20:09.80#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.17:20:09.80$vck44/va=7,4 2006.145.17:20:09.80#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.17:20:09.80#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.17:20:09.80#ibcon#ireg 11 cls_cnt 2 2006.145.17:20:09.80#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.17:20:09.86#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.17:20:09.86#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.17:20:09.88#ibcon#[25=AT07-04\r\n] 2006.145.17:20:09.91#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.17:20:09.91#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.17:20:09.91#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.17:20:09.91#ibcon#ireg 7 cls_cnt 0 2006.145.17:20:09.91#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.17:20:10.03#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.17:20:10.03#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.17:20:10.05#ibcon#[25=USB\r\n] 2006.145.17:20:10.08#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.17:20:10.08#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.17:20:10.08#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.17:20:10.08#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.17:20:10.08$vck44/valo=8,884.99 2006.145.17:20:10.08#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.17:20:10.08#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.17:20:10.08#ibcon#ireg 17 cls_cnt 0 2006.145.17:20:10.08#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.17:20:10.08#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.17:20:10.08#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.17:20:10.10#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.17:20:10.14#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.17:20:10.14#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.17:20:10.14#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.17:20:10.14#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.17:20:10.14$vck44/va=8,4 2006.145.17:20:10.14#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.17:20:10.14#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.17:20:10.14#ibcon#ireg 11 cls_cnt 2 2006.145.17:20:10.14#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.17:20:10.20#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.17:20:10.20#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.17:20:10.22#ibcon#[25=AT08-04\r\n] 2006.145.17:20:10.25#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.17:20:10.25#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.17:20:10.25#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.17:20:10.25#ibcon#ireg 7 cls_cnt 0 2006.145.17:20:10.25#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.17:20:10.37#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.17:20:10.37#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.17:20:10.39#ibcon#[25=USB\r\n] 2006.145.17:20:10.42#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.17:20:10.42#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.17:20:10.42#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.17:20:10.42#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.17:20:10.42$vck44/vblo=1,629.99 2006.145.17:20:10.42#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.17:20:10.42#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.17:20:10.42#ibcon#ireg 17 cls_cnt 0 2006.145.17:20:10.42#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.17:20:10.42#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.17:20:10.42#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.17:20:10.44#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.17:20:10.48#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.17:20:10.48#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.17:20:10.48#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.17:20:10.48#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.17:20:10.48$vck44/vb=1,3 2006.145.17:20:10.48#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.17:20:10.48#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.17:20:10.48#ibcon#ireg 11 cls_cnt 2 2006.145.17:20:10.48#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.17:20:10.48#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.17:20:10.48#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.17:20:10.50#ibcon#[27=AT01-03\r\n] 2006.145.17:20:10.53#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.17:20:10.53#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.17:20:10.53#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.17:20:10.53#ibcon#ireg 7 cls_cnt 0 2006.145.17:20:10.53#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.17:20:10.65#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.17:20:10.65#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.17:20:10.67#ibcon#[27=USB\r\n] 2006.145.17:20:10.70#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.17:20:10.70#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.17:20:10.70#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.17:20:10.70#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.17:20:10.70$vck44/vblo=2,634.99 2006.145.17:20:10.70#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.17:20:10.70#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.17:20:10.70#ibcon#ireg 17 cls_cnt 0 2006.145.17:20:10.70#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.17:20:10.70#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.17:20:10.70#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.17:20:10.72#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.17:20:10.76#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.17:20:10.76#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.17:20:10.76#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.17:20:10.76#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.17:20:10.76$vck44/vb=2,4 2006.145.17:20:10.76#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.17:20:10.76#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.17:20:10.76#ibcon#ireg 11 cls_cnt 2 2006.145.17:20:10.76#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.17:20:10.82#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.17:20:10.82#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.17:20:10.84#ibcon#[27=AT02-04\r\n] 2006.145.17:20:10.87#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.17:20:10.87#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.17:20:10.87#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.17:20:10.87#ibcon#ireg 7 cls_cnt 0 2006.145.17:20:10.87#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.17:20:10.99#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.17:20:10.99#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.17:20:11.01#ibcon#[27=USB\r\n] 2006.145.17:20:11.04#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.17:20:11.04#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.17:20:11.04#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.17:20:11.04#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.17:20:11.04$vck44/vblo=3,649.99 2006.145.17:20:11.04#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.17:20:11.04#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.17:20:11.04#ibcon#ireg 17 cls_cnt 0 2006.145.17:20:11.04#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.17:20:11.04#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.17:20:11.04#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.17:20:11.06#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.17:20:11.10#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.17:20:11.10#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.17:20:11.10#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.17:20:11.10#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.17:20:11.10$vck44/vb=3,4 2006.145.17:20:11.10#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.17:20:11.10#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.17:20:11.10#ibcon#ireg 11 cls_cnt 2 2006.145.17:20:11.10#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.17:20:11.16#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.17:20:11.16#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.17:20:11.18#ibcon#[27=AT03-04\r\n] 2006.145.17:20:11.21#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.17:20:11.21#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.17:20:11.21#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.17:20:11.21#ibcon#ireg 7 cls_cnt 0 2006.145.17:20:11.21#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.17:20:11.33#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.17:20:11.33#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.17:20:11.35#ibcon#[27=USB\r\n] 2006.145.17:20:11.38#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.17:20:11.38#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.17:20:11.38#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.17:20:11.38#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.17:20:11.38$vck44/vblo=4,679.99 2006.145.17:20:11.38#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.17:20:11.38#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.17:20:11.38#ibcon#ireg 17 cls_cnt 0 2006.145.17:20:11.38#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.17:20:11.38#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.17:20:11.38#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.17:20:11.40#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.17:20:11.44#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.17:20:11.44#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.17:20:11.44#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.17:20:11.44#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.17:20:11.44$vck44/vb=4,4 2006.145.17:20:11.44#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.17:20:11.44#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.17:20:11.44#ibcon#ireg 11 cls_cnt 2 2006.145.17:20:11.44#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.17:20:11.50#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.17:20:11.50#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.17:20:11.52#ibcon#[27=AT04-04\r\n] 2006.145.17:20:11.55#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.17:20:11.55#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.17:20:11.55#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.17:20:11.55#ibcon#ireg 7 cls_cnt 0 2006.145.17:20:11.55#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.17:20:11.67#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.17:20:11.67#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.17:20:11.69#ibcon#[27=USB\r\n] 2006.145.17:20:11.72#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.17:20:11.72#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.17:20:11.72#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.17:20:11.72#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.17:20:11.72$vck44/vblo=5,709.99 2006.145.17:20:11.72#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.17:20:11.72#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.17:20:11.72#ibcon#ireg 17 cls_cnt 0 2006.145.17:20:11.72#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:20:11.72#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:20:11.72#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:20:11.74#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.17:20:11.78#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:20:11.78#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:20:11.78#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.17:20:11.78#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.17:20:11.78$vck44/vb=5,4 2006.145.17:20:11.78#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.17:20:11.78#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.17:20:11.78#ibcon#ireg 11 cls_cnt 2 2006.145.17:20:11.78#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.17:20:11.84#abcon#<5=/04 0.4 1.0 16.03 881019.7\r\n> 2006.145.17:20:11.84#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.17:20:11.84#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.17:20:11.86#ibcon#[27=AT05-04\r\n] 2006.145.17:20:11.86#abcon#{5=INTERFACE CLEAR} 2006.145.17:20:11.89#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.17:20:11.89#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.17:20:11.89#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.17:20:11.89#ibcon#ireg 7 cls_cnt 0 2006.145.17:20:11.89#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.17:20:11.92#abcon#[5=S1D000X0/0*\r\n] 2006.145.17:20:12.01#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.17:20:12.01#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.17:20:12.03#ibcon#[27=USB\r\n] 2006.145.17:20:12.06#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.17:20:12.06#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.17:20:12.06#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.17:20:12.06#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.17:20:12.06$vck44/vblo=6,719.99 2006.145.17:20:12.06#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.17:20:12.06#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.17:20:12.06#ibcon#ireg 17 cls_cnt 0 2006.145.17:20:12.06#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.17:20:12.06#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.17:20:12.06#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.17:20:12.08#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.17:20:12.12#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.17:20:12.12#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.17:20:12.12#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.17:20:12.12#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.17:20:12.12$vck44/vb=6,4 2006.145.17:20:12.12#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.17:20:12.12#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.17:20:12.12#ibcon#ireg 11 cls_cnt 2 2006.145.17:20:12.12#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.17:20:12.18#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.17:20:12.18#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.17:20:12.20#ibcon#[27=AT06-04\r\n] 2006.145.17:20:12.23#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.17:20:12.23#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.17:20:12.23#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.17:20:12.23#ibcon#ireg 7 cls_cnt 0 2006.145.17:20:12.23#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.17:20:12.35#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.17:20:12.35#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.17:20:12.37#ibcon#[27=USB\r\n] 2006.145.17:20:12.40#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.17:20:12.40#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.17:20:12.40#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.17:20:12.40#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.17:20:12.40$vck44/vblo=7,734.99 2006.145.17:20:12.40#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.17:20:12.40#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.17:20:12.40#ibcon#ireg 17 cls_cnt 0 2006.145.17:20:12.40#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.17:20:12.40#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.17:20:12.40#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.17:20:12.42#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.17:20:12.46#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.17:20:12.46#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.17:20:12.46#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.17:20:12.46#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.17:20:12.46$vck44/vb=7,4 2006.145.17:20:12.46#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.17:20:12.46#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.17:20:12.46#ibcon#ireg 11 cls_cnt 2 2006.145.17:20:12.46#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.17:20:12.52#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.17:20:12.52#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.17:20:12.54#ibcon#[27=AT07-04\r\n] 2006.145.17:20:12.57#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.17:20:12.57#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.17:20:12.57#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.17:20:12.57#ibcon#ireg 7 cls_cnt 0 2006.145.17:20:12.57#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.17:20:12.69#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.17:20:12.69#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.17:20:12.71#ibcon#[27=USB\r\n] 2006.145.17:20:12.74#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.17:20:12.74#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.17:20:12.74#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.17:20:12.74#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.17:20:12.74$vck44/vblo=8,744.99 2006.145.17:20:12.74#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.17:20:12.74#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.17:20:12.74#ibcon#ireg 17 cls_cnt 0 2006.145.17:20:12.74#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.17:20:12.74#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.17:20:12.74#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.17:20:12.76#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.17:20:12.80#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.17:20:12.80#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.17:20:12.80#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.17:20:12.80#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.17:20:12.80$vck44/vb=8,4 2006.145.17:20:12.80#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.17:20:12.80#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.17:20:12.80#ibcon#ireg 11 cls_cnt 2 2006.145.17:20:12.80#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.17:20:12.86#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.17:20:12.86#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.17:20:12.88#ibcon#[27=AT08-04\r\n] 2006.145.17:20:12.91#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.17:20:12.91#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.17:20:12.91#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.17:20:12.91#ibcon#ireg 7 cls_cnt 0 2006.145.17:20:12.91#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.17:20:13.03#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.17:20:13.03#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.17:20:13.05#ibcon#[27=USB\r\n] 2006.145.17:20:13.08#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.17:20:13.08#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.17:20:13.08#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.17:20:13.08#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.17:20:13.08$vck44/vabw=wide 2006.145.17:20:13.08#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.17:20:13.08#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.17:20:13.08#ibcon#ireg 8 cls_cnt 0 2006.145.17:20:13.08#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.17:20:13.08#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.17:20:13.08#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.17:20:13.10#ibcon#[25=BW32\r\n] 2006.145.17:20:13.13#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.17:20:13.13#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.17:20:13.13#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.17:20:13.13#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.17:20:13.13$vck44/vbbw=wide 2006.145.17:20:13.13#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.17:20:13.13#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.17:20:13.13#ibcon#ireg 8 cls_cnt 0 2006.145.17:20:13.13#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:20:13.20#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:20:13.20#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:20:13.22#ibcon#[27=BW32\r\n] 2006.145.17:20:13.25#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:20:13.25#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:20:13.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.17:20:13.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.17:20:13.25$setupk4/ifdk4 2006.145.17:20:13.25$ifdk4/lo= 2006.145.17:20:13.25$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.17:20:13.25$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.17:20:13.25$ifdk4/patch= 2006.145.17:20:13.25$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.17:20:13.25$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.17:20:13.25$setupk4/!*+20s 2006.145.17:20:22.01#abcon#<5=/04 0.4 0.8 16.03 891019.6\r\n> 2006.145.17:20:22.03#abcon#{5=INTERFACE CLEAR} 2006.145.17:20:22.09#abcon#[5=S1D000X0/0*\r\n] 2006.145.17:20:26.13#trakl#Source acquired 2006.145.17:20:26.13#flagr#flagr/antenna,acquired 2006.145.17:20:27.69$setupk4/"tpicd 2006.145.17:20:27.69$setupk4/echo=off 2006.145.17:20:27.69$setupk4/xlog=off 2006.145.17:20:27.69:!2006.145.17:20:49 2006.145.17:20:49.00:preob 2006.145.17:20:49.14/onsource/TRACKING 2006.145.17:20:49.14:!2006.145.17:20:59 2006.145.17:20:59.00:"tape 2006.145.17:20:59.00:"st=record 2006.145.17:20:59.00:data_valid=on 2006.145.17:20:59.00:midob 2006.145.17:20:59.14/onsource/TRACKING 2006.145.17:20:59.14/wx/16.03,1019.6,89 2006.145.17:20:59.25/cable/+6.5479E-03 2006.145.17:21:00.34/va/01,08,usb,yes,30,32 2006.145.17:21:00.34/va/02,07,usb,yes,32,33 2006.145.17:21:00.34/va/03,08,usb,yes,29,30 2006.145.17:21:00.34/va/04,07,usb,yes,33,35 2006.145.17:21:00.34/va/05,04,usb,yes,29,29 2006.145.17:21:00.34/va/06,04,usb,yes,32,32 2006.145.17:21:00.34/va/07,04,usb,yes,33,34 2006.145.17:21:00.34/va/08,04,usb,yes,28,34 2006.145.17:21:00.57/valo/01,524.99,yes,locked 2006.145.17:21:00.57/valo/02,534.99,yes,locked 2006.145.17:21:00.57/valo/03,564.99,yes,locked 2006.145.17:21:00.57/valo/04,624.99,yes,locked 2006.145.17:21:00.57/valo/05,734.99,yes,locked 2006.145.17:21:00.57/valo/06,814.99,yes,locked 2006.145.17:21:00.57/valo/07,864.99,yes,locked 2006.145.17:21:00.57/valo/08,884.99,yes,locked 2006.145.17:21:01.66/vb/01,03,usb,yes,37,35 2006.145.17:21:01.66/vb/02,04,usb,yes,32,32 2006.145.17:21:01.66/vb/03,04,usb,yes,29,32 2006.145.17:21:01.66/vb/04,04,usb,yes,34,33 2006.145.17:21:01.66/vb/05,04,usb,yes,26,29 2006.145.17:21:01.66/vb/06,04,usb,yes,31,27 2006.145.17:21:01.66/vb/07,04,usb,yes,31,30 2006.145.17:21:01.66/vb/08,04,usb,yes,28,31 2006.145.17:21:01.90/vblo/01,629.99,yes,locked 2006.145.17:21:01.90/vblo/02,634.99,yes,locked 2006.145.17:21:01.90/vblo/03,649.99,yes,locked 2006.145.17:21:01.90/vblo/04,679.99,yes,locked 2006.145.17:21:01.90/vblo/05,709.99,yes,locked 2006.145.17:21:01.90/vblo/06,719.99,yes,locked 2006.145.17:21:01.90/vblo/07,734.99,yes,locked 2006.145.17:21:01.90/vblo/08,744.99,yes,locked 2006.145.17:21:02.05/vabw/8 2006.145.17:21:02.20/vbbw/8 2006.145.17:21:02.29/xfe/off,on,15.2 2006.145.17:21:02.68/ifatt/23,28,28,28 2006.145.17:21:03.07/fmout-gps/S +4.3E-08 2006.145.17:21:03.15:!2006.145.17:34:03 2006.145.17:34:03.00:data_valid=off 2006.145.17:34:03.00:"et 2006.145.17:34:03.00:!+3s 2006.145.17:34:06.02:"tape 2006.145.17:34:06.02:postob 2006.145.17:34:06.09/cable/+6.5491E-03 2006.145.17:34:06.09/wx/15.91,1019.7,89 2006.145.17:34:07.08/fmout-gps/S +4.1E-08 2006.145.17:34:07.08:scan_name=145-1736,jd0605,40 2006.145.17:34:07.08:source=3c345,164258.81,394837.0,2000.0,ccw 2006.145.17:34:08.14#flagr#flagr/antenna,new-source 2006.145.17:34:08.14:checkk5 2006.145.17:34:08.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.17:34:09.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.17:34:09.48/chk_autoobs//k5ts3/ autoobs is running! 2006.145.17:34:09.92/chk_autoobs//k5ts4/ autoobs is running! 2006.145.17:34:10.66/chk_obsdata//k5ts1/T1451720??a.dat file size is correct (nominal:3136MB, actual:3136MB). 2006.145.17:34:11.40/chk_obsdata//k5ts2/T1451720??b.dat file size is correct (nominal:3136MB, actual:3136MB). 2006.145.17:34:12.15/chk_obsdata//k5ts3/T1451720??c.dat file size is correct (nominal:3136MB, actual:3136MB). 2006.145.17:34:12.88/chk_obsdata//k5ts4/T1451720??d.dat file size is correct (nominal:3136MB, actual:3136MB). 2006.145.17:34:13.62/k5log//k5ts1_log_newline 2006.145.17:34:14.35/k5log//k5ts2_log_newline 2006.145.17:34:15.09/k5log//k5ts3_log_newline 2006.145.17:34:15.85/k5log//k5ts4_log_newline 2006.145.17:34:15.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.17:34:15.88:setupk4=1 2006.145.17:34:15.88$setupk4/echo=on 2006.145.17:34:15.88$setupk4/pcalon 2006.145.17:34:15.88$pcalon/"no phase cal control is implemented here 2006.145.17:34:15.88$setupk4/"tpicd=stop 2006.145.17:34:15.88$setupk4/"rec=synch_on 2006.145.17:34:15.88$setupk4/"rec_mode=128 2006.145.17:34:15.88$setupk4/!* 2006.145.17:34:15.88$setupk4/recpk4 2006.145.17:34:15.88$recpk4/recpatch= 2006.145.17:34:15.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.17:34:15.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.17:34:15.88$setupk4/vck44 2006.145.17:34:15.88$vck44/valo=1,524.99 2006.145.17:34:15.88#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.17:34:15.88#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.17:34:15.88#ibcon#ireg 17 cls_cnt 0 2006.145.17:34:15.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.17:34:15.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.17:34:15.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.17:34:15.90#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.17:34:15.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.17:34:15.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.17:34:15.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.17:34:15.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.17:34:15.95$vck44/va=1,8 2006.145.17:34:15.95#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.17:34:15.95#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.17:34:15.95#ibcon#ireg 11 cls_cnt 2 2006.145.17:34:15.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.17:34:15.95#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.17:34:15.95#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.17:34:15.97#ibcon#[25=AT01-08\r\n] 2006.145.17:34:16.00#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.17:34:16.00#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.17:34:16.00#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.17:34:16.00#ibcon#ireg 7 cls_cnt 0 2006.145.17:34:16.00#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.17:34:16.12#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.17:34:16.12#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.17:34:16.14#ibcon#[25=USB\r\n] 2006.145.17:34:16.17#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.17:34:16.17#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.17:34:16.17#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.17:34:16.17#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.17:34:16.17$vck44/valo=2,534.99 2006.145.17:34:16.17#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.17:34:16.17#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.17:34:16.17#ibcon#ireg 17 cls_cnt 0 2006.145.17:34:16.17#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.17:34:16.17#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.17:34:16.17#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.17:34:16.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.17:34:16.24#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.17:34:16.24#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.17:34:16.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.17:34:16.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.17:34:16.24$vck44/va=2,7 2006.145.17:34:16.24#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.17:34:16.24#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.17:34:16.24#ibcon#ireg 11 cls_cnt 2 2006.145.17:34:16.24#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.17:34:16.25#abcon#<5=/04 0.8 1.5 15.91 901019.7\r\n> 2006.145.17:34:16.27#abcon#{5=INTERFACE CLEAR} 2006.145.17:34:16.29#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.17:34:16.29#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.17:34:16.31#ibcon#[25=AT02-07\r\n] 2006.145.17:34:16.33#abcon#[5=S1D000X0/0*\r\n] 2006.145.17:34:16.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.17:34:16.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.17:34:16.34#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.17:34:16.34#ibcon#ireg 7 cls_cnt 0 2006.145.17:34:16.34#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.17:34:16.46#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.17:34:16.46#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.17:34:16.48#ibcon#[25=USB\r\n] 2006.145.17:34:16.51#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.17:34:16.51#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.17:34:16.51#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.17:34:16.51#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.17:34:16.51$vck44/valo=3,564.99 2006.145.17:34:16.51#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.17:34:16.51#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.17:34:16.51#ibcon#ireg 17 cls_cnt 0 2006.145.17:34:16.51#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.17:34:16.51#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.17:34:16.51#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.17:34:16.53#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.17:34:16.57#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.17:34:16.57#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.17:34:16.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.17:34:16.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.17:34:16.57$vck44/va=3,8 2006.145.17:34:16.57#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.17:34:16.57#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.17:34:16.57#ibcon#ireg 11 cls_cnt 2 2006.145.17:34:16.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.17:34:16.63#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.17:34:16.63#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.17:34:16.65#ibcon#[25=AT03-08\r\n] 2006.145.17:34:16.68#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.17:34:16.68#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.17:34:16.68#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.17:34:16.68#ibcon#ireg 7 cls_cnt 0 2006.145.17:34:16.68#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.17:34:16.80#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.17:34:16.80#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.17:34:16.82#ibcon#[25=USB\r\n] 2006.145.17:34:16.85#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.17:34:16.85#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.17:34:16.85#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.17:34:16.85#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.17:34:16.85$vck44/valo=4,624.99 2006.145.17:34:16.85#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.17:34:16.85#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.17:34:16.85#ibcon#ireg 17 cls_cnt 0 2006.145.17:34:16.85#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.17:34:16.85#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.17:34:16.85#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.17:34:16.87#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.17:34:16.91#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.17:34:16.91#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.17:34:16.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.17:34:16.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.17:34:16.91$vck44/va=4,7 2006.145.17:34:16.91#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.17:34:16.91#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.17:34:16.91#ibcon#ireg 11 cls_cnt 2 2006.145.17:34:16.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.17:34:16.97#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.17:34:16.97#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.17:34:16.99#ibcon#[25=AT04-07\r\n] 2006.145.17:34:17.02#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.17:34:17.02#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.17:34:17.02#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.17:34:17.02#ibcon#ireg 7 cls_cnt 0 2006.145.17:34:17.02#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.17:34:17.14#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.17:34:17.14#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.17:34:17.16#ibcon#[25=USB\r\n] 2006.145.17:34:17.19#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.17:34:17.19#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.17:34:17.19#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.17:34:17.19#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.17:34:17.19$vck44/valo=5,734.99 2006.145.17:34:17.19#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.17:34:17.19#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.17:34:17.19#ibcon#ireg 17 cls_cnt 0 2006.145.17:34:17.19#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.17:34:17.19#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.17:34:17.19#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.17:34:17.21#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.17:34:17.25#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.17:34:17.25#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.17:34:17.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.17:34:17.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.17:34:17.25$vck44/va=5,4 2006.145.17:34:17.25#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.17:34:17.25#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.17:34:17.25#ibcon#ireg 11 cls_cnt 2 2006.145.17:34:17.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.17:34:17.31#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.17:34:17.31#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.17:34:17.33#ibcon#[25=AT05-04\r\n] 2006.145.17:34:17.36#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.17:34:17.36#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.17:34:17.36#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.17:34:17.36#ibcon#ireg 7 cls_cnt 0 2006.145.17:34:17.36#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.17:34:17.48#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.17:34:17.48#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.17:34:17.50#ibcon#[25=USB\r\n] 2006.145.17:34:17.53#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.17:34:17.53#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.17:34:17.53#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.17:34:17.53#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.17:34:17.53$vck44/valo=6,814.99 2006.145.17:34:17.53#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.17:34:17.53#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.17:34:17.53#ibcon#ireg 17 cls_cnt 0 2006.145.17:34:17.53#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.17:34:17.53#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.17:34:17.53#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.17:34:17.56#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.17:34:17.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.17:34:17.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.17:34:17.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.17:34:17.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.17:34:17.60$vck44/va=6,4 2006.145.17:34:17.60#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.17:34:17.60#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.17:34:17.60#ibcon#ireg 11 cls_cnt 2 2006.145.17:34:17.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.17:34:17.65#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.17:34:17.65#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.17:34:17.67#ibcon#[25=AT06-04\r\n] 2006.145.17:34:17.70#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.17:34:17.70#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.17:34:17.70#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.17:34:17.70#ibcon#ireg 7 cls_cnt 0 2006.145.17:34:17.70#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.17:34:17.82#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.17:34:17.82#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.17:34:17.84#ibcon#[25=USB\r\n] 2006.145.17:34:17.87#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.17:34:17.87#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.17:34:17.87#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.17:34:17.87#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.17:34:17.87$vck44/valo=7,864.99 2006.145.17:34:17.87#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.17:34:17.87#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.17:34:17.87#ibcon#ireg 17 cls_cnt 0 2006.145.17:34:17.87#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.17:34:17.87#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.17:34:17.87#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.17:34:17.89#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.17:34:17.93#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.17:34:17.93#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.17:34:17.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.17:34:17.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.17:34:17.93$vck44/va=7,4 2006.145.17:34:17.93#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.17:34:17.93#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.17:34:17.93#ibcon#ireg 11 cls_cnt 2 2006.145.17:34:17.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.17:34:17.99#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.17:34:17.99#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.17:34:18.01#ibcon#[25=AT07-04\r\n] 2006.145.17:34:18.04#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.17:34:18.04#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.17:34:18.04#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.17:34:18.04#ibcon#ireg 7 cls_cnt 0 2006.145.17:34:18.04#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.17:34:18.16#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.17:34:18.16#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.17:34:18.18#ibcon#[25=USB\r\n] 2006.145.17:34:18.21#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.17:34:18.21#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.17:34:18.21#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.17:34:18.21#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.17:34:18.21$vck44/valo=8,884.99 2006.145.17:34:18.21#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.17:34:18.21#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.17:34:18.21#ibcon#ireg 17 cls_cnt 0 2006.145.17:34:18.21#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.17:34:18.21#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.17:34:18.21#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.17:34:18.23#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.17:34:18.27#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.17:34:18.27#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.17:34:18.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.17:34:18.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.17:34:18.27$vck44/va=8,4 2006.145.17:34:18.27#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.17:34:18.27#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.17:34:18.27#ibcon#ireg 11 cls_cnt 2 2006.145.17:34:18.27#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.17:34:18.33#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.17:34:18.33#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.17:34:18.35#ibcon#[25=AT08-04\r\n] 2006.145.17:34:18.38#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.17:34:18.38#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.17:34:18.38#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.17:34:18.38#ibcon#ireg 7 cls_cnt 0 2006.145.17:34:18.38#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.17:34:18.50#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.17:34:18.50#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.17:34:18.52#ibcon#[25=USB\r\n] 2006.145.17:34:18.55#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.17:34:18.55#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.17:34:18.55#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.17:34:18.55#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.17:34:18.55$vck44/vblo=1,629.99 2006.145.17:34:18.55#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.17:34:18.55#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.17:34:18.55#ibcon#ireg 17 cls_cnt 0 2006.145.17:34:18.55#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.17:34:18.55#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.17:34:18.55#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.17:34:18.57#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.17:34:18.61#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.17:34:18.61#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.17:34:18.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.17:34:18.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.17:34:18.61$vck44/vb=1,3 2006.145.17:34:18.61#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.17:34:18.61#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.17:34:18.61#ibcon#ireg 11 cls_cnt 2 2006.145.17:34:18.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.17:34:18.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.17:34:18.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.17:34:18.63#ibcon#[27=AT01-03\r\n] 2006.145.17:34:18.66#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.17:34:18.66#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.17:34:18.66#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.17:34:18.66#ibcon#ireg 7 cls_cnt 0 2006.145.17:34:18.66#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.17:34:18.78#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.17:34:18.78#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.17:34:18.80#ibcon#[27=USB\r\n] 2006.145.17:34:18.83#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.17:34:18.83#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.17:34:18.83#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.17:34:18.83#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.17:34:18.83$vck44/vblo=2,634.99 2006.145.17:34:18.83#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.17:34:18.83#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.17:34:18.83#ibcon#ireg 17 cls_cnt 0 2006.145.17:34:18.83#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.17:34:18.83#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.17:34:18.83#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.17:34:18.85#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.17:34:18.89#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.17:34:18.89#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.17:34:18.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.17:34:18.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.17:34:18.89$vck44/vb=2,4 2006.145.17:34:18.89#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.17:34:18.89#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.17:34:18.89#ibcon#ireg 11 cls_cnt 2 2006.145.17:34:18.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.17:34:18.95#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.17:34:18.95#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.17:34:18.97#ibcon#[27=AT02-04\r\n] 2006.145.17:34:19.00#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.17:34:19.00#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.17:34:19.00#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.17:34:19.00#ibcon#ireg 7 cls_cnt 0 2006.145.17:34:19.00#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.17:34:19.12#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.17:34:19.12#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.17:34:19.14#ibcon#[27=USB\r\n] 2006.145.17:34:19.17#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.17:34:19.17#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.17:34:19.17#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.17:34:19.17#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.17:34:19.17$vck44/vblo=3,649.99 2006.145.17:34:19.17#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.17:34:19.17#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.17:34:19.17#ibcon#ireg 17 cls_cnt 0 2006.145.17:34:19.17#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.17:34:19.17#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.17:34:19.17#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.17:34:19.19#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.17:34:19.23#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.17:34:19.23#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.17:34:19.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.17:34:19.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.17:34:19.23$vck44/vb=3,4 2006.145.17:34:19.23#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.17:34:19.23#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.17:34:19.23#ibcon#ireg 11 cls_cnt 2 2006.145.17:34:19.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.17:34:19.29#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.17:34:19.29#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.17:34:19.31#ibcon#[27=AT03-04\r\n] 2006.145.17:34:19.34#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.17:34:19.34#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.17:34:19.34#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.17:34:19.34#ibcon#ireg 7 cls_cnt 0 2006.145.17:34:19.34#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.17:34:19.46#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.17:34:19.46#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.17:34:19.48#ibcon#[27=USB\r\n] 2006.145.17:34:19.51#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.17:34:19.51#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.17:34:19.51#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.17:34:19.51#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.17:34:19.51$vck44/vblo=4,679.99 2006.145.17:34:19.51#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.17:34:19.51#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.17:34:19.51#ibcon#ireg 17 cls_cnt 0 2006.145.17:34:19.51#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.17:34:19.51#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.17:34:19.51#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.17:34:19.53#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.17:34:19.57#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.17:34:19.57#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.17:34:19.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.17:34:19.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.17:34:19.57$vck44/vb=4,4 2006.145.17:34:19.57#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.17:34:19.57#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.17:34:19.57#ibcon#ireg 11 cls_cnt 2 2006.145.17:34:19.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.17:34:19.63#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.17:34:19.63#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.17:34:19.65#ibcon#[27=AT04-04\r\n] 2006.145.17:34:19.68#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.17:34:19.68#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.17:34:19.68#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.17:34:19.68#ibcon#ireg 7 cls_cnt 0 2006.145.17:34:19.68#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.17:34:19.80#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.17:34:19.80#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.17:34:19.82#ibcon#[27=USB\r\n] 2006.145.17:34:19.85#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.17:34:19.85#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.17:34:19.85#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.17:34:19.85#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.17:34:19.85$vck44/vblo=5,709.99 2006.145.17:34:19.85#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.17:34:19.85#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.17:34:19.85#ibcon#ireg 17 cls_cnt 0 2006.145.17:34:19.85#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.17:34:19.85#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.17:34:19.85#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.17:34:19.87#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.17:34:19.91#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.17:34:19.91#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.17:34:19.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.17:34:19.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.17:34:19.91$vck44/vb=5,4 2006.145.17:34:19.91#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.17:34:19.91#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.17:34:19.91#ibcon#ireg 11 cls_cnt 2 2006.145.17:34:19.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.17:34:19.97#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.17:34:19.97#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.17:34:19.99#ibcon#[27=AT05-04\r\n] 2006.145.17:34:20.02#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.17:34:20.02#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.17:34:20.02#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.17:34:20.02#ibcon#ireg 7 cls_cnt 0 2006.145.17:34:20.02#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.17:34:20.14#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.17:34:20.14#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.17:34:20.16#ibcon#[27=USB\r\n] 2006.145.17:34:20.19#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.17:34:20.19#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.17:34:20.19#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.17:34:20.19#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.17:34:20.19$vck44/vblo=6,719.99 2006.145.17:34:20.19#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.17:34:20.19#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.17:34:20.19#ibcon#ireg 17 cls_cnt 0 2006.145.17:34:20.19#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.17:34:20.19#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.17:34:20.19#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.17:34:20.21#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.17:34:20.25#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.17:34:20.25#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.17:34:20.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.17:34:20.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.17:34:20.25$vck44/vb=6,4 2006.145.17:34:20.25#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.17:34:20.25#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.17:34:20.25#ibcon#ireg 11 cls_cnt 2 2006.145.17:34:20.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.17:34:20.31#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.17:34:20.31#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.17:34:20.33#ibcon#[27=AT06-04\r\n] 2006.145.17:34:20.36#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.17:34:20.36#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.17:34:20.36#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.17:34:20.36#ibcon#ireg 7 cls_cnt 0 2006.145.17:34:20.36#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.17:34:20.48#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.17:34:20.48#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.17:34:20.50#ibcon#[27=USB\r\n] 2006.145.17:34:20.53#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.17:34:20.53#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.17:34:20.53#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.17:34:20.53#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.17:34:20.53$vck44/vblo=7,734.99 2006.145.17:34:20.53#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.17:34:20.53#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.17:34:20.53#ibcon#ireg 17 cls_cnt 0 2006.145.17:34:20.53#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.17:34:20.53#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.17:34:20.53#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.17:34:20.55#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.17:34:20.59#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.17:34:20.59#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.17:34:20.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.17:34:20.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.17:34:20.59$vck44/vb=7,4 2006.145.17:34:20.59#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.17:34:20.59#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.17:34:20.59#ibcon#ireg 11 cls_cnt 2 2006.145.17:34:20.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.17:34:20.65#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.17:34:20.65#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.17:34:20.67#ibcon#[27=AT07-04\r\n] 2006.145.17:34:20.70#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.17:34:20.70#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.17:34:20.70#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.17:34:20.70#ibcon#ireg 7 cls_cnt 0 2006.145.17:34:20.70#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.17:34:20.82#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.17:34:20.82#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.17:34:20.84#ibcon#[27=USB\r\n] 2006.145.17:34:20.87#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.17:34:20.87#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.17:34:20.87#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.17:34:20.87#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.17:34:20.87$vck44/vblo=8,744.99 2006.145.17:34:20.87#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.17:34:20.87#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.17:34:20.87#ibcon#ireg 17 cls_cnt 0 2006.145.17:34:20.87#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.17:34:20.87#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.17:34:20.87#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.17:34:20.89#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.17:34:20.93#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.17:34:20.93#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.17:34:20.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.17:34:20.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.17:34:20.93$vck44/vb=8,4 2006.145.17:34:20.93#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.17:34:20.93#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.17:34:20.93#ibcon#ireg 11 cls_cnt 2 2006.145.17:34:20.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.17:34:20.99#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.17:34:20.99#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.17:34:21.01#ibcon#[27=AT08-04\r\n] 2006.145.17:34:21.04#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.17:34:21.04#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.17:34:21.04#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.17:34:21.04#ibcon#ireg 7 cls_cnt 0 2006.145.17:34:21.04#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.17:34:21.16#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.17:34:21.16#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.17:34:21.18#ibcon#[27=USB\r\n] 2006.145.17:34:21.21#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.17:34:21.21#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.17:34:21.21#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.17:34:21.21#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.17:34:21.21$vck44/vabw=wide 2006.145.17:34:21.21#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.17:34:21.21#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.17:34:21.21#ibcon#ireg 8 cls_cnt 0 2006.145.17:34:21.21#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.17:34:21.21#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.17:34:21.21#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.17:34:21.23#ibcon#[25=BW32\r\n] 2006.145.17:34:21.26#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.17:34:21.26#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.17:34:21.26#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.17:34:21.26#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.17:34:21.26$vck44/vbbw=wide 2006.145.17:34:21.26#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.17:34:21.26#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.17:34:21.26#ibcon#ireg 8 cls_cnt 0 2006.145.17:34:21.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.17:34:21.33#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.17:34:21.33#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.17:34:21.35#ibcon#[27=BW32\r\n] 2006.145.17:34:21.38#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.17:34:21.38#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.17:34:21.38#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.17:34:21.38#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.17:34:21.38$setupk4/ifdk4 2006.145.17:34:21.38$ifdk4/lo= 2006.145.17:34:21.38$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.17:34:21.38$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.17:34:21.38$ifdk4/patch= 2006.145.17:34:21.38$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.17:34:21.38$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.17:34:21.38$setupk4/!*+20s 2006.145.17:34:26.42#abcon#<5=/04 0.8 1.5 15.91 901019.7\r\n> 2006.145.17:34:26.44#abcon#{5=INTERFACE CLEAR} 2006.145.17:34:26.52#abcon#[5=S1D000X0/0*\r\n] 2006.145.17:34:35.89$setupk4/"tpicd 2006.145.17:34:35.89$setupk4/echo=off 2006.145.17:34:35.89$setupk4/xlog=off 2006.145.17:34:35.89:!2006.145.17:36:16 2006.145.17:34:54.14#trakl#Source acquired 2006.145.17:34:54.14#flagr#flagr/antenna,acquired 2006.145.17:36:16.00:preob 2006.145.17:36:16.13/onsource/TRACKING 2006.145.17:36:16.13:!2006.145.17:36:26 2006.145.17:36:26.00:"tape 2006.145.17:36:26.00:"st=record 2006.145.17:36:26.00:data_valid=on 2006.145.17:36:26.00:midob 2006.145.17:36:27.13/onsource/TRACKING 2006.145.17:36:27.13/wx/15.89,1019.7,89 2006.145.17:36:27.33/cable/+6.5512E-03 2006.145.17:36:28.42/va/01,08,usb,yes,28,30 2006.145.17:36:28.42/va/02,07,usb,yes,30,31 2006.145.17:36:28.42/va/03,08,usb,yes,27,29 2006.145.17:36:28.42/va/04,07,usb,yes,31,33 2006.145.17:36:28.42/va/05,04,usb,yes,27,28 2006.145.17:36:28.42/va/06,04,usb,yes,30,30 2006.145.17:36:28.42/va/07,04,usb,yes,31,32 2006.145.17:36:28.42/va/08,04,usb,yes,26,32 2006.145.17:36:28.65/valo/01,524.99,yes,locked 2006.145.17:36:28.65/valo/02,534.99,yes,locked 2006.145.17:36:28.65/valo/03,564.99,yes,locked 2006.145.17:36:28.65/valo/04,624.99,yes,locked 2006.145.17:36:28.65/valo/05,734.99,yes,locked 2006.145.17:36:28.65/valo/06,814.99,yes,locked 2006.145.17:36:28.65/valo/07,864.99,yes,locked 2006.145.17:36:28.65/valo/08,884.99,yes,locked 2006.145.17:36:29.74/vb/01,03,usb,yes,35,33 2006.145.17:36:29.74/vb/02,04,usb,yes,31,31 2006.145.17:36:29.74/vb/03,04,usb,yes,28,31 2006.145.17:36:29.74/vb/04,04,usb,yes,32,31 2006.145.17:36:29.74/vb/05,04,usb,yes,25,27 2006.145.17:36:29.74/vb/06,04,usb,yes,29,26 2006.145.17:36:29.74/vb/07,04,usb,yes,29,29 2006.145.17:36:29.74/vb/08,04,usb,yes,27,30 2006.145.17:36:29.98/vblo/01,629.99,yes,locked 2006.145.17:36:29.98/vblo/02,634.99,yes,locked 2006.145.17:36:29.98/vblo/03,649.99,yes,locked 2006.145.17:36:29.98/vblo/04,679.99,yes,locked 2006.145.17:36:29.98/vblo/05,709.99,yes,locked 2006.145.17:36:29.98/vblo/06,719.99,yes,locked 2006.145.17:36:29.98/vblo/07,734.99,yes,locked 2006.145.17:36:29.98/vblo/08,744.99,yes,locked 2006.145.17:36:30.13/vabw/8 2006.145.17:36:30.28/vbbw/8 2006.145.17:36:30.37/xfe/off,on,15.7 2006.145.17:36:30.74/ifatt/23,28,28,28 2006.145.17:36:31.08/fmout-gps/S +4.0E-08 2006.145.17:36:31.12:!2006.145.17:37:06 2006.145.17:37:06.02:data_valid=off 2006.145.17:37:06.02:"et 2006.145.17:37:06.02:!+3s 2006.145.17:37:09.06:"tape 2006.145.17:37:09.06:postob 2006.145.17:37:09.13/cable/+6.5506E-03 2006.145.17:37:09.13/wx/15.89,1019.7,89 2006.145.17:37:09.19/fmout-gps/S +4.1E-08 2006.145.17:37:09.19:scan_name=145-1738,jd0605,90 2006.145.17:37:09.19:source=1908-201,191109.65,-200655.1,2000.0,ccw 2006.145.17:37:11.13#flagr#flagr/antenna,new-source 2006.145.17:37:11.13:checkk5 2006.145.17:37:11.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.17:37:12.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.17:37:12.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.17:37:12.88/chk_autoobs//k5ts4/ autoobs is running! 2006.145.17:37:13.32/chk_obsdata//k5ts1/T1451736??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.17:37:13.75/chk_obsdata//k5ts2/T1451736??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.17:37:14.18/chk_obsdata//k5ts3/T1451736??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.17:37:14.61/chk_obsdata//k5ts4/T1451736??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.17:37:15.38/k5log//k5ts1_log_newline 2006.145.17:37:16.11/k5log//k5ts2_log_newline 2006.145.17:37:16.86/k5log//k5ts3_log_newline 2006.145.17:37:17.60/k5log//k5ts4_log_newline 2006.145.17:37:17.62/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.17:37:17.62:setupk4=1 2006.145.17:37:17.62$setupk4/echo=on 2006.145.17:37:17.62$setupk4/pcalon 2006.145.17:37:17.62$pcalon/"no phase cal control is implemented here 2006.145.17:37:17.62$setupk4/"tpicd=stop 2006.145.17:37:17.62$setupk4/"rec=synch_on 2006.145.17:37:17.62$setupk4/"rec_mode=128 2006.145.17:37:17.62$setupk4/!* 2006.145.17:37:17.62$setupk4/recpk4 2006.145.17:37:17.62$recpk4/recpatch= 2006.145.17:37:17.63$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.17:37:17.63$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.17:37:17.63$setupk4/vck44 2006.145.17:37:17.63$vck44/valo=1,524.99 2006.145.17:37:17.63#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.17:37:17.63#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.17:37:17.63#ibcon#ireg 17 cls_cnt 0 2006.145.17:37:17.63#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:37:17.63#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:37:17.63#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:37:17.66#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.17:37:17.71#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:37:17.71#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:37:17.71#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.17:37:17.71#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.17:37:17.72$vck44/va=1,8 2006.145.17:37:17.72#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.17:37:17.72#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.17:37:17.72#ibcon#ireg 11 cls_cnt 2 2006.145.17:37:17.72#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:37:17.72#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:37:17.72#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:37:17.73#ibcon#[25=AT01-08\r\n] 2006.145.17:37:17.76#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:37:17.76#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:37:17.76#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.17:37:17.77#ibcon#ireg 7 cls_cnt 0 2006.145.17:37:17.77#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:37:17.87#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:37:17.87#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:37:17.91#ibcon#[25=USB\r\n] 2006.145.17:37:17.93#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:37:17.93#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:37:17.93#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.17:37:17.93#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.17:37:17.94$vck44/valo=2,534.99 2006.145.17:37:17.94#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.17:37:17.94#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.17:37:17.94#ibcon#ireg 17 cls_cnt 0 2006.145.17:37:17.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.17:37:17.94#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.17:37:17.94#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.17:37:17.95#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.17:37:17.99#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.17:37:17.99#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.17:37:17.99#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.17:37:17.99#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.17:37:18.00$vck44/va=2,7 2006.145.17:37:18.00#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.17:37:18.00#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.17:37:18.00#ibcon#ireg 11 cls_cnt 2 2006.145.17:37:18.00#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.17:37:18.04#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.17:37:18.04#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.17:37:18.06#ibcon#[25=AT02-07\r\n] 2006.145.17:37:18.09#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.17:37:18.09#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.17:37:18.09#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.17:37:18.09#ibcon#ireg 7 cls_cnt 0 2006.145.17:37:18.09#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.17:37:18.21#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.17:37:18.21#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.17:37:18.23#ibcon#[25=USB\r\n] 2006.145.17:37:18.26#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.17:37:18.26#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.17:37:18.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.17:37:18.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.17:37:18.27$vck44/valo=3,564.99 2006.145.17:37:18.27#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.17:37:18.27#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.17:37:18.27#ibcon#ireg 17 cls_cnt 0 2006.145.17:37:18.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.17:37:18.27#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.17:37:18.27#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.17:37:18.28#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.17:37:18.32#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.17:37:18.32#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.17:37:18.32#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.17:37:18.32#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.17:37:18.33$vck44/va=3,8 2006.145.17:37:18.33#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.17:37:18.33#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.17:37:18.33#ibcon#ireg 11 cls_cnt 2 2006.145.17:37:18.33#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.17:37:18.37#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.17:37:18.37#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.17:37:18.39#ibcon#[25=AT03-08\r\n] 2006.145.17:37:18.42#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.17:37:18.42#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.17:37:18.42#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.17:37:18.42#ibcon#ireg 7 cls_cnt 0 2006.145.17:37:18.42#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.17:37:18.54#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.17:37:18.55#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.17:37:18.56#ibcon#[25=USB\r\n] 2006.145.17:37:18.59#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.17:37:18.59#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.17:37:18.59#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.17:37:18.59#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.17:37:18.60$vck44/valo=4,624.99 2006.145.17:37:18.60#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.17:37:18.60#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.17:37:18.60#ibcon#ireg 17 cls_cnt 0 2006.145.17:37:18.60#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:37:18.60#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:37:18.60#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:37:18.61#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.17:37:18.65#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:37:18.65#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:37:18.65#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.17:37:18.65#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.17:37:18.66$vck44/va=4,7 2006.145.17:37:18.66#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.17:37:18.66#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.17:37:18.66#ibcon#ireg 11 cls_cnt 2 2006.145.17:37:18.66#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:37:18.70#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:37:18.70#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:37:18.72#ibcon#[25=AT04-07\r\n] 2006.145.17:37:18.75#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:37:18.75#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:37:18.75#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.17:37:18.75#ibcon#ireg 7 cls_cnt 0 2006.145.17:37:18.75#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:37:18.87#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:37:18.87#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:37:18.89#ibcon#[25=USB\r\n] 2006.145.17:37:18.92#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:37:18.92#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:37:18.92#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.17:37:18.92#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.17:37:18.93$vck44/valo=5,734.99 2006.145.17:37:18.93#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.17:37:18.93#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.17:37:18.93#ibcon#ireg 17 cls_cnt 0 2006.145.17:37:18.93#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:37:18.93#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:37:18.93#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:37:18.94#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.17:37:18.98#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:37:18.98#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:37:18.98#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.17:37:18.98#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.17:37:18.99$vck44/va=5,4 2006.145.17:37:18.99#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.17:37:18.99#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.17:37:18.99#ibcon#ireg 11 cls_cnt 2 2006.145.17:37:18.99#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:37:19.04#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:37:19.04#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:37:19.06#ibcon#[25=AT05-04\r\n] 2006.145.17:37:19.08#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:37:19.08#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:37:19.08#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.17:37:19.08#ibcon#ireg 7 cls_cnt 0 2006.145.17:37:19.08#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:37:19.20#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:37:19.20#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:37:19.24#ibcon#[25=USB\r\n] 2006.145.17:37:19.26#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:37:19.26#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:37:19.26#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.17:37:19.26#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.17:37:19.27$vck44/valo=6,814.99 2006.145.17:37:19.27#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.17:37:19.27#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.17:37:19.27#ibcon#ireg 17 cls_cnt 0 2006.145.17:37:19.27#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:37:19.27#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:37:19.27#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:37:19.28#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.17:37:19.33#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:37:19.33#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:37:19.33#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.17:37:19.33#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.17:37:19.33$vck44/va=6,4 2006.145.17:37:19.33#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.17:37:19.33#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.17:37:19.33#ibcon#ireg 11 cls_cnt 2 2006.145.17:37:19.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.17:37:19.34#abcon#<5=/04 0.8 1.5 15.88 901019.7\r\n> 2006.145.17:37:19.35#abcon#{5=INTERFACE CLEAR} 2006.145.17:37:19.37#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.17:37:19.37#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.17:37:19.39#ibcon#[25=AT06-04\r\n] 2006.145.17:37:19.41#abcon#[5=S1D000X0/0*\r\n] 2006.145.17:37:19.42#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.17:37:19.42#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.17:37:19.42#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.17:37:19.42#ibcon#ireg 7 cls_cnt 0 2006.145.17:37:19.42#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.17:37:19.54#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.17:37:19.54#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.17:37:19.56#ibcon#[25=USB\r\n] 2006.145.17:37:19.59#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.17:37:19.59#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.17:37:19.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.17:37:19.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.17:37:19.60$vck44/valo=7,864.99 2006.145.17:37:19.60#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.17:37:19.60#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.17:37:19.60#ibcon#ireg 17 cls_cnt 0 2006.145.17:37:19.60#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:37:19.60#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:37:19.60#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:37:19.61#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.17:37:19.65#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:37:19.65#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:37:19.65#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.17:37:19.65#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.17:37:19.66$vck44/va=7,4 2006.145.17:37:19.66#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.17:37:19.66#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.17:37:19.66#ibcon#ireg 11 cls_cnt 2 2006.145.17:37:19.66#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:37:19.70#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:37:19.70#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:37:19.72#ibcon#[25=AT07-04\r\n] 2006.145.17:37:19.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:37:19.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:37:19.75#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.17:37:19.75#ibcon#ireg 7 cls_cnt 0 2006.145.17:37:19.75#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:37:19.87#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:37:19.87#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:37:19.89#ibcon#[25=USB\r\n] 2006.145.17:37:19.92#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:37:19.92#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:37:19.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.17:37:19.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.17:37:19.93$vck44/valo=8,884.99 2006.145.17:37:19.93#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.17:37:19.93#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.17:37:19.93#ibcon#ireg 17 cls_cnt 0 2006.145.17:37:19.93#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:37:19.93#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:37:19.93#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:37:19.94#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.17:37:19.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:37:19.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:37:19.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.17:37:19.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.17:37:19.99$vck44/va=8,4 2006.145.17:37:19.99#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.17:37:19.99#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.17:37:19.99#ibcon#ireg 11 cls_cnt 2 2006.145.17:37:19.99#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.17:37:20.03#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.17:37:20.03#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.17:37:20.05#ibcon#[25=AT08-04\r\n] 2006.145.17:37:20.08#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.17:37:20.08#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.17:37:20.08#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.17:37:20.08#ibcon#ireg 7 cls_cnt 0 2006.145.17:37:20.08#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.17:37:20.20#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.17:37:20.20#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.17:37:20.22#ibcon#[25=USB\r\n] 2006.145.17:37:20.25#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.17:37:20.25#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.17:37:20.25#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.17:37:20.25#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.17:37:20.26$vck44/vblo=1,629.99 2006.145.17:37:20.26#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.17:37:20.26#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.17:37:20.26#ibcon#ireg 17 cls_cnt 0 2006.145.17:37:20.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:37:20.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:37:20.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:37:20.27#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.17:37:20.31#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:37:20.31#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:37:20.31#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.17:37:20.31#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.17:37:20.32$vck44/vb=1,3 2006.145.17:37:20.32#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.17:37:20.32#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.17:37:20.32#ibcon#ireg 11 cls_cnt 2 2006.145.17:37:20.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:37:20.32#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:37:20.32#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:37:20.33#ibcon#[27=AT01-03\r\n] 2006.145.17:37:20.36#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:37:20.36#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:37:20.36#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.17:37:20.36#ibcon#ireg 7 cls_cnt 0 2006.145.17:37:20.36#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:37:20.48#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:37:20.48#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:37:20.50#ibcon#[27=USB\r\n] 2006.145.17:37:20.53#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:37:20.53#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:37:20.53#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.17:37:20.53#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.17:37:20.54$vck44/vblo=2,634.99 2006.145.17:37:20.54#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.17:37:20.54#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.17:37:20.54#ibcon#ireg 17 cls_cnt 0 2006.145.17:37:20.54#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.17:37:20.54#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.17:37:20.54#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.17:37:20.55#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.17:37:20.59#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.17:37:20.59#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.17:37:20.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.17:37:20.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.17:37:20.60$vck44/vb=2,4 2006.145.17:37:20.60#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.17:37:20.60#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.17:37:20.60#ibcon#ireg 11 cls_cnt 2 2006.145.17:37:20.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.17:37:20.65#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.17:37:20.65#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.17:37:20.66#ibcon#[27=AT02-04\r\n] 2006.145.17:37:20.69#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.17:37:20.69#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.17:37:20.69#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.17:37:20.69#ibcon#ireg 7 cls_cnt 0 2006.145.17:37:20.69#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.17:37:20.81#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.17:37:20.81#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.17:37:20.83#ibcon#[27=USB\r\n] 2006.145.17:37:20.86#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.17:37:20.86#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.17:37:20.86#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.17:37:20.86#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.17:37:20.87$vck44/vblo=3,649.99 2006.145.17:37:20.87#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.17:37:20.87#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.17:37:20.87#ibcon#ireg 17 cls_cnt 0 2006.145.17:37:20.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.17:37:20.87#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.17:37:20.87#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.17:37:20.88#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.17:37:20.92#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.17:37:20.92#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.17:37:20.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.17:37:20.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.17:37:20.93$vck44/vb=3,4 2006.145.17:37:20.93#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.17:37:20.93#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.17:37:20.93#ibcon#ireg 11 cls_cnt 2 2006.145.17:37:20.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.17:37:20.97#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.17:37:20.97#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.17:37:20.99#ibcon#[27=AT03-04\r\n] 2006.145.17:37:21.02#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.17:37:21.02#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.17:37:21.02#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.17:37:21.02#ibcon#ireg 7 cls_cnt 0 2006.145.17:37:21.02#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.17:37:21.14#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.17:37:21.14#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.17:37:21.16#ibcon#[27=USB\r\n] 2006.145.17:37:21.19#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.17:37:21.19#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.17:37:21.19#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.17:37:21.19#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.17:37:21.20$vck44/vblo=4,679.99 2006.145.17:37:21.20#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.17:37:21.20#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.17:37:21.20#ibcon#ireg 17 cls_cnt 0 2006.145.17:37:21.20#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:37:21.20#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:37:21.20#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:37:21.21#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.17:37:21.25#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:37:21.25#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:37:21.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.17:37:21.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.17:37:21.26$vck44/vb=4,4 2006.145.17:37:21.26#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.17:37:21.26#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.17:37:21.26#ibcon#ireg 11 cls_cnt 2 2006.145.17:37:21.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:37:21.30#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:37:21.30#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:37:21.32#ibcon#[27=AT04-04\r\n] 2006.145.17:37:21.35#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:37:21.35#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:37:21.35#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.17:37:21.35#ibcon#ireg 7 cls_cnt 0 2006.145.17:37:21.35#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:37:21.47#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:37:21.47#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:37:21.49#ibcon#[27=USB\r\n] 2006.145.17:37:21.52#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:37:21.52#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:37:21.52#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.17:37:21.52#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.17:37:21.53$vck44/vblo=5,709.99 2006.145.17:37:21.53#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.17:37:21.53#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.17:37:21.53#ibcon#ireg 17 cls_cnt 0 2006.145.17:37:21.53#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:37:21.53#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:37:21.53#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:37:21.54#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.17:37:21.58#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:37:21.58#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:37:21.58#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.17:37:21.58#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.17:37:21.59$vck44/vb=5,4 2006.145.17:37:21.59#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.17:37:21.59#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.17:37:21.59#ibcon#ireg 11 cls_cnt 2 2006.145.17:37:21.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:37:21.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:37:21.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:37:21.65#ibcon#[27=AT05-04\r\n] 2006.145.17:37:21.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:37:21.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:37:21.68#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.17:37:21.68#ibcon#ireg 7 cls_cnt 0 2006.145.17:37:21.68#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:37:21.80#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:37:21.80#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:37:21.82#ibcon#[27=USB\r\n] 2006.145.17:37:21.85#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:37:21.85#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:37:21.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.17:37:21.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.17:37:21.86$vck44/vblo=6,719.99 2006.145.17:37:21.86#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.17:37:21.86#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.17:37:21.86#ibcon#ireg 17 cls_cnt 0 2006.145.17:37:21.86#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:37:21.86#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:37:21.86#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:37:21.87#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.17:37:21.91#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:37:21.91#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:37:21.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.17:37:21.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.17:37:21.92$vck44/vb=6,4 2006.145.17:37:21.92#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.17:37:21.92#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.17:37:21.92#ibcon#ireg 11 cls_cnt 2 2006.145.17:37:21.92#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.17:37:21.96#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.17:37:21.96#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.17:37:21.98#ibcon#[27=AT06-04\r\n] 2006.145.17:37:22.01#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.17:37:22.01#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.17:37:22.01#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.17:37:22.01#ibcon#ireg 7 cls_cnt 0 2006.145.17:37:22.01#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.17:37:22.14#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.17:37:22.14#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.17:37:22.15#ibcon#[27=USB\r\n] 2006.145.17:37:22.18#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.17:37:22.18#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.17:37:22.18#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.17:37:22.18#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.17:37:22.19$vck44/vblo=7,734.99 2006.145.17:37:22.19#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.17:37:22.19#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.17:37:22.19#ibcon#ireg 17 cls_cnt 0 2006.145.17:37:22.19#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.17:37:22.19#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.17:37:22.19#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.17:37:22.20#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.17:37:22.24#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.17:37:22.24#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.17:37:22.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.17:37:22.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.17:37:22.25$vck44/vb=7,4 2006.145.17:37:22.25#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.17:37:22.25#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.17:37:22.25#ibcon#ireg 11 cls_cnt 2 2006.145.17:37:22.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.17:37:22.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.17:37:22.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.17:37:22.31#ibcon#[27=AT07-04\r\n] 2006.145.17:37:22.34#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.17:37:22.34#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.17:37:22.34#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.17:37:22.34#ibcon#ireg 7 cls_cnt 0 2006.145.17:37:22.34#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.17:37:22.46#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.17:37:22.46#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.17:37:22.48#ibcon#[27=USB\r\n] 2006.145.17:37:22.51#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.17:37:22.51#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.17:37:22.51#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.17:37:22.51#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.17:37:22.52$vck44/vblo=8,744.99 2006.145.17:37:22.52#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.17:37:22.52#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.17:37:22.52#ibcon#ireg 17 cls_cnt 0 2006.145.17:37:22.52#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:37:22.52#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:37:22.52#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:37:22.53#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.17:37:22.57#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:37:22.57#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:37:22.57#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.17:37:22.57#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.17:37:22.58$vck44/vb=8,4 2006.145.17:37:22.58#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.17:37:22.58#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.17:37:22.58#ibcon#ireg 11 cls_cnt 2 2006.145.17:37:22.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:37:22.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:37:22.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:37:22.64#ibcon#[27=AT08-04\r\n] 2006.145.17:37:22.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:37:22.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:37:22.67#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.17:37:22.67#ibcon#ireg 7 cls_cnt 0 2006.145.17:37:22.67#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:37:22.79#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:37:22.79#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:37:22.81#ibcon#[27=USB\r\n] 2006.145.17:37:22.84#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:37:22.84#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:37:22.84#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.17:37:22.84#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.17:37:22.85$vck44/vabw=wide 2006.145.17:37:22.85#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.17:37:22.85#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.17:37:22.85#ibcon#ireg 8 cls_cnt 0 2006.145.17:37:22.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:37:22.85#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:37:22.85#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:37:22.86#ibcon#[25=BW32\r\n] 2006.145.17:37:22.89#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:37:22.89#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:37:22.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.17:37:22.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.17:37:22.90$vck44/vbbw=wide 2006.145.17:37:22.90#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.17:37:22.90#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.17:37:22.90#ibcon#ireg 8 cls_cnt 0 2006.145.17:37:22.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.17:37:22.95#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.17:37:22.95#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.17:37:22.97#ibcon#[27=BW32\r\n] 2006.145.17:37:23.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.17:37:23.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.17:37:23.00#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.17:37:23.00#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.17:37:23.01$setupk4/ifdk4 2006.145.17:37:23.01$ifdk4/lo= 2006.145.17:37:23.01$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.17:37:23.01$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.17:37:23.01$ifdk4/patch= 2006.145.17:37:23.01$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.17:37:23.01$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.17:37:23.01$setupk4/!*+20s 2006.145.17:37:29.50#abcon#<5=/04 0.8 1.5 15.88 901019.7\r\n> 2006.145.17:37:29.52#abcon#{5=INTERFACE CLEAR} 2006.145.17:37:29.58#abcon#[5=S1D000X0/0*\r\n] 2006.145.17:37:37.64$setupk4/"tpicd 2006.145.17:37:37.65$setupk4/echo=off 2006.145.17:37:37.65$setupk4/xlog=off 2006.145.17:37:37.65:!2006.145.17:38:41 2006.145.17:37:54.14#trakl#Source acquired 2006.145.17:37:54.15#flagr#flagr/antenna,acquired 2006.145.17:38:41.02:preob 2006.145.17:38:42.15/onsource/TRACKING 2006.145.17:38:42.15:!2006.145.17:38:51 2006.145.17:38:51.02:"tape 2006.145.17:38:51.02:"st=record 2006.145.17:38:51.02:data_valid=on 2006.145.17:38:51.02:midob 2006.145.17:38:52.15/onsource/TRACKING 2006.145.17:38:52.15/wx/15.88,1019.7,90 2006.145.17:38:52.32/cable/+6.5496E-03 2006.145.17:38:53.41/va/01,08,usb,yes,29,31 2006.145.17:38:53.41/va/02,07,usb,yes,31,31 2006.145.17:38:53.41/va/03,08,usb,yes,28,29 2006.145.17:38:53.41/va/04,07,usb,yes,32,33 2006.145.17:38:53.41/va/05,04,usb,yes,28,28 2006.145.17:38:53.41/va/06,04,usb,yes,31,31 2006.145.17:38:53.41/va/07,04,usb,yes,31,33 2006.145.17:38:53.41/va/08,04,usb,yes,27,32 2006.145.17:38:53.64/valo/01,524.99,yes,locked 2006.145.17:38:53.64/valo/02,534.99,yes,locked 2006.145.17:38:53.64/valo/03,564.99,yes,locked 2006.145.17:38:53.64/valo/04,624.99,yes,locked 2006.145.17:38:53.64/valo/05,734.99,yes,locked 2006.145.17:38:53.64/valo/06,814.99,yes,locked 2006.145.17:38:53.64/valo/07,864.99,yes,locked 2006.145.17:38:53.64/valo/08,884.99,yes,locked 2006.145.17:38:54.73/vb/01,03,usb,yes,37,34 2006.145.17:38:54.73/vb/02,04,usb,yes,32,32 2006.145.17:38:54.73/vb/03,04,usb,yes,29,32 2006.145.17:38:54.73/vb/04,04,usb,yes,33,32 2006.145.17:38:54.73/vb/05,04,usb,yes,26,28 2006.145.17:38:54.73/vb/06,04,usb,yes,30,26 2006.145.17:38:54.73/vb/07,04,usb,yes,30,29 2006.145.17:38:54.73/vb/08,04,usb,yes,27,31 2006.145.17:38:54.96/vblo/01,629.99,yes,locked 2006.145.17:38:54.96/vblo/02,634.99,yes,locked 2006.145.17:38:54.96/vblo/03,649.99,yes,locked 2006.145.17:38:54.96/vblo/04,679.99,yes,locked 2006.145.17:38:54.96/vblo/05,709.99,yes,locked 2006.145.17:38:54.96/vblo/06,719.99,yes,locked 2006.145.17:38:54.96/vblo/07,734.99,yes,locked 2006.145.17:38:54.96/vblo/08,744.99,yes,locked 2006.145.17:38:55.11/vabw/8 2006.145.17:38:55.26/vbbw/8 2006.145.17:38:55.38/xfe/off,on,14.5 2006.145.17:38:55.77/ifatt/23,28,28,28 2006.145.17:38:56.07/fmout-gps/S +4.0E-08 2006.145.17:38:56.12:!2006.145.17:40:21 2006.145.17:40:21.01:data_valid=off 2006.145.17:40:21.02:"et 2006.145.17:40:21.02:!+3s 2006.145.17:40:24.05:"tape 2006.145.17:40:24.06:postob 2006.145.17:40:24.20/cable/+6.5494E-03 2006.145.17:40:24.21/wx/15.87,1019.7,90 2006.145.17:40:24.26/fmout-gps/S +4.1E-08 2006.145.17:40:24.26:scan_name=145-1744,jd0605,40 2006.145.17:40:24.27:source=1954-388,195800.00,-384506.4,2000.0,ccw 2006.145.17:40:25.14#flagr#flagr/antenna,new-source 2006.145.17:40:25.15:checkk5 2006.145.17:40:25.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.17:40:26.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.17:40:26.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.17:40:26.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.17:40:27.34/chk_obsdata//k5ts1/T1451738??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.17:40:27.77/chk_obsdata//k5ts2/T1451738??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.17:40:28.22/chk_obsdata//k5ts3/T1451738??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.17:40:28.65/chk_obsdata//k5ts4/T1451738??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.17:40:29.42/k5log//k5ts1_log_newline 2006.145.17:40:30.15/k5log//k5ts2_log_newline 2006.145.17:40:30.92/k5log//k5ts3_log_newline 2006.145.17:40:31.68/k5log//k5ts4_log_newline 2006.145.17:40:31.70/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.17:40:31.70:setupk4=1 2006.145.17:40:31.70$setupk4/echo=on 2006.145.17:40:31.70$setupk4/pcalon 2006.145.17:40:31.70$pcalon/"no phase cal control is implemented here 2006.145.17:40:31.70$setupk4/"tpicd=stop 2006.145.17:40:31.70$setupk4/"rec=synch_on 2006.145.17:40:31.70$setupk4/"rec_mode=128 2006.145.17:40:31.70$setupk4/!* 2006.145.17:40:31.70$setupk4/recpk4 2006.145.17:40:31.70$recpk4/recpatch= 2006.145.17:40:31.70$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.17:40:31.71$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.17:40:31.71$setupk4/vck44 2006.145.17:40:31.71$vck44/valo=1,524.99 2006.145.17:40:31.71#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.17:40:31.71#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.17:40:31.71#ibcon#ireg 17 cls_cnt 0 2006.145.17:40:31.71#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.17:40:31.71#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.17:40:31.71#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.17:40:31.74#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.17:40:31.79#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.17:40:31.79#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.17:40:31.79#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.17:40:31.79#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.17:40:31.79$vck44/va=1,8 2006.145.17:40:31.79#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.17:40:31.79#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.17:40:31.79#ibcon#ireg 11 cls_cnt 2 2006.145.17:40:31.79#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.17:40:31.79#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.17:40:31.79#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.17:40:31.81#ibcon#[25=AT01-08\r\n] 2006.145.17:40:31.84#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.17:40:31.84#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.17:40:31.84#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.17:40:31.84#ibcon#ireg 7 cls_cnt 0 2006.145.17:40:31.84#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.17:40:31.96#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.17:40:31.96#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.17:40:31.98#ibcon#[25=USB\r\n] 2006.145.17:40:32.03#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.17:40:32.03#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.17:40:32.03#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.17:40:32.03#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.17:40:32.03$vck44/valo=2,534.99 2006.145.17:40:32.03#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.17:40:32.03#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.17:40:32.03#ibcon#ireg 17 cls_cnt 0 2006.145.17:40:32.03#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.17:40:32.03#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.17:40:32.03#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.17:40:32.05#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.17:40:32.09#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.17:40:32.09#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.17:40:32.09#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.17:40:32.09#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.17:40:32.09$vck44/va=2,7 2006.145.17:40:32.09#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.17:40:32.09#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.17:40:32.09#ibcon#ireg 11 cls_cnt 2 2006.145.17:40:32.09#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.17:40:32.15#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.17:40:32.15#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.17:40:32.17#ibcon#[25=AT02-07\r\n] 2006.145.17:40:32.20#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.17:40:32.20#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.17:40:32.20#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.17:40:32.20#ibcon#ireg 7 cls_cnt 0 2006.145.17:40:32.20#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.17:40:32.32#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.17:40:32.32#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.17:40:32.34#ibcon#[25=USB\r\n] 2006.145.17:40:32.37#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.17:40:32.37#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.17:40:32.37#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.17:40:32.37#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.17:40:32.37$vck44/valo=3,564.99 2006.145.17:40:32.37#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.17:40:32.37#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.17:40:32.37#ibcon#ireg 17 cls_cnt 0 2006.145.17:40:32.37#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.17:40:32.37#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.17:40:32.37#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.17:40:32.39#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.17:40:32.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.17:40:32.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.17:40:32.43#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.17:40:32.43#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.17:40:32.43$vck44/va=3,8 2006.145.17:40:32.43#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.17:40:32.43#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.17:40:32.43#ibcon#ireg 11 cls_cnt 2 2006.145.17:40:32.43#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.17:40:32.49#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.17:40:32.49#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.17:40:32.51#ibcon#[25=AT03-08\r\n] 2006.145.17:40:32.54#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.17:40:32.54#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.17:40:32.54#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.17:40:32.54#ibcon#ireg 7 cls_cnt 0 2006.145.17:40:32.54#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.17:40:32.66#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.17:40:32.66#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.17:40:32.68#ibcon#[25=USB\r\n] 2006.145.17:40:32.68#abcon#<5=/04 0.8 1.5 15.87 901019.7\r\n> 2006.145.17:40:32.70#abcon#{5=INTERFACE CLEAR} 2006.145.17:40:32.71#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.17:40:32.71#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.17:40:32.71#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.17:40:32.71#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.17:40:32.71$vck44/valo=4,624.99 2006.145.17:40:32.71#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.17:40:32.71#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.17:40:32.71#ibcon#ireg 17 cls_cnt 0 2006.145.17:40:32.71#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.17:40:32.71#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.17:40:32.71#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.17:40:32.73#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.17:40:32.76#abcon#[5=S1D000X0/0*\r\n] 2006.145.17:40:32.77#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.17:40:32.77#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.17:40:32.77#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.17:40:32.77#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.17:40:32.77$vck44/va=4,7 2006.145.17:40:32.77#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.17:40:32.77#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.17:40:32.77#ibcon#ireg 11 cls_cnt 2 2006.145.17:40:32.77#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.17:40:32.83#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.17:40:32.83#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.17:40:32.85#ibcon#[25=AT04-07\r\n] 2006.145.17:40:32.88#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.17:40:32.88#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.17:40:32.88#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.17:40:32.88#ibcon#ireg 7 cls_cnt 0 2006.145.17:40:32.88#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.17:40:33.00#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.17:40:33.00#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.17:40:33.02#ibcon#[25=USB\r\n] 2006.145.17:40:33.05#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.17:40:33.05#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.17:40:33.05#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.17:40:33.05#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.17:40:33.05$vck44/valo=5,734.99 2006.145.17:40:33.05#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.17:40:33.05#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.17:40:33.05#ibcon#ireg 17 cls_cnt 0 2006.145.17:40:33.05#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.17:40:33.05#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.17:40:33.05#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.17:40:33.07#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.17:40:33.11#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.17:40:33.11#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.17:40:33.11#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.17:40:33.11#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.17:40:33.11$vck44/va=5,4 2006.145.17:40:33.11#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.17:40:33.11#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.17:40:33.11#ibcon#ireg 11 cls_cnt 2 2006.145.17:40:33.11#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.17:40:33.17#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.17:40:33.17#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.17:40:33.20#ibcon#[25=AT05-04\r\n] 2006.145.17:40:33.22#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.17:40:33.22#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.17:40:33.22#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.17:40:33.22#ibcon#ireg 7 cls_cnt 0 2006.145.17:40:33.22#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.17:40:33.34#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.17:40:33.34#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.17:40:33.36#ibcon#[25=USB\r\n] 2006.145.17:40:33.41#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.17:40:33.41#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.17:40:33.41#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.17:40:33.41#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.17:40:33.41$vck44/valo=6,814.99 2006.145.17:40:33.41#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.17:40:33.41#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.17:40:33.41#ibcon#ireg 17 cls_cnt 0 2006.145.17:40:33.41#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.17:40:33.41#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.17:40:33.41#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.17:40:33.42#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.17:40:33.46#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.17:40:33.46#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.17:40:33.46#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.17:40:33.46#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.17:40:33.46$vck44/va=6,4 2006.145.17:40:33.46#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.17:40:33.46#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.17:40:33.46#ibcon#ireg 11 cls_cnt 2 2006.145.17:40:33.46#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.17:40:33.53#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.17:40:33.53#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.17:40:33.55#ibcon#[25=AT06-04\r\n] 2006.145.17:40:33.58#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.17:40:33.58#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.17:40:33.58#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.17:40:33.58#ibcon#ireg 7 cls_cnt 0 2006.145.17:40:33.58#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.17:40:33.70#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.17:40:33.70#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.17:40:33.72#ibcon#[25=USB\r\n] 2006.145.17:40:33.75#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.17:40:33.75#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.17:40:33.75#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.17:40:33.75#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.17:40:33.75$vck44/valo=7,864.99 2006.145.17:40:33.75#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.17:40:33.75#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.17:40:33.75#ibcon#ireg 17 cls_cnt 0 2006.145.17:40:33.75#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.17:40:33.75#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.17:40:33.75#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.17:40:33.77#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.17:40:33.81#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.17:40:33.81#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.17:40:33.81#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.17:40:33.81#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.17:40:33.81$vck44/va=7,4 2006.145.17:40:33.81#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.17:40:33.81#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.17:40:33.81#ibcon#ireg 11 cls_cnt 2 2006.145.17:40:33.81#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.17:40:33.87#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.17:40:33.87#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.17:40:33.89#ibcon#[25=AT07-04\r\n] 2006.145.17:40:33.92#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.17:40:33.92#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.17:40:33.92#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.17:40:33.92#ibcon#ireg 7 cls_cnt 0 2006.145.17:40:33.92#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.17:40:34.04#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.17:40:34.04#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.17:40:34.06#ibcon#[25=USB\r\n] 2006.145.17:40:34.09#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.17:40:34.09#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.17:40:34.09#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.17:40:34.09#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.17:40:34.09$vck44/valo=8,884.99 2006.145.17:40:34.09#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.17:40:34.09#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.17:40:34.09#ibcon#ireg 17 cls_cnt 0 2006.145.17:40:34.09#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.17:40:34.09#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.17:40:34.09#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.17:40:34.11#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.17:40:34.15#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.17:40:34.15#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.17:40:34.15#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.17:40:34.15#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.17:40:34.15$vck44/va=8,4 2006.145.17:40:34.15#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.17:40:34.15#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.17:40:34.15#ibcon#ireg 11 cls_cnt 2 2006.145.17:40:34.15#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.17:40:34.21#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.17:40:34.21#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.17:40:34.23#ibcon#[25=AT08-04\r\n] 2006.145.17:40:34.26#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.17:40:34.26#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.17:40:34.26#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.17:40:34.26#ibcon#ireg 7 cls_cnt 0 2006.145.17:40:34.26#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.17:40:34.38#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.17:40:34.38#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.17:40:34.40#ibcon#[25=USB\r\n] 2006.145.17:40:34.43#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.17:40:34.43#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.17:40:34.43#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.17:40:34.43#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.17:40:34.43$vck44/vblo=1,629.99 2006.145.17:40:34.43#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.17:40:34.43#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.17:40:34.43#ibcon#ireg 17 cls_cnt 0 2006.145.17:40:34.43#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.17:40:34.43#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.17:40:34.43#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.17:40:34.45#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.17:40:34.49#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.17:40:34.49#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.17:40:34.49#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.17:40:34.49#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.17:40:34.49$vck44/vb=1,3 2006.145.17:40:34.49#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.17:40:34.49#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.17:40:34.49#ibcon#ireg 11 cls_cnt 2 2006.145.17:40:34.49#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.17:40:34.49#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.17:40:34.49#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.17:40:34.51#ibcon#[27=AT01-03\r\n] 2006.145.17:40:34.54#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.17:40:34.54#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.17:40:34.54#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.17:40:34.54#ibcon#ireg 7 cls_cnt 0 2006.145.17:40:34.54#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.17:40:34.67#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.17:40:34.67#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.17:40:34.68#ibcon#[27=USB\r\n] 2006.145.17:40:34.71#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.17:40:34.71#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.17:40:34.71#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.17:40:34.71#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.17:40:34.71$vck44/vblo=2,634.99 2006.145.17:40:34.71#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.17:40:34.71#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.17:40:34.71#ibcon#ireg 17 cls_cnt 0 2006.145.17:40:34.71#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.17:40:34.71#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.17:40:34.71#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.17:40:34.73#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.17:40:34.77#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.17:40:34.77#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.17:40:34.77#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.17:40:34.77#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.17:40:34.77$vck44/vb=2,4 2006.145.17:40:34.77#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.17:40:34.77#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.17:40:34.77#ibcon#ireg 11 cls_cnt 2 2006.145.17:40:34.77#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.17:40:34.83#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.17:40:34.83#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.17:40:34.85#ibcon#[27=AT02-04\r\n] 2006.145.17:40:34.88#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.17:40:34.88#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.17:40:34.88#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.17:40:34.88#ibcon#ireg 7 cls_cnt 0 2006.145.17:40:34.88#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.17:40:35.00#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.17:40:35.00#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.17:40:35.02#ibcon#[27=USB\r\n] 2006.145.17:40:35.05#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.17:40:35.05#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.17:40:35.05#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.17:40:35.05#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.17:40:35.05$vck44/vblo=3,649.99 2006.145.17:40:35.05#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.17:40:35.05#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.17:40:35.05#ibcon#ireg 17 cls_cnt 0 2006.145.17:40:35.05#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.17:40:35.05#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.17:40:35.05#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.17:40:35.07#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.17:40:35.11#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.17:40:35.11#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.17:40:35.11#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.17:40:35.11#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.17:40:35.11$vck44/vb=3,4 2006.145.17:40:35.11#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.17:40:35.11#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.17:40:35.11#ibcon#ireg 11 cls_cnt 2 2006.145.17:40:35.11#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.17:40:35.17#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.17:40:35.17#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.17:40:35.19#ibcon#[27=AT03-04\r\n] 2006.145.17:40:35.22#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.17:40:35.22#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.17:40:35.22#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.17:40:35.22#ibcon#ireg 7 cls_cnt 0 2006.145.17:40:35.22#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.17:40:35.34#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.17:40:35.34#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.17:40:35.36#ibcon#[27=USB\r\n] 2006.145.17:40:35.39#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.17:40:35.39#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.17:40:35.39#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.17:40:35.39#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.17:40:35.39$vck44/vblo=4,679.99 2006.145.17:40:35.39#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.17:40:35.39#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.17:40:35.39#ibcon#ireg 17 cls_cnt 0 2006.145.17:40:35.39#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.17:40:35.39#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.17:40:35.39#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.17:40:35.41#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.17:40:35.45#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.17:40:35.45#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.17:40:35.45#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.17:40:35.45#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.17:40:35.45$vck44/vb=4,4 2006.145.17:40:35.45#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.17:40:35.45#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.17:40:35.45#ibcon#ireg 11 cls_cnt 2 2006.145.17:40:35.45#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.17:40:35.51#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.17:40:35.51#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.17:40:35.53#ibcon#[27=AT04-04\r\n] 2006.145.17:40:35.56#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.17:40:35.56#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.17:40:35.56#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.17:40:35.56#ibcon#ireg 7 cls_cnt 0 2006.145.17:40:35.56#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.17:40:35.68#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.17:40:35.68#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.17:40:35.70#ibcon#[27=USB\r\n] 2006.145.17:40:35.73#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.17:40:35.73#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.17:40:35.73#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.17:40:35.73#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.17:40:35.73$vck44/vblo=5,709.99 2006.145.17:40:35.73#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.17:40:35.73#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.17:40:35.73#ibcon#ireg 17 cls_cnt 0 2006.145.17:40:35.73#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.17:40:35.73#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.17:40:35.73#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.17:40:35.75#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.17:40:35.79#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.17:40:35.79#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.17:40:35.79#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.17:40:35.79#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.17:40:35.79$vck44/vb=5,4 2006.145.17:40:35.79#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.17:40:35.79#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.17:40:35.79#ibcon#ireg 11 cls_cnt 2 2006.145.17:40:35.79#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.17:40:35.85#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.17:40:35.85#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.17:40:35.87#ibcon#[27=AT05-04\r\n] 2006.145.17:40:35.90#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.17:40:35.90#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.17:40:35.90#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.17:40:35.90#ibcon#ireg 7 cls_cnt 0 2006.145.17:40:35.90#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.17:40:36.02#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.17:40:36.02#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.17:40:36.04#ibcon#[27=USB\r\n] 2006.145.17:40:36.07#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.17:40:36.07#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.17:40:36.07#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.17:40:36.07#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.17:40:36.07$vck44/vblo=6,719.99 2006.145.17:40:36.07#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.17:40:36.07#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.17:40:36.07#ibcon#ireg 17 cls_cnt 0 2006.145.17:40:36.07#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.17:40:36.07#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.17:40:36.07#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.17:40:36.09#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.17:40:36.13#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.17:40:36.13#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.17:40:36.13#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.17:40:36.13#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.17:40:36.13$vck44/vb=6,4 2006.145.17:40:36.13#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.17:40:36.13#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.17:40:36.13#ibcon#ireg 11 cls_cnt 2 2006.145.17:40:36.13#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.17:40:36.19#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.17:40:36.19#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.17:40:36.21#ibcon#[27=AT06-04\r\n] 2006.145.17:40:36.24#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.17:40:36.24#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.17:40:36.24#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.17:40:36.24#ibcon#ireg 7 cls_cnt 0 2006.145.17:40:36.24#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.17:40:36.36#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.17:40:36.36#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.17:40:36.38#ibcon#[27=USB\r\n] 2006.145.17:40:36.41#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.17:40:36.41#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.17:40:36.41#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.17:40:36.41#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.17:40:36.41$vck44/vblo=7,734.99 2006.145.17:40:36.41#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.17:40:36.41#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.17:40:36.41#ibcon#ireg 17 cls_cnt 0 2006.145.17:40:36.41#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.17:40:36.41#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.17:40:36.41#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.17:40:36.43#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.17:40:36.47#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.17:40:36.47#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.17:40:36.47#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.17:40:36.47#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.17:40:36.47$vck44/vb=7,4 2006.145.17:40:36.47#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.17:40:36.47#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.17:40:36.47#ibcon#ireg 11 cls_cnt 2 2006.145.17:40:36.47#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.17:40:36.53#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.17:40:36.53#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.17:40:36.55#ibcon#[27=AT07-04\r\n] 2006.145.17:40:36.58#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.17:40:36.58#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.17:40:36.58#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.17:40:36.58#ibcon#ireg 7 cls_cnt 0 2006.145.17:40:36.58#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.17:40:36.70#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.17:40:36.70#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.17:40:36.72#ibcon#[27=USB\r\n] 2006.145.17:40:36.75#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.17:40:36.75#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.17:40:36.75#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.17:40:36.75#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.17:40:36.75$vck44/vblo=8,744.99 2006.145.17:40:36.75#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.17:40:36.75#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.17:40:36.75#ibcon#ireg 17 cls_cnt 0 2006.145.17:40:36.75#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.17:40:36.75#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.17:40:36.75#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.17:40:36.77#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.17:40:36.81#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.17:40:36.81#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.17:40:36.81#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.17:40:36.81#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.17:40:36.81$vck44/vb=8,4 2006.145.17:40:36.81#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.17:40:36.81#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.17:40:36.81#ibcon#ireg 11 cls_cnt 2 2006.145.17:40:36.81#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.17:40:36.87#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.17:40:36.87#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.17:40:36.89#ibcon#[27=AT08-04\r\n] 2006.145.17:40:36.92#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.17:40:36.92#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.17:40:36.92#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.17:40:36.92#ibcon#ireg 7 cls_cnt 0 2006.145.17:40:36.92#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.17:40:37.04#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.17:40:37.04#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.17:40:37.06#ibcon#[27=USB\r\n] 2006.145.17:40:37.09#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.17:40:37.09#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.17:40:37.09#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.17:40:37.09#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.17:40:37.09$vck44/vabw=wide 2006.145.17:40:37.09#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.17:40:37.09#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.17:40:37.09#ibcon#ireg 8 cls_cnt 0 2006.145.17:40:37.09#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.17:40:37.09#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.17:40:37.09#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.17:40:37.11#ibcon#[25=BW32\r\n] 2006.145.17:40:37.14#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.17:40:37.14#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.17:40:37.14#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.17:40:37.14#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.17:40:37.15$vck44/vbbw=wide 2006.145.17:40:37.15#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.17:40:37.15#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.17:40:37.15#ibcon#ireg 8 cls_cnt 0 2006.145.17:40:37.15#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.17:40:37.20#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.17:40:37.20#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.17:40:37.22#ibcon#[27=BW32\r\n] 2006.145.17:40:37.25#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.17:40:37.25#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.17:40:37.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.17:40:37.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.17:40:37.25$setupk4/ifdk4 2006.145.17:40:37.25$ifdk4/lo= 2006.145.17:40:37.25$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.17:40:37.25$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.17:40:37.26$ifdk4/patch= 2006.145.17:40:37.26$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.17:40:37.26$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.17:40:37.26$setupk4/!*+20s 2006.145.17:40:42.85#abcon#<5=/04 0.8 1.5 15.86 901019.7\r\n> 2006.145.17:40:42.87#abcon#{5=INTERFACE CLEAR} 2006.145.17:40:42.93#abcon#[5=S1D000X0/0*\r\n] 2006.145.17:40:44.14#trakl#Source acquired 2006.145.17:40:44.14#flagr#flagr/antenna,acquired 2006.145.17:40:51.72$setupk4/"tpicd 2006.145.17:40:51.72$setupk4/echo=off 2006.145.17:40:51.72$setupk4/xlog=off 2006.145.17:40:51.72:!2006.145.17:44:27 2006.145.17:44:27.00:preob 2006.145.17:44:27.13/onsource/TRACKING 2006.145.17:44:27.13:!2006.145.17:44:37 2006.145.17:44:37.00:"tape 2006.145.17:44:37.00:"st=record 2006.145.17:44:37.00:data_valid=on 2006.145.17:44:37.00:midob 2006.145.17:44:38.13/onsource/TRACKING 2006.145.17:44:38.13/wx/15.83,1019.7,90 2006.145.17:44:38.20/cable/+6.5474E-03 2006.145.17:44:39.29/va/01,08,usb,yes,31,33 2006.145.17:44:39.29/va/02,07,usb,yes,33,34 2006.145.17:44:39.29/va/03,08,usb,yes,30,32 2006.145.17:44:39.29/va/04,07,usb,yes,35,36 2006.145.17:44:39.29/va/05,04,usb,yes,30,31 2006.145.17:44:39.29/va/06,04,usb,yes,34,34 2006.145.17:44:39.29/va/07,04,usb,yes,34,35 2006.145.17:44:39.29/va/08,04,usb,yes,29,35 2006.145.17:44:39.52/valo/01,524.99,yes,locked 2006.145.17:44:39.52/valo/02,534.99,yes,locked 2006.145.17:44:39.52/valo/03,564.99,yes,locked 2006.145.17:44:39.52/valo/04,624.99,yes,locked 2006.145.17:44:39.52/valo/05,734.99,yes,locked 2006.145.17:44:39.52/valo/06,814.99,yes,locked 2006.145.17:44:39.52/valo/07,864.99,yes,locked 2006.145.17:44:39.52/valo/08,884.99,yes,locked 2006.145.17:44:40.61/vb/01,03,usb,yes,37,35 2006.145.17:44:40.61/vb/02,04,usb,yes,33,32 2006.145.17:44:40.61/vb/03,04,usb,yes,30,33 2006.145.17:44:40.61/vb/04,04,usb,yes,34,33 2006.145.17:44:40.61/vb/05,04,usb,yes,27,29 2006.145.17:44:40.61/vb/06,04,usb,yes,31,27 2006.145.17:44:40.61/vb/07,04,usb,yes,31,31 2006.145.17:44:40.61/vb/08,04,usb,yes,28,32 2006.145.17:44:40.85/vblo/01,629.99,yes,locked 2006.145.17:44:40.85/vblo/02,634.99,yes,locked 2006.145.17:44:40.85/vblo/03,649.99,yes,locked 2006.145.17:44:40.85/vblo/04,679.99,yes,locked 2006.145.17:44:40.85/vblo/05,709.99,yes,locked 2006.145.17:44:40.85/vblo/06,719.99,yes,locked 2006.145.17:44:40.85/vblo/07,734.99,yes,locked 2006.145.17:44:40.85/vblo/08,744.99,yes,locked 2006.145.17:44:41.00/vabw/8 2006.145.17:44:41.15/vbbw/8 2006.145.17:44:41.24/xfe/off,on,14.7 2006.145.17:44:41.61/ifatt/23,28,28,28 2006.145.17:44:42.07/fmout-gps/S +4.5E-08 2006.145.17:44:42.11:!2006.145.17:45:17 2006.145.17:45:17.01:data_valid=off 2006.145.17:45:17.02:"et 2006.145.17:45:17.02:!+3s 2006.145.17:45:20.05:"tape 2006.145.17:45:20.06:postob 2006.145.17:45:20.16/cable/+6.5501E-03 2006.145.17:45:20.17/wx/15.82,1019.7,90 2006.145.17:45:20.23/fmout-gps/S +4.5E-08 2006.145.17:45:20.24:scan_name=145-1749,jd0605,40 2006.145.17:45:20.24:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.145.17:45:22.13#flagr#flagr/antenna,new-source 2006.145.17:45:22.14:checkk5 2006.145.17:45:22.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.17:45:23.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.17:45:23.43/chk_autoobs//k5ts3/ autoobs is running! 2006.145.17:45:23.85/chk_autoobs//k5ts4/ autoobs is running! 2006.145.17:45:24.28/chk_obsdata//k5ts1/T1451744??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.17:45:24.71/chk_obsdata//k5ts2/T1451744??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.17:45:25.15/chk_obsdata//k5ts3/T1451744??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.17:45:25.58/chk_obsdata//k5ts4/T1451744??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.17:45:26.35/k5log//k5ts1_log_newline 2006.145.17:45:27.08/k5log//k5ts2_log_newline 2006.145.17:45:27.84/k5log//k5ts3_log_newline 2006.145.17:45:28.58/k5log//k5ts4_log_newline 2006.145.17:45:28.60/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.17:45:28.60:setupk4=1 2006.145.17:45:28.60$setupk4/echo=on 2006.145.17:45:28.60$setupk4/pcalon 2006.145.17:45:28.60$pcalon/"no phase cal control is implemented here 2006.145.17:45:28.60$setupk4/"tpicd=stop 2006.145.17:45:28.60$setupk4/"rec=synch_on 2006.145.17:45:28.60$setupk4/"rec_mode=128 2006.145.17:45:28.60$setupk4/!* 2006.145.17:45:28.60$setupk4/recpk4 2006.145.17:45:28.60$recpk4/recpatch= 2006.145.17:45:28.61$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.17:45:28.61$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.17:45:28.61$setupk4/vck44 2006.145.17:45:28.61$vck44/valo=1,524.99 2006.145.17:45:28.61#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.17:45:28.61#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.17:45:28.61#ibcon#ireg 17 cls_cnt 0 2006.145.17:45:28.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.17:45:28.61#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.17:45:28.61#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.17:45:28.64#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.17:45:28.69#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.17:45:28.69#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.17:45:28.69#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.17:45:28.69#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.17:45:28.69$vck44/va=1,8 2006.145.17:45:28.69#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.17:45:28.69#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.17:45:28.69#ibcon#ireg 11 cls_cnt 2 2006.145.17:45:28.69#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.17:45:28.69#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.17:45:28.69#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.17:45:28.71#ibcon#[25=AT01-08\r\n] 2006.145.17:45:28.74#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.17:45:28.74#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.17:45:28.74#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.17:45:28.74#ibcon#ireg 7 cls_cnt 0 2006.145.17:45:28.74#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.17:45:28.87#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.17:45:28.87#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.17:45:28.88#ibcon#[25=USB\r\n] 2006.145.17:45:28.91#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.17:45:28.91#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.17:45:28.91#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.17:45:28.91#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.17:45:28.91$vck44/valo=2,534.99 2006.145.17:45:28.91#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.17:45:28.91#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.17:45:28.91#ibcon#ireg 17 cls_cnt 0 2006.145.17:45:28.91#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.17:45:28.91#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.17:45:28.91#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.17:45:28.94#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.17:45:28.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.17:45:28.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.17:45:28.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.17:45:28.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.17:45:28.98$vck44/va=2,7 2006.145.17:45:28.98#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.17:45:28.98#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.17:45:28.98#ibcon#ireg 11 cls_cnt 2 2006.145.17:45:28.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.17:45:29.03#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.17:45:29.03#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.17:45:29.05#ibcon#[25=AT02-07\r\n] 2006.145.17:45:29.08#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.17:45:29.08#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.17:45:29.08#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.17:45:29.08#ibcon#ireg 7 cls_cnt 0 2006.145.17:45:29.08#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.17:45:29.20#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.17:45:29.20#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.17:45:29.22#ibcon#[25=USB\r\n] 2006.145.17:45:29.25#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.17:45:29.25#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.17:45:29.25#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.17:45:29.25#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.17:45:29.25$vck44/valo=3,564.99 2006.145.17:45:29.25#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.17:45:29.25#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.17:45:29.25#ibcon#ireg 17 cls_cnt 0 2006.145.17:45:29.25#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.17:45:29.25#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.17:45:29.25#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.17:45:29.27#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.17:45:29.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.17:45:29.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.17:45:29.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.17:45:29.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.17:45:29.31$vck44/va=3,8 2006.145.17:45:29.31#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.17:45:29.31#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.17:45:29.31#ibcon#ireg 11 cls_cnt 2 2006.145.17:45:29.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.17:45:29.37#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.17:45:29.37#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.17:45:29.39#ibcon#[25=AT03-08\r\n] 2006.145.17:45:29.42#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.17:45:29.42#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.17:45:29.42#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.17:45:29.42#ibcon#ireg 7 cls_cnt 0 2006.145.17:45:29.42#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.17:45:29.54#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.17:45:29.54#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.17:45:29.56#ibcon#[25=USB\r\n] 2006.145.17:45:29.59#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.17:45:29.59#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.17:45:29.59#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.17:45:29.59#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.17:45:29.59$vck44/valo=4,624.99 2006.145.17:45:29.59#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.17:45:29.59#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.17:45:29.59#ibcon#ireg 17 cls_cnt 0 2006.145.17:45:29.59#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.17:45:29.59#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.17:45:29.59#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.17:45:29.61#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.17:45:29.65#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.17:45:29.65#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.17:45:29.65#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.17:45:29.65#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.17:45:29.65$vck44/va=4,7 2006.145.17:45:29.65#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.17:45:29.65#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.17:45:29.65#ibcon#ireg 11 cls_cnt 2 2006.145.17:45:29.65#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.17:45:29.71#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.17:45:29.71#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.17:45:29.73#ibcon#[25=AT04-07\r\n] 2006.145.17:45:29.76#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.17:45:29.76#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.17:45:29.76#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.17:45:29.76#ibcon#ireg 7 cls_cnt 0 2006.145.17:45:29.76#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.17:45:29.88#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.17:45:29.88#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.17:45:29.90#ibcon#[25=USB\r\n] 2006.145.17:45:29.93#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.17:45:29.93#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.17:45:29.93#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.17:45:29.93#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.17:45:29.93$vck44/valo=5,734.99 2006.145.17:45:29.93#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.17:45:29.93#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.17:45:29.93#ibcon#ireg 17 cls_cnt 0 2006.145.17:45:29.93#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.17:45:29.93#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.17:45:29.93#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.17:45:29.95#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.17:45:29.99#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.17:45:29.99#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.17:45:29.99#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.17:45:29.99#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.17:45:29.99$vck44/va=5,4 2006.145.17:45:29.99#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.17:45:29.99#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.17:45:29.99#ibcon#ireg 11 cls_cnt 2 2006.145.17:45:29.99#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.17:45:30.05#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.17:45:30.05#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.17:45:30.08#ibcon#[25=AT05-04\r\n] 2006.145.17:45:30.11#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.17:45:30.11#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.17:45:30.11#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.17:45:30.11#ibcon#ireg 7 cls_cnt 0 2006.145.17:45:30.11#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.17:45:30.23#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.17:45:30.23#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.17:45:30.25#ibcon#[25=USB\r\n] 2006.145.17:45:30.28#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.17:45:30.28#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.17:45:30.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.17:45:30.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.17:45:30.28$vck44/valo=6,814.99 2006.145.17:45:30.28#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.17:45:30.28#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.17:45:30.28#ibcon#ireg 17 cls_cnt 0 2006.145.17:45:30.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.17:45:30.28#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.17:45:30.28#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.17:45:30.30#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.17:45:30.34#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.17:45:30.34#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.17:45:30.34#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.17:45:30.34#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.17:45:30.34$vck44/va=6,4 2006.145.17:45:30.34#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.17:45:30.34#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.17:45:30.34#ibcon#ireg 11 cls_cnt 2 2006.145.17:45:30.34#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.17:45:30.40#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.17:45:30.40#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.17:45:30.42#ibcon#[25=AT06-04\r\n] 2006.145.17:45:30.45#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.17:45:30.45#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.17:45:30.45#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.17:45:30.45#ibcon#ireg 7 cls_cnt 0 2006.145.17:45:30.45#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.17:45:30.57#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.17:45:30.57#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.17:45:30.59#ibcon#[25=USB\r\n] 2006.145.17:45:30.62#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.17:45:30.62#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.17:45:30.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.17:45:30.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.17:45:30.62$vck44/valo=7,864.99 2006.145.17:45:30.62#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.17:45:30.62#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.17:45:30.62#ibcon#ireg 17 cls_cnt 0 2006.145.17:45:30.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.17:45:30.62#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.17:45:30.62#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.17:45:30.64#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.17:45:30.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.17:45:30.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.17:45:30.68#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.17:45:30.68#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.17:45:30.68$vck44/va=7,4 2006.145.17:45:30.68#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.17:45:30.68#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.17:45:30.68#ibcon#ireg 11 cls_cnt 2 2006.145.17:45:30.68#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.17:45:30.74#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.17:45:30.74#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.17:45:30.76#ibcon#[25=AT07-04\r\n] 2006.145.17:45:30.79#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.17:45:30.79#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.17:45:30.79#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.17:45:30.79#ibcon#ireg 7 cls_cnt 0 2006.145.17:45:30.79#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.17:45:30.91#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.17:45:30.91#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.17:45:30.93#ibcon#[25=USB\r\n] 2006.145.17:45:30.96#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.17:45:30.96#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.17:45:30.96#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.17:45:30.96#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.17:45:30.96$vck44/valo=8,884.99 2006.145.17:45:30.96#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.17:45:30.96#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.17:45:30.96#ibcon#ireg 17 cls_cnt 0 2006.145.17:45:30.96#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:45:30.96#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:45:30.96#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:45:30.98#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.17:45:31.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:45:31.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:45:31.02#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.17:45:31.02#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.17:45:31.02$vck44/va=8,4 2006.145.17:45:31.02#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.17:45:31.02#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.17:45:31.02#ibcon#ireg 11 cls_cnt 2 2006.145.17:45:31.02#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.17:45:31.08#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.17:45:31.08#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.17:45:31.10#ibcon#[25=AT08-04\r\n] 2006.145.17:45:31.13#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.17:45:31.13#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.17:45:31.13#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.17:45:31.13#ibcon#ireg 7 cls_cnt 0 2006.145.17:45:31.13#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.17:45:31.25#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.17:45:31.25#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.17:45:31.27#ibcon#[25=USB\r\n] 2006.145.17:45:31.30#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.17:45:31.30#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.17:45:31.30#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.17:45:31.30#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.17:45:31.30$vck44/vblo=1,629.99 2006.145.17:45:31.30#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.17:45:31.30#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.17:45:31.30#ibcon#ireg 17 cls_cnt 0 2006.145.17:45:31.30#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.17:45:31.30#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.17:45:31.30#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.17:45:31.33#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.17:45:31.37#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.17:45:31.37#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.17:45:31.37#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.17:45:31.37#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.17:45:31.37$vck44/vb=1,3 2006.145.17:45:31.37#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.17:45:31.37#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.17:45:31.37#ibcon#ireg 11 cls_cnt 2 2006.145.17:45:31.37#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.17:45:31.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.17:45:31.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.17:45:31.39#ibcon#[27=AT01-03\r\n] 2006.145.17:45:31.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.17:45:31.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.17:45:31.43#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.17:45:31.43#ibcon#ireg 7 cls_cnt 0 2006.145.17:45:31.43#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.17:45:31.54#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.17:45:31.54#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.17:45:31.56#ibcon#[27=USB\r\n] 2006.145.17:45:31.59#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.17:45:31.59#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.17:45:31.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.17:45:31.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.17:45:31.59$vck44/vblo=2,634.99 2006.145.17:45:31.59#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.17:45:31.59#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.17:45:31.59#ibcon#ireg 17 cls_cnt 0 2006.145.17:45:31.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.17:45:31.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.17:45:31.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.17:45:31.61#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.17:45:31.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.17:45:31.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.17:45:31.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.17:45:31.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.17:45:31.65$vck44/vb=2,4 2006.145.17:45:31.65#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.17:45:31.65#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.17:45:31.65#ibcon#ireg 11 cls_cnt 2 2006.145.17:45:31.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.17:45:31.71#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.17:45:31.71#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.17:45:31.73#ibcon#[27=AT02-04\r\n] 2006.145.17:45:31.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.17:45:31.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.17:45:31.76#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.17:45:31.76#ibcon#ireg 7 cls_cnt 0 2006.145.17:45:31.76#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.17:45:31.88#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.17:45:31.88#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.17:45:31.90#ibcon#[27=USB\r\n] 2006.145.17:45:31.93#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.17:45:31.93#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.17:45:31.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.17:45:31.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.17:45:31.93$vck44/vblo=3,649.99 2006.145.17:45:31.93#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.17:45:31.93#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.17:45:31.93#ibcon#ireg 17 cls_cnt 0 2006.145.17:45:31.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.17:45:31.93#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.17:45:31.93#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.17:45:31.95#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.17:45:31.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.17:45:31.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.17:45:31.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.17:45:31.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.17:45:31.99$vck44/vb=3,4 2006.145.17:45:31.99#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.17:45:31.99#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.17:45:31.99#ibcon#ireg 11 cls_cnt 2 2006.145.17:45:31.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.17:45:32.05#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.17:45:32.05#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.17:45:32.07#ibcon#[27=AT03-04\r\n] 2006.145.17:45:32.10#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.17:45:32.10#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.17:45:32.10#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.17:45:32.10#ibcon#ireg 7 cls_cnt 0 2006.145.17:45:32.10#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.17:45:32.22#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.17:45:32.22#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.17:45:32.24#ibcon#[27=USB\r\n] 2006.145.17:45:32.27#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.17:45:32.27#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.17:45:32.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.17:45:32.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.17:45:32.27$vck44/vblo=4,679.99 2006.145.17:45:32.27#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.17:45:32.27#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.17:45:32.27#ibcon#ireg 17 cls_cnt 0 2006.145.17:45:32.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.17:45:32.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.17:45:32.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.17:45:32.29#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.17:45:32.33#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.17:45:32.33#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.17:45:32.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.17:45:32.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.17:45:32.33$vck44/vb=4,4 2006.145.17:45:32.33#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.17:45:32.33#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.17:45:32.33#ibcon#ireg 11 cls_cnt 2 2006.145.17:45:32.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.17:45:32.40#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.17:45:32.40#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.17:45:32.42#ibcon#[27=AT04-04\r\n] 2006.145.17:45:32.45#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.17:45:32.45#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.17:45:32.45#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.17:45:32.45#ibcon#ireg 7 cls_cnt 0 2006.145.17:45:32.45#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.17:45:32.57#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.17:45:32.57#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.17:45:32.59#ibcon#[27=USB\r\n] 2006.145.17:45:32.62#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.17:45:32.62#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.17:45:32.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.17:45:32.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.17:45:32.62$vck44/vblo=5,709.99 2006.145.17:45:32.62#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.17:45:32.62#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.17:45:32.62#ibcon#ireg 17 cls_cnt 0 2006.145.17:45:32.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.17:45:32.62#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.17:45:32.62#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.17:45:32.64#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.17:45:32.68#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.17:45:32.68#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.17:45:32.68#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.17:45:32.68#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.17:45:32.68$vck44/vb=5,4 2006.145.17:45:32.68#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.17:45:32.68#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.17:45:32.68#ibcon#ireg 11 cls_cnt 2 2006.145.17:45:32.68#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.17:45:32.74#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.17:45:32.74#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.17:45:32.76#ibcon#[27=AT05-04\r\n] 2006.145.17:45:32.79#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.17:45:32.79#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.17:45:32.79#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.17:45:32.79#ibcon#ireg 7 cls_cnt 0 2006.145.17:45:32.79#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.17:45:32.91#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.17:45:32.91#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.17:45:32.93#ibcon#[27=USB\r\n] 2006.145.17:45:32.96#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.17:45:32.96#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.17:45:32.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.17:45:32.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.17:45:32.96$vck44/vblo=6,719.99 2006.145.17:45:32.96#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.17:45:32.96#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.17:45:32.96#ibcon#ireg 17 cls_cnt 0 2006.145.17:45:32.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.17:45:32.96#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.17:45:32.96#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.17:45:32.98#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.17:45:33.02#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.17:45:33.02#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.17:45:33.02#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.17:45:33.02#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.17:45:33.02$vck44/vb=6,4 2006.145.17:45:33.02#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.17:45:33.02#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.17:45:33.02#ibcon#ireg 11 cls_cnt 2 2006.145.17:45:33.02#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.17:45:33.08#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.17:45:33.08#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.17:45:33.10#ibcon#[27=AT06-04\r\n] 2006.145.17:45:33.13#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.17:45:33.13#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.17:45:33.13#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.17:45:33.13#ibcon#ireg 7 cls_cnt 0 2006.145.17:45:33.13#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.17:45:33.25#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.17:45:33.25#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.17:45:33.27#ibcon#[27=USB\r\n] 2006.145.17:45:33.30#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.17:45:33.30#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.17:45:33.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.17:45:33.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.17:45:33.30$vck44/vblo=7,734.99 2006.145.17:45:33.30#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.17:45:33.30#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.17:45:33.30#ibcon#ireg 17 cls_cnt 0 2006.145.17:45:33.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.17:45:33.30#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.17:45:33.30#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.17:45:33.32#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.17:45:33.36#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.17:45:33.36#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.17:45:33.36#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.17:45:33.36#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.17:45:33.36$vck44/vb=7,4 2006.145.17:45:33.36#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.17:45:33.36#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.17:45:33.36#ibcon#ireg 11 cls_cnt 2 2006.145.17:45:33.36#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.17:45:33.42#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.17:45:33.42#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.17:45:33.44#ibcon#[27=AT07-04\r\n] 2006.145.17:45:33.47#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.17:45:33.47#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.17:45:33.47#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.17:45:33.47#ibcon#ireg 7 cls_cnt 0 2006.145.17:45:33.47#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.17:45:33.59#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.17:45:33.59#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.17:45:33.61#ibcon#[27=USB\r\n] 2006.145.17:45:33.64#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.17:45:33.64#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.17:45:33.64#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.17:45:33.64#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.17:45:33.64$vck44/vblo=8,744.99 2006.145.17:45:33.64#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.17:45:33.64#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.17:45:33.64#ibcon#ireg 17 cls_cnt 0 2006.145.17:45:33.64#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.17:45:33.64#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.17:45:33.64#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.17:45:33.66#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.17:45:33.70#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.17:45:33.70#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.17:45:33.70#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.17:45:33.70#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.17:45:33.70$vck44/vb=8,4 2006.145.17:45:33.70#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.17:45:33.70#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.17:45:33.70#ibcon#ireg 11 cls_cnt 2 2006.145.17:45:33.70#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.17:45:33.76#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.17:45:33.76#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.17:45:33.78#ibcon#[27=AT08-04\r\n] 2006.145.17:45:33.81#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.17:45:33.81#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.17:45:33.81#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.17:45:33.81#ibcon#ireg 7 cls_cnt 0 2006.145.17:45:33.81#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.17:45:33.93#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.17:45:33.93#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.17:45:33.95#ibcon#[27=USB\r\n] 2006.145.17:45:33.98#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.17:45:33.98#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.17:45:33.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.17:45:33.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.17:45:33.98$vck44/vabw=wide 2006.145.17:45:33.98#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.17:45:33.98#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.17:45:33.98#ibcon#ireg 8 cls_cnt 0 2006.145.17:45:33.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:45:33.98#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:45:33.98#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:45:34.00#ibcon#[25=BW32\r\n] 2006.145.17:45:34.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:45:34.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:45:34.03#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.17:45:34.03#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.17:45:34.03$vck44/vbbw=wide 2006.145.17:45:34.03#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.17:45:34.03#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.17:45:34.03#ibcon#ireg 8 cls_cnt 0 2006.145.17:45:34.03#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.17:45:34.10#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.17:45:34.10#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.17:45:34.12#ibcon#[27=BW32\r\n] 2006.145.17:45:34.15#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.17:45:34.15#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.17:45:34.15#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.17:45:34.15#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.17:45:34.15$setupk4/ifdk4 2006.145.17:45:34.15$ifdk4/lo= 2006.145.17:45:34.15$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.17:45:34.15$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.17:45:34.15$ifdk4/patch= 2006.145.17:45:34.15$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.17:45:34.15$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.17:45:34.15$setupk4/!*+20s 2006.145.17:45:37.78#abcon#<5=/04 0.8 1.3 15.82 901019.7\r\n> 2006.145.17:45:37.80#abcon#{5=INTERFACE CLEAR} 2006.145.17:45:37.87#abcon#[5=S1D000X0/0*\r\n] 2006.145.17:45:44.13#trakl#Source acquired 2006.145.17:45:44.13#flagr#flagr/antenna,acquired 2006.145.17:45:47.95#abcon#<5=/04 0.7 1.3 15.82 901019.7\r\n> 2006.145.17:45:47.97#abcon#{5=INTERFACE CLEAR} 2006.145.17:45:48.03#abcon#[5=S1D000X0/0*\r\n] 2006.145.17:45:48.61$setupk4/"tpicd 2006.145.17:45:48.61$setupk4/echo=off 2006.145.17:45:48.61$setupk4/xlog=off 2006.145.17:45:48.61:!2006.145.17:49:23 2006.145.17:49:23.00:preob 2006.145.17:49:24.14/onsource/TRACKING 2006.145.17:49:24.14:!2006.145.17:49:33 2006.145.17:49:33.00:"tape 2006.145.17:49:33.00:"st=record 2006.145.17:49:33.00:data_valid=on 2006.145.17:49:33.00:midob 2006.145.17:49:33.14/onsource/TRACKING 2006.145.17:49:33.14/wx/15.79,1019.6,91 2006.145.17:49:33.32/cable/+6.5503E-03 2006.145.17:49:34.41/va/01,08,usb,yes,29,31 2006.145.17:49:34.41/va/02,07,usb,yes,31,31 2006.145.17:49:34.41/va/03,08,usb,yes,28,29 2006.145.17:49:34.41/va/04,07,usb,yes,32,33 2006.145.17:49:34.41/va/05,04,usb,yes,28,28 2006.145.17:49:34.41/va/06,04,usb,yes,31,31 2006.145.17:49:34.41/va/07,04,usb,yes,31,32 2006.145.17:49:34.41/va/08,04,usb,yes,27,32 2006.145.17:49:34.64/valo/01,524.99,yes,locked 2006.145.17:49:34.64/valo/02,534.99,yes,locked 2006.145.17:49:34.64/valo/03,564.99,yes,locked 2006.145.17:49:34.64/valo/04,624.99,yes,locked 2006.145.17:49:34.64/valo/05,734.99,yes,locked 2006.145.17:49:34.64/valo/06,814.99,yes,locked 2006.145.17:49:34.64/valo/07,864.99,yes,locked 2006.145.17:49:34.64/valo/08,884.99,yes,locked 2006.145.17:49:35.73/vb/01,03,usb,yes,36,34 2006.145.17:49:35.73/vb/02,04,usb,yes,31,31 2006.145.17:49:35.73/vb/03,04,usb,yes,28,31 2006.145.17:49:35.73/vb/04,04,usb,yes,33,32 2006.145.17:49:35.73/vb/05,04,usb,yes,25,28 2006.145.17:49:35.73/vb/06,04,usb,yes,30,26 2006.145.17:49:35.73/vb/07,04,usb,yes,29,29 2006.145.17:49:35.73/vb/08,04,usb,yes,27,30 2006.145.17:49:35.96/vblo/01,629.99,yes,locked 2006.145.17:49:35.96/vblo/02,634.99,yes,locked 2006.145.17:49:35.96/vblo/03,649.99,yes,locked 2006.145.17:49:35.96/vblo/04,679.99,yes,locked 2006.145.17:49:35.96/vblo/05,709.99,yes,locked 2006.145.17:49:35.96/vblo/06,719.99,yes,locked 2006.145.17:49:35.96/vblo/07,734.99,yes,locked 2006.145.17:49:35.96/vblo/08,744.99,yes,locked 2006.145.17:49:36.11/vabw/8 2006.145.17:49:36.26/vbbw/8 2006.145.17:49:36.35/xfe/off,on,15.0 2006.145.17:49:36.73/ifatt/23,28,28,28 2006.145.17:49:37.07/fmout-gps/S +4.3E-08 2006.145.17:49:37.13:!2006.145.17:50:13 2006.145.17:50:13.01:data_valid=off 2006.145.17:50:13.02:"et 2006.145.17:50:13.02:!+3s 2006.145.17:50:16.03:"tape 2006.145.17:50:16.04:postob 2006.145.17:50:16.10/cable/+6.5498E-03 2006.145.17:50:16.11/wx/15.79,1019.6,91 2006.145.17:50:16.16/fmout-gps/S +4.3E-08 2006.145.17:50:16.17:scan_name=145-1752,jd0605,130 2006.145.17:50:16.17:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.145.17:50:18.14#flagr#flagr/antenna,new-source 2006.145.17:50:18.15:checkk5 2006.145.17:50:18.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.17:50:19.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.17:50:19.48/chk_autoobs//k5ts3/ autoobs is running! 2006.145.17:50:19.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.17:50:20.32/chk_obsdata//k5ts1/T1451749??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.17:50:20.78/chk_obsdata//k5ts2/T1451749??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.17:50:21.22/chk_obsdata//k5ts3/T1451749??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.17:50:21.67/chk_obsdata//k5ts4/T1451749??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.17:50:22.45/k5log//k5ts1_log_newline 2006.145.17:50:23.20/k5log//k5ts2_log_newline 2006.145.17:50:23.93/k5log//k5ts3_log_newline 2006.145.17:50:24.67/k5log//k5ts4_log_newline 2006.145.17:50:24.69/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.17:50:24.69:setupk4=1 2006.145.17:50:24.69$setupk4/echo=on 2006.145.17:50:24.69$setupk4/pcalon 2006.145.17:50:24.69$pcalon/"no phase cal control is implemented here 2006.145.17:50:24.69$setupk4/"tpicd=stop 2006.145.17:50:24.69$setupk4/"rec=synch_on 2006.145.17:50:24.69$setupk4/"rec_mode=128 2006.145.17:50:24.69$setupk4/!* 2006.145.17:50:24.69$setupk4/recpk4 2006.145.17:50:24.69$recpk4/recpatch= 2006.145.17:50:24.69$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.17:50:24.69$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.17:50:24.69$setupk4/vck44 2006.145.17:50:24.69$vck44/valo=1,524.99 2006.145.17:50:24.69#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.17:50:24.69#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.17:50:24.69#ibcon#ireg 17 cls_cnt 0 2006.145.17:50:24.69#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.17:50:24.69#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.17:50:24.69#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.17:50:24.74#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.17:50:24.78#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.17:50:24.78#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.17:50:24.78#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.17:50:24.78#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.17:50:24.78$vck44/va=1,8 2006.145.17:50:24.78#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.17:50:24.78#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.17:50:24.78#ibcon#ireg 11 cls_cnt 2 2006.145.17:50:24.78#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.17:50:24.78#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.17:50:24.78#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.17:50:24.80#ibcon#[25=AT01-08\r\n] 2006.145.17:50:24.83#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.17:50:24.83#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.17:50:24.83#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.17:50:24.83#ibcon#ireg 7 cls_cnt 0 2006.145.17:50:24.83#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.17:50:24.96#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.17:50:24.96#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.17:50:24.97#ibcon#[25=USB\r\n] 2006.145.17:50:25.00#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.17:50:25.00#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.17:50:25.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.17:50:25.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.17:50:25.00$vck44/valo=2,534.99 2006.145.17:50:25.00#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.17:50:25.00#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.17:50:25.00#ibcon#ireg 17 cls_cnt 0 2006.145.17:50:25.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.17:50:25.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.17:50:25.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.17:50:25.03#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.17:50:25.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.17:50:25.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.17:50:25.07#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.17:50:25.07#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.17:50:25.07$vck44/va=2,7 2006.145.17:50:25.07#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.17:50:25.07#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.17:50:25.07#ibcon#ireg 11 cls_cnt 2 2006.145.17:50:25.07#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.17:50:25.12#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.17:50:25.12#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.17:50:25.14#ibcon#[25=AT02-07\r\n] 2006.145.17:50:25.17#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.17:50:25.17#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.17:50:25.17#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.17:50:25.17#ibcon#ireg 7 cls_cnt 0 2006.145.17:50:25.17#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.17:50:25.29#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.17:50:25.29#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.17:50:25.31#ibcon#[25=USB\r\n] 2006.145.17:50:25.34#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.17:50:25.34#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.17:50:25.34#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.17:50:25.34#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.17:50:25.34$vck44/valo=3,564.99 2006.145.17:50:25.34#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.17:50:25.34#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.17:50:25.34#ibcon#ireg 17 cls_cnt 0 2006.145.17:50:25.34#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.17:50:25.34#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.17:50:25.34#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.17:50:25.36#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.17:50:25.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.17:50:25.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.17:50:25.40#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.17:50:25.40#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.17:50:25.40$vck44/va=3,8 2006.145.17:50:25.40#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.17:50:25.40#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.17:50:25.40#ibcon#ireg 11 cls_cnt 2 2006.145.17:50:25.40#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.17:50:25.46#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.17:50:25.46#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.17:50:25.48#ibcon#[25=AT03-08\r\n] 2006.145.17:50:25.51#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.17:50:25.51#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.17:50:25.51#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.17:50:25.51#ibcon#ireg 7 cls_cnt 0 2006.145.17:50:25.51#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.17:50:25.63#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.17:50:25.63#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.17:50:25.65#ibcon#[25=USB\r\n] 2006.145.17:50:25.68#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.17:50:25.68#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.17:50:25.68#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.17:50:25.68#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.17:50:25.68$vck44/valo=4,624.99 2006.145.17:50:25.68#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.17:50:25.68#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.17:50:25.68#ibcon#ireg 17 cls_cnt 0 2006.145.17:50:25.68#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.17:50:25.68#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.17:50:25.68#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.17:50:25.70#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.17:50:25.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.17:50:25.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.17:50:25.74#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.17:50:25.74#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.17:50:25.74$vck44/va=4,7 2006.145.17:50:25.74#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.17:50:25.74#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.17:50:25.74#ibcon#ireg 11 cls_cnt 2 2006.145.17:50:25.74#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.17:50:25.80#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.17:50:25.80#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.17:50:25.82#ibcon#[25=AT04-07\r\n] 2006.145.17:50:25.85#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.17:50:25.85#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.17:50:25.85#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.17:50:25.85#ibcon#ireg 7 cls_cnt 0 2006.145.17:50:25.85#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.17:50:25.97#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.17:50:25.97#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.17:50:25.99#ibcon#[25=USB\r\n] 2006.145.17:50:26.02#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.17:50:26.02#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.17:50:26.02#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.17:50:26.02#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.17:50:26.02$vck44/valo=5,734.99 2006.145.17:50:26.02#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.17:50:26.02#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.17:50:26.02#ibcon#ireg 17 cls_cnt 0 2006.145.17:50:26.02#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.17:50:26.02#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.17:50:26.02#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.17:50:26.04#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.17:50:26.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.17:50:26.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.17:50:26.08#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.17:50:26.08#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.17:50:26.08$vck44/va=5,4 2006.145.17:50:26.08#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.17:50:26.08#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.17:50:26.08#ibcon#ireg 11 cls_cnt 2 2006.145.17:50:26.08#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.17:50:26.14#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.17:50:26.14#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.17:50:26.17#ibcon#[25=AT05-04\r\n] 2006.145.17:50:26.20#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.17:50:26.20#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.17:50:26.20#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.17:50:26.20#ibcon#ireg 7 cls_cnt 0 2006.145.17:50:26.20#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.17:50:26.32#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.17:50:26.32#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.17:50:26.34#ibcon#[25=USB\r\n] 2006.145.17:50:26.37#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.17:50:26.37#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.17:50:26.37#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.17:50:26.37#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.17:50:26.37$vck44/valo=6,814.99 2006.145.17:50:26.37#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.17:50:26.37#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.17:50:26.37#ibcon#ireg 17 cls_cnt 0 2006.145.17:50:26.37#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.17:50:26.37#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.17:50:26.37#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.17:50:26.39#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.17:50:26.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.17:50:26.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.17:50:26.43#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.17:50:26.43#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.17:50:26.43$vck44/va=6,4 2006.145.17:50:26.43#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.17:50:26.43#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.17:50:26.43#ibcon#ireg 11 cls_cnt 2 2006.145.17:50:26.43#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.17:50:26.49#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.17:50:26.49#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.17:50:26.51#ibcon#[25=AT06-04\r\n] 2006.145.17:50:26.54#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.17:50:26.54#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.17:50:26.54#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.17:50:26.54#ibcon#ireg 7 cls_cnt 0 2006.145.17:50:26.54#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.17:50:26.66#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.17:50:26.66#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.17:50:26.68#ibcon#[25=USB\r\n] 2006.145.17:50:26.71#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.17:50:26.71#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.17:50:26.71#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.17:50:26.71#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.17:50:26.71$vck44/valo=7,864.99 2006.145.17:50:26.71#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.17:50:26.71#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.17:50:26.71#ibcon#ireg 17 cls_cnt 0 2006.145.17:50:26.71#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.17:50:26.71#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.17:50:26.71#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.17:50:26.73#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.17:50:26.77#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.17:50:26.77#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.17:50:26.77#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.17:50:26.77#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.17:50:26.77$vck44/va=7,4 2006.145.17:50:26.77#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.17:50:26.77#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.17:50:26.77#ibcon#ireg 11 cls_cnt 2 2006.145.17:50:26.77#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.17:50:26.83#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.17:50:26.83#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.17:50:26.85#ibcon#[25=AT07-04\r\n] 2006.145.17:50:26.88#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.17:50:26.88#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.17:50:26.88#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.17:50:26.88#ibcon#ireg 7 cls_cnt 0 2006.145.17:50:26.88#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.17:50:27.00#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.17:50:27.00#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.17:50:27.02#ibcon#[25=USB\r\n] 2006.145.17:50:27.05#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.17:50:27.05#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.17:50:27.05#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.17:50:27.05#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.17:50:27.05$vck44/valo=8,884.99 2006.145.17:50:27.05#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.17:50:27.05#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.17:50:27.05#ibcon#ireg 17 cls_cnt 0 2006.145.17:50:27.05#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.17:50:27.05#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.17:50:27.05#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.17:50:27.07#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.17:50:27.11#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.17:50:27.11#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.17:50:27.11#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.17:50:27.11#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.17:50:27.11$vck44/va=8,4 2006.145.17:50:27.11#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.17:50:27.11#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.17:50:27.11#ibcon#ireg 11 cls_cnt 2 2006.145.17:50:27.11#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.17:50:27.17#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.17:50:27.17#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.17:50:27.19#ibcon#[25=AT08-04\r\n] 2006.145.17:50:27.22#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.17:50:27.22#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.17:50:27.22#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.17:50:27.22#ibcon#ireg 7 cls_cnt 0 2006.145.17:50:27.22#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.17:50:27.34#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.17:50:27.34#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.17:50:27.36#ibcon#[25=USB\r\n] 2006.145.17:50:27.39#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.17:50:27.39#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.17:50:27.39#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.17:50:27.39#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.17:50:27.39$vck44/vblo=1,629.99 2006.145.17:50:27.39#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.17:50:27.39#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.17:50:27.39#ibcon#ireg 17 cls_cnt 0 2006.145.17:50:27.39#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.17:50:27.39#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.17:50:27.39#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.17:50:27.42#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.17:50:27.46#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.17:50:27.46#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.17:50:27.46#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.17:50:27.46#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.17:50:27.46$vck44/vb=1,3 2006.145.17:50:27.46#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.17:50:27.46#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.17:50:27.46#ibcon#ireg 11 cls_cnt 2 2006.145.17:50:27.46#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.17:50:27.46#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.17:50:27.46#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.17:50:27.48#ibcon#[27=AT01-03\r\n] 2006.145.17:50:27.51#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.17:50:27.51#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.17:50:27.51#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.17:50:27.51#ibcon#ireg 7 cls_cnt 0 2006.145.17:50:27.51#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.17:50:27.63#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.17:50:27.63#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.17:50:27.65#ibcon#[27=USB\r\n] 2006.145.17:50:27.68#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.17:50:27.68#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.17:50:27.68#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.17:50:27.68#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.17:50:27.68$vck44/vblo=2,634.99 2006.145.17:50:27.68#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.17:50:27.68#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.17:50:27.68#ibcon#ireg 17 cls_cnt 0 2006.145.17:50:27.68#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.17:50:27.68#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.17:50:27.68#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.17:50:27.70#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.17:50:27.74#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.17:50:27.74#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.17:50:27.74#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.17:50:27.74#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.17:50:27.74$vck44/vb=2,4 2006.145.17:50:27.74#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.17:50:27.74#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.17:50:27.74#ibcon#ireg 11 cls_cnt 2 2006.145.17:50:27.74#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.17:50:27.80#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.17:50:27.80#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.17:50:27.82#ibcon#[27=AT02-04\r\n] 2006.145.17:50:27.85#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.17:50:27.85#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.17:50:27.85#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.17:50:27.85#ibcon#ireg 7 cls_cnt 0 2006.145.17:50:27.85#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.17:50:27.97#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.17:50:27.97#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.17:50:27.99#ibcon#[27=USB\r\n] 2006.145.17:50:28.02#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.17:50:28.02#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.17:50:28.02#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.17:50:28.02#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.17:50:28.02$vck44/vblo=3,649.99 2006.145.17:50:28.02#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.17:50:28.02#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.17:50:28.02#ibcon#ireg 17 cls_cnt 0 2006.145.17:50:28.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.17:50:28.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.17:50:28.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.17:50:28.04#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.17:50:28.08#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.17:50:28.08#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.17:50:28.08#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.17:50:28.08#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.17:50:28.08$vck44/vb=3,4 2006.145.17:50:28.08#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.17:50:28.08#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.17:50:28.08#ibcon#ireg 11 cls_cnt 2 2006.145.17:50:28.08#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.17:50:28.14#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.17:50:28.14#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.17:50:28.16#ibcon#[27=AT03-04\r\n] 2006.145.17:50:28.19#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.17:50:28.19#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.17:50:28.19#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.17:50:28.19#ibcon#ireg 7 cls_cnt 0 2006.145.17:50:28.19#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.17:50:28.31#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.17:50:28.31#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.17:50:28.33#ibcon#[27=USB\r\n] 2006.145.17:50:28.36#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.17:50:28.36#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.17:50:28.36#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.17:50:28.36#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.17:50:28.36$vck44/vblo=4,679.99 2006.145.17:50:28.36#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.17:50:28.36#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.17:50:28.36#ibcon#ireg 17 cls_cnt 0 2006.145.17:50:28.36#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.17:50:28.36#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.17:50:28.36#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.17:50:28.38#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.17:50:28.42#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.17:50:28.42#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.17:50:28.42#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.17:50:28.42#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.17:50:28.42$vck44/vb=4,4 2006.145.17:50:28.42#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.17:50:28.42#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.17:50:28.42#ibcon#ireg 11 cls_cnt 2 2006.145.17:50:28.42#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.17:50:28.48#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.17:50:28.48#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.17:50:28.50#ibcon#[27=AT04-04\r\n] 2006.145.17:50:28.53#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.17:50:28.53#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.17:50:28.53#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.17:50:28.53#ibcon#ireg 7 cls_cnt 0 2006.145.17:50:28.53#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.17:50:28.65#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.17:50:28.65#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.17:50:28.67#ibcon#[27=USB\r\n] 2006.145.17:50:28.70#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.17:50:28.70#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.17:50:28.70#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.17:50:28.70#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.17:50:28.70$vck44/vblo=5,709.99 2006.145.17:50:28.70#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.17:50:28.70#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.17:50:28.70#ibcon#ireg 17 cls_cnt 0 2006.145.17:50:28.70#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.17:50:28.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.17:50:28.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.17:50:28.72#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.17:50:28.76#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.17:50:28.76#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.17:50:28.76#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.17:50:28.76#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.17:50:28.76$vck44/vb=5,4 2006.145.17:50:28.76#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.17:50:28.76#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.17:50:28.76#ibcon#ireg 11 cls_cnt 2 2006.145.17:50:28.76#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.17:50:28.82#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.17:50:28.82#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.17:50:28.84#ibcon#[27=AT05-04\r\n] 2006.145.17:50:28.87#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.17:50:28.87#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.17:50:28.87#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.17:50:28.87#ibcon#ireg 7 cls_cnt 0 2006.145.17:50:28.87#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.17:50:28.99#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.17:50:28.99#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.17:50:29.01#ibcon#[27=USB\r\n] 2006.145.17:50:29.04#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.17:50:29.04#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.17:50:29.04#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.17:50:29.04#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.17:50:29.04$vck44/vblo=6,719.99 2006.145.17:50:29.04#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.17:50:29.04#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.17:50:29.04#ibcon#ireg 17 cls_cnt 0 2006.145.17:50:29.04#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.17:50:29.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.17:50:29.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.17:50:29.06#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.17:50:29.10#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.17:50:29.10#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.17:50:29.10#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.17:50:29.10#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.17:50:29.10$vck44/vb=6,4 2006.145.17:50:29.10#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.17:50:29.10#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.17:50:29.10#ibcon#ireg 11 cls_cnt 2 2006.145.17:50:29.10#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.17:50:29.16#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.17:50:29.16#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.17:50:29.18#ibcon#[27=AT06-04\r\n] 2006.145.17:50:29.21#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.17:50:29.21#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.17:50:29.21#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.17:50:29.21#ibcon#ireg 7 cls_cnt 0 2006.145.17:50:29.21#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.17:50:29.33#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.17:50:29.33#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.17:50:29.35#ibcon#[27=USB\r\n] 2006.145.17:50:29.38#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.17:50:29.38#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.17:50:29.38#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.17:50:29.38#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.17:50:29.38$vck44/vblo=7,734.99 2006.145.17:50:29.38#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.17:50:29.38#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.17:50:29.38#ibcon#ireg 17 cls_cnt 0 2006.145.17:50:29.38#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.17:50:29.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.17:50:29.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.17:50:29.40#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.17:50:29.44#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.17:50:29.44#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.17:50:29.44#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.17:50:29.44#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.17:50:29.44$vck44/vb=7,4 2006.145.17:50:29.44#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.17:50:29.44#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.17:50:29.44#ibcon#ireg 11 cls_cnt 2 2006.145.17:50:29.44#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.17:50:29.50#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.17:50:29.50#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.17:50:29.52#ibcon#[27=AT07-04\r\n] 2006.145.17:50:29.55#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.17:50:29.55#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.17:50:29.55#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.17:50:29.55#ibcon#ireg 7 cls_cnt 0 2006.145.17:50:29.55#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.17:50:29.67#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.17:50:29.67#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.17:50:29.69#ibcon#[27=USB\r\n] 2006.145.17:50:29.72#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.17:50:29.72#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.17:50:29.72#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.17:50:29.72#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.17:50:29.72$vck44/vblo=8,744.99 2006.145.17:50:29.72#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.17:50:29.72#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.17:50:29.72#ibcon#ireg 17 cls_cnt 0 2006.145.17:50:29.72#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.17:50:29.72#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.17:50:29.72#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.17:50:29.74#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.17:50:29.78#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.17:50:29.78#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.17:50:29.78#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.17:50:29.78#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.17:50:29.78$vck44/vb=8,4 2006.145.17:50:29.78#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.17:50:29.78#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.17:50:29.78#ibcon#ireg 11 cls_cnt 2 2006.145.17:50:29.78#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.17:50:29.84#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.17:50:29.84#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.17:50:29.86#ibcon#[27=AT08-04\r\n] 2006.145.17:50:29.89#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.17:50:29.89#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.17:50:29.89#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.17:50:29.89#ibcon#ireg 7 cls_cnt 0 2006.145.17:50:29.89#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.17:50:30.01#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.17:50:30.01#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.17:50:30.03#ibcon#[27=USB\r\n] 2006.145.17:50:30.06#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.17:50:30.06#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.17:50:30.06#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.17:50:30.06#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.17:50:30.06$vck44/vabw=wide 2006.145.17:50:30.06#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.17:50:30.06#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.17:50:30.06#ibcon#ireg 8 cls_cnt 0 2006.145.17:50:30.06#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.17:50:30.06#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.17:50:30.06#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.17:50:30.08#ibcon#[25=BW32\r\n] 2006.145.17:50:30.11#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.17:50:30.11#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.17:50:30.11#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.17:50:30.11#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.17:50:30.11$vck44/vbbw=wide 2006.145.17:50:30.11#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.17:50:30.11#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.17:50:30.11#ibcon#ireg 8 cls_cnt 0 2006.145.17:50:30.11#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.17:50:30.18#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.17:50:30.18#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.17:50:30.20#ibcon#[27=BW32\r\n] 2006.145.17:50:30.23#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.17:50:30.23#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.17:50:30.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.17:50:30.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.17:50:30.23$setupk4/ifdk4 2006.145.17:50:30.23$ifdk4/lo= 2006.145.17:50:30.23$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.17:50:30.23$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.17:50:30.23$ifdk4/patch= 2006.145.17:50:30.23$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.17:50:30.23$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.17:50:30.23$setupk4/!*+20s 2006.145.17:50:32.84#abcon#<5=/05 1.0 1.7 15.78 901019.6\r\n> 2006.145.17:50:32.86#abcon#{5=INTERFACE CLEAR} 2006.145.17:50:32.92#abcon#[5=S1D000X0/0*\r\n] 2006.145.17:50:43.01#abcon#<5=/05 1.0 1.8 15.78 911019.6\r\n> 2006.145.17:50:43.03#abcon#{5=INTERFACE CLEAR} 2006.145.17:50:43.09#abcon#[5=S1D000X0/0*\r\n] 2006.145.17:50:44.70$setupk4/"tpicd 2006.145.17:50:44.70$setupk4/echo=off 2006.145.17:50:44.70$setupk4/xlog=off 2006.145.17:50:44.70:!2006.145.17:52:09 2006.145.17:51:07.14#trakl#Source acquired 2006.145.17:51:07.14#flagr#flagr/antenna,acquired 2006.145.17:52:09.00:preob 2006.145.17:52:09.13/onsource/TRACKING 2006.145.17:52:09.13:!2006.145.17:52:19 2006.145.17:52:19.00:"tape 2006.145.17:52:19.00:"st=record 2006.145.17:52:19.00:data_valid=on 2006.145.17:52:19.00:midob 2006.145.17:52:20.13/onsource/TRACKING 2006.145.17:52:20.13/wx/15.77,1019.6,90 2006.145.17:52:20.21/cable/+6.5505E-03 2006.145.17:52:21.30/va/01,08,usb,yes,28,30 2006.145.17:52:21.30/va/02,07,usb,yes,30,31 2006.145.17:52:21.30/va/03,08,usb,yes,27,28 2006.145.17:52:21.30/va/04,07,usb,yes,31,33 2006.145.17:52:21.30/va/05,04,usb,yes,27,27 2006.145.17:52:21.30/va/06,04,usb,yes,30,30 2006.145.17:52:21.30/va/07,04,usb,yes,31,32 2006.145.17:52:21.30/va/08,04,usb,yes,26,31 2006.145.17:52:21.53/valo/01,524.99,yes,locked 2006.145.17:52:21.53/valo/02,534.99,yes,locked 2006.145.17:52:21.53/valo/03,564.99,yes,locked 2006.145.17:52:21.53/valo/04,624.99,yes,locked 2006.145.17:52:21.53/valo/05,734.99,yes,locked 2006.145.17:52:21.53/valo/06,814.99,yes,locked 2006.145.17:52:21.53/valo/07,864.99,yes,locked 2006.145.17:52:21.53/valo/08,884.99,yes,locked 2006.145.17:52:22.62/vb/01,03,usb,yes,35,33 2006.145.17:52:22.62/vb/02,04,usb,yes,31,31 2006.145.17:52:22.62/vb/03,04,usb,yes,28,31 2006.145.17:52:22.62/vb/04,04,usb,yes,32,31 2006.145.17:52:22.62/vb/05,04,usb,yes,25,27 2006.145.17:52:22.62/vb/06,04,usb,yes,29,26 2006.145.17:52:22.62/vb/07,04,usb,yes,29,29 2006.145.17:52:22.62/vb/08,04,usb,yes,27,30 2006.145.17:52:22.85/vblo/01,629.99,yes,locked 2006.145.17:52:22.85/vblo/02,634.99,yes,locked 2006.145.17:52:22.85/vblo/03,649.99,yes,locked 2006.145.17:52:22.85/vblo/04,679.99,yes,locked 2006.145.17:52:22.85/vblo/05,709.99,yes,locked 2006.145.17:52:22.85/vblo/06,719.99,yes,locked 2006.145.17:52:22.85/vblo/07,734.99,yes,locked 2006.145.17:52:22.85/vblo/08,744.99,yes,locked 2006.145.17:52:23.00/vabw/8 2006.145.17:52:23.15/vbbw/8 2006.145.17:52:23.24/xfe/off,on,15.0 2006.145.17:52:23.62/ifatt/23,28,28,28 2006.145.17:52:24.08/fmout-gps/S +4.4E-08 2006.145.17:52:24.12:!2006.145.17:54:29 2006.145.17:54:29.01:data_valid=off 2006.145.17:54:29.02:"et 2006.145.17:54:29.02:!+3s 2006.145.17:54:32.03:"tape 2006.145.17:54:32.03:postob 2006.145.17:54:32.20/cable/+6.5495E-03 2006.145.17:54:32.21/wx/15.75,1019.6,91 2006.145.17:54:32.28/fmout-gps/S +4.4E-08 2006.145.17:54:32.28:scan_name=145-1800,jd0605,430 2006.145.17:54:32.28:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.145.17:54:34.14#flagr#flagr/antenna,new-source 2006.145.17:54:34.14:checkk5 2006.145.17:54:34.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.17:54:35.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.17:54:35.45/chk_autoobs//k5ts3/ autoobs is running! 2006.145.17:54:35.87/chk_autoobs//k5ts4/ autoobs is running! 2006.145.17:54:36.30/chk_obsdata//k5ts1/T1451752??a.dat file size is correct (nominal:520MB, actual:520MB). 2006.145.17:54:36.73/chk_obsdata//k5ts2/T1451752??b.dat file size is correct (nominal:520MB, actual:520MB). 2006.145.17:54:37.18/chk_obsdata//k5ts3/T1451752??c.dat file size is correct (nominal:520MB, actual:520MB). 2006.145.17:54:37.62/chk_obsdata//k5ts4/T1451752??d.dat file size is correct (nominal:520MB, actual:520MB). 2006.145.17:54:38.37/k5log//k5ts1_log_newline 2006.145.17:54:39.12/k5log//k5ts2_log_newline 2006.145.17:54:39.84/k5log//k5ts3_log_newline 2006.145.17:54:40.60/k5log//k5ts4_log_newline 2006.145.17:54:40.62/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.17:54:40.62:setupk4=1 2006.145.17:54:40.62$setupk4/echo=on 2006.145.17:54:40.62$setupk4/pcalon 2006.145.17:54:40.62$pcalon/"no phase cal control is implemented here 2006.145.17:54:40.62$setupk4/"tpicd=stop 2006.145.17:54:40.62$setupk4/"rec=synch_on 2006.145.17:54:40.62$setupk4/"rec_mode=128 2006.145.17:54:40.62$setupk4/!* 2006.145.17:54:40.62$setupk4/recpk4 2006.145.17:54:40.62$recpk4/recpatch= 2006.145.17:54:40.62$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.17:54:40.62$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.17:54:40.62$setupk4/vck44 2006.145.17:54:40.62$vck44/valo=1,524.99 2006.145.17:54:40.62#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.17:54:40.62#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.17:54:40.62#ibcon#ireg 17 cls_cnt 0 2006.145.17:54:40.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:54:40.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:54:40.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:54:40.64#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.17:54:40.69#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:54:40.69#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:54:40.69#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.17:54:40.69#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.17:54:40.69$vck44/va=1,8 2006.145.17:54:40.69#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.17:54:40.69#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.17:54:40.69#ibcon#ireg 11 cls_cnt 2 2006.145.17:54:40.69#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:54:40.69#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:54:40.69#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:54:40.71#ibcon#[25=AT01-08\r\n] 2006.145.17:54:40.74#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:54:40.74#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:54:40.74#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.17:54:40.74#ibcon#ireg 7 cls_cnt 0 2006.145.17:54:40.74#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:54:40.86#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:54:40.86#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:54:40.88#ibcon#[25=USB\r\n] 2006.145.17:54:40.91#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:54:40.91#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:54:40.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.17:54:40.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.17:54:40.91$vck44/valo=2,534.99 2006.145.17:54:40.91#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.17:54:40.91#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.17:54:40.91#ibcon#ireg 17 cls_cnt 0 2006.145.17:54:40.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:54:40.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:54:40.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:54:40.94#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.17:54:40.98#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:54:40.98#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:54:40.98#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.17:54:40.98#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.17:54:40.98$vck44/va=2,7 2006.145.17:54:40.98#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.17:54:40.98#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.17:54:40.98#ibcon#ireg 11 cls_cnt 2 2006.145.17:54:40.98#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:54:41.03#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:54:41.03#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:54:41.05#ibcon#[25=AT02-07\r\n] 2006.145.17:54:41.08#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:54:41.08#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:54:41.08#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.17:54:41.08#ibcon#ireg 7 cls_cnt 0 2006.145.17:54:41.08#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:54:41.20#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:54:41.20#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:54:41.22#ibcon#[25=USB\r\n] 2006.145.17:54:41.25#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:54:41.25#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:54:41.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.17:54:41.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.17:54:41.25$vck44/valo=3,564.99 2006.145.17:54:41.25#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.17:54:41.25#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.17:54:41.25#ibcon#ireg 17 cls_cnt 0 2006.145.17:54:41.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:54:41.25#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:54:41.25#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:54:41.27#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.17:54:41.31#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:54:41.31#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:54:41.31#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.17:54:41.31#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.17:54:41.31$vck44/va=3,8 2006.145.17:54:41.31#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.17:54:41.31#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.17:54:41.31#ibcon#ireg 11 cls_cnt 2 2006.145.17:54:41.31#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.17:54:41.37#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.17:54:41.37#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.17:54:41.39#ibcon#[25=AT03-08\r\n] 2006.145.17:54:41.42#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.17:54:41.42#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.17:54:41.42#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.17:54:41.42#ibcon#ireg 7 cls_cnt 0 2006.145.17:54:41.42#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.17:54:41.54#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.17:54:41.54#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.17:54:41.56#ibcon#[25=USB\r\n] 2006.145.17:54:41.59#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.17:54:41.59#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.17:54:41.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.17:54:41.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.17:54:41.59$vck44/valo=4,624.99 2006.145.17:54:41.59#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.17:54:41.59#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.17:54:41.59#ibcon#ireg 17 cls_cnt 0 2006.145.17:54:41.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.17:54:41.59#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.17:54:41.59#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.17:54:41.61#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.17:54:41.65#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.17:54:41.65#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.17:54:41.65#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.17:54:41.65#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.17:54:41.65$vck44/va=4,7 2006.145.17:54:41.65#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.17:54:41.65#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.17:54:41.65#ibcon#ireg 11 cls_cnt 2 2006.145.17:54:41.65#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.17:54:41.71#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.17:54:41.71#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.17:54:41.73#ibcon#[25=AT04-07\r\n] 2006.145.17:54:41.76#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.17:54:41.76#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.17:54:41.76#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.17:54:41.76#ibcon#ireg 7 cls_cnt 0 2006.145.17:54:41.76#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.17:54:41.88#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.17:54:41.88#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.17:54:41.90#ibcon#[25=USB\r\n] 2006.145.17:54:41.93#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.17:54:41.93#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.17:54:41.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.17:54:41.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.17:54:41.93$vck44/valo=5,734.99 2006.145.17:54:41.93#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.17:54:41.93#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.17:54:41.93#ibcon#ireg 17 cls_cnt 0 2006.145.17:54:41.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:54:41.93#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:54:41.93#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:54:41.95#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.17:54:41.99#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:54:41.99#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:54:41.99#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.17:54:41.99#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.17:54:41.99$vck44/va=5,4 2006.145.17:54:41.99#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.17:54:41.99#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.17:54:41.99#ibcon#ireg 11 cls_cnt 2 2006.145.17:54:41.99#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:54:42.05#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:54:42.05#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:54:42.07#ibcon#[25=AT05-04\r\n] 2006.145.17:54:42.10#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:54:42.10#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:54:42.10#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.17:54:42.10#ibcon#ireg 7 cls_cnt 0 2006.145.17:54:42.10#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:54:42.22#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:54:42.22#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:54:42.24#ibcon#[25=USB\r\n] 2006.145.17:54:42.27#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:54:42.27#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:54:42.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.17:54:42.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.17:54:42.27$vck44/valo=6,814.99 2006.145.17:54:42.27#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.17:54:42.27#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.17:54:42.27#ibcon#ireg 17 cls_cnt 0 2006.145.17:54:42.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:54:42.27#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:54:42.27#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:54:42.30#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.17:54:42.34#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:54:42.34#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:54:42.34#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.17:54:42.34#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.17:54:42.34$vck44/va=6,4 2006.145.17:54:42.34#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.17:54:42.34#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.17:54:42.34#ibcon#ireg 11 cls_cnt 2 2006.145.17:54:42.34#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.17:54:42.39#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.17:54:42.39#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.17:54:42.41#ibcon#[25=AT06-04\r\n] 2006.145.17:54:42.44#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.17:54:42.44#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.17:54:42.44#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.17:54:42.44#ibcon#ireg 7 cls_cnt 0 2006.145.17:54:42.44#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.17:54:42.56#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.17:54:42.56#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.17:54:42.58#ibcon#[25=USB\r\n] 2006.145.17:54:42.61#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.17:54:42.61#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.17:54:42.61#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.17:54:42.61#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.17:54:42.61$vck44/valo=7,864.99 2006.145.17:54:42.61#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.17:54:42.61#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.17:54:42.61#ibcon#ireg 17 cls_cnt 0 2006.145.17:54:42.61#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:54:42.61#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:54:42.61#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:54:42.63#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.17:54:42.67#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:54:42.67#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:54:42.67#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.17:54:42.67#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.17:54:42.67$vck44/va=7,4 2006.145.17:54:42.67#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.17:54:42.67#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.17:54:42.67#ibcon#ireg 11 cls_cnt 2 2006.145.17:54:42.67#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:54:42.73#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:54:42.73#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:54:42.75#ibcon#[25=AT07-04\r\n] 2006.145.17:54:42.78#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:54:42.78#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:54:42.78#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.17:54:42.78#ibcon#ireg 7 cls_cnt 0 2006.145.17:54:42.78#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:54:42.90#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:54:42.90#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:54:42.92#ibcon#[25=USB\r\n] 2006.145.17:54:42.95#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:54:42.95#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:54:42.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.17:54:42.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.17:54:42.95$vck44/valo=8,884.99 2006.145.17:54:42.95#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.17:54:42.95#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.17:54:42.95#ibcon#ireg 17 cls_cnt 0 2006.145.17:54:42.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.17:54:42.95#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.17:54:42.95#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.17:54:42.97#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.17:54:43.01#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.17:54:43.01#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.17:54:43.01#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.17:54:43.01#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.17:54:43.01$vck44/va=8,4 2006.145.17:54:43.01#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.17:54:43.01#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.17:54:43.01#ibcon#ireg 11 cls_cnt 2 2006.145.17:54:43.01#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.17:54:43.07#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.17:54:43.07#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.17:54:43.09#ibcon#[25=AT08-04\r\n] 2006.145.17:54:43.12#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.17:54:43.12#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.17:54:43.12#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.17:54:43.12#ibcon#ireg 7 cls_cnt 0 2006.145.17:54:43.12#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.17:54:43.24#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.17:54:43.24#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.17:54:43.26#ibcon#[25=USB\r\n] 2006.145.17:54:43.29#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.17:54:43.29#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.17:54:43.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.17:54:43.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.17:54:43.29$vck44/vblo=1,629.99 2006.145.17:54:43.29#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.17:54:43.29#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.17:54:43.29#ibcon#ireg 17 cls_cnt 0 2006.145.17:54:43.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.17:54:43.29#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.17:54:43.29#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.17:54:43.31#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.17:54:43.35#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.17:54:43.35#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.17:54:43.35#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.17:54:43.35#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.17:54:43.35$vck44/vb=1,3 2006.145.17:54:43.35#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.17:54:43.35#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.17:54:43.35#ibcon#ireg 11 cls_cnt 2 2006.145.17:54:43.35#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.17:54:43.35#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.17:54:43.35#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.17:54:43.37#ibcon#[27=AT01-03\r\n] 2006.145.17:54:43.40#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.17:54:43.40#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.17:54:43.40#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.17:54:43.40#ibcon#ireg 7 cls_cnt 0 2006.145.17:54:43.40#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.17:54:43.52#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.17:54:43.52#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.17:54:43.54#ibcon#[27=USB\r\n] 2006.145.17:54:43.57#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.17:54:43.57#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.17:54:43.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.17:54:43.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.17:54:43.57$vck44/vblo=2,634.99 2006.145.17:54:43.57#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.17:54:43.57#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.17:54:43.57#ibcon#ireg 17 cls_cnt 0 2006.145.17:54:43.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:54:43.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:54:43.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:54:43.59#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.17:54:43.63#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:54:43.63#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.17:54:43.63#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.17:54:43.63#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.17:54:43.63$vck44/vb=2,4 2006.145.17:54:43.63#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.17:54:43.63#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.17:54:43.63#ibcon#ireg 11 cls_cnt 2 2006.145.17:54:43.63#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:54:43.69#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:54:43.69#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:54:43.71#ibcon#[27=AT02-04\r\n] 2006.145.17:54:43.74#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:54:43.74#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.17:54:43.74#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.17:54:43.74#ibcon#ireg 7 cls_cnt 0 2006.145.17:54:43.74#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:54:43.86#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:54:43.86#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:54:43.88#ibcon#[27=USB\r\n] 2006.145.17:54:43.91#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:54:43.91#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.17:54:43.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.17:54:43.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.17:54:43.91$vck44/vblo=3,649.99 2006.145.17:54:43.91#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.17:54:43.91#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.17:54:43.91#ibcon#ireg 17 cls_cnt 0 2006.145.17:54:43.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:54:43.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:54:43.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:54:43.93#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.17:54:43.97#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:54:43.97#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.17:54:43.97#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.17:54:43.97#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.17:54:43.97$vck44/vb=3,4 2006.145.17:54:43.97#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.17:54:43.97#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.17:54:43.97#ibcon#ireg 11 cls_cnt 2 2006.145.17:54:43.97#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:54:44.03#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:54:44.03#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:54:44.05#ibcon#[27=AT03-04\r\n] 2006.145.17:54:44.08#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:54:44.08#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.17:54:44.08#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.17:54:44.08#ibcon#ireg 7 cls_cnt 0 2006.145.17:54:44.08#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:54:44.20#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:54:44.20#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:54:44.22#ibcon#[27=USB\r\n] 2006.145.17:54:44.25#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:54:44.25#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.17:54:44.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.17:54:44.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.17:54:44.25$vck44/vblo=4,679.99 2006.145.17:54:44.25#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.17:54:44.25#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.17:54:44.25#ibcon#ireg 17 cls_cnt 0 2006.145.17:54:44.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:54:44.25#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:54:44.25#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:54:44.27#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.17:54:44.31#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:54:44.31#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.17:54:44.31#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.17:54:44.31#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.17:54:44.31$vck44/vb=4,4 2006.145.17:54:44.31#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.17:54:44.31#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.17:54:44.31#ibcon#ireg 11 cls_cnt 2 2006.145.17:54:44.31#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.17:54:44.37#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.17:54:44.37#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.17:54:44.39#ibcon#[27=AT04-04\r\n] 2006.145.17:54:44.42#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.17:54:44.42#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.17:54:44.42#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.17:54:44.42#ibcon#ireg 7 cls_cnt 0 2006.145.17:54:44.42#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.17:54:44.54#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.17:54:44.54#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.17:54:44.56#ibcon#[27=USB\r\n] 2006.145.17:54:44.59#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.17:54:44.59#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.17:54:44.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.17:54:44.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.17:54:44.59$vck44/vblo=5,709.99 2006.145.17:54:44.59#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.17:54:44.59#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.17:54:44.59#ibcon#ireg 17 cls_cnt 0 2006.145.17:54:44.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.17:54:44.59#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.17:54:44.59#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.17:54:44.61#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.17:54:44.65#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.17:54:44.65#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.17:54:44.65#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.17:54:44.65#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.17:54:44.65$vck44/vb=5,4 2006.145.17:54:44.65#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.17:54:44.65#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.17:54:44.65#ibcon#ireg 11 cls_cnt 2 2006.145.17:54:44.65#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.17:54:44.71#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.17:54:44.71#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.17:54:44.73#ibcon#[27=AT05-04\r\n] 2006.145.17:54:44.76#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.17:54:44.76#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.17:54:44.76#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.17:54:44.76#ibcon#ireg 7 cls_cnt 0 2006.145.17:54:44.76#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.17:54:44.88#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.17:54:44.88#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.17:54:44.90#ibcon#[27=USB\r\n] 2006.145.17:54:44.93#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.17:54:44.93#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.17:54:44.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.17:54:44.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.17:54:44.93$vck44/vblo=6,719.99 2006.145.17:54:44.93#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.17:54:44.93#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.17:54:44.93#ibcon#ireg 17 cls_cnt 0 2006.145.17:54:44.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:54:44.93#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:54:44.93#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:54:44.95#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.17:54:44.99#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:54:44.99#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.17:54:44.99#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.17:54:44.99#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.17:54:44.99$vck44/vb=6,4 2006.145.17:54:44.99#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.17:54:44.99#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.17:54:44.99#ibcon#ireg 11 cls_cnt 2 2006.145.17:54:44.99#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:54:45.05#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:54:45.05#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:54:45.07#ibcon#[27=AT06-04\r\n] 2006.145.17:54:45.10#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:54:45.10#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.17:54:45.10#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.17:54:45.10#ibcon#ireg 7 cls_cnt 0 2006.145.17:54:45.10#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:54:45.22#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:54:45.22#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:54:45.24#ibcon#[27=USB\r\n] 2006.145.17:54:45.27#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:54:45.27#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.17:54:45.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.17:54:45.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.17:54:45.27$vck44/vblo=7,734.99 2006.145.17:54:45.27#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.17:54:45.27#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.17:54:45.27#ibcon#ireg 17 cls_cnt 0 2006.145.17:54:45.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:54:45.27#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:54:45.27#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:54:45.29#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.17:54:45.33#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:54:45.33#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.17:54:45.33#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.17:54:45.33#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.17:54:45.33$vck44/vb=7,4 2006.145.17:54:45.33#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.17:54:45.33#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.17:54:45.33#ibcon#ireg 11 cls_cnt 2 2006.145.17:54:45.33#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.17:54:45.39#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.17:54:45.39#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.17:54:45.41#ibcon#[27=AT07-04\r\n] 2006.145.17:54:45.44#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.17:54:45.44#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.17:54:45.44#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.17:54:45.44#ibcon#ireg 7 cls_cnt 0 2006.145.17:54:45.44#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.17:54:45.56#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.17:54:45.56#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.17:54:45.58#ibcon#[27=USB\r\n] 2006.145.17:54:45.61#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.17:54:45.61#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.17:54:45.61#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.17:54:45.61#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.17:54:45.61$vck44/vblo=8,744.99 2006.145.17:54:45.61#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.17:54:45.61#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.17:54:45.61#ibcon#ireg 17 cls_cnt 0 2006.145.17:54:45.61#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:54:45.61#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:54:45.61#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:54:45.63#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.17:54:45.67#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:54:45.67#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.17:54:45.67#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.17:54:45.67#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.17:54:45.67$vck44/vb=8,4 2006.145.17:54:45.67#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.17:54:45.67#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.17:54:45.67#ibcon#ireg 11 cls_cnt 2 2006.145.17:54:45.67#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:54:45.73#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:54:45.73#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:54:45.75#ibcon#[27=AT08-04\r\n] 2006.145.17:54:45.78#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:54:45.78#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.17:54:45.78#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.17:54:45.78#ibcon#ireg 7 cls_cnt 0 2006.145.17:54:45.78#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:54:45.90#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:54:45.90#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:54:45.92#ibcon#[27=USB\r\n] 2006.145.17:54:45.95#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:54:45.95#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.17:54:45.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.17:54:45.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.17:54:45.95$vck44/vabw=wide 2006.145.17:54:45.95#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.17:54:45.95#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.17:54:45.95#ibcon#ireg 8 cls_cnt 0 2006.145.17:54:45.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.17:54:45.95#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.17:54:45.95#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.17:54:45.97#ibcon#[25=BW32\r\n] 2006.145.17:54:46.00#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.17:54:46.00#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.17:54:46.00#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.17:54:46.00#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.17:54:46.00$vck44/vbbw=wide 2006.145.17:54:46.00#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.17:54:46.00#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.17:54:46.00#ibcon#ireg 8 cls_cnt 0 2006.145.17:54:46.00#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:54:46.07#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:54:46.07#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:54:46.09#ibcon#[27=BW32\r\n] 2006.145.17:54:46.12#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:54:46.12#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.17:54:46.12#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.17:54:46.12#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.17:54:46.12$setupk4/ifdk4 2006.145.17:54:46.12$ifdk4/lo= 2006.145.17:54:46.12$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.17:54:46.12$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.17:54:46.12$ifdk4/patch= 2006.145.17:54:46.12$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.17:54:46.12$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.17:54:46.12$setupk4/!*+20s 2006.145.17:54:47.09#abcon#<5=/04 1.2 1.9 15.75 911019.6\r\n> 2006.145.17:54:47.11#abcon#{5=INTERFACE CLEAR} 2006.145.17:54:47.17#abcon#[5=S1D000X0/0*\r\n] 2006.145.17:54:57.26#abcon#<5=/04 1.2 1.9 15.75 901019.6\r\n> 2006.145.17:54:57.28#abcon#{5=INTERFACE CLEAR} 2006.145.17:54:57.34#abcon#[5=S1D000X0/0*\r\n] 2006.145.17:54:58.14#trakl#Source acquired 2006.145.17:54:59.14#flagr#flagr/antenna,acquired 2006.145.17:55:00.63$setupk4/"tpicd 2006.145.17:55:00.63$setupk4/echo=off 2006.145.17:55:00.63$setupk4/xlog=off 2006.145.17:55:00.63:!2006.145.18:00:05 2006.145.18:00:05.00:preob 2006.145.18:00:06.14/onsource/TRACKING 2006.145.18:00:06.14:!2006.145.18:00:15 2006.145.18:00:15.00:"tape 2006.145.18:00:15.00:"st=record 2006.145.18:00:15.00:data_valid=on 2006.145.18:00:15.00:midob 2006.145.18:00:15.14/onsource/TRACKING 2006.145.18:00:15.14/wx/15.70,1019.7,90 2006.145.18:00:15.25/cable/+6.5509E-03 2006.145.18:00:16.34/va/01,08,usb,yes,29,31 2006.145.18:00:16.34/va/02,07,usb,yes,31,31 2006.145.18:00:16.34/va/03,08,usb,yes,28,29 2006.145.18:00:16.34/va/04,07,usb,yes,32,33 2006.145.18:00:16.34/va/05,04,usb,yes,28,28 2006.145.18:00:16.34/va/06,04,usb,yes,31,31 2006.145.18:00:16.34/va/07,04,usb,yes,31,32 2006.145.18:00:16.34/va/08,04,usb,yes,27,32 2006.145.18:00:16.57/valo/01,524.99,yes,locked 2006.145.18:00:16.57/valo/02,534.99,yes,locked 2006.145.18:00:16.57/valo/03,564.99,yes,locked 2006.145.18:00:16.57/valo/04,624.99,yes,locked 2006.145.18:00:16.57/valo/05,734.99,yes,locked 2006.145.18:00:16.57/valo/06,814.99,yes,locked 2006.145.18:00:16.57/valo/07,864.99,yes,locked 2006.145.18:00:16.57/valo/08,884.99,yes,locked 2006.145.18:00:17.66/vb/01,03,usb,yes,36,34 2006.145.18:00:17.66/vb/02,04,usb,yes,31,31 2006.145.18:00:17.66/vb/03,04,usb,yes,28,31 2006.145.18:00:17.66/vb/04,04,usb,yes,33,32 2006.145.18:00:17.66/vb/05,04,usb,yes,25,28 2006.145.18:00:17.66/vb/06,04,usb,yes,30,26 2006.145.18:00:17.66/vb/07,04,usb,yes,29,29 2006.145.18:00:17.66/vb/08,04,usb,yes,27,30 2006.145.18:00:17.90/vblo/01,629.99,yes,locked 2006.145.18:00:17.90/vblo/02,634.99,yes,locked 2006.145.18:00:17.90/vblo/03,649.99,yes,locked 2006.145.18:00:17.90/vblo/04,679.99,yes,locked 2006.145.18:00:17.90/vblo/05,709.99,yes,locked 2006.145.18:00:17.90/vblo/06,719.99,yes,locked 2006.145.18:00:17.90/vblo/07,734.99,yes,locked 2006.145.18:00:17.90/vblo/08,744.99,yes,locked 2006.145.18:00:18.05/vabw/8 2006.145.18:00:18.20/vbbw/8 2006.145.18:00:18.30/xfe/off,on,14.5 2006.145.18:00:18.69/ifatt/23,28,28,28 2006.145.18:00:19.08/fmout-gps/S +4.6E-08 2006.145.18:00:19.12:!2006.145.18:07:25 2006.145.18:07:25.00:data_valid=off 2006.145.18:07:25.00:"et 2006.145.18:07:25.01:!+3s 2006.145.18:07:28.02:"tape 2006.145.18:07:28.02:postob 2006.145.18:07:28.13/cable/+6.5504E-03 2006.145.18:07:28.13/wx/15.68,1019.7,91 2006.145.18:07:29.08/fmout-gps/S +4.7E-08 2006.145.18:07:29.08:scan_name=145-1813,jd0605,190 2006.145.18:07:29.09:source=3c446,222547.26,-045701.4,2000.0,ccw 2006.145.18:07:30.14#flagr#flagr/antenna,new-source 2006.145.18:07:30.14:checkk5 2006.145.18:07:30.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.18:07:31.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.18:07:31.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.18:07:31.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.18:07:32.31/chk_obsdata//k5ts1/T1451800??a.dat file size is correct (nominal:1720MB, actual:1716MB). 2006.145.18:07:32.76/chk_obsdata//k5ts2/T1451800??b.dat file size is correct (nominal:1720MB, actual:1716MB). 2006.145.18:07:33.20/chk_obsdata//k5ts3/T1451800??c.dat file size is correct (nominal:1720MB, actual:1716MB). 2006.145.18:07:33.66/chk_obsdata//k5ts4/T1451800??d.dat file size is correct (nominal:1720MB, actual:1716MB). 2006.145.18:07:34.41/k5log//k5ts1_log_newline 2006.145.18:07:35.16/k5log//k5ts2_log_newline 2006.145.18:07:35.90/k5log//k5ts3_log_newline 2006.145.18:07:36.65/k5log//k5ts4_log_newline 2006.145.18:07:36.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.18:07:36.67:setupk4=1 2006.145.18:07:36.67$setupk4/echo=on 2006.145.18:07:36.67$setupk4/pcalon 2006.145.18:07:36.67$pcalon/"no phase cal control is implemented here 2006.145.18:07:36.67$setupk4/"tpicd=stop 2006.145.18:07:36.67$setupk4/"rec=synch_on 2006.145.18:07:36.67$setupk4/"rec_mode=128 2006.145.18:07:36.67$setupk4/!* 2006.145.18:07:36.67$setupk4/recpk4 2006.145.18:07:36.67$recpk4/recpatch= 2006.145.18:07:36.68$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.18:07:36.68$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.18:07:36.68$setupk4/vck44 2006.145.18:07:36.68$vck44/valo=1,524.99 2006.145.18:07:36.68#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.18:07:36.68#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.18:07:36.68#ibcon#ireg 17 cls_cnt 0 2006.145.18:07:36.68#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.18:07:36.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.18:07:36.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.18:07:36.72#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.18:07:36.77#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.18:07:36.77#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.18:07:36.77#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.18:07:36.77#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.18:07:36.77$vck44/va=1,8 2006.145.18:07:36.77#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.18:07:36.77#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.18:07:36.77#ibcon#ireg 11 cls_cnt 2 2006.145.18:07:36.77#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.18:07:36.77#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.18:07:36.77#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.18:07:36.79#ibcon#[25=AT01-08\r\n] 2006.145.18:07:36.82#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.18:07:36.82#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.18:07:36.82#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.18:07:36.82#ibcon#ireg 7 cls_cnt 0 2006.145.18:07:36.82#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.18:07:36.94#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.18:07:36.94#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.18:07:36.96#ibcon#[25=USB\r\n] 2006.145.18:07:36.99#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.18:07:36.99#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.18:07:36.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.18:07:36.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.18:07:36.99$vck44/valo=2,534.99 2006.145.18:07:36.99#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.18:07:36.99#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.18:07:36.99#ibcon#ireg 17 cls_cnt 0 2006.145.18:07:36.99#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:07:36.99#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:07:36.99#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:07:37.02#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.18:07:37.06#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:07:37.06#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:07:37.06#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.18:07:37.06#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.18:07:37.06$vck44/va=2,7 2006.145.18:07:37.06#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.18:07:37.06#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.18:07:37.06#ibcon#ireg 11 cls_cnt 2 2006.145.18:07:37.06#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:07:37.11#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:07:37.11#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:07:37.13#ibcon#[25=AT02-07\r\n] 2006.145.18:07:37.16#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:07:37.16#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:07:37.16#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.18:07:37.16#ibcon#ireg 7 cls_cnt 0 2006.145.18:07:37.16#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:07:37.28#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:07:37.28#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:07:37.30#ibcon#[25=USB\r\n] 2006.145.18:07:37.33#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:07:37.33#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:07:37.33#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.18:07:37.33#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.18:07:37.33$vck44/valo=3,564.99 2006.145.18:07:37.33#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.18:07:37.33#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.18:07:37.33#ibcon#ireg 17 cls_cnt 0 2006.145.18:07:37.33#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.18:07:37.33#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.18:07:37.33#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.18:07:37.35#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.18:07:37.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.18:07:37.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.18:07:37.39#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.18:07:37.39#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.18:07:37.39$vck44/va=3,8 2006.145.18:07:37.39#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.18:07:37.39#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.18:07:37.39#ibcon#ireg 11 cls_cnt 2 2006.145.18:07:37.39#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.18:07:37.45#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.18:07:37.45#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.18:07:37.47#ibcon#[25=AT03-08\r\n] 2006.145.18:07:37.50#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.18:07:37.50#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.18:07:37.50#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.18:07:37.50#ibcon#ireg 7 cls_cnt 0 2006.145.18:07:37.50#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.18:07:37.62#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.18:07:37.62#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.18:07:37.64#ibcon#[25=USB\r\n] 2006.145.18:07:37.67#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.18:07:37.67#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.18:07:37.67#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.18:07:37.67#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.18:07:37.67$vck44/valo=4,624.99 2006.145.18:07:37.67#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.18:07:37.67#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.18:07:37.67#ibcon#ireg 17 cls_cnt 0 2006.145.18:07:37.67#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:07:37.67#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:07:37.67#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:07:37.69#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.18:07:37.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:07:37.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:07:37.73#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.18:07:37.73#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.18:07:37.73$vck44/va=4,7 2006.145.18:07:37.73#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.18:07:37.73#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.18:07:37.73#ibcon#ireg 11 cls_cnt 2 2006.145.18:07:37.73#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:07:37.79#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:07:37.79#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:07:37.81#ibcon#[25=AT04-07\r\n] 2006.145.18:07:37.84#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:07:37.84#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:07:37.84#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.18:07:37.84#ibcon#ireg 7 cls_cnt 0 2006.145.18:07:37.84#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:07:37.96#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:07:37.96#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:07:37.98#ibcon#[25=USB\r\n] 2006.145.18:07:38.01#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:07:38.01#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:07:38.01#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.18:07:38.01#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.18:07:38.01$vck44/valo=5,734.99 2006.145.18:07:38.01#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.18:07:38.01#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.18:07:38.01#ibcon#ireg 17 cls_cnt 0 2006.145.18:07:38.01#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:07:38.01#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:07:38.01#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:07:38.03#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.18:07:38.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:07:38.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:07:38.07#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.18:07:38.07#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.18:07:38.07$vck44/va=5,4 2006.145.18:07:38.07#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.18:07:38.07#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.18:07:38.07#ibcon#ireg 11 cls_cnt 2 2006.145.18:07:38.07#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:07:38.13#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:07:38.13#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:07:38.15#ibcon#[25=AT05-04\r\n] 2006.145.18:07:38.18#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:07:38.18#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:07:38.18#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.18:07:38.18#ibcon#ireg 7 cls_cnt 0 2006.145.18:07:38.18#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:07:38.30#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:07:38.30#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:07:38.32#ibcon#[25=USB\r\n] 2006.145.18:07:38.35#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:07:38.35#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:07:38.35#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.18:07:38.35#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.18:07:38.35$vck44/valo=6,814.99 2006.145.18:07:38.35#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.18:07:38.35#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.18:07:38.35#ibcon#ireg 17 cls_cnt 0 2006.145.18:07:38.35#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.18:07:38.35#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.18:07:38.35#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.18:07:38.37#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.18:07:38.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.18:07:38.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.18:07:38.41#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.18:07:38.41#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.18:07:38.41$vck44/va=6,4 2006.145.18:07:38.41#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.18:07:38.41#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.18:07:38.41#ibcon#ireg 11 cls_cnt 2 2006.145.18:07:38.41#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.18:07:38.47#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.18:07:38.47#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.18:07:38.49#ibcon#[25=AT06-04\r\n] 2006.145.18:07:38.52#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.18:07:38.52#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.18:07:38.52#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.18:07:38.52#ibcon#ireg 7 cls_cnt 0 2006.145.18:07:38.52#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.18:07:38.64#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.18:07:38.64#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.18:07:38.66#ibcon#[25=USB\r\n] 2006.145.18:07:38.69#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.18:07:38.69#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.18:07:38.69#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.18:07:38.69#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.18:07:38.69$vck44/valo=7,864.99 2006.145.18:07:38.69#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.18:07:38.69#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.18:07:38.69#ibcon#ireg 17 cls_cnt 0 2006.145.18:07:38.69#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:07:38.69#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:07:38.69#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:07:38.71#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.18:07:38.75#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:07:38.75#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:07:38.75#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.18:07:38.75#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.18:07:38.75$vck44/va=7,4 2006.145.18:07:38.75#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.18:07:38.75#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.18:07:38.75#ibcon#ireg 11 cls_cnt 2 2006.145.18:07:38.75#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:07:38.81#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:07:38.81#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:07:38.83#ibcon#[25=AT07-04\r\n] 2006.145.18:07:38.86#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:07:38.86#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:07:38.86#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.18:07:38.86#ibcon#ireg 7 cls_cnt 0 2006.145.18:07:38.86#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:07:38.98#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:07:38.98#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:07:39.00#ibcon#[25=USB\r\n] 2006.145.18:07:39.03#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:07:39.03#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:07:39.03#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.18:07:39.03#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.18:07:39.03$vck44/valo=8,884.99 2006.145.18:07:39.03#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.18:07:39.03#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.18:07:39.03#ibcon#ireg 17 cls_cnt 0 2006.145.18:07:39.03#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:07:39.03#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:07:39.03#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:07:39.05#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.18:07:39.09#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:07:39.09#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:07:39.09#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.18:07:39.09#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.18:07:39.09$vck44/va=8,4 2006.145.18:07:39.09#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.18:07:39.09#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.18:07:39.09#ibcon#ireg 11 cls_cnt 2 2006.145.18:07:39.09#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:07:39.15#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:07:39.15#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:07:39.17#ibcon#[25=AT08-04\r\n] 2006.145.18:07:39.20#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:07:39.20#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:07:39.20#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.18:07:39.20#ibcon#ireg 7 cls_cnt 0 2006.145.18:07:39.20#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:07:39.32#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:07:39.32#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:07:39.34#ibcon#[25=USB\r\n] 2006.145.18:07:39.37#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:07:39.37#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:07:39.37#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.18:07:39.37#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.18:07:39.37$vck44/vblo=1,629.99 2006.145.18:07:39.37#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.18:07:39.37#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.18:07:39.37#ibcon#ireg 17 cls_cnt 0 2006.145.18:07:39.37#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.18:07:39.37#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.18:07:39.37#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.18:07:39.39#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.18:07:39.43#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.18:07:39.43#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.18:07:39.43#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.18:07:39.43#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.18:07:39.43$vck44/vb=1,3 2006.145.18:07:39.43#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.18:07:39.43#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.18:07:39.43#ibcon#ireg 11 cls_cnt 2 2006.145.18:07:39.43#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.18:07:39.43#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.18:07:39.43#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.18:07:39.45#ibcon#[27=AT01-03\r\n] 2006.145.18:07:39.48#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.18:07:39.48#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.18:07:39.48#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.18:07:39.48#ibcon#ireg 7 cls_cnt 0 2006.145.18:07:39.48#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.18:07:39.60#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.18:07:39.60#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.18:07:39.62#ibcon#[27=USB\r\n] 2006.145.18:07:39.65#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.18:07:39.65#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.18:07:39.65#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.18:07:39.65#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.18:07:39.65$vck44/vblo=2,634.99 2006.145.18:07:39.65#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.18:07:39.65#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.18:07:39.65#ibcon#ireg 17 cls_cnt 0 2006.145.18:07:39.65#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.18:07:39.65#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.18:07:39.65#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.18:07:39.67#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.18:07:39.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.18:07:39.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.18:07:39.71#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.18:07:39.71#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.18:07:39.71$vck44/vb=2,4 2006.145.18:07:39.71#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.18:07:39.71#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.18:07:39.71#ibcon#ireg 11 cls_cnt 2 2006.145.18:07:39.71#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.18:07:39.77#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.18:07:39.77#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.18:07:39.79#ibcon#[27=AT02-04\r\n] 2006.145.18:07:39.82#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.18:07:39.82#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.18:07:39.82#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.18:07:39.82#ibcon#ireg 7 cls_cnt 0 2006.145.18:07:39.82#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.18:07:39.94#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.18:07:39.94#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.18:07:39.96#ibcon#[27=USB\r\n] 2006.145.18:07:39.99#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.18:07:39.99#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.18:07:39.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.18:07:39.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.18:07:39.99$vck44/vblo=3,649.99 2006.145.18:07:39.99#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.18:07:39.99#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.18:07:39.99#ibcon#ireg 17 cls_cnt 0 2006.145.18:07:39.99#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:07:39.99#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:07:39.99#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:07:40.01#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.18:07:40.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:07:40.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:07:40.05#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.18:07:40.05#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.18:07:40.05$vck44/vb=3,4 2006.145.18:07:40.05#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.18:07:40.05#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.18:07:40.05#ibcon#ireg 11 cls_cnt 2 2006.145.18:07:40.05#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:07:40.11#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:07:40.11#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:07:40.13#ibcon#[27=AT03-04\r\n] 2006.145.18:07:40.16#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:07:40.16#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:07:40.16#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.18:07:40.16#ibcon#ireg 7 cls_cnt 0 2006.145.18:07:40.16#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:07:40.28#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:07:40.28#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:07:40.30#ibcon#[27=USB\r\n] 2006.145.18:07:40.30#abcon#<5=/05 0.9 1.9 15.68 911019.8\r\n> 2006.145.18:07:40.32#abcon#{5=INTERFACE CLEAR} 2006.145.18:07:40.33#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:07:40.33#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:07:40.33#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.18:07:40.33#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.18:07:40.33$vck44/vblo=4,679.99 2006.145.18:07:40.33#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.18:07:40.33#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.18:07:40.33#ibcon#ireg 17 cls_cnt 0 2006.145.18:07:40.33#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:07:40.33#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:07:40.33#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:07:40.35#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.18:07:40.38#abcon#[5=S1D000X0/0*\r\n] 2006.145.18:07:40.39#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:07:40.39#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:07:40.39#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.18:07:40.39#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.18:07:40.39$vck44/vb=4,4 2006.145.18:07:40.39#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.18:07:40.39#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.18:07:40.39#ibcon#ireg 11 cls_cnt 2 2006.145.18:07:40.39#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:07:40.45#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:07:40.45#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:07:40.47#ibcon#[27=AT04-04\r\n] 2006.145.18:07:40.50#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:07:40.50#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:07:40.50#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.18:07:40.50#ibcon#ireg 7 cls_cnt 0 2006.145.18:07:40.50#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:07:40.62#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:07:40.62#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:07:40.64#ibcon#[27=USB\r\n] 2006.145.18:07:40.67#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:07:40.67#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:07:40.67#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.18:07:40.67#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.18:07:40.67$vck44/vblo=5,709.99 2006.145.18:07:40.67#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.18:07:40.67#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.18:07:40.67#ibcon#ireg 17 cls_cnt 0 2006.145.18:07:40.67#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:07:40.67#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:07:40.67#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:07:40.69#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.18:07:40.73#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:07:40.73#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:07:40.73#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.18:07:40.73#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.18:07:40.73$vck44/vb=5,4 2006.145.18:07:40.73#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.18:07:40.73#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.18:07:40.73#ibcon#ireg 11 cls_cnt 2 2006.145.18:07:40.73#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:07:40.79#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:07:40.79#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:07:40.81#ibcon#[27=AT05-04\r\n] 2006.145.18:07:40.84#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:07:40.84#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:07:40.84#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.18:07:40.84#ibcon#ireg 7 cls_cnt 0 2006.145.18:07:40.84#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:07:40.96#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:07:40.96#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:07:40.98#ibcon#[27=USB\r\n] 2006.145.18:07:41.01#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:07:41.01#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:07:41.01#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.18:07:41.01#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.18:07:41.01$vck44/vblo=6,719.99 2006.145.18:07:41.01#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.18:07:41.01#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.18:07:41.01#ibcon#ireg 17 cls_cnt 0 2006.145.18:07:41.01#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.18:07:41.01#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.18:07:41.01#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.18:07:41.03#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.18:07:41.07#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.18:07:41.07#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.18:07:41.07#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.18:07:41.07#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.18:07:41.07$vck44/vb=6,4 2006.145.18:07:41.07#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.18:07:41.07#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.18:07:41.07#ibcon#ireg 11 cls_cnt 2 2006.145.18:07:41.07#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.18:07:41.13#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.18:07:41.13#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.18:07:41.15#ibcon#[27=AT06-04\r\n] 2006.145.18:07:41.18#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.18:07:41.18#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.18:07:41.18#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.18:07:41.18#ibcon#ireg 7 cls_cnt 0 2006.145.18:07:41.18#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.18:07:41.30#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.18:07:41.30#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.18:07:41.32#ibcon#[27=USB\r\n] 2006.145.18:07:41.35#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.18:07:41.35#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.18:07:41.35#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.18:07:41.35#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.18:07:41.35$vck44/vblo=7,734.99 2006.145.18:07:41.35#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.18:07:41.35#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.18:07:41.35#ibcon#ireg 17 cls_cnt 0 2006.145.18:07:41.35#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:07:41.35#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:07:41.35#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:07:41.37#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.18:07:41.41#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:07:41.41#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:07:41.41#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.18:07:41.41#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.18:07:41.41$vck44/vb=7,4 2006.145.18:07:41.41#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.18:07:41.41#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.18:07:41.41#ibcon#ireg 11 cls_cnt 2 2006.145.18:07:41.41#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:07:41.47#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:07:41.47#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:07:41.49#ibcon#[27=AT07-04\r\n] 2006.145.18:07:41.52#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:07:41.52#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:07:41.52#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.18:07:41.52#ibcon#ireg 7 cls_cnt 0 2006.145.18:07:41.52#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:07:41.64#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:07:41.64#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:07:41.66#ibcon#[27=USB\r\n] 2006.145.18:07:41.69#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:07:41.69#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:07:41.69#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.18:07:41.69#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.18:07:41.69$vck44/vblo=8,744.99 2006.145.18:07:41.69#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.18:07:41.69#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.18:07:41.69#ibcon#ireg 17 cls_cnt 0 2006.145.18:07:41.69#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:07:41.69#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:07:41.69#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:07:41.71#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.18:07:41.75#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:07:41.75#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:07:41.75#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.18:07:41.75#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.18:07:41.75$vck44/vb=8,4 2006.145.18:07:41.75#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.18:07:41.75#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.18:07:41.75#ibcon#ireg 11 cls_cnt 2 2006.145.18:07:41.75#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:07:41.81#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:07:41.81#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:07:41.83#ibcon#[27=AT08-04\r\n] 2006.145.18:07:41.86#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:07:41.86#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:07:41.86#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.18:07:41.86#ibcon#ireg 7 cls_cnt 0 2006.145.18:07:41.86#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:07:41.98#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:07:41.98#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:07:42.00#ibcon#[27=USB\r\n] 2006.145.18:07:42.03#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:07:42.03#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:07:42.03#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.18:07:42.03#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.18:07:42.03$vck44/vabw=wide 2006.145.18:07:42.03#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.18:07:42.03#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.18:07:42.03#ibcon#ireg 8 cls_cnt 0 2006.145.18:07:42.03#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.18:07:42.03#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.18:07:42.03#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.18:07:42.05#ibcon#[25=BW32\r\n] 2006.145.18:07:42.08#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.18:07:42.08#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.18:07:42.08#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.18:07:42.08#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.18:07:42.08$vck44/vbbw=wide 2006.145.18:07:42.08#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.18:07:42.08#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.18:07:42.08#ibcon#ireg 8 cls_cnt 0 2006.145.18:07:42.08#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.18:07:42.15#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.18:07:42.15#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.18:07:42.17#ibcon#[27=BW32\r\n] 2006.145.18:07:42.20#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.18:07:42.20#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.18:07:42.20#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.18:07:42.20#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.18:07:42.20$setupk4/ifdk4 2006.145.18:07:42.20$ifdk4/lo= 2006.145.18:07:42.20$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.18:07:42.20$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.18:07:42.20$ifdk4/patch= 2006.145.18:07:42.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.18:07:42.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.18:07:42.20$setupk4/!*+20s 2006.145.18:07:50.47#abcon#<5=/05 0.9 1.9 15.68 911019.8\r\n> 2006.145.18:07:50.49#abcon#{5=INTERFACE CLEAR} 2006.145.18:07:50.57#abcon#[5=S1D000X0/0*\r\n] 2006.145.18:07:56.68$setupk4/"tpicd 2006.145.18:07:56.68$setupk4/echo=off 2006.145.18:07:56.68$setupk4/xlog=off 2006.145.18:07:56.68:!2006.145.18:13:45 2006.145.18:08:07.14#trakl#Source acquired 2006.145.18:08:07.14#flagr#flagr/antenna,acquired 2006.145.18:13:45.00:preob 2006.145.18:13:45.14/onsource/TRACKING 2006.145.18:13:45.14:!2006.145.18:13:55 2006.145.18:13:55.00:"tape 2006.145.18:13:55.00:"st=record 2006.145.18:13:55.00:data_valid=on 2006.145.18:13:55.00:midob 2006.145.18:13:55.14/onsource/TRACKING 2006.145.18:13:55.14/wx/15.70,1019.7,92 2006.145.18:13:55.37/cable/+6.5470E-03 2006.145.18:13:56.46/va/01,08,usb,yes,29,31 2006.145.18:13:56.46/va/02,07,usb,yes,31,32 2006.145.18:13:56.46/va/03,08,usb,yes,28,29 2006.145.18:13:56.46/va/04,07,usb,yes,32,33 2006.145.18:13:56.46/va/05,04,usb,yes,28,28 2006.145.18:13:56.46/va/06,04,usb,yes,31,31 2006.145.18:13:56.46/va/07,04,usb,yes,32,33 2006.145.18:13:56.46/va/08,04,usb,yes,27,32 2006.145.18:13:56.69/valo/01,524.99,yes,locked 2006.145.18:13:56.69/valo/02,534.99,yes,locked 2006.145.18:13:56.69/valo/03,564.99,yes,locked 2006.145.18:13:56.69/valo/04,624.99,yes,locked 2006.145.18:13:56.69/valo/05,734.99,yes,locked 2006.145.18:13:56.69/valo/06,814.99,yes,locked 2006.145.18:13:56.69/valo/07,864.99,yes,locked 2006.145.18:13:56.69/valo/08,884.99,yes,locked 2006.145.18:13:57.78/vb/01,03,usb,yes,36,34 2006.145.18:13:57.78/vb/02,04,usb,yes,32,32 2006.145.18:13:57.78/vb/03,04,usb,yes,29,32 2006.145.18:13:57.78/vb/04,04,usb,yes,33,32 2006.145.18:13:57.78/vb/05,04,usb,yes,25,28 2006.145.18:13:57.78/vb/06,04,usb,yes,30,26 2006.145.18:13:57.78/vb/07,04,usb,yes,30,29 2006.145.18:13:57.78/vb/08,04,usb,yes,27,31 2006.145.18:13:58.01/vblo/01,629.99,yes,locked 2006.145.18:13:58.01/vblo/02,634.99,yes,locked 2006.145.18:13:58.01/vblo/03,649.99,yes,locked 2006.145.18:13:58.01/vblo/04,679.99,yes,locked 2006.145.18:13:58.01/vblo/05,709.99,yes,locked 2006.145.18:13:58.01/vblo/06,719.99,yes,locked 2006.145.18:13:58.01/vblo/07,734.99,yes,locked 2006.145.18:13:58.01/vblo/08,744.99,yes,locked 2006.145.18:13:58.16/vabw/8 2006.145.18:13:58.31/vbbw/8 2006.145.18:13:58.40/xfe/off,on,15.2 2006.145.18:13:58.78/ifatt/23,28,28,28 2006.145.18:13:59.08/fmout-gps/S +4.6E-08 2006.145.18:13:59.12:!2006.145.18:17:05 2006.145.18:17:05.02:data_valid=off 2006.145.18:17:05.02:"et 2006.145.18:17:05.02:!+3s 2006.145.18:17:08.04:"tape 2006.145.18:17:08.04:postob 2006.145.18:17:08.13/cable/+6.5501E-03 2006.145.18:17:08.14/wx/15.71,1019.7,91 2006.145.18:17:08.21/fmout-gps/S +4.5E-08 2006.145.18:17:08.21:scan_name=145-1819,jd0605,40 2006.145.18:17:08.21:source=3c454.3,225357.75,160853.6,2000.0,ccw 2006.145.18:17:10.14#flagr#flagr/antenna,new-source 2006.145.18:17:10.14:checkk5 2006.145.18:17:10.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.18:17:11.04/chk_autoobs//k5ts2/ autoobs is running! 2006.145.18:17:11.48/chk_autoobs//k5ts3/ autoobs is running! 2006.145.18:17:11.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.18:17:12.33/chk_obsdata//k5ts1/T1451813??a.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.18:17:12.76/chk_obsdata//k5ts2/T1451813??b.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.18:17:13.21/chk_obsdata//k5ts3/T1451813??c.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.18:17:13.65/chk_obsdata//k5ts4/T1451813??d.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.18:17:14.42/k5log//k5ts1_log_newline 2006.145.18:17:15.16/k5log//k5ts2_log_newline 2006.145.18:17:15.92/k5log//k5ts3_log_newline 2006.145.18:17:16.65/k5log//k5ts4_log_newline 2006.145.18:17:16.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.18:17:16.67:setupk4=1 2006.145.18:17:16.67$setupk4/echo=on 2006.145.18:17:16.67$setupk4/pcalon 2006.145.18:17:16.67$pcalon/"no phase cal control is implemented here 2006.145.18:17:16.67$setupk4/"tpicd=stop 2006.145.18:17:16.67$setupk4/"rec=synch_on 2006.145.18:17:16.67$setupk4/"rec_mode=128 2006.145.18:17:16.68$setupk4/!* 2006.145.18:17:16.68$setupk4/recpk4 2006.145.18:17:16.68$recpk4/recpatch= 2006.145.18:17:16.68$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.18:17:16.68$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.18:17:16.68$setupk4/vck44 2006.145.18:17:16.68$vck44/valo=1,524.99 2006.145.18:17:16.68#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.18:17:16.68#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.18:17:16.68#ibcon#ireg 17 cls_cnt 0 2006.145.18:17:16.68#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:17:16.68#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:17:16.68#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:17:16.72#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.18:17:16.76#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:17:16.76#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:17:16.76#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.18:17:16.76#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.18:17:16.76$vck44/va=1,8 2006.145.18:17:16.77#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.18:17:16.77#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.18:17:16.77#ibcon#ireg 11 cls_cnt 2 2006.145.18:17:16.77#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.18:17:16.77#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.18:17:16.77#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.18:17:16.78#ibcon#[25=AT01-08\r\n] 2006.145.18:17:16.81#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.18:17:16.81#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.18:17:16.81#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.18:17:16.81#ibcon#ireg 7 cls_cnt 0 2006.145.18:17:16.81#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.18:17:16.94#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.18:17:16.94#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.18:17:16.96#ibcon#[25=USB\r\n] 2006.145.18:17:16.98#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.18:17:16.98#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.18:17:16.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.18:17:16.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.18:17:16.99$vck44/valo=2,534.99 2006.145.18:17:16.99#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.18:17:16.99#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.18:17:16.99#ibcon#ireg 17 cls_cnt 0 2006.145.18:17:16.99#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:17:16.99#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:17:16.99#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:17:17.02#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.18:17:17.05#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:17:17.05#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:17:17.05#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.18:17:17.05#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.18:17:17.06$vck44/va=2,7 2006.145.18:17:17.06#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.18:17:17.06#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.18:17:17.06#ibcon#ireg 11 cls_cnt 2 2006.145.18:17:17.06#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.18:17:17.09#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.18:17:17.09#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.18:17:17.12#ibcon#[25=AT02-07\r\n] 2006.145.18:17:17.15#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.18:17:17.15#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.18:17:17.15#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.18:17:17.15#ibcon#ireg 7 cls_cnt 0 2006.145.18:17:17.15#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.18:17:17.26#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.18:17:17.26#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.18:17:17.28#ibcon#[25=USB\r\n] 2006.145.18:17:17.31#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.18:17:17.31#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.18:17:17.31#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.18:17:17.31#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.18:17:17.32$vck44/valo=3,564.99 2006.145.18:17:17.32#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.18:17:17.32#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.18:17:17.32#ibcon#ireg 17 cls_cnt 0 2006.145.18:17:17.32#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.18:17:17.32#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.18:17:17.32#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.18:17:17.33#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.18:17:17.37#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.18:17:17.37#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.18:17:17.37#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.18:17:17.37#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.18:17:17.37$vck44/va=3,8 2006.145.18:17:17.38#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.18:17:17.38#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.18:17:17.38#ibcon#ireg 11 cls_cnt 2 2006.145.18:17:17.38#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.18:17:17.42#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.18:17:17.42#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.18:17:17.44#ibcon#[25=AT03-08\r\n] 2006.145.18:17:17.47#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.18:17:17.47#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.18:17:17.47#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.18:17:17.47#ibcon#ireg 7 cls_cnt 0 2006.145.18:17:17.47#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.18:17:17.59#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.18:17:17.59#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.18:17:17.61#ibcon#[25=USB\r\n] 2006.145.18:17:17.64#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.18:17:17.64#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.18:17:17.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.18:17:17.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.18:17:17.64$vck44/valo=4,624.99 2006.145.18:17:17.65#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.18:17:17.65#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.18:17:17.65#ibcon#ireg 17 cls_cnt 0 2006.145.18:17:17.65#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:17:17.65#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:17:17.65#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:17:17.66#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.18:17:17.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:17:17.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:17:17.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.18:17:17.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.18:17:17.70$vck44/va=4,7 2006.145.18:17:17.71#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.18:17:17.71#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.18:17:17.71#ibcon#ireg 11 cls_cnt 2 2006.145.18:17:17.71#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.18:17:17.76#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.18:17:17.76#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.18:17:17.77#ibcon#[25=AT04-07\r\n] 2006.145.18:17:17.80#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.18:17:17.80#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.18:17:17.80#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.18:17:17.80#ibcon#ireg 7 cls_cnt 0 2006.145.18:17:17.80#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.18:17:17.92#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.18:17:17.92#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.18:17:17.94#ibcon#[25=USB\r\n] 2006.145.18:17:17.97#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.18:17:17.97#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.18:17:17.97#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.18:17:17.97#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.18:17:17.97$vck44/valo=5,734.99 2006.145.18:17:17.97#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.18:17:17.97#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.18:17:17.97#ibcon#ireg 17 cls_cnt 0 2006.145.18:17:17.98#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:17:17.98#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:17:17.98#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:17:17.99#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.18:17:18.03#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:17:18.03#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:17:18.03#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.18:17:18.03#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.18:17:18.03$vck44/va=5,4 2006.145.18:17:18.03#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.18:17:18.03#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.18:17:18.04#ibcon#ireg 11 cls_cnt 2 2006.145.18:17:18.04#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:17:18.08#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:17:18.08#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:17:18.10#ibcon#[25=AT05-04\r\n] 2006.145.18:17:18.13#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:17:18.13#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:17:18.13#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.18:17:18.13#ibcon#ireg 7 cls_cnt 0 2006.145.18:17:18.13#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:17:18.25#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:17:18.25#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:17:18.27#ibcon#[25=USB\r\n] 2006.145.18:17:18.32#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:17:18.32#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:17:18.32#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.18:17:18.32#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.18:17:18.32$vck44/valo=6,814.99 2006.145.18:17:18.32#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.18:17:18.32#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.18:17:18.32#ibcon#ireg 17 cls_cnt 0 2006.145.18:17:18.32#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:17:18.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:17:18.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:17:18.33#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.18:17:18.37#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:17:18.37#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:17:18.37#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.18:17:18.37#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.18:17:18.38$vck44/va=6,4 2006.145.18:17:18.38#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.18:17:18.38#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.18:17:18.38#ibcon#ireg 11 cls_cnt 2 2006.145.18:17:18.38#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:17:18.43#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:17:18.43#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:17:18.45#ibcon#[25=AT06-04\r\n] 2006.145.18:17:18.48#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:17:18.48#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:17:18.48#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.18:17:18.48#ibcon#ireg 7 cls_cnt 0 2006.145.18:17:18.48#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:17:18.60#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:17:18.60#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:17:18.62#ibcon#[25=USB\r\n] 2006.145.18:17:18.65#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:17:18.65#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:17:18.65#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.18:17:18.65#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.18:17:18.66$vck44/valo=7,864.99 2006.145.18:17:18.66#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.18:17:18.66#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.18:17:18.66#ibcon#ireg 17 cls_cnt 0 2006.145.18:17:18.66#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:17:18.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:17:18.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:17:18.67#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.18:17:18.71#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:17:18.71#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:17:18.71#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.18:17:18.71#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.18:17:18.71$vck44/va=7,4 2006.145.18:17:18.72#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.18:17:18.72#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.18:17:18.72#ibcon#ireg 11 cls_cnt 2 2006.145.18:17:18.72#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:17:18.76#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:17:18.76#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:17:18.78#ibcon#[25=AT07-04\r\n] 2006.145.18:17:18.81#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:17:18.81#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:17:18.81#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.18:17:18.81#ibcon#ireg 7 cls_cnt 0 2006.145.18:17:18.81#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:17:18.93#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:17:18.93#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:17:18.95#ibcon#[25=USB\r\n] 2006.145.18:17:18.98#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:17:18.98#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:17:18.98#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.18:17:18.98#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.18:17:18.99$vck44/valo=8,884.99 2006.145.18:17:18.99#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.18:17:18.99#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.18:17:18.99#ibcon#ireg 17 cls_cnt 0 2006.145.18:17:18.99#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:17:18.99#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:17:18.99#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:17:19.00#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.18:17:19.04#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:17:19.04#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:17:19.04#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.18:17:19.04#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.18:17:19.05$vck44/va=8,4 2006.145.18:17:19.05#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.18:17:19.05#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.18:17:19.05#ibcon#ireg 11 cls_cnt 2 2006.145.18:17:19.05#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.18:17:19.09#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.18:17:19.09#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.18:17:19.11#ibcon#[25=AT08-04\r\n] 2006.145.18:17:19.14#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.18:17:19.14#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.18:17:19.14#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.18:17:19.14#ibcon#ireg 7 cls_cnt 0 2006.145.18:17:19.14#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.18:17:19.26#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.18:17:19.26#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.18:17:19.28#ibcon#[25=USB\r\n] 2006.145.18:17:19.31#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.18:17:19.31#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.18:17:19.31#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.18:17:19.31#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.18:17:19.31$vck44/vblo=1,629.99 2006.145.18:17:19.32#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.18:17:19.32#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.18:17:19.32#ibcon#ireg 17 cls_cnt 0 2006.145.18:17:19.32#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:17:19.32#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:17:19.32#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:17:19.33#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.18:17:19.37#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:17:19.37#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:17:19.37#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.18:17:19.37#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.18:17:19.37$vck44/vb=1,3 2006.145.18:17:19.38#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.18:17:19.38#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.18:17:19.38#ibcon#ireg 11 cls_cnt 2 2006.145.18:17:19.38#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.18:17:19.38#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.18:17:19.38#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.18:17:19.40#ibcon#[27=AT01-03\r\n] 2006.145.18:17:19.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.18:17:19.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.18:17:19.42#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.18:17:19.42#ibcon#ireg 7 cls_cnt 0 2006.145.18:17:19.42#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.18:17:19.54#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.18:17:19.54#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.18:17:19.56#ibcon#[27=USB\r\n] 2006.145.18:17:19.59#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.18:17:19.59#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.18:17:19.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.18:17:19.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.18:17:19.60$vck44/vblo=2,634.99 2006.145.18:17:19.60#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.18:17:19.60#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.18:17:19.60#ibcon#ireg 17 cls_cnt 0 2006.145.18:17:19.60#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:17:19.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:17:19.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:17:19.61#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.18:17:19.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:17:19.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:17:19.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.18:17:19.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.18:17:19.66$vck44/vb=2,4 2006.145.18:17:19.66#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.18:17:19.66#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.18:17:19.66#ibcon#ireg 11 cls_cnt 2 2006.145.18:17:19.66#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.18:17:19.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.18:17:19.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.18:17:19.72#ibcon#[27=AT02-04\r\n] 2006.145.18:17:19.75#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.18:17:19.75#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.18:17:19.75#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.18:17:19.75#ibcon#ireg 7 cls_cnt 0 2006.145.18:17:19.75#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.18:17:19.87#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.18:17:19.87#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.18:17:19.89#ibcon#[27=USB\r\n] 2006.145.18:17:19.92#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.18:17:19.92#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.18:17:19.92#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.18:17:19.92#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.18:17:19.92$vck44/vblo=3,649.99 2006.145.18:17:19.93#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.18:17:19.93#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.18:17:19.93#ibcon#ireg 17 cls_cnt 0 2006.145.18:17:19.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:17:19.93#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:17:19.93#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:17:19.94#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.18:17:19.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:17:19.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:17:19.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.18:17:19.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.18:17:19.98$vck44/vb=3,4 2006.145.18:17:19.99#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.18:17:19.99#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.18:17:19.99#ibcon#ireg 11 cls_cnt 2 2006.145.18:17:19.99#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:17:20.00#abcon#<5=/05 0.9 1.6 15.71 911019.7\r\n> 2006.145.18:17:20.02#abcon#{5=INTERFACE CLEAR} 2006.145.18:17:20.03#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:17:20.03#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:17:20.05#ibcon#[27=AT03-04\r\n] 2006.145.18:17:20.08#abcon#[5=S1D000X0/0*\r\n] 2006.145.18:17:20.08#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:17:20.08#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:17:20.08#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.18:17:20.08#ibcon#ireg 7 cls_cnt 0 2006.145.18:17:20.08#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:17:20.20#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:17:20.20#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:17:20.22#ibcon#[27=USB\r\n] 2006.145.18:17:20.25#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:17:20.25#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:17:20.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.18:17:20.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.18:17:20.25$vck44/vblo=4,679.99 2006.145.18:17:20.26#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.18:17:20.26#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.18:17:20.26#ibcon#ireg 17 cls_cnt 0 2006.145.18:17:20.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:17:20.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:17:20.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:17:20.27#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.18:17:20.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:17:20.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:17:20.31#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.18:17:20.31#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.18:17:20.31$vck44/vb=4,4 2006.145.18:17:20.32#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.18:17:20.32#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.18:17:20.32#ibcon#ireg 11 cls_cnt 2 2006.145.18:17:20.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.18:17:20.36#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.18:17:20.36#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.18:17:20.38#ibcon#[27=AT04-04\r\n] 2006.145.18:17:20.41#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.18:17:20.41#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.18:17:20.41#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.18:17:20.41#ibcon#ireg 7 cls_cnt 0 2006.145.18:17:20.41#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.18:17:20.53#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.18:17:20.53#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.18:17:20.55#ibcon#[27=USB\r\n] 2006.145.18:17:20.58#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.18:17:20.58#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.18:17:20.58#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.18:17:20.58#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.18:17:20.58$vck44/vblo=5,709.99 2006.145.18:17:20.58#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.18:17:20.58#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.18:17:20.59#ibcon#ireg 17 cls_cnt 0 2006.145.18:17:20.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:17:20.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:17:20.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:17:20.60#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.18:17:20.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:17:20.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:17:20.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.18:17:20.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.18:17:20.64$vck44/vb=5,4 2006.145.18:17:20.64#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.18:17:20.65#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.18:17:20.65#ibcon#ireg 11 cls_cnt 2 2006.145.18:17:20.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:17:20.69#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:17:20.69#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:17:20.71#ibcon#[27=AT05-04\r\n] 2006.145.18:17:20.74#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:17:20.74#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:17:20.74#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.18:17:20.74#ibcon#ireg 7 cls_cnt 0 2006.145.18:17:20.74#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:17:20.86#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:17:20.86#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:17:20.88#ibcon#[27=USB\r\n] 2006.145.18:17:20.91#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:17:20.91#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:17:20.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.18:17:20.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.18:17:20.92$vck44/vblo=6,719.99 2006.145.18:17:20.92#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.18:17:20.92#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.18:17:20.92#ibcon#ireg 17 cls_cnt 0 2006.145.18:17:20.92#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:17:20.92#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:17:20.92#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:17:20.93#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.18:17:20.97#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:17:20.97#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:17:20.97#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.18:17:20.97#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.18:17:20.98$vck44/vb=6,4 2006.145.18:17:20.98#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.18:17:20.98#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.18:17:20.98#ibcon#ireg 11 cls_cnt 2 2006.145.18:17:20.98#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:17:21.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:17:21.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:17:21.04#ibcon#[27=AT06-04\r\n] 2006.145.18:17:21.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:17:21.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:17:21.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.18:17:21.07#ibcon#ireg 7 cls_cnt 0 2006.145.18:17:21.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:17:21.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:17:21.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:17:21.21#ibcon#[27=USB\r\n] 2006.145.18:17:21.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:17:21.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:17:21.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.18:17:21.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.18:17:21.25$vck44/vblo=7,734.99 2006.145.18:17:21.25#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.18:17:21.25#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.18:17:21.25#ibcon#ireg 17 cls_cnt 0 2006.145.18:17:21.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:17:21.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:17:21.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:17:21.26#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.18:17:21.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:17:21.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:17:21.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.18:17:21.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.18:17:21.31$vck44/vb=7,4 2006.145.18:17:21.31#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.18:17:21.31#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.18:17:21.31#ibcon#ireg 11 cls_cnt 2 2006.145.18:17:21.31#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:17:21.35#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:17:21.35#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:17:21.37#ibcon#[27=AT07-04\r\n] 2006.145.18:17:21.40#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:17:21.40#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:17:21.40#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.18:17:21.40#ibcon#ireg 7 cls_cnt 0 2006.145.18:17:21.40#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:17:21.52#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:17:21.52#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:17:21.54#ibcon#[27=USB\r\n] 2006.145.18:17:21.57#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:17:21.57#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:17:21.57#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.18:17:21.57#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.18:17:21.57$vck44/vblo=8,744.99 2006.145.18:17:21.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.18:17:21.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.18:17:21.58#ibcon#ireg 17 cls_cnt 0 2006.145.18:17:21.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:17:21.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:17:21.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:17:21.59#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.18:17:21.63#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:17:21.63#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:17:21.63#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.18:17:21.63#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.18:17:21.64$vck44/vb=8,4 2006.145.18:17:21.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.18:17:21.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.18:17:21.64#ibcon#ireg 11 cls_cnt 2 2006.145.18:17:21.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.18:17:21.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.18:17:21.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.18:17:21.70#ibcon#[27=AT08-04\r\n] 2006.145.18:17:21.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.18:17:21.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.18:17:21.73#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.18:17:21.73#ibcon#ireg 7 cls_cnt 0 2006.145.18:17:21.73#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.18:17:21.85#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.18:17:21.85#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.18:17:21.87#ibcon#[27=USB\r\n] 2006.145.18:17:21.90#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.18:17:21.90#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.18:17:21.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.18:17:21.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.18:17:21.90$vck44/vabw=wide 2006.145.18:17:21.90#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.18:17:21.90#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.18:17:21.91#ibcon#ireg 8 cls_cnt 0 2006.145.18:17:21.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:17:21.91#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:17:21.91#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:17:21.92#ibcon#[25=BW32\r\n] 2006.145.18:17:21.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:17:21.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:17:21.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.18:17:21.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.18:17:21.95$vck44/vbbw=wide 2006.145.18:17:21.95#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.18:17:21.95#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.18:17:21.95#ibcon#ireg 8 cls_cnt 0 2006.145.18:17:21.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.18:17:22.02#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.18:17:22.02#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.18:17:22.04#ibcon#[27=BW32\r\n] 2006.145.18:17:22.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.18:17:22.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.18:17:22.07#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.18:17:22.07#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.18:17:22.08$setupk4/ifdk4 2006.145.18:17:22.08$ifdk4/lo= 2006.145.18:17:22.08$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.18:17:22.08$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.18:17:22.08$ifdk4/patch= 2006.145.18:17:22.08$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.18:17:22.08$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.18:17:22.08$setupk4/!*+20s 2006.145.18:17:28.13#trakl#Source acquired 2006.145.18:17:29.14#flagr#flagr/antenna,acquired 2006.145.18:17:30.29#abcon#<5=/05 1.0 1.6 15.71 911019.7\r\n> 2006.145.18:17:30.31#abcon#{5=INTERFACE CLEAR} 2006.145.18:17:30.37#abcon#[5=S1D000X0/0*\r\n] 2006.145.18:17:36.70$setupk4/"tpicd 2006.145.18:17:36.70$setupk4/echo=off 2006.145.18:17:36.70$setupk4/xlog=off 2006.145.18:17:36.70:!2006.145.18:19:31 2006.145.18:19:31.00:preob 2006.145.18:19:31.14/onsource/TRACKING 2006.145.18:19:31.14:!2006.145.18:19:41 2006.145.18:19:41.00:"tape 2006.145.18:19:41.00:"st=record 2006.145.18:19:41.00:data_valid=on 2006.145.18:19:41.00:midob 2006.145.18:19:41.14/onsource/TRACKING 2006.145.18:19:41.15/wx/15.71,1019.7,91 2006.145.18:19:41.33/cable/+6.5474E-03 2006.145.18:19:42.42/va/01,08,usb,yes,29,31 2006.145.18:19:42.42/va/02,07,usb,yes,31,32 2006.145.18:19:42.42/va/03,08,usb,yes,28,29 2006.145.18:19:42.42/va/04,07,usb,yes,32,33 2006.145.18:19:42.42/va/05,04,usb,yes,28,28 2006.145.18:19:42.42/va/06,04,usb,yes,31,31 2006.145.18:19:42.42/va/07,04,usb,yes,31,33 2006.145.18:19:42.42/va/08,04,usb,yes,27,32 2006.145.18:19:42.65/valo/01,524.99,yes,locked 2006.145.18:19:42.65/valo/02,534.99,yes,locked 2006.145.18:19:42.65/valo/03,564.99,yes,locked 2006.145.18:19:42.65/valo/04,624.99,yes,locked 2006.145.18:19:42.65/valo/05,734.99,yes,locked 2006.145.18:19:42.65/valo/06,814.99,yes,locked 2006.145.18:19:42.65/valo/07,864.99,yes,locked 2006.145.18:19:42.65/valo/08,884.99,yes,locked 2006.145.18:19:43.74/vb/01,03,usb,yes,36,34 2006.145.18:19:43.74/vb/02,04,usb,yes,32,32 2006.145.18:19:43.74/vb/03,04,usb,yes,29,32 2006.145.18:19:43.74/vb/04,04,usb,yes,33,32 2006.145.18:19:43.74/vb/05,04,usb,yes,26,28 2006.145.18:19:43.74/vb/06,04,usb,yes,30,26 2006.145.18:19:43.74/vb/07,04,usb,yes,30,30 2006.145.18:19:43.74/vb/08,04,usb,yes,27,31 2006.145.18:19:43.97/vblo/01,629.99,yes,locked 2006.145.18:19:43.97/vblo/02,634.99,yes,locked 2006.145.18:19:43.97/vblo/03,649.99,yes,locked 2006.145.18:19:43.97/vblo/04,679.99,yes,locked 2006.145.18:19:43.97/vblo/05,709.99,yes,locked 2006.145.18:19:43.97/vblo/06,719.99,yes,locked 2006.145.18:19:43.97/vblo/07,734.99,yes,locked 2006.145.18:19:43.97/vblo/08,744.99,yes,locked 2006.145.18:19:44.12/vabw/8 2006.145.18:19:44.27/vbbw/8 2006.145.18:19:44.36/xfe/off,on,14.0 2006.145.18:19:44.73/ifatt/23,28,28,28 2006.145.18:19:45.07/fmout-gps/S +4.5E-08 2006.145.18:19:45.12:!2006.145.18:20:21 2006.145.18:20:21.01:data_valid=off 2006.145.18:20:21.02:"et 2006.145.18:20:21.02:!+3s 2006.145.18:20:24.05:"tape 2006.145.18:20:24.09:postob 2006.145.18:20:24.28/cable/+6.5494E-03 2006.145.18:20:24.29/wx/15.71,1019.7,91 2006.145.18:20:24.37/fmout-gps/S +4.4E-08 2006.145.18:20:24.37:scan_name=145-1822,jd0605,784 2006.145.18:20:24.37:source=1749+096,175132.82,093900.7,2000.0,ccw 2006.145.18:20:26.14#flagr#flagr/antenna,new-source 2006.145.18:20:26.15:checkk5 2006.145.18:20:26.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.18:20:27.06/chk_autoobs//k5ts2/ autoobs is running! 2006.145.18:20:27.49/chk_autoobs//k5ts3/ autoobs is running! 2006.145.18:20:27.91/chk_autoobs//k5ts4/ autoobs is running! 2006.145.18:20:28.33/chk_obsdata//k5ts1/T1451819??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.18:20:28.77/chk_obsdata//k5ts2/T1451819??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.18:20:29.23/chk_obsdata//k5ts3/T1451819??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.18:20:29.67/chk_obsdata//k5ts4/T1451819??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.18:20:30.44/k5log//k5ts1_log_newline 2006.145.18:20:31.17/k5log//k5ts2_log_newline 2006.145.18:20:31.92/k5log//k5ts3_log_newline 2006.145.18:20:32.66/k5log//k5ts4_log_newline 2006.145.18:20:32.68/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.18:20:32.68:setupk4=1 2006.145.18:20:32.68$setupk4/echo=on 2006.145.18:20:32.68$setupk4/pcalon 2006.145.18:20:32.68$pcalon/"no phase cal control is implemented here 2006.145.18:20:32.68$setupk4/"tpicd=stop 2006.145.18:20:32.68$setupk4/"rec=synch_on 2006.145.18:20:32.68$setupk4/"rec_mode=128 2006.145.18:20:32.68$setupk4/!* 2006.145.18:20:32.68$setupk4/recpk4 2006.145.18:20:32.69$recpk4/recpatch= 2006.145.18:20:32.69$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.18:20:32.69$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.18:20:32.69$setupk4/vck44 2006.145.18:20:32.69$vck44/valo=1,524.99 2006.145.18:20:32.69#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.18:20:32.69#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.18:20:32.69#ibcon#ireg 17 cls_cnt 0 2006.145.18:20:32.69#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.18:20:32.69#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.18:20:32.69#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.18:20:32.73#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.18:20:32.77#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.18:20:32.77#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.18:20:32.77#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.18:20:32.77#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.18:20:32.77$vck44/va=1,8 2006.145.18:20:32.77#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.18:20:32.77#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.18:20:32.77#ibcon#ireg 11 cls_cnt 2 2006.145.18:20:32.77#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.18:20:32.77#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.18:20:32.77#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.18:20:32.79#ibcon#[25=AT01-08\r\n] 2006.145.18:20:32.82#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.18:20:32.82#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.18:20:32.82#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.18:20:32.82#ibcon#ireg 7 cls_cnt 0 2006.145.18:20:32.82#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.18:20:32.94#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.18:20:32.94#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.18:20:32.98#ibcon#[25=USB\r\n] 2006.145.18:20:33.00#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.18:20:33.00#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.18:20:33.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.18:20:33.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.18:20:33.01$vck44/valo=2,534.99 2006.145.18:20:33.01#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.18:20:33.01#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.18:20:33.01#ibcon#ireg 17 cls_cnt 0 2006.145.18:20:33.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.18:20:33.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.18:20:33.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.18:20:33.02#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.18:20:33.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.18:20:33.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.18:20:33.07#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.18:20:33.07#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.18:20:33.07$vck44/va=2,7 2006.145.18:20:33.07#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.18:20:33.07#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.18:20:33.07#ibcon#ireg 11 cls_cnt 2 2006.145.18:20:33.07#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.18:20:33.11#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.18:20:33.11#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.18:20:33.14#ibcon#[25=AT02-07\r\n] 2006.145.18:20:33.16#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.18:20:33.16#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.18:20:33.16#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.18:20:33.16#ibcon#ireg 7 cls_cnt 0 2006.145.18:20:33.17#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.18:20:33.27#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.18:20:33.27#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.18:20:33.29#ibcon#[25=USB\r\n] 2006.145.18:20:33.32#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.18:20:33.32#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.18:20:33.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.18:20:33.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.18:20:33.32$vck44/valo=3,564.99 2006.145.18:20:33.32#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.18:20:33.32#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.18:20:33.32#ibcon#ireg 17 cls_cnt 0 2006.145.18:20:33.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:20:33.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:20:33.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:20:33.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.18:20:33.35#abcon#<5=/05 1.0 1.6 15.71 911019.8\r\n> 2006.145.18:20:33.37#abcon#{5=INTERFACE CLEAR} 2006.145.18:20:33.38#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:20:33.38#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:20:33.38#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.18:20:33.38#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.18:20:33.38$vck44/va=3,8 2006.145.18:20:33.38#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.18:20:33.38#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.18:20:33.38#ibcon#ireg 11 cls_cnt 2 2006.145.18:20:33.38#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.18:20:33.43#abcon#[5=S1D000X0/0*\r\n] 2006.145.18:20:33.44#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.18:20:33.44#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.18:20:33.46#ibcon#[25=AT03-08\r\n] 2006.145.18:20:33.49#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.18:20:33.49#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.18:20:33.49#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.18:20:33.49#ibcon#ireg 7 cls_cnt 0 2006.145.18:20:33.49#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.18:20:33.61#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.18:20:33.61#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.18:20:33.63#ibcon#[25=USB\r\n] 2006.145.18:20:33.66#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.18:20:33.66#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.18:20:33.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.18:20:33.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.18:20:33.66$vck44/valo=4,624.99 2006.145.18:20:33.66#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.18:20:33.66#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.18:20:33.66#ibcon#ireg 17 cls_cnt 0 2006.145.18:20:33.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.18:20:33.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.18:20:33.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.18:20:33.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.18:20:33.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.18:20:33.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.18:20:33.72#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.18:20:33.72#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.18:20:33.72$vck44/va=4,7 2006.145.18:20:33.72#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.18:20:33.72#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.18:20:33.72#ibcon#ireg 11 cls_cnt 2 2006.145.18:20:33.72#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.18:20:33.78#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.18:20:33.78#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.18:20:33.80#ibcon#[25=AT04-07\r\n] 2006.145.18:20:33.83#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.18:20:33.83#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.18:20:33.83#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.18:20:33.83#ibcon#ireg 7 cls_cnt 0 2006.145.18:20:33.83#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.18:20:33.95#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.18:20:33.95#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.18:20:33.97#ibcon#[25=USB\r\n] 2006.145.18:20:34.00#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.18:20:34.00#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.18:20:34.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.18:20:34.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.18:20:34.00$vck44/valo=5,734.99 2006.145.18:20:34.00#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.18:20:34.00#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.18:20:34.00#ibcon#ireg 17 cls_cnt 0 2006.145.18:20:34.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.18:20:34.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.18:20:34.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.18:20:34.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.18:20:34.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.18:20:34.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.18:20:34.06#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.18:20:34.06#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.18:20:34.06$vck44/va=5,4 2006.145.18:20:34.06#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.18:20:34.06#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.18:20:34.06#ibcon#ireg 11 cls_cnt 2 2006.145.18:20:34.06#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.18:20:34.12#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.18:20:34.12#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.18:20:34.14#ibcon#[25=AT05-04\r\n] 2006.145.18:20:34.17#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.18:20:34.17#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.18:20:34.17#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.18:20:34.17#ibcon#ireg 7 cls_cnt 0 2006.145.18:20:34.17#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.18:20:34.29#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.18:20:34.29#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.18:20:34.31#ibcon#[25=USB\r\n] 2006.145.18:20:34.34#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.18:20:34.34#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.18:20:34.34#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.18:20:34.34#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.18:20:34.34$vck44/valo=6,814.99 2006.145.18:20:34.34#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.18:20:34.34#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.18:20:34.34#ibcon#ireg 17 cls_cnt 0 2006.145.18:20:34.34#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.18:20:34.34#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.18:20:34.34#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.18:20:34.38#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.18:20:34.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.18:20:34.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.18:20:34.41#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.18:20:34.41#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.18:20:34.41$vck44/va=6,4 2006.145.18:20:34.41#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.18:20:34.41#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.18:20:34.41#ibcon#ireg 11 cls_cnt 2 2006.145.18:20:34.41#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.18:20:34.47#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.18:20:34.47#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.18:20:34.48#ibcon#[25=AT06-04\r\n] 2006.145.18:20:34.51#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.18:20:34.51#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.18:20:34.51#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.18:20:34.51#ibcon#ireg 7 cls_cnt 0 2006.145.18:20:34.51#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.18:20:34.63#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.18:20:34.63#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.18:20:34.65#ibcon#[25=USB\r\n] 2006.145.18:20:34.68#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.18:20:34.68#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.18:20:34.68#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.18:20:34.68#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.18:20:34.68$vck44/valo=7,864.99 2006.145.18:20:34.68#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.18:20:34.68#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.18:20:34.68#ibcon#ireg 17 cls_cnt 0 2006.145.18:20:34.68#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.18:20:34.68#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.18:20:34.68#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.18:20:34.70#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.18:20:34.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.18:20:34.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.18:20:34.74#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.18:20:34.74#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.18:20:34.74$vck44/va=7,4 2006.145.18:20:34.74#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.18:20:34.74#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.18:20:34.74#ibcon#ireg 11 cls_cnt 2 2006.145.18:20:34.74#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.18:20:34.80#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.18:20:34.80#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.18:20:34.82#ibcon#[25=AT07-04\r\n] 2006.145.18:20:34.85#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.18:20:34.85#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.18:20:34.85#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.18:20:34.85#ibcon#ireg 7 cls_cnt 0 2006.145.18:20:34.85#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.18:20:34.97#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.18:20:34.97#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.18:20:34.99#ibcon#[25=USB\r\n] 2006.145.18:20:35.02#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.18:20:35.02#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.18:20:35.02#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.18:20:35.02#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.18:20:35.02$vck44/valo=8,884.99 2006.145.18:20:35.02#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.18:20:35.02#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.18:20:35.02#ibcon#ireg 17 cls_cnt 0 2006.145.18:20:35.02#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.18:20:35.02#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.18:20:35.02#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.18:20:35.04#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.18:20:35.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.18:20:35.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.18:20:35.08#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.18:20:35.08#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.18:20:35.08$vck44/va=8,4 2006.145.18:20:35.08#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.18:20:35.08#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.18:20:35.08#ibcon#ireg 11 cls_cnt 2 2006.145.18:20:35.08#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.18:20:35.14#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.18:20:35.14#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.18:20:35.16#ibcon#[25=AT08-04\r\n] 2006.145.18:20:35.19#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.18:20:35.19#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.18:20:35.19#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.18:20:35.19#ibcon#ireg 7 cls_cnt 0 2006.145.18:20:35.19#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.18:20:35.31#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.18:20:35.31#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.18:20:35.33#ibcon#[25=USB\r\n] 2006.145.18:20:35.36#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.18:20:35.36#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.18:20:35.36#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.18:20:35.36#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.18:20:35.36$vck44/vblo=1,629.99 2006.145.18:20:35.36#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.18:20:35.36#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.18:20:35.36#ibcon#ireg 17 cls_cnt 0 2006.145.18:20:35.36#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.18:20:35.36#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.18:20:35.36#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.18:20:35.38#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.18:20:35.42#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.18:20:35.42#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.18:20:35.42#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.18:20:35.42#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.18:20:35.42$vck44/vb=1,3 2006.145.18:20:35.42#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.18:20:35.42#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.18:20:35.42#ibcon#ireg 11 cls_cnt 2 2006.145.18:20:35.42#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.18:20:35.42#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.18:20:35.42#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.18:20:35.44#ibcon#[27=AT01-03\r\n] 2006.145.18:20:35.47#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.18:20:35.47#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.18:20:35.47#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.18:20:35.47#ibcon#ireg 7 cls_cnt 0 2006.145.18:20:35.47#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.18:20:35.59#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.18:20:35.59#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.18:20:35.61#ibcon#[27=USB\r\n] 2006.145.18:20:35.64#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.18:20:35.64#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.18:20:35.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.18:20:35.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.18:20:35.64$vck44/vblo=2,634.99 2006.145.18:20:35.64#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.18:20:35.64#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.18:20:35.64#ibcon#ireg 17 cls_cnt 0 2006.145.18:20:35.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.18:20:35.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.18:20:35.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.18:20:35.66#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.18:20:35.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.18:20:35.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.18:20:35.70#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.18:20:35.70#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.18:20:35.70$vck44/vb=2,4 2006.145.18:20:35.70#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.18:20:35.70#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.18:20:35.70#ibcon#ireg 11 cls_cnt 2 2006.145.18:20:35.70#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.18:20:35.76#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.18:20:35.76#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.18:20:35.78#ibcon#[27=AT02-04\r\n] 2006.145.18:20:35.81#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.18:20:35.81#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.18:20:35.81#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.18:20:35.81#ibcon#ireg 7 cls_cnt 0 2006.145.18:20:35.81#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.18:20:35.93#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.18:20:35.93#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.18:20:35.95#ibcon#[27=USB\r\n] 2006.145.18:20:35.98#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.18:20:35.98#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.18:20:35.98#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.18:20:35.98#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.18:20:35.98$vck44/vblo=3,649.99 2006.145.18:20:35.98#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.18:20:35.98#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.18:20:35.98#ibcon#ireg 17 cls_cnt 0 2006.145.18:20:35.98#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.18:20:35.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.18:20:35.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.18:20:36.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.18:20:36.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.18:20:36.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.18:20:36.04#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.18:20:36.04#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.18:20:36.04$vck44/vb=3,4 2006.145.18:20:36.04#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.18:20:36.04#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.18:20:36.04#ibcon#ireg 11 cls_cnt 2 2006.145.18:20:36.04#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.18:20:36.10#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.18:20:36.10#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.18:20:36.12#ibcon#[27=AT03-04\r\n] 2006.145.18:20:36.15#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.18:20:36.15#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.18:20:36.15#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.18:20:36.15#ibcon#ireg 7 cls_cnt 0 2006.145.18:20:36.15#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.18:20:36.27#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.18:20:36.27#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.18:20:36.29#ibcon#[27=USB\r\n] 2006.145.18:20:36.32#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.18:20:36.32#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.18:20:36.32#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.18:20:36.32#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.18:20:36.32$vck44/vblo=4,679.99 2006.145.18:20:36.32#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.18:20:36.32#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.18:20:36.32#ibcon#ireg 17 cls_cnt 0 2006.145.18:20:36.32#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.18:20:36.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.18:20:36.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.18:20:36.34#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.18:20:36.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.18:20:36.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.18:20:36.38#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.18:20:36.38#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.18:20:36.38$vck44/vb=4,4 2006.145.18:20:36.38#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.18:20:36.38#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.18:20:36.38#ibcon#ireg 11 cls_cnt 2 2006.145.18:20:36.38#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.18:20:36.44#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.18:20:36.44#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.18:20:36.46#ibcon#[27=AT04-04\r\n] 2006.145.18:20:36.49#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.18:20:36.49#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.18:20:36.49#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.18:20:36.49#ibcon#ireg 7 cls_cnt 0 2006.145.18:20:36.49#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.18:20:36.61#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.18:20:36.61#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.18:20:36.63#ibcon#[27=USB\r\n] 2006.145.18:20:36.66#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.18:20:36.66#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.18:20:36.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.18:20:36.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.18:20:36.66$vck44/vblo=5,709.99 2006.145.18:20:36.66#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.18:20:36.66#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.18:20:36.66#ibcon#ireg 17 cls_cnt 0 2006.145.18:20:36.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.18:20:36.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.18:20:36.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.18:20:36.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.18:20:36.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.18:20:36.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.18:20:36.72#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.18:20:36.72#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.18:20:36.72$vck44/vb=5,4 2006.145.18:20:36.72#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.18:20:36.72#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.18:20:36.72#ibcon#ireg 11 cls_cnt 2 2006.145.18:20:36.72#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.18:20:36.78#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.18:20:36.78#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.18:20:36.80#ibcon#[27=AT05-04\r\n] 2006.145.18:20:36.83#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.18:20:36.83#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.18:20:36.83#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.18:20:36.83#ibcon#ireg 7 cls_cnt 0 2006.145.18:20:36.83#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.18:20:36.95#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.18:20:36.95#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.18:20:36.97#ibcon#[27=USB\r\n] 2006.145.18:20:37.00#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.18:20:37.00#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.18:20:37.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.18:20:37.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.18:20:37.00$vck44/vblo=6,719.99 2006.145.18:20:37.00#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.18:20:37.00#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.18:20:37.00#ibcon#ireg 17 cls_cnt 0 2006.145.18:20:37.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.18:20:37.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.18:20:37.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.18:20:37.02#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.18:20:37.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.18:20:37.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.18:20:37.06#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.18:20:37.06#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.18:20:37.06$vck44/vb=6,4 2006.145.18:20:37.06#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.18:20:37.06#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.18:20:37.06#ibcon#ireg 11 cls_cnt 2 2006.145.18:20:37.06#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.18:20:37.12#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.18:20:37.12#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.18:20:37.14#ibcon#[27=AT06-04\r\n] 2006.145.18:20:37.17#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.18:20:37.17#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.18:20:37.17#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.18:20:37.17#ibcon#ireg 7 cls_cnt 0 2006.145.18:20:37.17#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.18:20:37.29#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.18:20:37.29#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.18:20:37.31#ibcon#[27=USB\r\n] 2006.145.18:20:37.34#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.18:20:37.34#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.18:20:37.34#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.18:20:37.34#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.18:20:37.34$vck44/vblo=7,734.99 2006.145.18:20:37.34#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.18:20:37.34#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.18:20:37.34#ibcon#ireg 17 cls_cnt 0 2006.145.18:20:37.34#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.18:20:37.34#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.18:20:37.34#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.18:20:37.36#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.18:20:37.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.18:20:37.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.18:20:37.40#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.18:20:37.40#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.18:20:37.40$vck44/vb=7,4 2006.145.18:20:37.40#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.18:20:37.40#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.18:20:37.40#ibcon#ireg 11 cls_cnt 2 2006.145.18:20:37.40#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.18:20:37.46#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.18:20:37.46#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.18:20:37.48#ibcon#[27=AT07-04\r\n] 2006.145.18:20:37.51#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.18:20:37.51#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.18:20:37.51#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.18:20:37.51#ibcon#ireg 7 cls_cnt 0 2006.145.18:20:37.51#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.18:20:37.63#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.18:20:37.63#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.18:20:37.65#ibcon#[27=USB\r\n] 2006.145.18:20:37.68#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.18:20:37.68#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.18:20:37.68#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.18:20:37.68#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.18:20:37.68$vck44/vblo=8,744.99 2006.145.18:20:37.68#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.18:20:37.68#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.18:20:37.68#ibcon#ireg 17 cls_cnt 0 2006.145.18:20:37.68#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.18:20:37.68#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.18:20:37.68#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.18:20:37.70#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.18:20:37.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.18:20:37.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.18:20:37.74#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.18:20:37.74#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.18:20:37.74$vck44/vb=8,4 2006.145.18:20:37.74#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.18:20:37.74#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.18:20:37.74#ibcon#ireg 11 cls_cnt 2 2006.145.18:20:37.74#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.18:20:37.80#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.18:20:37.80#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.18:20:37.82#ibcon#[27=AT08-04\r\n] 2006.145.18:20:37.85#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.18:20:37.85#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.18:20:37.85#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.18:20:37.85#ibcon#ireg 7 cls_cnt 0 2006.145.18:20:37.85#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.18:20:37.97#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.18:20:37.97#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.18:20:37.99#ibcon#[27=USB\r\n] 2006.145.18:20:38.02#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.18:20:38.02#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.18:20:38.02#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.18:20:38.02#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.18:20:38.02$vck44/vabw=wide 2006.145.18:20:38.02#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.18:20:38.02#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.18:20:38.02#ibcon#ireg 8 cls_cnt 0 2006.145.18:20:38.02#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.18:20:38.02#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.18:20:38.02#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.18:20:38.04#ibcon#[25=BW32\r\n] 2006.145.18:20:38.07#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.18:20:38.07#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.18:20:38.07#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.18:20:38.07#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.18:20:38.07$vck44/vbbw=wide 2006.145.18:20:38.07#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.18:20:38.07#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.18:20:38.07#ibcon#ireg 8 cls_cnt 0 2006.145.18:20:38.07#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:20:38.14#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:20:38.14#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:20:38.16#ibcon#[27=BW32\r\n] 2006.145.18:20:38.19#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:20:38.19#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:20:38.19#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.18:20:38.19#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.18:20:38.19$setupk4/ifdk4 2006.145.18:20:38.19$ifdk4/lo= 2006.145.18:20:38.19$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.18:20:38.19$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.18:20:38.19$ifdk4/patch= 2006.145.18:20:38.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.18:20:38.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.18:20:38.20$setupk4/!*+20s 2006.145.18:20:43.52#abcon#<5=/05 1.0 1.6 15.70 911019.8\r\n> 2006.145.18:20:43.54#abcon#{5=INTERFACE CLEAR} 2006.145.18:20:43.60#abcon#[5=S1D000X0/0*\r\n] 2006.145.18:20:52.70$setupk4/"tpicd 2006.145.18:20:52.70$setupk4/echo=off 2006.145.18:20:52.70$setupk4/xlog=off 2006.145.18:20:52.70:!2006.145.18:22:18 2006.145.18:21:15.14#trakl#Source acquired 2006.145.18:21:15.14#flagr#flagr/antenna,acquired 2006.145.18:22:18.00:preob 2006.145.18:22:19.14/onsource/TRACKING 2006.145.18:22:19.14:!2006.145.18:22:28 2006.145.18:22:28.00:"tape 2006.145.18:22:28.00:"st=record 2006.145.18:22:28.00:data_valid=on 2006.145.18:22:28.00:midob 2006.145.18:22:28.14/onsource/TRACKING 2006.145.18:22:28.14/wx/15.70,1019.8,92 2006.145.18:22:28.20/cable/+6.5516E-03 2006.145.18:22:29.29/va/01,08,usb,yes,28,30 2006.145.18:22:29.29/va/02,07,usb,yes,30,31 2006.145.18:22:29.29/va/03,08,usb,yes,27,29 2006.145.18:22:29.29/va/04,07,usb,yes,31,33 2006.145.18:22:29.29/va/05,04,usb,yes,27,28 2006.145.18:22:29.29/va/06,04,usb,yes,31,30 2006.145.18:22:29.29/va/07,04,usb,yes,31,32 2006.145.18:22:29.29/va/08,04,usb,yes,26,32 2006.145.18:22:29.52/valo/01,524.99,yes,locked 2006.145.18:22:29.52/valo/02,534.99,yes,locked 2006.145.18:22:29.52/valo/03,564.99,yes,locked 2006.145.18:22:29.52/valo/04,624.99,yes,locked 2006.145.18:22:29.52/valo/05,734.99,yes,locked 2006.145.18:22:29.52/valo/06,814.99,yes,locked 2006.145.18:22:29.52/valo/07,864.99,yes,locked 2006.145.18:22:29.52/valo/08,884.99,yes,locked 2006.145.18:22:30.61/vb/01,03,usb,yes,35,33 2006.145.18:22:30.61/vb/02,04,usb,yes,31,31 2006.145.18:22:30.61/vb/03,04,usb,yes,28,31 2006.145.18:22:30.61/vb/04,04,usb,yes,32,31 2006.145.18:22:30.61/vb/05,04,usb,yes,25,27 2006.145.18:22:30.61/vb/06,04,usb,yes,29,26 2006.145.18:22:30.61/vb/07,04,usb,yes,29,29 2006.145.18:22:30.61/vb/08,04,usb,yes,27,30 2006.145.18:22:30.85/vblo/01,629.99,yes,locked 2006.145.18:22:30.85/vblo/02,634.99,yes,locked 2006.145.18:22:30.85/vblo/03,649.99,yes,locked 2006.145.18:22:30.85/vblo/04,679.99,yes,locked 2006.145.18:22:30.85/vblo/05,709.99,yes,locked 2006.145.18:22:30.85/vblo/06,719.99,yes,locked 2006.145.18:22:30.85/vblo/07,734.99,yes,locked 2006.145.18:22:30.85/vblo/08,744.99,yes,locked 2006.145.18:22:31.00/vabw/8 2006.145.18:22:31.15/vbbw/8 2006.145.18:22:31.24/xfe/off,on,15.2 2006.145.18:22:31.64/ifatt/23,28,28,28 2006.145.18:22:32.07/fmout-gps/S +4.4E-08 2006.145.18:22:32.11:!2006.145.18:35:32 2006.145.18:35:32.00:data_valid=off 2006.145.18:35:32.00:"et 2006.145.18:35:32.01:!+3s 2006.145.18:35:35.02:"tape 2006.145.18:35:35.02:postob 2006.145.18:35:35.17/cable/+6.5512E-03 2006.145.18:35:35.21/wx/15.68,1019.7,89 2006.145.18:35:36.08/fmout-gps/S +4.5E-08 2006.145.18:35:36.08:scan_name=145-1836,jd0605,40 2006.145.18:35:36.09:source=1921-293,192451.06,-291430.1,2000.0,ccw 2006.145.18:35:37.13#flagr#flagr/antenna,new-source 2006.145.18:35:37.13:checkk5 2006.145.18:35:37.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.18:35:38.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.18:35:38.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.18:35:38.91/chk_autoobs//k5ts4/ autoobs is running! 2006.145.18:35:39.64/chk_obsdata//k5ts1/T1451822??a.dat file size is correct (nominal:3136MB, actual:3136MB). 2006.145.18:35:40.39/chk_obsdata//k5ts2/T1451822??b.dat file size is correct (nominal:3136MB, actual:3136MB). 2006.145.18:35:41.14/chk_obsdata//k5ts3/T1451822??c.dat file size is correct (nominal:3136MB, actual:3136MB). 2006.145.18:35:41.88/chk_obsdata//k5ts4/T1451822??d.dat file size is correct (nominal:3136MB, actual:3136MB). 2006.145.18:35:42.63/k5log//k5ts1_log_newline 2006.145.18:35:43.39/k5log//k5ts2_log_newline 2006.145.18:35:44.13/k5log//k5ts3_log_newline 2006.145.18:35:44.86/k5log//k5ts4_log_newline 2006.145.18:35:44.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.18:35:44.89:setupk4=1 2006.145.18:35:44.89$setupk4/echo=on 2006.145.18:35:44.89$setupk4/pcalon 2006.145.18:35:44.89$pcalon/"no phase cal control is implemented here 2006.145.18:35:44.89$setupk4/"tpicd=stop 2006.145.18:35:44.89$setupk4/"rec=synch_on 2006.145.18:35:44.89$setupk4/"rec_mode=128 2006.145.18:35:44.89$setupk4/!* 2006.145.18:35:44.89$setupk4/recpk4 2006.145.18:35:44.89$recpk4/recpatch= 2006.145.18:35:44.89$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.18:35:44.89$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.18:35:44.89$setupk4/vck44 2006.145.18:35:44.89$vck44/valo=1,524.99 2006.145.18:35:44.89#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.18:35:44.89#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.18:35:44.89#ibcon#ireg 17 cls_cnt 0 2006.145.18:35:44.89#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.18:35:44.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.18:35:44.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.18:35:44.93#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.18:35:44.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.18:35:44.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.18:35:44.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.18:35:44.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.18:35:44.98$vck44/va=1,8 2006.145.18:35:44.98#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.18:35:44.98#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.18:35:44.98#ibcon#ireg 11 cls_cnt 2 2006.145.18:35:44.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.18:35:44.98#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.18:35:44.98#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.18:35:45.00#ibcon#[25=AT01-08\r\n] 2006.145.18:35:45.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.18:35:45.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.18:35:45.03#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.18:35:45.03#ibcon#ireg 7 cls_cnt 0 2006.145.18:35:45.03#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.18:35:45.15#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.18:35:45.15#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.18:35:45.17#ibcon#[25=USB\r\n] 2006.145.18:35:45.20#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.18:35:45.20#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.18:35:45.20#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.18:35:45.20#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.18:35:45.20$vck44/valo=2,534.99 2006.145.18:35:45.20#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.18:35:45.20#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.18:35:45.20#ibcon#ireg 17 cls_cnt 0 2006.145.18:35:45.20#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.18:35:45.20#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.18:35:45.20#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.18:35:45.23#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.18:35:45.27#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.18:35:45.27#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.18:35:45.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.18:35:45.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.18:35:45.27$vck44/va=2,7 2006.145.18:35:45.27#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.18:35:45.27#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.18:35:45.27#ibcon#ireg 11 cls_cnt 2 2006.145.18:35:45.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.18:35:45.32#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.18:35:45.32#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.18:35:45.34#ibcon#[25=AT02-07\r\n] 2006.145.18:35:45.37#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.18:35:45.37#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.18:35:45.37#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.18:35:45.37#ibcon#ireg 7 cls_cnt 0 2006.145.18:35:45.37#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.18:35:45.49#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.18:35:45.49#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.18:35:45.51#ibcon#[25=USB\r\n] 2006.145.18:35:45.54#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.18:35:45.54#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.18:35:45.54#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.18:35:45.54#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.18:35:45.54$vck44/valo=3,564.99 2006.145.18:35:45.54#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.18:35:45.54#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.18:35:45.54#ibcon#ireg 17 cls_cnt 0 2006.145.18:35:45.54#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.18:35:45.54#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.18:35:45.54#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.18:35:45.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.18:35:45.60#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.18:35:45.60#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.18:35:45.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.18:35:45.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.18:35:45.60$vck44/va=3,8 2006.145.18:35:45.60#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.18:35:45.60#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.18:35:45.60#ibcon#ireg 11 cls_cnt 2 2006.145.18:35:45.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.18:35:45.66#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.18:35:45.66#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.18:35:45.68#ibcon#[25=AT03-08\r\n] 2006.145.18:35:45.71#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.18:35:45.71#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.18:35:45.71#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.18:35:45.71#ibcon#ireg 7 cls_cnt 0 2006.145.18:35:45.71#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.18:35:45.83#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.18:35:45.83#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.18:35:45.85#ibcon#[25=USB\r\n] 2006.145.18:35:45.88#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.18:35:45.88#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.18:35:45.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.18:35:45.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.18:35:45.88$vck44/valo=4,624.99 2006.145.18:35:45.88#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.18:35:45.88#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.18:35:45.88#ibcon#ireg 17 cls_cnt 0 2006.145.18:35:45.88#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.18:35:45.88#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.18:35:45.88#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.18:35:45.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.18:35:45.94#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.18:35:45.94#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.18:35:45.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.18:35:45.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.18:35:45.94$vck44/va=4,7 2006.145.18:35:45.94#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.18:35:45.94#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.18:35:45.94#ibcon#ireg 11 cls_cnt 2 2006.145.18:35:45.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.18:35:46.00#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.18:35:46.00#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.18:35:46.02#ibcon#[25=AT04-07\r\n] 2006.145.18:35:46.05#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.18:35:46.05#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.18:35:46.05#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.18:35:46.05#ibcon#ireg 7 cls_cnt 0 2006.145.18:35:46.05#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.18:35:46.17#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.18:35:46.17#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.18:35:46.19#ibcon#[25=USB\r\n] 2006.145.18:35:46.22#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.18:35:46.22#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.18:35:46.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.18:35:46.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.18:35:46.22$vck44/valo=5,734.99 2006.145.18:35:46.22#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.18:35:46.22#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.18:35:46.22#ibcon#ireg 17 cls_cnt 0 2006.145.18:35:46.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.18:35:46.22#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.18:35:46.22#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.18:35:46.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.18:35:46.28#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.18:35:46.28#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.18:35:46.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.18:35:46.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.18:35:46.28$vck44/va=5,4 2006.145.18:35:46.28#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.18:35:46.28#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.18:35:46.28#ibcon#ireg 11 cls_cnt 2 2006.145.18:35:46.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.18:35:46.34#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.18:35:46.34#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.18:35:46.36#ibcon#[25=AT05-04\r\n] 2006.145.18:35:46.39#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.18:35:46.39#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.18:35:46.39#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.18:35:46.39#ibcon#ireg 7 cls_cnt 0 2006.145.18:35:46.39#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.18:35:46.51#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.18:35:46.51#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.18:35:46.53#ibcon#[25=USB\r\n] 2006.145.18:35:46.56#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.18:35:46.56#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.18:35:46.56#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.18:35:46.56#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.18:35:46.56$vck44/valo=6,814.99 2006.145.18:35:46.56#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.18:35:46.56#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.18:35:46.56#ibcon#ireg 17 cls_cnt 0 2006.145.18:35:46.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.18:35:46.56#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.18:35:46.56#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.18:35:46.59#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.18:35:46.63#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.18:35:46.63#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.18:35:46.63#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.18:35:46.63#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.18:35:46.63$vck44/va=6,4 2006.145.18:35:46.63#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.18:35:46.63#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.18:35:46.63#ibcon#ireg 11 cls_cnt 2 2006.145.18:35:46.63#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.18:35:46.68#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.18:35:46.68#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.18:35:46.70#ibcon#[25=AT06-04\r\n] 2006.145.18:35:46.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.18:35:46.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.18:35:46.73#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.18:35:46.73#ibcon#ireg 7 cls_cnt 0 2006.145.18:35:46.73#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.18:35:46.85#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.18:35:46.85#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.18:35:46.87#ibcon#[25=USB\r\n] 2006.145.18:35:46.90#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.18:35:46.90#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.18:35:46.90#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.18:35:46.90#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.18:35:46.90$vck44/valo=7,864.99 2006.145.18:35:46.90#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.18:35:46.90#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.18:35:46.90#ibcon#ireg 17 cls_cnt 0 2006.145.18:35:46.90#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.18:35:46.90#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.18:35:46.90#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.18:35:46.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.18:35:46.96#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.18:35:46.96#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.18:35:46.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.18:35:46.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.18:35:46.96$vck44/va=7,4 2006.145.18:35:46.96#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.18:35:46.96#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.18:35:46.96#ibcon#ireg 11 cls_cnt 2 2006.145.18:35:46.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.18:35:47.02#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.18:35:47.02#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.18:35:47.04#ibcon#[25=AT07-04\r\n] 2006.145.18:35:47.07#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.18:35:47.07#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.18:35:47.07#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.18:35:47.07#ibcon#ireg 7 cls_cnt 0 2006.145.18:35:47.07#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.18:35:47.19#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.18:35:47.19#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.18:35:47.21#ibcon#[25=USB\r\n] 2006.145.18:35:47.24#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.18:35:47.24#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.18:35:47.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.18:35:47.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.18:35:47.24$vck44/valo=8,884.99 2006.145.18:35:47.24#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.18:35:47.24#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.18:35:47.24#ibcon#ireg 17 cls_cnt 0 2006.145.18:35:47.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.18:35:47.24#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.18:35:47.24#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.18:35:47.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.18:35:47.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.18:35:47.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.18:35:47.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.18:35:47.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.18:35:47.30$vck44/va=8,4 2006.145.18:35:47.30#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.18:35:47.30#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.18:35:47.30#ibcon#ireg 11 cls_cnt 2 2006.145.18:35:47.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.18:35:47.36#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.18:35:47.36#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.18:35:47.38#ibcon#[25=AT08-04\r\n] 2006.145.18:35:47.41#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.18:35:47.41#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.18:35:47.41#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.18:35:47.41#ibcon#ireg 7 cls_cnt 0 2006.145.18:35:47.41#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.18:35:47.53#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.18:35:47.53#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.18:35:47.55#ibcon#[25=USB\r\n] 2006.145.18:35:47.58#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.18:35:47.58#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.18:35:47.58#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.18:35:47.58#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.18:35:47.58$vck44/vblo=1,629.99 2006.145.18:35:47.58#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.18:35:47.58#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.18:35:47.58#ibcon#ireg 17 cls_cnt 0 2006.145.18:35:47.58#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.18:35:47.58#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.18:35:47.58#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.18:35:47.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.18:35:47.64#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.18:35:47.64#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.18:35:47.64#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.18:35:47.64#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.18:35:47.64$vck44/vb=1,3 2006.145.18:35:47.64#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.18:35:47.64#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.18:35:47.64#ibcon#ireg 11 cls_cnt 2 2006.145.18:35:47.64#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.18:35:47.64#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.18:35:47.64#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.18:35:47.66#ibcon#[27=AT01-03\r\n] 2006.145.18:35:47.69#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.18:35:47.69#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.18:35:47.69#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.18:35:47.69#ibcon#ireg 7 cls_cnt 0 2006.145.18:35:47.69#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.18:35:47.81#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.18:35:47.81#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.18:35:47.83#ibcon#[27=USB\r\n] 2006.145.18:35:47.86#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.18:35:47.86#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.18:35:47.86#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.18:35:47.86#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.18:35:47.86$vck44/vblo=2,634.99 2006.145.18:35:47.86#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.18:35:47.86#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.18:35:47.86#ibcon#ireg 17 cls_cnt 0 2006.145.18:35:47.86#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.18:35:47.86#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.18:35:47.86#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.18:35:47.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.18:35:47.92#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.18:35:47.92#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.18:35:47.92#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.18:35:47.92#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.18:35:47.92$vck44/vb=2,4 2006.145.18:35:47.92#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.18:35:47.92#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.18:35:47.92#ibcon#ireg 11 cls_cnt 2 2006.145.18:35:47.92#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.18:35:47.98#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.18:35:47.98#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.18:35:48.00#ibcon#[27=AT02-04\r\n] 2006.145.18:35:48.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.18:35:48.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.18:35:48.03#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.18:35:48.03#ibcon#ireg 7 cls_cnt 0 2006.145.18:35:48.03#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.18:35:48.15#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.18:35:48.15#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.18:35:48.17#ibcon#[27=USB\r\n] 2006.145.18:35:48.20#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.18:35:48.20#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.18:35:48.20#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.18:35:48.20#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.18:35:48.20$vck44/vblo=3,649.99 2006.145.18:35:48.20#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.18:35:48.20#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.18:35:48.20#ibcon#ireg 17 cls_cnt 0 2006.145.18:35:48.20#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.18:35:48.20#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.18:35:48.20#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.18:35:48.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.18:35:48.26#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.18:35:48.26#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.18:35:48.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.18:35:48.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.18:35:48.26$vck44/vb=3,4 2006.145.18:35:48.26#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.18:35:48.26#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.18:35:48.26#ibcon#ireg 11 cls_cnt 2 2006.145.18:35:48.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.18:35:48.32#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.18:35:48.32#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.18:35:48.34#ibcon#[27=AT03-04\r\n] 2006.145.18:35:48.37#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.18:35:48.37#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.18:35:48.37#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.18:35:48.37#ibcon#ireg 7 cls_cnt 0 2006.145.18:35:48.37#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.18:35:48.49#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.18:35:48.49#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.18:35:48.51#ibcon#[27=USB\r\n] 2006.145.18:35:48.54#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.18:35:48.54#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.18:35:48.54#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.18:35:48.54#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.18:35:48.54$vck44/vblo=4,679.99 2006.145.18:35:48.54#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.18:35:48.54#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.18:35:48.54#ibcon#ireg 17 cls_cnt 0 2006.145.18:35:48.54#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.18:35:48.54#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.18:35:48.54#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.18:35:48.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.18:35:48.60#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.18:35:48.60#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.18:35:48.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.18:35:48.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.18:35:48.60$vck44/vb=4,4 2006.145.18:35:48.60#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.18:35:48.60#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.18:35:48.60#ibcon#ireg 11 cls_cnt 2 2006.145.18:35:48.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.18:35:48.66#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.18:35:48.66#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.18:35:48.68#ibcon#[27=AT04-04\r\n] 2006.145.18:35:48.71#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.18:35:48.71#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.18:35:48.71#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.18:35:48.71#ibcon#ireg 7 cls_cnt 0 2006.145.18:35:48.71#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.18:35:48.79#abcon#<5=/07 1.3 1.7 15.68 881019.8\r\n> 2006.145.18:35:48.81#abcon#{5=INTERFACE CLEAR} 2006.145.18:35:48.83#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.18:35:48.83#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.18:35:48.85#ibcon#[27=USB\r\n] 2006.145.18:35:48.87#abcon#[5=S1D000X0/0*\r\n] 2006.145.18:35:48.88#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.18:35:48.88#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.18:35:48.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.18:35:48.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.18:35:48.88$vck44/vblo=5,709.99 2006.145.18:35:48.88#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.18:35:48.88#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.18:35:48.88#ibcon#ireg 17 cls_cnt 0 2006.145.18:35:48.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.18:35:48.88#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.18:35:48.88#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.18:35:48.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.18:35:48.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.18:35:48.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.18:35:48.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.18:35:48.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.18:35:48.94$vck44/vb=5,4 2006.145.18:35:48.94#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.18:35:48.94#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.18:35:48.94#ibcon#ireg 11 cls_cnt 2 2006.145.18:35:48.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.18:35:49.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.18:35:49.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.18:35:49.02#ibcon#[27=AT05-04\r\n] 2006.145.18:35:49.05#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.18:35:49.05#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.18:35:49.05#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.18:35:49.05#ibcon#ireg 7 cls_cnt 0 2006.145.18:35:49.05#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.18:35:49.17#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.18:35:49.17#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.18:35:49.19#ibcon#[27=USB\r\n] 2006.145.18:35:49.22#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.18:35:49.22#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.18:35:49.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.18:35:49.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.18:35:49.22$vck44/vblo=6,719.99 2006.145.18:35:49.22#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.18:35:49.22#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.18:35:49.22#ibcon#ireg 17 cls_cnt 0 2006.145.18:35:49.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.18:35:49.22#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.18:35:49.22#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.18:35:49.24#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.18:35:49.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.18:35:49.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.18:35:49.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.18:35:49.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.18:35:49.28$vck44/vb=6,4 2006.145.18:35:49.28#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.18:35:49.28#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.18:35:49.28#ibcon#ireg 11 cls_cnt 2 2006.145.18:35:49.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.18:35:49.34#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.18:35:49.34#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.18:35:49.36#ibcon#[27=AT06-04\r\n] 2006.145.18:35:49.39#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.18:35:49.39#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.18:35:49.39#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.18:35:49.39#ibcon#ireg 7 cls_cnt 0 2006.145.18:35:49.39#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.18:35:49.51#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.18:35:49.51#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.18:35:49.53#ibcon#[27=USB\r\n] 2006.145.18:35:49.56#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.18:35:49.56#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.18:35:49.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.18:35:49.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.18:35:49.56$vck44/vblo=7,734.99 2006.145.18:35:49.56#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.18:35:49.56#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.18:35:49.56#ibcon#ireg 17 cls_cnt 0 2006.145.18:35:49.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.18:35:49.56#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.18:35:49.56#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.18:35:49.58#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.18:35:49.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.18:35:49.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.18:35:49.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.18:35:49.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.18:35:49.62$vck44/vb=7,4 2006.145.18:35:49.62#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.18:35:49.62#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.18:35:49.62#ibcon#ireg 11 cls_cnt 2 2006.145.18:35:49.62#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.18:35:49.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.18:35:49.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.18:35:49.70#ibcon#[27=AT07-04\r\n] 2006.145.18:35:49.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.18:35:49.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.18:35:49.73#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.18:35:49.73#ibcon#ireg 7 cls_cnt 0 2006.145.18:35:49.73#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.18:35:49.85#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.18:35:49.85#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.18:35:49.87#ibcon#[27=USB\r\n] 2006.145.18:35:49.90#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.18:35:49.90#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.18:35:49.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.18:35:49.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.18:35:49.90$vck44/vblo=8,744.99 2006.145.18:35:49.90#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.18:35:49.90#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.18:35:49.90#ibcon#ireg 17 cls_cnt 0 2006.145.18:35:49.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.18:35:49.90#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.18:35:49.90#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.18:35:49.92#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.18:35:49.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.18:35:49.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.18:35:49.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.18:35:49.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.18:35:49.96$vck44/vb=8,4 2006.145.18:35:49.96#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.18:35:49.96#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.18:35:49.96#ibcon#ireg 11 cls_cnt 2 2006.145.18:35:49.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.18:35:50.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.18:35:50.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.18:35:50.04#ibcon#[27=AT08-04\r\n] 2006.145.18:35:50.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.18:35:50.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.18:35:50.07#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.18:35:50.07#ibcon#ireg 7 cls_cnt 0 2006.145.18:35:50.07#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.18:35:50.19#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.18:35:50.19#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.18:35:50.21#ibcon#[27=USB\r\n] 2006.145.18:35:50.24#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.18:35:50.24#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.18:35:50.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.18:35:50.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.18:35:50.24$vck44/vabw=wide 2006.145.18:35:50.24#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.18:35:50.24#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.18:35:50.24#ibcon#ireg 8 cls_cnt 0 2006.145.18:35:50.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.18:35:50.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.18:35:50.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.18:35:50.26#ibcon#[25=BW32\r\n] 2006.145.18:35:50.29#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.18:35:50.29#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.18:35:50.29#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.18:35:50.29#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.18:35:50.29$vck44/vbbw=wide 2006.145.18:35:50.29#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.18:35:50.29#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.18:35:50.29#ibcon#ireg 8 cls_cnt 0 2006.145.18:35:50.29#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:35:50.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:35:50.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:35:50.38#ibcon#[27=BW32\r\n] 2006.145.18:35:50.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:35:50.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:35:50.41#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.18:35:50.41#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.18:35:50.41$setupk4/ifdk4 2006.145.18:35:50.41$ifdk4/lo= 2006.145.18:35:50.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.18:35:50.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.18:35:50.41$ifdk4/patch= 2006.145.18:35:50.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.18:35:50.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.18:35:50.41$setupk4/!*+20s 2006.145.18:35:58.96#abcon#<5=/07 1.3 1.7 15.68 881019.8\r\n> 2006.145.18:35:58.98#abcon#{5=INTERFACE CLEAR} 2006.145.18:35:59.04#abcon#[5=S1D000X0/0*\r\n] 2006.145.18:36:02.13#trakl#Source acquired 2006.145.18:36:02.13#flagr#flagr/antenna,acquired 2006.145.18:36:04.90$setupk4/"tpicd 2006.145.18:36:04.90$setupk4/echo=off 2006.145.18:36:04.90$setupk4/xlog=off 2006.145.18:36:04.90:!2006.145.18:36:14 2006.145.18:36:14.00:preob 2006.145.18:36:15.14/onsource/TRACKING 2006.145.18:36:15.14:!2006.145.18:36:24 2006.145.18:36:24.00:"tape 2006.145.18:36:24.00:"st=record 2006.145.18:36:24.00:data_valid=on 2006.145.18:36:24.00:midob 2006.145.18:36:24.14/onsource/TRACKING 2006.145.18:36:24.14/wx/15.68,1019.7,88 2006.145.18:36:24.32/cable/+6.5507E-03 2006.145.18:36:25.41/va/01,08,usb,yes,30,32 2006.145.18:36:25.41/va/02,07,usb,yes,32,33 2006.145.18:36:25.41/va/03,08,usb,yes,29,31 2006.145.18:36:25.41/va/04,07,usb,yes,33,35 2006.145.18:36:25.41/va/05,04,usb,yes,29,30 2006.145.18:36:25.41/va/06,04,usb,yes,33,32 2006.145.18:36:25.41/va/07,04,usb,yes,33,34 2006.145.18:36:25.41/va/08,04,usb,yes,28,34 2006.145.18:36:25.64/valo/01,524.99,yes,locked 2006.145.18:36:25.64/valo/02,534.99,yes,locked 2006.145.18:36:25.64/valo/03,564.99,yes,locked 2006.145.18:36:25.64/valo/04,624.99,yes,locked 2006.145.18:36:25.64/valo/05,734.99,yes,locked 2006.145.18:36:25.64/valo/06,814.99,yes,locked 2006.145.18:36:25.64/valo/07,864.99,yes,locked 2006.145.18:36:25.64/valo/08,884.99,yes,locked 2006.145.18:36:26.73/vb/01,03,usb,yes,37,35 2006.145.18:36:26.73/vb/02,04,usb,yes,33,32 2006.145.18:36:26.73/vb/03,04,usb,yes,29,32 2006.145.18:36:26.73/vb/04,04,usb,yes,34,33 2006.145.18:36:26.73/vb/05,04,usb,yes,27,29 2006.145.18:36:26.73/vb/06,04,usb,yes,31,27 2006.145.18:36:26.73/vb/07,04,usb,yes,31,30 2006.145.18:36:26.73/vb/08,04,usb,yes,28,31 2006.145.18:36:26.97/vblo/01,629.99,yes,locked 2006.145.18:36:26.97/vblo/02,634.99,yes,locked 2006.145.18:36:26.97/vblo/03,649.99,yes,locked 2006.145.18:36:26.97/vblo/04,679.99,yes,locked 2006.145.18:36:26.97/vblo/05,709.99,yes,locked 2006.145.18:36:26.97/vblo/06,719.99,yes,locked 2006.145.18:36:26.97/vblo/07,734.99,yes,locked 2006.145.18:36:26.97/vblo/08,744.99,yes,locked 2006.145.18:36:27.12/vabw/8 2006.145.18:36:27.27/vbbw/8 2006.145.18:36:27.36/xfe/off,on,14.7 2006.145.18:36:27.76/ifatt/23,28,28,28 2006.145.18:36:28.08/fmout-gps/S +4.6E-08 2006.145.18:36:28.16:!2006.145.18:37:04 2006.145.18:37:04.01:data_valid=off 2006.145.18:37:04.01:"et 2006.145.18:37:04.02:!+3s 2006.145.18:37:07.03:"tape 2006.145.18:37:07.03:postob 2006.145.18:37:07.21/cable/+6.5508E-03 2006.145.18:37:07.21/wx/15.68,1019.8,88 2006.145.18:37:07.29/fmout-gps/S +4.6E-08 2006.145.18:37:07.29:scan_name=145-1837,jd0605,40 2006.145.18:37:07.29:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.145.18:37:09.14#flagr#flagr/antenna,new-source 2006.145.18:37:09.14:checkk5 2006.145.18:37:09.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.18:37:10.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.18:37:10.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.18:37:10.91/chk_autoobs//k5ts4/ autoobs is running! 2006.145.18:37:11.33/chk_obsdata//k5ts1/T1451836??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.18:37:11.77/chk_obsdata//k5ts2/T1451836??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.18:37:12.20/chk_obsdata//k5ts3/T1451836??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.18:37:12.65/chk_obsdata//k5ts4/T1451836??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.18:37:13.41/k5log//k5ts1_log_newline 2006.145.18:37:14.17/k5log//k5ts2_log_newline 2006.145.18:37:14.92/k5log//k5ts3_log_newline 2006.145.18:37:15.66/k5log//k5ts4_log_newline 2006.145.18:37:15.69/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.18:37:15.69:setupk4=1 2006.145.18:37:15.69$setupk4/echo=on 2006.145.18:37:15.69$setupk4/pcalon 2006.145.18:37:15.69$pcalon/"no phase cal control is implemented here 2006.145.18:37:15.69$setupk4/"tpicd=stop 2006.145.18:37:15.69$setupk4/"rec=synch_on 2006.145.18:37:15.69$setupk4/"rec_mode=128 2006.145.18:37:15.69$setupk4/!* 2006.145.18:37:15.69$setupk4/recpk4 2006.145.18:37:15.69$recpk4/recpatch= 2006.145.18:37:15.69$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.18:37:15.69$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.18:37:15.69$setupk4/vck44 2006.145.18:37:15.69$vck44/valo=1,524.99 2006.145.18:37:15.69#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.18:37:15.69#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.18:37:15.69#ibcon#ireg 17 cls_cnt 0 2006.145.18:37:15.69#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:37:15.69#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:37:15.69#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:37:15.73#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.18:37:15.78#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:37:15.78#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:37:15.78#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.18:37:15.78#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.18:37:15.78$vck44/va=1,8 2006.145.18:37:15.78#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.18:37:15.78#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.18:37:15.78#ibcon#ireg 11 cls_cnt 2 2006.145.18:37:15.78#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:37:15.78#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:37:15.78#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:37:15.80#ibcon#[25=AT01-08\r\n] 2006.145.18:37:15.83#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:37:15.83#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:37:15.83#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.18:37:15.83#ibcon#ireg 7 cls_cnt 0 2006.145.18:37:15.83#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:37:15.95#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:37:15.95#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:37:15.97#ibcon#[25=USB\r\n] 2006.145.18:37:16.02#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:37:16.02#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:37:16.02#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.18:37:16.02#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.18:37:16.02$vck44/valo=2,534.99 2006.145.18:37:16.02#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.18:37:16.02#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.18:37:16.02#ibcon#ireg 17 cls_cnt 0 2006.145.18:37:16.02#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:37:16.02#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:37:16.02#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:37:16.03#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.18:37:16.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:37:16.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:37:16.07#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.18:37:16.07#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.18:37:16.07$vck44/va=2,7 2006.145.18:37:16.07#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.18:37:16.07#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.18:37:16.07#ibcon#ireg 11 cls_cnt 2 2006.145.18:37:16.07#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:37:16.14#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:37:16.14#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:37:16.16#ibcon#[25=AT02-07\r\n] 2006.145.18:37:16.19#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:37:16.19#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:37:16.19#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.18:37:16.19#ibcon#ireg 7 cls_cnt 0 2006.145.18:37:16.19#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:37:16.31#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:37:16.31#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:37:16.33#ibcon#[25=USB\r\n] 2006.145.18:37:16.36#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:37:16.36#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:37:16.36#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.18:37:16.36#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.18:37:16.36$vck44/valo=3,564.99 2006.145.18:37:16.36#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.18:37:16.36#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.18:37:16.36#ibcon#ireg 17 cls_cnt 0 2006.145.18:37:16.36#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.18:37:16.36#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.18:37:16.36#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.18:37:16.38#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.18:37:16.42#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.18:37:16.42#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.18:37:16.42#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.18:37:16.42#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.18:37:16.42$vck44/va=3,8 2006.145.18:37:16.42#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.18:37:16.42#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.18:37:16.42#ibcon#ireg 11 cls_cnt 2 2006.145.18:37:16.42#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.18:37:16.48#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.18:37:16.48#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.18:37:16.50#ibcon#[25=AT03-08\r\n] 2006.145.18:37:16.53#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.18:37:16.53#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.18:37:16.53#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.18:37:16.53#ibcon#ireg 7 cls_cnt 0 2006.145.18:37:16.53#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.18:37:16.65#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.18:37:16.65#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.18:37:16.67#ibcon#[25=USB\r\n] 2006.145.18:37:16.70#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.18:37:16.70#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.18:37:16.70#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.18:37:16.70#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.18:37:16.70$vck44/valo=4,624.99 2006.145.18:37:16.70#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.18:37:16.70#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.18:37:16.70#ibcon#ireg 17 cls_cnt 0 2006.145.18:37:16.70#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:37:16.70#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:37:16.70#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:37:16.72#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.18:37:16.76#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:37:16.76#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:37:16.76#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.18:37:16.76#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.18:37:16.76$vck44/va=4,7 2006.145.18:37:16.76#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.18:37:16.76#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.18:37:16.76#ibcon#ireg 11 cls_cnt 2 2006.145.18:37:16.76#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:37:16.82#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:37:16.82#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:37:16.84#ibcon#[25=AT04-07\r\n] 2006.145.18:37:16.87#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:37:16.87#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:37:16.87#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.18:37:16.87#ibcon#ireg 7 cls_cnt 0 2006.145.18:37:16.87#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:37:16.99#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:37:16.99#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:37:17.01#ibcon#[25=USB\r\n] 2006.145.18:37:17.06#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:37:17.06#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:37:17.06#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.18:37:17.06#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.18:37:17.06$vck44/valo=5,734.99 2006.145.18:37:17.06#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.18:37:17.06#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.18:37:17.06#ibcon#ireg 17 cls_cnt 0 2006.145.18:37:17.06#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:37:17.06#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:37:17.06#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:37:17.07#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.18:37:17.11#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:37:17.11#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:37:17.11#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.18:37:17.11#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.18:37:17.11$vck44/va=5,4 2006.145.18:37:17.11#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.18:37:17.11#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.18:37:17.11#ibcon#ireg 11 cls_cnt 2 2006.145.18:37:17.11#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:37:17.18#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:37:17.18#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:37:17.20#ibcon#[25=AT05-04\r\n] 2006.145.18:37:17.25#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:37:17.25#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:37:17.25#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.18:37:17.25#ibcon#ireg 7 cls_cnt 0 2006.145.18:37:17.25#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:37:17.36#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:37:17.36#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:37:17.38#ibcon#[25=USB\r\n] 2006.145.18:37:17.43#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:37:17.43#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:37:17.43#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.18:37:17.43#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.18:37:17.43$vck44/valo=6,814.99 2006.145.18:37:17.43#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.18:37:17.43#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.18:37:17.43#ibcon#ireg 17 cls_cnt 0 2006.145.18:37:17.43#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.18:37:17.43#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.18:37:17.43#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.18:37:17.44#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.18:37:17.48#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.18:37:17.48#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.18:37:17.48#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.18:37:17.48#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.18:37:17.48$vck44/va=6,4 2006.145.18:37:17.48#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.18:37:17.48#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.18:37:17.48#ibcon#ireg 11 cls_cnt 2 2006.145.18:37:17.48#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.18:37:17.55#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.18:37:17.55#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.18:37:17.57#ibcon#[25=AT06-04\r\n] 2006.145.18:37:17.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.18:37:17.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.18:37:17.60#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.18:37:17.60#ibcon#ireg 7 cls_cnt 0 2006.145.18:37:17.60#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.18:37:17.72#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.18:37:17.72#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.18:37:17.74#ibcon#[25=USB\r\n] 2006.145.18:37:17.77#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.18:37:17.77#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.18:37:17.77#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.18:37:17.77#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.18:37:17.77$vck44/valo=7,864.99 2006.145.18:37:17.77#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.18:37:17.77#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.18:37:17.77#ibcon#ireg 17 cls_cnt 0 2006.145.18:37:17.77#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.18:37:17.77#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.18:37:17.77#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.18:37:17.79#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.18:37:17.83#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.18:37:17.83#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.18:37:17.83#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.18:37:17.83#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.18:37:17.83$vck44/va=7,4 2006.145.18:37:17.83#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.18:37:17.83#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.18:37:17.83#ibcon#ireg 11 cls_cnt 2 2006.145.18:37:17.83#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.18:37:17.89#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.18:37:17.89#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.18:37:17.91#ibcon#[25=AT07-04\r\n] 2006.145.18:37:17.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.18:37:17.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.18:37:17.94#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.18:37:17.94#ibcon#ireg 7 cls_cnt 0 2006.145.18:37:17.94#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.18:37:18.06#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.18:37:18.06#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.18:37:18.08#ibcon#[25=USB\r\n] 2006.145.18:37:18.11#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.18:37:18.11#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.18:37:18.11#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.18:37:18.11#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.18:37:18.11$vck44/valo=8,884.99 2006.145.18:37:18.11#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.18:37:18.11#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.18:37:18.11#ibcon#ireg 17 cls_cnt 0 2006.145.18:37:18.11#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:37:18.11#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:37:18.11#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:37:18.13#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.18:37:18.17#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:37:18.17#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:37:18.17#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.18:37:18.17#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.18:37:18.17$vck44/va=8,4 2006.145.18:37:18.17#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.18:37:18.17#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.18:37:18.17#ibcon#ireg 11 cls_cnt 2 2006.145.18:37:18.17#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:37:18.23#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:37:18.23#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:37:18.25#ibcon#[25=AT08-04\r\n] 2006.145.18:37:18.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:37:18.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:37:18.28#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.18:37:18.28#ibcon#ireg 7 cls_cnt 0 2006.145.18:37:18.28#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:37:18.40#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:37:18.40#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:37:18.42#ibcon#[25=USB\r\n] 2006.145.18:37:18.45#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:37:18.45#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:37:18.45#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.18:37:18.45#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.18:37:18.45$vck44/vblo=1,629.99 2006.145.18:37:18.45#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.18:37:18.45#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.18:37:18.45#ibcon#ireg 17 cls_cnt 0 2006.145.18:37:18.45#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.18:37:18.45#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.18:37:18.45#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.18:37:18.47#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.18:37:18.51#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.18:37:18.51#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.18:37:18.51#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.18:37:18.51#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.18:37:18.51$vck44/vb=1,3 2006.145.18:37:18.51#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.18:37:18.51#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.18:37:18.51#ibcon#ireg 11 cls_cnt 2 2006.145.18:37:18.51#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.18:37:18.51#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.18:37:18.51#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.18:37:18.53#ibcon#[27=AT01-03\r\n] 2006.145.18:37:18.56#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.18:37:18.56#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.18:37:18.56#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.18:37:18.56#ibcon#ireg 7 cls_cnt 0 2006.145.18:37:18.56#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.18:37:18.68#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.18:37:18.68#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.18:37:18.70#ibcon#[27=USB\r\n] 2006.145.18:37:18.73#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.18:37:18.73#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.18:37:18.73#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.18:37:18.73#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.18:37:18.73$vck44/vblo=2,634.99 2006.145.18:37:18.73#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.18:37:18.73#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.18:37:18.73#ibcon#ireg 17 cls_cnt 0 2006.145.18:37:18.73#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:37:18.73#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:37:18.73#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:37:18.75#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.18:37:18.79#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:37:18.79#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:37:18.79#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.18:37:18.79#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.18:37:18.79$vck44/vb=2,4 2006.145.18:37:18.79#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.18:37:18.79#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.18:37:18.79#ibcon#ireg 11 cls_cnt 2 2006.145.18:37:18.79#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:37:18.85#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:37:18.85#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:37:18.87#ibcon#[27=AT02-04\r\n] 2006.145.18:37:18.90#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:37:18.90#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:37:18.90#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.18:37:18.90#ibcon#ireg 7 cls_cnt 0 2006.145.18:37:18.90#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:37:19.02#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:37:19.02#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:37:19.04#ibcon#[27=USB\r\n] 2006.145.18:37:19.07#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:37:19.07#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:37:19.07#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.18:37:19.07#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.18:37:19.07$vck44/vblo=3,649.99 2006.145.18:37:19.07#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.18:37:19.07#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.18:37:19.07#ibcon#ireg 17 cls_cnt 0 2006.145.18:37:19.07#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:37:19.07#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:37:19.07#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:37:19.09#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.18:37:19.13#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:37:19.13#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:37:19.13#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.18:37:19.13#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.18:37:19.13$vck44/vb=3,4 2006.145.18:37:19.13#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.18:37:19.13#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.18:37:19.13#ibcon#ireg 11 cls_cnt 2 2006.145.18:37:19.13#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:37:19.19#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:37:19.19#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:37:19.21#ibcon#[27=AT03-04\r\n] 2006.145.18:37:19.24#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:37:19.24#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:37:19.24#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.18:37:19.24#ibcon#ireg 7 cls_cnt 0 2006.145.18:37:19.24#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:37:19.36#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:37:19.36#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:37:19.38#ibcon#[27=USB\r\n] 2006.145.18:37:19.41#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:37:19.41#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:37:19.41#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.18:37:19.41#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.18:37:19.41$vck44/vblo=4,679.99 2006.145.18:37:19.41#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.18:37:19.41#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.18:37:19.41#ibcon#ireg 17 cls_cnt 0 2006.145.18:37:19.41#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.18:37:19.41#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.18:37:19.41#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.18:37:19.43#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.18:37:19.47#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.18:37:19.47#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.18:37:19.47#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.18:37:19.47#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.18:37:19.47$vck44/vb=4,4 2006.145.18:37:19.47#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.18:37:19.47#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.18:37:19.47#ibcon#ireg 11 cls_cnt 2 2006.145.18:37:19.47#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.18:37:19.53#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.18:37:19.53#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.18:37:19.55#ibcon#[27=AT04-04\r\n] 2006.145.18:37:19.58#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.18:37:19.58#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.18:37:19.58#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.18:37:19.58#ibcon#ireg 7 cls_cnt 0 2006.145.18:37:19.58#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.18:37:19.70#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.18:37:19.70#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.18:37:19.72#ibcon#[27=USB\r\n] 2006.145.18:37:19.75#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.18:37:19.75#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.18:37:19.75#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.18:37:19.75#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.18:37:19.75$vck44/vblo=5,709.99 2006.145.18:37:19.75#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.18:37:19.75#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.18:37:19.75#ibcon#ireg 17 cls_cnt 0 2006.145.18:37:19.75#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:37:19.75#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:37:19.75#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:37:19.77#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.18:37:19.81#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:37:19.81#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:37:19.81#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.18:37:19.81#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.18:37:19.81$vck44/vb=5,4 2006.145.18:37:19.81#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.18:37:19.81#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.18:37:19.81#ibcon#ireg 11 cls_cnt 2 2006.145.18:37:19.81#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:37:19.87#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:37:19.87#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:37:19.89#ibcon#[27=AT05-04\r\n] 2006.145.18:37:19.92#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:37:19.92#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:37:19.92#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.18:37:19.92#ibcon#ireg 7 cls_cnt 0 2006.145.18:37:19.92#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:37:20.04#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:37:20.04#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:37:20.06#ibcon#[27=USB\r\n] 2006.145.18:37:20.09#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:37:20.09#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:37:20.09#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.18:37:20.09#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.18:37:20.09$vck44/vblo=6,719.99 2006.145.18:37:20.09#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.18:37:20.09#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.18:37:20.09#ibcon#ireg 17 cls_cnt 0 2006.145.18:37:20.09#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:37:20.09#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:37:20.09#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:37:20.11#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.18:37:20.15#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:37:20.15#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:37:20.15#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.18:37:20.15#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.18:37:20.15$vck44/vb=6,4 2006.145.18:37:20.15#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.18:37:20.15#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.18:37:20.15#ibcon#ireg 11 cls_cnt 2 2006.145.18:37:20.15#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:37:20.21#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:37:20.21#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:37:20.23#ibcon#[27=AT06-04\r\n] 2006.145.18:37:20.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:37:20.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:37:20.26#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.18:37:20.26#ibcon#ireg 7 cls_cnt 0 2006.145.18:37:20.26#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:37:20.38#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:37:20.38#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:37:20.40#ibcon#[27=USB\r\n] 2006.145.18:37:20.43#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:37:20.43#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:37:20.43#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.18:37:20.43#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.18:37:20.43$vck44/vblo=7,734.99 2006.145.18:37:20.43#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.18:37:20.43#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.18:37:20.43#ibcon#ireg 17 cls_cnt 0 2006.145.18:37:20.43#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.18:37:20.43#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.18:37:20.43#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.18:37:20.45#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.18:37:20.46#abcon#<5=/07 1.4 1.6 15.68 881019.7\r\n> 2006.145.18:37:20.48#abcon#{5=INTERFACE CLEAR} 2006.145.18:37:20.49#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.18:37:20.49#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.18:37:20.49#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.18:37:20.49#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.18:37:20.49$vck44/vb=7,4 2006.145.18:37:20.49#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.18:37:20.49#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.18:37:20.49#ibcon#ireg 11 cls_cnt 2 2006.145.18:37:20.49#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:37:20.54#abcon#[5=S1D000X0/0*\r\n] 2006.145.18:37:20.55#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:37:20.55#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:37:20.57#ibcon#[27=AT07-04\r\n] 2006.145.18:37:20.60#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:37:20.60#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:37:20.60#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.18:37:20.60#ibcon#ireg 7 cls_cnt 0 2006.145.18:37:20.60#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:37:20.72#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:37:20.72#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:37:20.74#ibcon#[27=USB\r\n] 2006.145.18:37:20.77#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:37:20.77#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:37:20.77#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.18:37:20.77#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.18:37:20.77$vck44/vblo=8,744.99 2006.145.18:37:20.77#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.18:37:20.77#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.18:37:20.77#ibcon#ireg 17 cls_cnt 0 2006.145.18:37:20.77#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:37:20.77#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:37:20.77#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:37:20.79#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.18:37:20.83#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:37:20.83#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:37:20.83#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.18:37:20.83#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.18:37:20.83$vck44/vb=8,4 2006.145.18:37:20.83#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.18:37:20.83#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.18:37:20.83#ibcon#ireg 11 cls_cnt 2 2006.145.18:37:20.83#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:37:20.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:37:20.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:37:20.91#ibcon#[27=AT08-04\r\n] 2006.145.18:37:20.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:37:20.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:37:20.94#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.18:37:20.94#ibcon#ireg 7 cls_cnt 0 2006.145.18:37:20.94#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:37:21.06#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:37:21.06#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:37:21.08#ibcon#[27=USB\r\n] 2006.145.18:37:21.11#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:37:21.11#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:37:21.11#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.18:37:21.11#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.18:37:21.11$vck44/vabw=wide 2006.145.18:37:21.11#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.18:37:21.11#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.18:37:21.11#ibcon#ireg 8 cls_cnt 0 2006.145.18:37:21.11#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.18:37:21.11#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.18:37:21.11#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.18:37:21.13#ibcon#[25=BW32\r\n] 2006.145.18:37:21.16#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.18:37:21.16#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.18:37:21.16#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.18:37:21.16#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.18:37:21.16$vck44/vbbw=wide 2006.145.18:37:21.16#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.18:37:21.16#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.18:37:21.16#ibcon#ireg 8 cls_cnt 0 2006.145.18:37:21.16#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.18:37:21.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.18:37:21.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.18:37:21.25#ibcon#[27=BW32\r\n] 2006.145.18:37:21.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.18:37:21.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.18:37:21.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.18:37:21.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.18:37:21.28$setupk4/ifdk4 2006.145.18:37:21.28$ifdk4/lo= 2006.145.18:37:21.28$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.18:37:21.28$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.18:37:21.28$ifdk4/patch= 2006.145.18:37:21.28$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.18:37:21.28$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.18:37:21.28$setupk4/!*+20s 2006.145.18:37:30.14#trakl#Source acquired 2006.145.18:37:30.63#abcon#<5=/07 1.4 1.7 15.68 881019.8\r\n> 2006.145.18:37:30.65#abcon#{5=INTERFACE CLEAR} 2006.145.18:37:30.71#abcon#[5=S1D000X0/0*\r\n] 2006.145.18:37:31.14#flagr#flagr/antenna,acquired 2006.145.18:37:35.70$setupk4/"tpicd 2006.145.18:37:35.70$setupk4/echo=off 2006.145.18:37:35.70$setupk4/xlog=off 2006.145.18:37:35.70:!2006.145.18:37:39 2006.145.18:37:39.00:preob 2006.145.18:37:39.14/onsource/TRACKING 2006.145.18:37:39.14:!2006.145.18:37:49 2006.145.18:37:49.00:"tape 2006.145.18:37:49.00:"st=record 2006.145.18:37:49.00:data_valid=on 2006.145.18:37:49.00:midob 2006.145.18:37:49.14/onsource/TRACKING 2006.145.18:37:49.14/wx/15.68,1019.7,88 2006.145.18:37:49.28/cable/+6.5510E-03 2006.145.18:37:50.37/va/01,08,usb,yes,29,31 2006.145.18:37:50.37/va/02,07,usb,yes,31,32 2006.145.18:37:50.37/va/03,08,usb,yes,28,29 2006.145.18:37:50.37/va/04,07,usb,yes,32,34 2006.145.18:37:50.37/va/05,04,usb,yes,28,28 2006.145.18:37:50.37/va/06,04,usb,yes,31,31 2006.145.18:37:50.37/va/07,04,usb,yes,32,33 2006.145.18:37:50.37/va/08,04,usb,yes,27,32 2006.145.18:37:50.60/valo/01,524.99,yes,locked 2006.145.18:37:50.60/valo/02,534.99,yes,locked 2006.145.18:37:50.60/valo/03,564.99,yes,locked 2006.145.18:37:50.60/valo/04,624.99,yes,locked 2006.145.18:37:50.60/valo/05,734.99,yes,locked 2006.145.18:37:50.60/valo/06,814.99,yes,locked 2006.145.18:37:50.60/valo/07,864.99,yes,locked 2006.145.18:37:50.60/valo/08,884.99,yes,locked 2006.145.18:37:51.69/vb/01,03,usb,yes,37,34 2006.145.18:37:51.69/vb/02,04,usb,yes,32,32 2006.145.18:37:51.69/vb/03,04,usb,yes,29,32 2006.145.18:37:51.69/vb/04,04,usb,yes,33,32 2006.145.18:37:51.69/vb/05,04,usb,yes,25,28 2006.145.18:37:51.69/vb/06,04,usb,yes,30,26 2006.145.18:37:51.69/vb/07,04,usb,yes,30,29 2006.145.18:37:51.69/vb/08,04,usb,yes,27,31 2006.145.18:37:51.93/vblo/01,629.99,yes,locked 2006.145.18:37:51.93/vblo/02,634.99,yes,locked 2006.145.18:37:51.93/vblo/03,649.99,yes,locked 2006.145.18:37:51.93/vblo/04,679.99,yes,locked 2006.145.18:37:51.93/vblo/05,709.99,yes,locked 2006.145.18:37:51.93/vblo/06,719.99,yes,locked 2006.145.18:37:51.93/vblo/07,734.99,yes,locked 2006.145.18:37:51.93/vblo/08,744.99,yes,locked 2006.145.18:37:52.08/vabw/8 2006.145.18:37:52.23/vbbw/8 2006.145.18:37:52.32/xfe/off,on,15.2 2006.145.18:37:52.70/ifatt/23,28,28,28 2006.145.18:37:53.07/fmout-gps/S +4.6E-08 2006.145.18:37:53.11:!2006.145.18:38:29 2006.145.18:38:29.01:data_valid=off 2006.145.18:38:29.01:"et 2006.145.18:38:29.02:!+3s 2006.145.18:38:32.03:"tape 2006.145.18:38:32.03:postob 2006.145.18:38:32.24/cable/+6.5505E-03 2006.145.18:38:32.24/wx/15.68,1019.8,88 2006.145.18:38:32.32/fmout-gps/S +4.6E-08 2006.145.18:38:32.32:scan_name=145-1839,jd0605,40 2006.145.18:38:32.32:source=3c345,164258.81,394837.0,2000.0,ccw 2006.145.18:38:34.14#flagr#flagr/antenna,new-source 2006.145.18:38:34.14:checkk5 2006.145.18:38:34.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.18:38:35.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.18:38:35.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.18:38:35.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.18:38:36.33/chk_obsdata//k5ts1/T1451837??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.18:38:36.78/chk_obsdata//k5ts2/T1451837??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.18:38:37.21/chk_obsdata//k5ts3/T1451837??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.18:38:37.66/chk_obsdata//k5ts4/T1451837??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.18:38:38.43/k5log//k5ts1_log_newline 2006.145.18:38:39.21/k5log//k5ts2_log_newline 2006.145.18:38:39.95/k5log//k5ts3_log_newline 2006.145.18:38:40.69/k5log//k5ts4_log_newline 2006.145.18:38:40.72/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.18:38:40.72:setupk4=1 2006.145.18:38:40.72$setupk4/echo=on 2006.145.18:38:40.72$setupk4/pcalon 2006.145.18:38:40.72$pcalon/"no phase cal control is implemented here 2006.145.18:38:40.72$setupk4/"tpicd=stop 2006.145.18:38:40.72$setupk4/"rec=synch_on 2006.145.18:38:40.72$setupk4/"rec_mode=128 2006.145.18:38:40.72$setupk4/!* 2006.145.18:38:40.72$setupk4/recpk4 2006.145.18:38:40.72$recpk4/recpatch= 2006.145.18:38:40.72$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.18:38:40.72$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.18:38:40.72$setupk4/vck44 2006.145.18:38:40.72$vck44/valo=1,524.99 2006.145.18:38:40.72#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.18:38:40.72#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.18:38:40.72#ibcon#ireg 17 cls_cnt 0 2006.145.18:38:40.72#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:38:40.72#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:38:40.72#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:38:40.76#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.18:38:40.81#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:38:40.81#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:38:40.81#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.18:38:40.81#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.18:38:40.81$vck44/va=1,8 2006.145.18:38:40.81#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.18:38:40.81#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.18:38:40.81#ibcon#ireg 11 cls_cnt 2 2006.145.18:38:40.81#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.18:38:40.81#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.18:38:40.81#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.18:38:40.83#ibcon#[25=AT01-08\r\n] 2006.145.18:38:40.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.18:38:40.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.18:38:40.86#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.18:38:40.86#ibcon#ireg 7 cls_cnt 0 2006.145.18:38:40.86#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.18:38:40.99#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.18:38:40.99#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.18:38:41.00#ibcon#[25=USB\r\n] 2006.145.18:38:41.03#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.18:38:41.03#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.18:38:41.03#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.18:38:41.03#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.18:38:41.03$vck44/valo=2,534.99 2006.145.18:38:41.03#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.18:38:41.03#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.18:38:41.03#ibcon#ireg 17 cls_cnt 0 2006.145.18:38:41.03#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:38:41.03#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:38:41.03#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:38:41.06#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.18:38:41.10#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:38:41.10#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:38:41.10#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.18:38:41.10#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.18:38:41.10$vck44/va=2,7 2006.145.18:38:41.10#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.18:38:41.10#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.18:38:41.10#ibcon#ireg 11 cls_cnt 2 2006.145.18:38:41.10#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.18:38:41.15#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.18:38:41.15#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.18:38:41.17#ibcon#[25=AT02-07\r\n] 2006.145.18:38:41.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.18:38:41.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.18:38:41.20#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.18:38:41.20#ibcon#ireg 7 cls_cnt 0 2006.145.18:38:41.20#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.18:38:41.32#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.18:38:41.32#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.18:38:41.34#ibcon#[25=USB\r\n] 2006.145.18:38:41.37#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.18:38:41.37#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.18:38:41.37#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.18:38:41.37#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.18:38:41.37$vck44/valo=3,564.99 2006.145.18:38:41.37#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.18:38:41.37#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.18:38:41.37#ibcon#ireg 17 cls_cnt 0 2006.145.18:38:41.37#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:38:41.37#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:38:41.37#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:38:41.39#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.18:38:41.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:38:41.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:38:41.43#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.18:38:41.43#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.18:38:41.43$vck44/va=3,8 2006.145.18:38:41.43#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.18:38:41.43#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.18:38:41.43#ibcon#ireg 11 cls_cnt 2 2006.145.18:38:41.43#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.18:38:41.49#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.18:38:41.49#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.18:38:41.51#ibcon#[25=AT03-08\r\n] 2006.145.18:38:41.54#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.18:38:41.54#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.18:38:41.54#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.18:38:41.54#ibcon#ireg 7 cls_cnt 0 2006.145.18:38:41.54#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.18:38:41.66#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.18:38:41.66#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.18:38:41.68#ibcon#[25=USB\r\n] 2006.145.18:38:41.71#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.18:38:41.71#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.18:38:41.71#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.18:38:41.71#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.18:38:41.71$vck44/valo=4,624.99 2006.145.18:38:41.71#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.18:38:41.71#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.18:38:41.71#ibcon#ireg 17 cls_cnt 0 2006.145.18:38:41.71#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.18:38:41.71#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.18:38:41.71#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.18:38:41.73#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.18:38:41.77#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.18:38:41.77#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.18:38:41.77#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.18:38:41.77#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.18:38:41.77$vck44/va=4,7 2006.145.18:38:41.77#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.18:38:41.77#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.18:38:41.77#ibcon#ireg 11 cls_cnt 2 2006.145.18:38:41.77#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.18:38:41.83#abcon#<5=/07 1.5 1.7 15.67 881019.8\r\n> 2006.145.18:38:41.83#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.18:38:41.83#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.18:38:41.85#ibcon#[25=AT04-07\r\n] 2006.145.18:38:41.85#abcon#{5=INTERFACE CLEAR} 2006.145.18:38:41.88#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.18:38:41.88#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.18:38:41.88#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.18:38:41.88#ibcon#ireg 7 cls_cnt 0 2006.145.18:38:41.88#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.18:38:41.91#abcon#[5=S1D000X0/0*\r\n] 2006.145.18:38:42.00#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.18:38:42.00#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.18:38:42.02#ibcon#[25=USB\r\n] 2006.145.18:38:42.05#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.18:38:42.05#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.18:38:42.05#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.18:38:42.05#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.18:38:42.05$vck44/valo=5,734.99 2006.145.18:38:42.05#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.18:38:42.05#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.18:38:42.05#ibcon#ireg 17 cls_cnt 0 2006.145.18:38:42.05#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:38:42.05#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:38:42.05#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:38:42.07#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.18:38:42.11#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:38:42.11#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:38:42.11#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.18:38:42.11#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.18:38:42.11$vck44/va=5,4 2006.145.18:38:42.11#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.18:38:42.11#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.18:38:42.11#ibcon#ireg 11 cls_cnt 2 2006.145.18:38:42.11#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:38:42.17#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:38:42.17#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:38:42.19#ibcon#[25=AT05-04\r\n] 2006.145.18:38:42.22#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:38:42.22#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:38:42.22#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.18:38:42.22#ibcon#ireg 7 cls_cnt 0 2006.145.18:38:42.22#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:38:42.34#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:38:42.34#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:38:42.36#ibcon#[25=USB\r\n] 2006.145.18:38:42.39#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:38:42.39#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:38:42.39#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.18:38:42.39#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.18:38:42.39$vck44/valo=6,814.99 2006.145.18:38:42.39#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.18:38:42.39#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.18:38:42.39#ibcon#ireg 17 cls_cnt 0 2006.145.18:38:42.39#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:38:42.39#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:38:42.39#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:38:42.41#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.18:38:42.45#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:38:42.45#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:38:42.45#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.18:38:42.45#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.18:38:42.45$vck44/va=6,4 2006.145.18:38:42.45#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.18:38:42.45#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.18:38:42.45#ibcon#ireg 11 cls_cnt 2 2006.145.18:38:42.45#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:38:42.51#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:38:42.51#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:38:42.53#ibcon#[25=AT06-04\r\n] 2006.145.18:38:42.56#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:38:42.56#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:38:42.56#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.18:38:42.56#ibcon#ireg 7 cls_cnt 0 2006.145.18:38:42.56#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:38:42.68#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:38:42.68#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:38:42.70#ibcon#[25=USB\r\n] 2006.145.18:38:42.73#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:38:42.73#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:38:42.73#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.18:38:42.73#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.18:38:42.73$vck44/valo=7,864.99 2006.145.18:38:42.73#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.18:38:42.73#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.18:38:42.73#ibcon#ireg 17 cls_cnt 0 2006.145.18:38:42.73#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:38:42.73#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:38:42.73#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:38:42.75#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.18:38:42.79#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:38:42.79#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:38:42.79#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.18:38:42.79#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.18:38:42.79$vck44/va=7,4 2006.145.18:38:42.79#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.18:38:42.79#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.18:38:42.79#ibcon#ireg 11 cls_cnt 2 2006.145.18:38:42.79#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:38:42.85#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:38:42.85#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:38:42.87#ibcon#[25=AT07-04\r\n] 2006.145.18:38:42.90#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:38:42.90#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:38:42.90#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.18:38:42.90#ibcon#ireg 7 cls_cnt 0 2006.145.18:38:42.90#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:38:43.02#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:38:43.02#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:38:43.04#ibcon#[25=USB\r\n] 2006.145.18:38:43.07#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:38:43.07#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:38:43.07#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.18:38:43.07#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.18:38:43.07$vck44/valo=8,884.99 2006.145.18:38:43.07#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.18:38:43.07#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.18:38:43.07#ibcon#ireg 17 cls_cnt 0 2006.145.18:38:43.07#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:38:43.07#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:38:43.07#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:38:43.09#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.18:38:43.13#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:38:43.13#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:38:43.13#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.18:38:43.13#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.18:38:43.13$vck44/va=8,4 2006.145.18:38:43.13#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.18:38:43.13#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.18:38:43.13#ibcon#ireg 11 cls_cnt 2 2006.145.18:38:43.13#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.18:38:43.19#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.18:38:43.19#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.18:38:43.21#ibcon#[25=AT08-04\r\n] 2006.145.18:38:43.24#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.18:38:43.24#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.18:38:43.24#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.18:38:43.24#ibcon#ireg 7 cls_cnt 0 2006.145.18:38:43.24#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.18:38:43.36#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.18:38:43.36#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.18:38:43.38#ibcon#[25=USB\r\n] 2006.145.18:38:43.41#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.18:38:43.41#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.18:38:43.41#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.18:38:43.41#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.18:38:43.41$vck44/vblo=1,629.99 2006.145.18:38:43.41#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.18:38:43.41#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.18:38:43.41#ibcon#ireg 17 cls_cnt 0 2006.145.18:38:43.41#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:38:43.41#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:38:43.41#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:38:43.44#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.18:38:43.49#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:38:43.49#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:38:43.49#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.18:38:43.49#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.18:38:43.49$vck44/vb=1,3 2006.145.18:38:43.49#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.18:38:43.49#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.18:38:43.49#ibcon#ireg 11 cls_cnt 2 2006.145.18:38:43.49#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.18:38:43.49#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.18:38:43.49#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.18:38:43.51#ibcon#[27=AT01-03\r\n] 2006.145.18:38:43.54#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.18:38:43.54#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.18:38:43.54#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.18:38:43.54#ibcon#ireg 7 cls_cnt 0 2006.145.18:38:43.54#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.18:38:43.66#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.18:38:43.66#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.18:38:43.68#ibcon#[27=USB\r\n] 2006.145.18:38:43.71#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.18:38:43.71#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.18:38:43.71#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.18:38:43.71#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.18:38:43.71$vck44/vblo=2,634.99 2006.145.18:38:43.71#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.18:38:43.71#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.18:38:43.71#ibcon#ireg 17 cls_cnt 0 2006.145.18:38:43.71#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:38:43.71#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:38:43.71#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:38:43.73#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.18:38:43.77#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:38:43.77#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:38:43.77#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.18:38:43.77#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.18:38:43.77$vck44/vb=2,4 2006.145.18:38:43.77#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.18:38:43.77#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.18:38:43.77#ibcon#ireg 11 cls_cnt 2 2006.145.18:38:43.77#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.18:38:43.83#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.18:38:43.83#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.18:38:43.85#ibcon#[27=AT02-04\r\n] 2006.145.18:38:43.88#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.18:38:43.88#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.18:38:43.88#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.18:38:43.88#ibcon#ireg 7 cls_cnt 0 2006.145.18:38:43.88#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.18:38:44.00#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.18:38:44.00#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.18:38:44.02#ibcon#[27=USB\r\n] 2006.145.18:38:44.05#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.18:38:44.05#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.18:38:44.05#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.18:38:44.05#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.18:38:44.05$vck44/vblo=3,649.99 2006.145.18:38:44.05#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.18:38:44.05#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.18:38:44.05#ibcon#ireg 17 cls_cnt 0 2006.145.18:38:44.05#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:38:44.05#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:38:44.05#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:38:44.07#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.18:38:44.11#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:38:44.11#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:38:44.11#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.18:38:44.11#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.18:38:44.11$vck44/vb=3,4 2006.145.18:38:44.11#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.18:38:44.11#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.18:38:44.11#ibcon#ireg 11 cls_cnt 2 2006.145.18:38:44.11#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.18:38:44.17#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.18:38:44.17#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.18:38:44.19#ibcon#[27=AT03-04\r\n] 2006.145.18:38:44.22#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.18:38:44.22#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.18:38:44.22#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.18:38:44.22#ibcon#ireg 7 cls_cnt 0 2006.145.18:38:44.22#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.18:38:44.34#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.18:38:44.34#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.18:38:44.36#ibcon#[27=USB\r\n] 2006.145.18:38:44.39#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.18:38:44.39#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.18:38:44.39#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.18:38:44.39#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.18:38:44.39$vck44/vblo=4,679.99 2006.145.18:38:44.39#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.18:38:44.39#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.18:38:44.39#ibcon#ireg 17 cls_cnt 0 2006.145.18:38:44.39#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.18:38:44.39#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.18:38:44.39#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.18:38:44.41#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.18:38:44.45#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.18:38:44.45#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.18:38:44.45#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.18:38:44.45#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.18:38:44.45$vck44/vb=4,4 2006.145.18:38:44.45#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.18:38:44.45#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.18:38:44.45#ibcon#ireg 11 cls_cnt 2 2006.145.18:38:44.45#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.18:38:44.51#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.18:38:44.51#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.18:38:44.53#ibcon#[27=AT04-04\r\n] 2006.145.18:38:44.56#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.18:38:44.56#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.18:38:44.56#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.18:38:44.56#ibcon#ireg 7 cls_cnt 0 2006.145.18:38:44.56#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.18:38:44.68#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.18:38:44.68#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.18:38:44.70#ibcon#[27=USB\r\n] 2006.145.18:38:44.73#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.18:38:44.73#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.18:38:44.73#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.18:38:44.73#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.18:38:44.73$vck44/vblo=5,709.99 2006.145.18:38:44.73#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.18:38:44.73#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.18:38:44.73#ibcon#ireg 17 cls_cnt 0 2006.145.18:38:44.73#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:38:44.73#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:38:44.73#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:38:44.75#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.18:38:44.79#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:38:44.79#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:38:44.79#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.18:38:44.79#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.18:38:44.79$vck44/vb=5,4 2006.145.18:38:44.79#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.18:38:44.79#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.18:38:44.79#ibcon#ireg 11 cls_cnt 2 2006.145.18:38:44.79#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.18:38:44.85#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.18:38:44.85#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.18:38:44.87#ibcon#[27=AT05-04\r\n] 2006.145.18:38:44.90#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.18:38:44.90#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.18:38:44.90#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.18:38:44.90#ibcon#ireg 7 cls_cnt 0 2006.145.18:38:44.90#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.18:38:45.02#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.18:38:45.02#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.18:38:45.04#ibcon#[27=USB\r\n] 2006.145.18:38:45.07#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.18:38:45.07#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.18:38:45.07#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.18:38:45.07#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.18:38:45.07$vck44/vblo=6,719.99 2006.145.18:38:45.07#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.18:38:45.07#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.18:38:45.07#ibcon#ireg 17 cls_cnt 0 2006.145.18:38:45.07#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:38:45.07#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:38:45.07#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:38:45.09#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.18:38:45.13#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:38:45.13#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:38:45.13#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.18:38:45.13#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.18:38:45.13$vck44/vb=6,4 2006.145.18:38:45.13#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.18:38:45.13#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.18:38:45.13#ibcon#ireg 11 cls_cnt 2 2006.145.18:38:45.13#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:38:45.19#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:38:45.19#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:38:45.21#ibcon#[27=AT06-04\r\n] 2006.145.18:38:45.24#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:38:45.24#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:38:45.24#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.18:38:45.24#ibcon#ireg 7 cls_cnt 0 2006.145.18:38:45.24#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:38:45.36#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:38:45.36#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:38:45.38#ibcon#[27=USB\r\n] 2006.145.18:38:45.41#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:38:45.41#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:38:45.41#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.18:38:45.41#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.18:38:45.41$vck44/vblo=7,734.99 2006.145.18:38:45.41#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.18:38:45.41#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.18:38:45.41#ibcon#ireg 17 cls_cnt 0 2006.145.18:38:45.41#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:38:45.41#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:38:45.41#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:38:45.43#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.18:38:45.47#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:38:45.47#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:38:45.47#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.18:38:45.47#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.18:38:45.47$vck44/vb=7,4 2006.145.18:38:45.47#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.18:38:45.47#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.18:38:45.47#ibcon#ireg 11 cls_cnt 2 2006.145.18:38:45.47#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:38:45.53#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:38:45.53#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:38:45.55#ibcon#[27=AT07-04\r\n] 2006.145.18:38:45.58#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:38:45.58#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:38:45.58#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.18:38:45.58#ibcon#ireg 7 cls_cnt 0 2006.145.18:38:45.58#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:38:45.70#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:38:45.70#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:38:45.72#ibcon#[27=USB\r\n] 2006.145.18:38:45.75#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:38:45.75#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:38:45.75#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.18:38:45.75#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.18:38:45.75$vck44/vblo=8,744.99 2006.145.18:38:45.75#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.18:38:45.75#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.18:38:45.75#ibcon#ireg 17 cls_cnt 0 2006.145.18:38:45.75#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:38:45.75#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:38:45.75#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:38:45.77#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.18:38:45.81#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:38:45.81#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:38:45.81#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.18:38:45.81#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.18:38:45.81$vck44/vb=8,4 2006.145.18:38:45.81#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.18:38:45.81#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.18:38:45.81#ibcon#ireg 11 cls_cnt 2 2006.145.18:38:45.81#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:38:45.87#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:38:45.87#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:38:45.89#ibcon#[27=AT08-04\r\n] 2006.145.18:38:45.92#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:38:45.92#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:38:45.92#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.18:38:45.92#ibcon#ireg 7 cls_cnt 0 2006.145.18:38:45.92#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:38:46.04#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:38:46.04#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:38:46.06#ibcon#[27=USB\r\n] 2006.145.18:38:46.09#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:38:46.09#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:38:46.09#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.18:38:46.09#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.18:38:46.09$vck44/vabw=wide 2006.145.18:38:46.09#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.18:38:46.09#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.18:38:46.09#ibcon#ireg 8 cls_cnt 0 2006.145.18:38:46.09#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:38:46.09#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:38:46.09#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:38:46.11#ibcon#[25=BW32\r\n] 2006.145.18:38:46.14#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:38:46.14#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:38:46.14#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.18:38:46.14#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.18:38:46.14$vck44/vbbw=wide 2006.145.18:38:46.14#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.18:38:46.14#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.18:38:46.14#ibcon#ireg 8 cls_cnt 0 2006.145.18:38:46.14#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.18:38:46.21#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.18:38:46.21#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.18:38:46.23#ibcon#[27=BW32\r\n] 2006.145.18:38:46.26#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.18:38:46.26#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.18:38:46.26#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.18:38:46.26#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.18:38:46.26$setupk4/ifdk4 2006.145.18:38:46.26$ifdk4/lo= 2006.145.18:38:46.26$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.18:38:46.26$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.18:38:46.26$ifdk4/patch= 2006.145.18:38:46.26$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.18:38:46.26$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.18:38:46.26$setupk4/!*+20s 2006.145.18:38:52.00#abcon#<5=/07 1.5 1.7 15.67 881019.8\r\n> 2006.145.18:38:52.02#abcon#{5=INTERFACE CLEAR} 2006.145.18:38:52.08#abcon#[5=S1D000X0/0*\r\n] 2006.145.18:39:00.73$setupk4/"tpicd 2006.145.18:39:00.73$setupk4/echo=off 2006.145.18:39:00.73$setupk4/xlog=off 2006.145.18:39:00.73:!2006.145.18:39:27 2006.145.18:39:03.14#trakl#Source acquired 2006.145.18:39:05.14#flagr#flagr/antenna,acquired 2006.145.18:39:27.00:preob 2006.145.18:39:27.14/onsource/TRACKING 2006.145.18:39:27.14:!2006.145.18:39:37 2006.145.18:39:37.00:"tape 2006.145.18:39:37.00:"st=record 2006.145.18:39:37.00:data_valid=on 2006.145.18:39:37.00:midob 2006.145.18:39:38.14/onsource/TRACKING 2006.145.18:39:38.14/wx/15.67,1019.7,87 2006.145.18:39:38.21/cable/+6.5512E-03 2006.145.18:39:39.30/va/01,08,usb,yes,28,30 2006.145.18:39:39.30/va/02,07,usb,yes,30,31 2006.145.18:39:39.30/va/03,08,usb,yes,28,29 2006.145.18:39:39.30/va/04,07,usb,yes,31,33 2006.145.18:39:39.30/va/05,04,usb,yes,27,28 2006.145.18:39:39.30/va/06,04,usb,yes,31,31 2006.145.18:39:39.30/va/07,04,usb,yes,31,32 2006.145.18:39:39.30/va/08,04,usb,yes,26,32 2006.145.18:39:39.53/valo/01,524.99,yes,locked 2006.145.18:39:39.53/valo/02,534.99,yes,locked 2006.145.18:39:39.53/valo/03,564.99,yes,locked 2006.145.18:39:39.53/valo/04,624.99,yes,locked 2006.145.18:39:39.53/valo/05,734.99,yes,locked 2006.145.18:39:39.53/valo/06,814.99,yes,locked 2006.145.18:39:39.53/valo/07,864.99,yes,locked 2006.145.18:39:39.53/valo/08,884.99,yes,locked 2006.145.18:39:40.62/vb/01,03,usb,yes,36,34 2006.145.18:39:40.62/vb/02,04,usb,yes,32,31 2006.145.18:39:40.62/vb/03,04,usb,yes,28,31 2006.145.18:39:40.62/vb/04,04,usb,yes,33,32 2006.145.18:39:40.62/vb/05,04,usb,yes,26,28 2006.145.18:39:40.62/vb/06,04,usb,yes,30,26 2006.145.18:39:40.62/vb/07,04,usb,yes,29,29 2006.145.18:39:40.62/vb/08,04,usb,yes,27,30 2006.145.18:39:40.85/vblo/01,629.99,yes,locked 2006.145.18:39:40.85/vblo/02,634.99,yes,locked 2006.145.18:39:40.85/vblo/03,649.99,yes,locked 2006.145.18:39:40.85/vblo/04,679.99,yes,locked 2006.145.18:39:40.85/vblo/05,709.99,yes,locked 2006.145.18:39:40.85/vblo/06,719.99,yes,locked 2006.145.18:39:40.85/vblo/07,734.99,yes,locked 2006.145.18:39:40.85/vblo/08,744.99,yes,locked 2006.145.18:39:41.00/vabw/8 2006.145.18:39:41.15/vbbw/8 2006.145.18:39:41.32/xfe/off,on,15.2 2006.145.18:39:41.72/ifatt/23,28,28,28 2006.145.18:39:42.07/fmout-gps/S +4.6E-08 2006.145.18:39:42.11:!2006.145.18:40:17 2006.145.18:40:17.00:data_valid=off 2006.145.18:40:17.00:"et 2006.145.18:40:17.01:!+3s 2006.145.18:40:20.02:"tape 2006.145.18:40:20.02:postob 2006.145.18:40:20.09/cable/+6.5511E-03 2006.145.18:40:20.09/wx/15.67,1019.8,87 2006.145.18:40:21.08/fmout-gps/S +4.6E-08 2006.145.18:40:21.08:scan_name=145-1841,jd0605,210 2006.145.18:40:21.09:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.145.18:40:22.14#flagr#flagr/antenna,new-source 2006.145.18:40:22.14:checkk5 2006.145.18:40:22.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.18:40:23.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.18:40:23.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.18:40:23.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.18:40:24.33/chk_obsdata//k5ts1/T1451839??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.18:40:24.78/chk_obsdata//k5ts2/T1451839??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.18:40:25.20/chk_obsdata//k5ts3/T1451839??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.18:40:25.64/chk_obsdata//k5ts4/T1451839??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.18:40:26.40/k5log//k5ts1_log_newline 2006.145.18:40:27.15/k5log//k5ts2_log_newline 2006.145.18:40:27.89/k5log//k5ts3_log_newline 2006.145.18:40:28.63/k5log//k5ts4_log_newline 2006.145.18:40:28.66/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.18:40:28.66:setupk4=1 2006.145.18:40:28.66$setupk4/echo=on 2006.145.18:40:28.66$setupk4/pcalon 2006.145.18:40:28.66$pcalon/"no phase cal control is implemented here 2006.145.18:40:28.66$setupk4/"tpicd=stop 2006.145.18:40:28.66$setupk4/"rec=synch_on 2006.145.18:40:28.66$setupk4/"rec_mode=128 2006.145.18:40:28.66$setupk4/!* 2006.145.18:40:28.66$setupk4/recpk4 2006.145.18:40:28.66$recpk4/recpatch= 2006.145.18:40:28.67$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.18:40:28.67$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.18:40:28.67$setupk4/vck44 2006.145.18:40:28.67$vck44/valo=1,524.99 2006.145.18:40:28.67#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.18:40:28.67#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.18:40:28.67#ibcon#ireg 17 cls_cnt 0 2006.145.18:40:28.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.18:40:28.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.18:40:28.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.18:40:28.70#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.18:40:28.75#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.18:40:28.75#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.18:40:28.75#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.18:40:28.75#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.18:40:28.75$vck44/va=1,8 2006.145.18:40:28.75#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.18:40:28.75#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.18:40:28.75#ibcon#ireg 11 cls_cnt 2 2006.145.18:40:28.75#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.18:40:28.75#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.18:40:28.75#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.18:40:28.77#ibcon#[25=AT01-08\r\n] 2006.145.18:40:28.80#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.18:40:28.80#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.18:40:28.80#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.18:40:28.80#ibcon#ireg 7 cls_cnt 0 2006.145.18:40:28.80#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.18:40:28.93#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.18:40:28.93#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.18:40:28.94#ibcon#[25=USB\r\n] 2006.145.18:40:28.97#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.18:40:28.97#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.18:40:28.97#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.18:40:28.97#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.18:40:28.97$vck44/valo=2,534.99 2006.145.18:40:28.97#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.18:40:28.97#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.18:40:28.97#ibcon#ireg 17 cls_cnt 0 2006.145.18:40:28.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.18:40:28.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.18:40:28.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.18:40:29.00#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.18:40:29.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.18:40:29.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.18:40:29.04#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.18:40:29.04#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.18:40:29.04$vck44/va=2,7 2006.145.18:40:29.04#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.18:40:29.04#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.18:40:29.04#ibcon#ireg 11 cls_cnt 2 2006.145.18:40:29.04#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.18:40:29.10#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.18:40:29.10#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.18:40:29.12#ibcon#[25=AT02-07\r\n] 2006.145.18:40:29.15#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.18:40:29.15#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.18:40:29.15#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.18:40:29.15#ibcon#ireg 7 cls_cnt 0 2006.145.18:40:29.15#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.18:40:29.27#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.18:40:29.27#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.18:40:29.29#ibcon#[25=USB\r\n] 2006.145.18:40:29.32#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.18:40:29.32#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.18:40:29.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.18:40:29.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.18:40:29.32$vck44/valo=3,564.99 2006.145.18:40:29.32#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.18:40:29.32#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.18:40:29.32#ibcon#ireg 17 cls_cnt 0 2006.145.18:40:29.32#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.18:40:29.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.18:40:29.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.18:40:29.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.18:40:29.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.18:40:29.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.18:40:29.38#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.18:40:29.38#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.18:40:29.38$vck44/va=3,8 2006.145.18:40:29.38#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.18:40:29.38#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.18:40:29.38#ibcon#ireg 11 cls_cnt 2 2006.145.18:40:29.38#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.18:40:29.44#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.18:40:29.44#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.18:40:29.46#ibcon#[25=AT03-08\r\n] 2006.145.18:40:29.49#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.18:40:29.49#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.18:40:29.49#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.18:40:29.49#ibcon#ireg 7 cls_cnt 0 2006.145.18:40:29.49#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.18:40:29.61#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.18:40:29.61#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.18:40:29.63#ibcon#[25=USB\r\n] 2006.145.18:40:29.66#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.18:40:29.66#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.18:40:29.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.18:40:29.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.18:40:29.66$vck44/valo=4,624.99 2006.145.18:40:29.66#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.18:40:29.66#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.18:40:29.66#ibcon#ireg 17 cls_cnt 0 2006.145.18:40:29.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.18:40:29.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.18:40:29.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.18:40:29.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.18:40:29.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.18:40:29.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.18:40:29.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.18:40:29.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.18:40:29.72$vck44/va=4,7 2006.145.18:40:29.72#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.18:40:29.72#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.18:40:29.72#ibcon#ireg 11 cls_cnt 2 2006.145.18:40:29.72#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.18:40:29.78#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.18:40:29.78#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.18:40:29.80#ibcon#[25=AT04-07\r\n] 2006.145.18:40:29.83#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.18:40:29.83#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.18:40:29.83#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.18:40:29.83#ibcon#ireg 7 cls_cnt 0 2006.145.18:40:29.83#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.18:40:29.95#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.18:40:29.95#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.18:40:29.97#ibcon#[25=USB\r\n] 2006.145.18:40:30.00#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.18:40:30.00#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.18:40:30.00#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.18:40:30.00#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.18:40:30.00$vck44/valo=5,734.99 2006.145.18:40:30.00#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.18:40:30.00#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.18:40:30.00#ibcon#ireg 17 cls_cnt 0 2006.145.18:40:30.00#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.18:40:30.00#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.18:40:30.00#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.18:40:30.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.18:40:30.06#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.18:40:30.06#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.18:40:30.06#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.18:40:30.06#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.18:40:30.06$vck44/va=5,4 2006.145.18:40:30.06#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.18:40:30.06#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.18:40:30.06#ibcon#ireg 11 cls_cnt 2 2006.145.18:40:30.06#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.18:40:30.12#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.18:40:30.12#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.18:40:30.14#ibcon#[25=AT05-04\r\n] 2006.145.18:40:30.18#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.18:40:30.18#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.18:40:30.18#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.18:40:30.18#ibcon#ireg 7 cls_cnt 0 2006.145.18:40:30.18#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.18:40:30.29#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.18:40:30.29#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.18:40:30.31#ibcon#[25=USB\r\n] 2006.145.18:40:30.34#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.18:40:30.34#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.18:40:30.34#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.18:40:30.34#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.18:40:30.34$vck44/valo=6,814.99 2006.145.18:40:30.34#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.18:40:30.34#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.18:40:30.34#ibcon#ireg 17 cls_cnt 0 2006.145.18:40:30.34#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.18:40:30.34#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.18:40:30.34#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.18:40:30.37#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.18:40:30.41#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.18:40:30.41#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.18:40:30.41#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.18:40:30.41#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.18:40:30.41$vck44/va=6,4 2006.145.18:40:30.41#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.18:40:30.41#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.18:40:30.41#ibcon#ireg 11 cls_cnt 2 2006.145.18:40:30.41#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.18:40:30.46#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.18:40:30.46#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.18:40:30.48#ibcon#[25=AT06-04\r\n] 2006.145.18:40:30.51#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.18:40:30.51#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.18:40:30.51#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.18:40:30.51#ibcon#ireg 7 cls_cnt 0 2006.145.18:40:30.51#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.18:40:30.63#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.18:40:30.63#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.18:40:30.65#ibcon#[25=USB\r\n] 2006.145.18:40:30.68#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.18:40:30.68#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.18:40:30.68#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.18:40:30.68#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.18:40:30.68$vck44/valo=7,864.99 2006.145.18:40:30.68#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.18:40:30.68#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.18:40:30.68#ibcon#ireg 17 cls_cnt 0 2006.145.18:40:30.68#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.18:40:30.68#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.18:40:30.68#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.18:40:30.70#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.18:40:30.74#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.18:40:30.74#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.18:40:30.74#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.18:40:30.74#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.18:40:30.74$vck44/va=7,4 2006.145.18:40:30.74#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.18:40:30.74#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.18:40:30.74#ibcon#ireg 11 cls_cnt 2 2006.145.18:40:30.74#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.18:40:30.80#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.18:40:30.80#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.18:40:30.82#ibcon#[25=AT07-04\r\n] 2006.145.18:40:30.85#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.18:40:30.85#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.18:40:30.85#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.18:40:30.85#ibcon#ireg 7 cls_cnt 0 2006.145.18:40:30.85#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.18:40:30.97#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.18:40:30.97#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.18:40:30.99#ibcon#[25=USB\r\n] 2006.145.18:40:31.02#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.18:40:31.02#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.18:40:31.02#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.18:40:31.02#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.18:40:31.02$vck44/valo=8,884.99 2006.145.18:40:31.02#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.18:40:31.02#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.18:40:31.02#ibcon#ireg 17 cls_cnt 0 2006.145.18:40:31.02#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.18:40:31.02#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.18:40:31.02#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.18:40:31.04#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.18:40:31.08#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.18:40:31.08#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.18:40:31.08#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.18:40:31.08#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.18:40:31.08$vck44/va=8,4 2006.145.18:40:31.08#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.18:40:31.08#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.18:40:31.08#ibcon#ireg 11 cls_cnt 2 2006.145.18:40:31.08#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.18:40:31.14#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.18:40:31.14#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.18:40:31.16#ibcon#[25=AT08-04\r\n] 2006.145.18:40:31.19#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.18:40:31.19#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.18:40:31.19#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.18:40:31.19#ibcon#ireg 7 cls_cnt 0 2006.145.18:40:31.19#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.18:40:31.31#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.18:40:31.31#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.18:40:31.33#ibcon#[25=USB\r\n] 2006.145.18:40:31.36#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.18:40:31.36#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.18:40:31.36#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.18:40:31.36#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.18:40:31.36$vck44/vblo=1,629.99 2006.145.18:40:31.36#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.18:40:31.36#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.18:40:31.36#ibcon#ireg 17 cls_cnt 0 2006.145.18:40:31.36#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.18:40:31.36#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.18:40:31.36#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.18:40:31.38#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.18:40:31.42#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.18:40:31.42#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.18:40:31.42#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.18:40:31.42#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.18:40:31.42$vck44/vb=1,3 2006.145.18:40:31.42#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.18:40:31.42#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.18:40:31.42#ibcon#ireg 11 cls_cnt 2 2006.145.18:40:31.42#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.18:40:31.42#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.18:40:31.42#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.18:40:31.44#ibcon#[27=AT01-03\r\n] 2006.145.18:40:31.47#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.18:40:31.47#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.18:40:31.47#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.18:40:31.47#ibcon#ireg 7 cls_cnt 0 2006.145.18:40:31.47#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.18:40:31.59#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.18:40:31.59#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.18:40:31.61#ibcon#[27=USB\r\n] 2006.145.18:40:31.64#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.18:40:31.64#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.18:40:31.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.18:40:31.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.18:40:31.64$vck44/vblo=2,634.99 2006.145.18:40:31.64#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.18:40:31.64#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.18:40:31.64#ibcon#ireg 17 cls_cnt 0 2006.145.18:40:31.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.18:40:31.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.18:40:31.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.18:40:31.66#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.18:40:31.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.18:40:31.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.18:40:31.70#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.18:40:31.70#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.18:40:31.70$vck44/vb=2,4 2006.145.18:40:31.70#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.18:40:31.70#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.18:40:31.70#ibcon#ireg 11 cls_cnt 2 2006.145.18:40:31.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.18:40:31.76#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.18:40:31.76#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.18:40:31.78#ibcon#[27=AT02-04\r\n] 2006.145.18:40:31.81#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.18:40:31.81#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.18:40:31.81#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.18:40:31.81#ibcon#ireg 7 cls_cnt 0 2006.145.18:40:31.81#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.18:40:31.93#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.18:40:31.93#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.18:40:31.95#ibcon#[27=USB\r\n] 2006.145.18:40:31.98#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.18:40:31.98#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.18:40:31.98#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.18:40:31.98#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.18:40:31.98$vck44/vblo=3,649.99 2006.145.18:40:31.98#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.18:40:31.98#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.18:40:31.98#ibcon#ireg 17 cls_cnt 0 2006.145.18:40:31.98#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.18:40:31.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.18:40:31.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.18:40:32.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.18:40:32.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.18:40:32.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.18:40:32.04#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.18:40:32.04#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.18:40:32.04$vck44/vb=3,4 2006.145.18:40:32.04#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.18:40:32.04#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.18:40:32.04#ibcon#ireg 11 cls_cnt 2 2006.145.18:40:32.04#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.18:40:32.10#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.18:40:32.10#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.18:40:32.12#ibcon#[27=AT03-04\r\n] 2006.145.18:40:32.15#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.18:40:32.15#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.18:40:32.15#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.18:40:32.15#ibcon#ireg 7 cls_cnt 0 2006.145.18:40:32.15#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.18:40:32.27#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.18:40:32.27#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.18:40:32.29#ibcon#[27=USB\r\n] 2006.145.18:40:32.32#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.18:40:32.32#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.18:40:32.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.18:40:32.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.18:40:32.32$vck44/vblo=4,679.99 2006.145.18:40:32.32#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.18:40:32.32#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.18:40:32.32#ibcon#ireg 17 cls_cnt 0 2006.145.18:40:32.32#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.18:40:32.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.18:40:32.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.18:40:32.34#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.18:40:32.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.18:40:32.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.18:40:32.38#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.18:40:32.38#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.18:40:32.38$vck44/vb=4,4 2006.145.18:40:32.38#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.18:40:32.38#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.18:40:32.38#ibcon#ireg 11 cls_cnt 2 2006.145.18:40:32.38#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.18:40:32.44#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.18:40:32.44#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.18:40:32.46#ibcon#[27=AT04-04\r\n] 2006.145.18:40:32.49#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.18:40:32.49#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.18:40:32.49#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.18:40:32.49#ibcon#ireg 7 cls_cnt 0 2006.145.18:40:32.49#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.18:40:32.61#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.18:40:32.61#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.18:40:32.63#ibcon#[27=USB\r\n] 2006.145.18:40:32.66#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.18:40:32.66#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.18:40:32.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.18:40:32.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.18:40:32.66$vck44/vblo=5,709.99 2006.145.18:40:32.66#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.18:40:32.66#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.18:40:32.66#ibcon#ireg 17 cls_cnt 0 2006.145.18:40:32.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.18:40:32.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.18:40:32.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.18:40:32.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.18:40:32.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.18:40:32.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.18:40:32.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.18:40:32.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.18:40:32.72$vck44/vb=5,4 2006.145.18:40:32.72#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.18:40:32.72#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.18:40:32.72#ibcon#ireg 11 cls_cnt 2 2006.145.18:40:32.72#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.18:40:32.78#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.18:40:32.78#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.18:40:32.80#ibcon#[27=AT05-04\r\n] 2006.145.18:40:32.83#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.18:40:32.83#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.18:40:32.83#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.18:40:32.83#ibcon#ireg 7 cls_cnt 0 2006.145.18:40:32.83#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.18:40:32.95#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.18:40:32.95#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.18:40:32.97#ibcon#[27=USB\r\n] 2006.145.18:40:33.00#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.18:40:33.00#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.18:40:33.00#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.18:40:33.00#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.18:40:33.00$vck44/vblo=6,719.99 2006.145.18:40:33.00#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.18:40:33.00#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.18:40:33.00#ibcon#ireg 17 cls_cnt 0 2006.145.18:40:33.00#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.18:40:33.00#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.18:40:33.00#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.18:40:33.02#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.18:40:33.06#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.18:40:33.06#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.18:40:33.06#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.18:40:33.06#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.18:40:33.06$vck44/vb=6,4 2006.145.18:40:33.06#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.18:40:33.06#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.18:40:33.06#ibcon#ireg 11 cls_cnt 2 2006.145.18:40:33.06#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.18:40:33.12#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.18:40:33.12#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.18:40:33.14#ibcon#[27=AT06-04\r\n] 2006.145.18:40:33.17#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.18:40:33.17#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.18:40:33.17#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.18:40:33.17#ibcon#ireg 7 cls_cnt 0 2006.145.18:40:33.17#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.18:40:33.29#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.18:40:33.29#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.18:40:33.31#ibcon#[27=USB\r\n] 2006.145.18:40:33.34#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.18:40:33.34#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.18:40:33.34#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.18:40:33.34#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.18:40:33.34$vck44/vblo=7,734.99 2006.145.18:40:33.34#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.18:40:33.34#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.18:40:33.34#ibcon#ireg 17 cls_cnt 0 2006.145.18:40:33.34#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.18:40:33.34#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.18:40:33.34#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.18:40:33.36#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.18:40:33.40#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.18:40:33.40#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.18:40:33.40#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.18:40:33.40#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.18:40:33.40$vck44/vb=7,4 2006.145.18:40:33.40#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.18:40:33.40#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.18:40:33.40#ibcon#ireg 11 cls_cnt 2 2006.145.18:40:33.40#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.18:40:33.46#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.18:40:33.46#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.18:40:33.48#ibcon#[27=AT07-04\r\n] 2006.145.18:40:33.51#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.18:40:33.51#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.18:40:33.51#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.18:40:33.51#ibcon#ireg 7 cls_cnt 0 2006.145.18:40:33.51#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.18:40:33.63#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.18:40:33.63#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.18:40:33.65#ibcon#[27=USB\r\n] 2006.145.18:40:33.68#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.18:40:33.68#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.18:40:33.68#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.18:40:33.68#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.18:40:33.68$vck44/vblo=8,744.99 2006.145.18:40:33.68#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.18:40:33.68#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.18:40:33.68#ibcon#ireg 17 cls_cnt 0 2006.145.18:40:33.68#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:40:33.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:40:33.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:40:33.70#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.18:40:33.70#abcon#<5=/07 1.6 1.7 15.67 871019.8\r\n> 2006.145.18:40:33.72#abcon#{5=INTERFACE CLEAR} 2006.145.18:40:33.74#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:40:33.74#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:40:33.74#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.18:40:33.74#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.18:40:33.74$vck44/vb=8,4 2006.145.18:40:33.74#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.18:40:33.74#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.18:40:33.74#ibcon#ireg 11 cls_cnt 2 2006.145.18:40:33.74#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.18:40:33.78#abcon#[5=S1D000X0/0*\r\n] 2006.145.18:40:33.80#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.18:40:33.80#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.18:40:33.82#ibcon#[27=AT08-04\r\n] 2006.145.18:40:33.85#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.18:40:33.85#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.18:40:33.85#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.18:40:33.85#ibcon#ireg 7 cls_cnt 0 2006.145.18:40:33.85#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.18:40:33.97#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.18:40:33.97#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.18:40:33.99#ibcon#[27=USB\r\n] 2006.145.18:40:34.02#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.18:40:34.02#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.18:40:34.02#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.18:40:34.02#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.18:40:34.02$vck44/vabw=wide 2006.145.18:40:34.02#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.18:40:34.02#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.18:40:34.02#ibcon#ireg 8 cls_cnt 0 2006.145.18:40:34.02#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.18:40:34.02#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.18:40:34.02#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.18:40:34.04#ibcon#[25=BW32\r\n] 2006.145.18:40:34.07#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.18:40:34.07#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.18:40:34.07#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.18:40:34.07#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.18:40:34.07$vck44/vbbw=wide 2006.145.18:40:34.07#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.18:40:34.07#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.18:40:34.07#ibcon#ireg 8 cls_cnt 0 2006.145.18:40:34.07#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:40:34.14#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:40:34.14#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:40:34.16#ibcon#[27=BW32\r\n] 2006.145.18:40:34.19#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:40:34.19#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:40:34.19#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.18:40:34.19#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.18:40:34.19$setupk4/ifdk4 2006.145.18:40:34.19$ifdk4/lo= 2006.145.18:40:34.19$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.18:40:34.19$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.18:40:34.19$ifdk4/patch= 2006.145.18:40:34.19$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.18:40:34.19$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.18:40:34.19$setupk4/!*+20s 2006.145.18:40:43.87#abcon#<5=/07 1.6 1.7 15.67 871019.8\r\n> 2006.145.18:40:43.89#abcon#{5=INTERFACE CLEAR} 2006.145.18:40:43.95#abcon#[5=S1D000X0/0*\r\n] 2006.145.18:40:48.67$setupk4/"tpicd 2006.145.18:40:48.67$setupk4/echo=off 2006.145.18:40:48.67$setupk4/xlog=off 2006.145.18:40:48.67:!2006.145.18:41:21 2006.145.18:40:49.14#trakl#Source acquired 2006.145.18:40:50.14#flagr#flagr/antenna,acquired 2006.145.18:41:21.00:preob 2006.145.18:41:21.14/onsource/TRACKING 2006.145.18:41:21.14:!2006.145.18:41:31 2006.145.18:41:31.00:"tape 2006.145.18:41:31.00:"st=record 2006.145.18:41:31.00:data_valid=on 2006.145.18:41:31.00:midob 2006.145.18:41:32.14/onsource/TRACKING 2006.145.18:41:32.14/wx/15.68,1019.8,87 2006.145.18:41:32.29/cable/+6.5492E-03 2006.145.18:41:33.38/va/01,08,usb,yes,30,32 2006.145.18:41:33.38/va/02,07,usb,yes,32,33 2006.145.18:41:33.38/va/03,08,usb,yes,29,30 2006.145.18:41:33.38/va/04,07,usb,yes,33,35 2006.145.18:41:33.38/va/05,04,usb,yes,29,29 2006.145.18:41:33.38/va/06,04,usb,yes,32,32 2006.145.18:41:33.38/va/07,04,usb,yes,33,34 2006.145.18:41:33.38/va/08,04,usb,yes,28,33 2006.145.18:41:33.61/valo/01,524.99,yes,locked 2006.145.18:41:33.61/valo/02,534.99,yes,locked 2006.145.18:41:33.61/valo/03,564.99,yes,locked 2006.145.18:41:33.61/valo/04,624.99,yes,locked 2006.145.18:41:33.61/valo/05,734.99,yes,locked 2006.145.18:41:33.61/valo/06,814.99,yes,locked 2006.145.18:41:33.61/valo/07,864.99,yes,locked 2006.145.18:41:33.61/valo/08,884.99,yes,locked 2006.145.18:41:34.70/vb/01,03,usb,yes,37,34 2006.145.18:41:34.70/vb/02,04,usb,yes,32,32 2006.145.18:41:34.70/vb/03,04,usb,yes,29,32 2006.145.18:41:34.70/vb/04,04,usb,yes,34,32 2006.145.18:41:34.70/vb/05,04,usb,yes,26,29 2006.145.18:41:34.70/vb/06,04,usb,yes,31,27 2006.145.18:41:34.70/vb/07,04,usb,yes,30,30 2006.145.18:41:34.70/vb/08,04,usb,yes,28,31 2006.145.18:41:34.93/vblo/01,629.99,yes,locked 2006.145.18:41:34.93/vblo/02,634.99,yes,locked 2006.145.18:41:34.93/vblo/03,649.99,yes,locked 2006.145.18:41:34.93/vblo/04,679.99,yes,locked 2006.145.18:41:34.93/vblo/05,709.99,yes,locked 2006.145.18:41:34.93/vblo/06,719.99,yes,locked 2006.145.18:41:34.93/vblo/07,734.99,yes,locked 2006.145.18:41:34.93/vblo/08,744.99,yes,locked 2006.145.18:41:35.08/vabw/8 2006.145.18:41:35.23/vbbw/8 2006.145.18:41:35.32/xfe/off,on,15.5 2006.145.18:41:35.72/ifatt/23,28,28,28 2006.145.18:41:36.08/fmout-gps/S +4.8E-08 2006.145.18:41:36.12:!2006.145.18:45:01 2006.145.18:45:01.00:data_valid=off 2006.145.18:45:01.00:"et 2006.145.18:45:01.01:!+3s 2006.145.18:45:04.02:"tape 2006.145.18:45:04.02:postob 2006.145.18:45:04.21/cable/+6.5504E-03 2006.145.18:45:04.21/wx/15.69,1019.8,87 2006.145.18:45:04.29/fmout-gps/S +5.1E-08 2006.145.18:45:04.29:scan_name=145-1845,jd0605,70 2006.145.18:45:04.29:source=1308+326,131028.66,322043.8,2000.0,ccw 2006.145.18:45:05.14#flagr#flagr/antenna,new-source 2006.145.18:45:05.14:checkk5 2006.145.18:45:05.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.18:45:06.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.18:45:06.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.18:45:06.88/chk_autoobs//k5ts4/ autoobs is running! 2006.145.18:45:07.31/chk_obsdata//k5ts1/T1451841??a.dat file size is correct (nominal:840MB, actual:836MB). 2006.145.18:45:07.75/chk_obsdata//k5ts2/T1451841??b.dat file size is correct (nominal:840MB, actual:836MB). 2006.145.18:45:08.21/chk_obsdata//k5ts3/T1451841??c.dat file size is correct (nominal:840MB, actual:836MB). 2006.145.18:45:08.62/chk_obsdata//k5ts4/T1451841??d.dat file size is correct (nominal:840MB, actual:836MB). 2006.145.18:45:09.38/k5log//k5ts1_log_newline 2006.145.18:45:10.12/k5log//k5ts2_log_newline 2006.145.18:45:10.87/k5log//k5ts3_log_newline 2006.145.18:45:11.62/k5log//k5ts4_log_newline 2006.145.18:45:11.65/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.18:45:11.65:setupk4=1 2006.145.18:45:11.65$setupk4/echo=on 2006.145.18:45:11.65$setupk4/pcalon 2006.145.18:45:11.65$pcalon/"no phase cal control is implemented here 2006.145.18:45:11.65$setupk4/"tpicd=stop 2006.145.18:45:11.65$setupk4/"rec=synch_on 2006.145.18:45:11.65$setupk4/"rec_mode=128 2006.145.18:45:11.65$setupk4/!* 2006.145.18:45:11.65$setupk4/recpk4 2006.145.18:45:11.65$recpk4/recpatch= 2006.145.18:45:11.65$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.18:45:11.65$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.18:45:11.65$setupk4/vck44 2006.145.18:45:11.65$vck44/valo=1,524.99 2006.145.18:45:11.65#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.18:45:11.65#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.18:45:11.65#ibcon#ireg 17 cls_cnt 0 2006.145.18:45:11.65#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.18:45:11.65#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.18:45:11.65#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.18:45:11.69#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.18:45:11.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.18:45:11.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.18:45:11.74#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.18:45:11.74#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.18:45:11.74$vck44/va=1,8 2006.145.18:45:11.74#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.18:45:11.74#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.18:45:11.74#ibcon#ireg 11 cls_cnt 2 2006.145.18:45:11.74#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.18:45:11.74#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.18:45:11.74#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.18:45:11.76#ibcon#[25=AT01-08\r\n] 2006.145.18:45:11.79#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.18:45:11.79#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.18:45:11.79#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.18:45:11.79#ibcon#ireg 7 cls_cnt 0 2006.145.18:45:11.79#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.18:45:11.91#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.18:45:11.91#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.18:45:11.93#ibcon#[25=USB\r\n] 2006.145.18:45:11.96#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.18:45:11.96#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.18:45:11.96#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.18:45:11.96#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.18:45:11.96$vck44/valo=2,534.99 2006.145.18:45:11.96#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.18:45:11.96#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.18:45:11.96#ibcon#ireg 17 cls_cnt 0 2006.145.18:45:11.96#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.18:45:11.96#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.18:45:11.96#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.18:45:11.99#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.18:45:12.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.18:45:12.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.18:45:12.03#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.18:45:12.03#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.18:45:12.03$vck44/va=2,7 2006.145.18:45:12.03#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.18:45:12.03#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.18:45:12.03#ibcon#ireg 11 cls_cnt 2 2006.145.18:45:12.03#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.18:45:12.08#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.18:45:12.08#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.18:45:12.10#ibcon#[25=AT02-07\r\n] 2006.145.18:45:12.13#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.18:45:12.13#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.18:45:12.13#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.18:45:12.13#ibcon#ireg 7 cls_cnt 0 2006.145.18:45:12.13#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.18:45:12.25#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.18:45:12.25#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.18:45:12.27#ibcon#[25=USB\r\n] 2006.145.18:45:12.30#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.18:45:12.30#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.18:45:12.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.18:45:12.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.18:45:12.30$vck44/valo=3,564.99 2006.145.18:45:12.30#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.18:45:12.30#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.18:45:12.30#ibcon#ireg 17 cls_cnt 0 2006.145.18:45:12.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.18:45:12.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.18:45:12.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.18:45:12.32#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.18:45:12.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.18:45:12.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.18:45:12.36#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.18:45:12.36#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.18:45:12.36$vck44/va=3,8 2006.145.18:45:12.36#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.18:45:12.36#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.18:45:12.36#ibcon#ireg 11 cls_cnt 2 2006.145.18:45:12.36#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.18:45:12.42#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.18:45:12.42#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.18:45:12.44#ibcon#[25=AT03-08\r\n] 2006.145.18:45:12.47#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.18:45:12.47#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.18:45:12.47#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.18:45:12.47#ibcon#ireg 7 cls_cnt 0 2006.145.18:45:12.47#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.18:45:12.59#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.18:45:12.59#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.18:45:12.61#ibcon#[25=USB\r\n] 2006.145.18:45:12.64#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.18:45:12.64#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.18:45:12.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.18:45:12.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.18:45:12.64$vck44/valo=4,624.99 2006.145.18:45:12.64#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.18:45:12.64#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.18:45:12.64#ibcon#ireg 17 cls_cnt 0 2006.145.18:45:12.64#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.18:45:12.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.18:45:12.64#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.18:45:12.66#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.18:45:12.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.18:45:12.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.18:45:12.70#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.18:45:12.70#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.18:45:12.70$vck44/va=4,7 2006.145.18:45:12.70#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.18:45:12.70#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.18:45:12.70#ibcon#ireg 11 cls_cnt 2 2006.145.18:45:12.70#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.18:45:12.76#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.18:45:12.76#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.18:45:12.78#ibcon#[25=AT04-07\r\n] 2006.145.18:45:12.81#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.18:45:12.81#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.18:45:12.81#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.18:45:12.81#ibcon#ireg 7 cls_cnt 0 2006.145.18:45:12.81#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.18:45:12.93#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.18:45:12.93#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.18:45:12.95#ibcon#[25=USB\r\n] 2006.145.18:45:12.98#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.18:45:12.98#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.18:45:12.98#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.18:45:12.98#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.18:45:12.98$vck44/valo=5,734.99 2006.145.18:45:12.98#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.18:45:12.98#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.18:45:12.98#ibcon#ireg 17 cls_cnt 0 2006.145.18:45:12.98#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.18:45:12.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.18:45:12.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.18:45:13.00#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.18:45:13.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.18:45:13.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.18:45:13.04#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.18:45:13.04#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.18:45:13.04$vck44/va=5,4 2006.145.18:45:13.04#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.18:45:13.04#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.18:45:13.04#ibcon#ireg 11 cls_cnt 2 2006.145.18:45:13.04#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.18:45:13.10#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.18:45:13.10#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.18:45:13.12#ibcon#[25=AT05-04\r\n] 2006.145.18:45:13.15#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.18:45:13.15#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.18:45:13.15#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.18:45:13.15#ibcon#ireg 7 cls_cnt 0 2006.145.18:45:13.15#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.18:45:13.27#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.18:45:13.27#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.18:45:13.29#ibcon#[25=USB\r\n] 2006.145.18:45:13.32#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.18:45:13.32#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.18:45:13.32#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.18:45:13.32#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.18:45:13.32$vck44/valo=6,814.99 2006.145.18:45:13.32#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.18:45:13.32#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.18:45:13.32#ibcon#ireg 17 cls_cnt 0 2006.145.18:45:13.32#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.18:45:13.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.18:45:13.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.18:45:13.34#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.18:45:13.38#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.18:45:13.38#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.18:45:13.38#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.18:45:13.38#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.18:45:13.38$vck44/va=6,4 2006.145.18:45:13.38#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.18:45:13.38#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.18:45:13.38#ibcon#ireg 11 cls_cnt 2 2006.145.18:45:13.38#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.18:45:13.44#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.18:45:13.44#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.18:45:13.46#ibcon#[25=AT06-04\r\n] 2006.145.18:45:13.49#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.18:45:13.49#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.18:45:13.49#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.18:45:13.49#ibcon#ireg 7 cls_cnt 0 2006.145.18:45:13.49#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.18:45:13.61#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.18:45:13.61#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.18:45:13.63#ibcon#[25=USB\r\n] 2006.145.18:45:13.66#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.18:45:13.66#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.18:45:13.66#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.18:45:13.66#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.18:45:13.66$vck44/valo=7,864.99 2006.145.18:45:13.66#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.18:45:13.66#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.18:45:13.66#ibcon#ireg 17 cls_cnt 0 2006.145.18:45:13.66#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.18:45:13.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.18:45:13.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.18:45:13.68#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.18:45:13.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.18:45:13.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.18:45:13.72#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.18:45:13.72#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.18:45:13.72$vck44/va=7,4 2006.145.18:45:13.72#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.18:45:13.72#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.18:45:13.72#ibcon#ireg 11 cls_cnt 2 2006.145.18:45:13.72#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.18:45:13.78#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.18:45:13.78#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.18:45:13.80#ibcon#[25=AT07-04\r\n] 2006.145.18:45:13.83#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.18:45:13.83#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.18:45:13.83#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.18:45:13.83#ibcon#ireg 7 cls_cnt 0 2006.145.18:45:13.83#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.18:45:13.95#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.18:45:13.95#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.18:45:13.97#ibcon#[25=USB\r\n] 2006.145.18:45:14.00#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.18:45:14.00#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.18:45:14.00#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.18:45:14.00#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.18:45:14.00$vck44/valo=8,884.99 2006.145.18:45:14.00#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.18:45:14.00#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.18:45:14.00#ibcon#ireg 17 cls_cnt 0 2006.145.18:45:14.00#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.18:45:14.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.18:45:14.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.18:45:14.02#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.18:45:14.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.18:45:14.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.18:45:14.06#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.18:45:14.06#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.18:45:14.06$vck44/va=8,4 2006.145.18:45:14.06#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.18:45:14.06#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.18:45:14.06#ibcon#ireg 11 cls_cnt 2 2006.145.18:45:14.06#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.18:45:14.12#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.18:45:14.12#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.18:45:14.14#ibcon#[25=AT08-04\r\n] 2006.145.18:45:14.19#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.18:45:14.19#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.18:45:14.19#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.18:45:14.19#ibcon#ireg 7 cls_cnt 0 2006.145.18:45:14.19#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.18:45:14.31#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.18:45:14.31#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.18:45:14.33#ibcon#[25=USB\r\n] 2006.145.18:45:14.36#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.18:45:14.36#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.18:45:14.36#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.18:45:14.36#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.18:45:14.36$vck44/vblo=1,629.99 2006.145.18:45:14.36#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.18:45:14.36#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.18:45:14.36#ibcon#ireg 17 cls_cnt 0 2006.145.18:45:14.36#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.18:45:14.36#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.18:45:14.36#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.18:45:14.38#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.18:45:14.42#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.18:45:14.42#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.18:45:14.42#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.18:45:14.42#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.18:45:14.42$vck44/vb=1,3 2006.145.18:45:14.42#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.18:45:14.42#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.18:45:14.42#ibcon#ireg 11 cls_cnt 2 2006.145.18:45:14.42#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.18:45:14.42#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.18:45:14.42#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.18:45:14.44#ibcon#[27=AT01-03\r\n] 2006.145.18:45:14.47#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.18:45:14.47#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.18:45:14.47#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.18:45:14.47#ibcon#ireg 7 cls_cnt 0 2006.145.18:45:14.47#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.18:45:14.59#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.18:45:14.59#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.18:45:14.61#ibcon#[27=USB\r\n] 2006.145.18:45:14.64#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.18:45:14.64#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.18:45:14.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.18:45:14.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.18:45:14.64$vck44/vblo=2,634.99 2006.145.18:45:14.64#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.18:45:14.64#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.18:45:14.64#ibcon#ireg 17 cls_cnt 0 2006.145.18:45:14.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.18:45:14.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.18:45:14.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.18:45:14.66#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.18:45:14.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.18:45:14.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.18:45:14.70#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.18:45:14.70#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.18:45:14.70$vck44/vb=2,4 2006.145.18:45:14.70#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.18:45:14.70#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.18:45:14.70#ibcon#ireg 11 cls_cnt 2 2006.145.18:45:14.70#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.18:45:14.76#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.18:45:14.76#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.18:45:14.78#ibcon#[27=AT02-04\r\n] 2006.145.18:45:14.81#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.18:45:14.81#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.18:45:14.81#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.18:45:14.81#ibcon#ireg 7 cls_cnt 0 2006.145.18:45:14.81#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.18:45:14.93#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.18:45:14.93#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.18:45:14.95#ibcon#[27=USB\r\n] 2006.145.18:45:14.98#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.18:45:14.98#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.18:45:14.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.18:45:14.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.18:45:14.98$vck44/vblo=3,649.99 2006.145.18:45:14.98#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.18:45:14.98#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.18:45:14.98#ibcon#ireg 17 cls_cnt 0 2006.145.18:45:14.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.18:45:14.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.18:45:14.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.18:45:15.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.18:45:15.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.18:45:15.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.18:45:15.04#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.18:45:15.04#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.18:45:15.04$vck44/vb=3,4 2006.145.18:45:15.04#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.18:45:15.04#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.18:45:15.04#ibcon#ireg 11 cls_cnt 2 2006.145.18:45:15.04#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.18:45:15.10#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.18:45:15.10#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.18:45:15.12#ibcon#[27=AT03-04\r\n] 2006.145.18:45:15.15#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.18:45:15.15#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.18:45:15.15#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.18:45:15.15#ibcon#ireg 7 cls_cnt 0 2006.145.18:45:15.15#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.18:45:15.27#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.18:45:15.27#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.18:45:15.29#ibcon#[27=USB\r\n] 2006.145.18:45:15.32#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.18:45:15.32#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.18:45:15.32#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.18:45:15.32#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.18:45:15.32$vck44/vblo=4,679.99 2006.145.18:45:15.32#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.18:45:15.32#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.18:45:15.32#ibcon#ireg 17 cls_cnt 0 2006.145.18:45:15.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.18:45:15.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.18:45:15.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.18:45:15.34#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.18:45:15.38#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.18:45:15.38#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.18:45:15.38#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.18:45:15.38#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.18:45:15.38$vck44/vb=4,4 2006.145.18:45:15.38#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.18:45:15.38#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.18:45:15.38#ibcon#ireg 11 cls_cnt 2 2006.145.18:45:15.38#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.18:45:15.44#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.18:45:15.44#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.18:45:15.46#ibcon#[27=AT04-04\r\n] 2006.145.18:45:15.49#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.18:45:15.49#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.18:45:15.49#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.18:45:15.49#ibcon#ireg 7 cls_cnt 0 2006.145.18:45:15.49#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.18:45:15.61#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.18:45:15.61#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.18:45:15.63#ibcon#[27=USB\r\n] 2006.145.18:45:15.66#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.18:45:15.66#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.18:45:15.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.18:45:15.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.18:45:15.66$vck44/vblo=5,709.99 2006.145.18:45:15.66#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.18:45:15.66#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.18:45:15.66#ibcon#ireg 17 cls_cnt 0 2006.145.18:45:15.66#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.18:45:15.66#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.18:45:15.66#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.18:45:15.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.18:45:15.72#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.18:45:15.72#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.18:45:15.72#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.18:45:15.72#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.18:45:15.72$vck44/vb=5,4 2006.145.18:45:15.72#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.18:45:15.72#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.18:45:15.72#ibcon#ireg 11 cls_cnt 2 2006.145.18:45:15.72#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.18:45:15.78#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.18:45:15.78#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.18:45:15.80#ibcon#[27=AT05-04\r\n] 2006.145.18:45:15.83#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.18:45:15.83#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.18:45:15.83#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.18:45:15.83#ibcon#ireg 7 cls_cnt 0 2006.145.18:45:15.83#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.18:45:15.95#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.18:45:15.95#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.18:45:15.97#ibcon#[27=USB\r\n] 2006.145.18:45:16.00#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.18:45:16.00#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.18:45:16.00#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.18:45:16.00#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.18:45:16.00$vck44/vblo=6,719.99 2006.145.18:45:16.00#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.18:45:16.00#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.18:45:16.00#ibcon#ireg 17 cls_cnt 0 2006.145.18:45:16.00#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.18:45:16.00#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.18:45:16.00#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.18:45:16.02#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.18:45:16.06#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.18:45:16.06#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.18:45:16.06#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.18:45:16.06#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.18:45:16.06$vck44/vb=6,4 2006.145.18:45:16.06#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.18:45:16.06#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.18:45:16.06#ibcon#ireg 11 cls_cnt 2 2006.145.18:45:16.06#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.18:45:16.12#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.18:45:16.12#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.18:45:16.14#ibcon#[27=AT06-04\r\n] 2006.145.18:45:16.17#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.18:45:16.17#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.18:45:16.17#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.18:45:16.17#ibcon#ireg 7 cls_cnt 0 2006.145.18:45:16.17#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.18:45:16.29#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.18:45:16.29#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.18:45:16.31#ibcon#[27=USB\r\n] 2006.145.18:45:16.34#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.18:45:16.34#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.18:45:16.34#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.18:45:16.34#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.18:45:16.34$vck44/vblo=7,734.99 2006.145.18:45:16.34#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.18:45:16.34#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.18:45:16.34#ibcon#ireg 17 cls_cnt 0 2006.145.18:45:16.34#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.18:45:16.34#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.18:45:16.34#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.18:45:16.36#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.18:45:16.40#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.18:45:16.40#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.18:45:16.40#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.18:45:16.40#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.18:45:16.40$vck44/vb=7,4 2006.145.18:45:16.40#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.18:45:16.40#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.18:45:16.40#ibcon#ireg 11 cls_cnt 2 2006.145.18:45:16.40#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.18:45:16.46#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.18:45:16.46#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.18:45:16.48#ibcon#[27=AT07-04\r\n] 2006.145.18:45:16.51#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.18:45:16.51#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.18:45:16.51#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.18:45:16.51#ibcon#ireg 7 cls_cnt 0 2006.145.18:45:16.51#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.18:45:16.63#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.18:45:16.63#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.18:45:16.65#ibcon#[27=USB\r\n] 2006.145.18:45:16.68#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.18:45:16.68#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.18:45:16.68#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.18:45:16.68#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.18:45:16.68$vck44/vblo=8,744.99 2006.145.18:45:16.68#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.18:45:16.68#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.18:45:16.68#ibcon#ireg 17 cls_cnt 0 2006.145.18:45:16.68#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.18:45:16.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.18:45:16.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.18:45:16.70#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.18:45:16.74#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.18:45:16.74#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.18:45:16.74#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.18:45:16.74#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.18:45:16.74$vck44/vb=8,4 2006.145.18:45:16.74#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.18:45:16.74#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.18:45:16.74#ibcon#ireg 11 cls_cnt 2 2006.145.18:45:16.74#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.18:45:16.80#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.18:45:16.80#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.18:45:16.82#ibcon#[27=AT08-04\r\n] 2006.145.18:45:16.85#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.18:45:16.85#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.18:45:16.85#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.18:45:16.85#ibcon#ireg 7 cls_cnt 0 2006.145.18:45:16.85#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.18:45:16.97#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.18:45:16.97#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.18:45:16.99#ibcon#[27=USB\r\n] 2006.145.18:45:17.02#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.18:45:17.02#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.18:45:17.02#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.18:45:17.02#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.18:45:17.02$vck44/vabw=wide 2006.145.18:45:17.02#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.18:45:17.02#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.18:45:17.02#ibcon#ireg 8 cls_cnt 0 2006.145.18:45:17.02#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.18:45:17.02#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.18:45:17.02#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.18:45:17.04#ibcon#[25=BW32\r\n] 2006.145.18:45:17.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.18:45:17.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.18:45:17.07#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.18:45:17.07#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.18:45:17.07$vck44/vbbw=wide 2006.145.18:45:17.07#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.18:45:17.07#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.18:45:17.07#ibcon#ireg 8 cls_cnt 0 2006.145.18:45:17.07#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:45:17.14#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:45:17.14#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:45:17.16#ibcon#[27=BW32\r\n] 2006.145.18:45:17.19#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:45:17.19#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:45:17.19#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.18:45:17.19#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.18:45:17.19$setupk4/ifdk4 2006.145.18:45:17.19$ifdk4/lo= 2006.145.18:45:17.19$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.18:45:17.19$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.18:45:17.19$ifdk4/patch= 2006.145.18:45:17.19$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.18:45:17.19$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.18:45:17.19$setupk4/!*+20s 2006.145.18:45:18.49#abcon#<5=/06 1.7 2.6 15.69 871019.8\r\n> 2006.145.18:45:18.51#abcon#{5=INTERFACE CLEAR} 2006.145.18:45:18.57#abcon#[5=S1D000X0/0*\r\n] 2006.145.18:45:28.14#trakl#Source acquired 2006.145.18:45:28.14#flagr#flagr/antenna,acquired 2006.145.18:45:28.66#abcon#<5=/06 1.7 2.6 15.69 871019.8\r\n> 2006.145.18:45:28.68#abcon#{5=INTERFACE CLEAR} 2006.145.18:45:28.74#abcon#[5=S1D000X0/0*\r\n] 2006.145.18:45:31.66$setupk4/"tpicd 2006.145.18:45:31.66$setupk4/echo=off 2006.145.18:45:31.66$setupk4/xlog=off 2006.145.18:45:31.66:!2006.145.18:45:30 2006.145.18:45:31.66:preob 2006.145.18:45:32.14/onsource/TRACKING 2006.145.18:45:32.14:!2006.145.18:45:40 2006.145.18:45:40.00:"tape 2006.145.18:45:40.00:"st=record 2006.145.18:45:40.00:data_valid=on 2006.145.18:45:40.00:midob 2006.145.18:45:40.14/onsource/TRACKING 2006.145.18:45:40.14/wx/15.69,1019.8,87 2006.145.18:45:40.21/cable/+6.5520E-03 2006.145.18:45:41.30/va/01,08,usb,yes,50,53 2006.145.18:45:41.30/va/02,07,usb,yes,53,54 2006.145.18:45:41.30/va/03,08,usb,yes,49,51 2006.145.18:45:41.30/va/04,07,usb,yes,55,58 2006.145.18:45:41.30/va/05,04,usb,yes,49,50 2006.145.18:45:41.30/va/06,04,usb,yes,54,54 2006.145.18:45:41.30/va/07,04,usb,yes,55,56 2006.145.18:45:41.30/va/08,04,usb,yes,48,56 2006.145.18:45:41.53/valo/01,524.99,yes,locked 2006.145.18:45:41.53/valo/02,534.99,yes,locked 2006.145.18:45:41.53/valo/03,564.99,yes,locked 2006.145.18:45:41.53/valo/04,624.99,yes,locked 2006.145.18:45:41.53/valo/05,734.99,yes,locked 2006.145.18:45:41.53/valo/06,814.99,yes,locked 2006.145.18:45:41.53/valo/07,864.99,yes,locked 2006.145.18:45:41.53/valo/08,884.99,yes,locked 2006.145.18:45:42.62/vb/01,03,usb,yes,51,47 2006.145.18:45:42.62/vb/02,04,usb,yes,45,44 2006.145.18:45:42.62/vb/03,04,usb,yes,41,45 2006.145.18:45:42.62/vb/04,04,usb,yes,46,45 2006.145.18:45:42.62/vb/05,04,usb,yes,37,40 2006.145.18:45:42.62/vb/06,04,usb,yes,43,38 2006.145.18:45:42.62/vb/07,04,usb,yes,43,43 2006.145.18:45:42.62/vb/08,04,usb,yes,39,44 2006.145.18:45:42.85/vblo/01,629.99,yes,locked 2006.145.18:45:42.85/vblo/02,634.99,yes,locked 2006.145.18:45:42.85/vblo/03,649.99,yes,locked 2006.145.18:45:42.85/vblo/04,679.99,yes,locked 2006.145.18:45:42.85/vblo/05,709.99,yes,locked 2006.145.18:45:42.85/vblo/06,719.99,yes,locked 2006.145.18:45:42.85/vblo/07,734.99,yes,locked 2006.145.18:45:42.85/vblo/08,744.99,yes,locked 2006.145.18:45:43.00/vabw/8 2006.145.18:45:43.15/vbbw/8 2006.145.18:45:43.24/xfe/off,on,14.5 2006.145.18:45:43.62/ifatt/23,28,28,28 2006.145.18:45:44.07/fmout-gps/S +5.1E-08 2006.145.18:45:44.11:!2006.145.18:46:50 2006.145.18:46:50.00:data_valid=off 2006.145.18:46:50.00:"et 2006.145.18:46:50.00:!+3s 2006.145.18:46:53.02:"tape 2006.145.18:46:53.02:postob 2006.145.18:46:53.14/cable/+6.5518E-03 2006.145.18:46:53.14/wx/15.70,1019.8,87 2006.145.18:46:54.08/fmout-gps/S +5.2E-08 2006.145.18:46:54.08:scan_name=145-1847,jd0605,440 2006.145.18:46:54.08:source=1418+546,141946.60,542314.8,2000.0,ccw 2006.145.18:46:55.14#flagr#flagr/antenna,new-source 2006.145.18:46:55.14:checkk5 2006.145.18:46:55.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.18:46:56.04/chk_autoobs//k5ts2/ autoobs is running! 2006.145.18:46:56.48/chk_autoobs//k5ts3/ autoobs is running! 2006.145.18:46:56.91/chk_autoobs//k5ts4/ autoobs is running! 2006.145.18:46:57.34/chk_obsdata//k5ts1/T1451845??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.18:46:57.78/chk_obsdata//k5ts2/T1451845??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.18:46:58.22/chk_obsdata//k5ts3/T1451845??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.18:46:58.64/chk_obsdata//k5ts4/T1451845??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.18:46:59.40/k5log//k5ts1_log_newline 2006.145.18:47:00.14/k5log//k5ts2_log_newline 2006.145.18:47:00.90/k5log//k5ts3_log_newline 2006.145.18:47:01.64/k5log//k5ts4_log_newline 2006.145.18:47:01.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.18:47:01.67:setupk4=1 2006.145.18:47:01.67$setupk4/echo=on 2006.145.18:47:01.67$setupk4/pcalon 2006.145.18:47:01.67$pcalon/"no phase cal control is implemented here 2006.145.18:47:01.67$setupk4/"tpicd=stop 2006.145.18:47:01.67$setupk4/"rec=synch_on 2006.145.18:47:01.67$setupk4/"rec_mode=128 2006.145.18:47:01.67$setupk4/!* 2006.145.18:47:01.67$setupk4/recpk4 2006.145.18:47:01.67$recpk4/recpatch= 2006.145.18:47:01.67$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.18:47:01.67$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.18:47:01.67$setupk4/vck44 2006.145.18:47:01.67$vck44/valo=1,524.99 2006.145.18:47:01.67#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.18:47:01.67#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.18:47:01.67#ibcon#ireg 17 cls_cnt 0 2006.145.18:47:01.67#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:47:01.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:47:01.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:47:01.71#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.18:47:01.76#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:47:01.76#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:47:01.76#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.18:47:01.76#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.18:47:01.76$vck44/va=1,8 2006.145.18:47:01.76#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.18:47:01.76#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.18:47:01.76#ibcon#ireg 11 cls_cnt 2 2006.145.18:47:01.76#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:47:01.76#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:47:01.76#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:47:01.78#ibcon#[25=AT01-08\r\n] 2006.145.18:47:01.81#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:47:01.81#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:47:01.81#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.18:47:01.81#ibcon#ireg 7 cls_cnt 0 2006.145.18:47:01.81#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:47:01.93#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:47:01.93#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:47:01.95#ibcon#[25=USB\r\n] 2006.145.18:47:01.98#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:47:01.98#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:47:01.98#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.18:47:01.98#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.18:47:01.98$vck44/valo=2,534.99 2006.145.18:47:01.98#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.18:47:01.98#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.18:47:01.98#ibcon#ireg 17 cls_cnt 0 2006.145.18:47:01.98#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:47:01.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:47:01.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:47:02.00#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.18:47:02.04#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:47:02.04#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:47:02.04#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.18:47:02.04#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.18:47:02.04$vck44/va=2,7 2006.145.18:47:02.04#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.18:47:02.04#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.18:47:02.04#ibcon#ireg 11 cls_cnt 2 2006.145.18:47:02.04#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:47:02.10#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:47:02.10#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:47:02.12#ibcon#[25=AT02-07\r\n] 2006.145.18:47:02.15#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:47:02.15#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:47:02.15#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.18:47:02.15#ibcon#ireg 7 cls_cnt 0 2006.145.18:47:02.15#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:47:02.27#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:47:02.27#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:47:02.29#ibcon#[25=USB\r\n] 2006.145.18:47:02.32#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:47:02.32#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:47:02.32#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.18:47:02.32#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.18:47:02.32$vck44/valo=3,564.99 2006.145.18:47:02.32#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.18:47:02.32#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.18:47:02.32#ibcon#ireg 17 cls_cnt 0 2006.145.18:47:02.32#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.18:47:02.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.18:47:02.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.18:47:02.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.18:47:02.38#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.18:47:02.38#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.18:47:02.38#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.18:47:02.38#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.18:47:02.38$vck44/va=3,8 2006.145.18:47:02.38#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.18:47:02.38#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.18:47:02.38#ibcon#ireg 11 cls_cnt 2 2006.145.18:47:02.38#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.18:47:02.44#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.18:47:02.44#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.18:47:02.46#ibcon#[25=AT03-08\r\n] 2006.145.18:47:02.49#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.18:47:02.49#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.18:47:02.49#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.18:47:02.49#ibcon#ireg 7 cls_cnt 0 2006.145.18:47:02.49#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.18:47:02.61#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.18:47:02.61#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.18:47:02.63#ibcon#[25=USB\r\n] 2006.145.18:47:02.66#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.18:47:02.66#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.18:47:02.66#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.18:47:02.66#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.18:47:02.66$vck44/valo=4,624.99 2006.145.18:47:02.66#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.18:47:02.66#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.18:47:02.66#ibcon#ireg 17 cls_cnt 0 2006.145.18:47:02.66#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.18:47:02.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.18:47:02.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.18:47:02.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.18:47:02.72#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.18:47:02.72#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.18:47:02.72#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.18:47:02.72#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.18:47:02.72$vck44/va=4,7 2006.145.18:47:02.72#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.18:47:02.72#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.18:47:02.72#ibcon#ireg 11 cls_cnt 2 2006.145.18:47:02.72#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.18:47:02.78#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.18:47:02.78#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.18:47:02.80#ibcon#[25=AT04-07\r\n] 2006.145.18:47:02.85#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.18:47:02.85#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.18:47:02.85#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.18:47:02.85#ibcon#ireg 7 cls_cnt 0 2006.145.18:47:02.85#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.18:47:02.97#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.18:47:02.97#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.18:47:02.99#ibcon#[25=USB\r\n] 2006.145.18:47:03.04#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.18:47:03.04#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.18:47:03.04#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.18:47:03.04#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.18:47:03.04$vck44/valo=5,734.99 2006.145.18:47:03.04#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.18:47:03.04#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.18:47:03.04#ibcon#ireg 17 cls_cnt 0 2006.145.18:47:03.04#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:47:03.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:47:03.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:47:03.05#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.18:47:03.09#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:47:03.09#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:47:03.09#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.18:47:03.09#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.18:47:03.09$vck44/va=5,4 2006.145.18:47:03.09#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.18:47:03.09#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.18:47:03.09#ibcon#ireg 11 cls_cnt 2 2006.145.18:47:03.09#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:47:03.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:47:03.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:47:03.18#ibcon#[25=AT05-04\r\n] 2006.145.18:47:03.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:47:03.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:47:03.21#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.18:47:03.21#ibcon#ireg 7 cls_cnt 0 2006.145.18:47:03.21#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:47:03.33#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:47:03.33#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:47:03.35#ibcon#[25=USB\r\n] 2006.145.18:47:03.38#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:47:03.38#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:47:03.38#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.18:47:03.38#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.18:47:03.38$vck44/valo=6,814.99 2006.145.18:47:03.38#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.18:47:03.38#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.18:47:03.38#ibcon#ireg 17 cls_cnt 0 2006.145.18:47:03.38#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.18:47:03.38#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.18:47:03.38#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.18:47:03.40#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.18:47:03.44#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.18:47:03.44#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.18:47:03.44#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.18:47:03.44#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.18:47:03.44$vck44/va=6,4 2006.145.18:47:03.44#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.18:47:03.44#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.18:47:03.44#ibcon#ireg 11 cls_cnt 2 2006.145.18:47:03.44#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.18:47:03.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.18:47:03.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.18:47:03.52#ibcon#[25=AT06-04\r\n] 2006.145.18:47:03.55#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.18:47:03.55#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.18:47:03.55#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.18:47:03.55#ibcon#ireg 7 cls_cnt 0 2006.145.18:47:03.55#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.18:47:03.67#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.18:47:03.67#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.18:47:03.69#ibcon#[25=USB\r\n] 2006.145.18:47:03.72#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.18:47:03.72#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.18:47:03.72#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.18:47:03.72#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.18:47:03.72$vck44/valo=7,864.99 2006.145.18:47:03.72#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.18:47:03.72#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.18:47:03.72#ibcon#ireg 17 cls_cnt 0 2006.145.18:47:03.72#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:47:03.72#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:47:03.72#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:47:03.74#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.18:47:03.78#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:47:03.78#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:47:03.78#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.18:47:03.78#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.18:47:03.78$vck44/va=7,4 2006.145.18:47:03.78#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.18:47:03.78#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.18:47:03.78#ibcon#ireg 11 cls_cnt 2 2006.145.18:47:03.78#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:47:03.84#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:47:03.84#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:47:03.86#ibcon#[25=AT07-04\r\n] 2006.145.18:47:03.89#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:47:03.89#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:47:03.89#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.18:47:03.89#ibcon#ireg 7 cls_cnt 0 2006.145.18:47:03.89#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:47:04.01#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:47:04.01#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:47:04.03#ibcon#[25=USB\r\n] 2006.145.18:47:04.06#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:47:04.06#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:47:04.06#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.18:47:04.06#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.18:47:04.06$vck44/valo=8,884.99 2006.145.18:47:04.06#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.18:47:04.06#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.18:47:04.06#ibcon#ireg 17 cls_cnt 0 2006.145.18:47:04.06#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:47:04.06#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:47:04.06#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:47:04.08#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.18:47:04.12#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:47:04.12#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:47:04.12#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.18:47:04.12#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.18:47:04.12$vck44/va=8,4 2006.145.18:47:04.12#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.18:47:04.12#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.18:47:04.12#ibcon#ireg 11 cls_cnt 2 2006.145.18:47:04.12#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:47:04.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:47:04.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:47:04.20#ibcon#[25=AT08-04\r\n] 2006.145.18:47:04.23#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:47:04.23#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.18:47:04.23#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.18:47:04.23#ibcon#ireg 7 cls_cnt 0 2006.145.18:47:04.23#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:47:04.35#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:47:04.35#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:47:04.37#ibcon#[25=USB\r\n] 2006.145.18:47:04.40#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:47:04.40#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.18:47:04.40#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.18:47:04.40#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.18:47:04.40$vck44/vblo=1,629.99 2006.145.18:47:04.40#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.18:47:04.40#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.18:47:04.40#ibcon#ireg 17 cls_cnt 0 2006.145.18:47:04.40#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.18:47:04.40#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.18:47:04.40#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.18:47:04.42#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.18:47:04.46#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.18:47:04.46#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.18:47:04.46#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.18:47:04.46#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.18:47:04.46$vck44/vb=1,3 2006.145.18:47:04.46#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.18:47:04.46#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.18:47:04.46#ibcon#ireg 11 cls_cnt 2 2006.145.18:47:04.46#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.18:47:04.46#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.18:47:04.46#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.18:47:04.48#ibcon#[27=AT01-03\r\n] 2006.145.18:47:04.51#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.18:47:04.51#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.18:47:04.51#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.18:47:04.51#ibcon#ireg 7 cls_cnt 0 2006.145.18:47:04.51#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.18:47:04.63#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.18:47:04.63#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.18:47:04.65#ibcon#[27=USB\r\n] 2006.145.18:47:04.68#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.18:47:04.68#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.18:47:04.68#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.18:47:04.68#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.18:47:04.68$vck44/vblo=2,634.99 2006.145.18:47:04.68#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.18:47:04.68#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.18:47:04.68#ibcon#ireg 17 cls_cnt 0 2006.145.18:47:04.68#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:47:04.68#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:47:04.68#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:47:04.70#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.18:47:04.74#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:47:04.74#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.18:47:04.74#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.18:47:04.74#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.18:47:04.74$vck44/vb=2,4 2006.145.18:47:04.74#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.18:47:04.74#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.18:47:04.74#ibcon#ireg 11 cls_cnt 2 2006.145.18:47:04.74#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:47:04.80#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:47:04.80#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:47:04.82#ibcon#[27=AT02-04\r\n] 2006.145.18:47:04.85#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:47:04.85#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.18:47:04.85#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.18:47:04.85#ibcon#ireg 7 cls_cnt 0 2006.145.18:47:04.85#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:47:04.97#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:47:04.97#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:47:04.99#ibcon#[27=USB\r\n] 2006.145.18:47:05.02#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:47:05.02#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.18:47:05.02#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.18:47:05.02#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.18:47:05.02$vck44/vblo=3,649.99 2006.145.18:47:05.02#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.18:47:05.02#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.18:47:05.02#ibcon#ireg 17 cls_cnt 0 2006.145.18:47:05.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:47:05.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:47:05.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:47:05.04#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.18:47:05.08#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:47:05.08#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.18:47:05.08#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.18:47:05.08#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.18:47:05.08$vck44/vb=3,4 2006.145.18:47:05.08#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.18:47:05.08#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.18:47:05.08#ibcon#ireg 11 cls_cnt 2 2006.145.18:47:05.08#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:47:05.14#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:47:05.14#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:47:05.16#ibcon#[27=AT03-04\r\n] 2006.145.18:47:05.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:47:05.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.18:47:05.19#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.18:47:05.19#ibcon#ireg 7 cls_cnt 0 2006.145.18:47:05.19#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:47:05.31#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:47:05.31#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:47:05.33#ibcon#[27=USB\r\n] 2006.145.18:47:05.36#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:47:05.36#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.18:47:05.36#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.18:47:05.36#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.18:47:05.36$vck44/vblo=4,679.99 2006.145.18:47:05.36#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.18:47:05.36#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.18:47:05.36#ibcon#ireg 17 cls_cnt 0 2006.145.18:47:05.36#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.18:47:05.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.18:47:05.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.18:47:05.38#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.18:47:05.42#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.18:47:05.42#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.18:47:05.42#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.18:47:05.42#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.18:47:05.42$vck44/vb=4,4 2006.145.18:47:05.42#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.18:47:05.42#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.18:47:05.42#ibcon#ireg 11 cls_cnt 2 2006.145.18:47:05.42#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.18:47:05.48#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.18:47:05.48#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.18:47:05.50#ibcon#[27=AT04-04\r\n] 2006.145.18:47:05.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.18:47:05.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.18:47:05.53#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.18:47:05.53#ibcon#ireg 7 cls_cnt 0 2006.145.18:47:05.53#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.18:47:05.65#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.18:47:05.65#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.18:47:05.67#ibcon#[27=USB\r\n] 2006.145.18:47:05.70#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.18:47:05.70#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.18:47:05.70#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.18:47:05.70#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.18:47:05.70$vck44/vblo=5,709.99 2006.145.18:47:05.70#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.18:47:05.70#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.18:47:05.70#ibcon#ireg 17 cls_cnt 0 2006.145.18:47:05.70#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.18:47:05.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.18:47:05.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.18:47:05.72#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.18:47:05.76#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.18:47:05.76#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.18:47:05.76#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.18:47:05.76#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.18:47:05.76$vck44/vb=5,4 2006.145.18:47:05.76#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.18:47:05.76#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.18:47:05.76#ibcon#ireg 11 cls_cnt 2 2006.145.18:47:05.76#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.18:47:05.82#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.18:47:05.82#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.18:47:05.84#ibcon#[27=AT05-04\r\n] 2006.145.18:47:05.87#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.18:47:05.87#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.18:47:05.87#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.18:47:05.87#ibcon#ireg 7 cls_cnt 0 2006.145.18:47:05.87#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.18:47:05.99#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.18:47:05.99#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.18:47:06.01#ibcon#[27=USB\r\n] 2006.145.18:47:06.04#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.18:47:06.04#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.18:47:06.04#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.18:47:06.04#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.18:47:06.04$vck44/vblo=6,719.99 2006.145.18:47:06.04#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.18:47:06.04#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.18:47:06.04#ibcon#ireg 17 cls_cnt 0 2006.145.18:47:06.04#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:47:06.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:47:06.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:47:06.06#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.18:47:06.10#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:47:06.10#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.18:47:06.10#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.18:47:06.10#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.18:47:06.10$vck44/vb=6,4 2006.145.18:47:06.10#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.18:47:06.10#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.18:47:06.10#ibcon#ireg 11 cls_cnt 2 2006.145.18:47:06.10#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:47:06.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:47:06.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:47:06.18#ibcon#[27=AT06-04\r\n] 2006.145.18:47:06.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:47:06.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.18:47:06.21#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.18:47:06.21#ibcon#ireg 7 cls_cnt 0 2006.145.18:47:06.21#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:47:06.33#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:47:06.33#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:47:06.35#ibcon#[27=USB\r\n] 2006.145.18:47:06.38#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:47:06.38#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.18:47:06.38#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.18:47:06.38#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.18:47:06.38$vck44/vblo=7,734.99 2006.145.18:47:06.38#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.18:47:06.38#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.18:47:06.38#ibcon#ireg 17 cls_cnt 0 2006.145.18:47:06.38#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.18:47:06.38#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.18:47:06.38#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.18:47:06.40#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.18:47:06.44#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.18:47:06.44#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.18:47:06.44#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.18:47:06.44#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.18:47:06.44$vck44/vb=7,4 2006.145.18:47:06.44#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.18:47:06.44#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.18:47:06.44#ibcon#ireg 11 cls_cnt 2 2006.145.18:47:06.44#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.18:47:06.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.18:47:06.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.18:47:06.52#ibcon#[27=AT07-04\r\n] 2006.145.18:47:06.55#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.18:47:06.55#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.18:47:06.55#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.18:47:06.55#ibcon#ireg 7 cls_cnt 0 2006.145.18:47:06.55#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.18:47:06.67#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.18:47:06.67#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.18:47:06.69#ibcon#[27=USB\r\n] 2006.145.18:47:06.72#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.18:47:06.72#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.18:47:06.72#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.18:47:06.72#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.18:47:06.72$vck44/vblo=8,744.99 2006.145.18:47:06.72#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.18:47:06.72#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.18:47:06.72#ibcon#ireg 17 cls_cnt 0 2006.145.18:47:06.72#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:47:06.72#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:47:06.72#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:47:06.74#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.18:47:06.78#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:47:06.78#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.18:47:06.78#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.18:47:06.78#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.18:47:06.78$vck44/vb=8,4 2006.145.18:47:06.78#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.18:47:06.78#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.18:47:06.78#ibcon#ireg 11 cls_cnt 2 2006.145.18:47:06.78#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:47:06.84#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:47:06.84#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:47:06.86#ibcon#[27=AT08-04\r\n] 2006.145.18:47:06.89#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:47:06.89#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.18:47:06.89#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.18:47:06.89#ibcon#ireg 7 cls_cnt 0 2006.145.18:47:06.89#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:47:07.01#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:47:07.01#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:47:07.03#ibcon#[27=USB\r\n] 2006.145.18:47:07.06#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:47:07.06#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.18:47:07.06#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.18:47:07.06#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.18:47:07.06$vck44/vabw=wide 2006.145.18:47:07.06#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.18:47:07.06#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.18:47:07.06#ibcon#ireg 8 cls_cnt 0 2006.145.18:47:07.06#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:47:07.06#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:47:07.06#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:47:07.08#ibcon#[25=BW32\r\n] 2006.145.18:47:07.11#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:47:07.11#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.18:47:07.11#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.18:47:07.11#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.18:47:07.11$vck44/vbbw=wide 2006.145.18:47:07.11#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.18:47:07.11#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.18:47:07.11#ibcon#ireg 8 cls_cnt 0 2006.145.18:47:07.11#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.18:47:07.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.18:47:07.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.18:47:07.20#ibcon#[27=BW32\r\n] 2006.145.18:47:07.23#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.18:47:07.23#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.18:47:07.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.18:47:07.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.18:47:07.23$setupk4/ifdk4 2006.145.18:47:07.23$ifdk4/lo= 2006.145.18:47:07.23$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.18:47:07.23$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.18:47:07.23$ifdk4/patch= 2006.145.18:47:07.23$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.18:47:07.23$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.18:47:07.23$setupk4/!*+20s 2006.145.18:47:10.47#abcon#<5=/06 1.7 2.6 15.71 861019.8\r\n> 2006.145.18:47:10.49#abcon#{5=INTERFACE CLEAR} 2006.145.18:47:10.55#abcon#[5=S1D000X0/0*\r\n] 2006.145.18:47:13.14#trakl#Source acquired 2006.145.18:47:15.14#flagr#flagr/antenna,acquired 2006.145.18:47:20.64#abcon#<5=/06 1.7 2.6 15.71 861019.8\r\n> 2006.145.18:47:20.66#abcon#{5=INTERFACE CLEAR} 2006.145.18:47:20.72#abcon#[5=S1D000X0/0*\r\n] 2006.145.18:47:21.68$setupk4/"tpicd 2006.145.18:47:21.68$setupk4/echo=off 2006.145.18:47:21.68$setupk4/xlog=off 2006.145.18:47:21.68:!2006.145.18:47:16 2006.145.18:47:21.68:preob 2006.145.18:47:22.14/onsource/TRACKING 2006.145.18:47:22.14:!2006.145.18:47:26 2006.145.18:47:26.00:"tape 2006.145.18:47:26.00:"st=record 2006.145.18:47:26.00:data_valid=on 2006.145.18:47:26.00:midob 2006.145.18:47:27.14/onsource/TRACKING 2006.145.18:47:27.14/wx/15.71,1019.8,86 2006.145.18:47:27.34/cable/+6.5523E-03 2006.145.18:47:28.43/va/01,08,usb,yes,29,31 2006.145.18:47:28.43/va/02,07,usb,yes,31,32 2006.145.18:47:28.43/va/03,08,usb,yes,28,30 2006.145.18:47:28.43/va/04,07,usb,yes,32,34 2006.145.18:47:28.43/va/05,04,usb,yes,28,29 2006.145.18:47:28.43/va/06,04,usb,yes,31,31 2006.145.18:47:28.43/va/07,04,usb,yes,32,33 2006.145.18:47:28.43/va/08,04,usb,yes,27,33 2006.145.18:47:28.66/valo/01,524.99,yes,locked 2006.145.18:47:28.66/valo/02,534.99,yes,locked 2006.145.18:47:28.66/valo/03,564.99,yes,locked 2006.145.18:47:28.66/valo/04,624.99,yes,locked 2006.145.18:47:28.66/valo/05,734.99,yes,locked 2006.145.18:47:28.66/valo/06,814.99,yes,locked 2006.145.18:47:28.66/valo/07,864.99,yes,locked 2006.145.18:47:28.66/valo/08,884.99,yes,locked 2006.145.18:47:29.75/vb/01,03,usb,yes,36,34 2006.145.18:47:29.75/vb/02,04,usb,yes,32,31 2006.145.18:47:29.75/vb/03,04,usb,yes,29,31 2006.145.18:47:29.75/vb/04,04,usb,yes,33,32 2006.145.18:47:29.75/vb/05,04,usb,yes,25,28 2006.145.18:47:29.75/vb/06,04,usb,yes,30,26 2006.145.18:47:29.75/vb/07,04,usb,yes,30,29 2006.145.18:47:29.75/vb/08,04,usb,yes,27,31 2006.145.18:47:29.98/vblo/01,629.99,yes,locked 2006.145.18:47:29.98/vblo/02,634.99,yes,locked 2006.145.18:47:29.98/vblo/03,649.99,yes,locked 2006.145.18:47:29.98/vblo/04,679.99,yes,locked 2006.145.18:47:29.98/vblo/05,709.99,yes,locked 2006.145.18:47:29.98/vblo/06,719.99,yes,locked 2006.145.18:47:29.98/vblo/07,734.99,yes,locked 2006.145.18:47:29.98/vblo/08,744.99,yes,locked 2006.145.18:47:30.13/vabw/8 2006.145.18:47:30.28/vbbw/8 2006.145.18:47:30.37/xfe/off,on,15.0 2006.145.18:47:30.74/ifatt/23,28,28,28 2006.145.18:47:31.08/fmout-gps/S +5.3E-08 2006.145.18:47:31.12:!2006.145.18:54:46 2006.145.18:54:46.02:data_valid=off 2006.145.18:54:46.02:"et 2006.145.18:54:46.02:!+3s 2006.145.18:54:49.05:"tape 2006.145.18:54:49.09:postob 2006.145.18:54:49.25/cable/+6.5501E-03 2006.145.18:54:49.26/wx/15.73,1019.7,86 2006.145.18:54:49.34/fmout-gps/S +5.7E-08 2006.145.18:54:49.34:scan_name=145-1901,jd0605,180 2006.145.18:54:49.34:source=0014+813,001708.47,813508.1,2000.0,neutral 2006.145.18:54:50.14#flagr#flagr/antenna,new-source 2006.145.18:54:50.14:checkk5 2006.145.18:54:50.66/chk_autoobs//k5ts1/ autoobs is running! 2006.145.18:54:51.11/chk_autoobs//k5ts2/ autoobs is running! 2006.145.18:54:51.57/chk_autoobs//k5ts3/ autoobs is running! 2006.145.18:54:52.01/chk_autoobs//k5ts4/ autoobs is running! 2006.145.18:54:52.44/chk_obsdata//k5ts1/T1451847??a.dat file size is correct (nominal:1760MB, actual:1756MB). 2006.145.18:54:52.88/chk_obsdata//k5ts2/T1451847??b.dat file size is correct (nominal:1760MB, actual:1756MB). 2006.145.18:54:53.31/chk_obsdata//k5ts3/T1451847??c.dat file size is correct (nominal:1760MB, actual:1756MB). 2006.145.18:54:53.77/chk_obsdata//k5ts4/T1451847??d.dat file size is correct (nominal:1760MB, actual:1756MB). 2006.145.18:54:54.54/k5log//k5ts1_log_newline 2006.145.18:54:55.29/k5log//k5ts2_log_newline 2006.145.18:54:56.03/k5log//k5ts3_log_newline 2006.145.18:54:56.78/k5log//k5ts4_log_newline 2006.145.18:54:56.81/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.18:54:56.81:setupk4=1 2006.145.18:54:56.81$setupk4/echo=on 2006.145.18:54:56.81$setupk4/pcalon 2006.145.18:54:56.81$pcalon/"no phase cal control is implemented here 2006.145.18:54:56.81$setupk4/"tpicd=stop 2006.145.18:54:56.81$setupk4/"rec=synch_on 2006.145.18:54:56.81$setupk4/"rec_mode=128 2006.145.18:54:56.81$setupk4/!* 2006.145.18:54:56.81$setupk4/recpk4 2006.145.18:54:56.81$recpk4/recpatch= 2006.145.18:54:56.82$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.18:54:56.82$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.18:54:56.82$setupk4/vck44 2006.145.18:54:56.82$vck44/valo=1,524.99 2006.145.18:54:56.82#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.18:54:56.82#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.18:54:56.82#ibcon#ireg 17 cls_cnt 0 2006.145.18:54:56.82#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:54:56.82#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:54:56.82#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:54:56.85#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.18:54:56.89#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:54:56.89#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:54:56.89#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.18:54:56.89#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.18:54:56.89$vck44/va=1,8 2006.145.18:54:56.90#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.18:54:56.90#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.18:54:56.90#ibcon#ireg 11 cls_cnt 2 2006.145.18:54:56.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:54:56.90#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:54:56.90#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:54:56.91#ibcon#[25=AT01-08\r\n] 2006.145.18:54:56.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:54:56.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:54:56.94#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.18:54:56.94#ibcon#ireg 7 cls_cnt 0 2006.145.18:54:56.94#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:54:57.07#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:54:57.07#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:54:57.09#ibcon#[25=USB\r\n] 2006.145.18:54:57.11#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:54:57.11#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:54:57.11#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.18:54:57.11#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.18:54:57.12$vck44/valo=2,534.99 2006.145.18:54:57.12#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.18:54:57.12#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.18:54:57.12#ibcon#ireg 17 cls_cnt 0 2006.145.18:54:57.12#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:54:57.12#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:54:57.12#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:54:57.15#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.18:54:57.18#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:54:57.18#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:54:57.18#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.18:54:57.18#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.18:54:57.19$vck44/va=2,7 2006.145.18:54:57.19#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.18:54:57.19#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.18:54:57.19#ibcon#ireg 11 cls_cnt 2 2006.145.18:54:57.19#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:54:57.22#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:54:57.22#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:54:57.24#ibcon#[25=AT02-07\r\n] 2006.145.18:54:57.27#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:54:57.27#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:54:57.27#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.18:54:57.27#ibcon#ireg 7 cls_cnt 0 2006.145.18:54:57.27#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:54:57.39#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:54:57.39#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:54:57.41#ibcon#[25=USB\r\n] 2006.145.18:54:57.44#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:54:57.44#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:54:57.44#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.18:54:57.44#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.18:54:57.44$vck44/valo=3,564.99 2006.145.18:54:57.45#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.18:54:57.45#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.18:54:57.45#ibcon#ireg 17 cls_cnt 0 2006.145.18:54:57.45#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:54:57.45#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:54:57.45#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:54:57.46#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.18:54:57.50#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:54:57.50#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:54:57.50#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.18:54:57.50#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.18:54:57.50$vck44/va=3,8 2006.145.18:54:57.51#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.18:54:57.51#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.18:54:57.51#ibcon#ireg 11 cls_cnt 2 2006.145.18:54:57.51#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:54:57.55#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:54:57.55#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:54:57.57#ibcon#[25=AT03-08\r\n] 2006.145.18:54:57.60#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:54:57.60#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:54:57.60#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.18:54:57.60#ibcon#ireg 7 cls_cnt 0 2006.145.18:54:57.60#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:54:57.72#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:54:57.72#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:54:57.74#ibcon#[25=USB\r\n] 2006.145.18:54:57.77#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:54:57.77#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:54:57.77#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.18:54:57.77#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.18:54:57.77$vck44/valo=4,624.99 2006.145.18:54:57.78#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.18:54:57.78#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.18:54:57.78#ibcon#ireg 17 cls_cnt 0 2006.145.18:54:57.78#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:54:57.78#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:54:57.78#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:54:57.79#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.18:54:57.83#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:54:57.83#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:54:57.83#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.18:54:57.83#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.18:54:57.83$vck44/va=4,7 2006.145.18:54:57.84#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.18:54:57.84#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.18:54:57.84#ibcon#ireg 11 cls_cnt 2 2006.145.18:54:57.84#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.18:54:57.88#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.18:54:57.88#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.18:54:57.90#ibcon#[25=AT04-07\r\n] 2006.145.18:54:57.93#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.18:54:57.93#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.18:54:57.93#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.18:54:57.93#ibcon#ireg 7 cls_cnt 0 2006.145.18:54:57.93#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.18:54:58.05#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.18:54:58.05#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.18:54:58.07#ibcon#[25=USB\r\n] 2006.145.18:54:58.10#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.18:54:58.10#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.18:54:58.10#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.18:54:58.10#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.18:54:58.10$vck44/valo=5,734.99 2006.145.18:54:58.10#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.18:54:58.10#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.18:54:58.10#ibcon#ireg 17 cls_cnt 0 2006.145.18:54:58.10#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:54:58.11#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:54:58.11#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:54:58.12#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.18:54:58.17#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:54:58.17#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:54:58.17#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.18:54:58.17#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.18:54:58.17$vck44/va=5,4 2006.145.18:54:58.17#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.18:54:58.17#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.18:54:58.17#ibcon#ireg 11 cls_cnt 2 2006.145.18:54:58.17#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.18:54:58.21#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.18:54:58.21#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.18:54:58.23#ibcon#[25=AT05-04\r\n] 2006.145.18:54:58.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.18:54:58.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.18:54:58.26#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.18:54:58.26#ibcon#ireg 7 cls_cnt 0 2006.145.18:54:58.26#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.18:54:58.31#abcon#<5=/06 2.0 3.3 15.73 861019.7\r\n> 2006.145.18:54:58.33#abcon#{5=INTERFACE CLEAR} 2006.145.18:54:58.39#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.18:54:58.39#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.18:54:58.41#ibcon#[25=USB\r\n] 2006.145.18:54:58.41#abcon#[5=S1D000X0/0*\r\n] 2006.145.18:54:58.43#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.18:54:58.43#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.18:54:58.43#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.18:54:58.43#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.18:54:58.43$vck44/valo=6,814.99 2006.145.18:54:58.44#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.18:54:58.44#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.18:54:58.44#ibcon#ireg 17 cls_cnt 0 2006.145.18:54:58.44#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:54:58.44#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:54:58.44#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:54:58.45#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.18:54:58.49#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:54:58.49#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:54:58.49#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.18:54:58.49#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.18:54:58.49$vck44/va=6,4 2006.145.18:54:58.50#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.18:54:58.50#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.18:54:58.50#ibcon#ireg 11 cls_cnt 2 2006.145.18:54:58.50#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.18:54:58.54#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.18:54:58.54#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.18:54:58.56#ibcon#[25=AT06-04\r\n] 2006.145.18:54:58.59#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.18:54:58.59#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.18:54:58.59#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.18:54:58.59#ibcon#ireg 7 cls_cnt 0 2006.145.18:54:58.59#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.18:54:58.71#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.18:54:58.71#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.18:54:58.73#ibcon#[25=USB\r\n] 2006.145.18:54:58.76#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.18:54:58.76#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.18:54:58.76#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.18:54:58.76#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.18:54:58.76$vck44/valo=7,864.99 2006.145.18:54:58.77#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.18:54:58.77#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.18:54:58.77#ibcon#ireg 17 cls_cnt 0 2006.145.18:54:58.77#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.18:54:58.77#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.18:54:58.77#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.18:54:58.78#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.18:54:58.82#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.18:54:58.82#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.18:54:58.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.18:54:58.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.18:54:58.82$vck44/va=7,4 2006.145.18:54:58.82#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.18:54:58.82#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.18:54:58.83#ibcon#ireg 11 cls_cnt 2 2006.145.18:54:58.83#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.18:54:58.87#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.18:54:58.87#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.18:54:58.89#ibcon#[25=AT07-04\r\n] 2006.145.18:54:58.92#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.18:54:58.92#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.18:54:58.92#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.18:54:58.92#ibcon#ireg 7 cls_cnt 0 2006.145.18:54:58.92#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.18:54:59.04#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.18:54:59.04#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.18:54:59.06#ibcon#[25=USB\r\n] 2006.145.18:54:59.09#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.18:54:59.09#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.18:54:59.09#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.18:54:59.09#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.18:54:59.09$vck44/valo=8,884.99 2006.145.18:54:59.10#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.18:54:59.10#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.18:54:59.10#ibcon#ireg 17 cls_cnt 0 2006.145.18:54:59.10#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:54:59.10#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:54:59.10#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:54:59.11#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.18:54:59.15#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:54:59.15#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:54:59.15#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.18:54:59.15#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.18:54:59.15$vck44/va=8,4 2006.145.18:54:59.15#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.18:54:59.15#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.18:54:59.15#ibcon#ireg 11 cls_cnt 2 2006.145.18:54:59.15#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.18:54:59.21#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.18:54:59.21#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.18:54:59.23#ibcon#[25=AT08-04\r\n] 2006.145.18:54:59.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.18:54:59.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.18:54:59.26#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.18:54:59.26#ibcon#ireg 7 cls_cnt 0 2006.145.18:54:59.26#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.18:54:59.38#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.18:54:59.38#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.18:54:59.40#ibcon#[25=USB\r\n] 2006.145.18:54:59.43#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.18:54:59.43#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.18:54:59.43#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.18:54:59.43#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.18:54:59.44$vck44/vblo=1,629.99 2006.145.18:54:59.44#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.18:54:59.44#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.18:54:59.44#ibcon#ireg 17 cls_cnt 0 2006.145.18:54:59.44#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:54:59.44#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:54:59.44#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:54:59.45#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.18:54:59.50#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:54:59.50#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.18:54:59.50#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.18:54:59.50#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.18:54:59.50$vck44/vb=1,3 2006.145.18:54:59.50#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.18:54:59.50#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.18:54:59.50#ibcon#ireg 11 cls_cnt 2 2006.145.18:54:59.50#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:54:59.50#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:54:59.50#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:54:59.51#ibcon#[27=AT01-03\r\n] 2006.145.18:54:59.54#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:54:59.54#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.18:54:59.54#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.18:54:59.54#ibcon#ireg 7 cls_cnt 0 2006.145.18:54:59.54#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:54:59.66#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:54:59.66#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:54:59.68#ibcon#[27=USB\r\n] 2006.145.18:54:59.71#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:54:59.71#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.18:54:59.71#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.18:54:59.71#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.18:54:59.71$vck44/vblo=2,634.99 2006.145.18:54:59.72#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.18:54:59.72#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.18:54:59.72#ibcon#ireg 17 cls_cnt 0 2006.145.18:54:59.72#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:54:59.72#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:54:59.72#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:54:59.73#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.18:54:59.77#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:54:59.77#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.18:54:59.77#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.18:54:59.77#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.18:54:59.77$vck44/vb=2,4 2006.145.18:54:59.78#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.18:54:59.78#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.18:54:59.78#ibcon#ireg 11 cls_cnt 2 2006.145.18:54:59.78#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:54:59.82#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:54:59.82#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:54:59.84#ibcon#[27=AT02-04\r\n] 2006.145.18:54:59.87#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:54:59.87#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.18:54:59.87#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.18:54:59.87#ibcon#ireg 7 cls_cnt 0 2006.145.18:54:59.87#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:54:59.99#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:54:59.99#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:55:00.01#ibcon#[27=USB\r\n] 2006.145.18:55:00.04#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:55:00.04#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.18:55:00.04#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.18:55:00.04#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.18:55:00.04$vck44/vblo=3,649.99 2006.145.18:55:00.05#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.18:55:00.05#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.18:55:00.05#ibcon#ireg 17 cls_cnt 0 2006.145.18:55:00.05#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:55:00.05#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:55:00.05#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:55:00.06#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.18:55:00.10#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:55:00.10#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.18:55:00.10#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.18:55:00.10#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.18:55:00.10$vck44/vb=3,4 2006.145.18:55:00.11#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.18:55:00.11#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.18:55:00.11#ibcon#ireg 11 cls_cnt 2 2006.145.18:55:00.11#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:55:00.15#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:55:00.15#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:55:00.17#ibcon#[27=AT03-04\r\n] 2006.145.18:55:00.20#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:55:00.20#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.18:55:00.20#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.18:55:00.20#ibcon#ireg 7 cls_cnt 0 2006.145.18:55:00.20#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:55:00.32#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:55:00.32#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:55:00.34#ibcon#[27=USB\r\n] 2006.145.18:55:00.37#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:55:00.37#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.18:55:00.37#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.18:55:00.37#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.18:55:00.38$vck44/vblo=4,679.99 2006.145.18:55:00.38#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.18:55:00.38#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.18:55:00.38#ibcon#ireg 17 cls_cnt 0 2006.145.18:55:00.38#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:55:00.38#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:55:00.38#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:55:00.39#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.18:55:00.43#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:55:00.43#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.18:55:00.43#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.18:55:00.43#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.18:55:00.43$vck44/vb=4,4 2006.145.18:55:00.43#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.18:55:00.43#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.18:55:00.43#ibcon#ireg 11 cls_cnt 2 2006.145.18:55:00.43#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.18:55:00.49#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.18:55:00.49#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.18:55:00.51#ibcon#[27=AT04-04\r\n] 2006.145.18:55:00.54#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.18:55:00.54#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.18:55:00.54#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.18:55:00.54#ibcon#ireg 7 cls_cnt 0 2006.145.18:55:00.54#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.18:55:00.66#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.18:55:00.66#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.18:55:00.68#ibcon#[27=USB\r\n] 2006.145.18:55:00.71#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.18:55:00.71#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.18:55:00.71#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.18:55:00.71#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.18:55:00.71$vck44/vblo=5,709.99 2006.145.18:55:00.71#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.18:55:00.72#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.18:55:00.72#ibcon#ireg 17 cls_cnt 0 2006.145.18:55:00.72#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:55:00.72#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:55:00.72#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:55:00.73#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.18:55:00.77#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:55:00.77#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.18:55:00.77#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.18:55:00.77#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.18:55:00.78$vck44/vb=5,4 2006.145.18:55:00.78#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.18:55:00.78#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.18:55:00.78#ibcon#ireg 11 cls_cnt 2 2006.145.18:55:00.78#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.18:55:00.82#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.18:55:00.82#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.18:55:00.84#ibcon#[27=AT05-04\r\n] 2006.145.18:55:00.87#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.18:55:00.87#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.18:55:00.87#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.18:55:00.87#ibcon#ireg 7 cls_cnt 0 2006.145.18:55:00.87#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.18:55:00.99#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.18:55:00.99#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.18:55:01.01#ibcon#[27=USB\r\n] 2006.145.18:55:01.04#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.18:55:01.04#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.18:55:01.04#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.18:55:01.04#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.18:55:01.04$vck44/vblo=6,719.99 2006.145.18:55:01.05#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.18:55:01.05#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.18:55:01.05#ibcon#ireg 17 cls_cnt 0 2006.145.18:55:01.05#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:55:01.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:55:01.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:55:01.06#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.18:55:01.10#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:55:01.10#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.18:55:01.10#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.18:55:01.10#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.18:55:01.10$vck44/vb=6,4 2006.145.18:55:01.11#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.18:55:01.11#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.18:55:01.11#ibcon#ireg 11 cls_cnt 2 2006.145.18:55:01.11#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.18:55:01.15#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.18:55:01.15#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.18:55:01.17#ibcon#[27=AT06-04\r\n] 2006.145.18:55:01.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.18:55:01.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.18:55:01.20#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.18:55:01.20#ibcon#ireg 7 cls_cnt 0 2006.145.18:55:01.20#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.18:55:01.32#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.18:55:01.32#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.18:55:01.34#ibcon#[27=USB\r\n] 2006.145.18:55:01.37#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.18:55:01.37#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.18:55:01.37#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.18:55:01.37#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.18:55:01.37$vck44/vblo=7,734.99 2006.145.18:55:01.38#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.18:55:01.38#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.18:55:01.38#ibcon#ireg 17 cls_cnt 0 2006.145.18:55:01.38#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:55:01.38#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:55:01.38#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:55:01.39#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.18:55:01.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:55:01.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.18:55:01.43#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.18:55:01.43#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.18:55:01.43$vck44/vb=7,4 2006.145.18:55:01.44#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.18:55:01.44#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.18:55:01.44#ibcon#ireg 11 cls_cnt 2 2006.145.18:55:01.44#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.18:55:01.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.18:55:01.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.18:55:01.50#ibcon#[27=AT07-04\r\n] 2006.145.18:55:01.53#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.18:55:01.53#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.18:55:01.53#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.18:55:01.53#ibcon#ireg 7 cls_cnt 0 2006.145.18:55:01.53#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.18:55:01.65#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.18:55:01.65#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.18:55:01.67#ibcon#[27=USB\r\n] 2006.145.18:55:01.70#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.18:55:01.70#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.18:55:01.70#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.18:55:01.70#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.18:55:01.70$vck44/vblo=8,744.99 2006.145.18:55:01.71#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.18:55:01.71#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.18:55:01.71#ibcon#ireg 17 cls_cnt 0 2006.145.18:55:01.71#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.18:55:01.71#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.18:55:01.71#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.18:55:01.72#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.18:55:01.76#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.18:55:01.76#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.18:55:01.76#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.18:55:01.76#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.18:55:01.76$vck44/vb=8,4 2006.145.18:55:01.77#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.18:55:01.77#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.18:55:01.77#ibcon#ireg 11 cls_cnt 2 2006.145.18:55:01.77#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.18:55:01.81#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.18:55:01.81#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.18:55:01.83#ibcon#[27=AT08-04\r\n] 2006.145.18:55:01.86#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.18:55:01.86#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.18:55:01.86#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.18:55:01.86#ibcon#ireg 7 cls_cnt 0 2006.145.18:55:01.86#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.18:55:01.98#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.18:55:01.98#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.18:55:02.00#ibcon#[27=USB\r\n] 2006.145.18:55:02.03#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.18:55:02.03#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.18:55:02.03#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.18:55:02.03#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.18:55:02.03$vck44/vabw=wide 2006.145.18:55:02.03#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.18:55:02.03#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.18:55:02.03#ibcon#ireg 8 cls_cnt 0 2006.145.18:55:02.04#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:55:02.04#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:55:02.04#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:55:02.05#ibcon#[25=BW32\r\n] 2006.145.18:55:02.08#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:55:02.08#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.18:55:02.08#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.18:55:02.08#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.18:55:02.08$vck44/vbbw=wide 2006.145.18:55:02.09#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.18:55:02.09#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.18:55:02.09#ibcon#ireg 8 cls_cnt 0 2006.145.18:55:02.09#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.18:55:02.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.18:55:02.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.18:55:02.16#ibcon#[27=BW32\r\n] 2006.145.18:55:02.19#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.18:55:02.19#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.18:55:02.19#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.18:55:02.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.18:55:02.20$setupk4/ifdk4 2006.145.18:55:02.20$ifdk4/lo= 2006.145.18:55:02.20$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.18:55:02.20$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.18:55:02.20$ifdk4/patch= 2006.145.18:55:02.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.18:55:02.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.18:55:02.20$setupk4/!*+20s 2006.145.18:55:08.49#abcon#<5=/06 2.0 3.3 15.73 861019.7\r\n> 2006.145.18:55:08.51#abcon#{5=INTERFACE CLEAR} 2006.145.18:55:08.57#abcon#[5=S1D000X0/0*\r\n] 2006.145.18:55:15.14#trakl#Source acquired 2006.145.18:55:15.15#flagr#flagr/antenna,acquired 2006.145.18:55:16.83$setupk4/"tpicd 2006.145.18:55:16.83$setupk4/echo=off 2006.145.18:55:16.83$setupk4/xlog=off 2006.145.18:55:16.83:!2006.145.19:00:56 2006.145.19:00:56.00:preob 2006.145.19:00:56.13/onsource/TRACKING 2006.145.19:00:56.13:!2006.145.19:01:06 2006.145.19:01:06.00:"tape 2006.145.19:01:06.00:"st=record 2006.145.19:01:06.00:data_valid=on 2006.145.19:01:06.00:midob 2006.145.19:01:06.14/onsource/TRACKING 2006.145.19:01:06.14/wx/15.73,1019.7,85 2006.145.19:01:06.25/cable/+6.5473E-03 2006.145.19:01:07.34/va/01,08,usb,yes,28,30 2006.145.19:01:07.34/va/02,07,usb,yes,30,31 2006.145.19:01:07.34/va/03,08,usb,yes,27,29 2006.145.19:01:07.34/va/04,07,usb,yes,31,33 2006.145.19:01:07.34/va/05,04,usb,yes,27,28 2006.145.19:01:07.34/va/06,04,usb,yes,30,30 2006.145.19:01:07.34/va/07,04,usb,yes,31,32 2006.145.19:01:07.34/va/08,04,usb,yes,26,32 2006.145.19:01:07.57/valo/01,524.99,yes,locked 2006.145.19:01:07.57/valo/02,534.99,yes,locked 2006.145.19:01:07.57/valo/03,564.99,yes,locked 2006.145.19:01:07.57/valo/04,624.99,yes,locked 2006.145.19:01:07.57/valo/05,734.99,yes,locked 2006.145.19:01:07.57/valo/06,814.99,yes,locked 2006.145.19:01:07.57/valo/07,864.99,yes,locked 2006.145.19:01:07.57/valo/08,884.99,yes,locked 2006.145.19:01:08.66/vb/01,03,usb,yes,35,33 2006.145.19:01:08.66/vb/02,04,usb,yes,31,31 2006.145.19:01:08.66/vb/03,04,usb,yes,28,31 2006.145.19:01:08.66/vb/04,04,usb,yes,32,31 2006.145.19:01:08.66/vb/05,04,usb,yes,25,27 2006.145.19:01:08.66/vb/06,04,usb,yes,29,26 2006.145.19:01:08.66/vb/07,04,usb,yes,29,29 2006.145.19:01:08.66/vb/08,04,usb,yes,27,30 2006.145.19:01:08.89/vblo/01,629.99,yes,locked 2006.145.19:01:08.89/vblo/02,634.99,yes,locked 2006.145.19:01:08.89/vblo/03,649.99,yes,locked 2006.145.19:01:08.89/vblo/04,679.99,yes,locked 2006.145.19:01:08.89/vblo/05,709.99,yes,locked 2006.145.19:01:08.89/vblo/06,719.99,yes,locked 2006.145.19:01:08.89/vblo/07,734.99,yes,locked 2006.145.19:01:08.89/vblo/08,744.99,yes,locked 2006.145.19:01:09.04/vabw/8 2006.145.19:01:09.19/vbbw/8 2006.145.19:01:09.28/xfe/off,on,15.2 2006.145.19:01:09.66/ifatt/23,28,28,28 2006.145.19:01:10.07/fmout-gps/S +5.8E-08 2006.145.19:01:10.11:!2006.145.19:04:06 2006.145.19:04:06.01:data_valid=off 2006.145.19:04:06.02:"et 2006.145.19:04:06.02:!+3s 2006.145.19:04:09.03:"tape 2006.145.19:04:09.04:postob 2006.145.19:04:09.21/cable/+6.5497E-03 2006.145.19:04:09.22/wx/15.74,1019.8,85 2006.145.19:04:09.27/fmout-gps/S +5.8E-08 2006.145.19:04:09.28:scan_name=145-1915,jd0605,40 2006.145.19:04:09.28:source=2134+00,213638.59,004154.2,2000.0,cw 2006.145.19:04:10.14#flagr#flagr/antenna,new-source 2006.145.19:04:10.15:checkk5 2006.145.19:04:10.61/chk_autoobs//k5ts1/ autoobs is running! 2006.145.19:04:11.05/chk_autoobs//k5ts2/ autoobs is running! 2006.145.19:04:11.49/chk_autoobs//k5ts3/ autoobs is running! 2006.145.19:04:11.92/chk_autoobs//k5ts4/ autoobs is running! 2006.145.19:04:12.34/chk_obsdata//k5ts1/T1451901??a.dat file size is correct (nominal:720MB, actual:716MB). 2006.145.19:04:12.77/chk_obsdata//k5ts2/T1451901??b.dat file size is correct (nominal:720MB, actual:716MB). 2006.145.19:04:13.21/chk_obsdata//k5ts3/T1451901??c.dat file size is correct (nominal:720MB, actual:716MB). 2006.145.19:04:13.65/chk_obsdata//k5ts4/T1451901??d.dat file size is correct (nominal:720MB, actual:716MB). 2006.145.19:04:14.42/k5log//k5ts1_log_newline 2006.145.19:04:15.16/k5log//k5ts2_log_newline 2006.145.19:04:15.91/k5log//k5ts3_log_newline 2006.145.19:04:16.65/k5log//k5ts4_log_newline 2006.145.19:04:16.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.19:04:16.67:setupk4=1 2006.145.19:04:16.67$setupk4/echo=on 2006.145.19:04:16.67$setupk4/pcalon 2006.145.19:04:16.67$pcalon/"no phase cal control is implemented here 2006.145.19:04:16.67$setupk4/"tpicd=stop 2006.145.19:04:16.67$setupk4/"rec=synch_on 2006.145.19:04:16.67$setupk4/"rec_mode=128 2006.145.19:04:16.67$setupk4/!* 2006.145.19:04:16.67$setupk4/recpk4 2006.145.19:04:16.67$recpk4/recpatch= 2006.145.19:04:16.68$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.19:04:16.68$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.19:04:16.68$setupk4/vck44 2006.145.19:04:16.68$vck44/valo=1,524.99 2006.145.19:04:16.68#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.19:04:16.68#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.19:04:16.68#ibcon#ireg 17 cls_cnt 0 2006.145.19:04:16.68#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.19:04:16.68#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.19:04:16.68#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.19:04:16.71#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.19:04:16.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.19:04:16.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.19:04:16.76#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.19:04:16.76#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.19:04:16.76$vck44/va=1,8 2006.145.19:04:16.76#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.19:04:16.76#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.19:04:16.76#ibcon#ireg 11 cls_cnt 2 2006.145.19:04:16.76#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.19:04:16.76#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.19:04:16.76#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.19:04:16.78#ibcon#[25=AT01-08\r\n] 2006.145.19:04:16.81#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.19:04:16.81#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.19:04:16.81#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.19:04:16.81#ibcon#ireg 7 cls_cnt 0 2006.145.19:04:16.81#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.19:04:16.95#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.19:04:16.95#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.19:04:16.96#ibcon#[25=USB\r\n] 2006.145.19:04:16.99#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.19:04:16.99#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.19:04:16.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.19:04:16.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.19:04:16.99$vck44/valo=2,534.99 2006.145.19:04:16.99#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.19:04:16.99#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.19:04:16.99#ibcon#ireg 17 cls_cnt 0 2006.145.19:04:16.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.19:04:16.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.19:04:16.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.19:04:17.01#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.19:04:17.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.19:04:17.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.19:04:17.06#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.19:04:17.06#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.19:04:17.06$vck44/va=2,7 2006.145.19:04:17.06#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.19:04:17.06#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.19:04:17.06#ibcon#ireg 11 cls_cnt 2 2006.145.19:04:17.06#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.19:04:17.10#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.19:04:17.10#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.19:04:17.12#ibcon#[25=AT02-07\r\n] 2006.145.19:04:17.15#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.19:04:17.15#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.19:04:17.15#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.19:04:17.15#ibcon#ireg 7 cls_cnt 0 2006.145.19:04:17.15#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.19:04:17.27#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.19:04:17.27#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.19:04:17.29#ibcon#[25=USB\r\n] 2006.145.19:04:17.32#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.19:04:17.32#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.19:04:17.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.19:04:17.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.19:04:17.32$vck44/valo=3,564.99 2006.145.19:04:17.32#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.19:04:17.32#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.19:04:17.32#ibcon#ireg 17 cls_cnt 0 2006.145.19:04:17.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.19:04:17.32#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.19:04:17.32#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.19:04:17.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.19:04:17.38#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.19:04:17.38#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.19:04:17.38#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.19:04:17.38#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.19:04:17.38$vck44/va=3,8 2006.145.19:04:17.38#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.19:04:17.38#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.19:04:17.38#ibcon#ireg 11 cls_cnt 2 2006.145.19:04:17.38#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.19:04:17.44#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.19:04:17.44#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.19:04:17.46#ibcon#[25=AT03-08\r\n] 2006.145.19:04:17.49#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.19:04:17.49#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.19:04:17.49#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.19:04:17.49#ibcon#ireg 7 cls_cnt 0 2006.145.19:04:17.49#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.19:04:17.61#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.19:04:17.61#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.19:04:17.63#ibcon#[25=USB\r\n] 2006.145.19:04:17.66#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.19:04:17.66#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.19:04:17.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.19:04:17.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.19:04:17.66$vck44/valo=4,624.99 2006.145.19:04:17.66#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.19:04:17.66#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.19:04:17.66#ibcon#ireg 17 cls_cnt 0 2006.145.19:04:17.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.19:04:17.66#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.19:04:17.66#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.19:04:17.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.19:04:17.72#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.19:04:17.72#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.19:04:17.72#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.19:04:17.72#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.19:04:17.72$vck44/va=4,7 2006.145.19:04:17.72#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.19:04:17.72#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.19:04:17.72#ibcon#ireg 11 cls_cnt 2 2006.145.19:04:17.72#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.19:04:17.78#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.19:04:17.78#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.19:04:17.80#ibcon#[25=AT04-07\r\n] 2006.145.19:04:17.83#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.19:04:17.83#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.19:04:17.83#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.19:04:17.83#ibcon#ireg 7 cls_cnt 0 2006.145.19:04:17.83#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.19:04:17.95#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.19:04:17.95#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.19:04:17.97#ibcon#[25=USB\r\n] 2006.145.19:04:18.00#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.19:04:18.00#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.19:04:18.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.19:04:18.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.19:04:18.00$vck44/valo=5,734.99 2006.145.19:04:18.00#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.19:04:18.00#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.19:04:18.00#ibcon#ireg 17 cls_cnt 0 2006.145.19:04:18.00#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.19:04:18.00#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.19:04:18.00#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.19:04:18.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.19:04:18.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.19:04:18.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.19:04:18.06#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.19:04:18.06#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.19:04:18.06$vck44/va=5,4 2006.145.19:04:18.06#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.19:04:18.06#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.19:04:18.06#ibcon#ireg 11 cls_cnt 2 2006.145.19:04:18.06#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.19:04:18.12#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.19:04:18.12#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.19:04:18.14#ibcon#[25=AT05-04\r\n] 2006.145.19:04:18.17#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.19:04:18.17#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.19:04:18.17#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.19:04:18.17#ibcon#ireg 7 cls_cnt 0 2006.145.19:04:18.17#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.19:04:18.29#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.19:04:18.29#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.19:04:18.31#ibcon#[25=USB\r\n] 2006.145.19:04:18.34#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.19:04:18.34#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.19:04:18.34#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.19:04:18.34#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.19:04:18.34$vck44/valo=6,814.99 2006.145.19:04:18.34#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.19:04:18.34#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.19:04:18.34#ibcon#ireg 17 cls_cnt 0 2006.145.19:04:18.34#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.19:04:18.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.19:04:18.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.19:04:18.36#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.19:04:18.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.19:04:18.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.19:04:18.40#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.19:04:18.40#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.19:04:18.40$vck44/va=6,4 2006.145.19:04:18.40#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.19:04:18.40#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.19:04:18.40#ibcon#ireg 11 cls_cnt 2 2006.145.19:04:18.40#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.19:04:18.46#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.19:04:18.46#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.19:04:18.48#ibcon#[25=AT06-04\r\n] 2006.145.19:04:18.51#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.19:04:18.51#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.19:04:18.51#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.19:04:18.51#ibcon#ireg 7 cls_cnt 0 2006.145.19:04:18.51#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.19:04:18.63#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.19:04:18.63#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.19:04:18.65#ibcon#[25=USB\r\n] 2006.145.19:04:18.68#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.19:04:18.68#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.19:04:18.68#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.19:04:18.68#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.19:04:18.68$vck44/valo=7,864.99 2006.145.19:04:18.68#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.19:04:18.68#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.19:04:18.68#ibcon#ireg 17 cls_cnt 0 2006.145.19:04:18.68#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:04:18.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:04:18.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:04:18.70#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.19:04:18.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:04:18.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:04:18.74#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.19:04:18.74#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.19:04:18.74$vck44/va=7,4 2006.145.19:04:18.74#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.19:04:18.74#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.19:04:18.74#ibcon#ireg 11 cls_cnt 2 2006.145.19:04:18.74#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.19:04:18.80#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.19:04:18.80#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.19:04:18.82#ibcon#[25=AT07-04\r\n] 2006.145.19:04:18.85#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.19:04:18.85#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.19:04:18.85#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.19:04:18.85#ibcon#ireg 7 cls_cnt 0 2006.145.19:04:18.85#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.19:04:18.97#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.19:04:18.97#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.19:04:18.99#ibcon#[25=USB\r\n] 2006.145.19:04:19.02#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.19:04:19.02#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.19:04:19.02#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.19:04:19.02#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.19:04:19.02$vck44/valo=8,884.99 2006.145.19:04:19.02#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.19:04:19.02#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.19:04:19.02#ibcon#ireg 17 cls_cnt 0 2006.145.19:04:19.02#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.19:04:19.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.19:04:19.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.19:04:19.04#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.19:04:19.08#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.19:04:19.08#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.19:04:19.08#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.19:04:19.08#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.19:04:19.08$vck44/va=8,4 2006.145.19:04:19.08#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.19:04:19.08#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.19:04:19.08#ibcon#ireg 11 cls_cnt 2 2006.145.19:04:19.08#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.19:04:19.14#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.19:04:19.14#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.19:04:19.16#ibcon#[25=AT08-04\r\n] 2006.145.19:04:19.19#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.19:04:19.19#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.19:04:19.19#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.19:04:19.19#ibcon#ireg 7 cls_cnt 0 2006.145.19:04:19.19#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.19:04:19.33#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.19:04:19.33#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.19:04:19.34#ibcon#[25=USB\r\n] 2006.145.19:04:19.37#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.19:04:19.37#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.19:04:19.37#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.19:04:19.37#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.19:04:19.37$vck44/vblo=1,629.99 2006.145.19:04:19.37#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.19:04:19.37#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.19:04:19.37#ibcon#ireg 17 cls_cnt 0 2006.145.19:04:19.37#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.19:04:19.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.19:04:19.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.19:04:19.39#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.19:04:19.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.19:04:19.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.19:04:19.43#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.19:04:19.43#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.19:04:19.43$vck44/vb=1,3 2006.145.19:04:19.43#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.19:04:19.43#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.19:04:19.43#ibcon#ireg 11 cls_cnt 2 2006.145.19:04:19.43#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.19:04:19.43#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.19:04:19.43#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.19:04:19.45#ibcon#[27=AT01-03\r\n] 2006.145.19:04:19.48#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.19:04:19.48#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.19:04:19.48#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.19:04:19.48#ibcon#ireg 7 cls_cnt 0 2006.145.19:04:19.48#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.19:04:19.60#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.19:04:19.60#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.19:04:19.62#ibcon#[27=USB\r\n] 2006.145.19:04:19.65#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.19:04:19.65#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.19:04:19.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.19:04:19.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.19:04:19.65$vck44/vblo=2,634.99 2006.145.19:04:19.65#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.19:04:19.65#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.19:04:19.65#ibcon#ireg 17 cls_cnt 0 2006.145.19:04:19.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.19:04:19.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.19:04:19.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.19:04:19.67#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.19:04:19.71#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.19:04:19.71#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.19:04:19.71#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.19:04:19.71#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.19:04:19.71$vck44/vb=2,4 2006.145.19:04:19.71#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.19:04:19.71#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.19:04:19.71#ibcon#ireg 11 cls_cnt 2 2006.145.19:04:19.71#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.19:04:19.77#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.19:04:19.77#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.19:04:19.79#ibcon#[27=AT02-04\r\n] 2006.145.19:04:19.82#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.19:04:19.82#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.19:04:19.82#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.19:04:19.82#ibcon#ireg 7 cls_cnt 0 2006.145.19:04:19.82#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.19:04:19.94#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.19:04:19.94#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.19:04:19.96#ibcon#[27=USB\r\n] 2006.145.19:04:19.99#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.19:04:19.99#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.19:04:19.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.19:04:19.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.19:04:19.99$vck44/vblo=3,649.99 2006.145.19:04:19.99#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.19:04:19.99#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.19:04:19.99#ibcon#ireg 17 cls_cnt 0 2006.145.19:04:19.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.19:04:19.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.19:04:19.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.19:04:20.01#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.19:04:20.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.19:04:20.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.19:04:20.05#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.19:04:20.05#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.19:04:20.05$vck44/vb=3,4 2006.145.19:04:20.05#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.19:04:20.05#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.19:04:20.05#ibcon#ireg 11 cls_cnt 2 2006.145.19:04:20.05#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.19:04:20.11#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.19:04:20.11#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.19:04:20.13#ibcon#[27=AT03-04\r\n] 2006.145.19:04:20.16#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.19:04:20.16#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.19:04:20.16#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.19:04:20.16#ibcon#ireg 7 cls_cnt 0 2006.145.19:04:20.16#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.19:04:20.28#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.19:04:20.28#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.19:04:20.30#ibcon#[27=USB\r\n] 2006.145.19:04:20.33#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.19:04:20.33#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.19:04:20.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.19:04:20.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.19:04:20.33$vck44/vblo=4,679.99 2006.145.19:04:20.33#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.19:04:20.33#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.19:04:20.33#ibcon#ireg 17 cls_cnt 0 2006.145.19:04:20.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.19:04:20.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.19:04:20.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.19:04:20.35#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.19:04:20.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.19:04:20.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.19:04:20.39#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.19:04:20.39#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.19:04:20.39$vck44/vb=4,4 2006.145.19:04:20.39#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.19:04:20.39#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.19:04:20.39#ibcon#ireg 11 cls_cnt 2 2006.145.19:04:20.39#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.19:04:20.45#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.19:04:20.45#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.19:04:20.47#ibcon#[27=AT04-04\r\n] 2006.145.19:04:20.50#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.19:04:20.50#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.19:04:20.50#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.19:04:20.50#ibcon#ireg 7 cls_cnt 0 2006.145.19:04:20.50#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.19:04:20.59#abcon#<5=/07 2.2 3.8 15.74 851019.8\r\n> 2006.145.19:04:20.61#abcon#{5=INTERFACE CLEAR} 2006.145.19:04:20.62#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.19:04:20.62#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.19:04:20.64#ibcon#[27=USB\r\n] 2006.145.19:04:20.67#abcon#[5=S1D000X0/0*\r\n] 2006.145.19:04:20.67#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.19:04:20.67#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.19:04:20.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.19:04:20.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.19:04:20.67$vck44/vblo=5,709.99 2006.145.19:04:20.67#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.19:04:20.67#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.19:04:20.67#ibcon#ireg 17 cls_cnt 0 2006.145.19:04:20.67#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.19:04:20.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.19:04:20.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.19:04:20.69#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.19:04:20.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.19:04:20.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.19:04:20.73#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.19:04:20.73#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.19:04:20.73$vck44/vb=5,4 2006.145.19:04:20.73#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.19:04:20.73#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.19:04:20.73#ibcon#ireg 11 cls_cnt 2 2006.145.19:04:20.73#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.19:04:20.79#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.19:04:20.79#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.19:04:20.81#ibcon#[27=AT05-04\r\n] 2006.145.19:04:20.84#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.19:04:20.84#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.19:04:20.84#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.19:04:20.84#ibcon#ireg 7 cls_cnt 0 2006.145.19:04:20.84#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.19:04:20.96#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.19:04:20.96#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.19:04:20.98#ibcon#[27=USB\r\n] 2006.145.19:04:21.01#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.19:04:21.01#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.19:04:21.01#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.19:04:21.01#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.19:04:21.01$vck44/vblo=6,719.99 2006.145.19:04:21.01#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.19:04:21.01#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.19:04:21.01#ibcon#ireg 17 cls_cnt 0 2006.145.19:04:21.01#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.19:04:21.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.19:04:21.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.19:04:21.03#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.19:04:21.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.19:04:21.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.19:04:21.07#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.19:04:21.07#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.19:04:21.07$vck44/vb=6,4 2006.145.19:04:21.07#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.19:04:21.07#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.19:04:21.07#ibcon#ireg 11 cls_cnt 2 2006.145.19:04:21.07#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.19:04:21.13#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.19:04:21.13#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.19:04:21.15#ibcon#[27=AT06-04\r\n] 2006.145.19:04:21.18#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.19:04:21.18#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.19:04:21.18#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.19:04:21.18#ibcon#ireg 7 cls_cnt 0 2006.145.19:04:21.18#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.19:04:21.30#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.19:04:21.30#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.19:04:21.32#ibcon#[27=USB\r\n] 2006.145.19:04:21.35#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.19:04:21.35#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.19:04:21.35#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.19:04:21.35#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.19:04:21.35$vck44/vblo=7,734.99 2006.145.19:04:21.35#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.19:04:21.35#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.19:04:21.35#ibcon#ireg 17 cls_cnt 0 2006.145.19:04:21.35#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:04:21.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:04:21.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:04:21.37#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.19:04:21.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:04:21.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:04:21.41#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.19:04:21.41#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.19:04:21.41$vck44/vb=7,4 2006.145.19:04:21.41#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.19:04:21.41#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.19:04:21.41#ibcon#ireg 11 cls_cnt 2 2006.145.19:04:21.41#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.19:04:21.47#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.19:04:21.47#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.19:04:21.49#ibcon#[27=AT07-04\r\n] 2006.145.19:04:21.52#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.19:04:21.52#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.19:04:21.52#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.19:04:21.52#ibcon#ireg 7 cls_cnt 0 2006.145.19:04:21.52#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.19:04:21.64#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.19:04:21.64#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.19:04:21.66#ibcon#[27=USB\r\n] 2006.145.19:04:21.69#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.19:04:21.69#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.19:04:21.69#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.19:04:21.69#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.19:04:21.69$vck44/vblo=8,744.99 2006.145.19:04:21.69#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.19:04:21.69#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.19:04:21.69#ibcon#ireg 17 cls_cnt 0 2006.145.19:04:21.69#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.19:04:21.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.19:04:21.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.19:04:21.71#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.19:04:21.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.19:04:21.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.19:04:21.75#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.19:04:21.75#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.19:04:21.75$vck44/vb=8,4 2006.145.19:04:21.75#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.19:04:21.75#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.19:04:21.75#ibcon#ireg 11 cls_cnt 2 2006.145.19:04:21.75#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.19:04:21.81#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.19:04:21.81#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.19:04:21.83#ibcon#[27=AT08-04\r\n] 2006.145.19:04:21.86#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.19:04:21.86#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.19:04:21.86#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.19:04:21.86#ibcon#ireg 7 cls_cnt 0 2006.145.19:04:21.86#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.19:04:21.98#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.19:04:21.98#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.19:04:22.00#ibcon#[27=USB\r\n] 2006.145.19:04:22.03#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.19:04:22.03#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.19:04:22.03#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.19:04:22.03#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.19:04:22.03$vck44/vabw=wide 2006.145.19:04:22.03#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.19:04:22.03#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.19:04:22.03#ibcon#ireg 8 cls_cnt 0 2006.145.19:04:22.03#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.19:04:22.03#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.19:04:22.03#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.19:04:22.05#ibcon#[25=BW32\r\n] 2006.145.19:04:22.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.19:04:22.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.19:04:22.08#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.19:04:22.08#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.19:04:22.08$vck44/vbbw=wide 2006.145.19:04:22.08#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.19:04:22.08#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.19:04:22.08#ibcon#ireg 8 cls_cnt 0 2006.145.19:04:22.08#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:04:22.15#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:04:22.15#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:04:22.17#ibcon#[27=BW32\r\n] 2006.145.19:04:22.20#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:04:22.20#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:04:22.20#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.19:04:22.20#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.19:04:22.20$setupk4/ifdk4 2006.145.19:04:22.20$ifdk4/lo= 2006.145.19:04:22.20$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.19:04:22.20$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.19:04:22.20$ifdk4/patch= 2006.145.19:04:22.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.19:04:22.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.19:04:22.20$setupk4/!*+20s 2006.145.19:04:30.76#abcon#<5=/07 2.2 3.8 15.75 851019.8\r\n> 2006.145.19:04:30.78#abcon#{5=INTERFACE CLEAR} 2006.145.19:04:30.84#abcon#[5=S1D000X0/0*\r\n] 2006.145.19:04:36.68$setupk4/"tpicd 2006.145.19:04:36.68$setupk4/echo=off 2006.145.19:04:36.68$setupk4/xlog=off 2006.145.19:04:36.68:!2006.145.19:15:01 2006.145.19:05:05.14#trakl#Source acquired 2006.145.19:05:06.14#flagr#flagr/antenna,acquired 2006.145.19:15:01.00:preob 2006.145.19:15:01.14/onsource/TRACKING 2006.145.19:15:01.14:!2006.145.19:15:11 2006.145.19:15:11.00:"tape 2006.145.19:15:11.00:"st=record 2006.145.19:15:11.00:data_valid=on 2006.145.19:15:11.00:midob 2006.145.19:15:12.14/onsource/TRACKING 2006.145.19:15:12.14/wx/15.80,1019.9,86 2006.145.19:15:12.28/cable/+6.5501E-03 2006.145.19:15:13.37/va/01,08,usb,yes,29,31 2006.145.19:15:13.37/va/02,07,usb,yes,31,31 2006.145.19:15:13.37/va/03,08,usb,yes,28,29 2006.145.19:15:13.37/va/04,07,usb,yes,32,33 2006.145.19:15:13.37/va/05,04,usb,yes,27,28 2006.145.19:15:13.37/va/06,04,usb,yes,31,31 2006.145.19:15:13.37/va/07,04,usb,yes,31,32 2006.145.19:15:13.37/va/08,04,usb,yes,27,32 2006.145.19:15:13.60/valo/01,524.99,yes,locked 2006.145.19:15:13.60/valo/02,534.99,yes,locked 2006.145.19:15:13.60/valo/03,564.99,yes,locked 2006.145.19:15:13.60/valo/04,624.99,yes,locked 2006.145.19:15:13.60/valo/05,734.99,yes,locked 2006.145.19:15:13.60/valo/06,814.99,yes,locked 2006.145.19:15:13.60/valo/07,864.99,yes,locked 2006.145.19:15:13.60/valo/08,884.99,yes,locked 2006.145.19:15:14.69/vb/01,03,usb,yes,36,33 2006.145.19:15:14.69/vb/02,04,usb,yes,31,32 2006.145.19:15:14.69/vb/03,04,usb,yes,28,31 2006.145.19:15:14.69/vb/04,04,usb,yes,33,32 2006.145.19:15:14.69/vb/05,04,usb,yes,25,28 2006.145.19:15:14.69/vb/06,04,usb,yes,30,26 2006.145.19:15:14.69/vb/07,04,usb,yes,29,29 2006.145.19:15:14.69/vb/08,04,usb,yes,27,30 2006.145.19:15:14.92/vblo/01,629.99,yes,locked 2006.145.19:15:14.92/vblo/02,634.99,yes,locked 2006.145.19:15:14.92/vblo/03,649.99,yes,locked 2006.145.19:15:14.92/vblo/04,679.99,yes,locked 2006.145.19:15:14.92/vblo/05,709.99,yes,locked 2006.145.19:15:14.92/vblo/06,719.99,yes,locked 2006.145.19:15:14.92/vblo/07,734.99,yes,locked 2006.145.19:15:14.92/vblo/08,744.99,yes,locked 2006.145.19:15:15.07/vabw/8 2006.145.19:15:15.22/vbbw/8 2006.145.19:15:15.31/xfe/off,on,14.7 2006.145.19:15:15.71/ifatt/23,28,28,28 2006.145.19:15:16.07/fmout-gps/S +5.9E-08 2006.145.19:15:16.11:!2006.145.19:15:51 2006.145.19:15:51.00:data_valid=off 2006.145.19:15:51.00:"et 2006.145.19:15:51.01:!+3s 2006.145.19:15:54.02:"tape 2006.145.19:15:54.02:postob 2006.145.19:15:54.10/cable/+6.5508E-03 2006.145.19:15:54.11/wx/15.80,1019.9,87 2006.145.19:15:54.17/fmout-gps/S +5.8E-08 2006.145.19:15:54.17:scan_name=145-1916,jd0605,40 2006.145.19:15:54.18:source=3c454.3,225357.75,160853.6,2000.0,cw 2006.145.19:15:56.13#flagr#flagr/antenna,new-source 2006.145.19:15:56.13:checkk5 2006.145.19:15:56.56/chk_autoobs//k5ts1/ autoobs is running! 2006.145.19:15:57.00/chk_autoobs//k5ts2/ autoobs is running! 2006.145.19:15:57.45/chk_autoobs//k5ts3/ autoobs is running! 2006.145.19:15:57.88/chk_autoobs//k5ts4/ autoobs is running! 2006.145.19:15:58.30/chk_obsdata//k5ts1/T1451915??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.19:15:58.75/chk_obsdata//k5ts2/T1451915??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.19:15:59.20/chk_obsdata//k5ts3/T1451915??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.19:15:59.62/chk_obsdata//k5ts4/T1451915??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.19:16:00.39/k5log//k5ts1_log_newline 2006.145.19:16:01.12/k5log//k5ts2_log_newline 2006.145.19:16:01.85/k5log//k5ts3_log_newline 2006.145.19:16:02.62/k5log//k5ts4_log_newline 2006.145.19:16:02.64/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.19:16:02.64:setupk4=1 2006.145.19:16:02.64$setupk4/echo=on 2006.145.19:16:02.64$setupk4/pcalon 2006.145.19:16:02.64$pcalon/"no phase cal control is implemented here 2006.145.19:16:02.64$setupk4/"tpicd=stop 2006.145.19:16:02.64$setupk4/"rec=synch_on 2006.145.19:16:02.64$setupk4/"rec_mode=128 2006.145.19:16:02.64$setupk4/!* 2006.145.19:16:02.64$setupk4/recpk4 2006.145.19:16:02.64$recpk4/recpatch= 2006.145.19:16:02.64$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.19:16:02.64$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.19:16:02.65$setupk4/vck44 2006.145.19:16:02.65$vck44/valo=1,524.99 2006.145.19:16:02.65#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.19:16:02.65#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.19:16:02.65#ibcon#ireg 17 cls_cnt 0 2006.145.19:16:02.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:16:02.65#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:16:02.65#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:16:02.66#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.19:16:02.71#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:16:02.71#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:16:02.71#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.19:16:02.71#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.19:16:02.71$vck44/va=1,8 2006.145.19:16:02.71#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.19:16:02.71#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.19:16:02.71#ibcon#ireg 11 cls_cnt 2 2006.145.19:16:02.71#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:16:02.71#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:16:02.71#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:16:02.71#abcon#{5=INTERFACE CLEAR} 2006.145.19:16:02.73#ibcon#[25=AT01-08\r\n] 2006.145.19:16:02.76#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:16:02.76#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:16:02.76#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.19:16:02.76#ibcon#ireg 7 cls_cnt 0 2006.145.19:16:02.76#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:16:02.77#abcon#[5=S1D000X0/0*\r\n] 2006.145.19:16:02.88#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:16:02.88#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:16:02.90#ibcon#[25=USB\r\n] 2006.145.19:16:02.93#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:16:02.93#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:16:02.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.19:16:02.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.19:16:02.93$vck44/valo=2,534.99 2006.145.19:16:02.93#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.19:16:02.93#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.19:16:02.93#ibcon#ireg 17 cls_cnt 0 2006.145.19:16:02.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:16:02.93#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:16:02.93#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:16:02.96#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.19:16:03.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:16:03.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:16:03.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.19:16:03.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.19:16:03.00$vck44/va=2,7 2006.145.19:16:03.00#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.19:16:03.00#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.19:16:03.00#ibcon#ireg 11 cls_cnt 2 2006.145.19:16:03.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.19:16:03.05#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.19:16:03.05#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.19:16:03.07#ibcon#[25=AT02-07\r\n] 2006.145.19:16:03.10#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.19:16:03.10#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.19:16:03.10#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.19:16:03.10#ibcon#ireg 7 cls_cnt 0 2006.145.19:16:03.10#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.19:16:03.22#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.19:16:03.22#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.19:16:03.24#ibcon#[25=USB\r\n] 2006.145.19:16:03.27#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.19:16:03.27#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.19:16:03.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.19:16:03.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.19:16:03.27$vck44/valo=3,564.99 2006.145.19:16:03.27#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.19:16:03.27#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.19:16:03.27#ibcon#ireg 17 cls_cnt 0 2006.145.19:16:03.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:16:03.27#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:16:03.27#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:16:03.29#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.19:16:03.33#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:16:03.33#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:16:03.33#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.19:16:03.33#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.19:16:03.33$vck44/va=3,8 2006.145.19:16:03.33#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.19:16:03.33#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.19:16:03.33#ibcon#ireg 11 cls_cnt 2 2006.145.19:16:03.33#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:16:03.39#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:16:03.39#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:16:03.41#ibcon#[25=AT03-08\r\n] 2006.145.19:16:03.44#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:16:03.44#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:16:03.44#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.19:16:03.44#ibcon#ireg 7 cls_cnt 0 2006.145.19:16:03.44#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:16:03.56#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:16:03.56#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:16:03.58#ibcon#[25=USB\r\n] 2006.145.19:16:03.61#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:16:03.61#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:16:03.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.19:16:03.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.19:16:03.61$vck44/valo=4,624.99 2006.145.19:16:03.61#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.19:16:03.61#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.19:16:03.61#ibcon#ireg 17 cls_cnt 0 2006.145.19:16:03.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:16:03.61#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:16:03.61#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:16:03.63#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.19:16:03.67#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:16:03.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:16:03.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.19:16:03.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.19:16:03.67$vck44/va=4,7 2006.145.19:16:03.67#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.19:16:03.67#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.19:16:03.67#ibcon#ireg 11 cls_cnt 2 2006.145.19:16:03.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.19:16:03.73#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.19:16:03.73#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.19:16:03.75#ibcon#[25=AT04-07\r\n] 2006.145.19:16:03.78#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.19:16:03.78#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.19:16:03.78#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.19:16:03.78#ibcon#ireg 7 cls_cnt 0 2006.145.19:16:03.78#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.19:16:03.90#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.19:16:03.90#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.19:16:03.92#ibcon#[25=USB\r\n] 2006.145.19:16:03.95#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.19:16:03.95#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.19:16:03.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.19:16:03.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.19:16:03.95$vck44/valo=5,734.99 2006.145.19:16:03.95#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.19:16:03.95#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.19:16:03.95#ibcon#ireg 17 cls_cnt 0 2006.145.19:16:03.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.19:16:03.95#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.19:16:03.95#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.19:16:03.97#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.19:16:04.01#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.19:16:04.01#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.19:16:04.01#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.19:16:04.01#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.19:16:04.01$vck44/va=5,4 2006.145.19:16:04.01#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.19:16:04.01#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.19:16:04.01#ibcon#ireg 11 cls_cnt 2 2006.145.19:16:04.01#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.19:16:04.07#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.19:16:04.07#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.19:16:04.09#ibcon#[25=AT05-04\r\n] 2006.145.19:16:04.12#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.19:16:04.12#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.19:16:04.12#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.19:16:04.12#ibcon#ireg 7 cls_cnt 0 2006.145.19:16:04.12#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.19:16:04.26#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.19:16:04.26#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.19:16:04.28#ibcon#[25=USB\r\n] 2006.145.19:16:04.31#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.19:16:04.31#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.19:16:04.31#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.19:16:04.31#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.19:16:04.31$vck44/valo=6,814.99 2006.145.19:16:04.31#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.19:16:04.31#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.19:16:04.31#ibcon#ireg 17 cls_cnt 0 2006.145.19:16:04.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:16:04.31#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:16:04.31#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:16:04.33#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.19:16:04.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:16:04.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:16:04.37#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.19:16:04.37#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.19:16:04.37$vck44/va=6,4 2006.145.19:16:04.37#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.19:16:04.37#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.19:16:04.37#ibcon#ireg 11 cls_cnt 2 2006.145.19:16:04.37#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:16:04.43#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:16:04.43#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:16:04.45#ibcon#[25=AT06-04\r\n] 2006.145.19:16:04.48#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:16:04.48#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:16:04.48#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.19:16:04.48#ibcon#ireg 7 cls_cnt 0 2006.145.19:16:04.48#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:16:04.60#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:16:04.60#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:16:04.62#ibcon#[25=USB\r\n] 2006.145.19:16:04.65#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:16:04.65#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:16:04.65#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.19:16:04.65#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.19:16:04.65$vck44/valo=7,864.99 2006.145.19:16:04.65#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.19:16:04.65#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.19:16:04.65#ibcon#ireg 17 cls_cnt 0 2006.145.19:16:04.65#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:16:04.65#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:16:04.65#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:16:04.67#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.19:16:04.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:16:04.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:16:04.71#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.19:16:04.71#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.19:16:04.71$vck44/va=7,4 2006.145.19:16:04.71#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.19:16:04.71#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.19:16:04.71#ibcon#ireg 11 cls_cnt 2 2006.145.19:16:04.71#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:16:04.77#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:16:04.77#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:16:04.79#ibcon#[25=AT07-04\r\n] 2006.145.19:16:04.82#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:16:04.82#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:16:04.82#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.19:16:04.82#ibcon#ireg 7 cls_cnt 0 2006.145.19:16:04.82#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:16:04.94#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:16:04.94#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:16:04.96#ibcon#[25=USB\r\n] 2006.145.19:16:04.99#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:16:04.99#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:16:04.99#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.19:16:04.99#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.19:16:04.99$vck44/valo=8,884.99 2006.145.19:16:04.99#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.19:16:04.99#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.19:16:04.99#ibcon#ireg 17 cls_cnt 0 2006.145.19:16:04.99#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:16:04.99#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:16:04.99#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:16:05.01#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.19:16:05.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:16:05.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:16:05.05#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.19:16:05.05#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.19:16:05.05$vck44/va=8,4 2006.145.19:16:05.05#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.19:16:05.05#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.19:16:05.05#ibcon#ireg 11 cls_cnt 2 2006.145.19:16:05.05#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.19:16:05.11#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.19:16:05.11#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.19:16:05.13#ibcon#[25=AT08-04\r\n] 2006.145.19:16:05.16#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.19:16:05.16#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.19:16:05.16#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.19:16:05.16#ibcon#ireg 7 cls_cnt 0 2006.145.19:16:05.16#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.19:16:05.28#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.19:16:05.28#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.19:16:05.30#ibcon#[25=USB\r\n] 2006.145.19:16:05.33#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.19:16:05.33#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.19:16:05.33#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.19:16:05.33#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.19:16:05.33$vck44/vblo=1,629.99 2006.145.19:16:05.33#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.19:16:05.33#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.19:16:05.33#ibcon#ireg 17 cls_cnt 0 2006.145.19:16:05.33#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.19:16:05.33#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.19:16:05.33#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.19:16:05.35#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.19:16:05.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.19:16:05.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.19:16:05.39#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.19:16:05.39#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.19:16:05.39$vck44/vb=1,3 2006.145.19:16:05.39#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.19:16:05.39#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.19:16:05.39#ibcon#ireg 11 cls_cnt 2 2006.145.19:16:05.39#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.19:16:05.39#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.19:16:05.39#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.19:16:05.41#ibcon#[27=AT01-03\r\n] 2006.145.19:16:05.44#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.19:16:05.44#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.19:16:05.44#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.19:16:05.44#ibcon#ireg 7 cls_cnt 0 2006.145.19:16:05.44#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.19:16:05.56#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.19:16:05.56#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.19:16:05.58#ibcon#[27=USB\r\n] 2006.145.19:16:05.61#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.19:16:05.61#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.19:16:05.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.19:16:05.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.19:16:05.61$vck44/vblo=2,634.99 2006.145.19:16:05.61#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.19:16:05.61#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.19:16:05.61#ibcon#ireg 17 cls_cnt 0 2006.145.19:16:05.61#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.19:16:05.61#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.19:16:05.61#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.19:16:05.63#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.19:16:05.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.19:16:05.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.19:16:05.67#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.19:16:05.67#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.19:16:05.67$vck44/vb=2,4 2006.145.19:16:05.67#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.19:16:05.67#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.19:16:05.67#ibcon#ireg 11 cls_cnt 2 2006.145.19:16:05.67#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.19:16:05.73#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.19:16:05.73#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.19:16:05.75#ibcon#[27=AT02-04\r\n] 2006.145.19:16:05.78#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.19:16:05.78#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.19:16:05.78#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.19:16:05.78#ibcon#ireg 7 cls_cnt 0 2006.145.19:16:05.78#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.19:16:05.90#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.19:16:05.90#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.19:16:05.92#ibcon#[27=USB\r\n] 2006.145.19:16:05.95#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.19:16:05.95#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.19:16:05.95#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.19:16:05.95#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.19:16:05.95$vck44/vblo=3,649.99 2006.145.19:16:05.95#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.19:16:05.95#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.19:16:05.95#ibcon#ireg 17 cls_cnt 0 2006.145.19:16:05.95#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:16:05.95#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:16:05.95#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:16:05.97#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.19:16:06.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:16:06.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:16:06.01#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.19:16:06.01#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.19:16:06.01$vck44/vb=3,4 2006.145.19:16:06.01#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.19:16:06.01#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.19:16:06.01#ibcon#ireg 11 cls_cnt 2 2006.145.19:16:06.01#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.19:16:06.07#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.19:16:06.07#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.19:16:06.09#ibcon#[27=AT03-04\r\n] 2006.145.19:16:06.12#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.19:16:06.12#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.19:16:06.12#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.19:16:06.12#ibcon#ireg 7 cls_cnt 0 2006.145.19:16:06.12#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.19:16:06.24#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.19:16:06.24#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.19:16:06.26#ibcon#[27=USB\r\n] 2006.145.19:16:06.29#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.19:16:06.29#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.19:16:06.29#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.19:16:06.29#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.19:16:06.29$vck44/vblo=4,679.99 2006.145.19:16:06.29#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.19:16:06.29#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.19:16:06.29#ibcon#ireg 17 cls_cnt 0 2006.145.19:16:06.29#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:16:06.29#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:16:06.29#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:16:06.31#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.19:16:06.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:16:06.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:16:06.35#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.19:16:06.35#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.19:16:06.35$vck44/vb=4,4 2006.145.19:16:06.35#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.19:16:06.35#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.19:16:06.35#ibcon#ireg 11 cls_cnt 2 2006.145.19:16:06.35#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:16:06.41#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:16:06.41#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:16:06.43#ibcon#[27=AT04-04\r\n] 2006.145.19:16:06.46#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:16:06.46#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:16:06.46#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.19:16:06.46#ibcon#ireg 7 cls_cnt 0 2006.145.19:16:06.46#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:16:06.58#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:16:06.58#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:16:06.60#ibcon#[27=USB\r\n] 2006.145.19:16:06.63#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:16:06.63#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:16:06.63#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.19:16:06.63#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.19:16:06.63$vck44/vblo=5,709.99 2006.145.19:16:06.63#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.19:16:06.63#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.19:16:06.63#ibcon#ireg 17 cls_cnt 0 2006.145.19:16:06.63#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:16:06.63#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:16:06.63#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:16:06.65#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.19:16:06.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:16:06.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:16:06.69#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.19:16:06.69#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.19:16:06.69$vck44/vb=5,4 2006.145.19:16:06.69#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.19:16:06.69#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.19:16:06.69#ibcon#ireg 11 cls_cnt 2 2006.145.19:16:06.69#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.19:16:06.75#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.19:16:06.75#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.19:16:06.77#ibcon#[27=AT05-04\r\n] 2006.145.19:16:06.80#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.19:16:06.80#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.19:16:06.80#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.19:16:06.80#ibcon#ireg 7 cls_cnt 0 2006.145.19:16:06.80#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.19:16:06.92#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.19:16:06.92#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.19:16:06.94#ibcon#[27=USB\r\n] 2006.145.19:16:06.97#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.19:16:06.97#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.19:16:06.97#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.19:16:06.97#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.19:16:06.97$vck44/vblo=6,719.99 2006.145.19:16:06.97#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.19:16:06.97#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.19:16:06.97#ibcon#ireg 17 cls_cnt 0 2006.145.19:16:06.97#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.19:16:06.97#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.19:16:06.97#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.19:16:06.99#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.19:16:07.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.19:16:07.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.19:16:07.03#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.19:16:07.03#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.19:16:07.03$vck44/vb=6,4 2006.145.19:16:07.03#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.19:16:07.03#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.19:16:07.03#ibcon#ireg 11 cls_cnt 2 2006.145.19:16:07.03#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.19:16:07.09#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.19:16:07.09#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.19:16:07.11#ibcon#[27=AT06-04\r\n] 2006.145.19:16:07.14#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.19:16:07.14#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.19:16:07.14#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.19:16:07.14#ibcon#ireg 7 cls_cnt 0 2006.145.19:16:07.14#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.19:16:07.26#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.19:16:07.26#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.19:16:07.28#ibcon#[27=USB\r\n] 2006.145.19:16:07.31#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.19:16:07.31#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.19:16:07.31#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.19:16:07.31#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.19:16:07.31$vck44/vblo=7,734.99 2006.145.19:16:07.31#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.19:16:07.31#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.19:16:07.31#ibcon#ireg 17 cls_cnt 0 2006.145.19:16:07.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:16:07.31#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:16:07.31#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:16:07.33#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.19:16:07.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:16:07.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:16:07.37#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.19:16:07.37#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.19:16:07.37$vck44/vb=7,4 2006.145.19:16:07.37#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.19:16:07.37#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.19:16:07.37#ibcon#ireg 11 cls_cnt 2 2006.145.19:16:07.37#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:16:07.43#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:16:07.43#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:16:07.45#ibcon#[27=AT07-04\r\n] 2006.145.19:16:07.48#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:16:07.48#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:16:07.48#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.19:16:07.48#ibcon#ireg 7 cls_cnt 0 2006.145.19:16:07.48#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:16:07.60#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:16:07.60#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:16:07.62#ibcon#[27=USB\r\n] 2006.145.19:16:07.65#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:16:07.65#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:16:07.65#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.19:16:07.65#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.19:16:07.65$vck44/vblo=8,744.99 2006.145.19:16:07.65#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.19:16:07.65#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.19:16:07.65#ibcon#ireg 17 cls_cnt 0 2006.145.19:16:07.65#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:16:07.65#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:16:07.65#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:16:07.67#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.19:16:07.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:16:07.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:16:07.71#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.19:16:07.71#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.19:16:07.71$vck44/vb=8,4 2006.145.19:16:07.71#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.19:16:07.71#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.19:16:07.71#ibcon#ireg 11 cls_cnt 2 2006.145.19:16:07.71#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:16:07.77#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:16:07.77#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:16:07.79#ibcon#[27=AT08-04\r\n] 2006.145.19:16:07.82#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:16:07.82#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:16:07.82#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.19:16:07.82#ibcon#ireg 7 cls_cnt 0 2006.145.19:16:07.82#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:16:07.94#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:16:07.94#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:16:07.96#ibcon#[27=USB\r\n] 2006.145.19:16:07.99#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:16:07.99#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:16:07.99#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.19:16:07.99#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.19:16:07.99$vck44/vabw=wide 2006.145.19:16:07.99#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.19:16:07.99#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.19:16:07.99#ibcon#ireg 8 cls_cnt 0 2006.145.19:16:07.99#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:16:07.99#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:16:07.99#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:16:08.01#ibcon#[25=BW32\r\n] 2006.145.19:16:08.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:16:08.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:16:08.04#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.19:16:08.04#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.19:16:08.04$vck44/vbbw=wide 2006.145.19:16:08.04#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.19:16:08.04#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.19:16:08.04#ibcon#ireg 8 cls_cnt 0 2006.145.19:16:08.04#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.19:16:08.11#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.19:16:08.11#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.19:16:08.13#ibcon#[27=BW32\r\n] 2006.145.19:16:08.16#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.19:16:08.16#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.19:16:08.16#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.19:16:08.16#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.19:16:08.16$setupk4/ifdk4 2006.145.19:16:08.16$ifdk4/lo= 2006.145.19:16:08.16$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.19:16:08.16$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.19:16:08.16$ifdk4/patch= 2006.145.19:16:08.16$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.19:16:08.16$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.19:16:08.16$setupk4/!*+20s 2006.145.19:16:12.86#abcon#<5=/07 1.6 3.0 15.80 861019.9\r\n> 2006.145.19:16:12.88#abcon#{5=INTERFACE CLEAR} 2006.145.19:16:12.96#abcon#[5=S1D000X0/0*\r\n] 2006.145.19:16:19.13#trakl#Source acquired 2006.145.19:16:21.13#flagr#flagr/antenna,acquired 2006.145.19:16:22.65$setupk4/"tpicd 2006.145.19:16:22.65$setupk4/echo=off 2006.145.19:16:22.65$setupk4/xlog=off 2006.145.19:16:22.65:!2006.145.19:16:47 2006.145.19:16:47.00:preob 2006.145.19:16:47.13/onsource/TRACKING 2006.145.19:16:47.13:!2006.145.19:16:57 2006.145.19:16:57.00:"tape 2006.145.19:16:57.00:"st=record 2006.145.19:16:57.00:data_valid=on 2006.145.19:16:57.00:midob 2006.145.19:16:57.13/onsource/TRACKING 2006.145.19:16:57.13/wx/15.80,1019.8,87 2006.145.19:16:57.32/cable/+6.5502E-03 2006.145.19:16:58.41/va/01,08,usb,yes,29,31 2006.145.19:16:58.41/va/02,07,usb,yes,30,31 2006.145.19:16:58.41/va/03,08,usb,yes,28,29 2006.145.19:16:58.41/va/04,07,usb,yes,32,33 2006.145.19:16:58.41/va/05,04,usb,yes,27,28 2006.145.19:16:58.41/va/06,04,usb,yes,31,31 2006.145.19:16:58.41/va/07,04,usb,yes,31,32 2006.145.19:16:58.41/va/08,04,usb,yes,27,32 2006.145.19:16:58.64/valo/01,524.99,yes,locked 2006.145.19:16:58.64/valo/02,534.99,yes,locked 2006.145.19:16:58.64/valo/03,564.99,yes,locked 2006.145.19:16:58.64/valo/04,624.99,yes,locked 2006.145.19:16:58.64/valo/05,734.99,yes,locked 2006.145.19:16:58.64/valo/06,814.99,yes,locked 2006.145.19:16:58.64/valo/07,864.99,yes,locked 2006.145.19:16:58.64/valo/08,884.99,yes,locked 2006.145.19:16:59.73/vb/01,03,usb,yes,36,33 2006.145.19:16:59.73/vb/02,04,usb,yes,31,31 2006.145.19:16:59.73/vb/03,04,usb,yes,28,31 2006.145.19:16:59.73/vb/04,04,usb,yes,32,31 2006.145.19:16:59.73/vb/05,04,usb,yes,25,28 2006.145.19:16:59.73/vb/06,04,usb,yes,30,26 2006.145.19:16:59.73/vb/07,04,usb,yes,29,29 2006.145.19:16:59.73/vb/08,04,usb,yes,27,30 2006.145.19:16:59.96/vblo/01,629.99,yes,locked 2006.145.19:16:59.96/vblo/02,634.99,yes,locked 2006.145.19:16:59.96/vblo/03,649.99,yes,locked 2006.145.19:16:59.96/vblo/04,679.99,yes,locked 2006.145.19:16:59.96/vblo/05,709.99,yes,locked 2006.145.19:16:59.96/vblo/06,719.99,yes,locked 2006.145.19:16:59.96/vblo/07,734.99,yes,locked 2006.145.19:16:59.96/vblo/08,744.99,yes,locked 2006.145.19:17:00.11/vabw/8 2006.145.19:17:00.26/vbbw/8 2006.145.19:17:00.35/xfe/off,on,15.2 2006.145.19:17:00.73/ifatt/23,28,28,28 2006.145.19:17:01.07/fmout-gps/S +5.8E-08 2006.145.19:17:01.15:!2006.145.19:17:37 2006.145.19:17:37.00:data_valid=off 2006.145.19:17:37.00:"et 2006.145.19:17:37.01:!+3s 2006.145.19:17:40.02:"tape 2006.145.19:17:40.02:postob 2006.145.19:17:40.22/cable/+6.5505E-03 2006.145.19:17:40.22/wx/15.81,1019.9,87 2006.145.19:17:40.31/fmout-gps/S +5.7E-08 2006.145.19:17:40.31:scan_name=145-1918,jd0605,70 2006.145.19:17:40.31:source=2136+141,213901.31,142336.0,2000.0,cw 2006.145.19:17:42.13#flagr#flagr/antenna,new-source 2006.145.19:17:42.13:checkk5 2006.145.19:17:42.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.19:17:43.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.19:17:43.45/chk_autoobs//k5ts3/ autoobs is running! 2006.145.19:17:43.88/chk_autoobs//k5ts4/ autoobs is running! 2006.145.19:17:44.31/chk_obsdata//k5ts1/T1451916??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.19:17:44.77/chk_obsdata//k5ts2/T1451916??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.19:17:45.20/chk_obsdata//k5ts3/T1451916??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.19:17:45.64/chk_obsdata//k5ts4/T1451916??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.19:17:46.40/k5log//k5ts1_log_newline 2006.145.19:17:47.14/k5log//k5ts2_log_newline 2006.145.19:17:47.87/k5log//k5ts3_log_newline 2006.145.19:17:48.61/k5log//k5ts4_log_newline 2006.145.19:17:48.63/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.19:17:48.63:setupk4=1 2006.145.19:17:48.63$setupk4/echo=on 2006.145.19:17:48.63$setupk4/pcalon 2006.145.19:17:48.63$pcalon/"no phase cal control is implemented here 2006.145.19:17:48.63$setupk4/"tpicd=stop 2006.145.19:17:48.63$setupk4/"rec=synch_on 2006.145.19:17:48.63$setupk4/"rec_mode=128 2006.145.19:17:48.63$setupk4/!* 2006.145.19:17:48.63$setupk4/recpk4 2006.145.19:17:48.63$recpk4/recpatch= 2006.145.19:17:48.64$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.19:17:48.64$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.19:17:48.64$setupk4/vck44 2006.145.19:17:48.64$vck44/valo=1,524.99 2006.145.19:17:48.64#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.19:17:48.64#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.19:17:48.64#ibcon#ireg 17 cls_cnt 0 2006.145.19:17:48.64#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:17:48.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:17:48.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:17:48.68#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.19:17:48.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:17:48.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:17:48.72#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.19:17:48.72#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.19:17:48.72$vck44/va=1,8 2006.145.19:17:48.72#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.19:17:48.72#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.19:17:48.72#ibcon#ireg 11 cls_cnt 2 2006.145.19:17:48.72#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:17:48.72#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:17:48.72#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:17:48.74#ibcon#[25=AT01-08\r\n] 2006.145.19:17:48.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:17:48.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:17:48.77#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.19:17:48.77#ibcon#ireg 7 cls_cnt 0 2006.145.19:17:48.77#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:17:48.91#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:17:48.91#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:17:48.93#ibcon#[25=USB\r\n] 2006.145.19:17:48.96#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:17:48.96#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:17:48.96#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.19:17:48.96#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.19:17:48.96$vck44/valo=2,534.99 2006.145.19:17:48.96#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.19:17:48.96#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.19:17:48.96#ibcon#ireg 17 cls_cnt 0 2006.145.19:17:48.96#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:17:48.96#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:17:48.96#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:17:48.99#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.19:17:49.03#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:17:49.03#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:17:49.03#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.19:17:49.03#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.19:17:49.03$vck44/va=2,7 2006.145.19:17:49.03#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.19:17:49.03#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.19:17:49.03#ibcon#ireg 11 cls_cnt 2 2006.145.19:17:49.03#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:17:49.08#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:17:49.08#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:17:49.10#ibcon#[25=AT02-07\r\n] 2006.145.19:17:49.13#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:17:49.13#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:17:49.13#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.19:17:49.13#ibcon#ireg 7 cls_cnt 0 2006.145.19:17:49.13#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:17:49.25#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:17:49.25#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:17:49.27#ibcon#[25=USB\r\n] 2006.145.19:17:49.30#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:17:49.30#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:17:49.30#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.19:17:49.30#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.19:17:49.30$vck44/valo=3,564.99 2006.145.19:17:49.30#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.19:17:49.30#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.19:17:49.30#ibcon#ireg 17 cls_cnt 0 2006.145.19:17:49.30#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:17:49.30#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:17:49.30#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:17:49.32#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.19:17:49.36#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:17:49.36#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:17:49.36#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.19:17:49.36#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.19:17:49.36$vck44/va=3,8 2006.145.19:17:49.36#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.19:17:49.36#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.19:17:49.36#ibcon#ireg 11 cls_cnt 2 2006.145.19:17:49.36#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:17:49.42#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:17:49.42#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:17:49.44#ibcon#[25=AT03-08\r\n] 2006.145.19:17:49.47#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:17:49.47#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:17:49.47#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.19:17:49.47#ibcon#ireg 7 cls_cnt 0 2006.145.19:17:49.47#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:17:49.59#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:17:49.59#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:17:49.61#ibcon#[25=USB\r\n] 2006.145.19:17:49.64#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:17:49.64#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:17:49.64#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.19:17:49.64#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.19:17:49.64$vck44/valo=4,624.99 2006.145.19:17:49.64#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.19:17:49.64#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.19:17:49.64#ibcon#ireg 17 cls_cnt 0 2006.145.19:17:49.64#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:17:49.64#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:17:49.64#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:17:49.66#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.19:17:49.70#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:17:49.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:17:49.70#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.19:17:49.70#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.19:17:49.70$vck44/va=4,7 2006.145.19:17:49.70#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.19:17:49.70#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.19:17:49.70#ibcon#ireg 11 cls_cnt 2 2006.145.19:17:49.70#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:17:49.76#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:17:49.76#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:17:49.78#ibcon#[25=AT04-07\r\n] 2006.145.19:17:49.81#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:17:49.81#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:17:49.81#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.19:17:49.81#ibcon#ireg 7 cls_cnt 0 2006.145.19:17:49.81#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:17:49.93#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:17:49.93#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:17:49.95#ibcon#[25=USB\r\n] 2006.145.19:17:49.98#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:17:49.98#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:17:49.98#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.19:17:49.98#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.19:17:49.98$vck44/valo=5,734.99 2006.145.19:17:49.98#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.19:17:49.98#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.19:17:49.98#ibcon#ireg 17 cls_cnt 0 2006.145.19:17:49.98#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:17:49.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:17:49.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:17:50.01#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.19:17:50.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:17:50.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:17:50.05#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.19:17:50.05#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.19:17:50.05$vck44/va=5,4 2006.145.19:17:50.05#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.19:17:50.05#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.19:17:50.05#ibcon#ireg 11 cls_cnt 2 2006.145.19:17:50.05#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:17:50.11#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:17:50.11#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:17:50.13#ibcon#[25=AT05-04\r\n] 2006.145.19:17:50.16#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:17:50.16#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:17:50.16#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.19:17:50.16#ibcon#ireg 7 cls_cnt 0 2006.145.19:17:50.16#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:17:50.28#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:17:50.28#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:17:50.30#ibcon#[25=USB\r\n] 2006.145.19:17:50.33#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:17:50.33#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:17:50.33#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.19:17:50.33#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.19:17:50.33$vck44/valo=6,814.99 2006.145.19:17:50.33#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.19:17:50.33#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.19:17:50.33#ibcon#ireg 17 cls_cnt 0 2006.145.19:17:50.33#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:17:50.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:17:50.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:17:50.35#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.19:17:50.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:17:50.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:17:50.39#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.19:17:50.39#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.19:17:50.39$vck44/va=6,4 2006.145.19:17:50.39#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.19:17:50.39#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.19:17:50.39#ibcon#ireg 11 cls_cnt 2 2006.145.19:17:50.39#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.19:17:50.45#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.19:17:50.45#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.19:17:50.47#ibcon#[25=AT06-04\r\n] 2006.145.19:17:50.50#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.19:17:50.50#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.19:17:50.50#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.19:17:50.50#ibcon#ireg 7 cls_cnt 0 2006.145.19:17:50.50#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.19:17:50.62#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.19:17:50.62#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.19:17:50.64#ibcon#[25=USB\r\n] 2006.145.19:17:50.67#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.19:17:50.67#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.19:17:50.67#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.19:17:50.67#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.19:17:50.67$vck44/valo=7,864.99 2006.145.19:17:50.67#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.19:17:50.67#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.19:17:50.67#ibcon#ireg 17 cls_cnt 0 2006.145.19:17:50.67#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.19:17:50.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.19:17:50.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.19:17:50.69#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.19:17:50.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.19:17:50.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.19:17:50.73#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.19:17:50.73#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.19:17:50.73$vck44/va=7,4 2006.145.19:17:50.73#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.19:17:50.73#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.19:17:50.73#ibcon#ireg 11 cls_cnt 2 2006.145.19:17:50.73#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.19:17:50.79#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.19:17:50.79#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.19:17:50.81#ibcon#[25=AT07-04\r\n] 2006.145.19:17:50.84#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.19:17:50.84#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.19:17:50.84#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.19:17:50.84#ibcon#ireg 7 cls_cnt 0 2006.145.19:17:50.84#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.19:17:50.96#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.19:17:50.96#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.19:17:50.98#ibcon#[25=USB\r\n] 2006.145.19:17:51.01#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.19:17:51.01#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.19:17:51.01#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.19:17:51.01#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.19:17:51.01$vck44/valo=8,884.99 2006.145.19:17:51.01#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.19:17:51.01#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.19:17:51.01#ibcon#ireg 17 cls_cnt 0 2006.145.19:17:51.01#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.19:17:51.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.19:17:51.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.19:17:51.03#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.19:17:51.07#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.19:17:51.07#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.19:17:51.07#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.19:17:51.07#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.19:17:51.07$vck44/va=8,4 2006.145.19:17:51.07#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.19:17:51.07#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.19:17:51.07#ibcon#ireg 11 cls_cnt 2 2006.145.19:17:51.07#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.19:17:51.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.19:17:51.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.19:17:51.15#ibcon#[25=AT08-04\r\n] 2006.145.19:17:51.18#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.19:17:51.18#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.19:17:51.18#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.19:17:51.18#ibcon#ireg 7 cls_cnt 0 2006.145.19:17:51.18#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.19:17:51.30#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.19:17:51.30#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.19:17:51.32#ibcon#[25=USB\r\n] 2006.145.19:17:51.35#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.19:17:51.35#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.19:17:51.35#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.19:17:51.35#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.19:17:51.35$vck44/vblo=1,629.99 2006.145.19:17:51.35#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.19:17:51.35#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.19:17:51.35#ibcon#ireg 17 cls_cnt 0 2006.145.19:17:51.35#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.19:17:51.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.19:17:51.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.19:17:51.37#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.19:17:51.41#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.19:17:51.41#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.19:17:51.41#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.19:17:51.41#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.19:17:51.41$vck44/vb=1,3 2006.145.19:17:51.41#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.19:17:51.41#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.19:17:51.41#ibcon#ireg 11 cls_cnt 2 2006.145.19:17:51.41#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:17:51.41#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:17:51.41#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:17:51.43#ibcon#[27=AT01-03\r\n] 2006.145.19:17:51.46#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:17:51.46#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:17:51.46#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.19:17:51.46#ibcon#ireg 7 cls_cnt 0 2006.145.19:17:51.46#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:17:51.58#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:17:51.58#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:17:51.60#ibcon#[27=USB\r\n] 2006.145.19:17:51.63#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:17:51.63#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:17:51.63#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.19:17:51.63#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.19:17:51.63$vck44/vblo=2,634.99 2006.145.19:17:51.63#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.19:17:51.63#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.19:17:51.63#ibcon#ireg 17 cls_cnt 0 2006.145.19:17:51.63#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:17:51.63#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:17:51.63#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:17:51.65#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.19:17:51.69#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:17:51.69#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:17:51.69#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.19:17:51.69#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.19:17:51.69$vck44/vb=2,4 2006.145.19:17:51.69#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.19:17:51.69#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.19:17:51.69#ibcon#ireg 11 cls_cnt 2 2006.145.19:17:51.69#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:17:51.75#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:17:51.75#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:17:51.77#ibcon#[27=AT02-04\r\n] 2006.145.19:17:51.80#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:17:51.80#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:17:51.80#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.19:17:51.80#ibcon#ireg 7 cls_cnt 0 2006.145.19:17:51.80#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:17:51.92#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:17:51.92#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:17:51.94#ibcon#[27=USB\r\n] 2006.145.19:17:51.97#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:17:51.97#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:17:51.97#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.19:17:51.97#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.19:17:51.97$vck44/vblo=3,649.99 2006.145.19:17:51.97#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.19:17:51.97#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.19:17:51.97#ibcon#ireg 17 cls_cnt 0 2006.145.19:17:51.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:17:51.97#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:17:51.97#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:17:51.99#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.19:17:52.03#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:17:52.03#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:17:52.03#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.19:17:52.03#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.19:17:52.03$vck44/vb=3,4 2006.145.19:17:52.03#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.19:17:52.03#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.19:17:52.03#ibcon#ireg 11 cls_cnt 2 2006.145.19:17:52.03#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:17:52.09#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:17:52.09#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:17:52.11#ibcon#[27=AT03-04\r\n] 2006.145.19:17:52.14#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:17:52.14#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:17:52.14#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.19:17:52.14#ibcon#ireg 7 cls_cnt 0 2006.145.19:17:52.14#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:17:52.26#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:17:52.26#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:17:52.28#ibcon#[27=USB\r\n] 2006.145.19:17:52.31#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:17:52.31#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:17:52.31#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.19:17:52.31#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.19:17:52.31$vck44/vblo=4,679.99 2006.145.19:17:52.31#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.19:17:52.31#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.19:17:52.31#ibcon#ireg 17 cls_cnt 0 2006.145.19:17:52.31#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:17:52.31#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:17:52.31#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:17:52.33#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.19:17:52.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:17:52.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:17:52.37#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.19:17:52.37#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.19:17:52.37$vck44/vb=4,4 2006.145.19:17:52.37#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.19:17:52.37#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.19:17:52.37#ibcon#ireg 11 cls_cnt 2 2006.145.19:17:52.37#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:17:52.43#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:17:52.43#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:17:52.45#ibcon#[27=AT04-04\r\n] 2006.145.19:17:52.48#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:17:52.48#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:17:52.48#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.19:17:52.48#ibcon#ireg 7 cls_cnt 0 2006.145.19:17:52.48#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:17:52.60#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:17:52.60#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:17:52.62#ibcon#[27=USB\r\n] 2006.145.19:17:52.65#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:17:52.65#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:17:52.65#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.19:17:52.65#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.19:17:52.65$vck44/vblo=5,709.99 2006.145.19:17:52.65#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.19:17:52.65#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.19:17:52.65#ibcon#ireg 17 cls_cnt 0 2006.145.19:17:52.65#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:17:52.65#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:17:52.65#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:17:52.67#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.19:17:52.71#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:17:52.71#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:17:52.71#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.19:17:52.71#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.19:17:52.71$vck44/vb=5,4 2006.145.19:17:52.71#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.19:17:52.71#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.19:17:52.71#ibcon#ireg 11 cls_cnt 2 2006.145.19:17:52.71#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:17:52.77#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:17:52.77#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:17:52.79#ibcon#[27=AT05-04\r\n] 2006.145.19:17:52.82#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:17:52.82#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:17:52.82#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.19:17:52.82#ibcon#ireg 7 cls_cnt 0 2006.145.19:17:52.82#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:17:52.94#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:17:52.94#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:17:52.96#ibcon#[27=USB\r\n] 2006.145.19:17:52.99#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:17:52.99#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:17:52.99#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.19:17:52.99#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.19:17:52.99$vck44/vblo=6,719.99 2006.145.19:17:52.99#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.19:17:52.99#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.19:17:52.99#ibcon#ireg 17 cls_cnt 0 2006.145.19:17:52.99#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:17:52.99#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:17:52.99#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:17:53.01#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.19:17:53.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:17:53.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:17:53.05#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.19:17:53.05#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.19:17:53.05$vck44/vb=6,4 2006.145.19:17:53.05#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.19:17:53.05#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.19:17:53.05#ibcon#ireg 11 cls_cnt 2 2006.145.19:17:53.05#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:17:53.11#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:17:53.11#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:17:53.13#ibcon#[27=AT06-04\r\n] 2006.145.19:17:53.16#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:17:53.16#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:17:53.16#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.19:17:53.16#ibcon#ireg 7 cls_cnt 0 2006.145.19:17:53.16#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:17:53.28#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:17:53.28#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:17:53.30#ibcon#[27=USB\r\n] 2006.145.19:17:53.33#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:17:53.33#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:17:53.33#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.19:17:53.33#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.19:17:53.33$vck44/vblo=7,734.99 2006.145.19:17:53.33#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.19:17:53.33#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.19:17:53.33#ibcon#ireg 17 cls_cnt 0 2006.145.19:17:53.33#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:17:53.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:17:53.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:17:53.35#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.19:17:53.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:17:53.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:17:53.39#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.19:17:53.39#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.19:17:53.39$vck44/vb=7,4 2006.145.19:17:53.39#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.19:17:53.39#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.19:17:53.39#ibcon#ireg 11 cls_cnt 2 2006.145.19:17:53.39#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.19:17:53.45#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.19:17:53.45#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.19:17:53.47#ibcon#[27=AT07-04\r\n] 2006.145.19:17:53.50#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.19:17:53.50#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.19:17:53.50#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.19:17:53.50#ibcon#ireg 7 cls_cnt 0 2006.145.19:17:53.50#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.19:17:53.62#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.19:17:53.62#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.19:17:53.64#ibcon#[27=USB\r\n] 2006.145.19:17:53.67#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.19:17:53.67#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.19:17:53.67#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.19:17:53.67#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.19:17:53.67$vck44/vblo=8,744.99 2006.145.19:17:53.67#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.19:17:53.67#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.19:17:53.67#ibcon#ireg 17 cls_cnt 0 2006.145.19:17:53.67#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.19:17:53.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.19:17:53.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.19:17:53.69#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.19:17:53.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.19:17:53.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.19:17:53.73#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.19:17:53.73#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.19:17:53.73$vck44/vb=8,4 2006.145.19:17:53.73#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.19:17:53.73#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.19:17:53.73#ibcon#ireg 11 cls_cnt 2 2006.145.19:17:53.73#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.19:17:53.79#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.19:17:53.79#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.19:17:53.81#ibcon#[27=AT08-04\r\n] 2006.145.19:17:53.84#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.19:17:53.84#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.19:17:53.84#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.19:17:53.84#ibcon#ireg 7 cls_cnt 0 2006.145.19:17:53.84#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.19:17:53.96#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.19:17:53.96#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.19:17:53.98#ibcon#[27=USB\r\n] 2006.145.19:17:54.01#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.19:17:54.01#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.19:17:54.01#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.19:17:54.01#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.19:17:54.01$vck44/vabw=wide 2006.145.19:17:54.01#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.19:17:54.01#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.19:17:54.01#ibcon#ireg 8 cls_cnt 0 2006.145.19:17:54.01#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.19:17:54.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.19:17:54.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.19:17:54.03#ibcon#[25=BW32\r\n] 2006.145.19:17:54.06#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.19:17:54.06#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.19:17:54.06#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.19:17:54.06#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.19:17:54.06$vck44/vbbw=wide 2006.145.19:17:54.06#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.19:17:54.06#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.19:17:54.06#ibcon#ireg 8 cls_cnt 0 2006.145.19:17:54.06#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:17:54.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:17:54.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:17:54.15#ibcon#[27=BW32\r\n] 2006.145.19:17:54.18#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:17:54.18#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:17:54.18#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.19:17:54.18#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.19:17:54.18$setupk4/ifdk4 2006.145.19:17:54.18$ifdk4/lo= 2006.145.19:17:54.18$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.19:17:54.18$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.19:17:54.18$ifdk4/patch= 2006.145.19:17:54.18$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.19:17:54.18$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.19:17:54.18$setupk4/!*+20s 2006.145.19:17:54.60#abcon#<5=/07 1.5 2.6 15.81 871019.9\r\n> 2006.145.19:17:54.62#abcon#{5=INTERFACE CLEAR} 2006.145.19:17:54.68#abcon#[5=S1D000X0/0*\r\n] 2006.145.19:18:01.14#trakl#Source acquired 2006.145.19:18:01.14#flagr#flagr/antenna,acquired 2006.145.19:18:04.77#abcon#<5=/07 1.5 2.6 15.81 871019.9\r\n> 2006.145.19:18:04.79#abcon#{5=INTERFACE CLEAR} 2006.145.19:18:04.85#abcon#[5=S1D000X0/0*\r\n] 2006.145.19:18:08.64$setupk4/"tpicd 2006.145.19:18:08.64$setupk4/echo=off 2006.145.19:18:08.64$setupk4/xlog=off 2006.145.19:18:08.64:!2006.145.19:18:09 2006.145.19:18:09.00:preob 2006.145.19:18:09.14/onsource/TRACKING 2006.145.19:18:09.14:!2006.145.19:18:19 2006.145.19:18:19.00:"tape 2006.145.19:18:19.00:"st=record 2006.145.19:18:19.00:data_valid=on 2006.145.19:18:19.00:midob 2006.145.19:18:19.14/onsource/TRACKING 2006.145.19:18:19.14/wx/15.81,1019.9,87 2006.145.19:18:19.33/cable/+6.5511E-03 2006.145.19:18:20.42/va/01,08,usb,yes,28,30 2006.145.19:18:20.42/va/02,07,usb,yes,30,31 2006.145.19:18:20.42/va/03,08,usb,yes,27,28 2006.145.19:18:20.42/va/04,07,usb,yes,31,32 2006.145.19:18:20.42/va/05,04,usb,yes,27,27 2006.145.19:18:20.42/va/06,04,usb,yes,30,30 2006.145.19:18:20.42/va/07,04,usb,yes,30,32 2006.145.19:18:20.42/va/08,04,usb,yes,26,31 2006.145.19:18:20.65/valo/01,524.99,yes,locked 2006.145.19:18:20.65/valo/02,534.99,yes,locked 2006.145.19:18:20.65/valo/03,564.99,yes,locked 2006.145.19:18:20.65/valo/04,624.99,yes,locked 2006.145.19:18:20.65/valo/05,734.99,yes,locked 2006.145.19:18:20.65/valo/06,814.99,yes,locked 2006.145.19:18:20.65/valo/07,864.99,yes,locked 2006.145.19:18:20.65/valo/08,884.99,yes,locked 2006.145.19:18:21.74/vb/01,03,usb,yes,35,33 2006.145.19:18:21.74/vb/02,04,usb,yes,31,31 2006.145.19:18:21.74/vb/03,04,usb,yes,28,31 2006.145.19:18:21.74/vb/04,04,usb,yes,32,31 2006.145.19:18:21.74/vb/05,04,usb,yes,25,27 2006.145.19:18:21.74/vb/06,04,usb,yes,29,25 2006.145.19:18:21.74/vb/07,04,usb,yes,29,29 2006.145.19:18:21.74/vb/08,04,usb,yes,27,30 2006.145.19:18:21.97/vblo/01,629.99,yes,locked 2006.145.19:18:21.97/vblo/02,634.99,yes,locked 2006.145.19:18:21.97/vblo/03,649.99,yes,locked 2006.145.19:18:21.97/vblo/04,679.99,yes,locked 2006.145.19:18:21.97/vblo/05,709.99,yes,locked 2006.145.19:18:21.97/vblo/06,719.99,yes,locked 2006.145.19:18:21.97/vblo/07,734.99,yes,locked 2006.145.19:18:21.97/vblo/08,744.99,yes,locked 2006.145.19:18:22.12/vabw/8 2006.145.19:18:22.27/vbbw/8 2006.145.19:18:22.36/xfe/off,on,15.0 2006.145.19:18:22.75/ifatt/23,28,28,28 2006.145.19:18:23.07/fmout-gps/S +5.6E-08 2006.145.19:18:23.15:!2006.145.19:19:29 2006.145.19:19:29.00:data_valid=off 2006.145.19:19:29.00:"et 2006.145.19:19:29.01:!+3s 2006.145.19:19:32.02:"tape 2006.145.19:19:32.02:postob 2006.145.19:19:32.10/cable/+6.5486E-03 2006.145.19:19:32.10/wx/15.83,1019.9,87 2006.145.19:19:33.08/fmout-gps/S +5.6E-08 2006.145.19:19:33.08:scan_name=145-1923,jd0605,90 2006.145.19:19:33.09:source=1908-201,191109.65,-200655.1,2000.0,cw 2006.145.19:19:34.14#flagr#flagr/antenna,new-source 2006.145.19:19:34.14:checkk5 2006.145.19:19:34.57/chk_autoobs//k5ts1/ autoobs is running! 2006.145.19:19:34.99/chk_autoobs//k5ts2/ autoobs is running! 2006.145.19:19:35.43/chk_autoobs//k5ts3/ autoobs is running! 2006.145.19:19:35.86/chk_autoobs//k5ts4/ autoobs is running! 2006.145.19:19:36.28/chk_obsdata//k5ts1/T1451918??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.19:19:36.73/chk_obsdata//k5ts2/T1451918??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.19:19:37.18/chk_obsdata//k5ts3/T1451918??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.19:19:37.63/chk_obsdata//k5ts4/T1451918??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.19:19:38.37/k5log//k5ts1_log_newline 2006.145.19:19:39.12/k5log//k5ts2_log_newline 2006.145.19:19:39.87/k5log//k5ts3_log_newline 2006.145.19:19:40.62/k5log//k5ts4_log_newline 2006.145.19:19:40.64/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.19:19:40.64:setupk4=1 2006.145.19:19:40.64$setupk4/echo=on 2006.145.19:19:40.64$setupk4/pcalon 2006.145.19:19:40.65$pcalon/"no phase cal control is implemented here 2006.145.19:19:40.65$setupk4/"tpicd=stop 2006.145.19:19:40.65$setupk4/"rec=synch_on 2006.145.19:19:40.65$setupk4/"rec_mode=128 2006.145.19:19:40.65$setupk4/!* 2006.145.19:19:40.65$setupk4/recpk4 2006.145.19:19:40.65$recpk4/recpatch= 2006.145.19:19:40.65$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.19:19:40.65$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.19:19:40.65$setupk4/vck44 2006.145.19:19:40.65$vck44/valo=1,524.99 2006.145.19:19:40.65#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.19:19:40.65#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.19:19:40.65#ibcon#ireg 17 cls_cnt 0 2006.145.19:19:40.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.19:19:40.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.19:19:40.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.19:19:40.69#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.19:19:40.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.19:19:40.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.19:19:40.74#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.19:19:40.74#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.19:19:40.74$vck44/va=1,8 2006.145.19:19:40.74#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.19:19:40.74#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.19:19:40.74#ibcon#ireg 11 cls_cnt 2 2006.145.19:19:40.74#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.19:19:40.74#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.19:19:40.74#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.19:19:40.76#ibcon#[25=AT01-08\r\n] 2006.145.19:19:40.79#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.19:19:40.79#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.19:19:40.79#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.19:19:40.79#ibcon#ireg 7 cls_cnt 0 2006.145.19:19:40.79#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.19:19:40.91#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.19:19:40.91#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.19:19:40.93#ibcon#[25=USB\r\n] 2006.145.19:19:40.96#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.19:19:40.96#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.19:19:40.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.19:19:40.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.19:19:40.96$vck44/valo=2,534.99 2006.145.19:19:40.96#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.19:19:40.96#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.19:19:40.96#ibcon#ireg 17 cls_cnt 0 2006.145.19:19:40.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.19:19:40.96#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.19:19:40.96#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.19:19:40.98#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.19:19:41.02#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.19:19:41.02#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.19:19:41.02#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.19:19:41.02#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.19:19:41.02$vck44/va=2,7 2006.145.19:19:41.02#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.19:19:41.02#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.19:19:41.02#ibcon#ireg 11 cls_cnt 2 2006.145.19:19:41.02#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.19:19:41.08#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.19:19:41.08#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.19:19:41.10#ibcon#[25=AT02-07\r\n] 2006.145.19:19:41.13#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.19:19:41.13#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.19:19:41.13#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.19:19:41.13#ibcon#ireg 7 cls_cnt 0 2006.145.19:19:41.13#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.19:19:41.25#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.19:19:41.25#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.19:19:41.27#ibcon#[25=USB\r\n] 2006.145.19:19:41.30#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.19:19:41.30#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.19:19:41.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.19:19:41.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.19:19:41.30$vck44/valo=3,564.99 2006.145.19:19:41.30#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.19:19:41.30#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.19:19:41.30#ibcon#ireg 17 cls_cnt 0 2006.145.19:19:41.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.19:19:41.30#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.19:19:41.30#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.19:19:41.32#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.19:19:41.36#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.19:19:41.36#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.19:19:41.36#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.19:19:41.36#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.19:19:41.36$vck44/va=3,8 2006.145.19:19:41.36#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.19:19:41.36#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.19:19:41.36#ibcon#ireg 11 cls_cnt 2 2006.145.19:19:41.36#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.19:19:41.42#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.19:19:41.42#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.19:19:41.44#ibcon#[25=AT03-08\r\n] 2006.145.19:19:41.47#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.19:19:41.47#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.19:19:41.47#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.19:19:41.47#ibcon#ireg 7 cls_cnt 0 2006.145.19:19:41.47#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.19:19:41.59#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.19:19:41.59#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.19:19:41.61#ibcon#[25=USB\r\n] 2006.145.19:19:41.64#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.19:19:41.64#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.19:19:41.64#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.19:19:41.64#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.19:19:41.64$vck44/valo=4,624.99 2006.145.19:19:41.64#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.19:19:41.64#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.19:19:41.64#ibcon#ireg 17 cls_cnt 0 2006.145.19:19:41.64#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.19:19:41.64#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.19:19:41.64#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.19:19:41.66#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.19:19:41.70#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.19:19:41.70#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.19:19:41.70#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.19:19:41.70#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.19:19:41.70$vck44/va=4,7 2006.145.19:19:41.70#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.19:19:41.70#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.19:19:41.70#ibcon#ireg 11 cls_cnt 2 2006.145.19:19:41.70#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.19:19:41.76#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.19:19:41.76#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.19:19:41.78#ibcon#[25=AT04-07\r\n] 2006.145.19:19:41.81#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.19:19:41.81#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.19:19:41.81#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.19:19:41.81#ibcon#ireg 7 cls_cnt 0 2006.145.19:19:41.81#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.19:19:41.93#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.19:19:41.93#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.19:19:41.96#ibcon#[25=USB\r\n] 2006.145.19:19:41.99#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.19:19:41.99#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.19:19:41.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.19:19:41.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.19:19:41.99$vck44/valo=5,734.99 2006.145.19:19:41.99#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.19:19:41.99#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.19:19:41.99#ibcon#ireg 17 cls_cnt 0 2006.145.19:19:41.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.19:19:41.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.19:19:41.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.19:19:42.01#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.19:19:42.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.19:19:42.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.19:19:42.05#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.19:19:42.05#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.19:19:42.05$vck44/va=5,4 2006.145.19:19:42.05#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.19:19:42.05#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.19:19:42.05#ibcon#ireg 11 cls_cnt 2 2006.145.19:19:42.05#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.19:19:42.11#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.19:19:42.11#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.19:19:42.14#ibcon#[25=AT05-04\r\n] 2006.145.19:19:42.17#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.19:19:42.17#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.19:19:42.17#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.19:19:42.17#ibcon#ireg 7 cls_cnt 0 2006.145.19:19:42.17#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.19:19:42.29#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.19:19:42.29#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.19:19:42.31#ibcon#[25=USB\r\n] 2006.145.19:19:42.34#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.19:19:42.34#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.19:19:42.34#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.19:19:42.34#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.19:19:42.34$vck44/valo=6,814.99 2006.145.19:19:42.34#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.19:19:42.34#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.19:19:42.34#ibcon#ireg 17 cls_cnt 0 2006.145.19:19:42.34#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.19:19:42.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.19:19:42.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.19:19:42.36#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.19:19:42.40#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.19:19:42.40#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.19:19:42.40#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.19:19:42.40#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.19:19:42.40$vck44/va=6,4 2006.145.19:19:42.40#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.19:19:42.40#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.19:19:42.40#ibcon#ireg 11 cls_cnt 2 2006.145.19:19:42.40#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.19:19:42.46#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.19:19:42.46#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.19:19:42.48#ibcon#[25=AT06-04\r\n] 2006.145.19:19:42.51#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.19:19:42.51#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.19:19:42.51#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.19:19:42.51#ibcon#ireg 7 cls_cnt 0 2006.145.19:19:42.51#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.19:19:42.63#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.19:19:42.63#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.19:19:42.65#ibcon#[25=USB\r\n] 2006.145.19:19:42.68#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.19:19:42.68#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.19:19:42.68#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.19:19:42.68#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.19:19:42.68$vck44/valo=7,864.99 2006.145.19:19:42.68#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.19:19:42.68#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.19:19:42.68#ibcon#ireg 17 cls_cnt 0 2006.145.19:19:42.68#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.19:19:42.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.19:19:42.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.19:19:42.70#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.19:19:42.74#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.19:19:42.74#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.19:19:42.74#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.19:19:42.74#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.19:19:42.74$vck44/va=7,4 2006.145.19:19:42.74#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.19:19:42.74#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.19:19:42.74#ibcon#ireg 11 cls_cnt 2 2006.145.19:19:42.74#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.19:19:42.80#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.19:19:42.80#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.19:19:42.82#ibcon#[25=AT07-04\r\n] 2006.145.19:19:42.85#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.19:19:42.85#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.19:19:42.85#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.19:19:42.85#ibcon#ireg 7 cls_cnt 0 2006.145.19:19:42.85#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.19:19:42.97#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.19:19:42.97#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.19:19:42.99#ibcon#[25=USB\r\n] 2006.145.19:19:43.02#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.19:19:43.02#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.19:19:43.02#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.19:19:43.02#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.19:19:43.02$vck44/valo=8,884.99 2006.145.19:19:43.02#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.19:19:43.02#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.19:19:43.02#ibcon#ireg 17 cls_cnt 0 2006.145.19:19:43.02#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.19:19:43.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.19:19:43.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.19:19:43.04#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.19:19:43.08#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.19:19:43.08#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.19:19:43.08#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.19:19:43.08#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.19:19:43.08$vck44/va=8,4 2006.145.19:19:43.08#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.19:19:43.08#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.19:19:43.08#ibcon#ireg 11 cls_cnt 2 2006.145.19:19:43.08#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.19:19:43.14#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.19:19:43.14#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.19:19:43.16#ibcon#[25=AT08-04\r\n] 2006.145.19:19:43.19#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.19:19:43.19#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.19:19:43.19#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.19:19:43.19#ibcon#ireg 7 cls_cnt 0 2006.145.19:19:43.19#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.19:19:43.31#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.19:19:43.31#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.19:19:43.33#ibcon#[25=USB\r\n] 2006.145.19:19:43.36#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.19:19:43.36#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.19:19:43.36#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.19:19:43.36#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.19:19:43.36$vck44/vblo=1,629.99 2006.145.19:19:43.36#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.19:19:43.36#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.19:19:43.36#ibcon#ireg 17 cls_cnt 0 2006.145.19:19:43.36#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.19:19:43.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.19:19:43.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.19:19:43.38#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.19:19:43.42#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.19:19:43.42#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.19:19:43.42#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.19:19:43.42#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.19:19:43.42$vck44/vb=1,3 2006.145.19:19:43.42#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.19:19:43.42#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.19:19:43.42#ibcon#ireg 11 cls_cnt 2 2006.145.19:19:43.42#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.19:19:43.42#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.19:19:43.42#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.19:19:43.44#ibcon#[27=AT01-03\r\n] 2006.145.19:19:43.47#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.19:19:43.47#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.19:19:43.47#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.19:19:43.47#ibcon#ireg 7 cls_cnt 0 2006.145.19:19:43.47#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.19:19:43.59#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.19:19:43.59#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.19:19:43.61#ibcon#[27=USB\r\n] 2006.145.19:19:43.64#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.19:19:43.64#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.19:19:43.64#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.19:19:43.64#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.19:19:43.64$vck44/vblo=2,634.99 2006.145.19:19:43.64#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.19:19:43.64#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.19:19:43.64#ibcon#ireg 17 cls_cnt 0 2006.145.19:19:43.64#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.19:19:43.64#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.19:19:43.64#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.19:19:43.66#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.19:19:43.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.19:19:43.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.19:19:43.70#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.19:19:43.70#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.19:19:43.70$vck44/vb=2,4 2006.145.19:19:43.70#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.19:19:43.70#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.19:19:43.70#ibcon#ireg 11 cls_cnt 2 2006.145.19:19:43.70#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.19:19:43.76#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.19:19:43.76#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.19:19:43.78#ibcon#[27=AT02-04\r\n] 2006.145.19:19:43.81#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.19:19:43.81#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.19:19:43.81#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.19:19:43.81#ibcon#ireg 7 cls_cnt 0 2006.145.19:19:43.81#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.19:19:43.93#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.19:19:43.93#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.19:19:43.95#ibcon#[27=USB\r\n] 2006.145.19:19:43.98#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.19:19:43.98#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.19:19:43.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.19:19:43.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.19:19:43.98$vck44/vblo=3,649.99 2006.145.19:19:43.98#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.19:19:43.98#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.19:19:43.98#ibcon#ireg 17 cls_cnt 0 2006.145.19:19:43.98#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.19:19:43.98#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.19:19:43.98#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.19:19:44.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.19:19:44.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.19:19:44.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.19:19:44.04#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.19:19:44.04#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.19:19:44.04$vck44/vb=3,4 2006.145.19:19:44.04#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.19:19:44.04#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.19:19:44.04#ibcon#ireg 11 cls_cnt 2 2006.145.19:19:44.04#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.19:19:44.10#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.19:19:44.10#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.19:19:44.12#ibcon#[27=AT03-04\r\n] 2006.145.19:19:44.15#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.19:19:44.15#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.19:19:44.15#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.19:19:44.15#ibcon#ireg 7 cls_cnt 0 2006.145.19:19:44.15#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.19:19:44.27#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.19:19:44.27#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.19:19:44.29#ibcon#[27=USB\r\n] 2006.145.19:19:44.32#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.19:19:44.32#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.19:19:44.32#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.19:19:44.32#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.19:19:44.32$vck44/vblo=4,679.99 2006.145.19:19:44.32#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.19:19:44.32#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.19:19:44.32#ibcon#ireg 17 cls_cnt 0 2006.145.19:19:44.32#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.19:19:44.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.19:19:44.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.19:19:44.34#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.19:19:44.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.19:19:44.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.19:19:44.38#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.19:19:44.38#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.19:19:44.38$vck44/vb=4,4 2006.145.19:19:44.38#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.19:19:44.38#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.19:19:44.38#ibcon#ireg 11 cls_cnt 2 2006.145.19:19:44.38#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.19:19:44.44#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.19:19:44.44#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.19:19:44.46#ibcon#[27=AT04-04\r\n] 2006.145.19:19:44.49#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.19:19:44.49#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.19:19:44.49#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.19:19:44.49#ibcon#ireg 7 cls_cnt 0 2006.145.19:19:44.49#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.19:19:44.61#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.19:19:44.61#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.19:19:44.63#ibcon#[27=USB\r\n] 2006.145.19:19:44.66#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.19:19:44.66#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.19:19:44.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.19:19:44.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.19:19:44.66$vck44/vblo=5,709.99 2006.145.19:19:44.66#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.19:19:44.66#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.19:19:44.66#ibcon#ireg 17 cls_cnt 0 2006.145.19:19:44.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.19:19:44.66#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.19:19:44.66#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.19:19:44.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.19:19:44.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.19:19:44.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.19:19:44.72#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.19:19:44.72#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.19:19:44.72$vck44/vb=5,4 2006.145.19:19:44.72#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.19:19:44.72#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.19:19:44.72#ibcon#ireg 11 cls_cnt 2 2006.145.19:19:44.72#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.19:19:44.78#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.19:19:44.78#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.19:19:44.80#ibcon#[27=AT05-04\r\n] 2006.145.19:19:44.83#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.19:19:44.83#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.19:19:44.83#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.19:19:44.83#ibcon#ireg 7 cls_cnt 0 2006.145.19:19:44.83#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.19:19:44.95#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.19:19:44.95#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.19:19:44.97#ibcon#[27=USB\r\n] 2006.145.19:19:45.00#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.19:19:45.00#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.19:19:45.00#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.19:19:45.00#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.19:19:45.00$vck44/vblo=6,719.99 2006.145.19:19:45.00#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.19:19:45.00#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.19:19:45.00#ibcon#ireg 17 cls_cnt 0 2006.145.19:19:45.00#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.19:19:45.00#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.19:19:45.00#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.19:19:45.02#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.19:19:45.06#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.19:19:45.06#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.19:19:45.06#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.19:19:45.06#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.19:19:45.06$vck44/vb=6,4 2006.145.19:19:45.06#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.19:19:45.06#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.19:19:45.06#ibcon#ireg 11 cls_cnt 2 2006.145.19:19:45.06#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.19:19:45.12#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.19:19:45.12#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.19:19:45.14#ibcon#[27=AT06-04\r\n] 2006.145.19:19:45.17#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.19:19:45.17#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.19:19:45.17#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.19:19:45.17#ibcon#ireg 7 cls_cnt 0 2006.145.19:19:45.17#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.19:19:45.29#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.19:19:45.29#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.19:19:45.31#ibcon#[27=USB\r\n] 2006.145.19:19:45.34#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.19:19:45.34#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.19:19:45.34#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.19:19:45.34#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.19:19:45.34$vck44/vblo=7,734.99 2006.145.19:19:45.34#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.19:19:45.34#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.19:19:45.34#ibcon#ireg 17 cls_cnt 0 2006.145.19:19:45.34#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.19:19:45.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.19:19:45.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.19:19:45.36#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.19:19:45.40#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.19:19:45.40#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.19:19:45.40#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.19:19:45.40#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.19:19:45.40$vck44/vb=7,4 2006.145.19:19:45.40#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.19:19:45.40#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.19:19:45.40#ibcon#ireg 11 cls_cnt 2 2006.145.19:19:45.40#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.19:19:45.46#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.19:19:45.46#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.19:19:45.48#ibcon#[27=AT07-04\r\n] 2006.145.19:19:45.51#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.19:19:45.51#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.19:19:45.51#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.19:19:45.51#ibcon#ireg 7 cls_cnt 0 2006.145.19:19:45.51#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.19:19:45.63#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.19:19:45.63#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.19:19:45.65#ibcon#[27=USB\r\n] 2006.145.19:19:45.68#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.19:19:45.68#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.19:19:45.68#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.19:19:45.68#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.19:19:45.68$vck44/vblo=8,744.99 2006.145.19:19:45.68#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.19:19:45.68#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.19:19:45.68#ibcon#ireg 17 cls_cnt 0 2006.145.19:19:45.68#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.19:19:45.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.19:19:45.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.19:19:45.70#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.19:19:45.74#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.19:19:45.74#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.19:19:45.74#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.19:19:45.74#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.19:19:45.74$vck44/vb=8,4 2006.145.19:19:45.74#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.19:19:45.74#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.19:19:45.74#ibcon#ireg 11 cls_cnt 2 2006.145.19:19:45.74#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.19:19:45.80#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.19:19:45.80#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.19:19:45.82#ibcon#[27=AT08-04\r\n] 2006.145.19:19:45.85#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.19:19:45.85#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.19:19:45.85#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.19:19:45.85#ibcon#ireg 7 cls_cnt 0 2006.145.19:19:45.85#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.19:19:45.97#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.19:19:45.97#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.19:19:45.99#ibcon#[27=USB\r\n] 2006.145.19:19:46.02#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.19:19:46.02#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.19:19:46.02#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.19:19:46.02#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.19:19:46.02$vck44/vabw=wide 2006.145.19:19:46.02#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.19:19:46.02#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.19:19:46.02#ibcon#ireg 8 cls_cnt 0 2006.145.19:19:46.02#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.19:19:46.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.19:19:46.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.19:19:46.04#ibcon#[25=BW32\r\n] 2006.145.19:19:46.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.19:19:46.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.19:19:46.07#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.19:19:46.07#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.19:19:46.07$vck44/vbbw=wide 2006.145.19:19:46.07#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.19:19:46.07#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.19:19:46.07#ibcon#ireg 8 cls_cnt 0 2006.145.19:19:46.07#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:19:46.14#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:19:46.14#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:19:46.16#ibcon#[27=BW32\r\n] 2006.145.19:19:46.19#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:19:46.19#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:19:46.19#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.19:19:46.19#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.19:19:46.19$setupk4/ifdk4 2006.145.19:19:46.19$ifdk4/lo= 2006.145.19:19:46.19$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.19:19:46.19$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.19:19:46.19$ifdk4/patch= 2006.145.19:19:46.19$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.19:19:46.19$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.19:19:46.19$setupk4/!*+20s 2006.145.19:19:46.47#abcon#<5=/07 1.4 2.6 15.83 861019.9\r\n> 2006.145.19:19:46.49#abcon#{5=INTERFACE CLEAR} 2006.145.19:19:46.55#abcon#[5=S1D000X0/0*\r\n] 2006.145.19:19:56.64#abcon#<5=/07 1.4 2.6 15.83 861019.9\r\n> 2006.145.19:19:56.66#abcon#{5=INTERFACE CLEAR} 2006.145.19:19:56.72#abcon#[5=S1D000X0/0*\r\n] 2006.145.19:20:00.66$setupk4/"tpicd 2006.145.19:20:00.66$setupk4/echo=off 2006.145.19:20:00.66$setupk4/xlog=off 2006.145.19:20:00.66:!2006.145.19:23:05 2006.145.19:20:01.14#trakl#Source acquired 2006.145.19:20:02.14#flagr#flagr/antenna,acquired 2006.145.19:23:05.00:preob 2006.145.19:23:06.14/onsource/TRACKING 2006.145.19:23:06.14:!2006.145.19:23:15 2006.145.19:23:15.00:"tape 2006.145.19:23:15.00:"st=record 2006.145.19:23:15.00:data_valid=on 2006.145.19:23:15.00:midob 2006.145.19:23:15.14/onsource/TRACKING 2006.145.19:23:15.14/wx/15.84,1020.0,87 2006.145.19:23:15.32/cable/+6.5502E-03 2006.145.19:23:16.41/va/01,08,usb,yes,29,31 2006.145.19:23:16.41/va/02,07,usb,yes,31,32 2006.145.19:23:16.41/va/03,08,usb,yes,28,30 2006.145.19:23:16.41/va/04,07,usb,yes,32,34 2006.145.19:23:16.41/va/05,04,usb,yes,28,29 2006.145.19:23:16.41/va/06,04,usb,yes,32,31 2006.145.19:23:16.41/va/07,04,usb,yes,32,33 2006.145.19:23:16.41/va/08,04,usb,yes,27,33 2006.145.19:23:16.64/valo/01,524.99,yes,locked 2006.145.19:23:16.64/valo/02,534.99,yes,locked 2006.145.19:23:16.64/valo/03,564.99,yes,locked 2006.145.19:23:16.64/valo/04,624.99,yes,locked 2006.145.19:23:16.64/valo/05,734.99,yes,locked 2006.145.19:23:16.64/valo/06,814.99,yes,locked 2006.145.19:23:16.64/valo/07,864.99,yes,locked 2006.145.19:23:16.64/valo/08,884.99,yes,locked 2006.145.19:23:17.73/vb/01,03,usb,yes,37,34 2006.145.19:23:17.73/vb/02,04,usb,yes,32,32 2006.145.19:23:17.73/vb/03,04,usb,yes,29,32 2006.145.19:23:17.73/vb/04,04,usb,yes,33,32 2006.145.19:23:17.73/vb/05,04,usb,yes,26,28 2006.145.19:23:17.73/vb/06,04,usb,yes,30,27 2006.145.19:23:17.73/vb/07,04,usb,yes,30,30 2006.145.19:23:17.73/vb/08,04,usb,yes,28,31 2006.145.19:23:17.96/vblo/01,629.99,yes,locked 2006.145.19:23:17.96/vblo/02,634.99,yes,locked 2006.145.19:23:17.96/vblo/03,649.99,yes,locked 2006.145.19:23:17.96/vblo/04,679.99,yes,locked 2006.145.19:23:17.96/vblo/05,709.99,yes,locked 2006.145.19:23:17.96/vblo/06,719.99,yes,locked 2006.145.19:23:17.96/vblo/07,734.99,yes,locked 2006.145.19:23:17.96/vblo/08,744.99,yes,locked 2006.145.19:23:18.11/vabw/8 2006.145.19:23:18.26/vbbw/8 2006.145.19:23:18.35/xfe/off,on,15.2 2006.145.19:23:18.72/ifatt/23,28,28,28 2006.145.19:23:19.08/fmout-gps/S +5.5E-08 2006.145.19:23:19.12:!2006.145.19:24:45 2006.145.19:24:45.00:data_valid=off 2006.145.19:24:45.00:"et 2006.145.19:24:45.00:!+3s 2006.145.19:24:48.02:"tape 2006.145.19:24:48.02:postob 2006.145.19:24:48.20/cable/+6.5503E-03 2006.145.19:24:48.20/wx/15.84,1019.9,87 2006.145.19:24:49.08/fmout-gps/S +5.5E-08 2006.145.19:24:49.08:scan_name=145-1929,jd0605,40 2006.145.19:24:49.09:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.145.19:24:49.13#flagr#flagr/antenna,new-source 2006.145.19:24:50.13:checkk5 2006.145.19:24:50.53/chk_autoobs//k5ts1/ autoobs is running! 2006.145.19:24:50.97/chk_autoobs//k5ts2/ autoobs is running! 2006.145.19:24:51.41/chk_autoobs//k5ts3/ autoobs is running! 2006.145.19:24:51.84/chk_autoobs//k5ts4/ autoobs is running! 2006.145.19:24:52.26/chk_obsdata//k5ts1/T1451923??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.19:24:52.70/chk_obsdata//k5ts2/T1451923??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.19:24:53.14/chk_obsdata//k5ts3/T1451923??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.19:24:53.58/chk_obsdata//k5ts4/T1451923??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.145.19:24:54.33/k5log//k5ts1_log_newline 2006.145.19:24:55.08/k5log//k5ts2_log_newline 2006.145.19:24:55.83/k5log//k5ts3_log_newline 2006.145.19:24:56.59/k5log//k5ts4_log_newline 2006.145.19:24:56.61/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.19:24:56.61:setupk4=1 2006.145.19:24:56.61$setupk4/echo=on 2006.145.19:24:56.61$setupk4/pcalon 2006.145.19:24:56.61$pcalon/"no phase cal control is implemented here 2006.145.19:24:56.61$setupk4/"tpicd=stop 2006.145.19:24:56.61$setupk4/"rec=synch_on 2006.145.19:24:56.62$setupk4/"rec_mode=128 2006.145.19:24:56.62$setupk4/!* 2006.145.19:24:56.62$setupk4/recpk4 2006.145.19:24:56.62$recpk4/recpatch= 2006.145.19:24:56.62$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.19:24:56.62$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.19:24:56.62$setupk4/vck44 2006.145.19:24:56.62$vck44/valo=1,524.99 2006.145.19:24:56.62#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.19:24:56.62#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.19:24:56.62#ibcon#ireg 17 cls_cnt 0 2006.145.19:24:56.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:24:56.62#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:24:56.62#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:24:56.66#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.19:24:56.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:24:56.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:24:56.71#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.19:24:56.71#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.19:24:56.71$vck44/va=1,8 2006.145.19:24:56.71#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.19:24:56.71#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.19:24:56.71#ibcon#ireg 11 cls_cnt 2 2006.145.19:24:56.71#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:24:56.71#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:24:56.71#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:24:56.73#ibcon#[25=AT01-08\r\n] 2006.145.19:24:56.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:24:56.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:24:56.76#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.19:24:56.76#ibcon#ireg 7 cls_cnt 0 2006.145.19:24:56.76#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:24:56.88#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:24:56.88#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:24:56.90#ibcon#[25=USB\r\n] 2006.145.19:24:56.93#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:24:56.93#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:24:56.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.19:24:56.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.19:24:56.93$vck44/valo=2,534.99 2006.145.19:24:56.93#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.19:24:56.93#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.19:24:56.93#ibcon#ireg 17 cls_cnt 0 2006.145.19:24:56.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:24:56.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:24:56.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:24:56.96#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.19:24:57.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:24:57.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:24:57.00#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.19:24:57.00#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.19:24:57.00$vck44/va=2,7 2006.145.19:24:57.00#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.19:24:57.00#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.19:24:57.00#ibcon#ireg 11 cls_cnt 2 2006.145.19:24:57.00#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:24:57.05#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:24:57.05#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:24:57.07#ibcon#[25=AT02-07\r\n] 2006.145.19:24:57.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:24:57.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:24:57.10#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.19:24:57.10#ibcon#ireg 7 cls_cnt 0 2006.145.19:24:57.10#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:24:57.22#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:24:57.22#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:24:57.24#ibcon#[25=USB\r\n] 2006.145.19:24:57.27#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:24:57.27#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:24:57.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.19:24:57.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.19:24:57.27$vck44/valo=3,564.99 2006.145.19:24:57.27#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.19:24:57.27#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.19:24:57.27#ibcon#ireg 17 cls_cnt 0 2006.145.19:24:57.27#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:24:57.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:24:57.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:24:57.29#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.19:24:57.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:24:57.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:24:57.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.19:24:57.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.19:24:57.33$vck44/va=3,8 2006.145.19:24:57.33#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.19:24:57.33#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.19:24:57.33#ibcon#ireg 11 cls_cnt 2 2006.145.19:24:57.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.19:24:57.39#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.19:24:57.39#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.19:24:57.41#ibcon#[25=AT03-08\r\n] 2006.145.19:24:57.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.19:24:57.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.19:24:57.44#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.19:24:57.44#ibcon#ireg 7 cls_cnt 0 2006.145.19:24:57.44#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.19:24:57.56#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.19:24:57.56#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.19:24:57.58#ibcon#[25=USB\r\n] 2006.145.19:24:57.61#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.19:24:57.61#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.19:24:57.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.19:24:57.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.19:24:57.61$vck44/valo=4,624.99 2006.145.19:24:57.61#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.19:24:57.61#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.19:24:57.61#ibcon#ireg 17 cls_cnt 0 2006.145.19:24:57.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.19:24:57.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.19:24:57.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.19:24:57.63#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.19:24:57.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.19:24:57.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.19:24:57.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.19:24:57.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.19:24:57.67$vck44/va=4,7 2006.145.19:24:57.67#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.19:24:57.67#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.19:24:57.67#ibcon#ireg 11 cls_cnt 2 2006.145.19:24:57.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.19:24:57.73#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.19:24:57.73#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.19:24:57.75#ibcon#[25=AT04-07\r\n] 2006.145.19:24:57.78#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.19:24:57.78#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.19:24:57.78#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.19:24:57.78#ibcon#ireg 7 cls_cnt 0 2006.145.19:24:57.78#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.19:24:57.90#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.19:24:57.90#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.19:24:57.92#ibcon#[25=USB\r\n] 2006.145.19:24:57.95#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.19:24:57.95#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.19:24:57.95#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.19:24:57.95#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.19:24:57.95$vck44/valo=5,734.99 2006.145.19:24:57.95#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.19:24:57.95#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.19:24:57.95#ibcon#ireg 17 cls_cnt 0 2006.145.19:24:57.95#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.19:24:57.95#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.19:24:57.95#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.19:24:57.97#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.19:24:58.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.19:24:58.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.19:24:58.01#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.19:24:58.01#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.19:24:58.01$vck44/va=5,4 2006.145.19:24:58.01#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.19:24:58.01#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.19:24:58.01#ibcon#ireg 11 cls_cnt 2 2006.145.19:24:58.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.19:24:58.07#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.19:24:58.07#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.19:24:58.09#ibcon#[25=AT05-04\r\n] 2006.145.19:24:58.12#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.19:24:58.12#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.19:24:58.12#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.19:24:58.12#ibcon#ireg 7 cls_cnt 0 2006.145.19:24:58.12#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.19:24:58.24#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.19:24:58.24#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.19:24:58.26#ibcon#[25=USB\r\n] 2006.145.19:24:58.29#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.19:24:58.29#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.19:24:58.29#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.19:24:58.29#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.19:24:58.29$vck44/valo=6,814.99 2006.145.19:24:58.29#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.19:24:58.29#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.19:24:58.29#ibcon#ireg 17 cls_cnt 0 2006.145.19:24:58.29#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:24:58.29#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:24:58.29#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:24:58.31#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.19:24:58.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:24:58.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:24:58.35#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.19:24:58.35#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.19:24:58.35$vck44/va=6,4 2006.145.19:24:58.35#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.19:24:58.35#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.19:24:58.35#ibcon#ireg 11 cls_cnt 2 2006.145.19:24:58.35#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.19:24:58.41#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.19:24:58.41#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.19:24:58.43#ibcon#[25=AT06-04\r\n] 2006.145.19:24:58.46#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.19:24:58.46#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.19:24:58.46#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.19:24:58.46#ibcon#ireg 7 cls_cnt 0 2006.145.19:24:58.46#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.19:24:58.58#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.19:24:58.58#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.19:24:58.60#ibcon#[25=USB\r\n] 2006.145.19:24:58.63#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.19:24:58.63#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.19:24:58.63#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.19:24:58.63#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.19:24:58.63$vck44/valo=7,864.99 2006.145.19:24:58.63#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.19:24:58.63#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.19:24:58.63#ibcon#ireg 17 cls_cnt 0 2006.145.19:24:58.63#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:24:58.63#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:24:58.63#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:24:58.65#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.19:24:58.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:24:58.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:24:58.69#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.19:24:58.69#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.19:24:58.69$vck44/va=7,4 2006.145.19:24:58.69#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.19:24:58.69#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.19:24:58.69#ibcon#ireg 11 cls_cnt 2 2006.145.19:24:58.69#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:24:58.75#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:24:58.75#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:24:58.77#ibcon#[25=AT07-04\r\n] 2006.145.19:24:58.80#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:24:58.80#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:24:58.80#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.19:24:58.80#ibcon#ireg 7 cls_cnt 0 2006.145.19:24:58.80#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:24:58.92#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:24:58.92#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:24:58.94#ibcon#[25=USB\r\n] 2006.145.19:24:58.97#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:24:58.97#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:24:58.97#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.19:24:58.97#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.19:24:58.97$vck44/valo=8,884.99 2006.145.19:24:58.97#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.19:24:58.97#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.19:24:58.97#ibcon#ireg 17 cls_cnt 0 2006.145.19:24:58.97#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:24:58.97#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:24:58.97#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:24:58.99#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.19:24:59.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:24:59.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:24:59.03#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.19:24:59.03#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.19:24:59.03$vck44/va=8,4 2006.145.19:24:59.03#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.19:24:59.03#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.19:24:59.03#ibcon#ireg 11 cls_cnt 2 2006.145.19:24:59.03#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.19:24:59.09#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.19:24:59.09#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.19:24:59.11#ibcon#[25=AT08-04\r\n] 2006.145.19:24:59.14#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.19:24:59.14#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.19:24:59.14#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.19:24:59.14#ibcon#ireg 7 cls_cnt 0 2006.145.19:24:59.14#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.19:24:59.28#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.19:24:59.28#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.19:24:59.30#ibcon#[25=USB\r\n] 2006.145.19:24:59.33#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.19:24:59.33#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.19:24:59.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.19:24:59.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.19:24:59.33$vck44/vblo=1,629.99 2006.145.19:24:59.33#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.19:24:59.33#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.19:24:59.33#ibcon#ireg 17 cls_cnt 0 2006.145.19:24:59.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.19:24:59.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.19:24:59.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.19:24:59.35#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.19:24:59.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.19:24:59.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.19:24:59.39#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.19:24:59.39#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.19:24:59.39$vck44/vb=1,3 2006.145.19:24:59.39#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.19:24:59.39#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.19:24:59.39#ibcon#ireg 11 cls_cnt 2 2006.145.19:24:59.39#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.19:24:59.39#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.19:24:59.39#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.19:24:59.41#ibcon#[27=AT01-03\r\n] 2006.145.19:24:59.44#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.19:24:59.44#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.19:24:59.44#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.19:24:59.44#ibcon#ireg 7 cls_cnt 0 2006.145.19:24:59.44#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.19:24:59.56#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.19:24:59.56#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.19:24:59.58#ibcon#[27=USB\r\n] 2006.145.19:24:59.61#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.19:24:59.61#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.19:24:59.61#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.19:24:59.61#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.19:24:59.61$vck44/vblo=2,634.99 2006.145.19:24:59.61#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.19:24:59.61#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.19:24:59.61#ibcon#ireg 17 cls_cnt 0 2006.145.19:24:59.61#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:24:59.61#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:24:59.61#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:24:59.63#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.19:24:59.67#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:24:59.67#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:24:59.67#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.19:24:59.67#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.19:24:59.67$vck44/vb=2,4 2006.145.19:24:59.67#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.19:24:59.67#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.19:24:59.67#ibcon#ireg 11 cls_cnt 2 2006.145.19:24:59.67#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:24:59.73#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:24:59.73#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:24:59.75#ibcon#[27=AT02-04\r\n] 2006.145.19:24:59.78#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:24:59.78#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:24:59.78#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.19:24:59.78#ibcon#ireg 7 cls_cnt 0 2006.145.19:24:59.78#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:24:59.90#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:24:59.90#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:24:59.92#ibcon#[27=USB\r\n] 2006.145.19:24:59.95#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:24:59.95#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:24:59.95#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.19:24:59.95#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.19:24:59.95$vck44/vblo=3,649.99 2006.145.19:24:59.95#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.19:24:59.95#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.19:24:59.95#ibcon#ireg 17 cls_cnt 0 2006.145.19:24:59.95#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:24:59.95#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:24:59.95#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:24:59.97#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.19:25:00.01#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:25:00.01#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:25:00.01#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.19:25:00.01#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.19:25:00.01$vck44/vb=3,4 2006.145.19:25:00.01#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.19:25:00.01#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.19:25:00.01#ibcon#ireg 11 cls_cnt 2 2006.145.19:25:00.01#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:25:00.07#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:25:00.07#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:25:00.09#ibcon#[27=AT03-04\r\n] 2006.145.19:25:00.12#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:25:00.12#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:25:00.12#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.19:25:00.12#ibcon#ireg 7 cls_cnt 0 2006.145.19:25:00.12#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:25:00.24#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:25:00.24#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:25:00.26#ibcon#[27=USB\r\n] 2006.145.19:25:00.29#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:25:00.29#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:25:00.29#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.19:25:00.29#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.19:25:00.29$vck44/vblo=4,679.99 2006.145.19:25:00.29#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.19:25:00.29#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.19:25:00.29#ibcon#ireg 17 cls_cnt 0 2006.145.19:25:00.29#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:25:00.29#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:25:00.29#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:25:00.31#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.19:25:00.35#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:25:00.35#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:25:00.35#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.19:25:00.35#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.19:25:00.35$vck44/vb=4,4 2006.145.19:25:00.35#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.19:25:00.35#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.19:25:00.35#ibcon#ireg 11 cls_cnt 2 2006.145.19:25:00.35#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.19:25:00.41#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.19:25:00.41#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.19:25:00.43#ibcon#[27=AT04-04\r\n] 2006.145.19:25:00.46#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.19:25:00.46#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.19:25:00.46#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.19:25:00.46#ibcon#ireg 7 cls_cnt 0 2006.145.19:25:00.46#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.19:25:00.58#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.19:25:00.58#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.19:25:00.60#ibcon#[27=USB\r\n] 2006.145.19:25:00.63#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.19:25:00.63#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.19:25:00.63#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.19:25:00.63#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.19:25:00.63$vck44/vblo=5,709.99 2006.145.19:25:00.63#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.19:25:00.63#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.19:25:00.63#ibcon#ireg 17 cls_cnt 0 2006.145.19:25:00.63#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.19:25:00.63#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.19:25:00.63#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.19:25:00.65#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.19:25:00.69#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.19:25:00.69#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.19:25:00.69#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.19:25:00.69#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.19:25:00.69$vck44/vb=5,4 2006.145.19:25:00.69#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.19:25:00.69#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.19:25:00.69#ibcon#ireg 11 cls_cnt 2 2006.145.19:25:00.69#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.19:25:00.75#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.19:25:00.75#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.19:25:00.77#ibcon#[27=AT05-04\r\n] 2006.145.19:25:00.80#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.19:25:00.80#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.19:25:00.80#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.19:25:00.80#ibcon#ireg 7 cls_cnt 0 2006.145.19:25:00.80#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.19:25:00.92#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.19:25:00.92#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.19:25:00.94#ibcon#[27=USB\r\n] 2006.145.19:25:00.97#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.19:25:00.97#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.19:25:00.97#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.19:25:00.97#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.19:25:00.97$vck44/vblo=6,719.99 2006.145.19:25:00.97#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.19:25:00.97#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.19:25:00.97#ibcon#ireg 17 cls_cnt 0 2006.145.19:25:00.97#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.19:25:00.97#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.19:25:00.97#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.19:25:00.99#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.19:25:01.03#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.19:25:01.03#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.19:25:01.03#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.19:25:01.03#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.19:25:01.03$vck44/vb=6,4 2006.145.19:25:01.03#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.19:25:01.03#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.19:25:01.03#ibcon#ireg 11 cls_cnt 2 2006.145.19:25:01.03#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.19:25:01.09#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.19:25:01.09#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.19:25:01.11#ibcon#[27=AT06-04\r\n] 2006.145.19:25:01.14#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.19:25:01.14#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.19:25:01.14#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.19:25:01.14#ibcon#ireg 7 cls_cnt 0 2006.145.19:25:01.14#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.19:25:01.26#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.19:25:01.26#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.19:25:01.28#ibcon#[27=USB\r\n] 2006.145.19:25:01.31#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.19:25:01.31#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.19:25:01.31#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.19:25:01.31#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.19:25:01.31$vck44/vblo=7,734.99 2006.145.19:25:01.31#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.19:25:01.31#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.19:25:01.31#ibcon#ireg 17 cls_cnt 0 2006.145.19:25:01.31#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:25:01.31#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:25:01.31#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:25:01.33#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.19:25:01.37#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:25:01.37#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:25:01.37#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.19:25:01.37#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.19:25:01.37$vck44/vb=7,4 2006.145.19:25:01.37#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.19:25:01.37#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.19:25:01.37#ibcon#ireg 11 cls_cnt 2 2006.145.19:25:01.37#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.19:25:01.43#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.19:25:01.43#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.19:25:01.45#ibcon#[27=AT07-04\r\n] 2006.145.19:25:01.48#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.19:25:01.48#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.19:25:01.48#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.19:25:01.48#ibcon#ireg 7 cls_cnt 0 2006.145.19:25:01.48#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.19:25:01.60#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.19:25:01.60#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.19:25:01.62#ibcon#[27=USB\r\n] 2006.145.19:25:01.65#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.19:25:01.65#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.19:25:01.65#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.19:25:01.65#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.19:25:01.65$vck44/vblo=8,744.99 2006.145.19:25:01.65#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.19:25:01.65#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.19:25:01.65#ibcon#ireg 17 cls_cnt 0 2006.145.19:25:01.65#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:25:01.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:25:01.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:25:01.67#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.19:25:01.71#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:25:01.71#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:25:01.71#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.19:25:01.71#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.19:25:01.71$vck44/vb=8,4 2006.145.19:25:01.71#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.19:25:01.71#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.19:25:01.71#ibcon#ireg 11 cls_cnt 2 2006.145.19:25:01.71#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:25:01.77#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:25:01.77#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:25:01.79#ibcon#[27=AT08-04\r\n] 2006.145.19:25:01.82#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:25:01.82#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:25:01.82#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.19:25:01.82#ibcon#ireg 7 cls_cnt 0 2006.145.19:25:01.82#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:25:01.94#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:25:01.94#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:25:01.96#ibcon#[27=USB\r\n] 2006.145.19:25:01.99#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:25:01.99#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:25:01.99#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.19:25:01.99#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.19:25:01.99$vck44/vabw=wide 2006.145.19:25:01.99#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.19:25:01.99#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.19:25:01.99#ibcon#ireg 8 cls_cnt 0 2006.145.19:25:01.99#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:25:01.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:25:01.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:25:02.01#ibcon#[25=BW32\r\n] 2006.145.19:25:02.04#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:25:02.04#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:25:02.04#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.19:25:02.04#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.19:25:02.04$vck44/vbbw=wide 2006.145.19:25:02.04#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.19:25:02.04#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.19:25:02.04#ibcon#ireg 8 cls_cnt 0 2006.145.19:25:02.04#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.19:25:02.11#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.19:25:02.11#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.19:25:02.13#ibcon#[27=BW32\r\n] 2006.145.19:25:02.16#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.19:25:02.16#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.19:25:02.16#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.19:25:02.16#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.19:25:02.16$setupk4/ifdk4 2006.145.19:25:02.16$ifdk4/lo= 2006.145.19:25:02.16$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.19:25:02.16$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.19:25:02.16$ifdk4/patch= 2006.145.19:25:02.16$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.19:25:02.16$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.19:25:02.16$setupk4/!*+20s 2006.145.19:25:04.58#abcon#<5=/07 1.4 2.4 15.85 871019.9\r\n> 2006.145.19:25:04.60#abcon#{5=INTERFACE CLEAR} 2006.145.19:25:04.66#abcon#[5=S1D000X0/0*\r\n] 2006.145.19:25:09.13#trakl#Source acquired 2006.145.19:25:10.13#flagr#flagr/antenna,acquired 2006.145.19:25:14.75#abcon#<5=/07 1.4 2.4 15.85 871019.9\r\n> 2006.145.19:25:14.77#abcon#{5=INTERFACE CLEAR} 2006.145.19:25:14.83#abcon#[5=S1D000X0/0*\r\n] 2006.145.19:25:16.63$setupk4/"tpicd 2006.145.19:25:16.63$setupk4/echo=off 2006.145.19:25:16.63$setupk4/xlog=off 2006.145.19:25:16.63:!2006.145.19:29:11 2006.145.19:29:11.00:preob 2006.145.19:29:11.14/onsource/TRACKING 2006.145.19:29:11.14:!2006.145.19:29:21 2006.145.19:29:21.00:"tape 2006.145.19:29:21.00:"st=record 2006.145.19:29:21.00:data_valid=on 2006.145.19:29:21.00:midob 2006.145.19:29:22.14/onsource/TRACKING 2006.145.19:29:22.14/wx/15.85,1019.9,87 2006.145.19:29:22.30/cable/+6.5508E-03 2006.145.19:29:23.39/va/01,08,usb,yes,29,32 2006.145.19:29:23.39/va/02,07,usb,yes,31,32 2006.145.19:29:23.39/va/03,08,usb,yes,29,30 2006.145.19:29:23.39/va/04,07,usb,yes,33,34 2006.145.19:29:23.39/va/05,04,usb,yes,28,29 2006.145.19:29:23.39/va/06,04,usb,yes,32,32 2006.145.19:29:23.39/va/07,04,usb,yes,32,33 2006.145.19:29:23.39/va/08,04,usb,yes,27,33 2006.145.19:29:23.62/valo/01,524.99,yes,locked 2006.145.19:29:23.62/valo/02,534.99,yes,locked 2006.145.19:29:23.62/valo/03,564.99,yes,locked 2006.145.19:29:23.62/valo/04,624.99,yes,locked 2006.145.19:29:23.62/valo/05,734.99,yes,locked 2006.145.19:29:23.62/valo/06,814.99,yes,locked 2006.145.19:29:23.62/valo/07,864.99,yes,locked 2006.145.19:29:23.62/valo/08,884.99,yes,locked 2006.145.19:29:24.71/vb/01,03,usb,yes,37,34 2006.145.19:29:24.71/vb/02,04,usb,yes,32,32 2006.145.19:29:24.71/vb/03,04,usb,yes,29,32 2006.145.19:29:24.71/vb/04,04,usb,yes,33,32 2006.145.19:29:24.71/vb/05,04,usb,yes,26,28 2006.145.19:29:24.71/vb/06,04,usb,yes,30,26 2006.145.19:29:24.71/vb/07,04,usb,yes,30,30 2006.145.19:29:24.71/vb/08,04,usb,yes,27,31 2006.145.19:29:24.94/vblo/01,629.99,yes,locked 2006.145.19:29:24.94/vblo/02,634.99,yes,locked 2006.145.19:29:24.94/vblo/03,649.99,yes,locked 2006.145.19:29:24.94/vblo/04,679.99,yes,locked 2006.145.19:29:24.94/vblo/05,709.99,yes,locked 2006.145.19:29:24.94/vblo/06,719.99,yes,locked 2006.145.19:29:24.94/vblo/07,734.99,yes,locked 2006.145.19:29:24.94/vblo/08,744.99,yes,locked 2006.145.19:29:25.09/vabw/8 2006.145.19:29:25.24/vbbw/8 2006.145.19:29:25.44/xfe/off,on,15.0 2006.145.19:29:25.84/ifatt/23,28,28,28 2006.145.19:29:26.08/fmout-gps/S +5.5E-08 2006.145.19:29:26.12:!2006.145.19:30:01 2006.145.19:30:01.00:data_valid=off 2006.145.19:30:01.00:"et 2006.145.19:30:01.00:!+3s 2006.145.19:30:04.02:"tape 2006.145.19:30:04.02:postob 2006.145.19:30:04.10/cable/+6.5507E-03 2006.145.19:30:04.10/wx/15.85,1019.9,88 2006.145.19:30:05.08/fmout-gps/S +5.4E-08 2006.145.19:30:05.08:scan_name=145-1931,jd0605,120 2006.145.19:30:05.08:source=2201+315,220314.98,314538.3,2000.0,cw 2006.145.19:30:06.14#flagr#flagr/antenna,new-source 2006.145.19:30:06.14:checkk5 2006.145.19:30:06.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.19:30:07.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.19:30:07.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.19:30:07.91/chk_autoobs//k5ts4/ autoobs is running! 2006.145.19:30:08.34/chk_obsdata//k5ts1/T1451929??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.19:30:08.77/chk_obsdata//k5ts2/T1451929??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.19:30:09.22/chk_obsdata//k5ts3/T1451929??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.19:30:09.66/chk_obsdata//k5ts4/T1451929??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.19:30:10.44/k5log//k5ts1_log_newline 2006.145.19:30:11.18/k5log//k5ts2_log_newline 2006.145.19:30:11.93/k5log//k5ts3_log_newline 2006.145.19:30:12.67/k5log//k5ts4_log_newline 2006.145.19:30:12.69/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.19:30:12.69:setupk4=1 2006.145.19:30:12.69$setupk4/echo=on 2006.145.19:30:12.69$setupk4/pcalon 2006.145.19:30:12.69$pcalon/"no phase cal control is implemented here 2006.145.19:30:12.69$setupk4/"tpicd=stop 2006.145.19:30:12.69$setupk4/"rec=synch_on 2006.145.19:30:12.69$setupk4/"rec_mode=128 2006.145.19:30:12.70$setupk4/!* 2006.145.19:30:12.70$setupk4/recpk4 2006.145.19:30:12.70$recpk4/recpatch= 2006.145.19:30:12.70$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.19:30:12.70$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.19:30:12.70$setupk4/vck44 2006.145.19:30:12.70$vck44/valo=1,524.99 2006.145.19:30:12.70#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.19:30:12.70#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.19:30:12.70#ibcon#ireg 17 cls_cnt 0 2006.145.19:30:12.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.19:30:12.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.19:30:12.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.19:30:12.74#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.19:30:12.79#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.19:30:12.79#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.19:30:12.79#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.19:30:12.79#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.19:30:12.79$vck44/va=1,8 2006.145.19:30:12.79#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.19:30:12.79#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.19:30:12.79#ibcon#ireg 11 cls_cnt 2 2006.145.19:30:12.79#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:30:12.79#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:30:12.79#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:30:12.81#ibcon#[25=AT01-08\r\n] 2006.145.19:30:12.84#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:30:12.84#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:30:12.84#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.19:30:12.84#ibcon#ireg 7 cls_cnt 0 2006.145.19:30:12.84#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:30:12.96#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:30:12.96#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:30:12.98#ibcon#[25=USB\r\n] 2006.145.19:30:13.01#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:30:13.01#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:30:13.01#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.19:30:13.01#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.19:30:13.01$vck44/valo=2,534.99 2006.145.19:30:13.01#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.19:30:13.01#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.19:30:13.01#ibcon#ireg 17 cls_cnt 0 2006.145.19:30:13.01#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:30:13.01#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:30:13.01#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:30:13.04#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.19:30:13.08#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:30:13.08#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:30:13.08#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.19:30:13.08#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.19:30:13.08$vck44/va=2,7 2006.145.19:30:13.08#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.19:30:13.08#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.19:30:13.08#ibcon#ireg 11 cls_cnt 2 2006.145.19:30:13.08#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:30:13.13#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:30:13.13#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:30:13.15#ibcon#[25=AT02-07\r\n] 2006.145.19:30:13.18#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:30:13.18#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:30:13.18#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.19:30:13.18#ibcon#ireg 7 cls_cnt 0 2006.145.19:30:13.18#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:30:13.30#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:30:13.30#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:30:13.32#ibcon#[25=USB\r\n] 2006.145.19:30:13.35#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:30:13.35#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:30:13.35#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.19:30:13.35#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.19:30:13.35$vck44/valo=3,564.99 2006.145.19:30:13.35#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.19:30:13.35#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.19:30:13.35#ibcon#ireg 17 cls_cnt 0 2006.145.19:30:13.35#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:30:13.35#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:30:13.35#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:30:13.37#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.19:30:13.41#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:30:13.41#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:30:13.41#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.19:30:13.41#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.19:30:13.41$vck44/va=3,8 2006.145.19:30:13.41#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.19:30:13.41#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.19:30:13.41#ibcon#ireg 11 cls_cnt 2 2006.145.19:30:13.41#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:30:13.47#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:30:13.47#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:30:13.49#ibcon#[25=AT03-08\r\n] 2006.145.19:30:13.52#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:30:13.52#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:30:13.52#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.19:30:13.52#ibcon#ireg 7 cls_cnt 0 2006.145.19:30:13.52#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:30:13.64#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:30:13.64#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:30:13.66#ibcon#[25=USB\r\n] 2006.145.19:30:13.69#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:30:13.69#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:30:13.69#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.19:30:13.69#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.19:30:13.69$vck44/valo=4,624.99 2006.145.19:30:13.69#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.19:30:13.69#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.19:30:13.69#ibcon#ireg 17 cls_cnt 0 2006.145.19:30:13.69#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:30:13.69#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:30:13.69#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:30:13.71#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.19:30:13.75#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:30:13.75#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:30:13.75#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.19:30:13.75#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.19:30:13.75$vck44/va=4,7 2006.145.19:30:13.75#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.19:30:13.75#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.19:30:13.75#ibcon#ireg 11 cls_cnt 2 2006.145.19:30:13.75#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:30:13.81#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:30:13.81#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:30:13.83#ibcon#[25=AT04-07\r\n] 2006.145.19:30:13.86#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:30:13.86#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:30:13.86#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.19:30:13.86#ibcon#ireg 7 cls_cnt 0 2006.145.19:30:13.86#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:30:13.98#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:30:13.98#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:30:14.00#ibcon#[25=USB\r\n] 2006.145.19:30:14.03#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:30:14.03#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:30:14.03#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.19:30:14.03#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.19:30:14.03$vck44/valo=5,734.99 2006.145.19:30:14.03#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.19:30:14.03#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.19:30:14.03#ibcon#ireg 17 cls_cnt 0 2006.145.19:30:14.03#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:30:14.03#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:30:14.03#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:30:14.05#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.19:30:14.09#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:30:14.09#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:30:14.09#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.19:30:14.09#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.19:30:14.09$vck44/va=5,4 2006.145.19:30:14.09#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.19:30:14.09#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.19:30:14.09#ibcon#ireg 11 cls_cnt 2 2006.145.19:30:14.09#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:30:14.15#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:30:14.15#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:30:14.17#ibcon#[25=AT05-04\r\n] 2006.145.19:30:14.20#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:30:14.20#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:30:14.20#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.19:30:14.20#ibcon#ireg 7 cls_cnt 0 2006.145.19:30:14.20#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:30:14.32#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:30:14.32#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:30:14.34#ibcon#[25=USB\r\n] 2006.145.19:30:14.37#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:30:14.37#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:30:14.37#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.19:30:14.37#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.19:30:14.37$vck44/valo=6,814.99 2006.145.19:30:14.37#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.19:30:14.37#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.19:30:14.37#ibcon#ireg 17 cls_cnt 0 2006.145.19:30:14.37#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:30:14.37#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:30:14.37#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:30:14.40#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.19:30:14.44#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:30:14.44#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:30:14.44#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.19:30:14.44#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.19:30:14.44$vck44/va=6,4 2006.145.19:30:14.44#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.19:30:14.44#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.19:30:14.44#ibcon#ireg 11 cls_cnt 2 2006.145.19:30:14.44#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:30:14.49#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:30:14.49#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:30:14.51#ibcon#[25=AT06-04\r\n] 2006.145.19:30:14.54#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:30:14.54#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:30:14.54#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.19:30:14.54#ibcon#ireg 7 cls_cnt 0 2006.145.19:30:14.54#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:30:14.66#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:30:14.66#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:30:14.68#ibcon#[25=USB\r\n] 2006.145.19:30:14.71#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:30:14.71#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:30:14.71#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.19:30:14.71#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.19:30:14.71$vck44/valo=7,864.99 2006.145.19:30:14.71#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.19:30:14.71#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.19:30:14.71#ibcon#ireg 17 cls_cnt 0 2006.145.19:30:14.71#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:30:14.71#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:30:14.71#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:30:14.73#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.19:30:14.77#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:30:14.77#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:30:14.77#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.19:30:14.77#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.19:30:14.77$vck44/va=7,4 2006.145.19:30:14.77#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.19:30:14.77#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.19:30:14.77#ibcon#ireg 11 cls_cnt 2 2006.145.19:30:14.77#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.19:30:14.83#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.19:30:14.83#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.19:30:14.85#ibcon#[25=AT07-04\r\n] 2006.145.19:30:14.88#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.19:30:14.88#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.19:30:14.88#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.19:30:14.88#ibcon#ireg 7 cls_cnt 0 2006.145.19:30:14.88#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.19:30:15.00#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.19:30:15.00#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.19:30:15.02#ibcon#[25=USB\r\n] 2006.145.19:30:15.05#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.19:30:15.05#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.19:30:15.05#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.19:30:15.05#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.19:30:15.05$vck44/valo=8,884.99 2006.145.19:30:15.05#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.19:30:15.05#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.19:30:15.05#ibcon#ireg 17 cls_cnt 0 2006.145.19:30:15.05#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.19:30:15.05#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.19:30:15.05#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.19:30:15.07#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.19:30:15.11#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.19:30:15.11#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.19:30:15.11#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.19:30:15.11#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.19:30:15.11$vck44/va=8,4 2006.145.19:30:15.11#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.19:30:15.11#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.19:30:15.11#ibcon#ireg 11 cls_cnt 2 2006.145.19:30:15.11#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.19:30:15.17#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.19:30:15.17#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.19:30:15.19#ibcon#[25=AT08-04\r\n] 2006.145.19:30:15.22#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.19:30:15.22#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.19:30:15.22#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.19:30:15.22#ibcon#ireg 7 cls_cnt 0 2006.145.19:30:15.22#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.19:30:15.34#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.19:30:15.34#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.19:30:15.36#ibcon#[25=USB\r\n] 2006.145.19:30:15.39#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.19:30:15.39#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.19:30:15.39#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.19:30:15.39#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.19:30:15.39$vck44/vblo=1,629.99 2006.145.19:30:15.39#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.19:30:15.39#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.19:30:15.39#ibcon#ireg 17 cls_cnt 0 2006.145.19:30:15.39#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.19:30:15.39#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.19:30:15.39#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.19:30:15.41#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.19:30:15.45#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.19:30:15.45#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.19:30:15.45#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.19:30:15.45#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.19:30:15.45$vck44/vb=1,3 2006.145.19:30:15.45#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.19:30:15.45#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.19:30:15.45#ibcon#ireg 11 cls_cnt 2 2006.145.19:30:15.45#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.19:30:15.45#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.19:30:15.45#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.19:30:15.47#ibcon#[27=AT01-03\r\n] 2006.145.19:30:15.50#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.19:30:15.50#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.19:30:15.50#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.19:30:15.50#ibcon#ireg 7 cls_cnt 0 2006.145.19:30:15.50#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.19:30:15.62#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.19:30:15.62#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.19:30:15.64#ibcon#[27=USB\r\n] 2006.145.19:30:15.67#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.19:30:15.67#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.19:30:15.67#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.19:30:15.67#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.19:30:15.67$vck44/vblo=2,634.99 2006.145.19:30:15.67#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.19:30:15.67#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.19:30:15.67#ibcon#ireg 17 cls_cnt 0 2006.145.19:30:15.67#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.19:30:15.67#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.19:30:15.67#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.19:30:15.69#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.19:30:15.73#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.19:30:15.73#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.19:30:15.73#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.19:30:15.73#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.19:30:15.73$vck44/vb=2,4 2006.145.19:30:15.73#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.19:30:15.73#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.19:30:15.73#ibcon#ireg 11 cls_cnt 2 2006.145.19:30:15.73#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:30:15.79#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:30:15.79#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:30:15.81#ibcon#[27=AT02-04\r\n] 2006.145.19:30:15.84#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:30:15.84#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:30:15.84#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.19:30:15.84#ibcon#ireg 7 cls_cnt 0 2006.145.19:30:15.84#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:30:15.96#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:30:15.96#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:30:15.98#ibcon#[27=USB\r\n] 2006.145.19:30:16.01#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:30:16.01#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:30:16.01#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.19:30:16.01#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.19:30:16.01$vck44/vblo=3,649.99 2006.145.19:30:16.01#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.19:30:16.01#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.19:30:16.01#ibcon#ireg 17 cls_cnt 0 2006.145.19:30:16.01#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:30:16.01#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:30:16.01#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:30:16.03#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.19:30:16.07#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:30:16.07#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:30:16.07#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.19:30:16.07#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.19:30:16.07$vck44/vb=3,4 2006.145.19:30:16.07#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.19:30:16.07#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.19:30:16.07#ibcon#ireg 11 cls_cnt 2 2006.145.19:30:16.07#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:30:16.13#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:30:16.13#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:30:16.15#ibcon#[27=AT03-04\r\n] 2006.145.19:30:16.18#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:30:16.18#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:30:16.18#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.19:30:16.18#ibcon#ireg 7 cls_cnt 0 2006.145.19:30:16.18#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:30:16.30#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:30:16.30#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:30:16.32#ibcon#[27=USB\r\n] 2006.145.19:30:16.35#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:30:16.35#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:30:16.35#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.19:30:16.35#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.19:30:16.35$vck44/vblo=4,679.99 2006.145.19:30:16.35#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.19:30:16.35#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.19:30:16.35#ibcon#ireg 17 cls_cnt 0 2006.145.19:30:16.35#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:30:16.35#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:30:16.35#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:30:16.37#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.19:30:16.41#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:30:16.41#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:30:16.41#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.19:30:16.41#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.19:30:16.41$vck44/vb=4,4 2006.145.19:30:16.41#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.19:30:16.41#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.19:30:16.41#ibcon#ireg 11 cls_cnt 2 2006.145.19:30:16.41#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:30:16.47#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:30:16.47#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:30:16.49#ibcon#[27=AT04-04\r\n] 2006.145.19:30:16.52#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:30:16.52#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:30:16.52#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.19:30:16.52#ibcon#ireg 7 cls_cnt 0 2006.145.19:30:16.52#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:30:16.64#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:30:16.64#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:30:16.66#ibcon#[27=USB\r\n] 2006.145.19:30:16.69#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:30:16.69#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:30:16.69#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.19:30:16.69#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.19:30:16.69$vck44/vblo=5,709.99 2006.145.19:30:16.69#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.19:30:16.69#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.19:30:16.69#ibcon#ireg 17 cls_cnt 0 2006.145.19:30:16.69#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:30:16.69#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:30:16.69#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:30:16.71#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.19:30:16.75#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:30:16.75#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:30:16.75#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.19:30:16.75#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.19:30:16.75$vck44/vb=5,4 2006.145.19:30:16.75#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.19:30:16.75#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.19:30:16.75#ibcon#ireg 11 cls_cnt 2 2006.145.19:30:16.75#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:30:16.81#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:30:16.81#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:30:16.83#ibcon#[27=AT05-04\r\n] 2006.145.19:30:16.86#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:30:16.86#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:30:16.86#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.19:30:16.86#ibcon#ireg 7 cls_cnt 0 2006.145.19:30:16.86#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:30:16.98#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:30:16.98#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:30:17.00#ibcon#[27=USB\r\n] 2006.145.19:30:17.03#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:30:17.03#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:30:17.03#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.19:30:17.03#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.19:30:17.03$vck44/vblo=6,719.99 2006.145.19:30:17.03#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.19:30:17.03#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.19:30:17.03#ibcon#ireg 17 cls_cnt 0 2006.145.19:30:17.03#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:30:17.03#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:30:17.03#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:30:17.05#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.19:30:17.09#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:30:17.09#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:30:17.09#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.19:30:17.09#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.19:30:17.09$vck44/vb=6,4 2006.145.19:30:17.09#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.19:30:17.09#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.19:30:17.09#ibcon#ireg 11 cls_cnt 2 2006.145.19:30:17.09#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:30:17.15#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:30:17.15#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:30:17.17#ibcon#[27=AT06-04\r\n] 2006.145.19:30:17.20#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:30:17.20#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:30:17.20#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.19:30:17.20#ibcon#ireg 7 cls_cnt 0 2006.145.19:30:17.20#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:30:17.32#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:30:17.32#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:30:17.34#ibcon#[27=USB\r\n] 2006.145.19:30:17.37#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:30:17.37#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:30:17.37#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.19:30:17.37#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.19:30:17.37$vck44/vblo=7,734.99 2006.145.19:30:17.37#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.19:30:17.37#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.19:30:17.37#ibcon#ireg 17 cls_cnt 0 2006.145.19:30:17.37#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:30:17.37#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:30:17.37#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:30:17.39#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.19:30:17.43#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:30:17.43#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:30:17.43#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.19:30:17.43#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.19:30:17.43$vck44/vb=7,4 2006.145.19:30:17.43#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.19:30:17.43#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.19:30:17.43#ibcon#ireg 11 cls_cnt 2 2006.145.19:30:17.43#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:30:17.49#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:30:17.49#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:30:17.51#ibcon#[27=AT07-04\r\n] 2006.145.19:30:17.54#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:30:17.54#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:30:17.54#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.19:30:17.54#ibcon#ireg 7 cls_cnt 0 2006.145.19:30:17.54#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:30:17.66#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:30:17.66#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:30:17.68#ibcon#[27=USB\r\n] 2006.145.19:30:17.71#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:30:17.71#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:30:17.71#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.19:30:17.71#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.19:30:17.71$vck44/vblo=8,744.99 2006.145.19:30:17.71#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.19:30:17.71#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.19:30:17.71#ibcon#ireg 17 cls_cnt 0 2006.145.19:30:17.71#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:30:17.71#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:30:17.71#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:30:17.73#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.19:30:17.77#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:30:17.77#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:30:17.77#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.19:30:17.77#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.19:30:17.77$vck44/vb=8,4 2006.145.19:30:17.77#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.19:30:17.77#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.19:30:17.77#ibcon#ireg 11 cls_cnt 2 2006.145.19:30:17.77#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.19:30:17.83#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.19:30:17.83#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.19:30:17.85#ibcon#[27=AT08-04\r\n] 2006.145.19:30:17.88#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.19:30:17.88#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.19:30:17.88#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.19:30:17.88#ibcon#ireg 7 cls_cnt 0 2006.145.19:30:17.88#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.19:30:18.00#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.19:30:18.00#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.19:30:18.02#ibcon#[27=USB\r\n] 2006.145.19:30:18.05#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.19:30:18.05#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.19:30:18.05#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.19:30:18.05#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.19:30:18.05$vck44/vabw=wide 2006.145.19:30:18.05#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.19:30:18.05#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.19:30:18.05#ibcon#ireg 8 cls_cnt 0 2006.145.19:30:18.05#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.19:30:18.05#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.19:30:18.05#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.19:30:18.07#ibcon#[25=BW32\r\n] 2006.145.19:30:18.10#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.19:30:18.10#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.19:30:18.10#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.19:30:18.10#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.19:30:18.10$vck44/vbbw=wide 2006.145.19:30:18.10#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.19:30:18.10#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.19:30:18.10#ibcon#ireg 8 cls_cnt 0 2006.145.19:30:18.10#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.19:30:18.17#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.19:30:18.17#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.19:30:18.19#ibcon#[27=BW32\r\n] 2006.145.19:30:18.22#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.19:30:18.22#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.19:30:18.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.19:30:18.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.19:30:18.22$setupk4/ifdk4 2006.145.19:30:18.22$ifdk4/lo= 2006.145.19:30:18.22$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.19:30:18.22$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.19:30:18.22$ifdk4/patch= 2006.145.19:30:18.22$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.19:30:18.22$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.19:30:18.22$setupk4/!*+20s 2006.145.19:30:19.97#abcon#<5=/07 1.3 2.3 15.85 881019.9\r\n> 2006.145.19:30:19.99#abcon#{5=INTERFACE CLEAR} 2006.145.19:30:20.06#abcon#[5=S1D000X0/0*\r\n] 2006.145.19:30:30.29#abcon#<5=/07 1.3 2.3 15.85 881019.9\r\n> 2006.145.19:30:30.31#abcon#{5=INTERFACE CLEAR} 2006.145.19:30:30.37#abcon#[5=S1D000X0/0*\r\n] 2006.145.19:30:32.71$setupk4/"tpicd 2006.145.19:30:32.71$setupk4/echo=off 2006.145.19:30:32.71$setupk4/xlog=off 2006.145.19:30:32.71:!2006.145.19:31:45 2006.145.19:30:57.14#trakl#Source acquired 2006.145.19:30:58.14#flagr#flagr/antenna,acquired 2006.145.19:31:45.00:preob 2006.145.19:31:45.14/onsource/TRACKING 2006.145.19:31:45.14:!2006.145.19:31:55 2006.145.19:31:55.00:"tape 2006.145.19:31:55.00:"st=record 2006.145.19:31:55.00:data_valid=on 2006.145.19:31:55.00:midob 2006.145.19:31:55.14/onsource/TRACKING 2006.145.19:31:55.14/wx/15.86,1020.0,88 2006.145.19:31:55.37/cable/+6.5497E-03 2006.145.19:31:56.46/va/01,08,usb,yes,28,30 2006.145.19:31:56.46/va/02,07,usb,yes,30,31 2006.145.19:31:56.46/va/03,08,usb,yes,27,28 2006.145.19:31:56.46/va/04,07,usb,yes,31,32 2006.145.19:31:56.46/va/05,04,usb,yes,27,27 2006.145.19:31:56.46/va/06,04,usb,yes,30,30 2006.145.19:31:56.46/va/07,04,usb,yes,30,32 2006.145.19:31:56.46/va/08,04,usb,yes,26,31 2006.145.19:31:56.69/valo/01,524.99,yes,locked 2006.145.19:31:56.69/valo/02,534.99,yes,locked 2006.145.19:31:56.69/valo/03,564.99,yes,locked 2006.145.19:31:56.69/valo/04,624.99,yes,locked 2006.145.19:31:56.69/valo/05,734.99,yes,locked 2006.145.19:31:56.69/valo/06,814.99,yes,locked 2006.145.19:31:56.69/valo/07,864.99,yes,locked 2006.145.19:31:56.69/valo/08,884.99,yes,locked 2006.145.19:31:57.78/vb/01,03,usb,yes,35,33 2006.145.19:31:57.78/vb/02,04,usb,yes,31,31 2006.145.19:31:57.78/vb/03,04,usb,yes,28,31 2006.145.19:31:57.78/vb/04,04,usb,yes,32,31 2006.145.19:31:57.78/vb/05,04,usb,yes,25,27 2006.145.19:31:57.78/vb/06,04,usb,yes,29,26 2006.145.19:31:57.78/vb/07,04,usb,yes,29,29 2006.145.19:31:57.78/vb/08,04,usb,yes,27,30 2006.145.19:31:58.01/vblo/01,629.99,yes,locked 2006.145.19:31:58.01/vblo/02,634.99,yes,locked 2006.145.19:31:58.01/vblo/03,649.99,yes,locked 2006.145.19:31:58.01/vblo/04,679.99,yes,locked 2006.145.19:31:58.01/vblo/05,709.99,yes,locked 2006.145.19:31:58.01/vblo/06,719.99,yes,locked 2006.145.19:31:58.01/vblo/07,734.99,yes,locked 2006.145.19:31:58.01/vblo/08,744.99,yes,locked 2006.145.19:31:58.16/vabw/8 2006.145.19:31:58.31/vbbw/8 2006.145.19:31:58.40/xfe/off,on,16.0 2006.145.19:31:58.77/ifatt/23,28,28,28 2006.145.19:31:59.08/fmout-gps/S +5.3E-08 2006.145.19:31:59.12:!2006.145.19:33:55 2006.145.19:33:55.02:data_valid=off 2006.145.19:33:55.02:"et 2006.145.19:33:55.02:!+3s 2006.145.19:33:58.05:"tape 2006.145.19:33:58.10:postob 2006.145.19:33:58.25/cable/+6.5505E-03 2006.145.19:33:58.26/wx/15.87,1020.0,87 2006.145.19:33:58.34/fmout-gps/S +5.4E-08 2006.145.19:33:58.34:scan_name=145-1939,jd0605,410 2006.145.19:33:58.34:source=0059+581,010245.76,582411.1,2000.0,cw 2006.145.19:33:59.14#flagr#flagr/antenna,new-source 2006.145.19:33:59.14:checkk5 2006.145.19:33:59.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.19:34:00.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.19:34:00.45/chk_autoobs//k5ts3/ autoobs is running! 2006.145.19:34:00.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.19:34:01.31/chk_obsdata//k5ts1/T1451931??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.19:34:01.76/chk_obsdata//k5ts2/T1451931??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.19:34:02.21/chk_obsdata//k5ts3/T1451931??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.19:34:02.66/chk_obsdata//k5ts4/T1451931??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.19:34:03.43/k5log//k5ts1_log_newline 2006.145.19:34:04.18/k5log//k5ts2_log_newline 2006.145.19:34:04.92/k5log//k5ts3_log_newline 2006.145.19:34:05.67/k5log//k5ts4_log_newline 2006.145.19:34:05.69/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.19:34:05.69:setupk4=1 2006.145.19:34:05.69$setupk4/echo=on 2006.145.19:34:05.69$setupk4/pcalon 2006.145.19:34:05.69$pcalon/"no phase cal control is implemented here 2006.145.19:34:05.69$setupk4/"tpicd=stop 2006.145.19:34:05.69$setupk4/"rec=synch_on 2006.145.19:34:05.69$setupk4/"rec_mode=128 2006.145.19:34:05.70$setupk4/!* 2006.145.19:34:05.70$setupk4/recpk4 2006.145.19:34:05.70$recpk4/recpatch= 2006.145.19:34:05.70$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.19:34:05.70$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.19:34:05.70$setupk4/vck44 2006.145.19:34:05.70$vck44/valo=1,524.99 2006.145.19:34:05.70#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.19:34:05.70#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.19:34:05.70#ibcon#ireg 17 cls_cnt 0 2006.145.19:34:05.70#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.19:34:05.70#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.19:34:05.70#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.19:34:05.74#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.19:34:05.78#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.19:34:05.78#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.19:34:05.78#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.19:34:05.78#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.19:34:05.79$vck44/va=1,8 2006.145.19:34:05.79#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.19:34:05.79#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.19:34:05.79#ibcon#ireg 11 cls_cnt 2 2006.145.19:34:05.79#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.19:34:05.79#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.19:34:05.79#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.19:34:05.81#ibcon#[25=AT01-08\r\n] 2006.145.19:34:05.83#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.19:34:05.83#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.19:34:05.83#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.19:34:05.83#ibcon#ireg 7 cls_cnt 0 2006.145.19:34:05.83#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.19:34:05.96#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.19:34:05.96#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.19:34:05.97#ibcon#[25=USB\r\n] 2006.145.19:34:06.00#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.19:34:06.00#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.19:34:06.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.19:34:06.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.19:34:06.01$vck44/valo=2,534.99 2006.145.19:34:06.01#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.19:34:06.01#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.19:34:06.01#ibcon#ireg 17 cls_cnt 0 2006.145.19:34:06.01#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.19:34:06.01#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.19:34:06.01#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.19:34:06.04#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.19:34:06.08#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.19:34:06.08#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.19:34:06.08#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.19:34:06.08#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.19:34:06.09$vck44/va=2,7 2006.145.19:34:06.09#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.19:34:06.09#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.19:34:06.09#ibcon#ireg 11 cls_cnt 2 2006.145.19:34:06.09#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.19:34:06.11#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.19:34:06.11#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.19:34:06.13#ibcon#[25=AT02-07\r\n] 2006.145.19:34:06.16#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.19:34:06.16#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.19:34:06.16#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.19:34:06.16#ibcon#ireg 7 cls_cnt 0 2006.145.19:34:06.16#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.19:34:06.28#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.19:34:06.28#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.19:34:06.30#ibcon#[25=USB\r\n] 2006.145.19:34:06.33#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.19:34:06.33#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.19:34:06.33#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.19:34:06.33#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.19:34:06.34$vck44/valo=3,564.99 2006.145.19:34:06.34#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.19:34:06.34#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.19:34:06.34#ibcon#ireg 17 cls_cnt 0 2006.145.19:34:06.34#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.19:34:06.34#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.19:34:06.34#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.19:34:06.35#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.19:34:06.39#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.19:34:06.39#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.19:34:06.39#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.19:34:06.39#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.19:34:06.40$vck44/va=3,8 2006.145.19:34:06.40#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.19:34:06.40#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.19:34:06.40#ibcon#ireg 11 cls_cnt 2 2006.145.19:34:06.40#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.19:34:06.44#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.19:34:06.44#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.19:34:06.46#ibcon#[25=AT03-08\r\n] 2006.145.19:34:06.49#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.19:34:06.49#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.19:34:06.49#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.19:34:06.49#ibcon#ireg 7 cls_cnt 0 2006.145.19:34:06.49#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.19:34:06.61#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.19:34:06.61#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.19:34:06.63#ibcon#[25=USB\r\n] 2006.145.19:34:06.66#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.19:34:06.66#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.19:34:06.66#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.19:34:06.66#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.19:34:06.67$vck44/valo=4,624.99 2006.145.19:34:06.67#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.19:34:06.67#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.19:34:06.67#ibcon#ireg 17 cls_cnt 0 2006.145.19:34:06.67#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.19:34:06.67#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.19:34:06.67#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.19:34:06.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.19:34:06.72#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.19:34:06.72#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.19:34:06.72#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.19:34:06.72#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.19:34:06.73$vck44/va=4,7 2006.145.19:34:06.73#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.19:34:06.73#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.19:34:06.73#ibcon#ireg 11 cls_cnt 2 2006.145.19:34:06.73#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.19:34:06.77#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.19:34:06.77#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.19:34:06.79#ibcon#[25=AT04-07\r\n] 2006.145.19:34:06.82#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.19:34:06.82#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.19:34:06.82#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.19:34:06.82#ibcon#ireg 7 cls_cnt 0 2006.145.19:34:06.82#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.19:34:06.94#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.19:34:06.94#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.19:34:06.96#ibcon#[25=USB\r\n] 2006.145.19:34:06.99#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.19:34:06.99#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.19:34:06.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.19:34:06.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.19:34:06.99$vck44/valo=5,734.99 2006.145.19:34:07.00#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.19:34:07.00#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.19:34:07.00#ibcon#ireg 17 cls_cnt 0 2006.145.19:34:07.00#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.19:34:07.00#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.19:34:07.00#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.19:34:07.01#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.19:34:07.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.19:34:07.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.19:34:07.05#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.19:34:07.05#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.19:34:07.05$vck44/va=5,4 2006.145.19:34:07.05#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.19:34:07.06#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.19:34:07.06#ibcon#ireg 11 cls_cnt 2 2006.145.19:34:07.06#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.19:34:07.10#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.19:34:07.10#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.19:34:07.12#ibcon#[25=AT05-04\r\n] 2006.145.19:34:07.15#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.19:34:07.15#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.19:34:07.15#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.19:34:07.15#ibcon#ireg 7 cls_cnt 0 2006.145.19:34:07.15#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.19:34:07.29#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.19:34:07.29#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.19:34:07.30#ibcon#[25=USB\r\n] 2006.145.19:34:07.33#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.19:34:07.33#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.19:34:07.33#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.19:34:07.33#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.19:34:07.33$vck44/valo=6,814.99 2006.145.19:34:07.34#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.19:34:07.34#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.19:34:07.34#ibcon#ireg 17 cls_cnt 0 2006.145.19:34:07.34#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.19:34:07.34#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.19:34:07.34#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.19:34:07.37#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.19:34:07.40#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.19:34:07.40#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.19:34:07.40#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.19:34:07.40#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.19:34:07.41$vck44/va=6,4 2006.145.19:34:07.41#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.19:34:07.41#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.19:34:07.41#ibcon#ireg 11 cls_cnt 2 2006.145.19:34:07.41#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.19:34:07.44#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.19:34:07.44#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.19:34:07.46#ibcon#[25=AT06-04\r\n] 2006.145.19:34:07.49#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.19:34:07.49#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.19:34:07.49#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.19:34:07.49#ibcon#ireg 7 cls_cnt 0 2006.145.19:34:07.49#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.19:34:07.61#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.19:34:07.61#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.19:34:07.63#ibcon#[25=USB\r\n] 2006.145.19:34:07.66#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.19:34:07.66#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.19:34:07.66#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.19:34:07.66#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.19:34:07.66$vck44/valo=7,864.99 2006.145.19:34:07.67#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.19:34:07.67#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.19:34:07.67#ibcon#ireg 17 cls_cnt 0 2006.145.19:34:07.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.19:34:07.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.19:34:07.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.19:34:07.68#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.19:34:07.72#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.19:34:07.72#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.19:34:07.72#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.19:34:07.72#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.19:34:07.72$vck44/va=7,4 2006.145.19:34:07.73#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.19:34:07.73#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.19:34:07.73#ibcon#ireg 11 cls_cnt 2 2006.145.19:34:07.73#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.19:34:07.77#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.19:34:07.77#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.19:34:07.79#ibcon#[25=AT07-04\r\n] 2006.145.19:34:07.82#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.19:34:07.82#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.19:34:07.82#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.19:34:07.82#ibcon#ireg 7 cls_cnt 0 2006.145.19:34:07.82#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.19:34:07.94#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.19:34:07.94#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.19:34:07.96#ibcon#[25=USB\r\n] 2006.145.19:34:07.99#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.19:34:07.99#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.19:34:07.99#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.19:34:07.99#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.19:34:08.00$vck44/valo=8,884.99 2006.145.19:34:08.00#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.19:34:08.00#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.19:34:08.00#ibcon#ireg 17 cls_cnt 0 2006.145.19:34:08.00#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.19:34:08.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.19:34:08.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.19:34:08.01#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.19:34:08.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.19:34:08.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.19:34:08.05#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.19:34:08.05#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.19:34:08.05$vck44/va=8,4 2006.145.19:34:08.06#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.19:34:08.06#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.19:34:08.06#ibcon#ireg 11 cls_cnt 2 2006.145.19:34:08.06#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.19:34:08.10#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.19:34:08.10#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.19:34:08.12#ibcon#[25=AT08-04\r\n] 2006.145.19:34:08.15#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.19:34:08.15#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.19:34:08.15#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.19:34:08.15#ibcon#ireg 7 cls_cnt 0 2006.145.19:34:08.15#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.19:34:08.27#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.19:34:08.27#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.19:34:08.29#ibcon#[25=USB\r\n] 2006.145.19:34:08.32#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.19:34:08.32#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.19:34:08.32#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.19:34:08.32#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.19:34:08.32$vck44/vblo=1,629.99 2006.145.19:34:08.33#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.19:34:08.33#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.19:34:08.33#ibcon#ireg 17 cls_cnt 0 2006.145.19:34:08.33#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.19:34:08.33#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.19:34:08.33#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.19:34:08.34#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.19:34:08.41#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.19:34:08.41#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.19:34:08.41#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.19:34:08.41#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.19:34:08.41$vck44/vb=1,3 2006.145.19:34:08.41#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.19:34:08.41#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.19:34:08.41#ibcon#ireg 11 cls_cnt 2 2006.145.19:34:08.41#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.19:34:08.41#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.19:34:08.41#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.19:34:08.42#ibcon#[27=AT01-03\r\n] 2006.145.19:34:08.45#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.19:34:08.45#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.19:34:08.45#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.19:34:08.45#ibcon#ireg 7 cls_cnt 0 2006.145.19:34:08.45#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.19:34:08.57#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.19:34:08.57#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.19:34:08.59#ibcon#[27=USB\r\n] 2006.145.19:34:08.62#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.19:34:08.62#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.19:34:08.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.19:34:08.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.19:34:08.62$vck44/vblo=2,634.99 2006.145.19:34:08.63#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.19:34:08.63#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.19:34:08.63#ibcon#ireg 17 cls_cnt 0 2006.145.19:34:08.63#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.19:34:08.63#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.19:34:08.63#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.19:34:08.64#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.19:34:08.68#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.19:34:08.68#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.19:34:08.68#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.19:34:08.68#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.19:34:08.68$vck44/vb=2,4 2006.145.19:34:08.69#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.19:34:08.69#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.19:34:08.69#ibcon#ireg 11 cls_cnt 2 2006.145.19:34:08.69#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.19:34:08.73#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.19:34:08.73#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.19:34:08.75#ibcon#[27=AT02-04\r\n] 2006.145.19:34:08.78#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.19:34:08.78#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.19:34:08.78#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.19:34:08.78#ibcon#ireg 7 cls_cnt 0 2006.145.19:34:08.78#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.19:34:08.90#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.19:34:08.90#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.19:34:08.92#ibcon#[27=USB\r\n] 2006.145.19:34:08.95#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.19:34:08.95#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.19:34:08.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.19:34:08.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.19:34:08.95$vck44/vblo=3,649.99 2006.145.19:34:08.96#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.19:34:08.96#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.19:34:08.96#ibcon#ireg 17 cls_cnt 0 2006.145.19:34:08.96#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.19:34:08.96#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.19:34:08.96#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.19:34:08.97#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.19:34:09.01#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.19:34:09.01#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.19:34:09.01#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.19:34:09.01#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.19:34:09.02$vck44/vb=3,4 2006.145.19:34:09.02#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.19:34:09.02#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.19:34:09.02#ibcon#ireg 11 cls_cnt 2 2006.145.19:34:09.02#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.19:34:09.06#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.19:34:09.06#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.19:34:09.08#ibcon#[27=AT03-04\r\n] 2006.145.19:34:09.11#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.19:34:09.11#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.19:34:09.11#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.19:34:09.11#ibcon#ireg 7 cls_cnt 0 2006.145.19:34:09.11#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.19:34:09.23#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.19:34:09.23#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.19:34:09.25#ibcon#[27=USB\r\n] 2006.145.19:34:09.28#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.19:34:09.28#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.19:34:09.28#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.19:34:09.28#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.19:34:09.28$vck44/vblo=4,679.99 2006.145.19:34:09.29#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.19:34:09.29#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.19:34:09.29#ibcon#ireg 17 cls_cnt 0 2006.145.19:34:09.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.19:34:09.29#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.19:34:09.29#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.19:34:09.30#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.19:34:09.34#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.19:34:09.34#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.19:34:09.34#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.19:34:09.34#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.19:34:09.34$vck44/vb=4,4 2006.145.19:34:09.34#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.19:34:09.34#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.19:34:09.35#ibcon#ireg 11 cls_cnt 2 2006.145.19:34:09.35#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.19:34:09.39#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.19:34:09.39#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.19:34:09.41#ibcon#[27=AT04-04\r\n] 2006.145.19:34:09.44#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.19:34:09.44#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.19:34:09.44#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.19:34:09.44#ibcon#ireg 7 cls_cnt 0 2006.145.19:34:09.44#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.19:34:09.56#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.19:34:09.56#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.19:34:09.58#ibcon#[27=USB\r\n] 2006.145.19:34:09.61#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.19:34:09.61#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.19:34:09.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.19:34:09.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.19:34:09.61$vck44/vblo=5,709.99 2006.145.19:34:09.62#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.19:34:09.62#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.19:34:09.62#ibcon#ireg 17 cls_cnt 0 2006.145.19:34:09.62#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.19:34:09.62#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.19:34:09.62#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.19:34:09.63#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.19:34:09.67#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.19:34:09.67#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.19:34:09.67#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.19:34:09.67#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.19:34:09.67$vck44/vb=5,4 2006.145.19:34:09.67#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.19:34:09.67#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.19:34:09.68#ibcon#ireg 11 cls_cnt 2 2006.145.19:34:09.68#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.19:34:09.72#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.19:34:09.72#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.19:34:09.74#ibcon#[27=AT05-04\r\n] 2006.145.19:34:09.77#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.19:34:09.77#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.19:34:09.77#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.19:34:09.77#ibcon#ireg 7 cls_cnt 0 2006.145.19:34:09.77#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.19:34:09.89#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.19:34:09.89#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.19:34:09.91#ibcon#[27=USB\r\n] 2006.145.19:34:09.94#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.19:34:09.94#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.19:34:09.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.19:34:09.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.19:34:09.94$vck44/vblo=6,719.99 2006.145.19:34:09.95#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.19:34:09.95#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.19:34:09.95#ibcon#ireg 17 cls_cnt 0 2006.145.19:34:09.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.19:34:09.95#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.19:34:09.95#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.19:34:09.96#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.19:34:10.00#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.19:34:10.00#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.19:34:10.00#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.19:34:10.00#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.19:34:10.00$vck44/vb=6,4 2006.145.19:34:10.01#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.19:34:10.01#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.19:34:10.01#ibcon#ireg 11 cls_cnt 2 2006.145.19:34:10.01#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.19:34:10.05#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.19:34:10.05#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.19:34:10.07#ibcon#[27=AT06-04\r\n] 2006.145.19:34:10.10#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.19:34:10.10#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.19:34:10.10#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.19:34:10.10#ibcon#ireg 7 cls_cnt 0 2006.145.19:34:10.10#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.19:34:10.22#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.19:34:10.22#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.19:34:10.24#ibcon#[27=USB\r\n] 2006.145.19:34:10.27#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.19:34:10.27#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.19:34:10.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.19:34:10.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.19:34:10.27$vck44/vblo=7,734.99 2006.145.19:34:10.28#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.19:34:10.28#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.19:34:10.28#ibcon#ireg 17 cls_cnt 0 2006.145.19:34:10.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.19:34:10.28#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.19:34:10.28#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.19:34:10.29#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.19:34:10.33#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.19:34:10.33#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.19:34:10.33#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.19:34:10.33#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.19:34:10.33$vck44/vb=7,4 2006.145.19:34:10.33#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.19:34:10.33#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.19:34:10.33#ibcon#ireg 11 cls_cnt 2 2006.145.19:34:10.33#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.19:34:10.39#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.19:34:10.39#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.19:34:10.41#ibcon#[27=AT07-04\r\n] 2006.145.19:34:10.44#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.19:34:10.44#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.19:34:10.44#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.19:34:10.44#ibcon#ireg 7 cls_cnt 0 2006.145.19:34:10.44#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.19:34:10.56#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.19:34:10.56#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.19:34:10.58#ibcon#[27=USB\r\n] 2006.145.19:34:10.61#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.19:34:10.61#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.19:34:10.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.19:34:10.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.19:34:10.61$vck44/vblo=8,744.99 2006.145.19:34:10.61#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.19:34:10.61#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.19:34:10.61#ibcon#ireg 17 cls_cnt 0 2006.145.19:34:10.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.19:34:10.61#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.19:34:10.61#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.19:34:10.63#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.19:34:10.67#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.19:34:10.67#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.19:34:10.67#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.19:34:10.67#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.19:34:10.67$vck44/vb=8,4 2006.145.19:34:10.67#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.19:34:10.67#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.19:34:10.67#ibcon#ireg 11 cls_cnt 2 2006.145.19:34:10.67#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.19:34:10.73#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.19:34:10.73#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.19:34:10.75#ibcon#[27=AT08-04\r\n] 2006.145.19:34:10.78#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.19:34:10.78#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.19:34:10.78#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.19:34:10.78#ibcon#ireg 7 cls_cnt 0 2006.145.19:34:10.78#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.19:34:10.90#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.19:34:10.90#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.19:34:10.92#ibcon#[27=USB\r\n] 2006.145.19:34:10.95#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.19:34:10.95#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.19:34:10.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.19:34:10.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.19:34:10.95$vck44/vabw=wide 2006.145.19:34:10.95#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.19:34:10.95#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.19:34:10.95#ibcon#ireg 8 cls_cnt 0 2006.145.19:34:10.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.19:34:10.95#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.19:34:10.95#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.19:34:10.97#ibcon#[25=BW32\r\n] 2006.145.19:34:11.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.19:34:11.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.19:34:11.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.19:34:11.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.19:34:11.00$vck44/vbbw=wide 2006.145.19:34:11.00#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.19:34:11.00#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.19:34:11.00#ibcon#ireg 8 cls_cnt 0 2006.145.19:34:11.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:34:11.07#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:34:11.07#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:34:11.09#ibcon#[27=BW32\r\n] 2006.145.19:34:11.12#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:34:11.12#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:34:11.12#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.19:34:11.12#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.19:34:11.12$setupk4/ifdk4 2006.145.19:34:11.12$ifdk4/lo= 2006.145.19:34:11.13$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.19:34:11.13$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.19:34:11.13$ifdk4/patch= 2006.145.19:34:11.13$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.19:34:11.13$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.19:34:11.13$setupk4/!*+20s 2006.145.19:34:14.02#abcon#<5=/07 1.2 2.3 15.87 871020.0\r\n> 2006.145.19:34:14.04#abcon#{5=INTERFACE CLEAR} 2006.145.19:34:14.10#abcon#[5=S1D000X0/0*\r\n] 2006.145.19:34:24.19#abcon#<5=/07 1.2 2.3 15.87 871020.0\r\n> 2006.145.19:34:24.21#abcon#{5=INTERFACE CLEAR} 2006.145.19:34:24.27#abcon#[5=S1D000X0/0*\r\n] 2006.145.19:34:25.72$setupk4/"tpicd 2006.145.19:34:25.72$setupk4/echo=off 2006.145.19:34:25.72$setupk4/xlog=off 2006.145.19:34:25.72:!2006.145.19:39:11 2006.145.19:34:29.13#trakl#Source acquired 2006.145.19:34:31.14#flagr#flagr/antenna,acquired 2006.145.19:39:11.00:preob 2006.145.19:39:11.14/onsource/TRACKING 2006.145.19:39:11.14:!2006.145.19:39:21 2006.145.19:39:21.00:"tape 2006.145.19:39:21.00:"st=record 2006.145.19:39:21.00:data_valid=on 2006.145.19:39:21.00:midob 2006.145.19:39:22.14/onsource/TRACKING 2006.145.19:39:22.14/wx/15.87,1020.1,88 2006.145.19:39:22.28/cable/+6.5504E-03 2006.145.19:39:23.37/va/01,08,usb,yes,28,30 2006.145.19:39:23.37/va/02,07,usb,yes,30,31 2006.145.19:39:23.37/va/03,08,usb,yes,27,29 2006.145.19:39:23.37/va/04,07,usb,yes,31,33 2006.145.19:39:23.37/va/05,04,usb,yes,27,28 2006.145.19:39:23.37/va/06,04,usb,yes,31,30 2006.145.19:39:23.37/va/07,04,usb,yes,31,32 2006.145.19:39:23.37/va/08,04,usb,yes,26,32 2006.145.19:39:23.60/valo/01,524.99,yes,locked 2006.145.19:39:23.60/valo/02,534.99,yes,locked 2006.145.19:39:23.60/valo/03,564.99,yes,locked 2006.145.19:39:23.60/valo/04,624.99,yes,locked 2006.145.19:39:23.60/valo/05,734.99,yes,locked 2006.145.19:39:23.60/valo/06,814.99,yes,locked 2006.145.19:39:23.60/valo/07,864.99,yes,locked 2006.145.19:39:23.60/valo/08,884.99,yes,locked 2006.145.19:39:24.69/vb/01,03,usb,yes,36,33 2006.145.19:39:24.69/vb/02,04,usb,yes,31,31 2006.145.19:39:24.69/vb/03,04,usb,yes,28,31 2006.145.19:39:24.69/vb/04,04,usb,yes,32,31 2006.145.19:39:24.69/vb/05,04,usb,yes,25,28 2006.145.19:39:24.69/vb/06,04,usb,yes,29,26 2006.145.19:39:24.69/vb/07,04,usb,yes,29,29 2006.145.19:39:24.69/vb/08,04,usb,yes,27,30 2006.145.19:39:24.92/vblo/01,629.99,yes,locked 2006.145.19:39:24.92/vblo/02,634.99,yes,locked 2006.145.19:39:24.92/vblo/03,649.99,yes,locked 2006.145.19:39:24.92/vblo/04,679.99,yes,locked 2006.145.19:39:24.92/vblo/05,709.99,yes,locked 2006.145.19:39:24.92/vblo/06,719.99,yes,locked 2006.145.19:39:24.92/vblo/07,734.99,yes,locked 2006.145.19:39:24.92/vblo/08,744.99,yes,locked 2006.145.19:39:25.07/vabw/8 2006.145.19:39:25.22/vbbw/8 2006.145.19:39:25.31/xfe/off,on,16.0 2006.145.19:39:25.69/ifatt/23,28,28,28 2006.145.19:39:26.07/fmout-gps/S +5.4E-08 2006.145.19:39:26.12:!2006.145.19:46:11 2006.145.19:46:11.00:data_valid=off 2006.145.19:46:11.01:"et 2006.145.19:46:11.01:!+3s 2006.145.19:46:14.02:"tape 2006.145.19:46:14.03:postob 2006.145.19:46:14.11/cable/+6.5500E-03 2006.145.19:46:14.12/wx/15.94,1020.1,87 2006.145.19:46:14.19/fmout-gps/S +5.3E-08 2006.145.19:46:14.19:scan_name=145-1952,jd0605,80 2006.145.19:46:14.19:source=2121+053,212344.52,053522.1,2000.0,cw 2006.145.19:46:15.14#flagr#flagr/antenna,new-source 2006.145.19:46:15.15:checkk5 2006.145.19:46:15.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.19:46:16.00/chk_autoobs//k5ts2/ autoobs is running! 2006.145.19:46:16.43/chk_autoobs//k5ts3/ autoobs is running! 2006.145.19:46:16.87/chk_autoobs//k5ts4/ autoobs is running! 2006.145.19:46:17.31/chk_obsdata//k5ts1/T1451939??a.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.145.19:46:17.74/chk_obsdata//k5ts2/T1451939??b.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.145.19:46:18.17/chk_obsdata//k5ts3/T1451939??c.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.145.19:46:18.61/chk_obsdata//k5ts4/T1451939??d.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.145.19:46:19.36/k5log//k5ts1_log_newline 2006.145.19:46:20.09/k5log//k5ts2_log_newline 2006.145.19:46:20.83/k5log//k5ts3_log_newline 2006.145.19:46:21.60/k5log//k5ts4_log_newline 2006.145.19:46:21.63/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.19:46:21.63:setupk4=1 2006.145.19:46:21.63$setupk4/echo=on 2006.145.19:46:21.63$setupk4/pcalon 2006.145.19:46:21.63$pcalon/"no phase cal control is implemented here 2006.145.19:46:21.63$setupk4/"tpicd=stop 2006.145.19:46:21.63$setupk4/"rec=synch_on 2006.145.19:46:21.63$setupk4/"rec_mode=128 2006.145.19:46:21.63$setupk4/!* 2006.145.19:46:21.63$setupk4/recpk4 2006.145.19:46:21.63$recpk4/recpatch= 2006.145.19:46:21.63$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.19:46:21.64$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.19:46:21.64$setupk4/vck44 2006.145.19:46:21.64$vck44/valo=1,524.99 2006.145.19:46:21.64#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.19:46:21.64#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.19:46:21.64#ibcon#ireg 17 cls_cnt 0 2006.145.19:46:21.64#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.19:46:21.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.19:46:21.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.19:46:21.67#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.19:46:21.72#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.19:46:21.72#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.19:46:21.72#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.19:46:21.72#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.19:46:21.72$vck44/va=1,8 2006.145.19:46:21.72#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.19:46:21.72#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.19:46:21.72#ibcon#ireg 11 cls_cnt 2 2006.145.19:46:21.72#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.19:46:21.72#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.19:46:21.72#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.19:46:21.74#ibcon#[25=AT01-08\r\n] 2006.145.19:46:21.77#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.19:46:21.77#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.19:46:21.77#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.19:46:21.77#ibcon#ireg 7 cls_cnt 0 2006.145.19:46:21.77#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.19:46:21.89#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.19:46:21.89#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.19:46:21.91#ibcon#[25=USB\r\n] 2006.145.19:46:21.96#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.19:46:21.96#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.19:46:21.96#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.19:46:21.96#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.19:46:21.96$vck44/valo=2,534.99 2006.145.19:46:21.96#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.19:46:21.96#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.19:46:21.96#ibcon#ireg 17 cls_cnt 0 2006.145.19:46:21.96#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.19:46:21.96#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.19:46:21.96#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.19:46:21.98#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.19:46:22.02#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.19:46:22.02#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.19:46:22.02#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.19:46:22.02#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.19:46:22.02$vck44/va=2,7 2006.145.19:46:22.02#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.19:46:22.02#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.19:46:22.02#ibcon#ireg 11 cls_cnt 2 2006.145.19:46:22.02#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.19:46:22.08#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.19:46:22.08#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.19:46:22.10#ibcon#[25=AT02-07\r\n] 2006.145.19:46:22.13#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.19:46:22.13#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.19:46:22.13#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.19:46:22.13#ibcon#ireg 7 cls_cnt 0 2006.145.19:46:22.13#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.19:46:22.25#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.19:46:22.25#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.19:46:22.27#ibcon#[25=USB\r\n] 2006.145.19:46:22.30#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.19:46:22.30#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.19:46:22.30#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.19:46:22.30#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.19:46:22.30$vck44/valo=3,564.99 2006.145.19:46:22.30#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.19:46:22.30#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.19:46:22.30#ibcon#ireg 17 cls_cnt 0 2006.145.19:46:22.30#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.19:46:22.30#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.19:46:22.30#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.19:46:22.32#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.19:46:22.36#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.19:46:22.36#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.19:46:22.36#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.19:46:22.36#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.19:46:22.36$vck44/va=3,8 2006.145.19:46:22.36#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.19:46:22.36#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.19:46:22.36#ibcon#ireg 11 cls_cnt 2 2006.145.19:46:22.36#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.19:46:22.42#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.19:46:22.42#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.19:46:22.44#ibcon#[25=AT03-08\r\n] 2006.145.19:46:22.47#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.19:46:22.47#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.19:46:22.47#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.19:46:22.47#ibcon#ireg 7 cls_cnt 0 2006.145.19:46:22.47#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.19:46:22.59#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.19:46:22.59#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.19:46:22.61#ibcon#[25=USB\r\n] 2006.145.19:46:22.64#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.19:46:22.64#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.19:46:22.64#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.19:46:22.64#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.19:46:22.64$vck44/valo=4,624.99 2006.145.19:46:22.64#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.19:46:22.64#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.19:46:22.64#ibcon#ireg 17 cls_cnt 0 2006.145.19:46:22.64#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.19:46:22.64#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.19:46:22.64#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.19:46:22.66#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.19:46:22.70#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.19:46:22.70#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.19:46:22.70#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.19:46:22.70#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.19:46:22.70$vck44/va=4,7 2006.145.19:46:22.70#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.19:46:22.70#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.19:46:22.70#ibcon#ireg 11 cls_cnt 2 2006.145.19:46:22.70#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.19:46:22.76#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.19:46:22.76#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.19:46:22.78#ibcon#[25=AT04-07\r\n] 2006.145.19:46:22.81#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.19:46:22.81#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.19:46:22.81#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.19:46:22.81#ibcon#ireg 7 cls_cnt 0 2006.145.19:46:22.81#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.19:46:22.93#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.19:46:22.93#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.19:46:22.96#ibcon#[25=USB\r\n] 2006.145.19:46:22.98#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.19:46:22.98#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.19:46:22.98#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.19:46:22.98#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.19:46:22.98$vck44/valo=5,734.99 2006.145.19:46:22.98#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.19:46:22.98#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.19:46:22.98#ibcon#ireg 17 cls_cnt 0 2006.145.19:46:22.98#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:46:22.98#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:46:22.98#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:46:23.00#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.19:46:23.04#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:46:23.04#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:46:23.04#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.19:46:23.04#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.19:46:23.04$vck44/va=5,4 2006.145.19:46:23.04#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.19:46:23.04#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.19:46:23.04#ibcon#ireg 11 cls_cnt 2 2006.145.19:46:23.04#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.19:46:23.10#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.19:46:23.10#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.19:46:23.13#ibcon#[25=AT05-04\r\n] 2006.145.19:46:23.16#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.19:46:23.16#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.19:46:23.16#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.19:46:23.16#ibcon#ireg 7 cls_cnt 0 2006.145.19:46:23.16#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.19:46:23.28#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.19:46:23.28#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.19:46:23.30#ibcon#[25=USB\r\n] 2006.145.19:46:23.33#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.19:46:23.33#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.19:46:23.33#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.19:46:23.33#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.19:46:23.33$vck44/valo=6,814.99 2006.145.19:46:23.33#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.19:46:23.33#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.19:46:23.33#ibcon#ireg 17 cls_cnt 0 2006.145.19:46:23.33#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.19:46:23.33#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.19:46:23.33#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.19:46:23.35#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.19:46:23.39#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.19:46:23.39#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.19:46:23.39#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.19:46:23.39#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.19:46:23.39$vck44/va=6,4 2006.145.19:46:23.39#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.19:46:23.39#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.19:46:23.39#ibcon#ireg 11 cls_cnt 2 2006.145.19:46:23.39#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.19:46:23.45#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.19:46:23.45#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.19:46:23.47#ibcon#[25=AT06-04\r\n] 2006.145.19:46:23.50#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.19:46:23.50#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.19:46:23.50#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.19:46:23.50#ibcon#ireg 7 cls_cnt 0 2006.145.19:46:23.50#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.19:46:23.62#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.19:46:23.62#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.19:46:23.64#ibcon#[25=USB\r\n] 2006.145.19:46:23.67#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.19:46:23.67#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.19:46:23.67#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.19:46:23.67#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.19:46:23.67$vck44/valo=7,864.99 2006.145.19:46:23.67#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.19:46:23.67#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.19:46:23.67#ibcon#ireg 17 cls_cnt 0 2006.145.19:46:23.67#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.19:46:23.67#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.19:46:23.67#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.19:46:23.69#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.19:46:23.73#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.19:46:23.73#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.19:46:23.73#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.19:46:23.73#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.19:46:23.73$vck44/va=7,4 2006.145.19:46:23.73#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.19:46:23.73#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.19:46:23.73#ibcon#ireg 11 cls_cnt 2 2006.145.19:46:23.73#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.19:46:23.79#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.19:46:23.79#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.19:46:23.81#ibcon#[25=AT07-04\r\n] 2006.145.19:46:23.84#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.19:46:23.84#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.19:46:23.84#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.19:46:23.84#ibcon#ireg 7 cls_cnt 0 2006.145.19:46:23.84#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.19:46:23.96#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.19:46:23.96#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.19:46:23.98#ibcon#[25=USB\r\n] 2006.145.19:46:24.01#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.19:46:24.01#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.19:46:24.01#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.19:46:24.01#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.19:46:24.01$vck44/valo=8,884.99 2006.145.19:46:24.01#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.19:46:24.01#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.19:46:24.01#ibcon#ireg 17 cls_cnt 0 2006.145.19:46:24.01#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.19:46:24.01#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.19:46:24.01#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.19:46:24.03#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.19:46:24.07#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.19:46:24.07#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.19:46:24.07#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.19:46:24.07#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.19:46:24.07$vck44/va=8,4 2006.145.19:46:24.07#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.19:46:24.07#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.19:46:24.07#ibcon#ireg 11 cls_cnt 2 2006.145.19:46:24.07#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.19:46:24.13#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.19:46:24.13#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.19:46:24.15#ibcon#[25=AT08-04\r\n] 2006.145.19:46:24.18#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.19:46:24.18#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.19:46:24.18#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.19:46:24.18#ibcon#ireg 7 cls_cnt 0 2006.145.19:46:24.18#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.19:46:24.30#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.19:46:24.30#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.19:46:24.32#ibcon#[25=USB\r\n] 2006.145.19:46:24.35#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.19:46:24.35#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.19:46:24.35#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.19:46:24.35#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.19:46:24.35$vck44/vblo=1,629.99 2006.145.19:46:24.35#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.19:46:24.35#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.19:46:24.35#ibcon#ireg 17 cls_cnt 0 2006.145.19:46:24.35#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.19:46:24.35#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.19:46:24.35#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.19:46:24.37#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.19:46:24.41#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.19:46:24.41#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.19:46:24.41#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.19:46:24.41#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.19:46:24.41$vck44/vb=1,3 2006.145.19:46:24.41#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.19:46:24.41#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.19:46:24.41#ibcon#ireg 11 cls_cnt 2 2006.145.19:46:24.41#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.19:46:24.41#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.19:46:24.41#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.19:46:24.43#ibcon#[27=AT01-03\r\n] 2006.145.19:46:24.46#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.19:46:24.46#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.19:46:24.46#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.19:46:24.46#ibcon#ireg 7 cls_cnt 0 2006.145.19:46:24.46#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.19:46:24.58#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.19:46:24.58#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.19:46:24.60#ibcon#[27=USB\r\n] 2006.145.19:46:24.63#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.19:46:24.63#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.19:46:24.63#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.19:46:24.63#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.19:46:24.63$vck44/vblo=2,634.99 2006.145.19:46:24.63#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.19:46:24.63#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.19:46:24.63#ibcon#ireg 17 cls_cnt 0 2006.145.19:46:24.63#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.19:46:24.63#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.19:46:24.63#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.19:46:24.65#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.19:46:24.69#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.19:46:24.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.19:46:24.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.19:46:24.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.19:46:24.69$vck44/vb=2,4 2006.145.19:46:24.69#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.19:46:24.69#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.19:46:24.69#ibcon#ireg 11 cls_cnt 2 2006.145.19:46:24.69#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.19:46:24.75#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.19:46:24.75#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.19:46:24.77#ibcon#[27=AT02-04\r\n] 2006.145.19:46:24.80#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.19:46:24.80#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.19:46:24.80#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.19:46:24.80#ibcon#ireg 7 cls_cnt 0 2006.145.19:46:24.80#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.19:46:24.92#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.19:46:24.92#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.19:46:24.94#ibcon#[27=USB\r\n] 2006.145.19:46:24.97#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.19:46:24.97#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.19:46:24.97#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.19:46:24.97#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.19:46:24.97$vck44/vblo=3,649.99 2006.145.19:46:24.97#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.19:46:24.97#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.19:46:24.97#ibcon#ireg 17 cls_cnt 0 2006.145.19:46:24.97#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.19:46:24.97#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.19:46:24.97#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.19:46:24.99#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.19:46:25.03#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.19:46:25.03#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.19:46:25.03#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.19:46:25.03#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.19:46:25.03$vck44/vb=3,4 2006.145.19:46:25.03#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.19:46:25.03#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.19:46:25.03#ibcon#ireg 11 cls_cnt 2 2006.145.19:46:25.03#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.19:46:25.09#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.19:46:25.09#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.19:46:25.11#ibcon#[27=AT03-04\r\n] 2006.145.19:46:25.14#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.19:46:25.14#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.19:46:25.14#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.19:46:25.14#ibcon#ireg 7 cls_cnt 0 2006.145.19:46:25.14#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.19:46:25.26#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.19:46:25.26#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.19:46:25.28#ibcon#[27=USB\r\n] 2006.145.19:46:25.31#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.19:46:25.31#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.19:46:25.31#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.19:46:25.31#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.19:46:25.31$vck44/vblo=4,679.99 2006.145.19:46:25.31#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.19:46:25.31#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.19:46:25.31#ibcon#ireg 17 cls_cnt 0 2006.145.19:46:25.31#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.19:46:25.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.19:46:25.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.19:46:25.33#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.19:46:25.37#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.19:46:25.37#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.19:46:25.37#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.19:46:25.37#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.19:46:25.37$vck44/vb=4,4 2006.145.19:46:25.37#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.19:46:25.37#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.19:46:25.37#ibcon#ireg 11 cls_cnt 2 2006.145.19:46:25.37#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.19:46:25.43#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.19:46:25.43#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.19:46:25.45#ibcon#[27=AT04-04\r\n] 2006.145.19:46:25.48#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.19:46:25.48#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.19:46:25.48#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.19:46:25.48#ibcon#ireg 7 cls_cnt 0 2006.145.19:46:25.48#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.19:46:25.60#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.19:46:25.60#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.19:46:25.62#ibcon#[27=USB\r\n] 2006.145.19:46:25.65#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.19:46:25.65#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.19:46:25.65#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.19:46:25.65#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.19:46:25.65$vck44/vblo=5,709.99 2006.145.19:46:25.65#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.19:46:25.65#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.19:46:25.65#ibcon#ireg 17 cls_cnt 0 2006.145.19:46:25.65#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.19:46:25.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.19:46:25.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.19:46:25.67#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.19:46:25.71#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.19:46:25.71#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.19:46:25.71#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.19:46:25.71#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.19:46:25.71$vck44/vb=5,4 2006.145.19:46:25.71#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.19:46:25.71#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.19:46:25.71#ibcon#ireg 11 cls_cnt 2 2006.145.19:46:25.71#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.19:46:25.77#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.19:46:25.77#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.19:46:25.79#ibcon#[27=AT05-04\r\n] 2006.145.19:46:25.82#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.19:46:25.82#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.19:46:25.82#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.19:46:25.82#ibcon#ireg 7 cls_cnt 0 2006.145.19:46:25.82#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.19:46:25.94#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.19:46:25.94#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.19:46:25.96#ibcon#[27=USB\r\n] 2006.145.19:46:25.99#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.19:46:25.99#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.19:46:25.99#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.19:46:25.99#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.19:46:25.99$vck44/vblo=6,719.99 2006.145.19:46:25.99#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.19:46:25.99#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.19:46:25.99#ibcon#ireg 17 cls_cnt 0 2006.145.19:46:25.99#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:46:25.99#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:46:25.99#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:46:26.01#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.19:46:26.05#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:46:26.05#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.19:46:26.05#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.19:46:26.05#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.19:46:26.05$vck44/vb=6,4 2006.145.19:46:26.05#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.19:46:26.05#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.19:46:26.05#ibcon#ireg 11 cls_cnt 2 2006.145.19:46:26.05#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.19:46:26.11#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.19:46:26.11#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.19:46:26.13#ibcon#[27=AT06-04\r\n] 2006.145.19:46:26.16#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.19:46:26.16#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.19:46:26.16#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.19:46:26.16#ibcon#ireg 7 cls_cnt 0 2006.145.19:46:26.16#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.19:46:26.28#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.19:46:26.28#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.19:46:26.30#ibcon#[27=USB\r\n] 2006.145.19:46:26.33#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.19:46:26.33#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.19:46:26.33#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.19:46:26.33#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.19:46:26.33$vck44/vblo=7,734.99 2006.145.19:46:26.33#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.19:46:26.33#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.19:46:26.33#ibcon#ireg 17 cls_cnt 0 2006.145.19:46:26.33#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.19:46:26.33#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.19:46:26.33#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.19:46:26.35#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.19:46:26.39#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.19:46:26.39#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.19:46:26.39#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.19:46:26.39#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.19:46:26.39$vck44/vb=7,4 2006.145.19:46:26.39#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.19:46:26.39#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.19:46:26.39#ibcon#ireg 11 cls_cnt 2 2006.145.19:46:26.39#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.19:46:26.45#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.19:46:26.45#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.19:46:26.47#ibcon#[27=AT07-04\r\n] 2006.145.19:46:26.50#abcon#<5=/08 1.0 2.6 15.94 871020.1\r\n> 2006.145.19:46:26.50#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.19:46:26.50#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.19:46:26.50#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.19:46:26.50#ibcon#ireg 7 cls_cnt 0 2006.145.19:46:26.50#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.19:46:26.52#abcon#{5=INTERFACE CLEAR} 2006.145.19:46:26.58#abcon#[5=S1D000X0/0*\r\n] 2006.145.19:46:26.62#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.19:46:26.62#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.19:46:26.64#ibcon#[27=USB\r\n] 2006.145.19:46:26.67#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.19:46:26.67#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.19:46:26.67#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.19:46:26.67#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.19:46:26.67$vck44/vblo=8,744.99 2006.145.19:46:26.67#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.19:46:26.67#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.19:46:26.67#ibcon#ireg 17 cls_cnt 0 2006.145.19:46:26.67#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.19:46:26.67#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.19:46:26.67#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.19:46:26.69#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.19:46:26.73#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.19:46:26.73#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.19:46:26.73#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.19:46:26.73#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.19:46:26.73$vck44/vb=8,4 2006.145.19:46:26.73#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.19:46:26.73#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.19:46:26.73#ibcon#ireg 11 cls_cnt 2 2006.145.19:46:26.73#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.19:46:26.79#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.19:46:26.79#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.19:46:26.81#ibcon#[27=AT08-04\r\n] 2006.145.19:46:26.84#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.19:46:26.84#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.19:46:26.84#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.19:46:26.84#ibcon#ireg 7 cls_cnt 0 2006.145.19:46:26.84#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.19:46:26.96#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.19:46:26.96#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.19:46:26.98#ibcon#[27=USB\r\n] 2006.145.19:46:27.01#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.19:46:27.01#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.19:46:27.01#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.19:46:27.01#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.19:46:27.01$vck44/vabw=wide 2006.145.19:46:27.01#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.19:46:27.01#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.19:46:27.01#ibcon#ireg 8 cls_cnt 0 2006.145.19:46:27.01#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.19:46:27.01#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.19:46:27.01#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.19:46:27.03#ibcon#[25=BW32\r\n] 2006.145.19:46:27.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.19:46:27.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.19:46:27.06#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.19:46:27.06#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.19:46:27.06$vck44/vbbw=wide 2006.145.19:46:27.06#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.19:46:27.06#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.19:46:27.06#ibcon#ireg 8 cls_cnt 0 2006.145.19:46:27.06#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:46:27.13#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:46:27.13#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:46:27.15#ibcon#[27=BW32\r\n] 2006.145.19:46:27.18#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:46:27.18#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:46:27.18#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.19:46:27.18#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.19:46:27.18$setupk4/ifdk4 2006.145.19:46:27.18$ifdk4/lo= 2006.145.19:46:27.18$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.19:46:27.18$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.19:46:27.18$ifdk4/patch= 2006.145.19:46:27.18$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.19:46:27.18$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.19:46:27.18$setupk4/!*+20s 2006.145.19:46:36.67#abcon#<5=/08 1.0 2.6 15.94 871020.1\r\n> 2006.145.19:46:36.69#abcon#{5=INTERFACE CLEAR} 2006.145.19:46:36.76#abcon#[5=S1D000X0/0*\r\n] 2006.145.19:46:41.64$setupk4/"tpicd 2006.145.19:46:41.64$setupk4/echo=off 2006.145.19:46:41.64$setupk4/xlog=off 2006.145.19:46:41.64:!2006.145.19:52:22 2006.145.19:47:07.14#trakl#Source acquired 2006.145.19:47:07.14#flagr#flagr/antenna,acquired 2006.145.19:52:22.00:preob 2006.145.19:52:23.14/onsource/TRACKING 2006.145.19:52:23.14:!2006.145.19:52:32 2006.145.19:52:32.00:"tape 2006.145.19:52:32.00:"st=record 2006.145.19:52:32.00:data_valid=on 2006.145.19:52:32.00:midob 2006.145.19:52:32.14/onsource/TRACKING 2006.145.19:52:32.14/wx/15.93,1020.0,88 2006.145.19:52:32.25/cable/+6.5506E-03 2006.145.19:52:33.34/va/01,08,usb,yes,28,30 2006.145.19:52:33.34/va/02,07,usb,yes,30,31 2006.145.19:52:33.34/va/03,08,usb,yes,27,28 2006.145.19:52:33.34/va/04,07,usb,yes,31,33 2006.145.19:52:33.34/va/05,04,usb,yes,27,27 2006.145.19:52:33.34/va/06,04,usb,yes,30,30 2006.145.19:52:33.34/va/07,04,usb,yes,31,32 2006.145.19:52:33.34/va/08,04,usb,yes,26,31 2006.145.19:52:33.57/valo/01,524.99,yes,locked 2006.145.19:52:33.57/valo/02,534.99,yes,locked 2006.145.19:52:33.57/valo/03,564.99,yes,locked 2006.145.19:52:33.57/valo/04,624.99,yes,locked 2006.145.19:52:33.57/valo/05,734.99,yes,locked 2006.145.19:52:33.57/valo/06,814.99,yes,locked 2006.145.19:52:33.57/valo/07,864.99,yes,locked 2006.145.19:52:33.57/valo/08,884.99,yes,locked 2006.145.19:52:34.66/vb/01,03,usb,yes,35,33 2006.145.19:52:34.66/vb/02,04,usb,yes,31,31 2006.145.19:52:34.66/vb/03,04,usb,yes,28,31 2006.145.19:52:34.66/vb/04,04,usb,yes,32,31 2006.145.19:52:34.66/vb/05,04,usb,yes,25,27 2006.145.19:52:34.66/vb/06,04,usb,yes,29,26 2006.145.19:52:34.66/vb/07,04,usb,yes,29,29 2006.145.19:52:34.66/vb/08,04,usb,yes,27,30 2006.145.19:52:34.90/vblo/01,629.99,yes,locked 2006.145.19:52:34.90/vblo/02,634.99,yes,locked 2006.145.19:52:34.90/vblo/03,649.99,yes,locked 2006.145.19:52:34.90/vblo/04,679.99,yes,locked 2006.145.19:52:34.90/vblo/05,709.99,yes,locked 2006.145.19:52:34.90/vblo/06,719.99,yes,locked 2006.145.19:52:34.90/vblo/07,734.99,yes,locked 2006.145.19:52:34.90/vblo/08,744.99,yes,locked 2006.145.19:52:35.05/vabw/8 2006.145.19:52:35.20/vbbw/8 2006.145.19:52:35.41/xfe/off,on,14.5 2006.145.19:52:35.78/ifatt/23,28,28,28 2006.145.19:52:36.07/fmout-gps/S +5.1E-08 2006.145.19:52:36.11:!2006.145.19:53:52 2006.145.19:53:52.00:data_valid=off 2006.145.19:53:52.00:"et 2006.145.19:53:52.01:!+3s 2006.145.19:53:55.02:"tape 2006.145.19:53:55.02:postob 2006.145.19:53:55.10/cable/+6.5485E-03 2006.145.19:53:55.10/wx/15.92,1020.0,88 2006.145.19:53:55.18/fmout-gps/S +5.1E-08 2006.145.19:53:55.18:scan_name=145-1955,jd0605,40 2006.145.19:53:55.19:source=1954-388,195800.00,-384506.4,2000.0,cw 2006.145.19:53:56.14#flagr#flagr/antenna,new-source 2006.145.19:53:56.14:checkk5 2006.145.19:53:56.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.19:53:57.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.19:53:57.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.19:53:57.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.19:53:58.32/chk_obsdata//k5ts1/T1451952??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.19:53:58.77/chk_obsdata//k5ts2/T1451952??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.19:53:59.22/chk_obsdata//k5ts3/T1451952??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.19:53:59.67/chk_obsdata//k5ts4/T1451952??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.19:54:00.44/k5log//k5ts1_log_newline 2006.145.19:54:01.17/k5log//k5ts2_log_newline 2006.145.19:54:01.91/k5log//k5ts3_log_newline 2006.145.19:54:02.66/k5log//k5ts4_log_newline 2006.145.19:54:02.68/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.19:54:02.68:setupk4=1 2006.145.19:54:02.68$setupk4/echo=on 2006.145.19:54:02.68$setupk4/pcalon 2006.145.19:54:02.68$pcalon/"no phase cal control is implemented here 2006.145.19:54:02.68$setupk4/"tpicd=stop 2006.145.19:54:02.68$setupk4/"rec=synch_on 2006.145.19:54:02.68$setupk4/"rec_mode=128 2006.145.19:54:02.68$setupk4/!* 2006.145.19:54:02.68$setupk4/recpk4 2006.145.19:54:02.68$recpk4/recpatch= 2006.145.19:54:02.68$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.19:54:02.68$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.19:54:02.68$setupk4/vck44 2006.145.19:54:02.68$vck44/valo=1,524.99 2006.145.19:54:02.68#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.19:54:02.68#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.19:54:02.68#ibcon#ireg 17 cls_cnt 0 2006.145.19:54:02.68#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.19:54:02.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.19:54:02.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.19:54:02.72#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.19:54:02.77#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.19:54:02.77#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.19:54:02.77#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.19:54:02.77#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.19:54:02.77$vck44/va=1,8 2006.145.19:54:02.77#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.19:54:02.77#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.19:54:02.77#ibcon#ireg 11 cls_cnt 2 2006.145.19:54:02.77#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.19:54:02.77#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.19:54:02.77#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.19:54:02.79#ibcon#[25=AT01-08\r\n] 2006.145.19:54:02.82#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.19:54:02.82#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.19:54:02.82#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.19:54:02.82#ibcon#ireg 7 cls_cnt 0 2006.145.19:54:02.82#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.19:54:02.94#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.19:54:02.94#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.19:54:02.96#ibcon#[25=USB\r\n] 2006.145.19:54:02.99#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.19:54:02.99#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.19:54:02.99#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.19:54:02.99#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.19:54:02.99$vck44/valo=2,534.99 2006.145.19:54:02.99#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.19:54:02.99#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.19:54:02.99#ibcon#ireg 17 cls_cnt 0 2006.145.19:54:02.99#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:54:02.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:54:02.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:54:03.02#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.19:54:03.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:54:03.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:54:03.06#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.19:54:03.06#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.19:54:03.06$vck44/va=2,7 2006.145.19:54:03.06#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.19:54:03.06#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.19:54:03.06#ibcon#ireg 11 cls_cnt 2 2006.145.19:54:03.06#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:54:03.11#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:54:03.11#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:54:03.13#ibcon#[25=AT02-07\r\n] 2006.145.19:54:03.16#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:54:03.16#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:54:03.16#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.19:54:03.16#ibcon#ireg 7 cls_cnt 0 2006.145.19:54:03.16#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:54:03.28#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:54:03.28#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:54:03.30#ibcon#[25=USB\r\n] 2006.145.19:54:03.33#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:54:03.33#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:54:03.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.19:54:03.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.19:54:03.33$vck44/valo=3,564.99 2006.145.19:54:03.33#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.19:54:03.33#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.19:54:03.33#ibcon#ireg 17 cls_cnt 0 2006.145.19:54:03.33#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:54:03.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:54:03.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:54:03.35#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.19:54:03.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:54:03.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:54:03.39#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.19:54:03.39#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.19:54:03.39$vck44/va=3,8 2006.145.19:54:03.39#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.19:54:03.39#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.19:54:03.39#ibcon#ireg 11 cls_cnt 2 2006.145.19:54:03.39#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:54:03.45#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:54:03.45#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:54:03.47#ibcon#[25=AT03-08\r\n] 2006.145.19:54:03.50#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:54:03.50#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:54:03.50#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.19:54:03.50#ibcon#ireg 7 cls_cnt 0 2006.145.19:54:03.50#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:54:03.62#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:54:03.62#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:54:03.64#ibcon#[25=USB\r\n] 2006.145.19:54:03.67#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:54:03.67#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:54:03.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.19:54:03.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.19:54:03.67$vck44/valo=4,624.99 2006.145.19:54:03.67#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.19:54:03.67#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.19:54:03.67#ibcon#ireg 17 cls_cnt 0 2006.145.19:54:03.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:54:03.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:54:03.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:54:03.69#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.19:54:03.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:54:03.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:54:03.73#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.19:54:03.73#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.19:54:03.73$vck44/va=4,7 2006.145.19:54:03.73#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.19:54:03.73#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.19:54:03.73#ibcon#ireg 11 cls_cnt 2 2006.145.19:54:03.73#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.19:54:03.79#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.19:54:03.79#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.19:54:03.81#ibcon#[25=AT04-07\r\n] 2006.145.19:54:03.84#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.19:54:03.84#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.19:54:03.84#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.19:54:03.84#ibcon#ireg 7 cls_cnt 0 2006.145.19:54:03.84#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.19:54:03.96#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.19:54:03.96#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.19:54:03.98#ibcon#[25=USB\r\n] 2006.145.19:54:04.01#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.19:54:04.01#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.19:54:04.01#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.19:54:04.01#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.19:54:04.01$vck44/valo=5,734.99 2006.145.19:54:04.01#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.19:54:04.01#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.19:54:04.01#ibcon#ireg 17 cls_cnt 0 2006.145.19:54:04.01#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.19:54:04.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.19:54:04.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.19:54:04.03#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.19:54:04.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.19:54:04.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.19:54:04.07#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.19:54:04.07#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.19:54:04.07$vck44/va=5,4 2006.145.19:54:04.07#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.19:54:04.07#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.19:54:04.07#ibcon#ireg 11 cls_cnt 2 2006.145.19:54:04.07#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.19:54:04.13#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.19:54:04.13#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.19:54:04.15#ibcon#[25=AT05-04\r\n] 2006.145.19:54:04.18#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.19:54:04.18#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.19:54:04.18#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.19:54:04.18#ibcon#ireg 7 cls_cnt 0 2006.145.19:54:04.18#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.19:54:04.30#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.19:54:04.30#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.19:54:04.32#ibcon#[25=USB\r\n] 2006.145.19:54:04.35#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.19:54:04.35#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.19:54:04.35#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.19:54:04.35#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.19:54:04.35$vck44/valo=6,814.99 2006.145.19:54:04.35#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.19:54:04.35#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.19:54:04.35#ibcon#ireg 17 cls_cnt 0 2006.145.19:54:04.35#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.19:54:04.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.19:54:04.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.19:54:04.38#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.19:54:04.38#abcon#<5=/07 1.0 2.3 15.92 881020.0\r\n> 2006.145.19:54:04.40#abcon#{5=INTERFACE CLEAR} 2006.145.19:54:04.42#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.19:54:04.42#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.19:54:04.42#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.19:54:04.42#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.19:54:04.42$vck44/va=6,4 2006.145.19:54:04.42#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.19:54:04.42#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.19:54:04.42#ibcon#ireg 11 cls_cnt 2 2006.145.19:54:04.42#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:54:04.46#abcon#[5=S1D000X0/0*\r\n] 2006.145.19:54:04.47#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:54:04.47#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:54:04.49#ibcon#[25=AT06-04\r\n] 2006.145.19:54:04.52#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:54:04.52#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:54:04.52#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.19:54:04.52#ibcon#ireg 7 cls_cnt 0 2006.145.19:54:04.52#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:54:04.64#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:54:04.64#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:54:04.66#ibcon#[25=USB\r\n] 2006.145.19:54:04.69#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:54:04.69#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:54:04.69#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.19:54:04.69#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.19:54:04.69$vck44/valo=7,864.99 2006.145.19:54:04.69#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.19:54:04.69#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.19:54:04.69#ibcon#ireg 17 cls_cnt 0 2006.145.19:54:04.69#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:54:04.69#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:54:04.69#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:54:04.71#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.19:54:04.75#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:54:04.75#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:54:04.75#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.19:54:04.75#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.19:54:04.75$vck44/va=7,4 2006.145.19:54:04.75#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.19:54:04.75#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.19:54:04.75#ibcon#ireg 11 cls_cnt 2 2006.145.19:54:04.75#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:54:04.81#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:54:04.81#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:54:04.83#ibcon#[25=AT07-04\r\n] 2006.145.19:54:04.86#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:54:04.86#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:54:04.86#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.19:54:04.86#ibcon#ireg 7 cls_cnt 0 2006.145.19:54:04.86#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:54:04.98#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:54:04.98#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:54:05.00#ibcon#[25=USB\r\n] 2006.145.19:54:05.03#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:54:05.03#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:54:05.03#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.19:54:05.03#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.19:54:05.03$vck44/valo=8,884.99 2006.145.19:54:05.03#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.19:54:05.03#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.19:54:05.03#ibcon#ireg 17 cls_cnt 0 2006.145.19:54:05.03#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:54:05.03#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:54:05.03#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:54:05.05#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.19:54:05.09#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:54:05.09#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:54:05.09#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.19:54:05.09#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.19:54:05.09$vck44/va=8,4 2006.145.19:54:05.09#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.19:54:05.09#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.19:54:05.09#ibcon#ireg 11 cls_cnt 2 2006.145.19:54:05.09#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.19:54:05.15#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.19:54:05.15#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.19:54:05.17#ibcon#[25=AT08-04\r\n] 2006.145.19:54:05.20#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.19:54:05.20#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.19:54:05.20#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.19:54:05.20#ibcon#ireg 7 cls_cnt 0 2006.145.19:54:05.20#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.19:54:05.32#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.19:54:05.32#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.19:54:05.34#ibcon#[25=USB\r\n] 2006.145.19:54:05.37#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.19:54:05.37#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.19:54:05.37#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.19:54:05.37#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.19:54:05.37$vck44/vblo=1,629.99 2006.145.19:54:05.37#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.19:54:05.37#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.19:54:05.37#ibcon#ireg 17 cls_cnt 0 2006.145.19:54:05.37#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.19:54:05.37#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.19:54:05.37#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.19:54:05.39#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.19:54:05.43#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.19:54:05.43#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.19:54:05.43#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.19:54:05.43#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.19:54:05.43$vck44/vb=1,3 2006.145.19:54:05.43#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.19:54:05.43#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.19:54:05.43#ibcon#ireg 11 cls_cnt 2 2006.145.19:54:05.43#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.19:54:05.43#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.19:54:05.43#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.19:54:05.45#ibcon#[27=AT01-03\r\n] 2006.145.19:54:05.48#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.19:54:05.48#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.19:54:05.48#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.19:54:05.48#ibcon#ireg 7 cls_cnt 0 2006.145.19:54:05.48#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.19:54:05.60#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.19:54:05.60#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.19:54:05.62#ibcon#[27=USB\r\n] 2006.145.19:54:05.65#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.19:54:05.65#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.19:54:05.65#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.19:54:05.65#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.19:54:05.65$vck44/vblo=2,634.99 2006.145.19:54:05.65#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.19:54:05.65#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.19:54:05.65#ibcon#ireg 17 cls_cnt 0 2006.145.19:54:05.65#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:54:05.65#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:54:05.65#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:54:05.67#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.19:54:05.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:54:05.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.19:54:05.71#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.19:54:05.71#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.19:54:05.71$vck44/vb=2,4 2006.145.19:54:05.71#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.19:54:05.71#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.19:54:05.71#ibcon#ireg 11 cls_cnt 2 2006.145.19:54:05.71#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:54:05.77#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:54:05.77#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:54:05.79#ibcon#[27=AT02-04\r\n] 2006.145.19:54:05.82#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:54:05.82#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.19:54:05.82#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.19:54:05.82#ibcon#ireg 7 cls_cnt 0 2006.145.19:54:05.82#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:54:05.94#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:54:05.94#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:54:05.96#ibcon#[27=USB\r\n] 2006.145.19:54:05.99#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:54:05.99#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.19:54:05.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.19:54:05.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.19:54:05.99$vck44/vblo=3,649.99 2006.145.19:54:05.99#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.19:54:05.99#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.19:54:05.99#ibcon#ireg 17 cls_cnt 0 2006.145.19:54:05.99#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:54:05.99#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:54:05.99#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:54:06.01#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.19:54:06.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:54:06.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.19:54:06.05#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.19:54:06.05#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.19:54:06.05$vck44/vb=3,4 2006.145.19:54:06.05#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.19:54:06.05#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.19:54:06.05#ibcon#ireg 11 cls_cnt 2 2006.145.19:54:06.05#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:54:06.11#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:54:06.11#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:54:06.13#ibcon#[27=AT03-04\r\n] 2006.145.19:54:06.16#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:54:06.16#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.19:54:06.16#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.19:54:06.16#ibcon#ireg 7 cls_cnt 0 2006.145.19:54:06.16#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:54:06.28#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:54:06.28#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:54:06.30#ibcon#[27=USB\r\n] 2006.145.19:54:06.33#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:54:06.33#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.19:54:06.33#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.19:54:06.33#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.19:54:06.33$vck44/vblo=4,679.99 2006.145.19:54:06.33#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.19:54:06.33#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.19:54:06.33#ibcon#ireg 17 cls_cnt 0 2006.145.19:54:06.33#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:54:06.33#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:54:06.33#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:54:06.35#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.19:54:06.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:54:06.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.19:54:06.39#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.19:54:06.39#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.19:54:06.39$vck44/vb=4,4 2006.145.19:54:06.39#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.19:54:06.39#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.19:54:06.39#ibcon#ireg 11 cls_cnt 2 2006.145.19:54:06.39#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.19:54:06.45#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.19:54:06.45#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.19:54:06.47#ibcon#[27=AT04-04\r\n] 2006.145.19:54:06.50#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.19:54:06.50#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.19:54:06.50#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.19:54:06.50#ibcon#ireg 7 cls_cnt 0 2006.145.19:54:06.50#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.19:54:06.62#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.19:54:06.62#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.19:54:06.64#ibcon#[27=USB\r\n] 2006.145.19:54:06.67#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.19:54:06.67#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.19:54:06.67#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.19:54:06.67#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.19:54:06.67$vck44/vblo=5,709.99 2006.145.19:54:06.67#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.19:54:06.67#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.19:54:06.67#ibcon#ireg 17 cls_cnt 0 2006.145.19:54:06.67#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.19:54:06.67#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.19:54:06.67#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.19:54:06.69#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.19:54:06.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.19:54:06.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.19:54:06.73#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.19:54:06.73#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.19:54:06.73$vck44/vb=5,4 2006.145.19:54:06.73#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.19:54:06.73#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.19:54:06.73#ibcon#ireg 11 cls_cnt 2 2006.145.19:54:06.73#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.19:54:06.79#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.19:54:06.79#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.19:54:06.81#ibcon#[27=AT05-04\r\n] 2006.145.19:54:06.84#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.19:54:06.84#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.19:54:06.84#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.19:54:06.84#ibcon#ireg 7 cls_cnt 0 2006.145.19:54:06.84#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.19:54:06.96#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.19:54:06.96#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.19:54:06.98#ibcon#[27=USB\r\n] 2006.145.19:54:07.01#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.19:54:07.01#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.19:54:07.01#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.19:54:07.01#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.19:54:07.01$vck44/vblo=6,719.99 2006.145.19:54:07.01#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.19:54:07.01#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.19:54:07.01#ibcon#ireg 17 cls_cnt 0 2006.145.19:54:07.01#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.19:54:07.01#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.19:54:07.01#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.19:54:07.03#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.19:54:07.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.19:54:07.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.19:54:07.07#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.19:54:07.07#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.19:54:07.07$vck44/vb=6,4 2006.145.19:54:07.07#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.19:54:07.07#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.19:54:07.07#ibcon#ireg 11 cls_cnt 2 2006.145.19:54:07.07#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.19:54:07.13#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.19:54:07.13#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.19:54:07.15#ibcon#[27=AT06-04\r\n] 2006.145.19:54:07.18#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.19:54:07.18#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.19:54:07.18#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.19:54:07.18#ibcon#ireg 7 cls_cnt 0 2006.145.19:54:07.18#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.19:54:07.30#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.19:54:07.30#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.19:54:07.32#ibcon#[27=USB\r\n] 2006.145.19:54:07.35#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.19:54:07.35#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.19:54:07.35#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.19:54:07.35#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.19:54:07.35$vck44/vblo=7,734.99 2006.145.19:54:07.35#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.19:54:07.35#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.19:54:07.35#ibcon#ireg 17 cls_cnt 0 2006.145.19:54:07.35#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:54:07.35#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:54:07.35#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:54:07.37#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.19:54:07.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:54:07.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.19:54:07.41#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.19:54:07.41#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.19:54:07.41$vck44/vb=7,4 2006.145.19:54:07.41#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.19:54:07.41#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.19:54:07.41#ibcon#ireg 11 cls_cnt 2 2006.145.19:54:07.41#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.19:54:07.47#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.19:54:07.47#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.19:54:07.49#ibcon#[27=AT07-04\r\n] 2006.145.19:54:07.52#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.19:54:07.52#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.19:54:07.52#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.19:54:07.52#ibcon#ireg 7 cls_cnt 0 2006.145.19:54:07.52#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.19:54:07.64#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.19:54:07.64#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.19:54:07.66#ibcon#[27=USB\r\n] 2006.145.19:54:07.69#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.19:54:07.69#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.19:54:07.69#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.19:54:07.69#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.19:54:07.69$vck44/vblo=8,744.99 2006.145.19:54:07.69#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.19:54:07.69#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.19:54:07.69#ibcon#ireg 17 cls_cnt 0 2006.145.19:54:07.69#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:54:07.69#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:54:07.69#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:54:07.71#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.19:54:07.75#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:54:07.75#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.19:54:07.75#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.19:54:07.75#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.19:54:07.75$vck44/vb=8,4 2006.145.19:54:07.75#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.19:54:07.75#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.19:54:07.75#ibcon#ireg 11 cls_cnt 2 2006.145.19:54:07.75#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:54:07.81#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:54:07.81#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:54:07.83#ibcon#[27=AT08-04\r\n] 2006.145.19:54:07.86#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:54:07.86#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.19:54:07.86#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.19:54:07.86#ibcon#ireg 7 cls_cnt 0 2006.145.19:54:07.86#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:54:07.98#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:54:07.98#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:54:08.00#ibcon#[27=USB\r\n] 2006.145.19:54:08.03#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:54:08.03#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.19:54:08.03#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.19:54:08.03#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.19:54:08.03$vck44/vabw=wide 2006.145.19:54:08.03#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.19:54:08.03#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.19:54:08.03#ibcon#ireg 8 cls_cnt 0 2006.145.19:54:08.03#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:54:08.03#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:54:08.03#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:54:08.05#ibcon#[25=BW32\r\n] 2006.145.19:54:08.08#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:54:08.08#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.19:54:08.08#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.19:54:08.08#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.19:54:08.08$vck44/vbbw=wide 2006.145.19:54:08.08#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.19:54:08.08#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.19:54:08.08#ibcon#ireg 8 cls_cnt 0 2006.145.19:54:08.08#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.19:54:08.15#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.19:54:08.15#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.19:54:08.17#ibcon#[27=BW32\r\n] 2006.145.19:54:08.20#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.19:54:08.20#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.19:54:08.20#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.19:54:08.20#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.19:54:08.20$setupk4/ifdk4 2006.145.19:54:08.20$ifdk4/lo= 2006.145.19:54:08.20$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.19:54:08.20$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.19:54:08.20$ifdk4/patch= 2006.145.19:54:08.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.19:54:08.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.19:54:08.20$setupk4/!*+20s 2006.145.19:54:14.55#abcon#<5=/07 1.0 2.3 15.92 881020.0\r\n> 2006.145.19:54:14.57#abcon#{5=INTERFACE CLEAR} 2006.145.19:54:14.63#abcon#[5=S1D000X0/0*\r\n] 2006.145.19:54:22.69$setupk4/"tpicd 2006.145.19:54:22.69$setupk4/echo=off 2006.145.19:54:22.69$setupk4/xlog=off 2006.145.19:54:22.69:!2006.145.19:55:08 2006.145.19:54:24.14#trakl#Source acquired 2006.145.19:54:24.14#flagr#flagr/antenna,acquired 2006.145.19:55:08.00:preob 2006.145.19:55:08.14/onsource/TRACKING 2006.145.19:55:08.14:!2006.145.19:55:18 2006.145.19:55:18.00:"tape 2006.145.19:55:18.00:"st=record 2006.145.19:55:18.00:data_valid=on 2006.145.19:55:18.00:midob 2006.145.19:55:18.14/onsource/TRACKING 2006.145.19:55:18.14/wx/15.91,1020.1,88 2006.145.19:55:18.20/cable/+6.5511E-03 2006.145.19:55:19.29/va/01,08,usb,yes,33,35 2006.145.19:55:19.29/va/02,07,usb,yes,35,36 2006.145.19:55:19.29/va/03,08,usb,yes,32,33 2006.145.19:55:19.29/va/04,07,usb,yes,36,38 2006.145.19:55:19.29/va/05,04,usb,yes,32,32 2006.145.19:55:19.29/va/06,04,usb,yes,35,35 2006.145.19:55:19.29/va/07,04,usb,yes,36,37 2006.145.19:55:19.29/va/08,04,usb,yes,31,36 2006.145.19:55:19.52/valo/01,524.99,yes,locked 2006.145.19:55:19.52/valo/02,534.99,yes,locked 2006.145.19:55:19.52/valo/03,564.99,yes,locked 2006.145.19:55:19.52/valo/04,624.99,yes,locked 2006.145.19:55:19.52/valo/05,734.99,yes,locked 2006.145.19:55:19.52/valo/06,814.99,yes,locked 2006.145.19:55:19.52/valo/07,864.99,yes,locked 2006.145.19:55:19.52/valo/08,884.99,yes,locked 2006.145.19:55:20.61/vb/01,03,usb,yes,39,36 2006.145.19:55:20.61/vb/02,04,usb,yes,34,34 2006.145.19:55:20.61/vb/03,04,usb,yes,31,34 2006.145.19:55:20.61/vb/04,04,usb,yes,35,34 2006.145.19:55:20.61/vb/05,04,usb,yes,28,30 2006.145.19:55:20.61/vb/06,04,usb,yes,32,29 2006.145.19:55:20.61/vb/07,04,usb,yes,32,32 2006.145.19:55:20.61/vb/08,04,usb,yes,30,33 2006.145.19:55:20.85/vblo/01,629.99,yes,locked 2006.145.19:55:20.85/vblo/02,634.99,yes,locked 2006.145.19:55:20.85/vblo/03,649.99,yes,locked 2006.145.19:55:20.85/vblo/04,679.99,yes,locked 2006.145.19:55:20.85/vblo/05,709.99,yes,locked 2006.145.19:55:20.85/vblo/06,719.99,yes,locked 2006.145.19:55:20.85/vblo/07,734.99,yes,locked 2006.145.19:55:20.85/vblo/08,744.99,yes,locked 2006.145.19:55:21.00/vabw/8 2006.145.19:55:21.15/vbbw/8 2006.145.19:55:21.24/xfe/off,on,15.0 2006.145.19:55:21.61/ifatt/23,28,28,28 2006.145.19:55:22.07/fmout-gps/S +5.2E-08 2006.145.19:55:22.11:!2006.145.19:55:58 2006.145.19:55:58.00:data_valid=off 2006.145.19:55:58.00:"et 2006.145.19:55:58.01:!+3s 2006.145.19:56:01.02:"tape 2006.145.19:56:01.02:postob 2006.145.19:56:01.13/cable/+6.5517E-03 2006.145.19:56:01.13/wx/15.91,1020.1,88 2006.145.19:56:01.22/fmout-gps/S +5.1E-08 2006.145.19:56:01.23:scan_name=145-2000,jd0605,40 2006.145.19:56:01.23:source=3c345,164258.81,394837.0,2000.0,cw 2006.145.19:56:03.14#flagr#flagr/antenna,new-source 2006.145.19:56:03.14:checkk5 2006.145.19:56:03.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.19:56:04.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.19:56:04.45/chk_autoobs//k5ts3/ autoobs is running! 2006.145.19:56:04.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.19:56:05.32/chk_obsdata//k5ts1/T1451955??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.19:56:05.76/chk_obsdata//k5ts2/T1451955??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.19:56:06.17/chk_obsdata//k5ts3/T1451955??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.19:56:06.61/chk_obsdata//k5ts4/T1451955??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.19:56:07.39/k5log//k5ts1_log_newline 2006.145.19:56:08.14/k5log//k5ts2_log_newline 2006.145.19:56:08.90/k5log//k5ts3_log_newline 2006.145.19:56:09.64/k5log//k5ts4_log_newline 2006.145.19:56:09.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.19:56:09.67:setupk4=1 2006.145.19:56:09.67$setupk4/echo=on 2006.145.19:56:09.67$setupk4/pcalon 2006.145.19:56:09.67$pcalon/"no phase cal control is implemented here 2006.145.19:56:09.67$setupk4/"tpicd=stop 2006.145.19:56:09.67$setupk4/"rec=synch_on 2006.145.19:56:09.67$setupk4/"rec_mode=128 2006.145.19:56:09.67$setupk4/!* 2006.145.19:56:09.67$setupk4/recpk4 2006.145.19:56:09.67$recpk4/recpatch= 2006.145.19:56:09.68$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.19:56:09.68$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.19:56:09.68$setupk4/vck44 2006.145.19:56:09.68$vck44/valo=1,524.99 2006.145.19:56:09.68#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.19:56:09.68#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.19:56:09.68#ibcon#ireg 17 cls_cnt 0 2006.145.19:56:09.68#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.19:56:09.68#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.19:56:09.68#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.19:56:09.71#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.19:56:09.76#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.19:56:09.76#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.19:56:09.76#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.19:56:09.76#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.19:56:09.76$vck44/va=1,8 2006.145.19:56:09.76#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.19:56:09.76#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.19:56:09.76#ibcon#ireg 11 cls_cnt 2 2006.145.19:56:09.76#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.19:56:09.76#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.19:56:09.76#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.19:56:09.78#ibcon#[25=AT01-08\r\n] 2006.145.19:56:09.81#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.19:56:09.81#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.19:56:09.81#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.19:56:09.81#ibcon#ireg 7 cls_cnt 0 2006.145.19:56:09.81#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.19:56:09.94#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.19:56:09.94#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.19:56:09.95#ibcon#[25=USB\r\n] 2006.145.19:56:09.98#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.19:56:09.98#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.19:56:09.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.19:56:09.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.19:56:09.98$vck44/valo=2,534.99 2006.145.19:56:09.98#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.19:56:09.98#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.19:56:09.98#ibcon#ireg 17 cls_cnt 0 2006.145.19:56:09.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.19:56:09.98#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.19:56:09.98#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.19:56:10.02#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.19:56:10.06#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.19:56:10.06#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.19:56:10.06#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.19:56:10.06#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.19:56:10.06$vck44/va=2,7 2006.145.19:56:10.06#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.19:56:10.06#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.19:56:10.06#ibcon#ireg 11 cls_cnt 2 2006.145.19:56:10.06#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:56:10.11#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:56:10.11#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:56:10.12#ibcon#[25=AT02-07\r\n] 2006.145.19:56:10.15#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:56:10.15#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:56:10.15#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.19:56:10.15#ibcon#ireg 7 cls_cnt 0 2006.145.19:56:10.15#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:56:10.27#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:56:10.27#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:56:10.29#ibcon#[25=USB\r\n] 2006.145.19:56:10.32#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:56:10.32#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:56:10.32#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.19:56:10.32#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.19:56:10.32$vck44/valo=3,564.99 2006.145.19:56:10.32#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.19:56:10.32#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.19:56:10.32#ibcon#ireg 17 cls_cnt 0 2006.145.19:56:10.32#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:56:10.32#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:56:10.32#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:56:10.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.19:56:10.38#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:56:10.38#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:56:10.38#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.19:56:10.38#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.19:56:10.38$vck44/va=3,8 2006.145.19:56:10.38#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.19:56:10.38#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.19:56:10.38#ibcon#ireg 11 cls_cnt 2 2006.145.19:56:10.38#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:56:10.44#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:56:10.44#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:56:10.46#ibcon#[25=AT03-08\r\n] 2006.145.19:56:10.49#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:56:10.49#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:56:10.49#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.19:56:10.49#ibcon#ireg 7 cls_cnt 0 2006.145.19:56:10.49#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:56:10.61#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:56:10.61#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:56:10.63#ibcon#[25=USB\r\n] 2006.145.19:56:10.66#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:56:10.66#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:56:10.66#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.19:56:10.66#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.19:56:10.66$vck44/valo=4,624.99 2006.145.19:56:10.66#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.19:56:10.66#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.19:56:10.66#ibcon#ireg 17 cls_cnt 0 2006.145.19:56:10.66#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:56:10.66#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:56:10.66#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:56:10.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.19:56:10.72#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:56:10.72#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:56:10.72#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.19:56:10.72#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.19:56:10.72$vck44/va=4,7 2006.145.19:56:10.72#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.19:56:10.72#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.19:56:10.72#ibcon#ireg 11 cls_cnt 2 2006.145.19:56:10.72#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:56:10.78#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:56:10.78#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:56:10.80#ibcon#[25=AT04-07\r\n] 2006.145.19:56:10.83#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:56:10.83#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:56:10.83#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.19:56:10.83#ibcon#ireg 7 cls_cnt 0 2006.145.19:56:10.83#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:56:10.95#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:56:10.95#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:56:10.97#ibcon#[25=USB\r\n] 2006.145.19:56:11.00#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:56:11.00#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:56:11.00#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.19:56:11.00#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.19:56:11.00$vck44/valo=5,734.99 2006.145.19:56:11.00#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.19:56:11.00#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.19:56:11.00#ibcon#ireg 17 cls_cnt 0 2006.145.19:56:11.00#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:56:11.00#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:56:11.00#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:56:11.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.19:56:11.06#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:56:11.06#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:56:11.06#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.19:56:11.06#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.19:56:11.06$vck44/va=5,4 2006.145.19:56:11.06#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.19:56:11.06#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.19:56:11.06#ibcon#ireg 11 cls_cnt 2 2006.145.19:56:11.06#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:56:11.15#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:56:11.15#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:56:11.16#ibcon#[25=AT05-04\r\n] 2006.145.19:56:11.19#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:56:11.19#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:56:11.19#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.19:56:11.19#ibcon#ireg 7 cls_cnt 0 2006.145.19:56:11.19#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:56:11.31#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:56:11.31#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:56:11.33#ibcon#[25=USB\r\n] 2006.145.19:56:11.36#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:56:11.36#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:56:11.36#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.19:56:11.36#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.19:56:11.36$vck44/valo=6,814.99 2006.145.19:56:11.36#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.19:56:11.36#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.19:56:11.36#ibcon#ireg 17 cls_cnt 0 2006.145.19:56:11.36#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:56:11.36#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:56:11.36#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:56:11.39#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.19:56:11.43#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:56:11.43#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:56:11.43#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.19:56:11.43#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.19:56:11.43$vck44/va=6,4 2006.145.19:56:11.43#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.19:56:11.43#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.19:56:11.43#ibcon#ireg 11 cls_cnt 2 2006.145.19:56:11.43#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:56:11.48#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:56:11.48#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:56:11.50#ibcon#[25=AT06-04\r\n] 2006.145.19:56:11.53#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:56:11.53#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:56:11.53#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.19:56:11.53#ibcon#ireg 7 cls_cnt 0 2006.145.19:56:11.53#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:56:11.65#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:56:11.65#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:56:11.67#ibcon#[25=USB\r\n] 2006.145.19:56:11.70#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:56:11.70#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:56:11.70#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.19:56:11.70#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.19:56:11.70$vck44/valo=7,864.99 2006.145.19:56:11.70#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.19:56:11.70#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.19:56:11.70#ibcon#ireg 17 cls_cnt 0 2006.145.19:56:11.70#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:56:11.70#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:56:11.70#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:56:11.72#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.19:56:11.76#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:56:11.76#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:56:11.76#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.19:56:11.76#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.19:56:11.76$vck44/va=7,4 2006.145.19:56:11.76#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.19:56:11.76#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.19:56:11.76#ibcon#ireg 11 cls_cnt 2 2006.145.19:56:11.76#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:56:11.82#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:56:11.82#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:56:11.84#ibcon#[25=AT07-04\r\n] 2006.145.19:56:11.87#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:56:11.87#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:56:11.87#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.19:56:11.87#ibcon#ireg 7 cls_cnt 0 2006.145.19:56:11.87#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:56:11.99#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:56:11.99#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:56:12.01#ibcon#[25=USB\r\n] 2006.145.19:56:12.04#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:56:12.04#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:56:12.04#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.19:56:12.04#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.19:56:12.04$vck44/valo=8,884.99 2006.145.19:56:12.04#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.19:56:12.04#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.19:56:12.04#ibcon#ireg 17 cls_cnt 0 2006.145.19:56:12.04#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:56:12.04#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:56:12.04#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:56:12.06#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.19:56:12.10#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:56:12.10#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:56:12.10#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.19:56:12.10#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.19:56:12.10$vck44/va=8,4 2006.145.19:56:12.10#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.19:56:12.10#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.19:56:12.10#ibcon#ireg 11 cls_cnt 2 2006.145.19:56:12.10#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.19:56:12.16#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.19:56:12.16#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.19:56:12.18#ibcon#[25=AT08-04\r\n] 2006.145.19:56:12.21#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.19:56:12.21#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.19:56:12.21#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.19:56:12.21#ibcon#ireg 7 cls_cnt 0 2006.145.19:56:12.21#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.19:56:12.33#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.19:56:12.33#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.19:56:12.35#ibcon#[25=USB\r\n] 2006.145.19:56:12.38#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.19:56:12.38#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.19:56:12.38#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.19:56:12.38#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.19:56:12.38$vck44/vblo=1,629.99 2006.145.19:56:12.38#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.19:56:12.38#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.19:56:12.38#ibcon#ireg 17 cls_cnt 0 2006.145.19:56:12.38#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.19:56:12.38#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.19:56:12.38#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.19:56:12.40#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.19:56:12.44#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.19:56:12.44#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.19:56:12.44#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.19:56:12.44#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.19:56:12.44$vck44/vb=1,3 2006.145.19:56:12.44#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.19:56:12.44#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.19:56:12.44#ibcon#ireg 11 cls_cnt 2 2006.145.19:56:12.44#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.19:56:12.44#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.19:56:12.44#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.19:56:12.46#ibcon#[27=AT01-03\r\n] 2006.145.19:56:12.49#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.19:56:12.49#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.19:56:12.49#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.19:56:12.49#ibcon#ireg 7 cls_cnt 0 2006.145.19:56:12.49#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.19:56:12.61#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.19:56:12.61#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.19:56:12.63#ibcon#[27=USB\r\n] 2006.145.19:56:12.66#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.19:56:12.66#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.19:56:12.66#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.19:56:12.66#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.19:56:12.66$vck44/vblo=2,634.99 2006.145.19:56:12.66#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.19:56:12.66#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.19:56:12.66#ibcon#ireg 17 cls_cnt 0 2006.145.19:56:12.66#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.19:56:12.66#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.19:56:12.66#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.19:56:12.68#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.19:56:12.72#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.19:56:12.72#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.19:56:12.72#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.19:56:12.72#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.19:56:12.72$vck44/vb=2,4 2006.145.19:56:12.72#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.19:56:12.72#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.19:56:12.72#ibcon#ireg 11 cls_cnt 2 2006.145.19:56:12.72#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.19:56:12.78#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.19:56:12.78#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.19:56:12.80#ibcon#[27=AT02-04\r\n] 2006.145.19:56:12.83#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.19:56:12.83#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.19:56:12.83#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.19:56:12.83#ibcon#ireg 7 cls_cnt 0 2006.145.19:56:12.83#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.19:56:12.95#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.19:56:12.95#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.19:56:12.97#ibcon#[27=USB\r\n] 2006.145.19:56:13.00#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.19:56:13.00#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.19:56:13.00#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.19:56:13.00#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.19:56:13.00$vck44/vblo=3,649.99 2006.145.19:56:13.00#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.19:56:13.00#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.19:56:13.00#ibcon#ireg 17 cls_cnt 0 2006.145.19:56:13.00#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.19:56:13.00#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.19:56:13.00#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.19:56:13.02#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.19:56:13.06#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.19:56:13.06#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.19:56:13.06#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.19:56:13.06#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.19:56:13.06$vck44/vb=3,4 2006.145.19:56:13.06#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.19:56:13.06#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.19:56:13.06#ibcon#ireg 11 cls_cnt 2 2006.145.19:56:13.06#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:56:13.12#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:56:13.12#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:56:13.14#ibcon#[27=AT03-04\r\n] 2006.145.19:56:13.17#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:56:13.17#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.19:56:13.17#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.19:56:13.17#ibcon#ireg 7 cls_cnt 0 2006.145.19:56:13.17#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:56:13.29#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:56:13.29#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:56:13.31#ibcon#[27=USB\r\n] 2006.145.19:56:13.34#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:56:13.34#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.19:56:13.34#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.19:56:13.34#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.19:56:13.34$vck44/vblo=4,679.99 2006.145.19:56:13.34#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.19:56:13.34#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.19:56:13.34#ibcon#ireg 17 cls_cnt 0 2006.145.19:56:13.34#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:56:13.34#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:56:13.34#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:56:13.36#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.19:56:13.40#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:56:13.40#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.19:56:13.40#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.19:56:13.40#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.19:56:13.40$vck44/vb=4,4 2006.145.19:56:13.40#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.19:56:13.40#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.19:56:13.40#ibcon#ireg 11 cls_cnt 2 2006.145.19:56:13.40#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:56:13.46#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:56:13.46#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:56:13.48#ibcon#[27=AT04-04\r\n] 2006.145.19:56:13.51#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:56:13.51#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.19:56:13.51#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.19:56:13.51#ibcon#ireg 7 cls_cnt 0 2006.145.19:56:13.51#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:56:13.63#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:56:13.63#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:56:13.65#ibcon#[27=USB\r\n] 2006.145.19:56:13.68#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:56:13.68#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.19:56:13.68#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.19:56:13.68#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.19:56:13.68$vck44/vblo=5,709.99 2006.145.19:56:13.68#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.19:56:13.68#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.19:56:13.68#ibcon#ireg 17 cls_cnt 0 2006.145.19:56:13.68#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:56:13.68#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:56:13.68#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:56:13.70#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.19:56:13.74#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:56:13.74#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.19:56:13.74#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.19:56:13.74#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.19:56:13.74$vck44/vb=5,4 2006.145.19:56:13.74#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.19:56:13.74#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.19:56:13.74#ibcon#ireg 11 cls_cnt 2 2006.145.19:56:13.74#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:56:13.80#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:56:13.80#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:56:13.82#ibcon#[27=AT05-04\r\n] 2006.145.19:56:13.85#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:56:13.85#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.19:56:13.85#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.19:56:13.85#ibcon#ireg 7 cls_cnt 0 2006.145.19:56:13.85#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:56:13.97#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:56:13.97#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:56:13.99#ibcon#[27=USB\r\n] 2006.145.19:56:14.02#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:56:14.02#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.19:56:14.02#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.19:56:14.02#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.19:56:14.02$vck44/vblo=6,719.99 2006.145.19:56:14.02#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.19:56:14.02#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.19:56:14.02#ibcon#ireg 17 cls_cnt 0 2006.145.19:56:14.02#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:56:14.02#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:56:14.02#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:56:14.04#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.19:56:14.08#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:56:14.08#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.19:56:14.08#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.19:56:14.08#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.19:56:14.08$vck44/vb=6,4 2006.145.19:56:14.08#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.19:56:14.08#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.19:56:14.08#ibcon#ireg 11 cls_cnt 2 2006.145.19:56:14.08#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:56:14.14#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:56:14.14#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:56:14.16#ibcon#[27=AT06-04\r\n] 2006.145.19:56:14.19#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:56:14.19#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.19:56:14.19#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.19:56:14.19#ibcon#ireg 7 cls_cnt 0 2006.145.19:56:14.19#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:56:14.31#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:56:14.31#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:56:14.33#ibcon#[27=USB\r\n] 2006.145.19:56:14.36#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:56:14.36#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.19:56:14.36#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.19:56:14.36#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.19:56:14.36$vck44/vblo=7,734.99 2006.145.19:56:14.36#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.19:56:14.36#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.19:56:14.36#ibcon#ireg 17 cls_cnt 0 2006.145.19:56:14.36#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:56:14.36#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:56:14.36#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:56:14.38#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.19:56:14.42#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:56:14.42#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.19:56:14.42#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.19:56:14.42#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.19:56:14.42$vck44/vb=7,4 2006.145.19:56:14.42#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.19:56:14.42#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.19:56:14.42#ibcon#ireg 11 cls_cnt 2 2006.145.19:56:14.42#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:56:14.48#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:56:14.48#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:56:14.50#ibcon#[27=AT07-04\r\n] 2006.145.19:56:14.53#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:56:14.53#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.19:56:14.53#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.19:56:14.53#ibcon#ireg 7 cls_cnt 0 2006.145.19:56:14.53#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:56:14.65#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:56:14.65#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:56:14.67#ibcon#[27=USB\r\n] 2006.145.19:56:14.70#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:56:14.70#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.19:56:14.70#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.19:56:14.70#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.19:56:14.70$vck44/vblo=8,744.99 2006.145.19:56:14.70#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.19:56:14.70#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.19:56:14.70#ibcon#ireg 17 cls_cnt 0 2006.145.19:56:14.70#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:56:14.70#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:56:14.70#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:56:14.72#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.19:56:14.76#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:56:14.76#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.19:56:14.76#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.19:56:14.76#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.19:56:14.76$vck44/vb=8,4 2006.145.19:56:14.76#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.19:56:14.76#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.19:56:14.76#ibcon#ireg 11 cls_cnt 2 2006.145.19:56:14.76#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:56:14.82#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:56:14.82#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:56:14.84#ibcon#[27=AT08-04\r\n] 2006.145.19:56:14.87#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:56:14.87#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.19:56:14.87#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.19:56:14.87#ibcon#ireg 7 cls_cnt 0 2006.145.19:56:14.87#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:56:14.99#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:56:14.99#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:56:15.01#ibcon#[27=USB\r\n] 2006.145.19:56:15.04#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:56:15.04#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.19:56:15.04#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.19:56:15.04#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.19:56:15.04$vck44/vabw=wide 2006.145.19:56:15.04#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.19:56:15.04#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.19:56:15.04#ibcon#ireg 8 cls_cnt 0 2006.145.19:56:15.04#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:56:15.04#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:56:15.04#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:56:15.06#ibcon#[25=BW32\r\n] 2006.145.19:56:15.09#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:56:15.09#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.19:56:15.09#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.19:56:15.09#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.19:56:15.09$vck44/vbbw=wide 2006.145.19:56:15.09#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.19:56:15.09#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.19:56:15.09#ibcon#ireg 8 cls_cnt 0 2006.145.19:56:15.09#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.19:56:15.16#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.19:56:15.16#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.19:56:15.18#ibcon#[27=BW32\r\n] 2006.145.19:56:15.22#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.19:56:15.22#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.19:56:15.22#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.19:56:15.22#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.19:56:15.22$setupk4/ifdk4 2006.145.19:56:15.22$ifdk4/lo= 2006.145.19:56:15.22$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.19:56:15.22$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.19:56:15.22$ifdk4/patch= 2006.145.19:56:15.22$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.19:56:15.22$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.19:56:15.22$setupk4/!*+20s 2006.145.19:56:16.59#abcon#<5=/07 1.1 2.3 15.90 881020.1\r\n> 2006.145.19:56:16.61#abcon#{5=INTERFACE CLEAR} 2006.145.19:56:16.67#abcon#[5=S1D000X0/0*\r\n] 2006.145.19:56:26.76#abcon#<5=/07 1.2 2.3 15.90 881020.1\r\n> 2006.145.19:56:26.78#abcon#{5=INTERFACE CLEAR} 2006.145.19:56:26.84#abcon#[5=S1D000X0/0*\r\n] 2006.145.19:56:29.69$setupk4/"tpicd 2006.145.19:56:29.69$setupk4/echo=off 2006.145.19:56:29.69$setupk4/xlog=off 2006.145.19:56:29.69:!2006.145.20:00:14 2006.145.19:56:43.14#trakl#Source acquired 2006.145.19:56:43.14#flagr#flagr/antenna,acquired 2006.145.20:00:14.00:preob 2006.145.20:00:14.14/onsource/TRACKING 2006.145.20:00:14.14:!2006.145.20:00:24 2006.145.20:00:24.00:"tape 2006.145.20:00:24.00:"st=record 2006.145.20:00:24.00:data_valid=on 2006.145.20:00:24.00:midob 2006.145.20:00:25.14/onsource/TRACKING 2006.145.20:00:25.14/wx/15.89,1020.2,88 2006.145.20:00:25.36/cable/+6.5481E-03 2006.145.20:00:26.45/va/01,08,usb,yes,29,31 2006.145.20:00:26.45/va/02,07,usb,yes,31,32 2006.145.20:00:26.45/va/03,08,usb,yes,28,30 2006.145.20:00:26.45/va/04,07,usb,yes,32,34 2006.145.20:00:26.45/va/05,04,usb,yes,28,29 2006.145.20:00:26.45/va/06,04,usb,yes,32,32 2006.145.20:00:26.45/va/07,04,usb,yes,32,33 2006.145.20:00:26.45/va/08,04,usb,yes,27,33 2006.145.20:00:26.68/valo/01,524.99,yes,locked 2006.145.20:00:26.68/valo/02,534.99,yes,locked 2006.145.20:00:26.68/valo/03,564.99,yes,locked 2006.145.20:00:26.68/valo/04,624.99,yes,locked 2006.145.20:00:26.68/valo/05,734.99,yes,locked 2006.145.20:00:26.68/valo/06,814.99,yes,locked 2006.145.20:00:26.68/valo/07,864.99,yes,locked 2006.145.20:00:26.68/valo/08,884.99,yes,locked 2006.145.20:00:27.77/vb/01,03,usb,yes,36,34 2006.145.20:00:27.77/vb/02,04,usb,yes,32,32 2006.145.20:00:27.77/vb/03,04,usb,yes,29,32 2006.145.20:00:27.77/vb/04,04,usb,yes,33,32 2006.145.20:00:27.77/vb/05,04,usb,yes,26,28 2006.145.20:00:27.77/vb/06,04,usb,yes,30,27 2006.145.20:00:27.77/vb/07,04,usb,yes,30,30 2006.145.20:00:27.77/vb/08,04,usb,yes,28,31 2006.145.20:00:28.00/vblo/01,629.99,yes,locked 2006.145.20:00:28.00/vblo/02,634.99,yes,locked 2006.145.20:00:28.00/vblo/03,649.99,yes,locked 2006.145.20:00:28.00/vblo/04,679.99,yes,locked 2006.145.20:00:28.00/vblo/05,709.99,yes,locked 2006.145.20:00:28.00/vblo/06,719.99,yes,locked 2006.145.20:00:28.00/vblo/07,734.99,yes,locked 2006.145.20:00:28.00/vblo/08,744.99,yes,locked 2006.145.20:00:28.15/vabw/8 2006.145.20:00:28.30/vbbw/8 2006.145.20:00:28.39/xfe/off,on,15.2 2006.145.20:00:28.76/ifatt/23,28,28,28 2006.145.20:00:29.08/fmout-gps/S +4.9E-08 2006.145.20:00:29.16:!2006.145.20:01:04 2006.145.20:01:04.00:data_valid=off 2006.145.20:01:04.00:"et 2006.145.20:01:04.01:!+3s 2006.145.20:01:07.02:"tape 2006.145.20:01:07.02:postob 2006.145.20:01:07.10/cable/+6.5506E-03 2006.145.20:01:07.10/wx/15.89,1020.2,88 2006.145.20:01:08.08/fmout-gps/S +4.9E-08 2006.145.20:01:08.08:scan_name=145-2002,jd0605,40 2006.145.20:01:08.09:source=1921-293,192451.06,-291430.1,2000.0,cw 2006.145.20:01:09.14#flagr#flagr/antenna,new-source 2006.145.20:01:09.14:checkk5 2006.145.20:01:09.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.20:01:10.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.20:01:10.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.20:01:10.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.20:01:11.33/chk_obsdata//k5ts1/T1452000??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.20:01:11.79/chk_obsdata//k5ts2/T1452000??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.20:01:12.22/chk_obsdata//k5ts3/T1452000??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.20:01:12.65/chk_obsdata//k5ts4/T1452000??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.20:01:13.42/k5log//k5ts1_log_newline 2006.145.20:01:14.16/k5log//k5ts2_log_newline 2006.145.20:01:14.93/k5log//k5ts3_log_newline 2006.145.20:01:15.67/k5log//k5ts4_log_newline 2006.145.20:01:15.70/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.20:01:15.70:setupk4=1 2006.145.20:01:15.70$setupk4/echo=on 2006.145.20:01:15.70$setupk4/pcalon 2006.145.20:01:15.70$pcalon/"no phase cal control is implemented here 2006.145.20:01:15.70$setupk4/"tpicd=stop 2006.145.20:01:15.70$setupk4/"rec=synch_on 2006.145.20:01:15.70$setupk4/"rec_mode=128 2006.145.20:01:15.70$setupk4/!* 2006.145.20:01:15.70$setupk4/recpk4 2006.145.20:01:15.70$recpk4/recpatch= 2006.145.20:01:15.71$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.20:01:15.71$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.20:01:15.71$setupk4/vck44 2006.145.20:01:15.71$vck44/valo=1,524.99 2006.145.20:01:15.71#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.20:01:15.71#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.20:01:15.71#ibcon#ireg 17 cls_cnt 0 2006.145.20:01:15.71#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:01:15.71#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:01:15.71#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:01:15.74#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.20:01:15.79#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:01:15.79#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:01:15.79#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.20:01:15.79#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.20:01:15.79$vck44/va=1,8 2006.145.20:01:15.79#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.20:01:15.79#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.20:01:15.79#ibcon#ireg 11 cls_cnt 2 2006.145.20:01:15.79#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:01:15.79#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:01:15.79#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:01:15.81#ibcon#[25=AT01-08\r\n] 2006.145.20:01:15.84#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:01:15.84#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:01:15.84#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.20:01:15.84#ibcon#ireg 7 cls_cnt 0 2006.145.20:01:15.84#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:01:15.96#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:01:15.96#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:01:15.99#ibcon#[25=USB\r\n] 2006.145.20:01:16.02#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:01:16.02#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:01:16.02#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.20:01:16.02#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.20:01:16.02$vck44/valo=2,534.99 2006.145.20:01:16.02#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.20:01:16.02#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.20:01:16.02#ibcon#ireg 17 cls_cnt 0 2006.145.20:01:16.02#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:01:16.02#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:01:16.02#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:01:16.04#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.20:01:16.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:01:16.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:01:16.08#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.20:01:16.08#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.20:01:16.08$vck44/va=2,7 2006.145.20:01:16.08#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.20:01:16.08#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.20:01:16.08#ibcon#ireg 11 cls_cnt 2 2006.145.20:01:16.08#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:01:16.14#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:01:16.14#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:01:16.16#ibcon#[25=AT02-07\r\n] 2006.145.20:01:16.20#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:01:16.20#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:01:16.20#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.20:01:16.20#ibcon#ireg 7 cls_cnt 0 2006.145.20:01:16.20#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:01:16.32#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:01:16.32#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:01:16.34#ibcon#[25=USB\r\n] 2006.145.20:01:16.37#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:01:16.37#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:01:16.37#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.20:01:16.37#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.20:01:16.37$vck44/valo=3,564.99 2006.145.20:01:16.37#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.20:01:16.37#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.20:01:16.37#ibcon#ireg 17 cls_cnt 0 2006.145.20:01:16.37#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:01:16.37#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:01:16.37#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:01:16.39#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.20:01:16.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:01:16.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:01:16.43#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.20:01:16.43#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.20:01:16.43$vck44/va=3,8 2006.145.20:01:16.43#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.20:01:16.43#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.20:01:16.43#ibcon#ireg 11 cls_cnt 2 2006.145.20:01:16.43#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:01:16.49#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:01:16.49#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:01:16.51#ibcon#[25=AT03-08\r\n] 2006.145.20:01:16.54#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:01:16.54#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:01:16.54#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.20:01:16.54#ibcon#ireg 7 cls_cnt 0 2006.145.20:01:16.54#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:01:16.66#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:01:16.66#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:01:16.68#ibcon#[25=USB\r\n] 2006.145.20:01:16.71#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:01:16.71#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:01:16.71#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.20:01:16.71#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.20:01:16.71$vck44/valo=4,624.99 2006.145.20:01:16.71#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.20:01:16.71#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.20:01:16.71#ibcon#ireg 17 cls_cnt 0 2006.145.20:01:16.71#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:01:16.71#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:01:16.71#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:01:16.73#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.20:01:16.77#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:01:16.77#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:01:16.77#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.20:01:16.77#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.20:01:16.77$vck44/va=4,7 2006.145.20:01:16.77#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.20:01:16.77#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.20:01:16.77#ibcon#ireg 11 cls_cnt 2 2006.145.20:01:16.77#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:01:16.83#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:01:16.83#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:01:16.85#ibcon#[25=AT04-07\r\n] 2006.145.20:01:16.88#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:01:16.88#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:01:16.88#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.20:01:16.88#ibcon#ireg 7 cls_cnt 0 2006.145.20:01:16.88#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:01:17.00#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:01:17.00#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:01:17.02#ibcon#[25=USB\r\n] 2006.145.20:01:17.05#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:01:17.05#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:01:17.05#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.20:01:17.05#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.20:01:17.05$vck44/valo=5,734.99 2006.145.20:01:17.05#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.20:01:17.05#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.20:01:17.05#ibcon#ireg 17 cls_cnt 0 2006.145.20:01:17.05#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:01:17.05#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:01:17.05#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:01:17.07#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.20:01:17.11#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:01:17.11#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:01:17.11#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.20:01:17.11#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.20:01:17.11$vck44/va=5,4 2006.145.20:01:17.11#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.20:01:17.11#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.20:01:17.11#ibcon#ireg 11 cls_cnt 2 2006.145.20:01:17.11#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:01:17.17#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:01:17.17#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:01:17.19#ibcon#[25=AT05-04\r\n] 2006.145.20:01:17.22#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:01:17.22#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:01:17.22#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.20:01:17.22#ibcon#ireg 7 cls_cnt 0 2006.145.20:01:17.22#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:01:17.34#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:01:17.34#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:01:17.36#ibcon#[25=USB\r\n] 2006.145.20:01:17.39#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:01:17.39#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:01:17.39#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.20:01:17.39#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.20:01:17.39$vck44/valo=6,814.99 2006.145.20:01:17.39#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.20:01:17.39#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.20:01:17.39#ibcon#ireg 17 cls_cnt 0 2006.145.20:01:17.39#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:01:17.39#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:01:17.39#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:01:17.41#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.20:01:17.45#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:01:17.45#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:01:17.45#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.20:01:17.45#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.20:01:17.45$vck44/va=6,4 2006.145.20:01:17.45#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.20:01:17.45#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.20:01:17.45#ibcon#ireg 11 cls_cnt 2 2006.145.20:01:17.45#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:01:17.51#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:01:17.51#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:01:17.53#ibcon#[25=AT06-04\r\n] 2006.145.20:01:17.56#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:01:17.56#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:01:17.56#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.20:01:17.56#ibcon#ireg 7 cls_cnt 0 2006.145.20:01:17.56#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:01:17.68#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:01:17.68#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:01:17.70#ibcon#[25=USB\r\n] 2006.145.20:01:17.73#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:01:17.73#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:01:17.73#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.20:01:17.73#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.20:01:17.73$vck44/valo=7,864.99 2006.145.20:01:17.73#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.20:01:17.73#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.20:01:17.73#ibcon#ireg 17 cls_cnt 0 2006.145.20:01:17.73#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.20:01:17.73#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.20:01:17.73#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.20:01:17.75#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.20:01:17.79#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.20:01:17.79#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.20:01:17.79#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.20:01:17.79#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.20:01:17.79$vck44/va=7,4 2006.145.20:01:17.79#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.20:01:17.79#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.20:01:17.79#ibcon#ireg 11 cls_cnt 2 2006.145.20:01:17.79#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.20:01:17.85#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.20:01:17.85#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.20:01:17.87#ibcon#[25=AT07-04\r\n] 2006.145.20:01:17.90#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.20:01:17.90#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.20:01:17.90#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.20:01:17.90#ibcon#ireg 7 cls_cnt 0 2006.145.20:01:17.90#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.20:01:18.02#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.20:01:18.02#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.20:01:18.04#ibcon#[25=USB\r\n] 2006.145.20:01:18.07#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.20:01:18.07#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.20:01:18.07#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.20:01:18.07#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.20:01:18.07$vck44/valo=8,884.99 2006.145.20:01:18.07#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.20:01:18.07#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.20:01:18.07#ibcon#ireg 17 cls_cnt 0 2006.145.20:01:18.07#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:01:18.07#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:01:18.07#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:01:18.09#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.20:01:18.13#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:01:18.13#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:01:18.13#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.20:01:18.13#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.20:01:18.13$vck44/va=8,4 2006.145.20:01:18.13#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.20:01:18.13#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.20:01:18.13#ibcon#ireg 11 cls_cnt 2 2006.145.20:01:18.13#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:01:18.19#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:01:18.19#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:01:18.21#ibcon#[25=AT08-04\r\n] 2006.145.20:01:18.24#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:01:18.24#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:01:18.24#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.20:01:18.24#ibcon#ireg 7 cls_cnt 0 2006.145.20:01:18.24#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:01:18.36#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:01:18.36#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:01:18.38#ibcon#[25=USB\r\n] 2006.145.20:01:18.41#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:01:18.41#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:01:18.41#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.20:01:18.41#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.20:01:18.41$vck44/vblo=1,629.99 2006.145.20:01:18.41#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.20:01:18.41#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.20:01:18.41#ibcon#ireg 17 cls_cnt 0 2006.145.20:01:18.41#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:01:18.41#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:01:18.41#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:01:18.43#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.20:01:18.47#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:01:18.47#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:01:18.47#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.20:01:18.47#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.20:01:18.47$vck44/vb=1,3 2006.145.20:01:18.47#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.20:01:18.47#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.20:01:18.47#ibcon#ireg 11 cls_cnt 2 2006.145.20:01:18.47#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:01:18.47#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:01:18.47#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:01:18.49#ibcon#[27=AT01-03\r\n] 2006.145.20:01:18.52#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:01:18.52#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:01:18.52#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.20:01:18.52#ibcon#ireg 7 cls_cnt 0 2006.145.20:01:18.52#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:01:18.64#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:01:18.64#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:01:18.66#ibcon#[27=USB\r\n] 2006.145.20:01:18.69#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:01:18.69#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:01:18.69#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.20:01:18.69#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.20:01:18.69$vck44/vblo=2,634.99 2006.145.20:01:18.69#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.20:01:18.69#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.20:01:18.69#ibcon#ireg 17 cls_cnt 0 2006.145.20:01:18.69#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:01:18.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:01:18.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:01:18.71#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.20:01:18.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:01:18.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:01:18.75#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.20:01:18.75#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.20:01:18.75$vck44/vb=2,4 2006.145.20:01:18.75#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.20:01:18.75#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.20:01:18.75#ibcon#ireg 11 cls_cnt 2 2006.145.20:01:18.75#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:01:18.81#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:01:18.81#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:01:18.83#ibcon#[27=AT02-04\r\n] 2006.145.20:01:18.86#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:01:18.86#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:01:18.86#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.20:01:18.86#ibcon#ireg 7 cls_cnt 0 2006.145.20:01:18.86#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:01:18.98#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:01:18.98#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:01:19.00#ibcon#[27=USB\r\n] 2006.145.20:01:19.03#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:01:19.03#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:01:19.03#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.20:01:19.03#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.20:01:19.03$vck44/vblo=3,649.99 2006.145.20:01:19.03#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.20:01:19.03#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.20:01:19.03#ibcon#ireg 17 cls_cnt 0 2006.145.20:01:19.03#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:01:19.03#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:01:19.03#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:01:19.05#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.20:01:19.09#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:01:19.09#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:01:19.09#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.20:01:19.09#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.20:01:19.09$vck44/vb=3,4 2006.145.20:01:19.09#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.20:01:19.09#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.20:01:19.09#ibcon#ireg 11 cls_cnt 2 2006.145.20:01:19.09#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:01:19.15#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:01:19.15#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:01:19.17#ibcon#[27=AT03-04\r\n] 2006.145.20:01:19.20#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:01:19.20#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:01:19.20#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.20:01:19.20#ibcon#ireg 7 cls_cnt 0 2006.145.20:01:19.20#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:01:19.32#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:01:19.32#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:01:19.34#ibcon#[27=USB\r\n] 2006.145.20:01:19.37#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:01:19.37#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:01:19.37#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.20:01:19.37#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.20:01:19.37$vck44/vblo=4,679.99 2006.145.20:01:19.37#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.20:01:19.37#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.20:01:19.37#ibcon#ireg 17 cls_cnt 0 2006.145.20:01:19.37#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:01:19.37#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:01:19.37#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:01:19.39#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.20:01:19.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:01:19.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:01:19.43#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.20:01:19.43#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.20:01:19.43$vck44/vb=4,4 2006.145.20:01:19.43#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.20:01:19.43#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.20:01:19.43#ibcon#ireg 11 cls_cnt 2 2006.145.20:01:19.43#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:01:19.49#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:01:19.49#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:01:19.51#ibcon#[27=AT04-04\r\n] 2006.145.20:01:19.54#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:01:19.54#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:01:19.54#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.20:01:19.54#ibcon#ireg 7 cls_cnt 0 2006.145.20:01:19.54#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:01:19.66#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:01:19.66#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:01:19.68#ibcon#[27=USB\r\n] 2006.145.20:01:19.71#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:01:19.71#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:01:19.71#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.20:01:19.71#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.20:01:19.71$vck44/vblo=5,709.99 2006.145.20:01:19.71#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.20:01:19.71#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.20:01:19.71#ibcon#ireg 17 cls_cnt 0 2006.145.20:01:19.71#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:01:19.71#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:01:19.71#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:01:19.73#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.20:01:19.77#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:01:19.77#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:01:19.77#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.20:01:19.77#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.20:01:19.77$vck44/vb=5,4 2006.145.20:01:19.77#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.20:01:19.77#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.20:01:19.77#ibcon#ireg 11 cls_cnt 2 2006.145.20:01:19.77#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:01:19.83#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:01:19.83#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:01:19.85#ibcon#[27=AT05-04\r\n] 2006.145.20:01:19.88#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:01:19.88#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:01:19.88#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.20:01:19.88#ibcon#ireg 7 cls_cnt 0 2006.145.20:01:19.88#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:01:20.00#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:01:20.00#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:01:20.02#ibcon#[27=USB\r\n] 2006.145.20:01:20.05#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:01:20.05#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:01:20.05#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.20:01:20.05#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.20:01:20.05$vck44/vblo=6,719.99 2006.145.20:01:20.05#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.20:01:20.05#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.20:01:20.05#ibcon#ireg 17 cls_cnt 0 2006.145.20:01:20.05#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:01:20.05#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:01:20.05#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:01:20.07#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.20:01:20.11#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:01:20.11#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:01:20.11#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.20:01:20.11#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.20:01:20.11$vck44/vb=6,4 2006.145.20:01:20.11#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.20:01:20.11#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.20:01:20.11#ibcon#ireg 11 cls_cnt 2 2006.145.20:01:20.11#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:01:20.17#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:01:20.17#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:01:20.19#ibcon#[27=AT06-04\r\n] 2006.145.20:01:20.22#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:01:20.22#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:01:20.22#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.20:01:20.22#ibcon#ireg 7 cls_cnt 0 2006.145.20:01:20.22#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:01:20.34#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:01:20.34#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:01:20.36#ibcon#[27=USB\r\n] 2006.145.20:01:20.39#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:01:20.39#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:01:20.39#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.20:01:20.39#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.20:01:20.39$vck44/vblo=7,734.99 2006.145.20:01:20.39#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.20:01:20.39#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.20:01:20.39#ibcon#ireg 17 cls_cnt 0 2006.145.20:01:20.39#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:01:20.39#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:01:20.39#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:01:20.41#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.20:01:20.45#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:01:20.45#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:01:20.45#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.20:01:20.45#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.20:01:20.45$vck44/vb=7,4 2006.145.20:01:20.45#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.20:01:20.45#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.20:01:20.45#ibcon#ireg 11 cls_cnt 2 2006.145.20:01:20.45#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:01:20.51#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:01:20.51#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:01:20.53#ibcon#[27=AT07-04\r\n] 2006.145.20:01:20.56#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:01:20.56#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:01:20.56#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.20:01:20.56#ibcon#ireg 7 cls_cnt 0 2006.145.20:01:20.56#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:01:20.68#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:01:20.68#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:01:20.70#ibcon#[27=USB\r\n] 2006.145.20:01:20.73#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:01:20.73#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:01:20.73#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.20:01:20.73#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.20:01:20.73$vck44/vblo=8,744.99 2006.145.20:01:20.73#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.20:01:20.73#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.20:01:20.73#ibcon#ireg 17 cls_cnt 0 2006.145.20:01:20.73#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.20:01:20.73#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.20:01:20.73#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.20:01:20.75#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.20:01:20.79#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.20:01:20.79#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.20:01:20.79#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.20:01:20.79#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.20:01:20.79$vck44/vb=8,4 2006.145.20:01:20.79#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.20:01:20.79#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.20:01:20.79#ibcon#ireg 11 cls_cnt 2 2006.145.20:01:20.79#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.20:01:20.85#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.20:01:20.85#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.20:01:20.87#ibcon#[27=AT08-04\r\n] 2006.145.20:01:20.90#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.20:01:20.90#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.20:01:20.90#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.20:01:20.90#ibcon#ireg 7 cls_cnt 0 2006.145.20:01:20.90#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.20:01:21.02#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.20:01:21.02#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.20:01:21.04#ibcon#[27=USB\r\n] 2006.145.20:01:21.07#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.20:01:21.07#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.20:01:21.07#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.20:01:21.07#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.20:01:21.07$vck44/vabw=wide 2006.145.20:01:21.07#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.20:01:21.07#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.20:01:21.07#ibcon#ireg 8 cls_cnt 0 2006.145.20:01:21.07#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:01:21.07#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:01:21.07#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:01:21.09#ibcon#[25=BW32\r\n] 2006.145.20:01:21.12#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:01:21.12#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:01:21.12#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.20:01:21.12#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.20:01:21.12$vck44/vbbw=wide 2006.145.20:01:21.12#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.20:01:21.12#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.20:01:21.12#ibcon#ireg 8 cls_cnt 0 2006.145.20:01:21.12#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:01:21.19#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:01:21.19#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:01:21.21#ibcon#[27=BW32\r\n] 2006.145.20:01:21.24#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:01:21.24#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:01:21.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.20:01:21.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.20:01:21.24$setupk4/ifdk4 2006.145.20:01:21.24$ifdk4/lo= 2006.145.20:01:21.24$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.20:01:21.24$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.20:01:21.24$ifdk4/patch= 2006.145.20:01:21.24$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.20:01:21.24$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.20:01:21.24$setupk4/!*+20s 2006.145.20:01:24.52#abcon#<5=/07 1.2 2.4 15.89 881020.1\r\n> 2006.145.20:01:24.54#abcon#{5=INTERFACE CLEAR} 2006.145.20:01:24.60#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:01:34.69#abcon#<5=/07 1.2 2.4 15.89 881020.1\r\n> 2006.145.20:01:34.71#abcon#{5=INTERFACE CLEAR} 2006.145.20:01:34.77#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:01:35.71$setupk4/"tpicd 2006.145.20:01:35.71$setupk4/echo=off 2006.145.20:01:35.71$setupk4/xlog=off 2006.145.20:01:35.71:!2006.145.20:02:28 2006.145.20:01:46.14#trakl#Source acquired 2006.145.20:01:46.14#flagr#flagr/antenna,acquired 2006.145.20:02:28.00:preob 2006.145.20:02:29.14/onsource/TRACKING 2006.145.20:02:29.14:!2006.145.20:02:38 2006.145.20:02:38.00:"tape 2006.145.20:02:38.00:"st=record 2006.145.20:02:38.00:data_valid=on 2006.145.20:02:38.00:midob 2006.145.20:02:38.14/onsource/TRACKING 2006.145.20:02:38.14/wx/15.89,1020.2,88 2006.145.20:02:38.32/cable/+6.5512E-03 2006.145.20:02:39.41/va/01,08,usb,yes,31,33 2006.145.20:02:39.41/va/02,07,usb,yes,33,34 2006.145.20:02:39.41/va/03,08,usb,yes,30,32 2006.145.20:02:39.41/va/04,07,usb,yes,35,36 2006.145.20:02:39.41/va/05,04,usb,yes,30,31 2006.145.20:02:39.41/va/06,04,usb,yes,34,34 2006.145.20:02:39.41/va/07,04,usb,yes,34,35 2006.145.20:02:39.41/va/08,04,usb,yes,29,35 2006.145.20:02:39.64/valo/01,524.99,yes,locked 2006.145.20:02:39.64/valo/02,534.99,yes,locked 2006.145.20:02:39.64/valo/03,564.99,yes,locked 2006.145.20:02:39.64/valo/04,624.99,yes,locked 2006.145.20:02:39.64/valo/05,734.99,yes,locked 2006.145.20:02:39.64/valo/06,814.99,yes,locked 2006.145.20:02:39.64/valo/07,864.99,yes,locked 2006.145.20:02:39.64/valo/08,884.99,yes,locked 2006.145.20:02:40.73/vb/01,03,usb,yes,38,35 2006.145.20:02:40.73/vb/02,04,usb,yes,33,33 2006.145.20:02:40.73/vb/03,04,usb,yes,30,33 2006.145.20:02:40.73/vb/04,04,usb,yes,35,33 2006.145.20:02:40.73/vb/05,04,usb,yes,27,29 2006.145.20:02:40.73/vb/06,04,usb,yes,31,28 2006.145.20:02:40.73/vb/07,04,usb,yes,31,31 2006.145.20:02:40.73/vb/08,04,usb,yes,29,32 2006.145.20:02:40.96/vblo/01,629.99,yes,locked 2006.145.20:02:40.96/vblo/02,634.99,yes,locked 2006.145.20:02:40.96/vblo/03,649.99,yes,locked 2006.145.20:02:40.96/vblo/04,679.99,yes,locked 2006.145.20:02:40.96/vblo/05,709.99,yes,locked 2006.145.20:02:40.96/vblo/06,719.99,yes,locked 2006.145.20:02:40.96/vblo/07,734.99,yes,locked 2006.145.20:02:40.96/vblo/08,744.99,yes,locked 2006.145.20:02:41.11/vabw/8 2006.145.20:02:41.26/vbbw/8 2006.145.20:02:41.35/xfe/off,on,14.7 2006.145.20:02:41.72/ifatt/23,28,28,28 2006.145.20:02:42.08/fmout-gps/S +5.1E-08 2006.145.20:02:42.12:!2006.145.20:03:18 2006.145.20:03:18.00:data_valid=off 2006.145.20:03:18.00:"et 2006.145.20:03:18.00:!+3s 2006.145.20:03:21.02:"tape 2006.145.20:03:21.02:postob 2006.145.20:03:21.13/cable/+6.5494E-03 2006.145.20:03:21.13/wx/15.89,1020.2,88 2006.145.20:03:21.22/fmout-gps/S +5.1E-08 2006.145.20:03:21.22:scan_name=145-2003,jd0605,100 2006.145.20:03:21.22:source=1908-201,191109.65,-200655.1,2000.0,cw 2006.145.20:03:23.14#flagr#flagr/antenna,new-source 2006.145.20:03:23.14:checkk5 2006.145.20:03:23.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.20:03:24.04/chk_autoobs//k5ts2/ autoobs is running! 2006.145.20:03:24.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.20:03:24.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.20:03:25.32/chk_obsdata//k5ts1/T1452002??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.20:03:25.77/chk_obsdata//k5ts2/T1452002??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.20:03:26.21/chk_obsdata//k5ts3/T1452002??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.20:03:26.66/chk_obsdata//k5ts4/T1452002??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.20:03:27.40/k5log//k5ts1_log_newline 2006.145.20:03:28.15/k5log//k5ts2_log_newline 2006.145.20:03:28.90/k5log//k5ts3_log_newline 2006.145.20:03:29.64/k5log//k5ts4_log_newline 2006.145.20:03:29.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.20:03:29.67:setupk4=1 2006.145.20:03:29.67$setupk4/echo=on 2006.145.20:03:29.67$setupk4/pcalon 2006.145.20:03:29.67$pcalon/"no phase cal control is implemented here 2006.145.20:03:29.67$setupk4/"tpicd=stop 2006.145.20:03:29.67$setupk4/"rec=synch_on 2006.145.20:03:29.67$setupk4/"rec_mode=128 2006.145.20:03:29.67$setupk4/!* 2006.145.20:03:29.67$setupk4/recpk4 2006.145.20:03:29.67$recpk4/recpatch= 2006.145.20:03:29.67$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.20:03:29.67$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.20:03:29.67$setupk4/vck44 2006.145.20:03:29.67$vck44/valo=1,524.99 2006.145.20:03:29.67#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.20:03:29.67#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.20:03:29.67#ibcon#ireg 17 cls_cnt 0 2006.145.20:03:29.67#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:03:29.67#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:03:29.67#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:03:29.69#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.20:03:29.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:03:29.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:03:29.74#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.20:03:29.74#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.20:03:29.74$vck44/va=1,8 2006.145.20:03:29.74#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.20:03:29.74#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.20:03:29.74#ibcon#ireg 11 cls_cnt 2 2006.145.20:03:29.74#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:03:29.74#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:03:29.74#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:03:29.76#ibcon#[25=AT01-08\r\n] 2006.145.20:03:29.79#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:03:29.79#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:03:29.79#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.20:03:29.79#ibcon#ireg 7 cls_cnt 0 2006.145.20:03:29.79#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:03:29.91#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:03:29.91#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:03:29.93#ibcon#[25=USB\r\n] 2006.145.20:03:29.96#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:03:29.96#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:03:29.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.20:03:29.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.20:03:29.96$vck44/valo=2,534.99 2006.145.20:03:29.96#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.20:03:29.96#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.20:03:29.96#ibcon#ireg 17 cls_cnt 0 2006.145.20:03:29.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:03:29.96#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:03:29.96#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:03:29.99#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.20:03:30.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:03:30.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:03:30.03#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.20:03:30.03#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.20:03:30.03$vck44/va=2,7 2006.145.20:03:30.03#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.20:03:30.03#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.20:03:30.03#ibcon#ireg 11 cls_cnt 2 2006.145.20:03:30.03#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:03:30.08#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:03:30.08#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:03:30.10#ibcon#[25=AT02-07\r\n] 2006.145.20:03:30.13#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:03:30.13#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:03:30.13#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.20:03:30.13#ibcon#ireg 7 cls_cnt 0 2006.145.20:03:30.13#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:03:30.25#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:03:30.25#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:03:30.27#ibcon#[25=USB\r\n] 2006.145.20:03:30.30#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:03:30.30#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:03:30.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.20:03:30.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.20:03:30.30$vck44/valo=3,564.99 2006.145.20:03:30.30#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.20:03:30.30#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.20:03:30.30#ibcon#ireg 17 cls_cnt 0 2006.145.20:03:30.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:03:30.30#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:03:30.30#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:03:30.32#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.20:03:30.36#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:03:30.36#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:03:30.36#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.20:03:30.36#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.20:03:30.36$vck44/va=3,8 2006.145.20:03:30.36#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.20:03:30.36#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.20:03:30.36#ibcon#ireg 11 cls_cnt 2 2006.145.20:03:30.36#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.20:03:30.42#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.20:03:30.42#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.20:03:30.44#ibcon#[25=AT03-08\r\n] 2006.145.20:03:30.47#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.20:03:30.47#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.20:03:30.47#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.20:03:30.47#ibcon#ireg 7 cls_cnt 0 2006.145.20:03:30.47#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.20:03:30.59#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.20:03:30.59#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.20:03:30.61#ibcon#[25=USB\r\n] 2006.145.20:03:30.64#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.20:03:30.64#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.20:03:30.64#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.20:03:30.64#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.20:03:30.64$vck44/valo=4,624.99 2006.145.20:03:30.64#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.20:03:30.64#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.20:03:30.64#ibcon#ireg 17 cls_cnt 0 2006.145.20:03:30.64#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:03:30.64#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:03:30.64#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:03:30.66#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.20:03:30.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:03:30.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:03:30.70#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.20:03:30.70#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.20:03:30.70$vck44/va=4,7 2006.145.20:03:30.70#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.20:03:30.70#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.20:03:30.70#ibcon#ireg 11 cls_cnt 2 2006.145.20:03:30.70#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.20:03:30.76#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.20:03:30.76#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.20:03:30.78#ibcon#[25=AT04-07\r\n] 2006.145.20:03:30.81#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.20:03:30.81#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.20:03:30.81#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.20:03:30.81#ibcon#ireg 7 cls_cnt 0 2006.145.20:03:30.81#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.20:03:30.93#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.20:03:30.93#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.20:03:30.95#ibcon#[25=USB\r\n] 2006.145.20:03:30.98#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.20:03:30.98#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.20:03:30.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.20:03:30.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.20:03:30.98$vck44/valo=5,734.99 2006.145.20:03:30.98#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.20:03:30.98#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.20:03:30.98#ibcon#ireg 17 cls_cnt 0 2006.145.20:03:30.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:03:30.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:03:30.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:03:31.00#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.20:03:31.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:03:31.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:03:31.04#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.20:03:31.04#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.20:03:31.04$vck44/va=5,4 2006.145.20:03:31.04#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.20:03:31.04#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.20:03:31.04#ibcon#ireg 11 cls_cnt 2 2006.145.20:03:31.04#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:03:31.10#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:03:31.10#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:03:31.12#ibcon#[25=AT05-04\r\n] 2006.145.20:03:31.15#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:03:31.15#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:03:31.15#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.20:03:31.15#ibcon#ireg 7 cls_cnt 0 2006.145.20:03:31.15#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:03:31.28#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:03:31.28#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:03:31.30#ibcon#[25=USB\r\n] 2006.145.20:03:31.33#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:03:31.33#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:03:31.33#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.20:03:31.33#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.20:03:31.33$vck44/valo=6,814.99 2006.145.20:03:31.33#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.20:03:31.33#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.20:03:31.33#ibcon#ireg 17 cls_cnt 0 2006.145.20:03:31.33#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:03:31.33#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:03:31.33#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:03:31.36#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.20:03:31.40#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:03:31.40#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:03:31.40#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.20:03:31.40#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.20:03:31.40$vck44/va=6,4 2006.145.20:03:31.40#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.20:03:31.40#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.20:03:31.40#ibcon#ireg 11 cls_cnt 2 2006.145.20:03:31.40#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:03:31.45#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:03:31.45#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:03:31.47#ibcon#[25=AT06-04\r\n] 2006.145.20:03:31.50#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:03:31.50#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:03:31.50#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.20:03:31.50#ibcon#ireg 7 cls_cnt 0 2006.145.20:03:31.50#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:03:31.62#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:03:31.62#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:03:31.64#ibcon#[25=USB\r\n] 2006.145.20:03:31.67#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:03:31.67#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:03:31.67#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.20:03:31.67#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.20:03:31.67$vck44/valo=7,864.99 2006.145.20:03:31.67#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.20:03:31.67#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.20:03:31.67#ibcon#ireg 17 cls_cnt 0 2006.145.20:03:31.67#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.20:03:31.67#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.20:03:31.67#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.20:03:31.69#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.20:03:31.73#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.20:03:31.73#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.20:03:31.73#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.20:03:31.73#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.20:03:31.73$vck44/va=7,4 2006.145.20:03:31.73#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.20:03:31.73#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.20:03:31.73#ibcon#ireg 11 cls_cnt 2 2006.145.20:03:31.73#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.20:03:31.79#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.20:03:31.79#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.20:03:31.81#ibcon#[25=AT07-04\r\n] 2006.145.20:03:31.84#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.20:03:31.84#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.20:03:31.84#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.20:03:31.84#ibcon#ireg 7 cls_cnt 0 2006.145.20:03:31.84#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.20:03:31.96#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.20:03:31.96#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.20:03:31.98#ibcon#[25=USB\r\n] 2006.145.20:03:32.01#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.20:03:32.01#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.20:03:32.01#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.20:03:32.01#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.20:03:32.01$vck44/valo=8,884.99 2006.145.20:03:32.01#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.20:03:32.01#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.20:03:32.01#ibcon#ireg 17 cls_cnt 0 2006.145.20:03:32.01#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:03:32.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:03:32.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:03:32.03#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.20:03:32.07#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:03:32.07#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:03:32.07#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.20:03:32.07#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.20:03:32.07$vck44/va=8,4 2006.145.20:03:32.07#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.20:03:32.07#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.20:03:32.07#ibcon#ireg 11 cls_cnt 2 2006.145.20:03:32.07#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.20:03:32.13#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.20:03:32.13#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.20:03:32.15#ibcon#[25=AT08-04\r\n] 2006.145.20:03:32.18#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.20:03:32.18#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.20:03:32.18#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.20:03:32.18#ibcon#ireg 7 cls_cnt 0 2006.145.20:03:32.18#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.20:03:32.30#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.20:03:32.30#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.20:03:32.32#ibcon#[25=USB\r\n] 2006.145.20:03:32.35#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.20:03:32.35#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.20:03:32.35#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.20:03:32.35#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.20:03:32.35$vck44/vblo=1,629.99 2006.145.20:03:32.35#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.20:03:32.35#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.20:03:32.35#ibcon#ireg 17 cls_cnt 0 2006.145.20:03:32.35#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.20:03:32.35#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.20:03:32.35#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.20:03:32.37#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.20:03:32.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.20:03:32.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.20:03:32.41#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.20:03:32.41#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.20:03:32.41$vck44/vb=1,3 2006.145.20:03:32.41#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.20:03:32.41#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.20:03:32.41#ibcon#ireg 11 cls_cnt 2 2006.145.20:03:32.41#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.20:03:32.41#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.20:03:32.41#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.20:03:32.43#ibcon#[27=AT01-03\r\n] 2006.145.20:03:32.46#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.20:03:32.46#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.20:03:32.46#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.20:03:32.46#ibcon#ireg 7 cls_cnt 0 2006.145.20:03:32.46#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.20:03:32.58#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.20:03:32.58#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.20:03:32.60#ibcon#[27=USB\r\n] 2006.145.20:03:32.63#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.20:03:32.63#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.20:03:32.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.20:03:32.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.20:03:32.63$vck44/vblo=2,634.99 2006.145.20:03:32.63#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.20:03:32.63#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.20:03:32.63#ibcon#ireg 17 cls_cnt 0 2006.145.20:03:32.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:03:32.63#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:03:32.63#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:03:32.65#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.20:03:32.69#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:03:32.69#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:03:32.69#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.20:03:32.69#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.20:03:32.69$vck44/vb=2,4 2006.145.20:03:32.69#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.20:03:32.69#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.20:03:32.69#ibcon#ireg 11 cls_cnt 2 2006.145.20:03:32.69#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:03:32.75#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:03:32.75#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:03:32.77#ibcon#[27=AT02-04\r\n] 2006.145.20:03:32.80#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:03:32.80#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:03:32.80#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.20:03:32.80#ibcon#ireg 7 cls_cnt 0 2006.145.20:03:32.80#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:03:32.92#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:03:32.92#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:03:32.94#ibcon#[27=USB\r\n] 2006.145.20:03:32.97#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:03:32.97#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:03:32.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.20:03:32.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.20:03:32.97$vck44/vblo=3,649.99 2006.145.20:03:32.97#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.20:03:32.97#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.20:03:32.97#ibcon#ireg 17 cls_cnt 0 2006.145.20:03:32.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:03:32.97#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:03:32.97#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:03:32.99#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.20:03:33.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:03:33.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:03:33.03#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.20:03:33.03#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.20:03:33.03$vck44/vb=3,4 2006.145.20:03:33.03#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.20:03:33.03#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.20:03:33.03#ibcon#ireg 11 cls_cnt 2 2006.145.20:03:33.03#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:03:33.09#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:03:33.09#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:03:33.11#ibcon#[27=AT03-04\r\n] 2006.145.20:03:33.14#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:03:33.14#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:03:33.14#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.20:03:33.14#ibcon#ireg 7 cls_cnt 0 2006.145.20:03:33.14#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:03:33.26#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:03:33.26#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:03:33.28#ibcon#[27=USB\r\n] 2006.145.20:03:33.31#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:03:33.31#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:03:33.31#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.20:03:33.31#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.20:03:33.31$vck44/vblo=4,679.99 2006.145.20:03:33.31#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.20:03:33.31#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.20:03:33.31#ibcon#ireg 17 cls_cnt 0 2006.145.20:03:33.31#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:03:33.31#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:03:33.31#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:03:33.33#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.20:03:33.37#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:03:33.37#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:03:33.37#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.20:03:33.37#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.20:03:33.37$vck44/vb=4,4 2006.145.20:03:33.37#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.20:03:33.37#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.20:03:33.37#ibcon#ireg 11 cls_cnt 2 2006.145.20:03:33.37#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.20:03:33.43#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.20:03:33.43#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.20:03:33.45#ibcon#[27=AT04-04\r\n] 2006.145.20:03:33.48#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.20:03:33.48#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.20:03:33.48#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.20:03:33.48#ibcon#ireg 7 cls_cnt 0 2006.145.20:03:33.48#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.20:03:33.60#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.20:03:33.60#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.20:03:33.62#ibcon#[27=USB\r\n] 2006.145.20:03:33.65#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.20:03:33.65#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.20:03:33.65#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.20:03:33.65#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.20:03:33.65$vck44/vblo=5,709.99 2006.145.20:03:33.65#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.20:03:33.65#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.20:03:33.65#ibcon#ireg 17 cls_cnt 0 2006.145.20:03:33.65#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:03:33.65#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:03:33.65#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:03:33.67#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.20:03:33.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:03:33.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:03:33.71#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.20:03:33.71#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.20:03:33.71$vck44/vb=5,4 2006.145.20:03:33.71#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.20:03:33.71#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.20:03:33.71#ibcon#ireg 11 cls_cnt 2 2006.145.20:03:33.71#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.20:03:33.77#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.20:03:33.77#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.20:03:33.79#ibcon#[27=AT05-04\r\n] 2006.145.20:03:33.82#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.20:03:33.82#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.20:03:33.82#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.20:03:33.82#ibcon#ireg 7 cls_cnt 0 2006.145.20:03:33.82#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.20:03:33.94#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.20:03:33.94#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.20:03:33.96#ibcon#[27=USB\r\n] 2006.145.20:03:33.99#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.20:03:33.99#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.20:03:33.99#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.20:03:33.99#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.20:03:33.99$vck44/vblo=6,719.99 2006.145.20:03:33.99#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.20:03:33.99#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.20:03:33.99#ibcon#ireg 17 cls_cnt 0 2006.145.20:03:33.99#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:03:33.99#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:03:33.99#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:03:34.01#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.20:03:34.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:03:34.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:03:34.05#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.20:03:34.05#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.20:03:34.05$vck44/vb=6,4 2006.145.20:03:34.05#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.20:03:34.05#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.20:03:34.05#ibcon#ireg 11 cls_cnt 2 2006.145.20:03:34.05#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:03:34.11#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:03:34.11#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:03:34.13#ibcon#[27=AT06-04\r\n] 2006.145.20:03:34.16#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:03:34.16#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:03:34.16#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.20:03:34.16#ibcon#ireg 7 cls_cnt 0 2006.145.20:03:34.16#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:03:34.28#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:03:34.28#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:03:34.30#ibcon#[27=USB\r\n] 2006.145.20:03:34.33#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:03:34.33#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:03:34.33#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.20:03:34.33#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.20:03:34.33$vck44/vblo=7,734.99 2006.145.20:03:34.33#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.20:03:34.33#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.20:03:34.33#ibcon#ireg 17 cls_cnt 0 2006.145.20:03:34.33#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:03:34.33#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:03:34.33#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:03:34.35#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.20:03:34.39#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:03:34.39#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:03:34.39#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.20:03:34.39#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.20:03:34.39$vck44/vb=7,4 2006.145.20:03:34.39#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.20:03:34.39#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.20:03:34.39#ibcon#ireg 11 cls_cnt 2 2006.145.20:03:34.39#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:03:34.45#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:03:34.45#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:03:34.47#ibcon#[27=AT07-04\r\n] 2006.145.20:03:34.50#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:03:34.50#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:03:34.50#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.20:03:34.50#ibcon#ireg 7 cls_cnt 0 2006.145.20:03:34.50#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:03:34.62#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:03:34.62#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:03:34.64#ibcon#[27=USB\r\n] 2006.145.20:03:34.67#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:03:34.67#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:03:34.67#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.20:03:34.67#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.20:03:34.67$vck44/vblo=8,744.99 2006.145.20:03:34.67#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.20:03:34.67#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.20:03:34.67#ibcon#ireg 17 cls_cnt 0 2006.145.20:03:34.67#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.20:03:34.67#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.20:03:34.67#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.20:03:34.69#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.20:03:34.73#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.20:03:34.73#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.20:03:34.73#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.20:03:34.73#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.20:03:34.73$vck44/vb=8,4 2006.145.20:03:34.73#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.20:03:34.73#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.20:03:34.73#ibcon#ireg 11 cls_cnt 2 2006.145.20:03:34.73#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.20:03:34.79#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.20:03:34.79#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.20:03:34.81#ibcon#[27=AT08-04\r\n] 2006.145.20:03:34.84#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.20:03:34.84#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.20:03:34.84#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.20:03:34.84#ibcon#ireg 7 cls_cnt 0 2006.145.20:03:34.84#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.20:03:34.96#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.20:03:34.96#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.20:03:34.98#ibcon#[27=USB\r\n] 2006.145.20:03:35.01#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.20:03:35.01#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.20:03:35.01#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.20:03:35.01#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.20:03:35.01$vck44/vabw=wide 2006.145.20:03:35.01#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.20:03:35.01#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.20:03:35.01#ibcon#ireg 8 cls_cnt 0 2006.145.20:03:35.01#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:03:35.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:03:35.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:03:35.03#ibcon#[25=BW32\r\n] 2006.145.20:03:35.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:03:35.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:03:35.06#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.20:03:35.06#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.20:03:35.06$vck44/vbbw=wide 2006.145.20:03:35.06#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.20:03:35.06#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.20:03:35.06#ibcon#ireg 8 cls_cnt 0 2006.145.20:03:35.06#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:03:35.13#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:03:35.13#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:03:35.15#ibcon#[27=BW32\r\n] 2006.145.20:03:35.18#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:03:35.18#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:03:35.18#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.20:03:35.18#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.20:03:35.18$setupk4/ifdk4 2006.145.20:03:35.18$ifdk4/lo= 2006.145.20:03:35.18$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.20:03:35.18$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.20:03:35.18$ifdk4/patch= 2006.145.20:03:35.18$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.20:03:35.18$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.20:03:35.18$setupk4/!*+20s 2006.145.20:03:36.84#abcon#<5=/07 1.3 2.8 15.89 881020.2\r\n> 2006.145.20:03:36.86#abcon#{5=INTERFACE CLEAR} 2006.145.20:03:36.92#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:03:38.14#trakl#Source acquired 2006.145.20:03:39.14#flagr#flagr/antenna,acquired 2006.145.20:03:47.01#abcon#<5=/07 1.3 2.8 15.89 881020.2\r\n> 2006.145.20:03:47.03#abcon#{5=INTERFACE CLEAR} 2006.145.20:03:47.09#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:03:49.68$setupk4/"tpicd 2006.145.20:03:49.68$setupk4/echo=off 2006.145.20:03:49.68$setupk4/xlog=off 2006.145.20:03:49.68:!2006.145.20:03:44 2006.145.20:03:49.68:preob 2006.145.20:03:50.14/onsource/TRACKING 2006.145.20:03:50.14:!2006.145.20:03:54 2006.145.20:03:54.00:"tape 2006.145.20:03:54.00:"st=record 2006.145.20:03:54.00:data_valid=on 2006.145.20:03:54.00:midob 2006.145.20:03:54.14/onsource/TRACKING 2006.145.20:03:54.14/wx/15.89,1020.2,88 2006.145.20:03:54.29/cable/+6.5508E-03 2006.145.20:03:55.38/va/01,08,usb,yes,30,32 2006.145.20:03:55.38/va/02,07,usb,yes,32,33 2006.145.20:03:55.38/va/03,08,usb,yes,29,30 2006.145.20:03:55.38/va/04,07,usb,yes,33,35 2006.145.20:03:55.38/va/05,04,usb,yes,29,29 2006.145.20:03:55.38/va/06,04,usb,yes,32,32 2006.145.20:03:55.38/va/07,04,usb,yes,33,34 2006.145.20:03:55.38/va/08,04,usb,yes,28,33 2006.145.20:03:55.61/valo/01,524.99,yes,locked 2006.145.20:03:55.61/valo/02,534.99,yes,locked 2006.145.20:03:55.61/valo/03,564.99,yes,locked 2006.145.20:03:55.61/valo/04,624.99,yes,locked 2006.145.20:03:55.61/valo/05,734.99,yes,locked 2006.145.20:03:55.61/valo/06,814.99,yes,locked 2006.145.20:03:55.61/valo/07,864.99,yes,locked 2006.145.20:03:55.61/valo/08,884.99,yes,locked 2006.145.20:03:56.70/vb/01,03,usb,yes,37,34 2006.145.20:03:56.70/vb/02,04,usb,yes,32,32 2006.145.20:03:56.70/vb/03,04,usb,yes,29,32 2006.145.20:03:56.70/vb/04,04,usb,yes,33,32 2006.145.20:03:56.70/vb/05,04,usb,yes,26,28 2006.145.20:03:56.70/vb/06,04,usb,yes,30,27 2006.145.20:03:56.70/vb/07,04,usb,yes,30,30 2006.145.20:03:56.70/vb/08,04,usb,yes,28,31 2006.145.20:03:56.94/vblo/01,629.99,yes,locked 2006.145.20:03:56.94/vblo/02,634.99,yes,locked 2006.145.20:03:56.94/vblo/03,649.99,yes,locked 2006.145.20:03:56.94/vblo/04,679.99,yes,locked 2006.145.20:03:56.94/vblo/05,709.99,yes,locked 2006.145.20:03:56.94/vblo/06,719.99,yes,locked 2006.145.20:03:56.94/vblo/07,734.99,yes,locked 2006.145.20:03:56.94/vblo/08,744.99,yes,locked 2006.145.20:03:57.09/vabw/8 2006.145.20:03:57.24/vbbw/8 2006.145.20:03:57.40/xfe/off,on,14.7 2006.145.20:03:57.78/ifatt/23,28,28,28 2006.145.20:03:58.08/fmout-gps/S +5.1E-08 2006.145.20:03:58.12:!2006.145.20:05:34 2006.145.20:05:34.00:data_valid=off 2006.145.20:05:34.00:"et 2006.145.20:05:34.00:!+3s 2006.145.20:05:37.02:"tape 2006.145.20:05:37.02:postob 2006.145.20:05:37.18/cable/+6.5503E-03 2006.145.20:05:37.22/wx/15.90,1020.2,88 2006.145.20:05:38.08/fmout-gps/S +5.1E-08 2006.145.20:05:38.08:scan_name=145-2010,jd0605,40 2006.145.20:05:38.08:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.145.20:05:39.14#flagr#flagr/antenna,new-source 2006.145.20:05:39.14:checkk5 2006.145.20:05:39.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.20:05:40.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.20:05:40.44/chk_autoobs//k5ts3/ autoobs is running! 2006.145.20:05:40.87/chk_autoobs//k5ts4/ autoobs is running! 2006.145.20:05:41.30/chk_obsdata//k5ts1/T1452003??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.20:05:41.75/chk_obsdata//k5ts2/T1452003??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.20:05:42.19/chk_obsdata//k5ts3/T1452003??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.20:05:42.64/chk_obsdata//k5ts4/T1452003??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.20:05:43.40/k5log//k5ts1_log_newline 2006.145.20:05:44.14/k5log//k5ts2_log_newline 2006.145.20:05:44.89/k5log//k5ts3_log_newline 2006.145.20:05:45.62/k5log//k5ts4_log_newline 2006.145.20:05:45.65/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.20:05:45.65:setupk4=1 2006.145.20:05:45.65$setupk4/echo=on 2006.145.20:05:45.65$setupk4/pcalon 2006.145.20:05:45.65$pcalon/"no phase cal control is implemented here 2006.145.20:05:45.65$setupk4/"tpicd=stop 2006.145.20:05:45.65$setupk4/"rec=synch_on 2006.145.20:05:45.65$setupk4/"rec_mode=128 2006.145.20:05:45.65$setupk4/!* 2006.145.20:05:45.65$setupk4/recpk4 2006.145.20:05:45.65$recpk4/recpatch= 2006.145.20:05:45.65$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.20:05:45.65$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.20:05:45.65$setupk4/vck44 2006.145.20:05:45.65$vck44/valo=1,524.99 2006.145.20:05:45.65#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.20:05:45.65#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.20:05:45.65#ibcon#ireg 17 cls_cnt 0 2006.145.20:05:45.65#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:05:45.65#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:05:45.65#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:05:45.67#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.20:05:45.72#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:05:45.72#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:05:45.72#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.20:05:45.72#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.20:05:45.72$vck44/va=1,8 2006.145.20:05:45.72#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.20:05:45.72#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.20:05:45.72#ibcon#ireg 11 cls_cnt 2 2006.145.20:05:45.72#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.20:05:45.72#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.20:05:45.72#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.20:05:45.74#ibcon#[25=AT01-08\r\n] 2006.145.20:05:45.77#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.20:05:45.77#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.20:05:45.77#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.20:05:45.77#ibcon#ireg 7 cls_cnt 0 2006.145.20:05:45.77#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.20:05:45.89#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.20:05:45.89#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.20:05:45.91#ibcon#[25=USB\r\n] 2006.145.20:05:45.95#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.20:05:45.95#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.20:05:45.95#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.20:05:45.95#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.20:05:45.96$vck44/valo=2,534.99 2006.145.20:05:45.96#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.20:05:45.96#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.20:05:45.96#ibcon#ireg 17 cls_cnt 0 2006.145.20:05:45.96#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.20:05:45.96#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.20:05:45.96#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.20:05:45.97#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.20:05:46.01#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.20:05:46.01#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.20:05:46.01#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.20:05:46.01#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.20:05:46.01$vck44/va=2,7 2006.145.20:05:46.01#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.20:05:46.01#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.20:05:46.01#ibcon#ireg 11 cls_cnt 2 2006.145.20:05:46.01#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.20:05:46.07#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.20:05:46.07#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.20:05:46.09#ibcon#[25=AT02-07\r\n] 2006.145.20:05:46.12#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.20:05:46.12#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.20:05:46.12#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.20:05:46.12#ibcon#ireg 7 cls_cnt 0 2006.145.20:05:46.12#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.20:05:46.24#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.20:05:46.24#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.20:05:46.26#ibcon#[25=USB\r\n] 2006.145.20:05:46.29#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.20:05:46.29#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.20:05:46.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.20:05:46.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.20:05:46.29$vck44/valo=3,564.99 2006.145.20:05:46.29#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.20:05:46.29#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.20:05:46.29#ibcon#ireg 17 cls_cnt 0 2006.145.20:05:46.29#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:05:46.29#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:05:46.29#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:05:46.31#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.20:05:46.35#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:05:46.35#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:05:46.35#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.20:05:46.35#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.20:05:46.35$vck44/va=3,8 2006.145.20:05:46.35#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.20:05:46.35#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.20:05:46.35#ibcon#ireg 11 cls_cnt 2 2006.145.20:05:46.35#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:05:46.41#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:05:46.41#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:05:46.43#ibcon#[25=AT03-08\r\n] 2006.145.20:05:46.46#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:05:46.46#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:05:46.46#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.20:05:46.46#ibcon#ireg 7 cls_cnt 0 2006.145.20:05:46.46#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:05:46.58#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:05:46.58#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:05:46.60#ibcon#[25=USB\r\n] 2006.145.20:05:46.63#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:05:46.63#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:05:46.63#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.20:05:46.63#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.20:05:46.63$vck44/valo=4,624.99 2006.145.20:05:46.63#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.20:05:46.63#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.20:05:46.63#ibcon#ireg 17 cls_cnt 0 2006.145.20:05:46.63#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:05:46.63#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:05:46.63#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:05:46.65#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.20:05:46.69#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:05:46.69#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:05:46.69#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.20:05:46.69#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.20:05:46.69$vck44/va=4,7 2006.145.20:05:46.69#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.20:05:46.69#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.20:05:46.69#ibcon#ireg 11 cls_cnt 2 2006.145.20:05:46.69#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:05:46.75#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:05:46.75#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:05:46.77#ibcon#[25=AT04-07\r\n] 2006.145.20:05:46.80#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:05:46.80#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:05:46.80#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.20:05:46.80#ibcon#ireg 7 cls_cnt 0 2006.145.20:05:46.80#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:05:46.92#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:05:46.92#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:05:46.94#ibcon#[25=USB\r\n] 2006.145.20:05:46.97#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:05:46.97#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:05:46.97#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.20:05:46.97#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.20:05:46.97$vck44/valo=5,734.99 2006.145.20:05:46.97#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.20:05:46.97#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.20:05:46.97#ibcon#ireg 17 cls_cnt 0 2006.145.20:05:46.97#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:05:46.97#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:05:46.97#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:05:46.99#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.20:05:47.03#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:05:47.03#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:05:47.03#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.20:05:47.03#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.20:05:47.03$vck44/va=5,4 2006.145.20:05:47.03#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.20:05:47.03#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.20:05:47.03#ibcon#ireg 11 cls_cnt 2 2006.145.20:05:47.03#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:05:47.09#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:05:47.09#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:05:47.11#ibcon#[25=AT05-04\r\n] 2006.145.20:05:47.14#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:05:47.14#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:05:47.14#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.20:05:47.14#ibcon#ireg 7 cls_cnt 0 2006.145.20:05:47.14#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:05:47.26#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:05:47.26#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:05:47.29#ibcon#[25=USB\r\n] 2006.145.20:05:47.32#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:05:47.32#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:05:47.32#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.20:05:47.32#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.20:05:47.32$vck44/valo=6,814.99 2006.145.20:05:47.32#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.20:05:47.32#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.20:05:47.32#ibcon#ireg 17 cls_cnt 0 2006.145.20:05:47.32#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:05:47.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:05:47.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:05:47.34#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.20:05:47.38#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:05:47.38#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:05:47.38#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.20:05:47.38#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.20:05:47.38$vck44/va=6,4 2006.145.20:05:47.38#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.20:05:47.38#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.20:05:47.38#ibcon#ireg 11 cls_cnt 2 2006.145.20:05:47.38#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.20:05:47.44#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.20:05:47.44#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.20:05:47.46#ibcon#[25=AT06-04\r\n] 2006.145.20:05:47.49#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.20:05:47.49#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.20:05:47.49#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.20:05:47.49#ibcon#ireg 7 cls_cnt 0 2006.145.20:05:47.49#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.20:05:47.61#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.20:05:47.61#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.20:05:47.63#ibcon#[25=USB\r\n] 2006.145.20:05:47.66#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.20:05:47.66#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.20:05:47.66#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.20:05:47.66#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.20:05:47.66$vck44/valo=7,864.99 2006.145.20:05:47.66#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.20:05:47.66#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.20:05:47.66#ibcon#ireg 17 cls_cnt 0 2006.145.20:05:47.66#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:05:47.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:05:47.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:05:47.68#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.20:05:47.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:05:47.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:05:47.72#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.20:05:47.72#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.20:05:47.72$vck44/va=7,4 2006.145.20:05:47.72#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.20:05:47.72#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.20:05:47.72#ibcon#ireg 11 cls_cnt 2 2006.145.20:05:47.72#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:05:47.78#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:05:47.78#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:05:47.80#ibcon#[25=AT07-04\r\n] 2006.145.20:05:47.83#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:05:47.83#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:05:47.83#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.20:05:47.83#ibcon#ireg 7 cls_cnt 0 2006.145.20:05:47.83#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:05:47.95#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:05:47.95#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:05:47.97#ibcon#[25=USB\r\n] 2006.145.20:05:48.00#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:05:48.00#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:05:48.00#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.20:05:48.00#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.20:05:48.00$vck44/valo=8,884.99 2006.145.20:05:48.00#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.20:05:48.00#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.20:05:48.00#ibcon#ireg 17 cls_cnt 0 2006.145.20:05:48.00#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:05:48.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:05:48.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:05:48.02#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.20:05:48.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:05:48.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:05:48.06#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.20:05:48.06#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.20:05:48.06$vck44/va=8,4 2006.145.20:05:48.06#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.20:05:48.06#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.20:05:48.06#ibcon#ireg 11 cls_cnt 2 2006.145.20:05:48.06#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.20:05:48.12#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.20:05:48.12#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.20:05:48.14#ibcon#[25=AT08-04\r\n] 2006.145.20:05:48.17#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.20:05:48.17#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.20:05:48.17#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.20:05:48.17#ibcon#ireg 7 cls_cnt 0 2006.145.20:05:48.17#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.20:05:48.29#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.20:05:48.29#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.20:05:48.31#ibcon#[25=USB\r\n] 2006.145.20:05:48.34#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.20:05:48.34#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.20:05:48.34#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.20:05:48.34#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.20:05:48.34$vck44/vblo=1,629.99 2006.145.20:05:48.34#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.20:05:48.34#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.20:05:48.34#ibcon#ireg 17 cls_cnt 0 2006.145.20:05:48.34#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.20:05:48.34#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.20:05:48.34#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.20:05:48.36#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.20:05:48.40#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.20:05:48.40#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.20:05:48.40#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.20:05:48.40#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.20:05:48.40$vck44/vb=1,3 2006.145.20:05:48.40#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.20:05:48.40#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.20:05:48.40#ibcon#ireg 11 cls_cnt 2 2006.145.20:05:48.40#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.20:05:48.40#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.20:05:48.40#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.20:05:48.43#ibcon#[27=AT01-03\r\n] 2006.145.20:05:48.46#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.20:05:48.46#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.20:05:48.46#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.20:05:48.46#ibcon#ireg 7 cls_cnt 0 2006.145.20:05:48.46#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.20:05:48.58#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.20:05:48.58#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.20:05:48.60#ibcon#[27=USB\r\n] 2006.145.20:05:48.63#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.20:05:48.63#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.20:05:48.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.20:05:48.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.20:05:48.63$vck44/vblo=2,634.99 2006.145.20:05:48.63#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.20:05:48.63#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.20:05:48.63#ibcon#ireg 17 cls_cnt 0 2006.145.20:05:48.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:05:48.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:05:48.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:05:48.65#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.20:05:48.69#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:05:48.69#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:05:48.69#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.20:05:48.69#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.20:05:48.69$vck44/vb=2,4 2006.145.20:05:48.69#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.20:05:48.69#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.20:05:48.69#ibcon#ireg 11 cls_cnt 2 2006.145.20:05:48.69#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.20:05:48.75#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.20:05:48.75#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.20:05:48.77#ibcon#[27=AT02-04\r\n] 2006.145.20:05:48.80#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.20:05:48.80#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.20:05:48.80#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.20:05:48.80#ibcon#ireg 7 cls_cnt 0 2006.145.20:05:48.80#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.20:05:48.92#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.20:05:48.92#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.20:05:48.94#ibcon#[27=USB\r\n] 2006.145.20:05:48.97#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.20:05:48.97#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.20:05:48.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.20:05:48.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.20:05:48.97$vck44/vblo=3,649.99 2006.145.20:05:48.97#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.20:05:48.97#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.20:05:48.97#ibcon#ireg 17 cls_cnt 0 2006.145.20:05:48.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.20:05:48.97#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.20:05:48.97#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.20:05:48.99#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.20:05:49.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.20:05:49.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.20:05:49.03#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.20:05:49.03#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.20:05:49.03$vck44/vb=3,4 2006.145.20:05:49.03#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.20:05:49.03#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.20:05:49.03#ibcon#ireg 11 cls_cnt 2 2006.145.20:05:49.03#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:05:49.05#abcon#<5=/08 1.3 3.0 15.90 881020.2\r\n> 2006.145.20:05:49.07#abcon#{5=INTERFACE CLEAR} 2006.145.20:05:49.09#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:05:49.09#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:05:49.11#ibcon#[27=AT03-04\r\n] 2006.145.20:05:49.13#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:05:49.14#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:05:49.14#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:05:49.14#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.20:05:49.14#ibcon#ireg 7 cls_cnt 0 2006.145.20:05:49.14#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:05:49.26#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:05:49.26#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:05:49.28#ibcon#[27=USB\r\n] 2006.145.20:05:49.31#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:05:49.31#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:05:49.31#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.20:05:49.31#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.20:05:49.31$vck44/vblo=4,679.99 2006.145.20:05:49.31#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.20:05:49.31#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.20:05:49.31#ibcon#ireg 17 cls_cnt 0 2006.145.20:05:49.31#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:05:49.31#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:05:49.31#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:05:49.33#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.20:05:49.37#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:05:49.37#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:05:49.37#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.20:05:49.37#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.20:05:49.37$vck44/vb=4,4 2006.145.20:05:49.37#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.20:05:49.37#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.20:05:49.37#ibcon#ireg 11 cls_cnt 2 2006.145.20:05:49.37#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:05:49.43#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:05:49.43#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:05:49.45#ibcon#[27=AT04-04\r\n] 2006.145.20:05:49.48#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:05:49.48#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:05:49.48#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.20:05:49.48#ibcon#ireg 7 cls_cnt 0 2006.145.20:05:49.48#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:05:49.60#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:05:49.60#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:05:49.62#ibcon#[27=USB\r\n] 2006.145.20:05:49.65#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:05:49.65#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:05:49.65#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.20:05:49.65#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.20:05:49.65$vck44/vblo=5,709.99 2006.145.20:05:49.65#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.20:05:49.65#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.20:05:49.65#ibcon#ireg 17 cls_cnt 0 2006.145.20:05:49.65#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:05:49.65#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:05:49.65#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:05:49.67#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.20:05:49.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:05:49.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:05:49.71#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.20:05:49.71#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.20:05:49.71$vck44/vb=5,4 2006.145.20:05:49.71#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.20:05:49.71#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.20:05:49.71#ibcon#ireg 11 cls_cnt 2 2006.145.20:05:49.71#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:05:49.77#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:05:49.77#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:05:49.79#ibcon#[27=AT05-04\r\n] 2006.145.20:05:49.82#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:05:49.82#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:05:49.82#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.20:05:49.82#ibcon#ireg 7 cls_cnt 0 2006.145.20:05:49.82#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:05:49.94#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:05:49.94#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:05:49.96#ibcon#[27=USB\r\n] 2006.145.20:05:49.99#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:05:49.99#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:05:49.99#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.20:05:49.99#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.20:05:49.99$vck44/vblo=6,719.99 2006.145.20:05:49.99#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.20:05:49.99#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.20:05:49.99#ibcon#ireg 17 cls_cnt 0 2006.145.20:05:49.99#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:05:49.99#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:05:49.99#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:05:50.01#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.20:05:50.05#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:05:50.05#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:05:50.05#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.20:05:50.05#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.20:05:50.05$vck44/vb=6,4 2006.145.20:05:50.05#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.20:05:50.05#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.20:05:50.05#ibcon#ireg 11 cls_cnt 2 2006.145.20:05:50.05#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.20:05:50.11#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.20:05:50.11#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.20:05:50.13#ibcon#[27=AT06-04\r\n] 2006.145.20:05:50.16#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.20:05:50.16#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.20:05:50.16#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.20:05:50.16#ibcon#ireg 7 cls_cnt 0 2006.145.20:05:50.16#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.20:05:50.28#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.20:05:50.28#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.20:05:50.30#ibcon#[27=USB\r\n] 2006.145.20:05:50.33#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.20:05:50.33#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.20:05:50.33#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.20:05:50.33#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.20:05:50.33$vck44/vblo=7,734.99 2006.145.20:05:50.33#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.20:05:50.33#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.20:05:50.33#ibcon#ireg 17 cls_cnt 0 2006.145.20:05:50.33#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:05:50.33#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:05:50.33#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:05:50.35#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.20:05:50.39#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:05:50.39#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:05:50.39#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.20:05:50.39#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.20:05:50.39$vck44/vb=7,4 2006.145.20:05:50.39#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.20:05:50.39#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.20:05:50.39#ibcon#ireg 11 cls_cnt 2 2006.145.20:05:50.39#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:05:50.45#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:05:50.45#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:05:50.47#ibcon#[27=AT07-04\r\n] 2006.145.20:05:50.50#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:05:50.50#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:05:50.50#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.20:05:50.50#ibcon#ireg 7 cls_cnt 0 2006.145.20:05:50.50#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:05:50.62#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:05:50.62#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:05:50.64#ibcon#[27=USB\r\n] 2006.145.20:05:50.67#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:05:50.67#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:05:50.67#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.20:05:50.67#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.20:05:50.67$vck44/vblo=8,744.99 2006.145.20:05:50.67#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.20:05:50.67#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.20:05:50.67#ibcon#ireg 17 cls_cnt 0 2006.145.20:05:50.67#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:05:50.67#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:05:50.67#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:05:50.69#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.20:05:50.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:05:50.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:05:50.73#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.20:05:50.73#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.20:05:50.73$vck44/vb=8,4 2006.145.20:05:50.73#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.20:05:50.73#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.20:05:50.73#ibcon#ireg 11 cls_cnt 2 2006.145.20:05:50.73#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.20:05:50.79#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.20:05:50.79#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.20:05:50.81#ibcon#[27=AT08-04\r\n] 2006.145.20:05:50.84#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.20:05:50.84#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.20:05:50.84#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.20:05:50.84#ibcon#ireg 7 cls_cnt 0 2006.145.20:05:50.84#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.20:05:50.96#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.20:05:50.96#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.20:05:50.98#ibcon#[27=USB\r\n] 2006.145.20:05:51.01#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.20:05:51.01#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.20:05:51.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.20:05:51.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.20:05:51.01$vck44/vabw=wide 2006.145.20:05:51.01#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.20:05:51.01#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.20:05:51.01#ibcon#ireg 8 cls_cnt 0 2006.145.20:05:51.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.20:05:51.01#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.20:05:51.01#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.20:05:51.03#ibcon#[25=BW32\r\n] 2006.145.20:05:51.06#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.20:05:51.06#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.20:05:51.06#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.20:05:51.06#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.20:05:51.06$vck44/vbbw=wide 2006.145.20:05:51.06#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.20:05:51.06#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.20:05:51.06#ibcon#ireg 8 cls_cnt 0 2006.145.20:05:51.06#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:05:51.13#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:05:51.13#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:05:51.15#ibcon#[27=BW32\r\n] 2006.145.20:05:51.18#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:05:51.18#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:05:51.18#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.20:05:51.18#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.20:05:51.18$setupk4/ifdk4 2006.145.20:05:51.18$ifdk4/lo= 2006.145.20:05:51.18$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.20:05:51.18$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.20:05:51.18$ifdk4/patch= 2006.145.20:05:51.18$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.20:05:51.18$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.20:05:51.18$setupk4/!*+20s 2006.145.20:05:58.14#trakl#Source acquired 2006.145.20:05:58.14#flagr#flagr/antenna,acquired 2006.145.20:05:59.22#abcon#<5=/08 1.3 3.0 15.91 881020.2\r\n> 2006.145.20:05:59.24#abcon#{5=INTERFACE CLEAR} 2006.145.20:05:59.30#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:06:05.66$setupk4/"tpicd 2006.145.20:06:05.66$setupk4/echo=off 2006.145.20:06:05.66$setupk4/xlog=off 2006.145.20:06:05.66:!2006.145.20:10:00 2006.145.20:10:00.00:preob 2006.145.20:10:00.14/onsource/TRACKING 2006.145.20:10:00.14:!2006.145.20:10:10 2006.145.20:10:10.02:"tape 2006.145.20:10:10.02:"st=record 2006.145.20:10:10.02:data_valid=on 2006.145.20:10:10.02:midob 2006.145.20:10:11.14/onsource/TRACKING 2006.145.20:10:11.14/wx/15.94,1020.2,88 2006.145.20:10:11.22/cable/+6.5517E-03 2006.145.20:10:12.31/va/01,08,usb,yes,30,32 2006.145.20:10:12.31/va/02,07,usb,yes,32,33 2006.145.20:10:12.31/va/03,08,usb,yes,29,31 2006.145.20:10:12.31/va/04,07,usb,yes,33,35 2006.145.20:10:12.31/va/05,04,usb,yes,29,30 2006.145.20:10:12.31/va/06,04,usb,yes,33,33 2006.145.20:10:12.31/va/07,04,usb,yes,33,34 2006.145.20:10:12.31/va/08,04,usb,yes,28,34 2006.145.20:10:12.54/valo/01,524.99,yes,locked 2006.145.20:10:12.54/valo/02,534.99,yes,locked 2006.145.20:10:12.54/valo/03,564.99,yes,locked 2006.145.20:10:12.54/valo/04,624.99,yes,locked 2006.145.20:10:12.54/valo/05,734.99,yes,locked 2006.145.20:10:12.54/valo/06,814.99,yes,locked 2006.145.20:10:12.54/valo/07,864.99,yes,locked 2006.145.20:10:12.54/valo/08,884.99,yes,locked 2006.145.20:10:13.62/vb/01,03,usb,yes,37,35 2006.145.20:10:13.62/vb/02,04,usb,yes,33,32 2006.145.20:10:13.62/vb/03,04,usb,yes,29,32 2006.145.20:10:13.62/vb/04,04,usb,yes,34,33 2006.145.20:10:13.62/vb/05,04,usb,yes,26,29 2006.145.20:10:13.62/vb/06,04,usb,yes,31,27 2006.145.20:10:13.62/vb/07,04,usb,yes,31,30 2006.145.20:10:13.62/vb/08,04,usb,yes,28,31 2006.145.20:10:13.85/vblo/01,629.99,yes,locked 2006.145.20:10:13.85/vblo/02,634.99,yes,locked 2006.145.20:10:13.85/vblo/03,649.99,yes,locked 2006.145.20:10:13.85/vblo/04,679.99,yes,locked 2006.145.20:10:13.85/vblo/05,709.99,yes,locked 2006.145.20:10:13.85/vblo/06,719.99,yes,locked 2006.145.20:10:13.85/vblo/07,734.99,yes,locked 2006.145.20:10:13.85/vblo/08,744.99,yes,locked 2006.145.20:10:14.00/vabw/8 2006.145.20:10:14.15/vbbw/8 2006.145.20:10:14.24/xfe/off,on,14.7 2006.145.20:10:14.61/ifatt/23,28,28,28 2006.145.20:10:15.08/fmout-gps/S +5.1E-08 2006.145.20:10:15.12:!2006.145.20:10:50 2006.145.20:10:50.02:data_valid=off 2006.145.20:10:50.02:"et 2006.145.20:10:50.02:!+3s 2006.145.20:10:53.06:"tape 2006.145.20:10:53.06:postob 2006.145.20:10:53.29/cable/+6.5481E-03 2006.145.20:10:53.29/wx/15.94,1020.2,88 2006.145.20:10:53.37/fmout-gps/S +5.1E-08 2006.145.20:10:53.38:scan_name=145-2012,jd0605,70 2006.145.20:10:53.38:source=2136+141,213901.31,142336.0,2000.0,cw 2006.145.20:10:54.15#flagr#flagr/antenna,new-source 2006.145.20:10:54.15:checkk5 2006.145.20:10:54.61/chk_autoobs//k5ts1/ autoobs is running! 2006.145.20:10:55.05/chk_autoobs//k5ts2/ autoobs is running! 2006.145.20:10:55.48/chk_autoobs//k5ts3/ autoobs is running! 2006.145.20:10:55.91/chk_autoobs//k5ts4/ autoobs is running! 2006.145.20:10:56.33/chk_obsdata//k5ts1/T1452010??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.20:10:56.78/chk_obsdata//k5ts2/T1452010??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.20:10:57.22/chk_obsdata//k5ts3/T1452010??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.20:10:57.67/chk_obsdata//k5ts4/T1452010??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.20:10:58.44/k5log//k5ts1_log_newline 2006.145.20:10:59.18/k5log//k5ts2_log_newline 2006.145.20:10:59.93/k5log//k5ts3_log_newline 2006.145.20:11:00.68/k5log//k5ts4_log_newline 2006.145.20:11:00.70/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.20:11:00.70:setupk4=1 2006.145.20:11:00.70$setupk4/echo=on 2006.145.20:11:00.70$setupk4/pcalon 2006.145.20:11:00.70$pcalon/"no phase cal control is implemented here 2006.145.20:11:00.70$setupk4/"tpicd=stop 2006.145.20:11:00.70$setupk4/"rec=synch_on 2006.145.20:11:00.70$setupk4/"rec_mode=128 2006.145.20:11:00.70$setupk4/!* 2006.145.20:11:00.70$setupk4/recpk4 2006.145.20:11:00.70$recpk4/recpatch= 2006.145.20:11:00.71$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.20:11:00.71$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.20:11:00.71$setupk4/vck44 2006.145.20:11:00.71$vck44/valo=1,524.99 2006.145.20:11:00.71#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.20:11:00.71#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.20:11:00.71#ibcon#ireg 17 cls_cnt 0 2006.145.20:11:00.71#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:11:00.71#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:11:00.71#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:11:00.74#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.20:11:00.79#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:11:00.79#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:11:00.79#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.20:11:00.79#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.20:11:00.80$vck44/va=1,8 2006.145.20:11:00.80#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.20:11:00.80#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.20:11:00.80#ibcon#ireg 11 cls_cnt 2 2006.145.20:11:00.80#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:11:00.80#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:11:00.80#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:11:00.81#ibcon#[25=AT01-08\r\n] 2006.145.20:11:00.84#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:11:00.84#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:11:00.84#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.20:11:00.84#ibcon#ireg 7 cls_cnt 0 2006.145.20:11:00.84#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:11:00.96#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:11:00.96#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:11:00.98#ibcon#[25=USB\r\n] 2006.145.20:11:01.03#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:11:01.03#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:11:01.03#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.20:11:01.03#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.20:11:01.03$vck44/valo=2,534.99 2006.145.20:11:01.04#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.20:11:01.04#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.20:11:01.04#ibcon#ireg 17 cls_cnt 0 2006.145.20:11:01.04#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:11:01.04#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:11:01.04#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:11:01.05#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.20:11:01.09#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:11:01.09#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:11:01.09#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.20:11:01.09#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.20:11:01.10$vck44/va=2,7 2006.145.20:11:01.10#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.20:11:01.10#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.20:11:01.10#ibcon#ireg 11 cls_cnt 2 2006.145.20:11:01.10#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:11:01.15#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:11:01.15#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:11:01.17#ibcon#[25=AT02-07\r\n] 2006.145.20:11:01.19#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:11:01.19#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:11:01.19#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.20:11:01.19#ibcon#ireg 7 cls_cnt 0 2006.145.20:11:01.19#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:11:01.31#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:11:01.31#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:11:01.33#ibcon#[25=USB\r\n] 2006.145.20:11:01.36#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:11:01.36#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:11:01.36#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.20:11:01.36#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.20:11:01.37$vck44/valo=3,564.99 2006.145.20:11:01.37#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.20:11:01.37#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.20:11:01.37#ibcon#ireg 17 cls_cnt 0 2006.145.20:11:01.37#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.20:11:01.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.20:11:01.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.20:11:01.38#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.20:11:01.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.20:11:01.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.20:11:01.42#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.20:11:01.42#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.20:11:01.43$vck44/va=3,8 2006.145.20:11:01.43#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.20:11:01.43#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.20:11:01.43#ibcon#ireg 11 cls_cnt 2 2006.145.20:11:01.43#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.20:11:01.47#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.20:11:01.47#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.20:11:01.49#ibcon#[25=AT03-08\r\n] 2006.145.20:11:01.52#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.20:11:01.52#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.20:11:01.52#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.20:11:01.52#ibcon#ireg 7 cls_cnt 0 2006.145.20:11:01.52#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.20:11:01.64#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.20:11:01.64#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.20:11:01.66#ibcon#[25=USB\r\n] 2006.145.20:11:01.69#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.20:11:01.69#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.20:11:01.69#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.20:11:01.69#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.20:11:01.70$vck44/valo=4,624.99 2006.145.20:11:01.70#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.20:11:01.70#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.20:11:01.70#ibcon#ireg 17 cls_cnt 0 2006.145.20:11:01.70#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.20:11:01.70#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.20:11:01.70#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.20:11:01.71#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.20:11:01.75#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.20:11:01.75#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.20:11:01.75#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.20:11:01.75#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.20:11:01.76$vck44/va=4,7 2006.145.20:11:01.76#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.20:11:01.76#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.20:11:01.76#ibcon#ireg 11 cls_cnt 2 2006.145.20:11:01.76#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.20:11:01.80#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.20:11:01.80#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.20:11:01.82#ibcon#[25=AT04-07\r\n] 2006.145.20:11:01.85#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.20:11:01.85#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.20:11:01.85#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.20:11:01.85#ibcon#ireg 7 cls_cnt 0 2006.145.20:11:01.85#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.20:11:01.97#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.20:11:01.97#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.20:11:01.99#ibcon#[25=USB\r\n] 2006.145.20:11:02.02#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.20:11:02.02#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.20:11:02.02#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.20:11:02.02#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.20:11:02.03$vck44/valo=5,734.99 2006.145.20:11:02.03#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.20:11:02.03#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.20:11:02.03#ibcon#ireg 17 cls_cnt 0 2006.145.20:11:02.03#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:11:02.03#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:11:02.03#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:11:02.04#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.20:11:02.09#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:11:02.09#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:11:02.09#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.20:11:02.09#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.20:11:02.09$vck44/va=5,4 2006.145.20:11:02.09#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.20:11:02.09#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.20:11:02.09#ibcon#ireg 11 cls_cnt 2 2006.145.20:11:02.09#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:11:02.13#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:11:02.13#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:11:02.16#ibcon#[25=AT05-04\r\n] 2006.145.20:11:02.18#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:11:02.18#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:11:02.18#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.20:11:02.18#ibcon#ireg 7 cls_cnt 0 2006.145.20:11:02.18#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:11:02.30#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:11:02.30#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:11:02.32#ibcon#[25=USB\r\n] 2006.145.20:11:02.35#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:11:02.35#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:11:02.35#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.20:11:02.35#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.20:11:02.36$vck44/valo=6,814.99 2006.145.20:11:02.36#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.20:11:02.36#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.20:11:02.36#ibcon#ireg 17 cls_cnt 0 2006.145.20:11:02.36#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:11:02.36#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:11:02.36#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:11:02.37#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.20:11:02.41#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:11:02.41#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:11:02.41#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.20:11:02.41#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.20:11:02.42$vck44/va=6,4 2006.145.20:11:02.42#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.20:11:02.42#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.20:11:02.42#ibcon#ireg 11 cls_cnt 2 2006.145.20:11:02.42#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:11:02.46#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:11:02.46#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:11:02.48#ibcon#[25=AT06-04\r\n] 2006.145.20:11:02.51#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:11:02.51#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:11:02.51#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.20:11:02.51#ibcon#ireg 7 cls_cnt 0 2006.145.20:11:02.51#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:11:02.63#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:11:02.63#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:11:02.65#ibcon#[25=USB\r\n] 2006.145.20:11:02.68#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:11:02.68#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:11:02.68#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.20:11:02.68#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.20:11:02.69$vck44/valo=7,864.99 2006.145.20:11:02.69#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.20:11:02.69#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.20:11:02.69#ibcon#ireg 17 cls_cnt 0 2006.145.20:11:02.69#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:11:02.69#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:11:02.69#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:11:02.70#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.20:11:02.74#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:11:02.74#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:11:02.74#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.20:11:02.74#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.20:11:02.75$vck44/va=7,4 2006.145.20:11:02.75#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.20:11:02.75#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.20:11:02.75#ibcon#ireg 11 cls_cnt 2 2006.145.20:11:02.75#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.20:11:02.79#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.20:11:02.79#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.20:11:02.81#ibcon#[25=AT07-04\r\n] 2006.145.20:11:02.84#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.20:11:02.84#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.20:11:02.84#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.20:11:02.84#ibcon#ireg 7 cls_cnt 0 2006.145.20:11:02.84#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.20:11:02.96#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.20:11:02.96#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.20:11:02.98#ibcon#[25=USB\r\n] 2006.145.20:11:03.02#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.20:11:03.02#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.20:11:03.02#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.20:11:03.02#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.20:11:03.02$vck44/valo=8,884.99 2006.145.20:11:03.02#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.20:11:03.02#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.20:11:03.02#ibcon#ireg 17 cls_cnt 0 2006.145.20:11:03.02#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.20:11:03.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.20:11:03.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.20:11:03.03#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.20:11:03.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.20:11:03.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.20:11:03.07#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.20:11:03.07#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.20:11:03.08$vck44/va=8,4 2006.145.20:11:03.08#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.20:11:03.08#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.20:11:03.08#ibcon#ireg 11 cls_cnt 2 2006.145.20:11:03.08#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.20:11:03.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.20:11:03.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.20:11:03.15#ibcon#[25=AT08-04\r\n] 2006.145.20:11:03.18#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.20:11:03.18#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.20:11:03.18#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.20:11:03.18#ibcon#ireg 7 cls_cnt 0 2006.145.20:11:03.18#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.20:11:03.30#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.20:11:03.30#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.20:11:03.32#ibcon#[25=USB\r\n] 2006.145.20:11:03.38#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.20:11:03.38#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.20:11:03.38#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.20:11:03.38#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.20:11:03.38$vck44/vblo=1,629.99 2006.145.20:11:03.38#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.20:11:03.38#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.20:11:03.38#ibcon#ireg 17 cls_cnt 0 2006.145.20:11:03.38#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:11:03.38#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:11:03.38#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:11:03.39#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.20:11:03.43#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:11:03.43#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:11:03.43#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.20:11:03.43#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.20:11:03.44$vck44/vb=1,3 2006.145.20:11:03.44#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.20:11:03.44#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.20:11:03.44#ibcon#ireg 11 cls_cnt 2 2006.145.20:11:03.44#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.20:11:03.44#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.20:11:03.44#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.20:11:03.45#ibcon#[27=AT01-03\r\n] 2006.145.20:11:03.49#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.20:11:03.49#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.20:11:03.49#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.20:11:03.49#ibcon#ireg 7 cls_cnt 0 2006.145.20:11:03.49#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.20:11:03.60#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.20:11:03.60#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.20:11:03.62#ibcon#[27=USB\r\n] 2006.145.20:11:03.65#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.20:11:03.65#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.20:11:03.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.20:11:03.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.20:11:03.66$vck44/vblo=2,634.99 2006.145.20:11:03.66#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.20:11:03.66#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.20:11:03.66#ibcon#ireg 17 cls_cnt 0 2006.145.20:11:03.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:11:03.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:11:03.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:11:03.67#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.20:11:03.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:11:03.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:11:03.71#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.20:11:03.71#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.20:11:03.72$vck44/vb=2,4 2006.145.20:11:03.72#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.20:11:03.72#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.20:11:03.72#ibcon#ireg 11 cls_cnt 2 2006.145.20:11:03.72#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:11:03.76#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:11:03.76#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:11:03.78#ibcon#[27=AT02-04\r\n] 2006.145.20:11:03.81#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:11:03.81#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:11:03.81#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.20:11:03.81#ibcon#ireg 7 cls_cnt 0 2006.145.20:11:03.81#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:11:03.93#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:11:03.93#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:11:03.95#ibcon#[27=USB\r\n] 2006.145.20:11:03.98#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:11:03.98#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:11:03.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.20:11:03.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.20:11:03.99$vck44/vblo=3,649.99 2006.145.20:11:03.99#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.20:11:03.99#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.20:11:03.99#ibcon#ireg 17 cls_cnt 0 2006.145.20:11:03.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:11:03.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:11:03.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:11:04.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.20:11:04.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:11:04.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:11:04.04#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.20:11:04.04#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.20:11:04.05$vck44/vb=3,4 2006.145.20:11:04.05#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.20:11:04.05#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.20:11:04.05#ibcon#ireg 11 cls_cnt 2 2006.145.20:11:04.05#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:11:04.09#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:11:04.09#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:11:04.11#ibcon#[27=AT03-04\r\n] 2006.145.20:11:04.15#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:11:04.15#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:11:04.15#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.20:11:04.15#ibcon#ireg 7 cls_cnt 0 2006.145.20:11:04.15#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:11:04.26#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:11:04.26#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:11:04.28#ibcon#[27=USB\r\n] 2006.145.20:11:04.31#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:11:04.31#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:11:04.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.20:11:04.32#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.20:11:04.32$vck44/vblo=4,679.99 2006.145.20:11:04.32#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.20:11:04.32#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.20:11:04.32#ibcon#ireg 17 cls_cnt 0 2006.145.20:11:04.32#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:11:04.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:11:04.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:11:04.33#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.20:11:04.36#abcon#<5=/08 1.3 3.0 15.94 881020.1\r\n> 2006.145.20:11:04.37#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:11:04.37#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:11:04.37#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.20:11:04.37#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.20:11:04.38$vck44/vb=4,4 2006.145.20:11:04.38#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.20:11:04.38#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.20:11:04.38#ibcon#ireg 11 cls_cnt 2 2006.145.20:11:04.38#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:11:04.38#abcon#{5=INTERFACE CLEAR} 2006.145.20:11:04.42#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:11:04.42#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:11:04.44#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:11:04.44#ibcon#[27=AT04-04\r\n] 2006.145.20:11:04.47#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:11:04.47#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:11:04.47#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.20:11:04.47#ibcon#ireg 7 cls_cnt 0 2006.145.20:11:04.47#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:11:04.59#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:11:04.59#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:11:04.61#ibcon#[27=USB\r\n] 2006.145.20:11:04.64#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:11:04.64#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:11:04.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.20:11:04.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.20:11:04.65$vck44/vblo=5,709.99 2006.145.20:11:04.65#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.20:11:04.65#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.20:11:04.65#ibcon#ireg 17 cls_cnt 0 2006.145.20:11:04.65#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:11:04.65#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:11:04.65#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:11:04.66#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.20:11:04.70#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:11:04.70#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:11:04.70#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.20:11:04.70#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.20:11:04.71$vck44/vb=5,4 2006.145.20:11:04.71#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.20:11:04.71#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.20:11:04.71#ibcon#ireg 11 cls_cnt 2 2006.145.20:11:04.71#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:11:04.75#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:11:04.75#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:11:04.77#ibcon#[27=AT05-04\r\n] 2006.145.20:11:04.80#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:11:04.80#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:11:04.80#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.20:11:04.80#ibcon#ireg 7 cls_cnt 0 2006.145.20:11:04.80#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:11:04.92#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:11:04.92#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:11:04.94#ibcon#[27=USB\r\n] 2006.145.20:11:04.97#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:11:04.97#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:11:04.97#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.20:11:04.97#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.20:11:04.98$vck44/vblo=6,719.99 2006.145.20:11:04.98#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.20:11:04.98#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.20:11:04.98#ibcon#ireg 17 cls_cnt 0 2006.145.20:11:04.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:11:04.98#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:11:04.98#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:11:04.99#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.20:11:05.03#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:11:05.03#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:11:05.03#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.20:11:05.03#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.20:11:05.04$vck44/vb=6,4 2006.145.20:11:05.04#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.20:11:05.04#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.20:11:05.04#ibcon#ireg 11 cls_cnt 2 2006.145.20:11:05.04#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:11:05.08#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:11:05.08#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:11:05.10#ibcon#[27=AT06-04\r\n] 2006.145.20:11:05.13#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:11:05.13#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:11:05.13#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.20:11:05.13#ibcon#ireg 7 cls_cnt 0 2006.145.20:11:05.13#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:11:05.25#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:11:05.25#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:11:05.27#ibcon#[27=USB\r\n] 2006.145.20:11:05.30#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:11:05.30#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:11:05.30#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.20:11:05.30#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.20:11:05.31$vck44/vblo=7,734.99 2006.145.20:11:05.31#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.20:11:05.31#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.20:11:05.31#ibcon#ireg 17 cls_cnt 0 2006.145.20:11:05.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:11:05.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:11:05.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:11:05.32#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.20:11:05.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:11:05.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:11:05.36#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.20:11:05.36#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.20:11:05.37$vck44/vb=7,4 2006.145.20:11:05.37#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.20:11:05.37#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.20:11:05.37#ibcon#ireg 11 cls_cnt 2 2006.145.20:11:05.37#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.20:11:05.41#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.20:11:05.41#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.20:11:05.43#ibcon#[27=AT07-04\r\n] 2006.145.20:11:05.46#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.20:11:05.46#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.20:11:05.46#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.20:11:05.46#ibcon#ireg 7 cls_cnt 0 2006.145.20:11:05.46#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.20:11:05.58#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.20:11:05.58#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.20:11:05.61#ibcon#[27=USB\r\n] 2006.145.20:11:05.63#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.20:11:05.63#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.20:11:05.63#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.20:11:05.63#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.20:11:05.64$vck44/vblo=8,744.99 2006.145.20:11:05.64#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.20:11:05.64#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.20:11:05.64#ibcon#ireg 17 cls_cnt 0 2006.145.20:11:05.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.20:11:05.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.20:11:05.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.20:11:05.65#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.20:11:05.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.20:11:05.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.20:11:05.69#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.20:11:05.69#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.20:11:05.70$vck44/vb=8,4 2006.145.20:11:05.70#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.20:11:05.70#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.20:11:05.70#ibcon#ireg 11 cls_cnt 2 2006.145.20:11:05.70#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.20:11:05.74#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.20:11:05.74#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.20:11:05.76#ibcon#[27=AT08-04\r\n] 2006.145.20:11:05.79#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.20:11:05.79#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.20:11:05.79#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.20:11:05.79#ibcon#ireg 7 cls_cnt 0 2006.145.20:11:05.79#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.20:11:05.91#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.20:11:05.91#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.20:11:05.93#ibcon#[27=USB\r\n] 2006.145.20:11:05.96#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.20:11:05.96#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.20:11:05.96#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.20:11:05.96#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.20:11:05.97$vck44/vabw=wide 2006.145.20:11:05.97#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.20:11:05.97#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.20:11:05.97#ibcon#ireg 8 cls_cnt 0 2006.145.20:11:05.97#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:11:05.97#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:11:05.97#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:11:05.98#ibcon#[25=BW32\r\n] 2006.145.20:11:06.02#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:11:06.02#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:11:06.02#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.20:11:06.02#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.20:11:06.02$vck44/vbbw=wide 2006.145.20:11:06.02#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.20:11:06.02#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.20:11:06.02#ibcon#ireg 8 cls_cnt 0 2006.145.20:11:06.02#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:11:06.07#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:11:06.07#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:11:06.09#ibcon#[27=BW32\r\n] 2006.145.20:11:06.12#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:11:06.12#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:11:06.12#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.20:11:06.12#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.20:11:06.13$setupk4/ifdk4 2006.145.20:11:06.13$ifdk4/lo= 2006.145.20:11:06.13$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.20:11:06.13$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.20:11:06.13$ifdk4/patch= 2006.145.20:11:06.13$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.20:11:06.13$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.20:11:06.13$setupk4/!*+20s 2006.145.20:11:14.53#abcon#<5=/08 1.3 3.0 15.94 881020.1\r\n> 2006.145.20:11:14.55#abcon#{5=INTERFACE CLEAR} 2006.145.20:11:14.61#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:11:20.72$setupk4/"tpicd 2006.145.20:11:20.72$setupk4/echo=off 2006.145.20:11:20.73$setupk4/xlog=off 2006.145.20:11:20.73:!2006.145.20:11:51 2006.145.20:11:24.14#trakl#Source acquired 2006.145.20:11:26.15#flagr#flagr/antenna,acquired 2006.145.20:11:51.02:preob 2006.145.20:11:52.15/onsource/TRACKING 2006.145.20:11:52.15:!2006.145.20:12:01 2006.145.20:12:01.02:"tape 2006.145.20:12:01.02:"st=record 2006.145.20:12:01.02:data_valid=on 2006.145.20:12:01.02:midob 2006.145.20:12:02.15/onsource/TRACKING 2006.145.20:12:02.15/wx/15.94,1020.2,88 2006.145.20:12:02.29/cable/+6.5508E-03 2006.145.20:12:03.38/va/01,08,usb,yes,28,30 2006.145.20:12:03.38/va/02,07,usb,yes,30,31 2006.145.20:12:03.38/va/03,08,usb,yes,27,28 2006.145.20:12:03.38/va/04,07,usb,yes,31,33 2006.145.20:12:03.38/va/05,04,usb,yes,27,27 2006.145.20:12:03.38/va/06,04,usb,yes,30,30 2006.145.20:12:03.38/va/07,04,usb,yes,31,32 2006.145.20:12:03.38/va/08,04,usb,yes,26,31 2006.145.20:12:03.61/valo/01,524.99,yes,locked 2006.145.20:12:03.61/valo/02,534.99,yes,locked 2006.145.20:12:03.61/valo/03,564.99,yes,locked 2006.145.20:12:03.61/valo/04,624.99,yes,locked 2006.145.20:12:03.61/valo/05,734.99,yes,locked 2006.145.20:12:03.61/valo/06,814.99,yes,locked 2006.145.20:12:03.61/valo/07,864.99,yes,locked 2006.145.20:12:03.61/valo/08,884.99,yes,locked 2006.145.20:12:04.70/vb/01,03,usb,yes,35,33 2006.145.20:12:04.70/vb/02,04,usb,yes,31,31 2006.145.20:12:04.70/vb/03,04,usb,yes,28,31 2006.145.20:12:04.70/vb/04,04,usb,yes,32,31 2006.145.20:12:04.70/vb/05,04,usb,yes,25,27 2006.145.20:12:04.70/vb/06,04,usb,yes,29,25 2006.145.20:12:04.70/vb/07,04,usb,yes,29,29 2006.145.20:12:04.70/vb/08,04,usb,yes,27,30 2006.145.20:12:04.94/vblo/01,629.99,yes,locked 2006.145.20:12:04.94/vblo/02,634.99,yes,locked 2006.145.20:12:04.94/vblo/03,649.99,yes,locked 2006.145.20:12:04.94/vblo/04,679.99,yes,locked 2006.145.20:12:04.94/vblo/05,709.99,yes,locked 2006.145.20:12:04.94/vblo/06,719.99,yes,locked 2006.145.20:12:04.94/vblo/07,734.99,yes,locked 2006.145.20:12:04.94/vblo/08,744.99,yes,locked 2006.145.20:12:05.09/vabw/8 2006.145.20:12:05.24/vbbw/8 2006.145.20:12:05.33/xfe/off,on,14.7 2006.145.20:12:05.76/ifatt/23,28,28,28 2006.145.20:12:06.06/fmout-gps/S +5.1E-08 2006.145.20:12:06.15:!2006.145.20:13:11 2006.145.20:13:11.01:data_valid=off 2006.145.20:13:11.02:"et 2006.145.20:13:11.02:!+3s 2006.145.20:13:14.05:"tape 2006.145.20:13:14.06:postob 2006.145.20:13:14.13/cable/+6.5528E-03 2006.145.20:13:14.14/wx/15.95,1020.1,88 2006.145.20:13:14.21/fmout-gps/S +5.1E-08 2006.145.20:13:14.21:scan_name=145-2017,jd0605,784 2006.145.20:13:14.21:source=1749+096,175132.82,093900.7,2000.0,cw 2006.145.20:13:15.14#flagr#flagr/antenna,new-source 2006.145.20:13:15.15:checkk5 2006.145.20:13:15.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.20:13:16.05/chk_autoobs//k5ts2/ autoobs is running! 2006.145.20:13:16.49/chk_autoobs//k5ts3/ autoobs is running! 2006.145.20:13:16.93/chk_autoobs//k5ts4/ autoobs is running! 2006.145.20:13:17.36/chk_obsdata//k5ts1/T1452012??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.20:13:17.80/chk_obsdata//k5ts2/T1452012??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.20:13:18.25/chk_obsdata//k5ts3/T1452012??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.20:13:18.69/chk_obsdata//k5ts4/T1452012??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.20:13:19.44/k5log//k5ts1_log_newline 2006.145.20:13:20.20/k5log//k5ts2_log_newline 2006.145.20:13:20.93/k5log//k5ts3_log_newline 2006.145.20:13:21.68/k5log//k5ts4_log_newline 2006.145.20:13:21.70/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.20:13:21.70:setupk4=1 2006.145.20:13:21.70$setupk4/echo=on 2006.145.20:13:21.70$setupk4/pcalon 2006.145.20:13:21.70$pcalon/"no phase cal control is implemented here 2006.145.20:13:21.70$setupk4/"tpicd=stop 2006.145.20:13:21.70$setupk4/"rec=synch_on 2006.145.20:13:21.70$setupk4/"rec_mode=128 2006.145.20:13:21.70$setupk4/!* 2006.145.20:13:21.70$setupk4/recpk4 2006.145.20:13:21.70$recpk4/recpatch= 2006.145.20:13:21.71$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.20:13:21.71$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.20:13:21.71$setupk4/vck44 2006.145.20:13:21.71$vck44/valo=1,524.99 2006.145.20:13:21.71#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.20:13:21.71#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.20:13:21.71#ibcon#ireg 17 cls_cnt 0 2006.145.20:13:21.71#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:13:21.71#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:13:21.71#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:13:21.74#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.20:13:21.79#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:13:21.79#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:13:21.79#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.20:13:21.79#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.20:13:21.79$vck44/va=1,8 2006.145.20:13:21.79#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.20:13:21.79#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.20:13:21.79#ibcon#ireg 11 cls_cnt 2 2006.145.20:13:21.79#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:13:21.79#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:13:21.79#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:13:21.81#ibcon#[25=AT01-08\r\n] 2006.145.20:13:21.84#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:13:21.84#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:13:21.84#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.20:13:21.84#ibcon#ireg 7 cls_cnt 0 2006.145.20:13:21.84#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:13:21.96#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:13:21.96#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:13:21.98#ibcon#[25=USB\r\n] 2006.145.20:13:22.03#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:13:22.03#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:13:22.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.20:13:22.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.20:13:22.03$vck44/valo=2,534.99 2006.145.20:13:22.03#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.20:13:22.03#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.20:13:22.03#ibcon#ireg 17 cls_cnt 0 2006.145.20:13:22.03#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:13:22.03#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:13:22.03#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:13:22.05#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.20:13:22.08#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:13:22.08#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:13:22.08#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.20:13:22.08#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.20:13:22.08$vck44/va=2,7 2006.145.20:13:22.08#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.20:13:22.08#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.20:13:22.08#ibcon#ireg 11 cls_cnt 2 2006.145.20:13:22.08#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:13:22.15#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:13:22.15#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:13:22.17#ibcon#[25=AT02-07\r\n] 2006.145.20:13:22.20#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:13:22.20#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:13:22.20#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.20:13:22.20#ibcon#ireg 7 cls_cnt 0 2006.145.20:13:22.20#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:13:22.32#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:13:22.32#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:13:22.34#ibcon#[25=USB\r\n] 2006.145.20:13:22.37#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:13:22.37#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:13:22.37#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.20:13:22.37#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.20:13:22.37$vck44/valo=3,564.99 2006.145.20:13:22.37#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.20:13:22.37#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.20:13:22.37#ibcon#ireg 17 cls_cnt 0 2006.145.20:13:22.37#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:13:22.37#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:13:22.37#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:13:22.39#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.20:13:22.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:13:22.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:13:22.43#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.20:13:22.43#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.20:13:22.43$vck44/va=3,8 2006.145.20:13:22.43#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.20:13:22.43#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.20:13:22.43#ibcon#ireg 11 cls_cnt 2 2006.145.20:13:22.43#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:13:22.49#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:13:22.49#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:13:22.51#ibcon#[25=AT03-08\r\n] 2006.145.20:13:22.54#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:13:22.54#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:13:22.54#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.20:13:22.54#ibcon#ireg 7 cls_cnt 0 2006.145.20:13:22.54#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:13:22.66#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:13:22.66#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:13:22.68#ibcon#[25=USB\r\n] 2006.145.20:13:22.71#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:13:22.71#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:13:22.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.20:13:22.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.20:13:22.71$vck44/valo=4,624.99 2006.145.20:13:22.71#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.20:13:22.71#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.20:13:22.71#ibcon#ireg 17 cls_cnt 0 2006.145.20:13:22.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:13:22.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:13:22.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:13:22.73#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.20:13:22.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:13:22.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:13:22.77#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.20:13:22.77#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.20:13:22.77$vck44/va=4,7 2006.145.20:13:22.77#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.20:13:22.77#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.20:13:22.77#ibcon#ireg 11 cls_cnt 2 2006.145.20:13:22.77#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:13:22.83#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:13:22.83#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:13:22.85#ibcon#[25=AT04-07\r\n] 2006.145.20:13:22.88#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:13:22.88#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:13:22.88#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.20:13:22.88#ibcon#ireg 7 cls_cnt 0 2006.145.20:13:22.88#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:13:23.00#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:13:23.00#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:13:23.02#ibcon#[25=USB\r\n] 2006.145.20:13:23.05#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:13:23.05#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:13:23.05#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.20:13:23.05#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.20:13:23.05$vck44/valo=5,734.99 2006.145.20:13:23.05#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.20:13:23.05#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.20:13:23.05#ibcon#ireg 17 cls_cnt 0 2006.145.20:13:23.05#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:13:23.05#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:13:23.05#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:13:23.07#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.20:13:23.13#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:13:23.13#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:13:23.13#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.20:13:23.13#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.20:13:23.13$vck44/va=5,4 2006.145.20:13:23.13#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.20:13:23.13#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.20:13:23.13#ibcon#ireg 11 cls_cnt 2 2006.145.20:13:23.13#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:13:23.16#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:13:23.16#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:13:23.18#ibcon#[25=AT05-04\r\n] 2006.145.20:13:23.21#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:13:23.21#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:13:23.21#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.20:13:23.21#ibcon#ireg 7 cls_cnt 0 2006.145.20:13:23.21#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:13:23.33#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:13:23.33#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:13:23.35#ibcon#[25=USB\r\n] 2006.145.20:13:23.38#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:13:23.38#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:13:23.38#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.20:13:23.38#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.20:13:23.38$vck44/valo=6,814.99 2006.145.20:13:23.38#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.20:13:23.38#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.20:13:23.38#ibcon#ireg 17 cls_cnt 0 2006.145.20:13:23.38#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:13:23.38#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:13:23.38#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:13:23.42#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.20:13:23.45#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:13:23.45#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:13:23.45#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.20:13:23.45#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.20:13:23.45$vck44/va=6,4 2006.145.20:13:23.45#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.20:13:23.45#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.20:13:23.45#ibcon#ireg 11 cls_cnt 2 2006.145.20:13:23.45#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:13:23.50#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:13:23.50#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:13:23.52#ibcon#[25=AT06-04\r\n] 2006.145.20:13:23.55#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:13:23.55#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:13:23.55#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.20:13:23.55#ibcon#ireg 7 cls_cnt 0 2006.145.20:13:23.55#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:13:23.67#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:13:23.67#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:13:23.69#ibcon#[25=USB\r\n] 2006.145.20:13:23.72#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:13:23.72#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:13:23.72#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.20:13:23.72#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.20:13:23.72$vck44/valo=7,864.99 2006.145.20:13:23.72#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.20:13:23.72#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.20:13:23.72#ibcon#ireg 17 cls_cnt 0 2006.145.20:13:23.72#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:13:23.72#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:13:23.72#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:13:23.74#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.20:13:23.78#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:13:23.78#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:13:23.78#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.20:13:23.78#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.20:13:23.78$vck44/va=7,4 2006.145.20:13:23.78#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.20:13:23.78#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.20:13:23.78#ibcon#ireg 11 cls_cnt 2 2006.145.20:13:23.78#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:13:23.84#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:13:23.84#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:13:23.86#ibcon#[25=AT07-04\r\n] 2006.145.20:13:23.89#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:13:23.89#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:13:23.89#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.20:13:23.89#ibcon#ireg 7 cls_cnt 0 2006.145.20:13:23.89#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:13:24.01#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:13:24.01#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:13:24.03#ibcon#[25=USB\r\n] 2006.145.20:13:24.06#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:13:24.06#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:13:24.06#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.20:13:24.06#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.20:13:24.06$vck44/valo=8,884.99 2006.145.20:13:24.06#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.20:13:24.06#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.20:13:24.06#ibcon#ireg 17 cls_cnt 0 2006.145.20:13:24.06#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:13:24.06#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:13:24.06#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:13:24.08#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.20:13:24.12#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:13:24.12#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:13:24.12#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.20:13:24.12#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.20:13:24.12$vck44/va=8,4 2006.145.20:13:24.12#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.20:13:24.12#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.20:13:24.12#ibcon#ireg 11 cls_cnt 2 2006.145.20:13:24.12#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:13:24.18#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:13:24.18#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:13:24.20#ibcon#[25=AT08-04\r\n] 2006.145.20:13:24.23#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:13:24.23#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:13:24.23#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.20:13:24.23#ibcon#ireg 7 cls_cnt 0 2006.145.20:13:24.23#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:13:24.35#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:13:24.35#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:13:24.37#ibcon#[25=USB\r\n] 2006.145.20:13:24.40#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:13:24.40#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:13:24.40#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.20:13:24.40#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.20:13:24.40$vck44/vblo=1,629.99 2006.145.20:13:24.40#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.20:13:24.40#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.20:13:24.40#ibcon#ireg 17 cls_cnt 0 2006.145.20:13:24.40#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.20:13:24.40#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.20:13:24.40#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.20:13:24.42#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.20:13:24.46#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.20:13:24.46#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.20:13:24.46#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.20:13:24.46#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.20:13:24.46$vck44/vb=1,3 2006.145.20:13:24.46#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.20:13:24.46#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.20:13:24.46#ibcon#ireg 11 cls_cnt 2 2006.145.20:13:24.46#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.20:13:24.46#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.20:13:24.46#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.20:13:24.49#ibcon#[27=AT01-03\r\n] 2006.145.20:13:24.52#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.20:13:24.52#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.20:13:24.52#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.20:13:24.52#ibcon#ireg 7 cls_cnt 0 2006.145.20:13:24.52#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.20:13:24.64#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.20:13:24.64#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.20:13:24.66#ibcon#[27=USB\r\n] 2006.145.20:13:24.69#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.20:13:24.69#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.20:13:24.69#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.20:13:24.69#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.20:13:24.69$vck44/vblo=2,634.99 2006.145.20:13:24.69#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.20:13:24.69#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.20:13:24.69#ibcon#ireg 17 cls_cnt 0 2006.145.20:13:24.69#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:13:24.69#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:13:24.69#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:13:24.71#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.20:13:24.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:13:24.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:13:24.75#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.20:13:24.75#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.20:13:24.75$vck44/vb=2,4 2006.145.20:13:24.75#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.20:13:24.75#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.20:13:24.75#ibcon#ireg 11 cls_cnt 2 2006.145.20:13:24.75#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:13:24.81#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:13:24.81#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:13:24.83#ibcon#[27=AT02-04\r\n] 2006.145.20:13:24.86#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:13:24.86#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:13:24.86#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.20:13:24.86#ibcon#ireg 7 cls_cnt 0 2006.145.20:13:24.86#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:13:24.98#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:13:24.98#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:13:25.00#ibcon#[27=USB\r\n] 2006.145.20:13:25.03#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:13:25.03#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:13:25.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.20:13:25.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.20:13:25.03$vck44/vblo=3,649.99 2006.145.20:13:25.03#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.20:13:25.03#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.20:13:25.03#ibcon#ireg 17 cls_cnt 0 2006.145.20:13:25.03#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:13:25.03#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:13:25.03#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:13:25.05#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.20:13:25.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:13:25.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:13:25.09#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.20:13:25.09#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.20:13:25.09$vck44/vb=3,4 2006.145.20:13:25.09#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.20:13:25.09#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.20:13:25.09#ibcon#ireg 11 cls_cnt 2 2006.145.20:13:25.09#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:13:25.15#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:13:25.15#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:13:25.17#ibcon#[27=AT03-04\r\n] 2006.145.20:13:25.20#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:13:25.20#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:13:25.20#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.20:13:25.20#ibcon#ireg 7 cls_cnt 0 2006.145.20:13:25.20#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:13:25.32#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:13:25.32#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:13:25.34#ibcon#[27=USB\r\n] 2006.145.20:13:25.37#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:13:25.37#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:13:25.37#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.20:13:25.37#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.20:13:25.37$vck44/vblo=4,679.99 2006.145.20:13:25.37#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.20:13:25.37#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.20:13:25.37#ibcon#ireg 17 cls_cnt 0 2006.145.20:13:25.37#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:13:25.37#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:13:25.37#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:13:25.39#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.20:13:25.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:13:25.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:13:25.43#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.20:13:25.43#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.20:13:25.43$vck44/vb=4,4 2006.145.20:13:25.43#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.20:13:25.43#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.20:13:25.43#ibcon#ireg 11 cls_cnt 2 2006.145.20:13:25.43#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:13:25.49#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:13:25.49#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:13:25.51#ibcon#[27=AT04-04\r\n] 2006.145.20:13:25.54#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:13:25.54#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:13:25.54#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.20:13:25.54#ibcon#ireg 7 cls_cnt 0 2006.145.20:13:25.54#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:13:25.66#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:13:25.66#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:13:25.68#ibcon#[27=USB\r\n] 2006.145.20:13:25.71#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:13:25.71#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:13:25.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.20:13:25.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.20:13:25.71$vck44/vblo=5,709.99 2006.145.20:13:25.71#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.20:13:25.71#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.20:13:25.71#ibcon#ireg 17 cls_cnt 0 2006.145.20:13:25.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:13:25.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:13:25.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:13:25.73#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.20:13:25.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:13:25.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:13:25.77#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.20:13:25.77#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.20:13:25.77$vck44/vb=5,4 2006.145.20:13:25.77#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.20:13:25.77#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.20:13:25.77#ibcon#ireg 11 cls_cnt 2 2006.145.20:13:25.77#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:13:25.83#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:13:25.83#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:13:25.85#ibcon#[27=AT05-04\r\n] 2006.145.20:13:25.88#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:13:25.88#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:13:25.88#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.20:13:25.88#ibcon#ireg 7 cls_cnt 0 2006.145.20:13:25.88#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:13:26.00#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:13:26.00#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:13:26.02#ibcon#[27=USB\r\n] 2006.145.20:13:26.05#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:13:26.05#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:13:26.05#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.20:13:26.05#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.20:13:26.05$vck44/vblo=6,719.99 2006.145.20:13:26.05#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.20:13:26.05#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.20:13:26.05#ibcon#ireg 17 cls_cnt 0 2006.145.20:13:26.05#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:13:26.05#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:13:26.05#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:13:26.07#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.20:13:26.11#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:13:26.11#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:13:26.11#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.20:13:26.11#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.20:13:26.11$vck44/vb=6,4 2006.145.20:13:26.11#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.20:13:26.11#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.20:13:26.11#ibcon#ireg 11 cls_cnt 2 2006.145.20:13:26.11#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:13:26.17#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:13:26.17#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:13:26.19#ibcon#[27=AT06-04\r\n] 2006.145.20:13:26.22#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:13:26.22#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:13:26.22#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.20:13:26.22#ibcon#ireg 7 cls_cnt 0 2006.145.20:13:26.22#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:13:26.34#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:13:26.34#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:13:26.36#ibcon#[27=USB\r\n] 2006.145.20:13:26.39#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:13:26.39#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:13:26.39#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.20:13:26.39#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.20:13:26.39$vck44/vblo=7,734.99 2006.145.20:13:26.39#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.20:13:26.39#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.20:13:26.39#ibcon#ireg 17 cls_cnt 0 2006.145.20:13:26.39#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:13:26.39#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:13:26.39#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:13:26.41#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.20:13:26.45#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:13:26.45#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:13:26.45#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.20:13:26.45#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.20:13:26.45$vck44/vb=7,4 2006.145.20:13:26.45#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.20:13:26.45#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.20:13:26.45#ibcon#ireg 11 cls_cnt 2 2006.145.20:13:26.45#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:13:26.51#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:13:26.51#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:13:26.53#ibcon#[27=AT07-04\r\n] 2006.145.20:13:26.56#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:13:26.56#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:13:26.56#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.20:13:26.56#ibcon#ireg 7 cls_cnt 0 2006.145.20:13:26.56#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:13:26.68#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:13:26.68#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:13:26.70#ibcon#[27=USB\r\n] 2006.145.20:13:26.73#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:13:26.73#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:13:26.73#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.20:13:26.73#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.20:13:26.73$vck44/vblo=8,744.99 2006.145.20:13:26.73#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.20:13:26.73#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.20:13:26.73#ibcon#ireg 17 cls_cnt 0 2006.145.20:13:26.73#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:13:26.73#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:13:26.73#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:13:26.75#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.20:13:26.79#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:13:26.79#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:13:26.79#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.20:13:26.79#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.20:13:26.79$vck44/vb=8,4 2006.145.20:13:26.79#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.20:13:26.79#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.20:13:26.79#ibcon#ireg 11 cls_cnt 2 2006.145.20:13:26.79#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:13:26.85#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:13:26.85#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:13:26.87#ibcon#[27=AT08-04\r\n] 2006.145.20:13:26.90#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:13:26.90#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:13:26.90#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.20:13:26.90#ibcon#ireg 7 cls_cnt 0 2006.145.20:13:26.90#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:13:27.02#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:13:27.02#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:13:27.04#ibcon#[27=USB\r\n] 2006.145.20:13:27.07#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:13:27.07#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:13:27.07#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.20:13:27.07#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.20:13:27.07$vck44/vabw=wide 2006.145.20:13:27.07#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.20:13:27.07#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.20:13:27.07#ibcon#ireg 8 cls_cnt 0 2006.145.20:13:27.07#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:13:27.07#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:13:27.07#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:13:27.09#ibcon#[25=BW32\r\n] 2006.145.20:13:27.12#abcon#<5=/08 1.3 3.0 15.95 881020.1\r\n> 2006.145.20:13:27.12#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:13:27.12#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:13:27.12#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.20:13:27.12#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.20:13:27.12$vck44/vbbw=wide 2006.145.20:13:27.12#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.20:13:27.12#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.20:13:27.12#ibcon#ireg 8 cls_cnt 0 2006.145.20:13:27.12#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:13:27.14#abcon#{5=INTERFACE CLEAR} 2006.145.20:13:27.19#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:13:27.19#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:13:27.20#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:13:27.21#ibcon#[27=BW32\r\n] 2006.145.20:13:27.24#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:13:27.24#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:13:27.24#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.20:13:27.24#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.20:13:27.24$setupk4/ifdk4 2006.145.20:13:27.24$ifdk4/lo= 2006.145.20:13:27.24$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.20:13:27.25$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.20:13:27.25$ifdk4/patch= 2006.145.20:13:27.25$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.20:13:27.25$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.20:13:27.25$setupk4/!*+20s 2006.145.20:13:37.29#abcon#<5=/08 1.2 3.0 15.95 881020.1\r\n> 2006.145.20:13:37.31#abcon#{5=INTERFACE CLEAR} 2006.145.20:13:37.37#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:13:41.72$setupk4/"tpicd 2006.145.20:13:41.72$setupk4/echo=off 2006.145.20:13:41.72$setupk4/xlog=off 2006.145.20:13:41.72:!2006.145.20:16:54 2006.145.20:13:47.14#trakl#Source acquired 2006.145.20:13:47.14#flagr#flagr/antenna,acquired 2006.145.20:16:54.00:preob 2006.145.20:16:54.14/onsource/TRACKING 2006.145.20:16:54.14:!2006.145.20:17:04 2006.145.20:17:04.00:"tape 2006.145.20:17:04.00:"st=record 2006.145.20:17:04.00:data_valid=on 2006.145.20:17:04.00:midob 2006.145.20:17:05.14/onsource/TRACKING 2006.145.20:17:05.14/wx/15.98,1020.1,87 2006.145.20:17:05.24/cable/+6.5498E-03 2006.145.20:17:06.33/va/01,08,usb,yes,29,31 2006.145.20:17:06.33/va/02,07,usb,yes,31,32 2006.145.20:17:06.33/va/03,08,usb,yes,29,30 2006.145.20:17:06.33/va/04,07,usb,yes,32,34 2006.145.20:17:06.33/va/05,04,usb,yes,28,29 2006.145.20:17:06.33/va/06,04,usb,yes,32,32 2006.145.20:17:06.33/va/07,04,usb,yes,32,33 2006.145.20:17:06.33/va/08,04,usb,yes,27,33 2006.145.20:17:06.56/valo/01,524.99,yes,locked 2006.145.20:17:06.56/valo/02,534.99,yes,locked 2006.145.20:17:06.56/valo/03,564.99,yes,locked 2006.145.20:17:06.56/valo/04,624.99,yes,locked 2006.145.20:17:06.56/valo/05,734.99,yes,locked 2006.145.20:17:06.56/valo/06,814.99,yes,locked 2006.145.20:17:06.56/valo/07,864.99,yes,locked 2006.145.20:17:06.56/valo/08,884.99,yes,locked 2006.145.20:17:07.65/vb/01,03,usb,yes,36,33 2006.145.20:17:07.65/vb/02,04,usb,yes,31,31 2006.145.20:17:07.65/vb/03,04,usb,yes,28,31 2006.145.20:17:07.65/vb/04,04,usb,yes,33,32 2006.145.20:17:07.65/vb/05,04,usb,yes,25,28 2006.145.20:17:07.65/vb/06,04,usb,yes,30,26 2006.145.20:17:07.65/vb/07,04,usb,yes,29,29 2006.145.20:17:07.65/vb/08,04,usb,yes,27,30 2006.145.20:17:07.88/vblo/01,629.99,yes,locked 2006.145.20:17:07.88/vblo/02,634.99,yes,locked 2006.145.20:17:07.88/vblo/03,649.99,yes,locked 2006.145.20:17:07.88/vblo/04,679.99,yes,locked 2006.145.20:17:07.88/vblo/05,709.99,yes,locked 2006.145.20:17:07.88/vblo/06,719.99,yes,locked 2006.145.20:17:07.88/vblo/07,734.99,yes,locked 2006.145.20:17:07.88/vblo/08,744.99,yes,locked 2006.145.20:17:08.03/vabw/8 2006.145.20:17:08.18/vbbw/8 2006.145.20:17:08.27/xfe/off,on,14.7 2006.145.20:17:08.66/ifatt/23,28,28,28 2006.145.20:17:09.07/fmout-gps/S +5.1E-08 2006.145.20:17:09.12:!2006.145.20:30:08 2006.145.20:30:08.00:data_valid=off 2006.145.20:30:08.00:"et 2006.145.20:30:08.01:!+3s 2006.145.20:30:11.02:"tape 2006.145.20:30:11.02:postob 2006.145.20:30:11.13/cable/+6.5507E-03 2006.145.20:30:11.13/wx/16.08,1020.0,86 2006.145.20:30:11.21/fmout-gps/S +5.0E-08 2006.145.20:30:11.21:scan_name=145-2031,jd0605,120 2006.145.20:30:11.21:source=2201+315,220314.98,314538.3,2000.0,cw 2006.145.20:30:13.14#flagr#flagr/antenna,new-source 2006.145.20:30:13.14:checkk5 2006.145.20:30:13.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.20:30:14.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.20:30:14.48/chk_autoobs//k5ts3/ autoobs is running! 2006.145.20:30:14.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.20:30:15.63/chk_obsdata//k5ts1/T1452017??a.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.20:30:16.38/chk_obsdata//k5ts2/T1452017??b.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.20:30:17.14/chk_obsdata//k5ts3/T1452017??c.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.20:30:17.89/chk_obsdata//k5ts4/T1452017??d.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.20:30:18.65/k5log//k5ts1_log_newline 2006.145.20:30:19.40/k5log//k5ts2_log_newline 2006.145.20:30:20.15/k5log//k5ts3_log_newline 2006.145.20:30:20.88/k5log//k5ts4_log_newline 2006.145.20:30:20.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.20:30:20.90:setupk4=1 2006.145.20:30:20.90$setupk4/echo=on 2006.145.20:30:20.90$setupk4/pcalon 2006.145.20:30:20.90$pcalon/"no phase cal control is implemented here 2006.145.20:30:20.90$setupk4/"tpicd=stop 2006.145.20:30:20.90$setupk4/"rec=synch_on 2006.145.20:30:20.90$setupk4/"rec_mode=128 2006.145.20:30:20.90$setupk4/!* 2006.145.20:30:20.90$setupk4/recpk4 2006.145.20:30:20.90$recpk4/recpatch= 2006.145.20:30:20.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.20:30:20.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.20:30:20.90$setupk4/vck44 2006.145.20:30:20.90$vck44/valo=1,524.99 2006.145.20:30:20.90#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.20:30:20.90#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.20:30:20.90#ibcon#ireg 17 cls_cnt 0 2006.145.20:30:20.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:30:20.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:30:20.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:30:20.95#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.20:30:20.99#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:30:20.99#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:30:20.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.20:30:20.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.20:30:20.99$vck44/va=1,8 2006.145.20:30:20.99#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.20:30:20.99#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.20:30:20.99#ibcon#ireg 11 cls_cnt 2 2006.145.20:30:20.99#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:30:20.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:30:20.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:30:21.01#ibcon#[25=AT01-08\r\n] 2006.145.20:30:21.04#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:30:21.04#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:30:21.04#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.20:30:21.04#ibcon#ireg 7 cls_cnt 0 2006.145.20:30:21.04#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:30:21.16#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:30:21.16#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:30:21.18#ibcon#[25=USB\r\n] 2006.145.20:30:21.21#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:30:21.21#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:30:21.21#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.20:30:21.21#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.20:30:21.21$vck44/valo=2,534.99 2006.145.20:30:21.21#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.20:30:21.21#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.20:30:21.21#ibcon#ireg 17 cls_cnt 0 2006.145.20:30:21.21#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:30:21.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:30:21.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:30:21.23#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.20:30:21.27#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:30:21.27#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:30:21.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.20:30:21.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.20:30:21.27$vck44/va=2,7 2006.145.20:30:21.27#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.20:30:21.27#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.20:30:21.27#ibcon#ireg 11 cls_cnt 2 2006.145.20:30:21.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:30:21.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:30:21.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:30:21.35#ibcon#[25=AT02-07\r\n] 2006.145.20:30:21.38#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:30:21.38#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:30:21.38#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.20:30:21.38#ibcon#ireg 7 cls_cnt 0 2006.145.20:30:21.38#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:30:21.50#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:30:21.50#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:30:21.52#ibcon#[25=USB\r\n] 2006.145.20:30:21.55#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:30:21.55#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:30:21.55#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.20:30:21.55#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.20:30:21.55$vck44/valo=3,564.99 2006.145.20:30:21.55#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.20:30:21.55#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.20:30:21.55#ibcon#ireg 17 cls_cnt 0 2006.145.20:30:21.55#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.20:30:21.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.20:30:21.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.20:30:21.57#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.20:30:21.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.20:30:21.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.20:30:21.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.20:30:21.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.20:30:21.61$vck44/va=3,8 2006.145.20:30:21.61#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.20:30:21.61#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.20:30:21.61#ibcon#ireg 11 cls_cnt 2 2006.145.20:30:21.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.20:30:21.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.20:30:21.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.20:30:21.69#ibcon#[25=AT03-08\r\n] 2006.145.20:30:21.72#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.20:30:21.72#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.20:30:21.72#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.20:30:21.72#ibcon#ireg 7 cls_cnt 0 2006.145.20:30:21.72#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.20:30:21.84#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.20:30:21.84#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.20:30:21.86#ibcon#[25=USB\r\n] 2006.145.20:30:21.89#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.20:30:21.89#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.20:30:21.89#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.20:30:21.89#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.20:30:21.89$vck44/valo=4,624.99 2006.145.20:30:21.89#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.20:30:21.89#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.20:30:21.89#ibcon#ireg 17 cls_cnt 0 2006.145.20:30:21.89#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:30:21.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:30:21.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:30:21.91#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.20:30:21.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:30:21.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:30:21.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.20:30:21.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.20:30:21.95$vck44/va=4,7 2006.145.20:30:21.95#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.20:30:21.95#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.20:30:21.95#ibcon#ireg 11 cls_cnt 2 2006.145.20:30:21.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.20:30:22.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.20:30:22.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.20:30:22.03#ibcon#[25=AT04-07\r\n] 2006.145.20:30:22.06#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.20:30:22.06#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.20:30:22.06#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.20:30:22.06#ibcon#ireg 7 cls_cnt 0 2006.145.20:30:22.06#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.20:30:22.18#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.20:30:22.18#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.20:30:22.20#ibcon#[25=USB\r\n] 2006.145.20:30:22.24#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.20:30:22.24#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.20:30:22.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.20:30:22.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.20:30:22.24$vck44/valo=5,734.99 2006.145.20:30:22.24#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.20:30:22.24#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.20:30:22.24#ibcon#ireg 17 cls_cnt 0 2006.145.20:30:22.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.20:30:22.24#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.20:30:22.24#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.20:30:22.25#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.20:30:22.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.20:30:22.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.20:30:22.29#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.20:30:22.29#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.20:30:22.29$vck44/va=5,4 2006.145.20:30:22.29#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.20:30:22.29#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.20:30:22.29#ibcon#ireg 11 cls_cnt 2 2006.145.20:30:22.29#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.20:30:22.36#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.20:30:22.36#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.20:30:22.38#ibcon#[25=AT05-04\r\n] 2006.145.20:30:22.41#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.20:30:22.41#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.20:30:22.41#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.20:30:22.41#ibcon#ireg 7 cls_cnt 0 2006.145.20:30:22.41#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.20:30:22.53#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.20:30:22.53#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.20:30:22.55#ibcon#[25=USB\r\n] 2006.145.20:30:22.58#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.20:30:22.58#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.20:30:22.58#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.20:30:22.58#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.20:30:22.58$vck44/valo=6,814.99 2006.145.20:30:22.58#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.20:30:22.58#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.20:30:22.58#ibcon#ireg 17 cls_cnt 0 2006.145.20:30:22.58#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:30:22.58#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:30:22.58#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:30:22.60#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.20:30:22.64#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:30:22.64#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:30:22.64#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.20:30:22.64#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.20:30:22.64$vck44/va=6,4 2006.145.20:30:22.64#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.20:30:22.64#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.20:30:22.64#ibcon#ireg 11 cls_cnt 2 2006.145.20:30:22.64#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:30:22.70#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:30:22.70#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:30:22.72#ibcon#[25=AT06-04\r\n] 2006.145.20:30:22.75#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:30:22.75#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:30:22.75#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.20:30:22.75#ibcon#ireg 7 cls_cnt 0 2006.145.20:30:22.75#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:30:22.87#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:30:22.87#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:30:22.89#ibcon#[25=USB\r\n] 2006.145.20:30:22.92#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:30:22.92#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:30:22.92#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.20:30:22.92#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.20:30:22.92$vck44/valo=7,864.99 2006.145.20:30:22.92#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.20:30:22.92#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.20:30:22.92#ibcon#ireg 17 cls_cnt 0 2006.145.20:30:22.92#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:30:22.92#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:30:22.92#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:30:22.94#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.20:30:22.98#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:30:22.98#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:30:22.98#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.20:30:22.98#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.20:30:22.98$vck44/va=7,4 2006.145.20:30:22.98#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.20:30:22.98#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.20:30:22.98#ibcon#ireg 11 cls_cnt 2 2006.145.20:30:22.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:30:23.04#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:30:23.04#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:30:23.06#ibcon#[25=AT07-04\r\n] 2006.145.20:30:23.09#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:30:23.09#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:30:23.09#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.20:30:23.09#ibcon#ireg 7 cls_cnt 0 2006.145.20:30:23.09#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:30:23.21#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:30:23.21#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:30:23.23#ibcon#[25=USB\r\n] 2006.145.20:30:23.26#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:30:23.26#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:30:23.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.20:30:23.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.20:30:23.26$vck44/valo=8,884.99 2006.145.20:30:23.26#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.20:30:23.26#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.20:30:23.26#ibcon#ireg 17 cls_cnt 0 2006.145.20:30:23.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:30:23.26#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:30:23.26#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:30:23.28#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.20:30:23.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:30:23.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:30:23.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.20:30:23.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.20:30:23.32$vck44/va=8,4 2006.145.20:30:23.32#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.20:30:23.32#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.20:30:23.32#ibcon#ireg 11 cls_cnt 2 2006.145.20:30:23.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.20:30:23.38#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.20:30:23.38#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.20:30:23.40#ibcon#[25=AT08-04\r\n] 2006.145.20:30:23.43#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.20:30:23.43#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.20:30:23.43#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.20:30:23.43#ibcon#ireg 7 cls_cnt 0 2006.145.20:30:23.43#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.20:30:23.57#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.20:30:23.57#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.20:30:23.58#ibcon#[25=USB\r\n] 2006.145.20:30:23.61#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.20:30:23.61#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.20:30:23.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.20:30:23.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.20:30:23.61$vck44/vblo=1,629.99 2006.145.20:30:23.61#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.20:30:23.61#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.20:30:23.61#ibcon#ireg 17 cls_cnt 0 2006.145.20:30:23.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:30:23.61#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:30:23.61#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:30:23.63#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.20:30:23.67#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:30:23.67#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:30:23.67#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.20:30:23.67#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.20:30:23.67$vck44/vb=1,3 2006.145.20:30:23.67#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.20:30:23.67#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.20:30:23.67#ibcon#ireg 11 cls_cnt 2 2006.145.20:30:23.67#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.20:30:23.67#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.20:30:23.67#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.20:30:23.69#ibcon#[27=AT01-03\r\n] 2006.145.20:30:23.72#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.20:30:23.72#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.20:30:23.72#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.20:30:23.72#ibcon#ireg 7 cls_cnt 0 2006.145.20:30:23.72#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.20:30:23.84#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.20:30:23.84#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.20:30:23.86#ibcon#[27=USB\r\n] 2006.145.20:30:23.89#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.20:30:23.89#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.20:30:23.89#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.20:30:23.89#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.20:30:23.89$vck44/vblo=2,634.99 2006.145.20:30:23.89#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.20:30:23.89#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.20:30:23.89#ibcon#ireg 17 cls_cnt 0 2006.145.20:30:23.89#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:30:23.89#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:30:23.89#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:30:23.91#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.20:30:23.95#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:30:23.95#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:30:23.95#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.20:30:23.95#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.20:30:23.95$vck44/vb=2,4 2006.145.20:30:23.95#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.20:30:23.95#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.20:30:23.95#ibcon#ireg 11 cls_cnt 2 2006.145.20:30:23.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:30:24.01#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:30:24.01#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:30:24.03#ibcon#[27=AT02-04\r\n] 2006.145.20:30:24.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:30:24.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:30:24.06#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.20:30:24.06#ibcon#ireg 7 cls_cnt 0 2006.145.20:30:24.06#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:30:24.18#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:30:24.18#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:30:24.20#ibcon#[27=USB\r\n] 2006.145.20:30:24.23#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:30:24.23#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:30:24.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.20:30:24.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.20:30:24.23$vck44/vblo=3,649.99 2006.145.20:30:24.23#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.20:30:24.23#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.20:30:24.23#ibcon#ireg 17 cls_cnt 0 2006.145.20:30:24.23#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:30:24.23#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:30:24.23#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:30:24.25#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.20:30:24.29#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:30:24.29#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:30:24.29#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.20:30:24.29#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.20:30:24.29$vck44/vb=3,4 2006.145.20:30:24.29#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.20:30:24.29#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.20:30:24.29#ibcon#ireg 11 cls_cnt 2 2006.145.20:30:24.29#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:30:24.35#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:30:24.35#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:30:24.36#abcon#<5=/07 1.5 3.5 16.08 871020.0\r\n> 2006.145.20:30:24.37#ibcon#[27=AT03-04\r\n] 2006.145.20:30:24.38#abcon#{5=INTERFACE CLEAR} 2006.145.20:30:24.40#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:30:24.40#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:30:24.40#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.20:30:24.40#ibcon#ireg 7 cls_cnt 0 2006.145.20:30:24.40#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:30:24.44#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:30:24.52#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:30:24.52#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:30:24.54#ibcon#[27=USB\r\n] 2006.145.20:30:24.57#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:30:24.57#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:30:24.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.20:30:24.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.20:30:24.57$vck44/vblo=4,679.99 2006.145.20:30:24.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.20:30:24.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.20:30:24.57#ibcon#ireg 17 cls_cnt 0 2006.145.20:30:24.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:30:24.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:30:24.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:30:24.59#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.20:30:24.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:30:24.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:30:24.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.20:30:24.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.20:30:24.63$vck44/vb=4,4 2006.145.20:30:24.63#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.20:30:24.63#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.20:30:24.63#ibcon#ireg 11 cls_cnt 2 2006.145.20:30:24.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.20:30:24.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.20:30:24.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.20:30:24.71#ibcon#[27=AT04-04\r\n] 2006.145.20:30:24.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.20:30:24.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.20:30:24.74#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.20:30:24.74#ibcon#ireg 7 cls_cnt 0 2006.145.20:30:24.74#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.20:30:24.86#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.20:30:24.86#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.20:30:24.88#ibcon#[27=USB\r\n] 2006.145.20:30:24.91#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.20:30:24.91#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.20:30:24.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.20:30:24.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.20:30:24.91$vck44/vblo=5,709.99 2006.145.20:30:24.91#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.20:30:24.91#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.20:30:24.91#ibcon#ireg 17 cls_cnt 0 2006.145.20:30:24.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.20:30:24.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.20:30:24.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.20:30:24.93#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.20:30:24.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.20:30:24.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.20:30:24.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.20:30:24.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.20:30:24.97$vck44/vb=5,4 2006.145.20:30:24.97#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.20:30:24.97#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.20:30:24.97#ibcon#ireg 11 cls_cnt 2 2006.145.20:30:24.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.20:30:25.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.20:30:25.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.20:30:25.05#ibcon#[27=AT05-04\r\n] 2006.145.20:30:25.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.20:30:25.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.20:30:25.08#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.20:30:25.08#ibcon#ireg 7 cls_cnt 0 2006.145.20:30:25.08#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.20:30:25.20#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.20:30:25.20#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.20:30:25.22#ibcon#[27=USB\r\n] 2006.145.20:30:25.25#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.20:30:25.25#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.20:30:25.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.20:30:25.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.20:30:25.25$vck44/vblo=6,719.99 2006.145.20:30:25.25#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.20:30:25.25#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.20:30:25.25#ibcon#ireg 17 cls_cnt 0 2006.145.20:30:25.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:30:25.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:30:25.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:30:25.27#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.20:30:25.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:30:25.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:30:25.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.20:30:25.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.20:30:25.31$vck44/vb=6,4 2006.145.20:30:25.31#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.20:30:25.31#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.20:30:25.31#ibcon#ireg 11 cls_cnt 2 2006.145.20:30:25.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:30:25.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:30:25.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:30:25.39#ibcon#[27=AT06-04\r\n] 2006.145.20:30:25.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:30:25.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:30:25.42#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.20:30:25.42#ibcon#ireg 7 cls_cnt 0 2006.145.20:30:25.42#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:30:25.54#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:30:25.54#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:30:25.56#ibcon#[27=USB\r\n] 2006.145.20:30:25.59#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:30:25.59#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:30:25.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.20:30:25.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.20:30:25.59$vck44/vblo=7,734.99 2006.145.20:30:25.59#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.20:30:25.59#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.20:30:25.59#ibcon#ireg 17 cls_cnt 0 2006.145.20:30:25.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:30:25.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:30:25.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:30:25.61#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.20:30:25.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:30:25.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:30:25.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.20:30:25.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.20:30:25.65$vck44/vb=7,4 2006.145.20:30:25.65#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.20:30:25.65#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.20:30:25.65#ibcon#ireg 11 cls_cnt 2 2006.145.20:30:25.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:30:25.71#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:30:25.71#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:30:25.73#ibcon#[27=AT07-04\r\n] 2006.145.20:30:25.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:30:25.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:30:25.76#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.20:30:25.76#ibcon#ireg 7 cls_cnt 0 2006.145.20:30:25.76#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:30:25.88#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:30:25.88#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:30:25.90#ibcon#[27=USB\r\n] 2006.145.20:30:25.93#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:30:25.93#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:30:25.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.20:30:25.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.20:30:25.93$vck44/vblo=8,744.99 2006.145.20:30:25.93#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.20:30:25.93#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.20:30:25.93#ibcon#ireg 17 cls_cnt 0 2006.145.20:30:25.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:30:25.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:30:25.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:30:25.95#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.20:30:25.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:30:25.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:30:25.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.20:30:25.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.20:30:25.99$vck44/vb=8,4 2006.145.20:30:25.99#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.20:30:25.99#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.20:30:25.99#ibcon#ireg 11 cls_cnt 2 2006.145.20:30:25.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.20:30:26.05#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.20:30:26.05#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.20:30:26.07#ibcon#[27=AT08-04\r\n] 2006.145.20:30:26.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.20:30:26.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.20:30:26.10#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.20:30:26.10#ibcon#ireg 7 cls_cnt 0 2006.145.20:30:26.10#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.20:30:26.22#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.20:30:26.22#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.20:30:26.24#ibcon#[27=USB\r\n] 2006.145.20:30:26.27#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.20:30:26.27#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.20:30:26.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.20:30:26.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.20:30:26.27$vck44/vabw=wide 2006.145.20:30:26.27#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.20:30:26.27#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.20:30:26.27#ibcon#ireg 8 cls_cnt 0 2006.145.20:30:26.27#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:30:26.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:30:26.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:30:26.29#ibcon#[25=BW32\r\n] 2006.145.20:30:26.32#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:30:26.32#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:30:26.32#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.20:30:26.32#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.20:30:26.32$vck44/vbbw=wide 2006.145.20:30:26.32#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.20:30:26.32#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.20:30:26.32#ibcon#ireg 8 cls_cnt 0 2006.145.20:30:26.32#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:30:26.39#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:30:26.39#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:30:26.41#ibcon#[27=BW32\r\n] 2006.145.20:30:26.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:30:26.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:30:26.44#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.20:30:26.44#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.20:30:26.44$setupk4/ifdk4 2006.145.20:30:26.44$ifdk4/lo= 2006.145.20:30:26.44$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.20:30:26.44$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.20:30:26.44$ifdk4/patch= 2006.145.20:30:26.44$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.20:30:26.44$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.20:30:26.44$setupk4/!*+20s 2006.145.20:30:34.53#abcon#<5=/07 1.5 3.5 16.08 871020.0\r\n> 2006.145.20:30:34.55#abcon#{5=INTERFACE CLEAR} 2006.145.20:30:34.61#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:30:40.91$setupk4/"tpicd 2006.145.20:30:40.91$setupk4/echo=off 2006.145.20:30:40.91$setupk4/xlog=off 2006.145.20:30:40.91:!2006.145.20:31:19 2006.145.20:30:47.14#trakl#Source acquired 2006.145.20:30:47.14#flagr#flagr/antenna,acquired 2006.145.20:31:19.00:preob 2006.145.20:31:19.13/onsource/TRACKING 2006.145.20:31:19.13:!2006.145.20:31:29 2006.145.20:31:29.00:"tape 2006.145.20:31:29.00:"st=record 2006.145.20:31:29.00:data_valid=on 2006.145.20:31:29.00:midob 2006.145.20:31:29.13/onsource/TRACKING 2006.145.20:31:29.13/wx/16.08,1020.0,87 2006.145.20:31:29.20/cable/+6.5512E-03 2006.145.20:31:30.29/va/01,08,usb,yes,28,30 2006.145.20:31:30.29/va/02,07,usb,yes,30,31 2006.145.20:31:30.29/va/03,08,usb,yes,27,28 2006.145.20:31:30.29/va/04,07,usb,yes,31,32 2006.145.20:31:30.29/va/05,04,usb,yes,27,27 2006.145.20:31:30.29/va/06,04,usb,yes,30,30 2006.145.20:31:30.29/va/07,04,usb,yes,30,32 2006.145.20:31:30.29/va/08,04,usb,yes,26,31 2006.145.20:31:30.52/valo/01,524.99,yes,locked 2006.145.20:31:30.52/valo/02,534.99,yes,locked 2006.145.20:31:30.52/valo/03,564.99,yes,locked 2006.145.20:31:30.52/valo/04,624.99,yes,locked 2006.145.20:31:30.52/valo/05,734.99,yes,locked 2006.145.20:31:30.52/valo/06,814.99,yes,locked 2006.145.20:31:30.52/valo/07,864.99,yes,locked 2006.145.20:31:30.52/valo/08,884.99,yes,locked 2006.145.20:31:31.61/vb/01,03,usb,yes,35,33 2006.145.20:31:31.61/vb/02,04,usb,yes,31,31 2006.145.20:31:31.61/vb/03,04,usb,yes,28,31 2006.145.20:31:31.61/vb/04,04,usb,yes,32,31 2006.145.20:31:31.61/vb/05,04,usb,yes,25,27 2006.145.20:31:31.61/vb/06,04,usb,yes,29,26 2006.145.20:31:31.61/vb/07,04,usb,yes,29,29 2006.145.20:31:31.61/vb/08,04,usb,yes,27,30 2006.145.20:31:31.84/vblo/01,629.99,yes,locked 2006.145.20:31:31.84/vblo/02,634.99,yes,locked 2006.145.20:31:31.84/vblo/03,649.99,yes,locked 2006.145.20:31:31.84/vblo/04,679.99,yes,locked 2006.145.20:31:31.84/vblo/05,709.99,yes,locked 2006.145.20:31:31.84/vblo/06,719.99,yes,locked 2006.145.20:31:31.84/vblo/07,734.99,yes,locked 2006.145.20:31:31.84/vblo/08,744.99,yes,locked 2006.145.20:31:31.99/vabw/8 2006.145.20:31:32.14/vbbw/8 2006.145.20:31:32.23/xfe/off,on,14.2 2006.145.20:31:32.60/ifatt/23,28,28,28 2006.145.20:31:33.07/fmout-gps/S +4.8E-08 2006.145.20:31:33.11:!2006.145.20:33:29 2006.145.20:33:29.01:data_valid=off 2006.145.20:33:29.01:"et 2006.145.20:33:29.02:!+3s 2006.145.20:33:32.03:"tape 2006.145.20:33:32.03:postob 2006.145.20:33:32.25/cable/+6.5490E-03 2006.145.20:33:32.25/wx/16.09,1020.0,87 2006.145.20:33:32.34/fmout-gps/S +4.9E-08 2006.145.20:33:32.34:scan_name=145-2036,jd0605,130 2006.145.20:33:32.34:source=0552+398,055530.81,394849.2,2000.0,cw 2006.145.20:33:33.13#flagr#flagr/antenna,new-source 2006.145.20:33:33.14:checkk5 2006.145.20:33:33.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.20:33:34.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.20:33:34.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.20:33:34.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.20:33:35.32/chk_obsdata//k5ts1/T1452031??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.20:33:35.77/chk_obsdata//k5ts2/T1452031??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.20:33:36.21/chk_obsdata//k5ts3/T1452031??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.20:33:36.64/chk_obsdata//k5ts4/T1452031??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.20:33:37.39/k5log//k5ts1_log_newline 2006.145.20:33:38.13/k5log//k5ts2_log_newline 2006.145.20:33:38.87/k5log//k5ts3_log_newline 2006.145.20:33:39.62/k5log//k5ts4_log_newline 2006.145.20:33:39.64/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.20:33:39.64:setupk4=1 2006.145.20:33:39.64$setupk4/echo=on 2006.145.20:33:39.64$setupk4/pcalon 2006.145.20:33:39.64$pcalon/"no phase cal control is implemented here 2006.145.20:33:39.64$setupk4/"tpicd=stop 2006.145.20:33:39.64$setupk4/"rec=synch_on 2006.145.20:33:39.64$setupk4/"rec_mode=128 2006.145.20:33:39.64$setupk4/!* 2006.145.20:33:39.64$setupk4/recpk4 2006.145.20:33:39.64$recpk4/recpatch= 2006.145.20:33:39.64$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.20:33:39.64$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.20:33:39.64$setupk4/vck44 2006.145.20:33:39.64$vck44/valo=1,524.99 2006.145.20:33:39.64#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.20:33:39.64#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.20:33:39.64#ibcon#ireg 17 cls_cnt 0 2006.145.20:33:39.64#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:33:39.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:33:39.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:33:39.66#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.20:33:39.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:33:39.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:33:39.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.20:33:39.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.20:33:39.71$vck44/va=1,8 2006.145.20:33:39.71#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.20:33:39.71#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.20:33:39.71#ibcon#ireg 11 cls_cnt 2 2006.145.20:33:39.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:33:39.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:33:39.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:33:39.73#ibcon#[25=AT01-08\r\n] 2006.145.20:33:39.76#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:33:39.76#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:33:39.76#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.20:33:39.76#ibcon#ireg 7 cls_cnt 0 2006.145.20:33:39.76#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:33:39.88#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:33:39.88#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:33:39.90#ibcon#[25=USB\r\n] 2006.145.20:33:39.93#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:33:39.93#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:33:39.93#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.20:33:39.93#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.20:33:39.93$vck44/valo=2,534.99 2006.145.20:33:39.93#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.20:33:39.93#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.20:33:39.93#ibcon#ireg 17 cls_cnt 0 2006.145.20:33:39.93#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:33:39.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:33:39.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:33:39.96#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.20:33:40.00#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:33:40.00#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:33:40.00#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.20:33:40.00#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.20:33:40.00$vck44/va=2,7 2006.145.20:33:40.00#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.20:33:40.00#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.20:33:40.00#ibcon#ireg 11 cls_cnt 2 2006.145.20:33:40.00#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:33:40.05#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:33:40.05#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:33:40.07#ibcon#[25=AT02-07\r\n] 2006.145.20:33:40.10#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:33:40.10#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:33:40.10#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.20:33:40.10#ibcon#ireg 7 cls_cnt 0 2006.145.20:33:40.10#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:33:40.22#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:33:40.22#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:33:40.24#ibcon#[25=USB\r\n] 2006.145.20:33:40.27#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:33:40.27#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:33:40.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.20:33:40.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.20:33:40.27$vck44/valo=3,564.99 2006.145.20:33:40.27#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.20:33:40.27#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.20:33:40.27#ibcon#ireg 17 cls_cnt 0 2006.145.20:33:40.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:33:40.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:33:40.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:33:40.29#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.20:33:40.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:33:40.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:33:40.33#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.20:33:40.33#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.20:33:40.33$vck44/va=3,8 2006.145.20:33:40.33#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.20:33:40.33#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.20:33:40.33#ibcon#ireg 11 cls_cnt 2 2006.145.20:33:40.33#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:33:40.39#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:33:40.39#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:33:40.41#ibcon#[25=AT03-08\r\n] 2006.145.20:33:40.44#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:33:40.44#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:33:40.44#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.20:33:40.44#ibcon#ireg 7 cls_cnt 0 2006.145.20:33:40.44#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:33:40.56#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:33:40.56#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:33:40.58#ibcon#[25=USB\r\n] 2006.145.20:33:40.61#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:33:40.61#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:33:40.61#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.20:33:40.61#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.20:33:40.61$vck44/valo=4,624.99 2006.145.20:33:40.61#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.20:33:40.61#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.20:33:40.61#ibcon#ireg 17 cls_cnt 0 2006.145.20:33:40.61#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:33:40.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:33:40.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:33:40.63#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.20:33:40.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:33:40.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:33:40.67#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.20:33:40.67#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.20:33:40.67$vck44/va=4,7 2006.145.20:33:40.67#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.20:33:40.67#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.20:33:40.67#ibcon#ireg 11 cls_cnt 2 2006.145.20:33:40.67#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.20:33:40.73#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.20:33:40.73#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.20:33:40.75#ibcon#[25=AT04-07\r\n] 2006.145.20:33:40.78#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.20:33:40.78#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.20:33:40.78#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.20:33:40.78#ibcon#ireg 7 cls_cnt 0 2006.145.20:33:40.78#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.20:33:40.90#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.20:33:40.90#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.20:33:40.92#ibcon#[25=USB\r\n] 2006.145.20:33:40.95#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.20:33:40.95#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.20:33:40.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.20:33:40.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.20:33:40.95$vck44/valo=5,734.99 2006.145.20:33:40.95#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.20:33:40.95#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.20:33:40.95#ibcon#ireg 17 cls_cnt 0 2006.145.20:33:40.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:33:40.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:33:40.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:33:40.98#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.20:33:41.02#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:33:41.02#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:33:41.02#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.20:33:41.02#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.20:33:41.02$vck44/va=5,4 2006.145.20:33:41.02#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.20:33:41.02#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.20:33:41.02#ibcon#ireg 11 cls_cnt 2 2006.145.20:33:41.02#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:33:41.07#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:33:41.07#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:33:41.09#ibcon#[25=AT05-04\r\n] 2006.145.20:33:41.12#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:33:41.12#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:33:41.12#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.20:33:41.12#ibcon#ireg 7 cls_cnt 0 2006.145.20:33:41.12#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:33:41.24#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:33:41.24#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:33:41.26#ibcon#[25=USB\r\n] 2006.145.20:33:41.29#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:33:41.29#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:33:41.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.20:33:41.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.20:33:41.29$vck44/valo=6,814.99 2006.145.20:33:41.29#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.20:33:41.29#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.20:33:41.29#ibcon#ireg 17 cls_cnt 0 2006.145.20:33:41.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:33:41.29#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:33:41.29#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:33:41.31#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.20:33:41.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:33:41.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:33:41.35#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.20:33:41.35#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.20:33:41.35$vck44/va=6,4 2006.145.20:33:41.35#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.20:33:41.35#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.20:33:41.35#ibcon#ireg 11 cls_cnt 2 2006.145.20:33:41.35#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.20:33:41.41#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.20:33:41.41#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.20:33:41.43#ibcon#[25=AT06-04\r\n] 2006.145.20:33:41.46#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.20:33:41.46#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.20:33:41.46#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.20:33:41.46#ibcon#ireg 7 cls_cnt 0 2006.145.20:33:41.46#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.20:33:41.58#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.20:33:41.58#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.20:33:41.60#ibcon#[25=USB\r\n] 2006.145.20:33:41.63#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.20:33:41.63#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.20:33:41.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.20:33:41.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.20:33:41.63$vck44/valo=7,864.99 2006.145.20:33:41.63#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.20:33:41.63#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.20:33:41.63#ibcon#ireg 17 cls_cnt 0 2006.145.20:33:41.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.20:33:41.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.20:33:41.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.20:33:41.65#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.20:33:41.69#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.20:33:41.69#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.20:33:41.69#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.20:33:41.69#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.20:33:41.69$vck44/va=7,4 2006.145.20:33:41.69#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.20:33:41.69#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.20:33:41.69#ibcon#ireg 11 cls_cnt 2 2006.145.20:33:41.69#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.20:33:41.75#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.20:33:41.75#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.20:33:41.77#ibcon#[25=AT07-04\r\n] 2006.145.20:33:41.80#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.20:33:41.80#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.20:33:41.80#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.20:33:41.80#ibcon#ireg 7 cls_cnt 0 2006.145.20:33:41.80#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.20:33:41.92#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.20:33:41.92#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.20:33:41.94#ibcon#[25=USB\r\n] 2006.145.20:33:41.97#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.20:33:41.97#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.20:33:41.97#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.20:33:41.97#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.20:33:41.97$vck44/valo=8,884.99 2006.145.20:33:41.97#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.20:33:41.97#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.20:33:41.97#ibcon#ireg 17 cls_cnt 0 2006.145.20:33:41.97#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:33:41.97#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:33:41.97#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:33:41.99#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.20:33:42.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:33:42.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:33:42.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.20:33:42.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.20:33:42.03$vck44/va=8,4 2006.145.20:33:42.03#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.20:33:42.03#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.20:33:42.03#ibcon#ireg 11 cls_cnt 2 2006.145.20:33:42.03#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.20:33:42.09#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.20:33:42.09#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.20:33:42.11#ibcon#[25=AT08-04\r\n] 2006.145.20:33:42.15#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.20:33:42.15#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.20:33:42.15#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.20:33:42.15#ibcon#ireg 7 cls_cnt 0 2006.145.20:33:42.15#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.20:33:42.26#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.20:33:42.26#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.20:33:42.28#ibcon#[25=USB\r\n] 2006.145.20:33:42.31#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.20:33:42.31#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.20:33:42.31#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.20:33:42.31#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.20:33:42.31$vck44/vblo=1,629.99 2006.145.20:33:42.31#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.20:33:42.31#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.20:33:42.31#ibcon#ireg 17 cls_cnt 0 2006.145.20:33:42.31#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.20:33:42.31#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.20:33:42.31#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.20:33:42.34#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.20:33:42.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.20:33:42.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.20:33:42.38#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.20:33:42.38#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.20:33:42.38$vck44/vb=1,3 2006.145.20:33:42.38#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.20:33:42.38#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.20:33:42.38#ibcon#ireg 11 cls_cnt 2 2006.145.20:33:42.38#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.20:33:42.38#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.20:33:42.38#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.20:33:42.40#ibcon#[27=AT01-03\r\n] 2006.145.20:33:42.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.20:33:42.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.20:33:42.43#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.20:33:42.43#ibcon#ireg 7 cls_cnt 0 2006.145.20:33:42.43#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.20:33:42.55#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.20:33:42.55#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.20:33:42.57#ibcon#[27=USB\r\n] 2006.145.20:33:42.60#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.20:33:42.60#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.20:33:42.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.20:33:42.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.20:33:42.60$vck44/vblo=2,634.99 2006.145.20:33:42.60#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.20:33:42.60#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.20:33:42.60#ibcon#ireg 17 cls_cnt 0 2006.145.20:33:42.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:33:42.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:33:42.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:33:42.62#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.20:33:42.66#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:33:42.66#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:33:42.66#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.20:33:42.66#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.20:33:42.66$vck44/vb=2,4 2006.145.20:33:42.66#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.20:33:42.66#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.20:33:42.66#ibcon#ireg 11 cls_cnt 2 2006.145.20:33:42.66#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:33:42.72#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:33:42.72#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:33:42.74#ibcon#[27=AT02-04\r\n] 2006.145.20:33:42.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:33:42.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:33:42.77#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.20:33:42.77#ibcon#ireg 7 cls_cnt 0 2006.145.20:33:42.77#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:33:42.89#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:33:42.89#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:33:42.91#ibcon#[27=USB\r\n] 2006.145.20:33:42.94#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:33:42.94#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:33:42.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.20:33:42.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.20:33:42.94$vck44/vblo=3,649.99 2006.145.20:33:42.94#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.20:33:42.94#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.20:33:42.94#ibcon#ireg 17 cls_cnt 0 2006.145.20:33:42.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:33:42.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:33:42.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:33:42.96#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.20:33:43.00#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:33:43.00#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:33:43.00#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.20:33:43.00#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.20:33:43.00$vck44/vb=3,4 2006.145.20:33:43.00#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.20:33:43.00#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.20:33:43.00#ibcon#ireg 11 cls_cnt 2 2006.145.20:33:43.00#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:33:43.06#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:33:43.06#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:33:43.08#ibcon#[27=AT03-04\r\n] 2006.145.20:33:43.11#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:33:43.11#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:33:43.11#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.20:33:43.11#ibcon#ireg 7 cls_cnt 0 2006.145.20:33:43.11#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:33:43.23#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:33:43.23#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:33:43.25#ibcon#[27=USB\r\n] 2006.145.20:33:43.28#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:33:43.28#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:33:43.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.20:33:43.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.20:33:43.28$vck44/vblo=4,679.99 2006.145.20:33:43.28#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.20:33:43.28#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.20:33:43.28#ibcon#ireg 17 cls_cnt 0 2006.145.20:33:43.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:33:43.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:33:43.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:33:43.30#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.20:33:43.34#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:33:43.34#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:33:43.34#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.20:33:43.34#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.20:33:43.34$vck44/vb=4,4 2006.145.20:33:43.34#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.20:33:43.34#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.20:33:43.34#ibcon#ireg 11 cls_cnt 2 2006.145.20:33:43.34#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:33:43.40#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:33:43.40#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:33:43.42#ibcon#[27=AT04-04\r\n] 2006.145.20:33:43.45#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:33:43.45#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:33:43.45#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.20:33:43.45#ibcon#ireg 7 cls_cnt 0 2006.145.20:33:43.45#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:33:43.57#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:33:43.57#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:33:43.59#ibcon#[27=USB\r\n] 2006.145.20:33:43.62#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:33:43.62#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:33:43.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.20:33:43.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.20:33:43.62$vck44/vblo=5,709.99 2006.145.20:33:43.62#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.20:33:43.62#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.20:33:43.62#ibcon#ireg 17 cls_cnt 0 2006.145.20:33:43.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:33:43.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:33:43.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:33:43.64#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.20:33:43.68#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:33:43.68#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:33:43.68#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.20:33:43.68#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.20:33:43.68$vck44/vb=5,4 2006.145.20:33:43.68#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.20:33:43.68#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.20:33:43.68#ibcon#ireg 11 cls_cnt 2 2006.145.20:33:43.68#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.20:33:43.74#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.20:33:43.74#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.20:33:43.76#ibcon#[27=AT05-04\r\n] 2006.145.20:33:43.79#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.20:33:43.79#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.20:33:43.79#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.20:33:43.79#ibcon#ireg 7 cls_cnt 0 2006.145.20:33:43.79#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.20:33:43.91#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.20:33:43.91#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.20:33:43.93#ibcon#[27=USB\r\n] 2006.145.20:33:43.96#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.20:33:43.96#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.20:33:43.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.20:33:43.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.20:33:43.96$vck44/vblo=6,719.99 2006.145.20:33:43.96#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.20:33:43.96#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.20:33:43.96#ibcon#ireg 17 cls_cnt 0 2006.145.20:33:43.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:33:43.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:33:43.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:33:43.98#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.20:33:44.02#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:33:44.02#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:33:44.02#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.20:33:44.02#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.20:33:44.02$vck44/vb=6,4 2006.145.20:33:44.02#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.20:33:44.02#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.20:33:44.02#ibcon#ireg 11 cls_cnt 2 2006.145.20:33:44.02#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:33:44.08#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:33:44.08#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:33:44.10#ibcon#[27=AT06-04\r\n] 2006.145.20:33:44.13#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:33:44.13#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:33:44.13#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.20:33:44.13#ibcon#ireg 7 cls_cnt 0 2006.145.20:33:44.13#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:33:44.25#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:33:44.25#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:33:44.27#ibcon#[27=USB\r\n] 2006.145.20:33:44.30#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:33:44.30#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:33:44.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.20:33:44.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.20:33:44.30$vck44/vblo=7,734.99 2006.145.20:33:44.30#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.20:33:44.30#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.20:33:44.30#ibcon#ireg 17 cls_cnt 0 2006.145.20:33:44.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:33:44.30#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:33:44.30#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:33:44.32#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.20:33:44.36#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:33:44.36#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:33:44.36#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.20:33:44.36#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.20:33:44.36$vck44/vb=7,4 2006.145.20:33:44.36#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.20:33:44.36#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.20:33:44.36#ibcon#ireg 11 cls_cnt 2 2006.145.20:33:44.36#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.20:33:44.42#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.20:33:44.42#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.20:33:44.44#ibcon#[27=AT07-04\r\n] 2006.145.20:33:44.47#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.20:33:44.47#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.20:33:44.47#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.20:33:44.47#ibcon#ireg 7 cls_cnt 0 2006.145.20:33:44.47#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.20:33:44.59#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.20:33:44.59#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.20:33:44.61#ibcon#[27=USB\r\n] 2006.145.20:33:44.64#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.20:33:44.64#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.20:33:44.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.20:33:44.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.20:33:44.64$vck44/vblo=8,744.99 2006.145.20:33:44.64#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.20:33:44.64#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.20:33:44.64#ibcon#ireg 17 cls_cnt 0 2006.145.20:33:44.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.20:33:44.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.20:33:44.64#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.20:33:44.66#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.20:33:44.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.20:33:44.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.20:33:44.70#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.20:33:44.70#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.20:33:44.70$vck44/vb=8,4 2006.145.20:33:44.70#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.20:33:44.70#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.20:33:44.70#ibcon#ireg 11 cls_cnt 2 2006.145.20:33:44.70#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.20:33:44.76#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.20:33:44.76#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.20:33:44.78#ibcon#[27=AT08-04\r\n] 2006.145.20:33:44.81#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.20:33:44.81#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.20:33:44.81#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.20:33:44.81#ibcon#ireg 7 cls_cnt 0 2006.145.20:33:44.81#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.20:33:44.93#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.20:33:44.93#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.20:33:44.95#ibcon#[27=USB\r\n] 2006.145.20:33:44.98#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.20:33:44.98#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.20:33:44.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.20:33:44.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.20:33:44.98$vck44/vabw=wide 2006.145.20:33:44.98#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.20:33:44.98#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.20:33:44.98#ibcon#ireg 8 cls_cnt 0 2006.145.20:33:44.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:33:44.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:33:44.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:33:45.00#ibcon#[25=BW32\r\n] 2006.145.20:33:45.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:33:45.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:33:45.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.20:33:45.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.20:33:45.03$vck44/vbbw=wide 2006.145.20:33:45.03#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.20:33:45.03#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.20:33:45.03#ibcon#ireg 8 cls_cnt 0 2006.145.20:33:45.03#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:33:45.10#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:33:45.10#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:33:45.12#ibcon#[27=BW32\r\n] 2006.145.20:33:45.15#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:33:45.15#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:33:45.15#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.20:33:45.15#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.20:33:45.15$setupk4/ifdk4 2006.145.20:33:45.15$ifdk4/lo= 2006.145.20:33:45.15$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.20:33:45.15$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.20:33:45.15$ifdk4/patch= 2006.145.20:33:45.15$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.20:33:45.15$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.20:33:45.15$setupk4/!*+20s 2006.145.20:33:47.85#abcon#<5=/07 1.7 3.5 16.09 871020.0\r\n> 2006.145.20:33:47.87#abcon#{5=INTERFACE CLEAR} 2006.145.20:33:47.93#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:33:58.02#abcon#<5=/07 1.6 3.5 16.09 871020.0\r\n> 2006.145.20:33:58.04#abcon#{5=INTERFACE CLEAR} 2006.145.20:33:58.10#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:33:59.65$setupk4/"tpicd 2006.145.20:33:59.65$setupk4/echo=off 2006.145.20:33:59.65$setupk4/xlog=off 2006.145.20:33:59.65:!2006.145.20:35:55 2006.145.20:34:30.14#trakl#Source acquired 2006.145.20:34:32.14#flagr#flagr/antenna,acquired 2006.145.20:35:55.00:preob 2006.145.20:35:55.14/onsource/TRACKING 2006.145.20:35:55.14:!2006.145.20:36:05 2006.145.20:36:05.00:"tape 2006.145.20:36:05.00:"st=record 2006.145.20:36:05.00:data_valid=on 2006.145.20:36:05.00:midob 2006.145.20:36:05.14/onsource/TRACKING 2006.145.20:36:05.14/wx/16.10,1020.1,87 2006.145.20:36:05.34/cable/+6.5486E-03 2006.145.20:36:06.43/va/01,08,usb,yes,37,40 2006.145.20:36:06.43/va/02,07,usb,yes,40,41 2006.145.20:36:06.43/va/03,08,usb,yes,36,38 2006.145.20:36:06.43/va/04,07,usb,yes,41,43 2006.145.20:36:06.43/va/05,04,usb,yes,36,37 2006.145.20:36:06.43/va/06,04,usb,yes,40,40 2006.145.20:36:06.43/va/07,04,usb,yes,41,42 2006.145.20:36:06.43/va/08,04,usb,yes,35,42 2006.145.20:36:06.66/valo/01,524.99,yes,locked 2006.145.20:36:06.66/valo/02,534.99,yes,locked 2006.145.20:36:06.66/valo/03,564.99,yes,locked 2006.145.20:36:06.66/valo/04,624.99,yes,locked 2006.145.20:36:06.66/valo/05,734.99,yes,locked 2006.145.20:36:06.66/valo/06,814.99,yes,locked 2006.145.20:36:06.66/valo/07,864.99,yes,locked 2006.145.20:36:06.66/valo/08,884.99,yes,locked 2006.145.20:36:07.75/vb/01,03,usb,yes,42,39 2006.145.20:36:07.75/vb/02,04,usb,yes,37,37 2006.145.20:36:07.75/vb/03,04,usb,yes,34,37 2006.145.20:36:07.75/vb/04,04,usb,yes,39,37 2006.145.20:36:07.75/vb/05,04,usb,yes,30,33 2006.145.20:36:07.75/vb/06,04,usb,yes,36,31 2006.145.20:36:07.75/vb/07,04,usb,yes,35,35 2006.145.20:36:07.75/vb/08,04,usb,yes,32,36 2006.145.20:36:07.98/vblo/01,629.99,yes,locked 2006.145.20:36:07.98/vblo/02,634.99,yes,locked 2006.145.20:36:07.98/vblo/03,649.99,yes,locked 2006.145.20:36:07.98/vblo/04,679.99,yes,locked 2006.145.20:36:07.98/vblo/05,709.99,yes,locked 2006.145.20:36:07.98/vblo/06,719.99,yes,locked 2006.145.20:36:07.98/vblo/07,734.99,yes,locked 2006.145.20:36:07.98/vblo/08,744.99,yes,locked 2006.145.20:36:08.13/vabw/8 2006.145.20:36:08.28/vbbw/8 2006.145.20:36:08.37/xfe/off,on,15.2 2006.145.20:36:08.75/ifatt/23,28,28,28 2006.145.20:36:09.08/fmout-gps/S +4.9E-08 2006.145.20:36:09.14:!2006.145.20:38:15 2006.145.20:38:15.01:data_valid=off 2006.145.20:38:15.01:"et 2006.145.20:38:15.02:!+3s 2006.145.20:38:18.03:"tape 2006.145.20:38:18.03:postob 2006.145.20:38:18.09/cable/+6.5508E-03 2006.145.20:38:18.09/wx/16.13,1020.1,88 2006.145.20:38:18.17/fmout-gps/S +4.9E-08 2006.145.20:38:18.17:scan_name=145-2039,jd0605,160 2006.145.20:38:18.17:source=cta26,033930.94,-014635.8,2000.0,cw 2006.145.20:38:20.14#flagr#flagr/antenna,new-source 2006.145.20:38:20.14:checkk5 2006.145.20:38:20.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.20:38:21.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.20:38:21.45/chk_autoobs//k5ts3/ autoobs is running! 2006.145.20:38:21.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.20:38:22.31/chk_obsdata//k5ts1/T1452036??a.dat file size is correct (nominal:520MB, actual:520MB). 2006.145.20:38:22.76/chk_obsdata//k5ts2/T1452036??b.dat file size is correct (nominal:520MB, actual:520MB). 2006.145.20:38:23.21/chk_obsdata//k5ts3/T1452036??c.dat file size is correct (nominal:520MB, actual:520MB). 2006.145.20:38:23.64/chk_obsdata//k5ts4/T1452036??d.dat file size is correct (nominal:520MB, actual:520MB). 2006.145.20:38:24.38/k5log//k5ts1_log_newline 2006.145.20:38:25.13/k5log//k5ts2_log_newline 2006.145.20:38:25.86/k5log//k5ts3_log_newline 2006.145.20:38:26.61/k5log//k5ts4_log_newline 2006.145.20:38:26.63/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.20:38:26.63:setupk4=1 2006.145.20:38:26.63$setupk4/echo=on 2006.145.20:38:26.63$setupk4/pcalon 2006.145.20:38:26.63$pcalon/"no phase cal control is implemented here 2006.145.20:38:26.63$setupk4/"tpicd=stop 2006.145.20:38:26.64$setupk4/"rec=synch_on 2006.145.20:38:26.64$setupk4/"rec_mode=128 2006.145.20:38:26.64$setupk4/!* 2006.145.20:38:26.64$setupk4/recpk4 2006.145.20:38:26.64$recpk4/recpatch= 2006.145.20:38:26.64$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.20:38:26.64$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.20:38:26.64$setupk4/vck44 2006.145.20:38:26.64$vck44/valo=1,524.99 2006.145.20:38:26.64#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.20:38:26.64#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.20:38:26.64#ibcon#ireg 17 cls_cnt 0 2006.145.20:38:26.64#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:38:26.64#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:38:26.64#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:38:26.68#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.20:38:26.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:38:26.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:38:26.73#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.20:38:26.73#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.20:38:26.73$vck44/va=1,8 2006.145.20:38:26.73#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.20:38:26.73#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.20:38:26.73#ibcon#ireg 11 cls_cnt 2 2006.145.20:38:26.73#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.20:38:26.73#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.20:38:26.73#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.20:38:26.75#ibcon#[25=AT01-08\r\n] 2006.145.20:38:26.78#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.20:38:26.78#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.20:38:26.78#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.20:38:26.78#ibcon#ireg 7 cls_cnt 0 2006.145.20:38:26.78#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.20:38:26.90#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.20:38:26.90#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.20:38:26.92#ibcon#[25=USB\r\n] 2006.145.20:38:26.97#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.20:38:26.97#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.20:38:26.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.20:38:26.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.20:38:26.97$vck44/valo=2,534.99 2006.145.20:38:26.97#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.20:38:26.97#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.20:38:26.97#ibcon#ireg 17 cls_cnt 0 2006.145.20:38:26.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:38:26.97#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:38:26.97#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:38:26.98#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.20:38:27.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:38:27.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:38:27.02#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.20:38:27.02#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.20:38:27.02$vck44/va=2,7 2006.145.20:38:27.02#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.20:38:27.02#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.20:38:27.02#ibcon#ireg 11 cls_cnt 2 2006.145.20:38:27.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:38:27.09#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:38:27.09#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:38:27.11#ibcon#[25=AT02-07\r\n] 2006.145.20:38:27.14#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:38:27.14#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:38:27.14#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.20:38:27.14#ibcon#ireg 7 cls_cnt 0 2006.145.20:38:27.14#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:38:27.26#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:38:27.26#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:38:27.28#ibcon#[25=USB\r\n] 2006.145.20:38:27.31#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:38:27.31#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:38:27.31#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.20:38:27.31#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.20:38:27.31$vck44/valo=3,564.99 2006.145.20:38:27.31#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.20:38:27.31#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.20:38:27.31#ibcon#ireg 17 cls_cnt 0 2006.145.20:38:27.31#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:38:27.31#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:38:27.31#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:38:27.33#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.20:38:27.37#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:38:27.37#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:38:27.37#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.20:38:27.37#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.20:38:27.37$vck44/va=3,8 2006.145.20:38:27.37#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.20:38:27.37#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.20:38:27.37#ibcon#ireg 11 cls_cnt 2 2006.145.20:38:27.37#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:38:27.43#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:38:27.43#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:38:27.45#ibcon#[25=AT03-08\r\n] 2006.145.20:38:27.48#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:38:27.48#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:38:27.48#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.20:38:27.48#ibcon#ireg 7 cls_cnt 0 2006.145.20:38:27.48#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:38:27.60#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:38:27.60#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:38:27.62#ibcon#[25=USB\r\n] 2006.145.20:38:27.65#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:38:27.65#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:38:27.65#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.20:38:27.65#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.20:38:27.65$vck44/valo=4,624.99 2006.145.20:38:27.65#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.20:38:27.65#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.20:38:27.65#ibcon#ireg 17 cls_cnt 0 2006.145.20:38:27.65#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.20:38:27.65#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.20:38:27.65#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.20:38:27.67#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.20:38:27.71#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.20:38:27.71#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.20:38:27.71#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.20:38:27.71#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.20:38:27.71$vck44/va=4,7 2006.145.20:38:27.71#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.20:38:27.71#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.20:38:27.71#ibcon#ireg 11 cls_cnt 2 2006.145.20:38:27.71#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.20:38:27.77#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.20:38:27.77#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.20:38:27.79#ibcon#[25=AT04-07\r\n] 2006.145.20:38:27.82#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.20:38:27.82#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.20:38:27.82#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.20:38:27.82#ibcon#ireg 7 cls_cnt 0 2006.145.20:38:27.82#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.20:38:27.94#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.20:38:27.94#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.20:38:27.96#ibcon#[25=USB\r\n] 2006.145.20:38:27.99#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.20:38:27.99#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.20:38:27.99#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.20:38:27.99#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.20:38:27.99$vck44/valo=5,734.99 2006.145.20:38:27.99#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.20:38:27.99#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.20:38:27.99#ibcon#ireg 17 cls_cnt 0 2006.145.20:38:27.99#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.20:38:27.99#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.20:38:27.99#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.20:38:28.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.20:38:28.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.20:38:28.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.20:38:28.06#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.20:38:28.06#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.20:38:28.06$vck44/va=5,4 2006.145.20:38:28.06#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.20:38:28.06#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.20:38:28.06#ibcon#ireg 11 cls_cnt 2 2006.145.20:38:28.06#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.20:38:28.11#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.20:38:28.11#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.20:38:28.13#ibcon#[25=AT05-04\r\n] 2006.145.20:38:28.16#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.20:38:28.16#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.20:38:28.16#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.20:38:28.16#ibcon#ireg 7 cls_cnt 0 2006.145.20:38:28.16#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.20:38:28.28#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.20:38:28.28#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.20:38:28.30#ibcon#[25=USB\r\n] 2006.145.20:38:28.33#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.20:38:28.33#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.20:38:28.33#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.20:38:28.33#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.20:38:28.33$vck44/valo=6,814.99 2006.145.20:38:28.33#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.20:38:28.33#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.20:38:28.33#ibcon#ireg 17 cls_cnt 0 2006.145.20:38:28.33#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:38:28.33#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:38:28.33#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:38:28.35#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.20:38:28.39#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:38:28.39#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:38:28.39#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.20:38:28.39#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.20:38:28.39$vck44/va=6,4 2006.145.20:38:28.39#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.20:38:28.39#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.20:38:28.39#ibcon#ireg 11 cls_cnt 2 2006.145.20:38:28.39#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:38:28.45#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:38:28.45#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:38:28.47#ibcon#[25=AT06-04\r\n] 2006.145.20:38:28.50#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:38:28.50#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:38:28.50#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.20:38:28.50#ibcon#ireg 7 cls_cnt 0 2006.145.20:38:28.50#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:38:28.62#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:38:28.62#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:38:28.64#ibcon#[25=USB\r\n] 2006.145.20:38:28.67#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:38:28.67#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:38:28.67#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.20:38:28.67#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.20:38:28.67$vck44/valo=7,864.99 2006.145.20:38:28.67#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.20:38:28.67#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.20:38:28.67#ibcon#ireg 17 cls_cnt 0 2006.145.20:38:28.67#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:38:28.67#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:38:28.67#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:38:28.69#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.20:38:28.73#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:38:28.73#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:38:28.73#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.20:38:28.73#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.20:38:28.73$vck44/va=7,4 2006.145.20:38:28.73#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.20:38:28.73#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.20:38:28.73#ibcon#ireg 11 cls_cnt 2 2006.145.20:38:28.73#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:38:28.79#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:38:28.79#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:38:28.81#ibcon#[25=AT07-04\r\n] 2006.145.20:38:28.84#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:38:28.84#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:38:28.84#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.20:38:28.84#ibcon#ireg 7 cls_cnt 0 2006.145.20:38:28.84#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:38:28.96#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:38:28.96#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:38:28.98#ibcon#[25=USB\r\n] 2006.145.20:38:29.01#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:38:29.01#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:38:29.01#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.20:38:29.01#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.20:38:29.01$vck44/valo=8,884.99 2006.145.20:38:29.01#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.20:38:29.01#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.20:38:29.01#ibcon#ireg 17 cls_cnt 0 2006.145.20:38:29.01#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:38:29.01#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:38:29.01#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:38:29.03#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.20:38:29.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:38:29.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:38:29.07#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.20:38:29.07#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.20:38:29.07$vck44/va=8,4 2006.145.20:38:29.07#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.20:38:29.07#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.20:38:29.07#ibcon#ireg 11 cls_cnt 2 2006.145.20:38:29.07#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.20:38:29.13#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.20:38:29.13#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.20:38:29.15#ibcon#[25=AT08-04\r\n] 2006.145.20:38:29.18#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.20:38:29.18#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.20:38:29.18#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.20:38:29.18#ibcon#ireg 7 cls_cnt 0 2006.145.20:38:29.18#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.20:38:29.30#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.20:38:29.30#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.20:38:29.32#ibcon#[25=USB\r\n] 2006.145.20:38:29.35#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.20:38:29.35#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.20:38:29.35#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.20:38:29.35#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.20:38:29.35$vck44/vblo=1,629.99 2006.145.20:38:29.35#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.20:38:29.35#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.20:38:29.35#ibcon#ireg 17 cls_cnt 0 2006.145.20:38:29.35#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.20:38:29.35#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.20:38:29.35#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.20:38:29.37#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.20:38:29.41#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.20:38:29.41#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.20:38:29.41#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.20:38:29.41#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.20:38:29.41$vck44/vb=1,3 2006.145.20:38:29.41#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.20:38:29.41#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.20:38:29.41#ibcon#ireg 11 cls_cnt 2 2006.145.20:38:29.41#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.20:38:29.41#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.20:38:29.41#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.20:38:29.43#ibcon#[27=AT01-03\r\n] 2006.145.20:38:29.46#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.20:38:29.46#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.20:38:29.46#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.20:38:29.46#ibcon#ireg 7 cls_cnt 0 2006.145.20:38:29.46#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.20:38:29.58#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.20:38:29.58#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.20:38:29.60#ibcon#[27=USB\r\n] 2006.145.20:38:29.63#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.20:38:29.63#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.20:38:29.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.20:38:29.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.20:38:29.63$vck44/vblo=2,634.99 2006.145.20:38:29.63#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.20:38:29.63#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.20:38:29.63#ibcon#ireg 17 cls_cnt 0 2006.145.20:38:29.63#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:38:29.63#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:38:29.63#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:38:29.65#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.20:38:29.69#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:38:29.69#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:38:29.69#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.20:38:29.69#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.20:38:29.69$vck44/vb=2,4 2006.145.20:38:29.69#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.20:38:29.69#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.20:38:29.69#ibcon#ireg 11 cls_cnt 2 2006.145.20:38:29.69#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.20:38:29.75#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.20:38:29.75#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.20:38:29.77#ibcon#[27=AT02-04\r\n] 2006.145.20:38:29.80#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.20:38:29.80#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.20:38:29.80#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.20:38:29.80#ibcon#ireg 7 cls_cnt 0 2006.145.20:38:29.80#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.20:38:29.92#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.20:38:29.92#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.20:38:29.94#ibcon#[27=USB\r\n] 2006.145.20:38:29.97#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.20:38:29.97#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.20:38:29.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.20:38:29.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.20:38:29.97$vck44/vblo=3,649.99 2006.145.20:38:29.97#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.20:38:29.97#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.20:38:29.97#ibcon#ireg 17 cls_cnt 0 2006.145.20:38:29.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:38:29.97#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:38:29.97#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:38:29.99#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.20:38:30.03#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:38:30.03#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:38:30.03#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.20:38:30.03#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.20:38:30.03$vck44/vb=3,4 2006.145.20:38:30.03#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.20:38:30.03#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.20:38:30.03#ibcon#ireg 11 cls_cnt 2 2006.145.20:38:30.03#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:38:30.09#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:38:30.09#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:38:30.11#ibcon#[27=AT03-04\r\n] 2006.145.20:38:30.14#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:38:30.14#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:38:30.14#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.20:38:30.14#ibcon#ireg 7 cls_cnt 0 2006.145.20:38:30.14#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:38:30.26#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:38:30.26#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:38:30.28#ibcon#[27=USB\r\n] 2006.145.20:38:30.31#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:38:30.31#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:38:30.31#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.20:38:30.31#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.20:38:30.31$vck44/vblo=4,679.99 2006.145.20:38:30.31#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.20:38:30.31#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.20:38:30.31#ibcon#ireg 17 cls_cnt 0 2006.145.20:38:30.31#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:38:30.31#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:38:30.31#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:38:30.33#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.20:38:30.37#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:38:30.37#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:38:30.37#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.20:38:30.37#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.20:38:30.37$vck44/vb=4,4 2006.145.20:38:30.37#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.20:38:30.37#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.20:38:30.37#ibcon#ireg 11 cls_cnt 2 2006.145.20:38:30.37#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:38:30.43#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:38:30.43#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:38:30.45#ibcon#[27=AT04-04\r\n] 2006.145.20:38:30.48#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:38:30.48#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:38:30.48#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.20:38:30.48#ibcon#ireg 7 cls_cnt 0 2006.145.20:38:30.48#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:38:30.60#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:38:30.60#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:38:30.62#ibcon#[27=USB\r\n] 2006.145.20:38:30.65#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:38:30.65#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:38:30.65#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.20:38:30.65#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.20:38:30.65$vck44/vblo=5,709.99 2006.145.20:38:30.65#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.20:38:30.65#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.20:38:30.65#ibcon#ireg 17 cls_cnt 0 2006.145.20:38:30.65#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.20:38:30.65#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.20:38:30.65#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.20:38:30.67#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.20:38:30.71#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.20:38:30.71#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.20:38:30.71#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.20:38:30.71#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.20:38:30.71$vck44/vb=5,4 2006.145.20:38:30.71#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.20:38:30.71#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.20:38:30.71#ibcon#ireg 11 cls_cnt 2 2006.145.20:38:30.71#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.20:38:30.77#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.20:38:30.77#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.20:38:30.79#ibcon#[27=AT05-04\r\n] 2006.145.20:38:30.82#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.20:38:30.82#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.20:38:30.82#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.20:38:30.82#ibcon#ireg 7 cls_cnt 0 2006.145.20:38:30.82#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.20:38:30.94#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.20:38:30.94#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.20:38:30.96#ibcon#[27=USB\r\n] 2006.145.20:38:30.99#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.20:38:30.99#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.20:38:30.99#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.20:38:30.99#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.20:38:30.99$vck44/vblo=6,719.99 2006.145.20:38:30.99#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.20:38:30.99#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.20:38:30.99#ibcon#ireg 17 cls_cnt 0 2006.145.20:38:30.99#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.20:38:30.99#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.20:38:30.99#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.20:38:31.01#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.20:38:31.05#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.20:38:31.05#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.20:38:31.05#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.20:38:31.05#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.20:38:31.05$vck44/vb=6,4 2006.145.20:38:31.05#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.20:38:31.05#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.20:38:31.05#ibcon#ireg 11 cls_cnt 2 2006.145.20:38:31.05#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.20:38:31.11#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.20:38:31.11#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.20:38:31.13#ibcon#[27=AT06-04\r\n] 2006.145.20:38:31.16#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.20:38:31.16#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.20:38:31.16#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.20:38:31.16#ibcon#ireg 7 cls_cnt 0 2006.145.20:38:31.16#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.20:38:31.28#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.20:38:31.28#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.20:38:31.30#ibcon#[27=USB\r\n] 2006.145.20:38:31.33#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.20:38:31.33#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.20:38:31.33#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.20:38:31.33#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.20:38:31.33$vck44/vblo=7,734.99 2006.145.20:38:31.33#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.20:38:31.33#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.20:38:31.33#ibcon#ireg 17 cls_cnt 0 2006.145.20:38:31.33#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:38:31.33#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:38:31.33#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:38:31.35#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.20:38:31.39#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:38:31.39#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:38:31.39#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.20:38:31.39#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.20:38:31.39$vck44/vb=7,4 2006.145.20:38:31.39#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.20:38:31.39#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.20:38:31.39#ibcon#ireg 11 cls_cnt 2 2006.145.20:38:31.39#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:38:31.45#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:38:31.45#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:38:31.47#ibcon#[27=AT07-04\r\n] 2006.145.20:38:31.50#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:38:31.50#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:38:31.50#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.20:38:31.50#ibcon#ireg 7 cls_cnt 0 2006.145.20:38:31.50#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:38:31.62#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:38:31.62#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:38:31.64#ibcon#[27=USB\r\n] 2006.145.20:38:31.67#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:38:31.67#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:38:31.67#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.20:38:31.67#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.20:38:31.67$vck44/vblo=8,744.99 2006.145.20:38:31.67#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.20:38:31.67#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.20:38:31.67#ibcon#ireg 17 cls_cnt 0 2006.145.20:38:31.67#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:38:31.67#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:38:31.67#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:38:31.69#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.20:38:31.73#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:38:31.73#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:38:31.73#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.20:38:31.73#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.20:38:31.73$vck44/vb=8,4 2006.145.20:38:31.73#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.20:38:31.73#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.20:38:31.73#ibcon#ireg 11 cls_cnt 2 2006.145.20:38:31.73#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:38:31.79#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:38:31.79#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:38:31.81#ibcon#[27=AT08-04\r\n] 2006.145.20:38:31.84#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:38:31.84#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:38:31.84#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.20:38:31.84#ibcon#ireg 7 cls_cnt 0 2006.145.20:38:31.84#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:38:31.96#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:38:31.96#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:38:31.98#ibcon#[27=USB\r\n] 2006.145.20:38:32.01#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:38:32.01#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:38:32.01#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.20:38:32.01#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.20:38:32.01$vck44/vabw=wide 2006.145.20:38:32.01#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.20:38:32.01#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.20:38:32.01#ibcon#ireg 8 cls_cnt 0 2006.145.20:38:32.01#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:38:32.01#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:38:32.01#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:38:32.03#ibcon#[25=BW32\r\n] 2006.145.20:38:32.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:38:32.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:38:32.06#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.20:38:32.06#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.20:38:32.06$vck44/vbbw=wide 2006.145.20:38:32.06#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.20:38:32.06#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.20:38:32.06#ibcon#ireg 8 cls_cnt 0 2006.145.20:38:32.06#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:38:32.13#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:38:32.13#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:38:32.15#ibcon#[27=BW32\r\n] 2006.145.20:38:32.18#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:38:32.18#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:38:32.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.20:38:32.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.20:38:32.18$setupk4/ifdk4 2006.145.20:38:32.18$ifdk4/lo= 2006.145.20:38:32.18$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.20:38:32.18$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.20:38:32.18$ifdk4/patch= 2006.145.20:38:32.18$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.20:38:32.18$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.20:38:32.18$setupk4/!*+20s 2006.145.20:38:32.66#abcon#<5=/07 1.8 3.4 16.14 881020.1\r\n> 2006.145.20:38:32.68#abcon#{5=INTERFACE CLEAR} 2006.145.20:38:32.74#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:38:42.83#abcon#<5=/07 1.8 3.4 16.14 881020.0\r\n> 2006.145.20:38:42.85#abcon#{5=INTERFACE CLEAR} 2006.145.20:38:42.91#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:38:46.65$setupk4/"tpicd 2006.145.20:38:46.65$setupk4/echo=off 2006.145.20:38:46.65$setupk4/xlog=off 2006.145.20:38:46.65:!2006.145.20:39:25 2006.145.20:38:48.14#trakl#Source acquired 2006.145.20:38:48.14#flagr#flagr/antenna,acquired 2006.145.20:39:25.00:preob 2006.145.20:39:25.14/onsource/TRACKING 2006.145.20:39:25.14:!2006.145.20:39:35 2006.145.20:39:35.00:"tape 2006.145.20:39:35.00:"st=record 2006.145.20:39:35.00:data_valid=on 2006.145.20:39:35.00:midob 2006.145.20:39:36.13/onsource/TRACKING 2006.145.20:39:36.13/wx/16.16,1020.1,88 2006.145.20:39:36.24/cable/+6.5506E-03 2006.145.20:39:37.33/va/01,08,usb,yes,38,40 2006.145.20:39:37.33/va/02,07,usb,yes,40,41 2006.145.20:39:37.33/va/03,08,usb,yes,37,38 2006.145.20:39:37.33/va/04,07,usb,yes,42,44 2006.145.20:39:37.33/va/05,04,usb,yes,36,37 2006.145.20:39:37.33/va/06,04,usb,yes,41,41 2006.145.20:39:37.33/va/07,04,usb,yes,41,43 2006.145.20:39:37.33/va/08,04,usb,yes,35,42 2006.145.20:39:37.56/valo/01,524.99,yes,locked 2006.145.20:39:37.56/valo/02,534.99,yes,locked 2006.145.20:39:37.56/valo/03,564.99,yes,locked 2006.145.20:39:37.56/valo/04,624.99,yes,locked 2006.145.20:39:37.56/valo/05,734.99,yes,locked 2006.145.20:39:37.56/valo/06,814.99,yes,locked 2006.145.20:39:37.56/valo/07,864.99,yes,locked 2006.145.20:39:37.56/valo/08,884.99,yes,locked 2006.145.20:39:38.65/vb/01,03,usb,yes,41,52 2006.145.20:39:38.65/vb/02,04,usb,yes,36,46 2006.145.20:39:38.65/vb/03,04,usb,yes,33,37 2006.145.20:39:38.65/vb/04,04,usb,yes,37,36 2006.145.20:39:38.65/vb/05,04,usb,yes,30,32 2006.145.20:39:38.65/vb/06,04,usb,yes,35,31 2006.145.20:39:38.65/vb/07,04,usb,yes,34,34 2006.145.20:39:38.65/vb/08,04,usb,yes,31,35 2006.145.20:39:38.88/vblo/01,629.99,yes,locked 2006.145.20:39:38.88/vblo/02,634.99,yes,locked 2006.145.20:39:38.88/vblo/03,649.99,yes,locked 2006.145.20:39:38.88/vblo/04,679.99,yes,locked 2006.145.20:39:38.88/vblo/05,709.99,yes,locked 2006.145.20:39:38.88/vblo/06,719.99,yes,locked 2006.145.20:39:38.88/vblo/07,734.99,yes,locked 2006.145.20:39:38.88/vblo/08,744.99,yes,locked 2006.145.20:39:39.03/vabw/8 2006.145.20:39:39.18/vbbw/8 2006.145.20:39:39.27/xfe/off,on,14.5 2006.145.20:39:39.64/ifatt/23,28,28,28 2006.145.20:39:40.08/fmout-gps/S +4.8E-08 2006.145.20:39:40.12:!2006.145.20:42:15 2006.145.20:42:15.00:data_valid=off 2006.145.20:42:15.00:"et 2006.145.20:42:15.00:!+3s 2006.145.20:42:18.01:"tape 2006.145.20:42:18.01:postob 2006.145.20:42:18.13/cable/+6.5490E-03 2006.145.20:42:18.13/wx/16.23,1020.0,86 2006.145.20:42:19.08/fmout-gps/S +4.9E-08 2006.145.20:42:19.08:scan_name=145-2043,jd0605,40 2006.145.20:42:19.08:source=2134+00,213638.59,004154.2,2000.0,cw 2006.145.20:42:20.14#flagr#flagr/antenna,new-source 2006.145.20:42:20.14:checkk5 2006.145.20:42:20.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.20:42:21.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.20:42:21.48/chk_autoobs//k5ts3/ autoobs is running! 2006.145.20:42:21.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.20:42:22.34/chk_obsdata//k5ts1/T1452039??a.dat file size is correct (nominal:640MB, actual:636MB). 2006.145.20:42:22.78/chk_obsdata//k5ts2/T1452039??b.dat file size is correct (nominal:640MB, actual:636MB). 2006.145.20:42:23.21/chk_obsdata//k5ts3/T1452039??c.dat file size is correct (nominal:640MB, actual:636MB). 2006.145.20:42:23.66/chk_obsdata//k5ts4/T1452039??d.dat file size is correct (nominal:640MB, actual:636MB). 2006.145.20:42:24.45/k5log//k5ts1_log_newline 2006.145.20:42:25.18/k5log//k5ts2_log_newline 2006.145.20:42:25.93/k5log//k5ts3_log_newline 2006.145.20:42:26.67/k5log//k5ts4_log_newline 2006.145.20:42:26.69/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.20:42:26.69:setupk4=1 2006.145.20:42:26.70$setupk4/echo=on 2006.145.20:42:26.70$setupk4/pcalon 2006.145.20:42:26.70$pcalon/"no phase cal control is implemented here 2006.145.20:42:26.70$setupk4/"tpicd=stop 2006.145.20:42:26.70$setupk4/"rec=synch_on 2006.145.20:42:26.70$setupk4/"rec_mode=128 2006.145.20:42:26.70$setupk4/!* 2006.145.20:42:26.70$setupk4/recpk4 2006.145.20:42:26.70$recpk4/recpatch= 2006.145.20:42:26.70$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.20:42:26.70$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.20:42:26.70$setupk4/vck44 2006.145.20:42:26.70$vck44/valo=1,524.99 2006.145.20:42:26.70#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.20:42:26.70#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.20:42:26.70#ibcon#ireg 17 cls_cnt 0 2006.145.20:42:26.70#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:42:26.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:42:26.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:42:26.74#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.20:42:26.76#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:42:26.79#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:42:26.79#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:42:26.79#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.20:42:26.79#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.20:42:26.79$vck44/va=1,8 2006.145.20:42:26.79#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.20:42:26.79#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.20:42:26.79#ibcon#ireg 11 cls_cnt 2 2006.145.20:42:26.79#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:42:26.79#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:42:26.79#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:42:26.81#ibcon#[25=AT01-08\r\n] 2006.145.20:42:26.84#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:42:26.84#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:42:26.84#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.20:42:26.84#ibcon#ireg 7 cls_cnt 0 2006.145.20:42:26.84#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:42:26.96#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:42:26.96#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:42:26.98#ibcon#[25=USB\r\n] 2006.145.20:42:27.01#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:42:27.01#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:42:27.01#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.20:42:27.01#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.20:42:27.01$vck44/valo=2,534.99 2006.145.20:42:27.01#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.20:42:27.01#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.20:42:27.01#ibcon#ireg 17 cls_cnt 0 2006.145.20:42:27.01#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:42:27.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:42:27.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:42:27.04#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.20:42:27.08#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:42:27.08#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:42:27.08#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.20:42:27.08#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.20:42:27.08$vck44/va=2,7 2006.145.20:42:27.08#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.20:42:27.08#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.20:42:27.08#ibcon#ireg 11 cls_cnt 2 2006.145.20:42:27.08#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:42:27.13#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:42:27.13#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:42:27.15#ibcon#[25=AT02-07\r\n] 2006.145.20:42:27.18#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:42:27.18#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:42:27.18#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.20:42:27.18#ibcon#ireg 7 cls_cnt 0 2006.145.20:42:27.18#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:42:27.30#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:42:27.30#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:42:27.32#ibcon#[25=USB\r\n] 2006.145.20:42:27.35#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:42:27.35#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:42:27.35#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.20:42:27.35#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.20:42:27.35$vck44/valo=3,564.99 2006.145.20:42:27.35#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.20:42:27.35#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.20:42:27.35#ibcon#ireg 17 cls_cnt 0 2006.145.20:42:27.35#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:42:27.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:42:27.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:42:27.37#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.20:42:27.41#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:42:27.41#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:42:27.41#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.20:42:27.41#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.20:42:27.41$vck44/va=3,8 2006.145.20:42:27.41#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.20:42:27.41#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.20:42:27.41#ibcon#ireg 11 cls_cnt 2 2006.145.20:42:27.41#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:42:27.47#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:42:27.47#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:42:27.49#ibcon#[25=AT03-08\r\n] 2006.145.20:42:27.52#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:42:27.52#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:42:27.52#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.20:42:27.52#ibcon#ireg 7 cls_cnt 0 2006.145.20:42:27.52#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:42:27.64#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:42:27.64#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:42:27.66#ibcon#[25=USB\r\n] 2006.145.20:42:27.69#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:42:27.69#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:42:27.69#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.20:42:27.69#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.20:42:27.69$vck44/valo=4,624.99 2006.145.20:42:27.69#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.20:42:27.69#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.20:42:27.69#ibcon#ireg 17 cls_cnt 0 2006.145.20:42:27.69#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:42:27.69#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:42:27.69#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:42:27.71#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.20:42:27.75#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:42:27.75#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:42:27.75#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.20:42:27.75#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.20:42:27.75$vck44/va=4,7 2006.145.20:42:27.75#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.20:42:27.75#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.20:42:27.75#ibcon#ireg 11 cls_cnt 2 2006.145.20:42:27.75#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:42:27.81#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:42:27.81#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:42:27.83#ibcon#[25=AT04-07\r\n] 2006.145.20:42:27.86#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:42:27.86#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:42:27.86#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.20:42:27.86#ibcon#ireg 7 cls_cnt 0 2006.145.20:42:27.86#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:42:27.98#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:42:27.98#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:42:28.00#ibcon#[25=USB\r\n] 2006.145.20:42:28.03#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:42:28.03#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:42:28.03#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.20:42:28.03#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.20:42:28.03$vck44/valo=5,734.99 2006.145.20:42:28.03#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.20:42:28.03#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.20:42:28.03#ibcon#ireg 17 cls_cnt 0 2006.145.20:42:28.03#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:42:28.03#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:42:28.03#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:42:28.05#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.20:42:28.09#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:42:28.09#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:42:28.09#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.20:42:28.09#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.20:42:28.09$vck44/va=5,4 2006.145.20:42:28.09#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.20:42:28.09#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.20:42:28.09#ibcon#ireg 11 cls_cnt 2 2006.145.20:42:28.09#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:42:28.15#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:42:28.15#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:42:28.17#ibcon#[25=AT05-04\r\n] 2006.145.20:42:28.20#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:42:28.20#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:42:28.20#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.20:42:28.20#ibcon#ireg 7 cls_cnt 0 2006.145.20:42:28.20#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:42:28.32#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:42:28.32#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:42:28.34#ibcon#[25=USB\r\n] 2006.145.20:42:28.37#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:42:28.37#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:42:28.37#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.20:42:28.37#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.20:42:28.37$vck44/valo=6,814.99 2006.145.20:42:28.37#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.20:42:28.37#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.20:42:28.37#ibcon#ireg 17 cls_cnt 0 2006.145.20:42:28.37#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:42:28.37#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:42:28.37#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:42:28.39#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.20:42:28.43#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:42:28.43#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:42:28.43#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.20:42:28.43#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.20:42:28.43$vck44/va=6,4 2006.145.20:42:28.43#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.20:42:28.43#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.20:42:28.43#ibcon#ireg 11 cls_cnt 2 2006.145.20:42:28.43#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:42:28.49#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:42:28.49#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:42:28.51#ibcon#[25=AT06-04\r\n] 2006.145.20:42:28.54#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:42:28.54#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:42:28.54#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.20:42:28.54#ibcon#ireg 7 cls_cnt 0 2006.145.20:42:28.54#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:42:28.66#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:42:28.66#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:42:28.68#ibcon#[25=USB\r\n] 2006.145.20:42:28.71#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:42:28.71#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:42:28.71#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.20:42:28.71#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.20:42:28.71$vck44/valo=7,864.99 2006.145.20:42:28.71#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.20:42:28.71#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.20:42:28.71#ibcon#ireg 17 cls_cnt 0 2006.145.20:42:28.71#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:42:28.71#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:42:28.71#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:42:28.73#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.20:42:28.77#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:42:28.77#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:42:28.77#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.20:42:28.77#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.20:42:28.77$vck44/va=7,4 2006.145.20:42:28.77#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.20:42:28.77#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.20:42:28.77#ibcon#ireg 11 cls_cnt 2 2006.145.20:42:28.77#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:42:28.83#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:42:28.83#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:42:28.85#ibcon#[25=AT07-04\r\n] 2006.145.20:42:28.88#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:42:28.88#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:42:28.88#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.20:42:28.88#ibcon#ireg 7 cls_cnt 0 2006.145.20:42:28.88#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:42:29.00#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:42:29.00#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:42:29.02#ibcon#[25=USB\r\n] 2006.145.20:42:29.05#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:42:29.05#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:42:29.05#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.20:42:29.05#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.20:42:29.05$vck44/valo=8,884.99 2006.145.20:42:29.05#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.20:42:29.05#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.20:42:29.05#ibcon#ireg 17 cls_cnt 0 2006.145.20:42:29.05#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:42:29.05#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:42:29.05#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:42:29.07#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.20:42:29.11#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:42:29.11#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:42:29.11#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.20:42:29.11#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.20:42:29.11$vck44/va=8,4 2006.145.20:42:29.11#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.20:42:29.11#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.20:42:29.11#ibcon#ireg 11 cls_cnt 2 2006.145.20:42:29.11#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:42:29.17#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:42:29.17#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:42:29.19#ibcon#[25=AT08-04\r\n] 2006.145.20:42:29.22#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:42:29.22#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:42:29.22#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.20:42:29.22#ibcon#ireg 7 cls_cnt 0 2006.145.20:42:29.22#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:42:29.35#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:42:29.35#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:42:29.37#ibcon#[25=USB\r\n] 2006.145.20:42:29.40#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:42:29.40#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:42:29.40#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.20:42:29.40#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.20:42:29.40$vck44/vblo=1,629.99 2006.145.20:42:29.40#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.20:42:29.40#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.20:42:29.40#ibcon#ireg 17 cls_cnt 0 2006.145.20:42:29.40#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.20:42:29.40#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.20:42:29.40#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.20:42:29.42#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.20:42:29.46#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.20:42:29.46#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.20:42:29.46#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.20:42:29.46#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.20:42:29.46$vck44/vb=1,3 2006.145.20:42:29.46#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.20:42:29.46#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.20:42:29.46#ibcon#ireg 11 cls_cnt 2 2006.145.20:42:29.46#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.20:42:29.46#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.20:42:29.46#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.20:42:29.48#ibcon#[27=AT01-03\r\n] 2006.145.20:42:29.51#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.20:42:29.51#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.20:42:29.51#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.20:42:29.51#ibcon#ireg 7 cls_cnt 0 2006.145.20:42:29.51#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.20:42:29.63#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.20:42:29.63#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.20:42:29.65#ibcon#[27=USB\r\n] 2006.145.20:42:29.68#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.20:42:29.68#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.20:42:29.68#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.20:42:29.68#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.20:42:29.68$vck44/vblo=2,634.99 2006.145.20:42:29.68#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.20:42:29.68#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.20:42:29.68#ibcon#ireg 17 cls_cnt 0 2006.145.20:42:29.68#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:42:29.68#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:42:29.68#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:42:29.70#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.20:42:29.74#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:42:29.74#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:42:29.74#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.20:42:29.74#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.20:42:29.74$vck44/vb=2,4 2006.145.20:42:29.74#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.20:42:29.74#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.20:42:29.74#ibcon#ireg 11 cls_cnt 2 2006.145.20:42:29.74#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:42:29.80#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:42:29.80#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:42:29.82#ibcon#[27=AT02-04\r\n] 2006.145.20:42:29.85#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:42:29.85#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:42:29.85#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.20:42:29.85#ibcon#ireg 7 cls_cnt 0 2006.145.20:42:29.85#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:42:29.97#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:42:29.97#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:42:29.99#ibcon#[27=USB\r\n] 2006.145.20:42:30.02#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:42:30.02#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:42:30.02#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.20:42:30.02#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.20:42:30.02$vck44/vblo=3,649.99 2006.145.20:42:30.02#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.20:42:30.02#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.20:42:30.02#ibcon#ireg 17 cls_cnt 0 2006.145.20:42:30.02#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:42:30.02#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:42:30.02#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:42:30.04#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.20:42:30.08#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:42:30.08#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:42:30.08#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.20:42:30.08#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.20:42:30.08$vck44/vb=3,4 2006.145.20:42:30.08#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.20:42:30.08#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.20:42:30.08#ibcon#ireg 11 cls_cnt 2 2006.145.20:42:30.08#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:42:30.14#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:42:30.14#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:42:30.16#ibcon#[27=AT03-04\r\n] 2006.145.20:42:30.19#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:42:30.19#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:42:30.19#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.20:42:30.19#ibcon#ireg 7 cls_cnt 0 2006.145.20:42:30.19#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:42:30.31#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:42:30.31#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:42:30.33#ibcon#[27=USB\r\n] 2006.145.20:42:30.36#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:42:30.36#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:42:30.36#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.20:42:30.36#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.20:42:30.36$vck44/vblo=4,679.99 2006.145.20:42:30.36#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.20:42:30.36#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.20:42:30.36#ibcon#ireg 17 cls_cnt 0 2006.145.20:42:30.36#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:42:30.36#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:42:30.36#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:42:30.38#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.20:42:30.42#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:42:30.42#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:42:30.42#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.20:42:30.42#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.20:42:30.42$vck44/vb=4,4 2006.145.20:42:30.42#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.20:42:30.42#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.20:42:30.42#ibcon#ireg 11 cls_cnt 2 2006.145.20:42:30.42#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:42:30.48#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:42:30.48#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:42:30.50#ibcon#[27=AT04-04\r\n] 2006.145.20:42:30.53#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:42:30.53#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:42:30.53#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.20:42:30.53#ibcon#ireg 7 cls_cnt 0 2006.145.20:42:30.53#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:42:30.65#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:42:30.65#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:42:30.67#ibcon#[27=USB\r\n] 2006.145.20:42:30.70#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:42:30.70#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:42:30.70#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.20:42:30.70#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.20:42:30.70$vck44/vblo=5,709.99 2006.145.20:42:30.70#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.20:42:30.70#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.20:42:30.70#ibcon#ireg 17 cls_cnt 0 2006.145.20:42:30.70#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:42:30.70#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:42:30.70#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:42:30.72#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.20:42:30.76#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:42:30.76#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:42:30.76#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.20:42:30.76#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.20:42:30.76$vck44/vb=5,4 2006.145.20:42:30.76#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.20:42:30.76#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.20:42:30.76#ibcon#ireg 11 cls_cnt 2 2006.145.20:42:30.76#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:42:30.82#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:42:30.82#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:42:30.84#ibcon#[27=AT05-04\r\n] 2006.145.20:42:30.87#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:42:30.87#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:42:30.87#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.20:42:30.87#ibcon#ireg 7 cls_cnt 0 2006.145.20:42:30.87#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:42:30.99#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:42:30.99#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:42:31.01#ibcon#[27=USB\r\n] 2006.145.20:42:31.04#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:42:31.04#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:42:31.04#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.20:42:31.04#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.20:42:31.04$vck44/vblo=6,719.99 2006.145.20:42:31.04#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.20:42:31.04#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.20:42:31.04#ibcon#ireg 17 cls_cnt 0 2006.145.20:42:31.04#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:42:31.04#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:42:31.04#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:42:31.06#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.20:42:31.10#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:42:31.10#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:42:31.10#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.20:42:31.10#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.20:42:31.10$vck44/vb=6,4 2006.145.20:42:31.10#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.20:42:31.10#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.20:42:31.10#ibcon#ireg 11 cls_cnt 2 2006.145.20:42:31.10#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:42:31.16#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:42:31.16#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:42:31.18#ibcon#[27=AT06-04\r\n] 2006.145.20:42:31.21#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:42:31.21#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:42:31.21#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.20:42:31.21#ibcon#ireg 7 cls_cnt 0 2006.145.20:42:31.21#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:42:31.33#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:42:31.33#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:42:31.35#ibcon#[27=USB\r\n] 2006.145.20:42:31.38#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:42:31.38#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:42:31.38#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.20:42:31.38#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.20:42:31.38$vck44/vblo=7,734.99 2006.145.20:42:31.38#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.20:42:31.38#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.20:42:31.38#ibcon#ireg 17 cls_cnt 0 2006.145.20:42:31.38#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:42:31.38#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:42:31.38#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:42:31.40#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.20:42:31.44#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:42:31.44#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:42:31.44#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.20:42:31.44#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.20:42:31.44$vck44/vb=7,4 2006.145.20:42:31.44#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.20:42:31.44#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.20:42:31.44#ibcon#ireg 11 cls_cnt 2 2006.145.20:42:31.44#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:42:31.50#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:42:31.50#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:42:31.52#ibcon#[27=AT07-04\r\n] 2006.145.20:42:31.55#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:42:31.55#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:42:31.55#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.20:42:31.55#ibcon#ireg 7 cls_cnt 0 2006.145.20:42:31.55#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:42:31.67#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:42:31.67#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:42:31.69#ibcon#[27=USB\r\n] 2006.145.20:42:31.72#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:42:31.72#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:42:31.72#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.20:42:31.72#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.20:42:31.72$vck44/vblo=8,744.99 2006.145.20:42:31.72#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.20:42:31.72#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.20:42:31.72#ibcon#ireg 17 cls_cnt 0 2006.145.20:42:31.72#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:42:31.72#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:42:31.72#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:42:31.74#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.20:42:31.78#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:42:31.78#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:42:31.78#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.20:42:31.78#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.20:42:31.78$vck44/vb=8,4 2006.145.20:42:31.78#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.20:42:31.78#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.20:42:31.78#ibcon#ireg 11 cls_cnt 2 2006.145.20:42:31.78#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:42:31.84#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:42:31.84#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:42:31.86#ibcon#[27=AT08-04\r\n] 2006.145.20:42:31.89#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:42:31.89#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:42:31.89#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.20:42:31.89#ibcon#ireg 7 cls_cnt 0 2006.145.20:42:31.89#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:42:32.01#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:42:32.01#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:42:32.03#ibcon#[27=USB\r\n] 2006.145.20:42:32.06#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:42:32.06#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:42:32.06#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.20:42:32.06#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.20:42:32.06$vck44/vabw=wide 2006.145.20:42:32.06#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.20:42:32.06#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.20:42:32.06#ibcon#ireg 8 cls_cnt 0 2006.145.20:42:32.06#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:42:32.06#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:42:32.06#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:42:32.08#ibcon#[25=BW32\r\n] 2006.145.20:42:32.11#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:42:32.11#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:42:32.11#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.20:42:32.11#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.20:42:32.11$vck44/vbbw=wide 2006.145.20:42:32.11#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.20:42:32.11#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.20:42:32.11#ibcon#ireg 8 cls_cnt 0 2006.145.20:42:32.11#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:42:32.18#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:42:32.18#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:42:32.20#ibcon#[27=BW32\r\n] 2006.145.20:42:32.23#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:42:32.23#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:42:32.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.20:42:32.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.20:42:32.23$setupk4/ifdk4 2006.145.20:42:32.23$ifdk4/lo= 2006.145.20:42:32.23$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.20:42:32.23$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.20:42:32.23$ifdk4/patch= 2006.145.20:42:32.23$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.20:42:32.23$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.20:42:32.23$setupk4/!*+20s 2006.145.20:42:36.85#abcon#<5=/07 1.6 3.9 16.24 861020.0\r\n> 2006.145.20:42:36.87#abcon#{5=INTERFACE CLEAR} 2006.145.20:42:36.93#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:42:46.71$setupk4/"tpicd 2006.145.20:42:46.71$setupk4/echo=off 2006.145.20:42:46.71$setupk4/xlog=off 2006.145.20:42:46.71:!2006.145.20:43:03 2006.145.20:43:00.14#trakl#Source acquired 2006.145.20:43:00.14#flagr#flagr/antenna,acquired 2006.145.20:43:03.00:preob 2006.145.20:43:04.14/onsource/TRACKING 2006.145.20:43:04.14:!2006.145.20:43:13 2006.145.20:43:13.00:"tape 2006.145.20:43:13.00:"st=record 2006.145.20:43:13.00:data_valid=on 2006.145.20:43:13.00:midob 2006.145.20:43:13.14/onsource/TRACKING 2006.145.20:43:13.14/wx/16.26,1020.0,86 2006.145.20:43:13.28/cable/+6.5503E-03 2006.145.20:43:14.37/va/01,08,usb,yes,29,31 2006.145.20:43:14.37/va/02,07,usb,yes,31,31 2006.145.20:43:14.37/va/03,08,usb,yes,28,29 2006.145.20:43:14.37/va/04,07,usb,yes,32,33 2006.145.20:43:14.37/va/05,04,usb,yes,28,28 2006.145.20:43:14.37/va/06,04,usb,yes,31,31 2006.145.20:43:14.37/va/07,04,usb,yes,31,32 2006.145.20:43:14.37/va/08,04,usb,yes,27,32 2006.145.20:43:14.60/valo/01,524.99,yes,locked 2006.145.20:43:14.60/valo/02,534.99,yes,locked 2006.145.20:43:14.60/valo/03,564.99,yes,locked 2006.145.20:43:14.60/valo/04,624.99,yes,locked 2006.145.20:43:14.60/valo/05,734.99,yes,locked 2006.145.20:43:14.60/valo/06,814.99,yes,locked 2006.145.20:43:14.60/valo/07,864.99,yes,locked 2006.145.20:43:14.60/valo/08,884.99,yes,locked 2006.145.20:43:15.69/vb/01,03,usb,yes,36,33 2006.145.20:43:15.69/vb/02,04,usb,yes,31,31 2006.145.20:43:15.69/vb/03,04,usb,yes,28,31 2006.145.20:43:15.69/vb/04,04,usb,yes,33,32 2006.145.20:43:15.69/vb/05,04,usb,yes,25,28 2006.145.20:43:15.69/vb/06,04,usb,yes,30,26 2006.145.20:43:15.69/vb/07,04,usb,yes,29,29 2006.145.20:43:15.69/vb/08,04,usb,yes,27,30 2006.145.20:43:15.92/vblo/01,629.99,yes,locked 2006.145.20:43:15.92/vblo/02,634.99,yes,locked 2006.145.20:43:15.92/vblo/03,649.99,yes,locked 2006.145.20:43:15.92/vblo/04,679.99,yes,locked 2006.145.20:43:15.92/vblo/05,709.99,yes,locked 2006.145.20:43:15.92/vblo/06,719.99,yes,locked 2006.145.20:43:15.92/vblo/07,734.99,yes,locked 2006.145.20:43:15.92/vblo/08,744.99,yes,locked 2006.145.20:43:16.07/vabw/8 2006.145.20:43:16.22/vbbw/8 2006.145.20:43:16.31/xfe/off,on,15.2 2006.145.20:43:16.68/ifatt/23,28,28,28 2006.145.20:43:17.08/fmout-gps/S +4.9E-08 2006.145.20:43:17.12:!2006.145.20:43:53 2006.145.20:43:53.00:data_valid=off 2006.145.20:43:53.00:"et 2006.145.20:43:53.00:!+3s 2006.145.20:43:56.02:"tape 2006.145.20:43:56.02:postob 2006.145.20:43:56.13/cable/+6.5492E-03 2006.145.20:43:56.13/wx/16.27,1020.0,86 2006.145.20:43:57.07/fmout-gps/S +4.9E-08 2006.145.20:43:57.07:scan_name=145-2045,jd0605,180 2006.145.20:43:57.07:source=3c446,222547.26,-045701.4,2000.0,cw 2006.145.20:43:58.14#flagr#flagr/antenna,new-source 2006.145.20:43:58.14:checkk5 2006.145.20:43:58.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.20:43:59.04/chk_autoobs//k5ts2/ autoobs is running! 2006.145.20:43:59.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.20:43:59.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.20:44:00.33/chk_obsdata//k5ts1/T1452043??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.20:44:00.76/chk_obsdata//k5ts2/T1452043??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.20:44:01.20/chk_obsdata//k5ts3/T1452043??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.20:44:01.66/chk_obsdata//k5ts4/T1452043??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.145.20:44:02.41/k5log//k5ts1_log_newline 2006.145.20:44:03.17/k5log//k5ts2_log_newline 2006.145.20:44:03.90/k5log//k5ts3_log_newline 2006.145.20:44:04.65/k5log//k5ts4_log_newline 2006.145.20:44:04.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.20:44:04.67:setupk4=1 2006.145.20:44:04.67$setupk4/echo=on 2006.145.20:44:04.67$setupk4/pcalon 2006.145.20:44:04.67$pcalon/"no phase cal control is implemented here 2006.145.20:44:04.67$setupk4/"tpicd=stop 2006.145.20:44:04.67$setupk4/"rec=synch_on 2006.145.20:44:04.67$setupk4/"rec_mode=128 2006.145.20:44:04.67$setupk4/!* 2006.145.20:44:04.67$setupk4/recpk4 2006.145.20:44:04.67$recpk4/recpatch= 2006.145.20:44:04.68$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.20:44:04.68$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.20:44:04.68$setupk4/vck44 2006.145.20:44:04.68$vck44/valo=1,524.99 2006.145.20:44:04.68#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.20:44:04.68#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.20:44:04.68#ibcon#ireg 17 cls_cnt 0 2006.145.20:44:04.68#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:44:04.68#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:44:04.68#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:44:04.72#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.20:44:04.77#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:44:04.77#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:44:04.77#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.20:44:04.77#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.20:44:04.77$vck44/va=1,8 2006.145.20:44:04.77#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.20:44:04.77#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.20:44:04.77#ibcon#ireg 11 cls_cnt 2 2006.145.20:44:04.77#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.20:44:04.77#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.20:44:04.77#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.20:44:04.79#ibcon#[25=AT01-08\r\n] 2006.145.20:44:04.82#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.20:44:04.82#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.20:44:04.82#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.20:44:04.82#ibcon#ireg 7 cls_cnt 0 2006.145.20:44:04.82#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.20:44:04.94#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.20:44:04.94#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.20:44:04.96#ibcon#[25=USB\r\n] 2006.145.20:44:05.01#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.20:44:05.01#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.20:44:05.01#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.20:44:05.01#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.20:44:05.01$vck44/valo=2,534.99 2006.145.20:44:05.01#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.20:44:05.01#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.20:44:05.01#ibcon#ireg 17 cls_cnt 0 2006.145.20:44:05.01#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:44:05.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:44:05.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:44:05.03#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.20:44:05.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:44:05.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:44:05.07#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.20:44:05.07#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.20:44:05.07$vck44/va=2,7 2006.145.20:44:05.07#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.20:44:05.07#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.20:44:05.07#ibcon#ireg 11 cls_cnt 2 2006.145.20:44:05.07#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:44:05.13#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:44:05.13#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:44:05.15#ibcon#[25=AT02-07\r\n] 2006.145.20:44:05.18#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:44:05.18#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:44:05.18#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.20:44:05.18#ibcon#ireg 7 cls_cnt 0 2006.145.20:44:05.18#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:44:05.30#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:44:05.30#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:44:05.32#ibcon#[25=USB\r\n] 2006.145.20:44:05.35#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:44:05.35#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:44:05.35#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.20:44:05.35#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.20:44:05.35$vck44/valo=3,564.99 2006.145.20:44:05.35#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.20:44:05.35#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.20:44:05.35#ibcon#ireg 17 cls_cnt 0 2006.145.20:44:05.35#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:44:05.35#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:44:05.35#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:44:05.37#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.20:44:05.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:44:05.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.20:44:05.41#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.20:44:05.41#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.20:44:05.41$vck44/va=3,8 2006.145.20:44:05.41#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.20:44:05.41#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.20:44:05.41#ibcon#ireg 11 cls_cnt 2 2006.145.20:44:05.41#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:44:05.47#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:44:05.47#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:44:05.49#ibcon#[25=AT03-08\r\n] 2006.145.20:44:05.52#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:44:05.52#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.20:44:05.52#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.20:44:05.52#ibcon#ireg 7 cls_cnt 0 2006.145.20:44:05.52#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:44:05.64#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:44:05.64#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:44:05.66#ibcon#[25=USB\r\n] 2006.145.20:44:05.69#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:44:05.69#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.20:44:05.69#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.20:44:05.69#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.20:44:05.69$vck44/valo=4,624.99 2006.145.20:44:05.69#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.20:44:05.69#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.20:44:05.69#ibcon#ireg 17 cls_cnt 0 2006.145.20:44:05.69#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.20:44:05.69#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.20:44:05.69#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.20:44:05.71#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.20:44:05.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.20:44:05.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.20:44:05.75#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.20:44:05.75#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.20:44:05.75$vck44/va=4,7 2006.145.20:44:05.75#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.20:44:05.75#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.20:44:05.75#ibcon#ireg 11 cls_cnt 2 2006.145.20:44:05.75#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.20:44:05.81#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.20:44:05.81#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.20:44:05.83#ibcon#[25=AT04-07\r\n] 2006.145.20:44:05.86#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.20:44:05.86#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.20:44:05.86#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.20:44:05.86#ibcon#ireg 7 cls_cnt 0 2006.145.20:44:05.86#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.20:44:05.98#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.20:44:05.98#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.20:44:06.00#ibcon#[25=USB\r\n] 2006.145.20:44:06.03#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.20:44:06.03#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.20:44:06.03#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.20:44:06.03#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.20:44:06.03$vck44/valo=5,734.99 2006.145.20:44:06.03#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.20:44:06.03#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.20:44:06.03#ibcon#ireg 17 cls_cnt 0 2006.145.20:44:06.03#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:44:06.03#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:44:06.03#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:44:06.05#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.20:44:06.09#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:44:06.09#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:44:06.09#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.20:44:06.09#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.20:44:06.09$vck44/va=5,4 2006.145.20:44:06.09#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.20:44:06.09#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.20:44:06.09#ibcon#ireg 11 cls_cnt 2 2006.145.20:44:06.09#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.20:44:06.15#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.20:44:06.15#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.20:44:06.17#ibcon#[25=AT05-04\r\n] 2006.145.20:44:06.21#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.20:44:06.21#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.20:44:06.21#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.20:44:06.21#ibcon#ireg 7 cls_cnt 0 2006.145.20:44:06.21#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.20:44:06.33#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.20:44:06.33#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.20:44:06.35#ibcon#[25=USB\r\n] 2006.145.20:44:06.38#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.20:44:06.38#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.20:44:06.38#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.20:44:06.38#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.20:44:06.38$vck44/valo=6,814.99 2006.145.20:44:06.38#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.20:44:06.38#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.20:44:06.38#ibcon#ireg 17 cls_cnt 0 2006.145.20:44:06.38#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.20:44:06.38#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.20:44:06.38#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.20:44:06.40#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.20:44:06.44#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.20:44:06.44#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.20:44:06.44#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.20:44:06.44#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.20:44:06.44$vck44/va=6,4 2006.145.20:44:06.44#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.20:44:06.44#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.20:44:06.44#ibcon#ireg 11 cls_cnt 2 2006.145.20:44:06.44#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.20:44:06.50#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.20:44:06.50#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.20:44:06.52#ibcon#[25=AT06-04\r\n] 2006.145.20:44:06.55#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.20:44:06.55#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.20:44:06.55#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.20:44:06.55#ibcon#ireg 7 cls_cnt 0 2006.145.20:44:06.55#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.20:44:06.67#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.20:44:06.67#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.20:44:06.69#ibcon#[25=USB\r\n] 2006.145.20:44:06.72#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.20:44:06.72#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.20:44:06.72#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.20:44:06.72#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.20:44:06.72$vck44/valo=7,864.99 2006.145.20:44:06.72#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.20:44:06.72#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.20:44:06.72#ibcon#ireg 17 cls_cnt 0 2006.145.20:44:06.72#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:44:06.72#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:44:06.72#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:44:06.74#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.20:44:06.78#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:44:06.78#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:44:06.78#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.20:44:06.78#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.20:44:06.78$vck44/va=7,4 2006.145.20:44:06.78#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.20:44:06.78#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.20:44:06.78#ibcon#ireg 11 cls_cnt 2 2006.145.20:44:06.78#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:44:06.84#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:44:06.84#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:44:06.86#ibcon#[25=AT07-04\r\n] 2006.145.20:44:06.89#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:44:06.89#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:44:06.89#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.20:44:06.89#ibcon#ireg 7 cls_cnt 0 2006.145.20:44:06.89#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:44:07.01#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:44:07.01#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:44:07.03#ibcon#[25=USB\r\n] 2006.145.20:44:07.06#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:44:07.06#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:44:07.06#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.20:44:07.06#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.20:44:07.06$vck44/valo=8,884.99 2006.145.20:44:07.06#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.20:44:07.06#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.20:44:07.06#ibcon#ireg 17 cls_cnt 0 2006.145.20:44:07.06#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:44:07.06#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:44:07.06#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:44:07.08#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.20:44:07.12#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:44:07.12#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:44:07.12#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.20:44:07.12#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.20:44:07.12$vck44/va=8,4 2006.145.20:44:07.12#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.20:44:07.12#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.20:44:07.12#ibcon#ireg 11 cls_cnt 2 2006.145.20:44:07.12#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:44:07.18#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:44:07.18#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:44:07.20#ibcon#[25=AT08-04\r\n] 2006.145.20:44:07.23#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:44:07.23#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:44:07.23#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.20:44:07.23#ibcon#ireg 7 cls_cnt 0 2006.145.20:44:07.23#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:44:07.36#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:44:07.36#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:44:07.38#ibcon#[25=USB\r\n] 2006.145.20:44:07.41#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:44:07.41#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:44:07.41#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.20:44:07.41#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.20:44:07.41$vck44/vblo=1,629.99 2006.145.20:44:07.41#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.20:44:07.41#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.20:44:07.41#ibcon#ireg 17 cls_cnt 0 2006.145.20:44:07.41#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:44:07.41#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:44:07.41#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:44:07.44#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.20:44:07.48#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:44:07.48#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:44:07.48#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.20:44:07.48#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.20:44:07.48$vck44/vb=1,3 2006.145.20:44:07.48#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.20:44:07.48#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.20:44:07.48#ibcon#ireg 11 cls_cnt 2 2006.145.20:44:07.48#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.20:44:07.48#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.20:44:07.48#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.20:44:07.50#ibcon#[27=AT01-03\r\n] 2006.145.20:44:07.53#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.20:44:07.53#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.20:44:07.53#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.20:44:07.53#ibcon#ireg 7 cls_cnt 0 2006.145.20:44:07.53#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.20:44:07.65#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.20:44:07.65#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.20:44:07.67#ibcon#[27=USB\r\n] 2006.145.20:44:07.70#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.20:44:07.70#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.20:44:07.70#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.20:44:07.70#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.20:44:07.70$vck44/vblo=2,634.99 2006.145.20:44:07.70#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.20:44:07.70#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.20:44:07.70#ibcon#ireg 17 cls_cnt 0 2006.145.20:44:07.70#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:44:07.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:44:07.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:44:07.72#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.20:44:07.76#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:44:07.76#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.20:44:07.76#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.20:44:07.76#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.20:44:07.76$vck44/vb=2,4 2006.145.20:44:07.76#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.20:44:07.76#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.20:44:07.76#ibcon#ireg 11 cls_cnt 2 2006.145.20:44:07.76#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.20:44:07.82#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.20:44:07.82#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.20:44:07.84#ibcon#[27=AT02-04\r\n] 2006.145.20:44:07.87#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.20:44:07.87#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.20:44:07.87#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.20:44:07.87#ibcon#ireg 7 cls_cnt 0 2006.145.20:44:07.87#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.20:44:07.99#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.20:44:07.99#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.20:44:08.01#ibcon#[27=USB\r\n] 2006.145.20:44:08.04#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.20:44:08.04#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.20:44:08.04#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.20:44:08.04#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.20:44:08.04$vck44/vblo=3,649.99 2006.145.20:44:08.04#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.20:44:08.04#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.20:44:08.04#ibcon#ireg 17 cls_cnt 0 2006.145.20:44:08.04#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:44:08.04#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:44:08.04#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:44:08.06#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.20:44:08.10#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:44:08.10#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.20:44:08.10#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.20:44:08.10#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.20:44:08.10$vck44/vb=3,4 2006.145.20:44:08.10#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.20:44:08.10#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.20:44:08.10#ibcon#ireg 11 cls_cnt 2 2006.145.20:44:08.10#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:44:08.16#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:44:08.16#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:44:08.18#ibcon#[27=AT03-04\r\n] 2006.145.20:44:08.21#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:44:08.21#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.20:44:08.21#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.20:44:08.21#ibcon#ireg 7 cls_cnt 0 2006.145.20:44:08.21#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:44:08.33#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:44:08.33#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:44:08.35#ibcon#[27=USB\r\n] 2006.145.20:44:08.38#abcon#<5=/07 1.7 3.9 16.28 861020.0\r\n> 2006.145.20:44:08.38#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:44:08.38#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.20:44:08.38#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.20:44:08.38#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.20:44:08.38$vck44/vblo=4,679.99 2006.145.20:44:08.38#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.20:44:08.38#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.20:44:08.38#ibcon#ireg 17 cls_cnt 0 2006.145.20:44:08.38#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:44:08.38#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:44:08.38#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:44:08.40#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.20:44:08.40#abcon#{5=INTERFACE CLEAR} 2006.145.20:44:08.44#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:44:08.44#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:44:08.44#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.20:44:08.44#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.20:44:08.44$vck44/vb=4,4 2006.145.20:44:08.44#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.20:44:08.44#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.20:44:08.44#ibcon#ireg 11 cls_cnt 2 2006.145.20:44:08.44#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:44:08.46#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:44:08.50#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:44:08.50#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:44:08.52#ibcon#[27=AT04-04\r\n] 2006.145.20:44:08.55#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:44:08.55#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:44:08.55#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.20:44:08.55#ibcon#ireg 7 cls_cnt 0 2006.145.20:44:08.55#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:44:08.67#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:44:08.67#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:44:08.69#ibcon#[27=USB\r\n] 2006.145.20:44:08.72#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:44:08.72#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:44:08.72#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.20:44:08.72#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.20:44:08.72$vck44/vblo=5,709.99 2006.145.20:44:08.72#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.20:44:08.72#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.20:44:08.72#ibcon#ireg 17 cls_cnt 0 2006.145.20:44:08.72#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:44:08.72#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:44:08.72#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:44:08.74#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.20:44:08.78#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:44:08.78#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.20:44:08.78#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.20:44:08.78#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.20:44:08.78$vck44/vb=5,4 2006.145.20:44:08.78#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.20:44:08.78#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.20:44:08.78#ibcon#ireg 11 cls_cnt 2 2006.145.20:44:08.78#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.20:44:08.84#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.20:44:08.84#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.20:44:08.86#ibcon#[27=AT05-04\r\n] 2006.145.20:44:08.89#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.20:44:08.89#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.20:44:08.89#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.20:44:08.89#ibcon#ireg 7 cls_cnt 0 2006.145.20:44:08.89#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.20:44:09.01#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.20:44:09.01#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.20:44:09.03#ibcon#[27=USB\r\n] 2006.145.20:44:09.06#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.20:44:09.06#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.20:44:09.06#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.20:44:09.06#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.20:44:09.06$vck44/vblo=6,719.99 2006.145.20:44:09.06#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.20:44:09.06#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.20:44:09.06#ibcon#ireg 17 cls_cnt 0 2006.145.20:44:09.06#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.20:44:09.06#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.20:44:09.06#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.20:44:09.08#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.20:44:09.12#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.20:44:09.12#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.20:44:09.12#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.20:44:09.12#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.20:44:09.12$vck44/vb=6,4 2006.145.20:44:09.12#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.20:44:09.12#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.20:44:09.12#ibcon#ireg 11 cls_cnt 2 2006.145.20:44:09.12#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.20:44:09.18#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.20:44:09.18#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.20:44:09.20#ibcon#[27=AT06-04\r\n] 2006.145.20:44:09.23#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.20:44:09.23#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.20:44:09.23#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.20:44:09.23#ibcon#ireg 7 cls_cnt 0 2006.145.20:44:09.23#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.20:44:09.35#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.20:44:09.35#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.20:44:09.37#ibcon#[27=USB\r\n] 2006.145.20:44:09.40#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.20:44:09.40#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.20:44:09.40#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.20:44:09.40#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.20:44:09.40$vck44/vblo=7,734.99 2006.145.20:44:09.40#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.20:44:09.40#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.20:44:09.40#ibcon#ireg 17 cls_cnt 0 2006.145.20:44:09.40#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:44:09.40#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:44:09.40#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:44:09.42#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.20:44:09.46#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:44:09.46#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.20:44:09.46#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.20:44:09.46#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.20:44:09.46$vck44/vb=7,4 2006.145.20:44:09.46#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.20:44:09.46#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.20:44:09.46#ibcon#ireg 11 cls_cnt 2 2006.145.20:44:09.46#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:44:09.52#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:44:09.52#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:44:09.54#ibcon#[27=AT07-04\r\n] 2006.145.20:44:09.57#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:44:09.57#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.20:44:09.57#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.20:44:09.57#ibcon#ireg 7 cls_cnt 0 2006.145.20:44:09.57#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:44:09.69#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:44:09.69#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:44:09.71#ibcon#[27=USB\r\n] 2006.145.20:44:09.74#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:44:09.74#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.20:44:09.74#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.20:44:09.74#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.20:44:09.74$vck44/vblo=8,744.99 2006.145.20:44:09.74#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.20:44:09.74#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.20:44:09.74#ibcon#ireg 17 cls_cnt 0 2006.145.20:44:09.74#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:44:09.74#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:44:09.74#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:44:09.76#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.20:44:09.80#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:44:09.80#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:44:09.80#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.20:44:09.80#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.20:44:09.80$vck44/vb=8,4 2006.145.20:44:09.80#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.20:44:09.80#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.20:44:09.80#ibcon#ireg 11 cls_cnt 2 2006.145.20:44:09.80#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:44:09.86#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:44:09.86#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:44:09.88#ibcon#[27=AT08-04\r\n] 2006.145.20:44:09.91#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:44:09.91#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.20:44:09.91#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.20:44:09.91#ibcon#ireg 7 cls_cnt 0 2006.145.20:44:09.91#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:44:10.03#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:44:10.03#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:44:10.05#ibcon#[27=USB\r\n] 2006.145.20:44:10.08#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:44:10.08#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.20:44:10.08#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.20:44:10.08#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.20:44:10.08$vck44/vabw=wide 2006.145.20:44:10.08#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.20:44:10.08#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.20:44:10.08#ibcon#ireg 8 cls_cnt 0 2006.145.20:44:10.08#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:44:10.08#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:44:10.08#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:44:10.10#ibcon#[25=BW32\r\n] 2006.145.20:44:10.13#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:44:10.13#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.20:44:10.13#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.20:44:10.13#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.20:44:10.13$vck44/vbbw=wide 2006.145.20:44:10.13#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.20:44:10.13#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.20:44:10.13#ibcon#ireg 8 cls_cnt 0 2006.145.20:44:10.13#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:44:10.20#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:44:10.20#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:44:10.22#ibcon#[27=BW32\r\n] 2006.145.20:44:10.25#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:44:10.25#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:44:10.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.20:44:10.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.20:44:10.25$setupk4/ifdk4 2006.145.20:44:10.25$ifdk4/lo= 2006.145.20:44:10.25$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.20:44:10.25$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.20:44:10.25$ifdk4/patch= 2006.145.20:44:10.25$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.20:44:10.25$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.20:44:10.25$setupk4/!*+20s 2006.145.20:44:14.14#trakl#Source acquired 2006.145.20:44:14.14#flagr#flagr/antenna,acquired 2006.145.20:44:18.55#abcon#<5=/07 1.6 3.9 16.28 861020.0\r\n> 2006.145.20:44:18.57#abcon#{5=INTERFACE CLEAR} 2006.145.20:44:18.63#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:44:24.68$setupk4/"tpicd 2006.145.20:44:24.68$setupk4/echo=off 2006.145.20:44:24.68$setupk4/xlog=off 2006.145.20:44:24.68:!2006.145.20:44:59 2006.145.20:44:59.00:preob 2006.145.20:45:00.14/onsource/TRACKING 2006.145.20:45:00.14:!2006.145.20:45:09 2006.145.20:45:09.00:"tape 2006.145.20:45:09.00:"st=record 2006.145.20:45:09.00:data_valid=on 2006.145.20:45:09.00:midob 2006.145.20:45:09.14/onsource/TRACKING 2006.145.20:45:09.14/wx/16.30,1020.0,85 2006.145.20:45:09.20/cable/+6.5503E-03 2006.145.20:45:10.29/va/01,08,usb,yes,28,31 2006.145.20:45:10.29/va/02,07,usb,yes,30,31 2006.145.20:45:10.29/va/03,08,usb,yes,28,29 2006.145.20:45:10.29/va/04,07,usb,yes,31,33 2006.145.20:45:10.29/va/05,04,usb,yes,27,28 2006.145.20:45:10.29/va/06,04,usb,yes,31,31 2006.145.20:45:10.29/va/07,04,usb,yes,31,32 2006.145.20:45:10.29/va/08,04,usb,yes,27,32 2006.145.20:45:10.52/valo/01,524.99,yes,locked 2006.145.20:45:10.52/valo/02,534.99,yes,locked 2006.145.20:45:10.52/valo/03,564.99,yes,locked 2006.145.20:45:10.52/valo/04,624.99,yes,locked 2006.145.20:45:10.52/valo/05,734.99,yes,locked 2006.145.20:45:10.52/valo/06,814.99,yes,locked 2006.145.20:45:10.52/valo/07,864.99,yes,locked 2006.145.20:45:10.52/valo/08,884.99,yes,locked 2006.145.20:45:11.61/vb/01,03,usb,yes,36,33 2006.145.20:45:11.61/vb/02,04,usb,yes,31,32 2006.145.20:45:11.61/vb/03,04,usb,yes,28,31 2006.145.20:45:11.61/vb/04,04,usb,yes,33,32 2006.145.20:45:11.61/vb/05,04,usb,yes,25,28 2006.145.20:45:11.61/vb/06,04,usb,yes,30,26 2006.145.20:45:11.61/vb/07,04,usb,yes,29,29 2006.145.20:45:11.61/vb/08,04,usb,yes,27,30 2006.145.20:45:11.84/vblo/01,629.99,yes,locked 2006.145.20:45:11.84/vblo/02,634.99,yes,locked 2006.145.20:45:11.84/vblo/03,649.99,yes,locked 2006.145.20:45:11.84/vblo/04,679.99,yes,locked 2006.145.20:45:11.84/vblo/05,709.99,yes,locked 2006.145.20:45:11.84/vblo/06,719.99,yes,locked 2006.145.20:45:11.84/vblo/07,734.99,yes,locked 2006.145.20:45:11.84/vblo/08,744.99,yes,locked 2006.145.20:45:11.99/vabw/8 2006.145.20:45:12.14/vbbw/8 2006.145.20:45:12.23/xfe/off,on,15.5 2006.145.20:45:12.63/ifatt/23,28,28,28 2006.145.20:45:13.08/fmout-gps/S +4.9E-08 2006.145.20:45:13.12:!2006.145.20:48:09 2006.145.20:48:09.02:data_valid=off 2006.145.20:48:09.02:"et 2006.145.20:48:09.02:!+3s 2006.145.20:48:12.06:"tape 2006.145.20:48:12.06:postob 2006.145.20:48:12.28/cable/+6.5507E-03 2006.145.20:48:12.29/wx/16.34,1020.0,86 2006.145.20:48:12.37/fmout-gps/S +4.7E-08 2006.145.20:48:12.37:scan_name=145-2050,jd0605,40 2006.145.20:48:12.37:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.145.20:48:13.14#flagr#flagr/antenna,new-source 2006.145.20:48:13.14:checkk5 2006.145.20:48:13.57/chk_autoobs//k5ts1/ autoobs is running! 2006.145.20:48:14.00/chk_autoobs//k5ts2/ autoobs is running! 2006.145.20:48:14.42/chk_autoobs//k5ts3/ autoobs is running! 2006.145.20:48:14.86/chk_autoobs//k5ts4/ autoobs is running! 2006.145.20:48:15.29/chk_obsdata//k5ts1/T1452045??a.dat file size is correct (nominal:720MB, actual:716MB). 2006.145.20:48:15.73/chk_obsdata//k5ts2/T1452045??b.dat file size is correct (nominal:720MB, actual:716MB). 2006.145.20:48:16.17/chk_obsdata//k5ts3/T1452045??c.dat file size is correct (nominal:720MB, actual:716MB). 2006.145.20:48:16.60/chk_obsdata//k5ts4/T1452045??d.dat file size is correct (nominal:720MB, actual:716MB). 2006.145.20:48:17.36/k5log//k5ts1_log_newline 2006.145.20:48:18.10/k5log//k5ts2_log_newline 2006.145.20:48:18.85/k5log//k5ts3_log_newline 2006.145.20:48:19.60/k5log//k5ts4_log_newline 2006.145.20:48:19.62/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.20:48:19.62:setupk4=1 2006.145.20:48:19.62$setupk4/echo=on 2006.145.20:48:19.62$setupk4/pcalon 2006.145.20:48:19.63$pcalon/"no phase cal control is implemented here 2006.145.20:48:19.63$setupk4/"tpicd=stop 2006.145.20:48:19.63$setupk4/"rec=synch_on 2006.145.20:48:19.63$setupk4/"rec_mode=128 2006.145.20:48:19.63$setupk4/!* 2006.145.20:48:19.63$setupk4/recpk4 2006.145.20:48:19.63$recpk4/recpatch= 2006.145.20:48:19.63$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.20:48:19.63$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.20:48:19.63$setupk4/vck44 2006.145.20:48:19.63$vck44/valo=1,524.99 2006.145.20:48:19.63#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.20:48:19.63#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.20:48:19.63#ibcon#ireg 17 cls_cnt 0 2006.145.20:48:19.63#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:48:19.63#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:48:19.63#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:48:19.67#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.20:48:19.71#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:48:19.71#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:48:19.71#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.20:48:19.71#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.20:48:19.72$vck44/va=1,8 2006.145.20:48:19.72#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.20:48:19.72#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.20:48:19.72#ibcon#ireg 11 cls_cnt 2 2006.145.20:48:19.72#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:48:19.72#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:48:19.72#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:48:19.74#ibcon#[25=AT01-08\r\n] 2006.145.20:48:19.76#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:48:19.76#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:48:19.76#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.20:48:19.76#ibcon#ireg 7 cls_cnt 0 2006.145.20:48:19.76#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:48:19.88#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:48:19.88#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:48:19.90#ibcon#[25=USB\r\n] 2006.145.20:48:19.93#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:48:19.93#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:48:19.93#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.20:48:19.93#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.20:48:19.94$vck44/valo=2,534.99 2006.145.20:48:19.94#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.20:48:19.94#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.20:48:19.94#ibcon#ireg 17 cls_cnt 0 2006.145.20:48:19.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:48:19.94#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:48:19.94#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:48:19.97#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.20:48:20.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:48:20.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.20:48:20.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.20:48:20.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.20:48:20.01$vck44/va=2,7 2006.145.20:48:20.01#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.20:48:20.01#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.20:48:20.01#ibcon#ireg 11 cls_cnt 2 2006.145.20:48:20.01#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.20:48:20.04#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.20:48:20.04#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.20:48:20.06#ibcon#[25=AT02-07\r\n] 2006.145.20:48:20.09#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.20:48:20.09#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.20:48:20.09#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.20:48:20.09#ibcon#ireg 7 cls_cnt 0 2006.145.20:48:20.09#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.20:48:20.21#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.20:48:20.21#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.20:48:20.23#ibcon#[25=USB\r\n] 2006.145.20:48:20.26#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.20:48:20.26#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.20:48:20.26#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.20:48:20.26#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.20:48:20.27$vck44/valo=3,564.99 2006.145.20:48:20.27#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.20:48:20.27#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.20:48:20.27#ibcon#ireg 17 cls_cnt 0 2006.145.20:48:20.27#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.20:48:20.27#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.20:48:20.27#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.20:48:20.28#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.20:48:20.32#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.20:48:20.32#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.20:48:20.32#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.20:48:20.32#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.20:48:20.33$vck44/va=3,8 2006.145.20:48:20.33#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.20:48:20.33#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.20:48:20.33#ibcon#ireg 11 cls_cnt 2 2006.145.20:48:20.33#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.20:48:20.37#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.20:48:20.37#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.20:48:20.39#ibcon#[25=AT03-08\r\n] 2006.145.20:48:20.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.20:48:20.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.20:48:20.42#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.20:48:20.42#ibcon#ireg 7 cls_cnt 0 2006.145.20:48:20.42#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.20:48:20.54#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.20:48:20.54#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.20:48:20.56#ibcon#[25=USB\r\n] 2006.145.20:48:20.59#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.20:48:20.59#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.20:48:20.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.20:48:20.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.20:48:20.60$vck44/valo=4,624.99 2006.145.20:48:20.60#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.20:48:20.60#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.20:48:20.60#ibcon#ireg 17 cls_cnt 0 2006.145.20:48:20.60#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:48:20.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:48:20.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:48:20.61#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.20:48:20.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:48:20.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:48:20.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.20:48:20.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.20:48:20.66$vck44/va=4,7 2006.145.20:48:20.66#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.20:48:20.66#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.20:48:20.66#ibcon#ireg 11 cls_cnt 2 2006.145.20:48:20.66#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.20:48:20.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.20:48:20.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.20:48:20.72#ibcon#[25=AT04-07\r\n] 2006.145.20:48:20.75#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.20:48:20.75#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.20:48:20.75#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.20:48:20.75#ibcon#ireg 7 cls_cnt 0 2006.145.20:48:20.75#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.20:48:20.88#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.20:48:20.88#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.20:48:20.89#ibcon#[25=USB\r\n] 2006.145.20:48:20.92#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.20:48:20.92#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.20:48:20.92#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.20:48:20.92#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.20:48:20.93$vck44/valo=5,734.99 2006.145.20:48:20.93#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.20:48:20.93#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.20:48:20.93#ibcon#ireg 17 cls_cnt 0 2006.145.20:48:20.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.20:48:20.93#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.20:48:20.93#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.20:48:20.94#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.20:48:20.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.20:48:20.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.20:48:20.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.20:48:20.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.20:48:20.99$vck44/va=5,4 2006.145.20:48:20.99#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.20:48:20.99#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.20:48:20.99#ibcon#ireg 11 cls_cnt 2 2006.145.20:48:20.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.20:48:21.03#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.20:48:21.03#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.20:48:21.05#ibcon#[25=AT05-04\r\n] 2006.145.20:48:21.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.20:48:21.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.20:48:21.09#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.20:48:21.09#ibcon#ireg 7 cls_cnt 0 2006.145.20:48:21.09#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.20:48:21.20#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.20:48:21.20#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.20:48:21.22#ibcon#[25=USB\r\n] 2006.145.20:48:21.25#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.20:48:21.25#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.20:48:21.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.20:48:21.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.20:48:21.26$vck44/valo=6,814.99 2006.145.20:48:21.26#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.20:48:21.26#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.20:48:21.26#ibcon#ireg 17 cls_cnt 0 2006.145.20:48:21.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:48:21.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:48:21.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:48:21.27#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.20:48:21.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:48:21.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:48:21.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.20:48:21.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.20:48:21.32$vck44/va=6,4 2006.145.20:48:21.32#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.20:48:21.32#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.20:48:21.32#ibcon#ireg 11 cls_cnt 2 2006.145.20:48:21.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:48:21.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:48:21.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:48:21.38#ibcon#[25=AT06-04\r\n] 2006.145.20:48:21.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:48:21.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:48:21.41#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.20:48:21.41#ibcon#ireg 7 cls_cnt 0 2006.145.20:48:21.41#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:48:21.53#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:48:21.53#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:48:21.55#ibcon#[25=USB\r\n] 2006.145.20:48:21.58#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:48:21.58#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:48:21.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.20:48:21.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.20:48:21.59$vck44/valo=7,864.99 2006.145.20:48:21.59#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.20:48:21.59#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.20:48:21.59#ibcon#ireg 17 cls_cnt 0 2006.145.20:48:21.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:48:21.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:48:21.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:48:21.60#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.20:48:21.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:48:21.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:48:21.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.20:48:21.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.20:48:21.65$vck44/va=7,4 2006.145.20:48:21.65#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.20:48:21.65#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.20:48:21.65#ibcon#ireg 11 cls_cnt 2 2006.145.20:48:21.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:48:21.69#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:48:21.69#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:48:21.71#ibcon#[25=AT07-04\r\n] 2006.145.20:48:21.74#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:48:21.74#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:48:21.74#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.20:48:21.74#ibcon#ireg 7 cls_cnt 0 2006.145.20:48:21.74#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:48:21.86#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:48:21.86#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:48:21.88#ibcon#[25=USB\r\n] 2006.145.20:48:21.91#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:48:21.91#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:48:21.91#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.20:48:21.91#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.20:48:21.92$vck44/valo=8,884.99 2006.145.20:48:21.92#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.20:48:21.92#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.20:48:21.92#ibcon#ireg 17 cls_cnt 0 2006.145.20:48:21.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:48:21.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:48:21.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:48:21.93#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.20:48:21.97#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:48:21.97#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:48:21.97#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.20:48:21.97#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.20:48:21.98$vck44/va=8,4 2006.145.20:48:21.98#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.20:48:21.98#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.20:48:21.98#ibcon#ireg 11 cls_cnt 2 2006.145.20:48:21.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:48:22.02#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:48:22.02#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:48:22.04#ibcon#[25=AT08-04\r\n] 2006.145.20:48:22.07#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:48:22.07#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:48:22.07#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.20:48:22.07#ibcon#ireg 7 cls_cnt 0 2006.145.20:48:22.07#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:48:22.19#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:48:22.19#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:48:22.21#ibcon#[25=USB\r\n] 2006.145.20:48:22.24#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:48:22.24#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:48:22.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.20:48:22.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.20:48:22.25$vck44/vblo=1,629.99 2006.145.20:48:22.25#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.20:48:22.25#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.20:48:22.25#ibcon#ireg 17 cls_cnt 0 2006.145.20:48:22.25#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:48:22.25#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:48:22.25#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:48:22.26#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.20:48:22.30#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:48:22.30#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:48:22.30#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.20:48:22.30#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.20:48:22.31$vck44/vb=1,3 2006.145.20:48:22.31#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.20:48:22.31#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.20:48:22.31#ibcon#ireg 11 cls_cnt 2 2006.145.20:48:22.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.20:48:22.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.20:48:22.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.20:48:22.32#ibcon#[27=AT01-03\r\n] 2006.145.20:48:22.35#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.20:48:22.35#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.20:48:22.35#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.20:48:22.35#ibcon#ireg 7 cls_cnt 0 2006.145.20:48:22.35#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.20:48:22.47#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.20:48:22.47#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.20:48:22.49#ibcon#[27=USB\r\n] 2006.145.20:48:22.52#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.20:48:22.52#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.20:48:22.52#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.20:48:22.52#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.20:48:22.53$vck44/vblo=2,634.99 2006.145.20:48:22.53#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.20:48:22.53#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.20:48:22.53#ibcon#ireg 17 cls_cnt 0 2006.145.20:48:22.53#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:48:22.53#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:48:22.53#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:48:22.54#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.20:48:22.58#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:48:22.58#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.20:48:22.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.20:48:22.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.20:48:22.59$vck44/vb=2,4 2006.145.20:48:22.59#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.20:48:22.59#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.20:48:22.59#ibcon#ireg 11 cls_cnt 2 2006.145.20:48:22.59#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:48:22.63#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:48:22.63#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:48:22.65#ibcon#[27=AT02-04\r\n] 2006.145.20:48:22.68#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:48:22.68#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.20:48:22.68#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.20:48:22.68#ibcon#ireg 7 cls_cnt 0 2006.145.20:48:22.68#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:48:22.80#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:48:22.80#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:48:22.82#ibcon#[27=USB\r\n] 2006.145.20:48:22.83#abcon#<5=/07 1.8 3.9 16.35 861020.0\r\n> 2006.145.20:48:22.85#abcon#{5=INTERFACE CLEAR} 2006.145.20:48:22.85#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:48:22.85#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.20:48:22.85#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.20:48:22.85#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.20:48:22.86$vck44/vblo=3,649.99 2006.145.20:48:22.86#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.20:48:22.86#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.20:48:22.86#ibcon#ireg 17 cls_cnt 0 2006.145.20:48:22.86#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:48:22.86#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:48:22.86#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:48:22.87#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.20:48:22.91#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:48:22.91#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:48:22.91#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:48:22.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.20:48:22.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.20:48:22.92$vck44/vb=3,4 2006.145.20:48:22.92#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.20:48:22.92#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.20:48:22.92#ibcon#ireg 11 cls_cnt 2 2006.145.20:48:22.92#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.20:48:22.96#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.20:48:22.96#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.20:48:22.98#ibcon#[27=AT03-04\r\n] 2006.145.20:48:23.01#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.20:48:23.01#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.20:48:23.01#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.20:48:23.01#ibcon#ireg 7 cls_cnt 0 2006.145.20:48:23.01#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.20:48:23.14#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.20:48:23.14#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.20:48:23.15#ibcon#[27=USB\r\n] 2006.145.20:48:23.18#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.20:48:23.18#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.20:48:23.18#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.20:48:23.18#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.20:48:23.19$vck44/vblo=4,679.99 2006.145.20:48:23.19#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.20:48:23.19#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.20:48:23.19#ibcon#ireg 17 cls_cnt 0 2006.145.20:48:23.19#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:48:23.19#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:48:23.19#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:48:23.20#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.20:48:23.24#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:48:23.24#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:48:23.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.20:48:23.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.20:48:23.25$vck44/vb=4,4 2006.145.20:48:23.25#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.20:48:23.25#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.20:48:23.25#ibcon#ireg 11 cls_cnt 2 2006.145.20:48:23.25#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.20:48:23.29#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.20:48:23.29#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.20:48:23.31#ibcon#[27=AT04-04\r\n] 2006.145.20:48:23.34#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.20:48:23.34#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.20:48:23.34#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.20:48:23.34#ibcon#ireg 7 cls_cnt 0 2006.145.20:48:23.34#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.20:48:23.46#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.20:48:23.46#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.20:48:23.48#ibcon#[27=USB\r\n] 2006.145.20:48:23.51#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.20:48:23.51#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.20:48:23.51#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.20:48:23.51#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.20:48:23.52$vck44/vblo=5,709.99 2006.145.20:48:23.52#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.20:48:23.52#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.20:48:23.52#ibcon#ireg 17 cls_cnt 0 2006.145.20:48:23.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.20:48:23.52#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.20:48:23.52#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.20:48:23.53#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.20:48:23.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.20:48:23.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.20:48:23.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.20:48:23.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.20:48:23.58$vck44/vb=5,4 2006.145.20:48:23.58#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.20:48:23.58#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.20:48:23.58#ibcon#ireg 11 cls_cnt 2 2006.145.20:48:23.58#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.20:48:23.62#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.20:48:23.62#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.20:48:23.64#ibcon#[27=AT05-04\r\n] 2006.145.20:48:23.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.20:48:23.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.20:48:23.67#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.20:48:23.67#ibcon#ireg 7 cls_cnt 0 2006.145.20:48:23.67#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.20:48:23.79#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.20:48:23.79#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.20:48:23.81#ibcon#[27=USB\r\n] 2006.145.20:48:23.84#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.20:48:23.84#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.20:48:23.84#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.20:48:23.84#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.20:48:23.85$vck44/vblo=6,719.99 2006.145.20:48:23.85#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.20:48:23.85#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.20:48:23.85#ibcon#ireg 17 cls_cnt 0 2006.145.20:48:23.85#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:48:23.85#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:48:23.85#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:48:23.86#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.20:48:23.90#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:48:23.90#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.20:48:23.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.20:48:23.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.20:48:23.91$vck44/vb=6,4 2006.145.20:48:23.91#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.20:48:23.91#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.20:48:23.91#ibcon#ireg 11 cls_cnt 2 2006.145.20:48:23.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:48:23.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:48:23.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:48:23.97#ibcon#[27=AT06-04\r\n] 2006.145.20:48:24.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:48:24.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.20:48:24.00#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.20:48:24.00#ibcon#ireg 7 cls_cnt 0 2006.145.20:48:24.00#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:48:24.12#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:48:24.12#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:48:24.14#ibcon#[27=USB\r\n] 2006.145.20:48:24.17#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:48:24.17#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.20:48:24.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.20:48:24.17#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.20:48:24.18$vck44/vblo=7,734.99 2006.145.20:48:24.18#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.20:48:24.18#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.20:48:24.18#ibcon#ireg 17 cls_cnt 0 2006.145.20:48:24.18#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:48:24.18#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:48:24.18#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:48:24.19#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.20:48:24.23#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:48:24.23#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.20:48:24.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.20:48:24.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.20:48:24.24$vck44/vb=7,4 2006.145.20:48:24.24#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.20:48:24.24#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.20:48:24.24#ibcon#ireg 11 cls_cnt 2 2006.145.20:48:24.24#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:48:24.28#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:48:24.28#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:48:24.30#ibcon#[27=AT07-04\r\n] 2006.145.20:48:24.33#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:48:24.33#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.20:48:24.33#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.20:48:24.33#ibcon#ireg 7 cls_cnt 0 2006.145.20:48:24.33#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:48:24.45#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:48:24.45#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:48:24.47#ibcon#[27=USB\r\n] 2006.145.20:48:24.50#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:48:24.50#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.20:48:24.50#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.20:48:24.50#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.20:48:24.51$vck44/vblo=8,744.99 2006.145.20:48:24.51#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.20:48:24.51#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.20:48:24.51#ibcon#ireg 17 cls_cnt 0 2006.145.20:48:24.51#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:48:24.51#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:48:24.51#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:48:24.52#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.20:48:24.56#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:48:24.56#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.20:48:24.56#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.20:48:24.56#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.20:48:24.57$vck44/vb=8,4 2006.145.20:48:24.57#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.20:48:24.57#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.20:48:24.57#ibcon#ireg 11 cls_cnt 2 2006.145.20:48:24.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:48:24.61#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:48:24.61#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:48:24.63#ibcon#[27=AT08-04\r\n] 2006.145.20:48:24.66#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:48:24.66#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.20:48:24.66#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.20:48:24.66#ibcon#ireg 7 cls_cnt 0 2006.145.20:48:24.66#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:48:24.78#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:48:24.78#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:48:24.80#ibcon#[27=USB\r\n] 2006.145.20:48:24.83#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:48:24.83#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.20:48:24.83#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.20:48:24.83#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.20:48:24.84$vck44/vabw=wide 2006.145.20:48:24.84#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.20:48:24.84#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.20:48:24.84#ibcon#ireg 8 cls_cnt 0 2006.145.20:48:24.84#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:48:24.84#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:48:24.84#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:48:24.85#ibcon#[25=BW32\r\n] 2006.145.20:48:24.88#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:48:24.88#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.20:48:24.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.20:48:24.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.20:48:24.89$vck44/vbbw=wide 2006.145.20:48:24.89#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.20:48:24.89#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.20:48:24.89#ibcon#ireg 8 cls_cnt 0 2006.145.20:48:24.89#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:48:24.95#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:48:24.95#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:48:24.96#ibcon#[27=BW32\r\n] 2006.145.20:48:24.99#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:48:24.99#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:48:24.99#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.20:48:24.99#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.20:48:25.00$setupk4/ifdk4 2006.145.20:48:25.00$ifdk4/lo= 2006.145.20:48:25.00$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.20:48:25.00$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.20:48:25.00$ifdk4/patch= 2006.145.20:48:25.00$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.20:48:25.00$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.20:48:25.00$setupk4/!*+20s 2006.145.20:48:33.00#abcon#<5=/07 1.9 3.9 16.35 861020.1\r\n> 2006.145.20:48:33.02#abcon#{5=INTERFACE CLEAR} 2006.145.20:48:33.08#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:48:39.65$setupk4/"tpicd 2006.145.20:48:39.65$setupk4/echo=off 2006.145.20:48:39.65$setupk4/xlog=off 2006.145.20:48:39.66:!2006.145.20:50:38 2006.145.20:48:46.13#trakl#Source acquired 2006.145.20:48:48.14#flagr#flagr/antenna,acquired 2006.145.20:50:38.01:preob 2006.145.20:50:39.14/onsource/TRACKING 2006.145.20:50:39.15:!2006.145.20:50:48 2006.145.20:50:48.01:"tape 2006.145.20:50:48.01:"st=record 2006.145.20:50:48.01:data_valid=on 2006.145.20:50:48.02:midob 2006.145.20:50:49.14/onsource/TRACKING 2006.145.20:50:49.15/wx/16.38,1020.1,87 2006.145.20:50:49.27/cable/+6.5520E-03 2006.145.20:50:50.36/va/01,08,usb,yes,32,34 2006.145.20:50:50.36/va/02,07,usb,yes,34,35 2006.145.20:50:50.36/va/03,08,usb,yes,31,32 2006.145.20:50:50.36/va/04,07,usb,yes,35,37 2006.145.20:50:50.36/va/05,04,usb,yes,31,31 2006.145.20:50:50.36/va/06,04,usb,yes,34,34 2006.145.20:50:50.36/va/07,04,usb,yes,35,36 2006.145.20:50:50.36/va/08,04,usb,yes,30,35 2006.145.20:50:50.59/valo/01,524.99,yes,locked 2006.145.20:50:50.59/valo/02,534.99,yes,locked 2006.145.20:50:50.59/valo/03,564.99,yes,locked 2006.145.20:50:50.59/valo/04,624.99,yes,locked 2006.145.20:50:50.59/valo/05,734.99,yes,locked 2006.145.20:50:50.59/valo/06,814.99,yes,locked 2006.145.20:50:50.59/valo/07,864.99,yes,locked 2006.145.20:50:50.59/valo/08,884.99,yes,locked 2006.145.20:50:51.68/vb/01,03,usb,yes,37,35 2006.145.20:50:51.68/vb/02,04,usb,yes,33,32 2006.145.20:50:51.68/vb/03,04,usb,yes,29,33 2006.145.20:50:51.68/vb/04,04,usb,yes,34,33 2006.145.20:50:51.68/vb/05,04,usb,yes,26,29 2006.145.20:50:51.68/vb/06,04,usb,yes,31,27 2006.145.20:50:51.68/vb/07,04,usb,yes,31,30 2006.145.20:50:51.68/vb/08,04,usb,yes,28,31 2006.145.20:50:51.91/vblo/01,629.99,yes,locked 2006.145.20:50:51.91/vblo/02,634.99,yes,locked 2006.145.20:50:51.91/vblo/03,649.99,yes,locked 2006.145.20:50:51.91/vblo/04,679.99,yes,locked 2006.145.20:50:51.91/vblo/05,709.99,yes,locked 2006.145.20:50:51.91/vblo/06,719.99,yes,locked 2006.145.20:50:51.91/vblo/07,734.99,yes,locked 2006.145.20:50:51.91/vblo/08,744.99,yes,locked 2006.145.20:50:52.06/vabw/8 2006.145.20:50:52.21/vbbw/8 2006.145.20:50:52.30/xfe/off,on,15.2 2006.145.20:50:52.68/ifatt/23,28,28,28 2006.145.20:50:53.07/fmout-gps/S +4.6E-08 2006.145.20:50:53.12:!2006.145.20:51:28 2006.145.20:51:28.01:data_valid=off 2006.145.20:51:28.02:"et 2006.145.20:51:28.02:!+3s 2006.145.20:51:31.05:"tape 2006.145.20:51:31.09:postob 2006.145.20:51:31.27/cable/+6.5502E-03 2006.145.20:51:31.28/wx/16.39,1020.1,87 2006.145.20:51:31.37/fmout-gps/S +4.6E-08 2006.145.20:51:31.37:scan_name=145-2052,jd0605,120 2006.145.20:51:31.38:source=1908-201,191109.65,-200655.1,2000.0,cw 2006.145.20:51:32.14#flagr#flagr/antenna,new-source 2006.145.20:51:32.15:checkk5 2006.145.20:51:32.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.20:51:33.04/chk_autoobs//k5ts2/ autoobs is running! 2006.145.20:51:33.48/chk_autoobs//k5ts3/ autoobs is running! 2006.145.20:51:33.92/chk_autoobs//k5ts4/ autoobs is running! 2006.145.20:51:34.36/chk_obsdata//k5ts1/T1452050??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.20:51:34.79/chk_obsdata//k5ts2/T1452050??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.20:51:35.22/chk_obsdata//k5ts3/T1452050??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.20:51:35.67/chk_obsdata//k5ts4/T1452050??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.20:51:36.45/k5log//k5ts1_log_newline 2006.145.20:51:37.18/k5log//k5ts2_log_newline 2006.145.20:51:37.93/k5log//k5ts3_log_newline 2006.145.20:51:38.67/k5log//k5ts4_log_newline 2006.145.20:51:38.69/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.20:51:38.69:setupk4=1 2006.145.20:51:38.69$setupk4/echo=on 2006.145.20:51:38.69$setupk4/pcalon 2006.145.20:51:38.69$pcalon/"no phase cal control is implemented here 2006.145.20:51:38.70$setupk4/"tpicd=stop 2006.145.20:51:38.70$setupk4/"rec=synch_on 2006.145.20:51:38.70$setupk4/"rec_mode=128 2006.145.20:51:38.70$setupk4/!* 2006.145.20:51:38.70$setupk4/recpk4 2006.145.20:51:38.70$recpk4/recpatch= 2006.145.20:51:38.70$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.20:51:38.70$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.20:51:38.70$setupk4/vck44 2006.145.20:51:38.70$vck44/valo=1,524.99 2006.145.20:51:38.70#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.20:51:38.70#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.20:51:38.70#ibcon#ireg 17 cls_cnt 0 2006.145.20:51:38.70#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:51:38.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:51:38.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:51:38.74#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.20:51:38.78#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:51:38.78#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:51:38.78#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.20:51:38.78#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.20:51:38.78$vck44/va=1,8 2006.145.20:51:38.78#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.20:51:38.78#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.20:51:38.78#ibcon#ireg 11 cls_cnt 2 2006.145.20:51:38.78#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:51:38.78#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:51:38.78#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:51:38.80#ibcon#[25=AT01-08\r\n] 2006.145.20:51:38.83#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:51:38.83#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:51:38.83#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.20:51:38.83#ibcon#ireg 7 cls_cnt 0 2006.145.20:51:38.83#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:51:38.96#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:51:38.96#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:51:38.97#ibcon#[25=USB\r\n] 2006.145.20:51:39.00#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:51:39.00#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:51:39.00#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.20:51:39.00#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.20:51:39.00$vck44/valo=2,534.99 2006.145.20:51:39.00#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.20:51:39.00#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.20:51:39.00#ibcon#ireg 17 cls_cnt 0 2006.145.20:51:39.00#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:51:39.00#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:51:39.00#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:51:39.04#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.20:51:39.07#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:51:39.07#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:51:39.07#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.20:51:39.07#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.20:51:39.07$vck44/va=2,7 2006.145.20:51:39.07#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.20:51:39.07#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.20:51:39.07#ibcon#ireg 11 cls_cnt 2 2006.145.20:51:39.07#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:51:39.12#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:51:39.12#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:51:39.14#ibcon#[25=AT02-07\r\n] 2006.145.20:51:39.17#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:51:39.17#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:51:39.17#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.20:51:39.17#ibcon#ireg 7 cls_cnt 0 2006.145.20:51:39.17#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:51:39.29#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:51:39.29#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:51:39.31#ibcon#[25=USB\r\n] 2006.145.20:51:39.34#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:51:39.34#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:51:39.34#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.20:51:39.34#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.20:51:39.34$vck44/valo=3,564.99 2006.145.20:51:39.34#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.20:51:39.34#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.20:51:39.34#ibcon#ireg 17 cls_cnt 0 2006.145.20:51:39.34#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:51:39.34#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:51:39.34#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:51:39.36#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.20:51:39.40#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:51:39.40#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:51:39.40#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.20:51:39.40#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.20:51:39.40$vck44/va=3,8 2006.145.20:51:39.40#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.20:51:39.40#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.20:51:39.40#ibcon#ireg 11 cls_cnt 2 2006.145.20:51:39.40#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.20:51:39.46#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.20:51:39.46#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.20:51:39.48#ibcon#[25=AT03-08\r\n] 2006.145.20:51:39.51#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.20:51:39.51#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.20:51:39.51#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.20:51:39.51#ibcon#ireg 7 cls_cnt 0 2006.145.20:51:39.51#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.20:51:39.63#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.20:51:39.63#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.20:51:39.65#ibcon#[25=USB\r\n] 2006.145.20:51:39.68#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.20:51:39.68#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.20:51:39.68#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.20:51:39.68#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.20:51:39.68$vck44/valo=4,624.99 2006.145.20:51:39.68#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.20:51:39.68#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.20:51:39.68#ibcon#ireg 17 cls_cnt 0 2006.145.20:51:39.68#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.20:51:39.68#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.20:51:39.68#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.20:51:39.70#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.20:51:39.74#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.20:51:39.74#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.20:51:39.74#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.20:51:39.74#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.20:51:39.74$vck44/va=4,7 2006.145.20:51:39.74#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.20:51:39.74#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.20:51:39.74#ibcon#ireg 11 cls_cnt 2 2006.145.20:51:39.74#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.20:51:39.80#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.20:51:39.80#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.20:51:39.82#ibcon#[25=AT04-07\r\n] 2006.145.20:51:39.85#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.20:51:39.85#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.20:51:39.85#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.20:51:39.85#ibcon#ireg 7 cls_cnt 0 2006.145.20:51:39.85#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.20:51:39.97#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.20:51:39.97#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.20:51:39.99#ibcon#[25=USB\r\n] 2006.145.20:51:40.02#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.20:51:40.02#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.20:51:40.02#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.20:51:40.02#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.20:51:40.02$vck44/valo=5,734.99 2006.145.20:51:40.02#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.20:51:40.02#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.20:51:40.02#ibcon#ireg 17 cls_cnt 0 2006.145.20:51:40.02#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:51:40.02#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:51:40.02#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:51:40.04#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.20:51:40.08#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:51:40.08#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:51:40.08#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.20:51:40.08#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.20:51:40.08$vck44/va=5,4 2006.145.20:51:40.08#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.20:51:40.08#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.20:51:40.08#ibcon#ireg 11 cls_cnt 2 2006.145.20:51:40.08#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.20:51:40.14#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.20:51:40.14#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.20:51:40.16#ibcon#[25=AT05-04\r\n] 2006.145.20:51:40.20#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.20:51:40.20#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.20:51:40.20#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.20:51:40.20#ibcon#ireg 7 cls_cnt 0 2006.145.20:51:40.20#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.20:51:40.31#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.20:51:40.31#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.20:51:40.33#ibcon#[25=USB\r\n] 2006.145.20:51:40.36#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.20:51:40.36#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.20:51:40.36#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.20:51:40.36#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.20:51:40.36$vck44/valo=6,814.99 2006.145.20:51:40.36#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.20:51:40.36#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.20:51:40.36#ibcon#ireg 17 cls_cnt 0 2006.145.20:51:40.36#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:51:40.36#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:51:40.36#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:51:40.38#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.20:51:40.42#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:51:40.42#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:51:40.42#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.20:51:40.42#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.20:51:40.42$vck44/va=6,4 2006.145.20:51:40.42#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.20:51:40.42#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.20:51:40.42#ibcon#ireg 11 cls_cnt 2 2006.145.20:51:40.42#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:51:40.48#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:51:40.48#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:51:40.50#ibcon#[25=AT06-04\r\n] 2006.145.20:51:40.53#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:51:40.53#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:51:40.53#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.20:51:40.53#ibcon#ireg 7 cls_cnt 0 2006.145.20:51:40.53#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:51:40.65#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:51:40.65#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:51:40.67#ibcon#[25=USB\r\n] 2006.145.20:51:40.70#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:51:40.70#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:51:40.70#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.20:51:40.70#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.20:51:40.70$vck44/valo=7,864.99 2006.145.20:51:40.70#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.20:51:40.70#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.20:51:40.70#ibcon#ireg 17 cls_cnt 0 2006.145.20:51:40.70#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:51:40.70#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:51:40.70#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:51:40.72#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.20:51:40.76#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:51:40.76#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:51:40.76#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.20:51:40.76#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.20:51:40.76$vck44/va=7,4 2006.145.20:51:40.76#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.20:51:40.76#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.20:51:40.76#ibcon#ireg 11 cls_cnt 2 2006.145.20:51:40.76#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:51:40.82#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:51:40.82#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:51:40.84#ibcon#[25=AT07-04\r\n] 2006.145.20:51:40.87#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:51:40.87#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:51:40.87#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.20:51:40.87#ibcon#ireg 7 cls_cnt 0 2006.145.20:51:40.87#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:51:40.99#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:51:40.99#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:51:41.01#ibcon#[25=USB\r\n] 2006.145.20:51:41.04#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:51:41.04#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:51:41.04#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.20:51:41.04#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.20:51:41.04$vck44/valo=8,884.99 2006.145.20:51:41.04#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.20:51:41.04#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.20:51:41.04#ibcon#ireg 17 cls_cnt 0 2006.145.20:51:41.04#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.20:51:41.04#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.20:51:41.04#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.20:51:41.06#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.20:51:41.10#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.20:51:41.10#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.20:51:41.10#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.20:51:41.10#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.20:51:41.10$vck44/va=8,4 2006.145.20:51:41.10#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.20:51:41.10#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.20:51:41.10#ibcon#ireg 11 cls_cnt 2 2006.145.20:51:41.10#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.20:51:41.16#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.20:51:41.16#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.20:51:41.18#ibcon#[25=AT08-04\r\n] 2006.145.20:51:41.21#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.20:51:41.21#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.20:51:41.21#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.20:51:41.21#ibcon#ireg 7 cls_cnt 0 2006.145.20:51:41.21#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.20:51:41.33#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.20:51:41.33#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.20:51:41.35#ibcon#[25=USB\r\n] 2006.145.20:51:41.39#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.20:51:41.39#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.20:51:41.39#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.20:51:41.39#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.20:51:41.39$vck44/vblo=1,629.99 2006.145.20:51:41.39#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.20:51:41.39#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.20:51:41.39#ibcon#ireg 17 cls_cnt 0 2006.145.20:51:41.39#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.20:51:41.39#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.20:51:41.39#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.20:51:41.40#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.20:51:41.44#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.20:51:41.44#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.20:51:41.44#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.20:51:41.44#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.20:51:41.44$vck44/vb=1,3 2006.145.20:51:41.44#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.20:51:41.44#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.20:51:41.44#ibcon#ireg 11 cls_cnt 2 2006.145.20:51:41.44#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.20:51:41.44#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.20:51:41.44#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.20:51:41.46#ibcon#[27=AT01-03\r\n] 2006.145.20:51:41.50#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.20:51:41.50#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.20:51:41.50#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.20:51:41.50#ibcon#ireg 7 cls_cnt 0 2006.145.20:51:41.50#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.20:51:41.61#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.20:51:41.61#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.20:51:41.63#ibcon#[27=USB\r\n] 2006.145.20:51:41.66#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.20:51:41.66#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.20:51:41.66#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.20:51:41.66#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.20:51:41.66$vck44/vblo=2,634.99 2006.145.20:51:41.66#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.20:51:41.66#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.20:51:41.66#ibcon#ireg 17 cls_cnt 0 2006.145.20:51:41.66#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:51:41.66#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:51:41.66#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:51:41.69#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.20:51:41.73#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:51:41.73#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.20:51:41.73#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.20:51:41.73#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.20:51:41.73$vck44/vb=2,4 2006.145.20:51:41.73#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.20:51:41.73#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.20:51:41.73#ibcon#ireg 11 cls_cnt 2 2006.145.20:51:41.73#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:51:41.78#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:51:41.78#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:51:41.80#ibcon#[27=AT02-04\r\n] 2006.145.20:51:41.83#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:51:41.83#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.20:51:41.83#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.20:51:41.83#ibcon#ireg 7 cls_cnt 0 2006.145.20:51:41.83#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:51:41.95#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:51:41.95#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:51:41.97#ibcon#[27=USB\r\n] 2006.145.20:51:42.00#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:51:42.00#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.20:51:42.00#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.20:51:42.00#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.20:51:42.00$vck44/vblo=3,649.99 2006.145.20:51:42.00#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.20:51:42.00#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.20:51:42.00#ibcon#ireg 17 cls_cnt 0 2006.145.20:51:42.00#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:51:42.00#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:51:42.00#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:51:42.02#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.20:51:42.06#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:51:42.06#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.20:51:42.06#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.20:51:42.06#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.20:51:42.06$vck44/vb=3,4 2006.145.20:51:42.06#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.20:51:42.06#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.20:51:42.06#ibcon#ireg 11 cls_cnt 2 2006.145.20:51:42.06#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:51:42.12#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:51:42.12#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:51:42.14#ibcon#[27=AT03-04\r\n] 2006.145.20:51:42.17#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:51:42.17#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.20:51:42.17#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.20:51:42.17#ibcon#ireg 7 cls_cnt 0 2006.145.20:51:42.17#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:51:42.29#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:51:42.29#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:51:42.31#ibcon#[27=USB\r\n] 2006.145.20:51:42.34#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:51:42.34#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.20:51:42.34#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.20:51:42.34#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.20:51:42.34$vck44/vblo=4,679.99 2006.145.20:51:42.34#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.20:51:42.34#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.20:51:42.34#ibcon#ireg 17 cls_cnt 0 2006.145.20:51:42.34#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:51:42.34#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:51:42.34#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:51:42.36#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.20:51:42.40#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:51:42.40#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.20:51:42.40#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.20:51:42.40#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.20:51:42.40$vck44/vb=4,4 2006.145.20:51:42.40#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.20:51:42.40#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.20:51:42.40#ibcon#ireg 11 cls_cnt 2 2006.145.20:51:42.40#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.20:51:42.46#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.20:51:42.46#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.20:51:42.48#ibcon#[27=AT04-04\r\n] 2006.145.20:51:42.51#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.20:51:42.51#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.20:51:42.51#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.20:51:42.51#ibcon#ireg 7 cls_cnt 0 2006.145.20:51:42.51#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.20:51:42.63#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.20:51:42.63#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.20:51:42.65#ibcon#[27=USB\r\n] 2006.145.20:51:42.68#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.20:51:42.68#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.20:51:42.68#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.20:51:42.68#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.20:51:42.68$vck44/vblo=5,709.99 2006.145.20:51:42.68#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.20:51:42.68#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.20:51:42.68#ibcon#ireg 17 cls_cnt 0 2006.145.20:51:42.68#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.20:51:42.68#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.20:51:42.68#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.20:51:42.70#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.20:51:42.74#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.20:51:42.74#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.20:51:42.74#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.20:51:42.74#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.20:51:42.74$vck44/vb=5,4 2006.145.20:51:42.74#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.20:51:42.74#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.20:51:42.74#ibcon#ireg 11 cls_cnt 2 2006.145.20:51:42.74#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.20:51:42.80#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.20:51:42.80#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.20:51:42.82#ibcon#[27=AT05-04\r\n] 2006.145.20:51:42.85#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.20:51:42.85#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.20:51:42.85#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.20:51:42.85#ibcon#ireg 7 cls_cnt 0 2006.145.20:51:42.85#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.20:51:42.97#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.20:51:42.97#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.20:51:42.99#ibcon#[27=USB\r\n] 2006.145.20:51:43.02#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.20:51:43.02#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.20:51:43.02#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.20:51:43.02#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.20:51:43.02$vck44/vblo=6,719.99 2006.145.20:51:43.02#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.20:51:43.02#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.20:51:43.02#ibcon#ireg 17 cls_cnt 0 2006.145.20:51:43.02#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:51:43.02#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:51:43.02#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:51:43.04#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.20:51:43.08#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:51:43.08#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.20:51:43.08#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.20:51:43.08#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.20:51:43.08$vck44/vb=6,4 2006.145.20:51:43.08#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.20:51:43.08#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.20:51:43.08#ibcon#ireg 11 cls_cnt 2 2006.145.20:51:43.08#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.20:51:43.14#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.20:51:43.14#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.20:51:43.16#ibcon#[27=AT06-04\r\n] 2006.145.20:51:43.19#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.20:51:43.19#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.20:51:43.19#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.20:51:43.19#ibcon#ireg 7 cls_cnt 0 2006.145.20:51:43.19#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.20:51:43.31#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.20:51:43.31#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.20:51:43.33#ibcon#[27=USB\r\n] 2006.145.20:51:43.36#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.20:51:43.36#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.20:51:43.36#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.20:51:43.36#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.20:51:43.36$vck44/vblo=7,734.99 2006.145.20:51:43.36#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.20:51:43.36#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.20:51:43.36#ibcon#ireg 17 cls_cnt 0 2006.145.20:51:43.36#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:51:43.36#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:51:43.36#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:51:43.38#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.20:51:43.42#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:51:43.42#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.20:51:43.42#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.20:51:43.42#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.20:51:43.42$vck44/vb=7,4 2006.145.20:51:43.42#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.20:51:43.42#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.20:51:43.42#ibcon#ireg 11 cls_cnt 2 2006.145.20:51:43.42#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:51:43.48#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:51:43.48#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:51:43.50#ibcon#[27=AT07-04\r\n] 2006.145.20:51:43.53#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:51:43.53#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.20:51:43.53#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.20:51:43.53#ibcon#ireg 7 cls_cnt 0 2006.145.20:51:43.53#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:51:43.65#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:51:43.65#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:51:43.67#ibcon#[27=USB\r\n] 2006.145.20:51:43.70#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:51:43.70#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.20:51:43.70#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.20:51:43.70#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.20:51:43.70$vck44/vblo=8,744.99 2006.145.20:51:43.70#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.20:51:43.70#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.20:51:43.70#ibcon#ireg 17 cls_cnt 0 2006.145.20:51:43.70#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:51:43.70#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:51:43.70#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:51:43.72#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.20:51:43.76#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:51:43.76#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.20:51:43.76#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.20:51:43.76#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.20:51:43.76$vck44/vb=8,4 2006.145.20:51:43.76#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.20:51:43.76#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.20:51:43.76#ibcon#ireg 11 cls_cnt 2 2006.145.20:51:43.76#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:51:43.82#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:51:43.82#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:51:43.84#ibcon#[27=AT08-04\r\n] 2006.145.20:51:43.87#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:51:43.87#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.20:51:43.87#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.20:51:43.87#ibcon#ireg 7 cls_cnt 0 2006.145.20:51:43.87#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:51:43.99#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:51:43.99#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:51:44.01#ibcon#[27=USB\r\n] 2006.145.20:51:44.04#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:51:44.04#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.20:51:44.04#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.20:51:44.04#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.20:51:44.04$vck44/vabw=wide 2006.145.20:51:44.04#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.20:51:44.04#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.20:51:44.04#ibcon#ireg 8 cls_cnt 0 2006.145.20:51:44.04#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.20:51:44.04#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.20:51:44.04#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.20:51:44.06#ibcon#[25=BW32\r\n] 2006.145.20:51:44.09#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.20:51:44.09#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.20:51:44.09#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.20:51:44.09#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.20:51:44.09$vck44/vbbw=wide 2006.145.20:51:44.09#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.20:51:44.09#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.20:51:44.09#ibcon#ireg 8 cls_cnt 0 2006.145.20:51:44.09#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:51:44.16#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:51:44.16#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:51:44.18#ibcon#[27=BW32\r\n] 2006.145.20:51:44.21#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:51:44.21#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.20:51:44.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.20:51:44.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.20:51:44.21$setupk4/ifdk4 2006.145.20:51:44.21$ifdk4/lo= 2006.145.20:51:44.21$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.20:51:44.21$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.20:51:44.22$ifdk4/patch= 2006.145.20:51:44.22$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.20:51:44.22$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.20:51:44.22$setupk4/!*+20s 2006.145.20:51:46.32#abcon#<5=/07 1.9 3.9 16.40 871020.1\r\n> 2006.145.20:51:46.34#abcon#{5=INTERFACE CLEAR} 2006.145.20:51:46.40#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:51:50.14#trakl#Source acquired 2006.145.20:51:52.14#flagr#flagr/antenna,acquired 2006.145.20:51:56.49#abcon#<5=/07 1.9 3.9 16.40 871020.1\r\n> 2006.145.20:51:56.51#abcon#{5=INTERFACE CLEAR} 2006.145.20:51:56.57#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:51:58.72$setupk4/"tpicd 2006.145.20:51:58.72$setupk4/echo=off 2006.145.20:51:58.72$setupk4/xlog=off 2006.145.20:51:58.72:!2006.145.20:52:44 2006.145.20:52:44.00:preob 2006.145.20:52:44.14/onsource/TRACKING 2006.145.20:52:44.14:!2006.145.20:52:54 2006.145.20:52:54.00:"tape 2006.145.20:52:54.00:"st=record 2006.145.20:52:54.00:data_valid=on 2006.145.20:52:54.00:midob 2006.145.20:52:55.14/onsource/TRACKING 2006.145.20:52:55.14/wx/16.43,1020.1,86 2006.145.20:52:55.20/cable/+6.5522E-03 2006.145.20:52:56.29/va/01,08,usb,yes,30,33 2006.145.20:52:56.29/va/02,07,usb,yes,33,33 2006.145.20:52:56.29/va/03,08,usb,yes,30,31 2006.145.20:52:56.29/va/04,07,usb,yes,34,35 2006.145.20:52:56.29/va/05,04,usb,yes,29,30 2006.145.20:52:56.29/va/06,04,usb,yes,33,33 2006.145.20:52:56.29/va/07,04,usb,yes,33,35 2006.145.20:52:56.29/va/08,04,usb,yes,28,34 2006.145.20:52:56.52/valo/01,524.99,yes,locked 2006.145.20:52:56.52/valo/02,534.99,yes,locked 2006.145.20:52:56.52/valo/03,564.99,yes,locked 2006.145.20:52:56.52/valo/04,624.99,yes,locked 2006.145.20:52:56.52/valo/05,734.99,yes,locked 2006.145.20:52:56.52/valo/06,814.99,yes,locked 2006.145.20:52:56.52/valo/07,864.99,yes,locked 2006.145.20:52:56.52/valo/08,884.99,yes,locked 2006.145.20:52:57.61/vb/01,03,usb,yes,37,35 2006.145.20:52:57.61/vb/02,04,usb,yes,33,33 2006.145.20:52:57.61/vb/03,04,usb,yes,30,33 2006.145.20:52:57.61/vb/04,04,usb,yes,34,33 2006.145.20:52:57.61/vb/05,04,usb,yes,26,29 2006.145.20:52:57.61/vb/06,04,usb,yes,31,27 2006.145.20:52:57.61/vb/07,04,usb,yes,31,30 2006.145.20:52:57.61/vb/08,04,usb,yes,28,31 2006.145.20:52:57.85/vblo/01,629.99,yes,locked 2006.145.20:52:57.85/vblo/02,634.99,yes,locked 2006.145.20:52:57.85/vblo/03,649.99,yes,locked 2006.145.20:52:57.85/vblo/04,679.99,yes,locked 2006.145.20:52:57.85/vblo/05,709.99,yes,locked 2006.145.20:52:57.85/vblo/06,719.99,yes,locked 2006.145.20:52:57.85/vblo/07,734.99,yes,locked 2006.145.20:52:57.85/vblo/08,744.99,yes,locked 2006.145.20:52:58.00/vabw/8 2006.145.20:52:58.15/vbbw/8 2006.145.20:52:58.24/xfe/off,on,15.2 2006.145.20:52:58.64/ifatt/23,28,28,28 2006.145.20:52:59.07/fmout-gps/S +4.5E-08 2006.145.20:52:59.12:!2006.145.20:54:54 2006.145.20:54:54.01:data_valid=off 2006.145.20:54:54.02:"et 2006.145.20:54:54.02:!+3s 2006.145.20:54:57.05:"tape 2006.145.20:54:57.09:postob 2006.145.20:54:57.24/cable/+6.5522E-03 2006.145.20:54:57.25/wx/16.47,1020.1,86 2006.145.20:54:57.33/fmout-gps/S +4.6E-08 2006.145.20:54:57.33:scan_name=145-2100,jd0605,70 2006.145.20:54:57.33:source=2136+141,213901.31,142336.0,2000.0,cw 2006.145.20:54:58.14#flagr#flagr/antenna,new-source 2006.145.20:54:58.15:checkk5 2006.145.20:54:58.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.20:54:59.04/chk_autoobs//k5ts2/ autoobs is running! 2006.145.20:54:59.51/chk_autoobs//k5ts3/ autoobs is running! 2006.145.20:54:59.94/chk_autoobs//k5ts4/ autoobs is running! 2006.145.20:55:00.36/chk_obsdata//k5ts1/T1452052??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.20:55:00.79/chk_obsdata//k5ts2/T1452052??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.20:55:01.23/chk_obsdata//k5ts3/T1452052??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.20:55:01.67/chk_obsdata//k5ts4/T1452052??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.20:55:02.42/k5log//k5ts1_log_newline 2006.145.20:55:03.16/k5log//k5ts2_log_newline 2006.145.20:55:03.91/k5log//k5ts3_log_newline 2006.145.20:55:04.65/k5log//k5ts4_log_newline 2006.145.20:55:04.68/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.20:55:04.68:setupk4=1 2006.145.20:55:04.68$setupk4/echo=on 2006.145.20:55:04.68$setupk4/pcalon 2006.145.20:55:04.68$pcalon/"no phase cal control is implemented here 2006.145.20:55:04.68$setupk4/"tpicd=stop 2006.145.20:55:04.68$setupk4/"rec=synch_on 2006.145.20:55:04.68$setupk4/"rec_mode=128 2006.145.20:55:04.68$setupk4/!* 2006.145.20:55:04.68$setupk4/recpk4 2006.145.20:55:04.68$recpk4/recpatch= 2006.145.20:55:04.68$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.20:55:04.68$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.20:55:04.68$setupk4/vck44 2006.145.20:55:04.68$vck44/valo=1,524.99 2006.145.20:55:04.68#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.20:55:04.68#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.20:55:04.68#ibcon#ireg 17 cls_cnt 0 2006.145.20:55:04.68#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:55:04.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:55:04.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:55:04.69#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.20:55:04.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:55:04.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:55:04.74#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.20:55:04.74#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.20:55:04.74$vck44/va=1,8 2006.145.20:55:04.74#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.20:55:04.74#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.20:55:04.74#ibcon#ireg 11 cls_cnt 2 2006.145.20:55:04.74#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:55:04.74#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:55:04.74#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:55:04.76#ibcon#[25=AT01-08\r\n] 2006.145.20:55:04.79#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:55:04.79#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:55:04.79#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.20:55:04.79#ibcon#ireg 7 cls_cnt 0 2006.145.20:55:04.79#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:55:04.91#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:55:04.91#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:55:04.93#ibcon#[25=USB\r\n] 2006.145.20:55:04.96#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:55:04.96#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:55:04.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.20:55:04.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.20:55:04.96$vck44/valo=2,534.99 2006.145.20:55:04.96#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.20:55:04.96#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.20:55:04.96#ibcon#ireg 17 cls_cnt 0 2006.145.20:55:04.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:55:04.96#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:55:04.96#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:55:05.00#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.20:55:05.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:55:05.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:55:05.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.20:55:05.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.20:55:05.03$vck44/va=2,7 2006.145.20:55:05.03#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.20:55:05.03#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.20:55:05.03#ibcon#ireg 11 cls_cnt 2 2006.145.20:55:05.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:55:05.09#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:55:05.09#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:55:05.10#ibcon#[25=AT02-07\r\n] 2006.145.20:55:05.13#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:55:05.13#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:55:05.13#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.20:55:05.13#ibcon#ireg 7 cls_cnt 0 2006.145.20:55:05.13#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:55:05.25#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:55:05.25#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:55:05.27#ibcon#[25=USB\r\n] 2006.145.20:55:05.30#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:55:05.30#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:55:05.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.20:55:05.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.20:55:05.30$vck44/valo=3,564.99 2006.145.20:55:05.30#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.20:55:05.30#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.20:55:05.30#ibcon#ireg 17 cls_cnt 0 2006.145.20:55:05.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:55:05.30#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:55:05.30#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:55:05.32#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.20:55:05.36#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:55:05.36#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:55:05.36#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.20:55:05.36#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.20:55:05.36$vck44/va=3,8 2006.145.20:55:05.36#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.20:55:05.36#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.20:55:05.36#ibcon#ireg 11 cls_cnt 2 2006.145.20:55:05.36#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:55:05.42#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:55:05.42#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:55:05.44#ibcon#[25=AT03-08\r\n] 2006.145.20:55:05.47#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:55:05.47#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:55:05.47#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.20:55:05.47#ibcon#ireg 7 cls_cnt 0 2006.145.20:55:05.47#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:55:05.59#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:55:05.59#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:55:05.61#ibcon#[25=USB\r\n] 2006.145.20:55:05.64#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:55:05.64#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:55:05.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.20:55:05.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.20:55:05.64$vck44/valo=4,624.99 2006.145.20:55:05.64#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.20:55:05.64#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.20:55:05.64#ibcon#ireg 17 cls_cnt 0 2006.145.20:55:05.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:55:05.64#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:55:05.64#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:55:05.66#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.20:55:05.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:55:05.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:55:05.70#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.20:55:05.70#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.20:55:05.70$vck44/va=4,7 2006.145.20:55:05.70#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.20:55:05.70#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.20:55:05.70#ibcon#ireg 11 cls_cnt 2 2006.145.20:55:05.70#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:55:05.76#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:55:05.76#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:55:05.78#ibcon#[25=AT04-07\r\n] 2006.145.20:55:05.81#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:55:05.81#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:55:05.81#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.20:55:05.81#ibcon#ireg 7 cls_cnt 0 2006.145.20:55:05.81#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:55:05.93#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:55:05.93#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:55:05.95#ibcon#[25=USB\r\n] 2006.145.20:55:05.98#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:55:05.98#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:55:05.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.20:55:05.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.20:55:05.98$vck44/valo=5,734.99 2006.145.20:55:05.98#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.20:55:05.98#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.20:55:05.98#ibcon#ireg 17 cls_cnt 0 2006.145.20:55:05.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:55:05.98#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:55:05.98#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:55:06.00#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.20:55:06.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:55:06.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:55:06.04#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.20:55:06.04#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.20:55:06.04$vck44/va=5,4 2006.145.20:55:06.04#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.20:55:06.04#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.20:55:06.04#ibcon#ireg 11 cls_cnt 2 2006.145.20:55:06.04#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:55:06.10#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:55:06.10#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:55:06.12#ibcon#[25=AT05-04\r\n] 2006.145.20:55:06.15#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:55:06.15#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:55:06.15#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.20:55:06.15#ibcon#ireg 7 cls_cnt 0 2006.145.20:55:06.15#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:55:06.27#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:55:06.27#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:55:06.31#ibcon#[25=USB\r\n] 2006.145.20:55:06.33#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:55:06.33#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:55:06.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.20:55:06.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.20:55:06.33$vck44/valo=6,814.99 2006.145.20:55:06.33#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.20:55:06.33#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.20:55:06.33#ibcon#ireg 17 cls_cnt 0 2006.145.20:55:06.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:55:06.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:55:06.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:55:06.35#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.20:55:06.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:55:06.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:55:06.39#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.20:55:06.39#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.20:55:06.40$vck44/va=6,4 2006.145.20:55:06.40#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.20:55:06.40#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.20:55:06.40#ibcon#ireg 11 cls_cnt 2 2006.145.20:55:06.40#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:55:06.44#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:55:06.44#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:55:06.46#ibcon#[25=AT06-04\r\n] 2006.145.20:55:06.49#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:55:06.49#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:55:06.49#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.20:55:06.49#ibcon#ireg 7 cls_cnt 0 2006.145.20:55:06.49#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:55:06.61#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:55:06.61#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:55:06.63#ibcon#[25=USB\r\n] 2006.145.20:55:06.66#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:55:06.66#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:55:06.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.20:55:06.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.20:55:06.66$vck44/valo=7,864.99 2006.145.20:55:06.66#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.20:55:06.66#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.20:55:06.66#ibcon#ireg 17 cls_cnt 0 2006.145.20:55:06.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:55:06.66#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:55:06.66#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:55:06.68#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.20:55:06.72#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:55:06.72#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:55:06.72#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.20:55:06.72#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.20:55:06.72$vck44/va=7,4 2006.145.20:55:06.72#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.20:55:06.72#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.20:55:06.72#ibcon#ireg 11 cls_cnt 2 2006.145.20:55:06.72#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:55:06.78#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:55:06.78#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:55:06.80#ibcon#[25=AT07-04\r\n] 2006.145.20:55:06.83#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:55:06.83#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.20:55:06.83#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.20:55:06.83#ibcon#ireg 7 cls_cnt 0 2006.145.20:55:06.83#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:55:06.95#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:55:06.95#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:55:06.97#ibcon#[25=USB\r\n] 2006.145.20:55:07.00#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:55:07.00#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.20:55:07.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.20:55:07.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.20:55:07.00$vck44/valo=8,884.99 2006.145.20:55:07.00#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.20:55:07.00#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.20:55:07.00#ibcon#ireg 17 cls_cnt 0 2006.145.20:55:07.00#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.20:55:07.00#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.20:55:07.00#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.20:55:07.02#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.20:55:07.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.20:55:07.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.20:55:07.06#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.20:55:07.06#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.20:55:07.06$vck44/va=8,4 2006.145.20:55:07.06#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.20:55:07.06#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.20:55:07.06#ibcon#ireg 11 cls_cnt 2 2006.145.20:55:07.06#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.20:55:07.12#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.20:55:07.12#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.20:55:07.14#ibcon#[25=AT08-04\r\n] 2006.145.20:55:07.17#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.20:55:07.17#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.20:55:07.17#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.20:55:07.17#ibcon#ireg 7 cls_cnt 0 2006.145.20:55:07.17#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.20:55:07.29#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.20:55:07.29#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.20:55:07.31#ibcon#[25=USB\r\n] 2006.145.20:55:07.34#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.20:55:07.34#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.20:55:07.34#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.20:55:07.34#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.20:55:07.34$vck44/vblo=1,629.99 2006.145.20:55:07.34#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.20:55:07.34#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.20:55:07.34#ibcon#ireg 17 cls_cnt 0 2006.145.20:55:07.34#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:55:07.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:55:07.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:55:07.36#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.20:55:07.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:55:07.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:55:07.40#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.20:55:07.40#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.20:55:07.40$vck44/vb=1,3 2006.145.20:55:07.40#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.20:55:07.40#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.20:55:07.40#ibcon#ireg 11 cls_cnt 2 2006.145.20:55:07.40#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:55:07.40#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:55:07.40#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:55:07.42#ibcon#[27=AT01-03\r\n] 2006.145.20:55:07.45#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:55:07.45#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.20:55:07.45#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.20:55:07.45#ibcon#ireg 7 cls_cnt 0 2006.145.20:55:07.45#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:55:07.58#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:55:07.58#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:55:07.59#ibcon#[27=USB\r\n] 2006.145.20:55:07.62#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:55:07.62#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.20:55:07.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.20:55:07.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.20:55:07.62$vck44/vblo=2,634.99 2006.145.20:55:07.62#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.20:55:07.62#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.20:55:07.62#ibcon#ireg 17 cls_cnt 0 2006.145.20:55:07.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:55:07.62#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:55:07.62#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:55:07.64#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.20:55:07.68#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:55:07.68#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.20:55:07.68#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.20:55:07.68#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.20:55:07.68$vck44/vb=2,4 2006.145.20:55:07.68#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.20:55:07.68#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.20:55:07.68#ibcon#ireg 11 cls_cnt 2 2006.145.20:55:07.68#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:55:07.74#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:55:07.74#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:55:07.76#ibcon#[27=AT02-04\r\n] 2006.145.20:55:07.79#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:55:07.79#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.20:55:07.79#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.20:55:07.79#ibcon#ireg 7 cls_cnt 0 2006.145.20:55:07.79#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:55:07.91#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:55:07.91#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:55:07.93#ibcon#[27=USB\r\n] 2006.145.20:55:07.96#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:55:07.96#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.20:55:07.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.20:55:07.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.20:55:07.96$vck44/vblo=3,649.99 2006.145.20:55:07.96#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.20:55:07.96#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.20:55:07.96#ibcon#ireg 17 cls_cnt 0 2006.145.20:55:07.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:55:07.96#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:55:07.96#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:55:07.98#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.20:55:08.02#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:55:08.02#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.20:55:08.02#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.20:55:08.02#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.20:55:08.02$vck44/vb=3,4 2006.145.20:55:08.02#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.20:55:08.02#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.20:55:08.02#ibcon#ireg 11 cls_cnt 2 2006.145.20:55:08.02#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:55:08.08#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:55:08.08#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:55:08.10#ibcon#[27=AT03-04\r\n] 2006.145.20:55:08.13#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:55:08.13#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.20:55:08.13#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.20:55:08.13#ibcon#ireg 7 cls_cnt 0 2006.145.20:55:08.13#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:55:08.25#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:55:08.25#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:55:08.27#ibcon#[27=USB\r\n] 2006.145.20:55:08.30#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:55:08.30#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.20:55:08.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.20:55:08.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.20:55:08.30$vck44/vblo=4,679.99 2006.145.20:55:08.30#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.20:55:08.30#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.20:55:08.30#ibcon#ireg 17 cls_cnt 0 2006.145.20:55:08.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:55:08.30#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:55:08.30#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:55:08.32#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.20:55:08.36#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:55:08.36#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.20:55:08.36#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.20:55:08.36#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.20:55:08.36$vck44/vb=4,4 2006.145.20:55:08.36#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.20:55:08.36#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.20:55:08.36#ibcon#ireg 11 cls_cnt 2 2006.145.20:55:08.36#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:55:08.42#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:55:08.42#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:55:08.44#ibcon#[27=AT04-04\r\n] 2006.145.20:55:08.47#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:55:08.47#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.20:55:08.47#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.20:55:08.47#ibcon#ireg 7 cls_cnt 0 2006.145.20:55:08.47#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:55:08.59#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:55:08.59#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:55:08.61#ibcon#[27=USB\r\n] 2006.145.20:55:08.64#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:55:08.64#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.20:55:08.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.20:55:08.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.20:55:08.64$vck44/vblo=5,709.99 2006.145.20:55:08.64#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.20:55:08.64#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.20:55:08.64#ibcon#ireg 17 cls_cnt 0 2006.145.20:55:08.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:55:08.64#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:55:08.64#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:55:08.66#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.20:55:08.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:55:08.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.20:55:08.70#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.20:55:08.70#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.20:55:08.70$vck44/vb=5,4 2006.145.20:55:08.70#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.20:55:08.70#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.20:55:08.70#ibcon#ireg 11 cls_cnt 2 2006.145.20:55:08.70#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:55:08.76#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:55:08.76#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:55:08.78#ibcon#[27=AT05-04\r\n] 2006.145.20:55:08.81#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:55:08.81#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.20:55:08.81#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.20:55:08.81#ibcon#ireg 7 cls_cnt 0 2006.145.20:55:08.81#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:55:08.93#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:55:08.93#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:55:08.95#ibcon#[27=USB\r\n] 2006.145.20:55:08.98#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:55:08.98#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.20:55:08.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.20:55:08.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.20:55:08.98$vck44/vblo=6,719.99 2006.145.20:55:08.98#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.20:55:08.98#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.20:55:08.98#ibcon#ireg 17 cls_cnt 0 2006.145.20:55:08.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:55:08.98#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:55:08.98#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:55:09.00#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.20:55:09.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:55:09.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.20:55:09.04#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.20:55:09.04#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.20:55:09.04$vck44/vb=6,4 2006.145.20:55:09.04#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.20:55:09.04#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.20:55:09.04#ibcon#ireg 11 cls_cnt 2 2006.145.20:55:09.04#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:55:09.10#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:55:09.10#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:55:09.12#ibcon#[27=AT06-04\r\n] 2006.145.20:55:09.15#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:55:09.15#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.20:55:09.15#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.20:55:09.15#ibcon#ireg 7 cls_cnt 0 2006.145.20:55:09.15#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:55:09.27#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:55:09.27#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:55:09.29#ibcon#[27=USB\r\n] 2006.145.20:55:09.32#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:55:09.32#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.20:55:09.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.20:55:09.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.20:55:09.32$vck44/vblo=7,734.99 2006.145.20:55:09.32#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.20:55:09.32#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.20:55:09.32#ibcon#ireg 17 cls_cnt 0 2006.145.20:55:09.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:55:09.32#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:55:09.32#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:55:09.34#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.20:55:09.38#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:55:09.38#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.20:55:09.38#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.20:55:09.38#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.20:55:09.38$vck44/vb=7,4 2006.145.20:55:09.38#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.20:55:09.38#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.20:55:09.38#ibcon#ireg 11 cls_cnt 2 2006.145.20:55:09.38#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:55:09.44#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:55:09.44#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:55:09.46#ibcon#[27=AT07-04\r\n] 2006.145.20:55:09.49#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:55:09.49#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.20:55:09.49#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.20:55:09.49#ibcon#ireg 7 cls_cnt 0 2006.145.20:55:09.49#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:55:09.61#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:55:09.61#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:55:09.63#ibcon#[27=USB\r\n] 2006.145.20:55:09.66#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:55:09.66#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.20:55:09.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.20:55:09.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.20:55:09.66$vck44/vblo=8,744.99 2006.145.20:55:09.66#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.20:55:09.66#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.20:55:09.66#ibcon#ireg 17 cls_cnt 0 2006.145.20:55:09.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:55:09.66#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:55:09.66#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:55:09.68#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.20:55:09.72#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:55:09.72#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.20:55:09.72#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.20:55:09.72#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.20:55:09.72$vck44/vb=8,4 2006.145.20:55:09.72#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.20:55:09.72#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.20:55:09.72#ibcon#ireg 11 cls_cnt 2 2006.145.20:55:09.72#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.20:55:09.74#abcon#<5=/07 1.7 3.6 16.48 861020.1\r\n> 2006.145.20:55:09.76#abcon#{5=INTERFACE CLEAR} 2006.145.20:55:09.78#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.20:55:09.78#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.20:55:09.80#ibcon#[27=AT08-04\r\n] 2006.145.20:55:09.82#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:55:09.83#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.20:55:09.83#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.20:55:09.83#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.20:55:09.83#ibcon#ireg 7 cls_cnt 0 2006.145.20:55:09.83#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.20:55:09.95#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.20:55:09.95#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.20:55:09.97#ibcon#[27=USB\r\n] 2006.145.20:55:10.00#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.20:55:10.00#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.20:55:10.00#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.20:55:10.00#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.20:55:10.00$vck44/vabw=wide 2006.145.20:55:10.00#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.20:55:10.00#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.20:55:10.00#ibcon#ireg 8 cls_cnt 0 2006.145.20:55:10.00#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:55:10.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:55:10.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:55:10.02#ibcon#[25=BW32\r\n] 2006.145.20:55:10.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:55:10.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.20:55:10.05#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.20:55:10.05#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.20:55:10.05$vck44/vbbw=wide 2006.145.20:55:10.05#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.20:55:10.05#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.20:55:10.05#ibcon#ireg 8 cls_cnt 0 2006.145.20:55:10.05#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:55:10.12#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:55:10.12#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:55:10.14#ibcon#[27=BW32\r\n] 2006.145.20:55:10.17#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:55:10.17#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.20:55:10.17#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.20:55:10.17#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.20:55:10.17$setupk4/ifdk4 2006.145.20:55:10.17$ifdk4/lo= 2006.145.20:55:10.17$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.20:55:10.17$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.20:55:10.17$ifdk4/patch= 2006.145.20:55:10.17$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.20:55:10.17$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.20:55:10.17$setupk4/!*+20s 2006.145.20:55:19.91#abcon#<5=/07 1.7 3.6 16.48 861020.2\r\n> 2006.145.20:55:19.93#abcon#{5=INTERFACE CLEAR} 2006.145.20:55:20.01#abcon#[5=S1D000X0/0*\r\n] 2006.145.20:55:24.14#trakl#Source acquired 2006.145.20:55:24.14#flagr#flagr/antenna,acquired 2006.145.20:55:24.69$setupk4/"tpicd 2006.145.20:55:24.69$setupk4/echo=off 2006.145.20:55:24.69$setupk4/xlog=off 2006.145.20:55:24.69:!2006.145.20:59:50 2006.145.20:59:50.00:preob 2006.145.20:59:50.14/onsource/TRACKING 2006.145.20:59:50.14:!2006.145.21:00:00 2006.145.21:00:00.00:"tape 2006.145.21:00:00.00:"st=record 2006.145.21:00:00.00:data_valid=on 2006.145.21:00:00.00:midob 2006.145.21:00:00.14/onsource/TRACKING 2006.145.21:00:00.14/wx/16.63,1020.1,85 2006.145.21:00:00.21/cable/+6.5496E-03 2006.145.21:00:01.30/va/01,08,usb,yes,28,30 2006.145.21:00:01.30/va/02,07,usb,yes,30,30 2006.145.21:00:01.30/va/03,08,usb,yes,27,28 2006.145.21:00:01.30/va/04,07,usb,yes,31,32 2006.145.21:00:01.30/va/05,04,usb,yes,27,27 2006.145.21:00:01.30/va/06,04,usb,yes,30,30 2006.145.21:00:01.30/va/07,04,usb,yes,30,32 2006.145.21:00:01.30/va/08,04,usb,yes,26,31 2006.145.21:00:01.53/valo/01,524.99,yes,locked 2006.145.21:00:01.53/valo/02,534.99,yes,locked 2006.145.21:00:01.53/valo/03,564.99,yes,locked 2006.145.21:00:01.53/valo/04,624.99,yes,locked 2006.145.21:00:01.53/valo/05,734.99,yes,locked 2006.145.21:00:01.53/valo/06,814.99,yes,locked 2006.145.21:00:01.53/valo/07,864.99,yes,locked 2006.145.21:00:01.53/valo/08,884.99,yes,locked 2006.145.21:00:02.62/vb/01,03,usb,yes,35,33 2006.145.21:00:02.62/vb/02,04,usb,yes,31,31 2006.145.21:00:02.62/vb/03,04,usb,yes,28,31 2006.145.21:00:02.62/vb/04,04,usb,yes,32,31 2006.145.21:00:02.62/vb/05,04,usb,yes,25,27 2006.145.21:00:02.62/vb/06,04,usb,yes,29,25 2006.145.21:00:02.62/vb/07,04,usb,yes,29,29 2006.145.21:00:02.62/vb/08,04,usb,yes,27,30 2006.145.21:00:02.85/vblo/01,629.99,yes,locked 2006.145.21:00:02.85/vblo/02,634.99,yes,locked 2006.145.21:00:02.85/vblo/03,649.99,yes,locked 2006.145.21:00:02.85/vblo/04,679.99,yes,locked 2006.145.21:00:02.85/vblo/05,709.99,yes,locked 2006.145.21:00:02.85/vblo/06,719.99,yes,locked 2006.145.21:00:02.85/vblo/07,734.99,yes,locked 2006.145.21:00:02.85/vblo/08,744.99,yes,locked 2006.145.21:00:03.00/vabw/8 2006.145.21:00:03.15/vbbw/8 2006.145.21:00:03.24/xfe/off,on,15.2 2006.145.21:00:03.64/ifatt/23,28,28,28 2006.145.21:00:04.07/fmout-gps/S +4.4E-08 2006.145.21:00:04.11:!2006.145.21:01:10 2006.145.21:01:10.00:data_valid=off 2006.145.21:01:10.01:"et 2006.145.21:01:10.01:!+3s 2006.145.21:01:13.02:"tape 2006.145.21:01:13.03:postob 2006.145.21:01:13.09/cable/+6.5507E-03 2006.145.21:01:13.10/wx/16.65,1020.2,85 2006.145.21:01:13.18/fmout-gps/S +4.3E-08 2006.145.21:01:13.18:scan_name=145-2104,jd0605,40 2006.145.21:01:13.18:source=1954-388,195800.00,-384506.4,2000.0,cw 2006.145.21:01:15.14#flagr#flagr/antenna,new-source 2006.145.21:01:15.15:checkk5 2006.145.21:01:15.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.21:01:16.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.21:01:16.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.21:01:16.92/chk_autoobs//k5ts4/ autoobs is running! 2006.145.21:01:17.34/chk_obsdata//k5ts1/T1452100??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.21:01:17.78/chk_obsdata//k5ts2/T1452100??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.21:01:18.24/chk_obsdata//k5ts3/T1452100??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.21:01:18.68/chk_obsdata//k5ts4/T1452100??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.21:01:19.45/k5log//k5ts1_log_newline 2006.145.21:01:20.20/k5log//k5ts2_log_newline 2006.145.21:01:20.93/k5log//k5ts3_log_newline 2006.145.21:01:21.68/k5log//k5ts4_log_newline 2006.145.21:01:21.71/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.21:01:21.71:setupk4=1 2006.145.21:01:21.71$setupk4/echo=on 2006.145.21:01:21.71$setupk4/pcalon 2006.145.21:01:21.71$pcalon/"no phase cal control is implemented here 2006.145.21:01:21.71$setupk4/"tpicd=stop 2006.145.21:01:21.71$setupk4/"rec=synch_on 2006.145.21:01:21.71$setupk4/"rec_mode=128 2006.145.21:01:21.71$setupk4/!* 2006.145.21:01:21.71$setupk4/recpk4 2006.145.21:01:21.71$recpk4/recpatch= 2006.145.21:01:21.71$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.21:01:21.71$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.21:01:21.72$setupk4/vck44 2006.145.21:01:21.72$vck44/valo=1,524.99 2006.145.21:01:21.72#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.21:01:21.72#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.21:01:21.72#ibcon#ireg 17 cls_cnt 0 2006.145.21:01:21.72#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:01:21.72#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:01:21.72#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:01:21.75#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.21:01:21.80#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:01:21.80#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:01:21.80#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.21:01:21.80#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.21:01:21.80$vck44/va=1,8 2006.145.21:01:21.80#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.21:01:21.80#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.21:01:21.80#ibcon#ireg 11 cls_cnt 2 2006.145.21:01:21.80#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.21:01:21.80#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.21:01:21.80#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.21:01:21.82#ibcon#[25=AT01-08\r\n] 2006.145.21:01:21.85#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.21:01:21.85#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.21:01:21.85#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.21:01:21.85#ibcon#ireg 7 cls_cnt 0 2006.145.21:01:21.85#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.21:01:21.97#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.21:01:21.97#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.21:01:21.99#ibcon#[25=USB\r\n] 2006.145.21:01:22.04#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.21:01:22.04#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.21:01:22.04#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.21:01:22.04#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.21:01:22.04$vck44/valo=2,534.99 2006.145.21:01:22.04#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.21:01:22.04#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.21:01:22.04#ibcon#ireg 17 cls_cnt 0 2006.145.21:01:22.04#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.21:01:22.04#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.21:01:22.04#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.21:01:22.06#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.21:01:22.10#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.21:01:22.10#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.21:01:22.10#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.21:01:22.10#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.21:01:22.10$vck44/va=2,7 2006.145.21:01:22.10#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.21:01:22.10#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.21:01:22.10#ibcon#ireg 11 cls_cnt 2 2006.145.21:01:22.10#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.21:01:22.16#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.21:01:22.16#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.21:01:22.18#ibcon#[25=AT02-07\r\n] 2006.145.21:01:22.21#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.21:01:22.21#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.21:01:22.21#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.21:01:22.21#ibcon#ireg 7 cls_cnt 0 2006.145.21:01:22.21#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.21:01:22.33#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.21:01:22.33#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.21:01:22.35#ibcon#[25=USB\r\n] 2006.145.21:01:22.38#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.21:01:22.38#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.21:01:22.38#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.21:01:22.38#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.21:01:22.38$vck44/valo=3,564.99 2006.145.21:01:22.38#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.21:01:22.38#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.21:01:22.38#ibcon#ireg 17 cls_cnt 0 2006.145.21:01:22.38#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:01:22.38#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:01:22.38#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:01:22.40#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.21:01:22.44#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:01:22.44#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:01:22.44#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.21:01:22.44#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.21:01:22.44$vck44/va=3,8 2006.145.21:01:22.44#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.21:01:22.44#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.21:01:22.44#ibcon#ireg 11 cls_cnt 2 2006.145.21:01:22.44#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:01:22.50#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:01:22.50#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:01:22.52#ibcon#[25=AT03-08\r\n] 2006.145.21:01:22.55#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:01:22.55#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:01:22.55#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.21:01:22.55#ibcon#ireg 7 cls_cnt 0 2006.145.21:01:22.55#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:01:22.67#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:01:22.67#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:01:22.69#ibcon#[25=USB\r\n] 2006.145.21:01:22.72#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:01:22.72#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:01:22.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.21:01:22.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.21:01:22.72$vck44/valo=4,624.99 2006.145.21:01:22.72#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.21:01:22.72#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.21:01:22.72#ibcon#ireg 17 cls_cnt 0 2006.145.21:01:22.72#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:01:22.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:01:22.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:01:22.74#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.21:01:22.78#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:01:22.78#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:01:22.78#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.21:01:22.78#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.21:01:22.78$vck44/va=4,7 2006.145.21:01:22.78#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.21:01:22.78#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.21:01:22.78#ibcon#ireg 11 cls_cnt 2 2006.145.21:01:22.78#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:01:22.84#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:01:22.84#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:01:22.86#ibcon#[25=AT04-07\r\n] 2006.145.21:01:22.89#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:01:22.89#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:01:22.89#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.21:01:22.89#ibcon#ireg 7 cls_cnt 0 2006.145.21:01:22.89#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:01:23.01#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:01:23.01#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:01:23.03#ibcon#[25=USB\r\n] 2006.145.21:01:23.07#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:01:23.07#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:01:23.07#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.21:01:23.07#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.21:01:23.07$vck44/valo=5,734.99 2006.145.21:01:23.07#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.21:01:23.07#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.21:01:23.07#ibcon#ireg 17 cls_cnt 0 2006.145.21:01:23.07#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:01:23.07#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:01:23.07#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:01:23.09#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.21:01:23.13#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:01:23.13#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:01:23.13#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.21:01:23.13#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.21:01:23.13$vck44/va=5,4 2006.145.21:01:23.13#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.21:01:23.13#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.21:01:23.13#ibcon#ireg 11 cls_cnt 2 2006.145.21:01:23.13#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:01:23.19#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:01:23.19#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:01:23.21#ibcon#[25=AT05-04\r\n] 2006.145.21:01:23.24#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:01:23.24#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:01:23.24#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.21:01:23.24#ibcon#ireg 7 cls_cnt 0 2006.145.21:01:23.24#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:01:23.37#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:01:23.37#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:01:23.38#ibcon#[25=USB\r\n] 2006.145.21:01:23.41#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:01:23.41#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:01:23.41#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.21:01:23.41#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.21:01:23.41$vck44/valo=6,814.99 2006.145.21:01:23.41#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.21:01:23.41#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.21:01:23.41#ibcon#ireg 17 cls_cnt 0 2006.145.21:01:23.41#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.21:01:23.41#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.21:01:23.41#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.21:01:23.43#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.21:01:23.47#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.21:01:23.47#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.21:01:23.47#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.21:01:23.47#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.21:01:23.47$vck44/va=6,4 2006.145.21:01:23.47#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.21:01:23.47#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.21:01:23.47#ibcon#ireg 11 cls_cnt 2 2006.145.21:01:23.47#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.21:01:23.53#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.21:01:23.53#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.21:01:23.55#ibcon#[25=AT06-04\r\n] 2006.145.21:01:23.58#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.21:01:23.58#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.21:01:23.58#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.21:01:23.58#ibcon#ireg 7 cls_cnt 0 2006.145.21:01:23.58#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.21:01:23.70#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.21:01:23.70#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.21:01:23.72#ibcon#[25=USB\r\n] 2006.145.21:01:23.75#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.21:01:23.75#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.21:01:23.75#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.21:01:23.75#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.21:01:23.75$vck44/valo=7,864.99 2006.145.21:01:23.75#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.21:01:23.75#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.21:01:23.75#ibcon#ireg 17 cls_cnt 0 2006.145.21:01:23.75#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:01:23.75#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:01:23.75#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:01:23.77#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.21:01:23.81#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:01:23.81#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:01:23.81#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.21:01:23.81#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.21:01:23.81$vck44/va=7,4 2006.145.21:01:23.81#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.21:01:23.81#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.21:01:23.81#ibcon#ireg 11 cls_cnt 2 2006.145.21:01:23.81#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:01:23.87#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:01:23.87#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:01:23.89#ibcon#[25=AT07-04\r\n] 2006.145.21:01:23.92#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:01:23.92#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:01:23.92#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.21:01:23.92#ibcon#ireg 7 cls_cnt 0 2006.145.21:01:23.92#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:01:24.04#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:01:24.04#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:01:24.06#ibcon#[25=USB\r\n] 2006.145.21:01:24.09#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:01:24.09#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:01:24.09#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.21:01:24.09#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.21:01:24.09$vck44/valo=8,884.99 2006.145.21:01:24.09#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.21:01:24.09#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.21:01:24.09#ibcon#ireg 17 cls_cnt 0 2006.145.21:01:24.09#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:01:24.09#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:01:24.09#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:01:24.11#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.21:01:24.15#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:01:24.15#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:01:24.15#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.21:01:24.15#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.21:01:24.15$vck44/va=8,4 2006.145.21:01:24.15#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.21:01:24.15#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.21:01:24.15#ibcon#ireg 11 cls_cnt 2 2006.145.21:01:24.15#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.21:01:24.21#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.21:01:24.21#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.21:01:24.23#ibcon#[25=AT08-04\r\n] 2006.145.21:01:24.26#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.21:01:24.26#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.21:01:24.26#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.21:01:24.26#ibcon#ireg 7 cls_cnt 0 2006.145.21:01:24.26#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.21:01:24.38#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.21:01:24.38#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.21:01:24.40#ibcon#[25=USB\r\n] 2006.145.21:01:24.43#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.21:01:24.43#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.21:01:24.43#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.21:01:24.43#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.21:01:24.43$vck44/vblo=1,629.99 2006.145.21:01:24.43#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.21:01:24.43#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.21:01:24.43#ibcon#ireg 17 cls_cnt 0 2006.145.21:01:24.43#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.21:01:24.43#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.21:01:24.43#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.21:01:24.45#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.21:01:24.49#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.21:01:24.49#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.21:01:24.49#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.21:01:24.49#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.21:01:24.49$vck44/vb=1,3 2006.145.21:01:24.49#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.21:01:24.49#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.21:01:24.49#ibcon#ireg 11 cls_cnt 2 2006.145.21:01:24.49#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.21:01:24.49#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.21:01:24.49#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.21:01:24.51#ibcon#[27=AT01-03\r\n] 2006.145.21:01:24.55#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.21:01:24.55#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.21:01:24.55#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.21:01:24.55#ibcon#ireg 7 cls_cnt 0 2006.145.21:01:24.55#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.21:01:24.66#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.21:01:24.66#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.21:01:24.68#ibcon#[27=USB\r\n] 2006.145.21:01:24.71#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.21:01:24.71#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.21:01:24.71#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.21:01:24.71#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.21:01:24.71$vck44/vblo=2,634.99 2006.145.21:01:24.71#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.21:01:24.71#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.21:01:24.71#ibcon#ireg 17 cls_cnt 0 2006.145.21:01:24.71#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:01:24.71#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:01:24.71#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:01:24.74#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.21:01:24.78#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:01:24.78#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:01:24.78#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.21:01:24.78#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.21:01:24.78$vck44/vb=2,4 2006.145.21:01:24.78#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.21:01:24.78#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.21:01:24.78#ibcon#ireg 11 cls_cnt 2 2006.145.21:01:24.78#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.21:01:24.83#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.21:01:24.83#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.21:01:24.85#ibcon#[27=AT02-04\r\n] 2006.145.21:01:24.88#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.21:01:24.88#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.21:01:24.88#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.21:01:24.88#ibcon#ireg 7 cls_cnt 0 2006.145.21:01:24.88#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.21:01:25.00#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.21:01:25.00#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.21:01:25.02#ibcon#[27=USB\r\n] 2006.145.21:01:25.05#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.21:01:25.05#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.21:01:25.05#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.21:01:25.05#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.21:01:25.05$vck44/vblo=3,649.99 2006.145.21:01:25.05#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.21:01:25.05#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.21:01:25.05#ibcon#ireg 17 cls_cnt 0 2006.145.21:01:25.05#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.21:01:25.05#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.21:01:25.05#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.21:01:25.07#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.21:01:25.11#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.21:01:25.11#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.21:01:25.11#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.21:01:25.11#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.21:01:25.11$vck44/vb=3,4 2006.145.21:01:25.11#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.21:01:25.11#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.21:01:25.11#ibcon#ireg 11 cls_cnt 2 2006.145.21:01:25.11#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.21:01:25.17#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.21:01:25.17#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.21:01:25.19#ibcon#[27=AT03-04\r\n] 2006.145.21:01:25.22#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.21:01:25.22#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.21:01:25.22#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.21:01:25.22#ibcon#ireg 7 cls_cnt 0 2006.145.21:01:25.22#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.21:01:25.34#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.21:01:25.34#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.21:01:25.36#ibcon#[27=USB\r\n] 2006.145.21:01:25.39#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.21:01:25.39#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.21:01:25.39#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.21:01:25.39#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.21:01:25.39$vck44/vblo=4,679.99 2006.145.21:01:25.39#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.21:01:25.39#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.21:01:25.39#ibcon#ireg 17 cls_cnt 0 2006.145.21:01:25.39#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:01:25.39#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:01:25.39#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:01:25.41#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.21:01:25.45#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:01:25.45#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:01:25.45#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.21:01:25.45#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.21:01:25.45$vck44/vb=4,4 2006.145.21:01:25.45#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.21:01:25.45#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.21:01:25.45#ibcon#ireg 11 cls_cnt 2 2006.145.21:01:25.45#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:01:25.51#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:01:25.51#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:01:25.53#ibcon#[27=AT04-04\r\n] 2006.145.21:01:25.56#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:01:25.56#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:01:25.56#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.21:01:25.56#ibcon#ireg 7 cls_cnt 0 2006.145.21:01:25.56#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:01:25.68#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:01:25.68#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:01:25.70#ibcon#[27=USB\r\n] 2006.145.21:01:25.73#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:01:25.73#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:01:25.73#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.21:01:25.73#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.21:01:25.73$vck44/vblo=5,709.99 2006.145.21:01:25.73#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.21:01:25.73#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.21:01:25.73#ibcon#ireg 17 cls_cnt 0 2006.145.21:01:25.73#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:01:25.73#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:01:25.73#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:01:25.75#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.21:01:25.79#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:01:25.79#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:01:25.79#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.21:01:25.79#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.21:01:25.79$vck44/vb=5,4 2006.145.21:01:25.79#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.21:01:25.79#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.21:01:25.79#ibcon#ireg 11 cls_cnt 2 2006.145.21:01:25.79#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:01:25.85#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:01:25.85#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:01:25.87#ibcon#[27=AT05-04\r\n] 2006.145.21:01:25.90#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:01:25.90#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:01:25.90#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.21:01:25.90#ibcon#ireg 7 cls_cnt 0 2006.145.21:01:25.90#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:01:26.02#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:01:26.02#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:01:26.04#ibcon#[27=USB\r\n] 2006.145.21:01:26.07#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:01:26.07#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:01:26.07#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.21:01:26.07#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.21:01:26.07$vck44/vblo=6,719.99 2006.145.21:01:26.07#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.21:01:26.07#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.21:01:26.07#ibcon#ireg 17 cls_cnt 0 2006.145.21:01:26.07#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:01:26.07#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:01:26.07#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:01:26.09#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.21:01:26.13#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:01:26.13#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:01:26.13#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.21:01:26.13#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.21:01:26.13$vck44/vb=6,4 2006.145.21:01:26.13#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.21:01:26.13#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.21:01:26.13#ibcon#ireg 11 cls_cnt 2 2006.145.21:01:26.13#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:01:26.19#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:01:26.19#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:01:26.21#ibcon#[27=AT06-04\r\n] 2006.145.21:01:26.24#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:01:26.24#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:01:26.24#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.21:01:26.24#ibcon#ireg 7 cls_cnt 0 2006.145.21:01:26.24#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:01:26.32#abcon#<5=/07 1.3 3.0 16.66 851020.1\r\n> 2006.145.21:01:26.34#abcon#{5=INTERFACE CLEAR} 2006.145.21:01:26.36#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:01:26.36#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:01:26.38#ibcon#[27=USB\r\n] 2006.145.21:01:26.40#abcon#[5=S1D000X0/0*\r\n] 2006.145.21:01:26.41#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:01:26.41#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:01:26.41#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.21:01:26.41#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.21:01:26.41$vck44/vblo=7,734.99 2006.145.21:01:26.41#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.21:01:26.41#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.21:01:26.41#ibcon#ireg 17 cls_cnt 0 2006.145.21:01:26.41#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:01:26.41#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:01:26.41#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:01:26.43#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.21:01:26.47#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:01:26.47#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:01:26.47#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.21:01:26.47#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.21:01:26.47$vck44/vb=7,4 2006.145.21:01:26.47#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.21:01:26.47#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.21:01:26.47#ibcon#ireg 11 cls_cnt 2 2006.145.21:01:26.47#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:01:26.53#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:01:26.53#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:01:26.55#ibcon#[27=AT07-04\r\n] 2006.145.21:01:26.58#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:01:26.58#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:01:26.58#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.21:01:26.58#ibcon#ireg 7 cls_cnt 0 2006.145.21:01:26.58#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:01:26.70#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:01:26.70#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:01:26.72#ibcon#[27=USB\r\n] 2006.145.21:01:26.75#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:01:26.75#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:01:26.75#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.21:01:26.75#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.21:01:26.75$vck44/vblo=8,744.99 2006.145.21:01:26.75#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.21:01:26.75#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.21:01:26.75#ibcon#ireg 17 cls_cnt 0 2006.145.21:01:26.75#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:01:26.75#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:01:26.75#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:01:26.77#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.21:01:26.81#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:01:26.81#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:01:26.81#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.21:01:26.81#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.21:01:26.81$vck44/vb=8,4 2006.145.21:01:26.81#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.21:01:26.81#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.21:01:26.81#ibcon#ireg 11 cls_cnt 2 2006.145.21:01:26.81#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.21:01:26.87#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.21:01:26.87#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.21:01:26.89#ibcon#[27=AT08-04\r\n] 2006.145.21:01:26.92#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.21:01:26.92#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.21:01:26.92#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.21:01:26.92#ibcon#ireg 7 cls_cnt 0 2006.145.21:01:26.92#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.21:01:27.04#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.21:01:27.04#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.21:01:27.06#ibcon#[27=USB\r\n] 2006.145.21:01:27.09#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.21:01:27.09#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.21:01:27.09#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.21:01:27.09#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.21:01:27.09$vck44/vabw=wide 2006.145.21:01:27.09#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.21:01:27.09#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.21:01:27.09#ibcon#ireg 8 cls_cnt 0 2006.145.21:01:27.09#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.21:01:27.09#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.21:01:27.09#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.21:01:27.11#ibcon#[25=BW32\r\n] 2006.145.21:01:27.14#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.21:01:27.14#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.21:01:27.14#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.21:01:27.14#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.21:01:27.14$vck44/vbbw=wide 2006.145.21:01:27.14#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.21:01:27.14#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.21:01:27.14#ibcon#ireg 8 cls_cnt 0 2006.145.21:01:27.14#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.21:01:27.21#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.21:01:27.21#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.21:01:27.23#ibcon#[27=BW32\r\n] 2006.145.21:01:27.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.21:01:27.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.21:01:27.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.21:01:27.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.21:01:27.26$setupk4/ifdk4 2006.145.21:01:27.26$ifdk4/lo= 2006.145.21:01:27.26$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.21:01:27.26$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.21:01:27.26$ifdk4/patch= 2006.145.21:01:27.26$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.21:01:27.26$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.21:01:27.26$setupk4/!*+20s 2006.145.21:01:36.49#abcon#<5=/07 1.3 3.0 16.67 851020.1\r\n> 2006.145.21:01:36.51#abcon#{5=INTERFACE CLEAR} 2006.145.21:01:36.58#abcon#[5=S1D000X0/0*\r\n] 2006.145.21:01:41.72$setupk4/"tpicd 2006.145.21:01:41.72$setupk4/echo=off 2006.145.21:01:41.72$setupk4/xlog=off 2006.145.21:01:41.72:!2006.145.21:04:46 2006.145.21:01:45.14#trakl#Source acquired 2006.145.21:01:46.14#flagr#flagr/antenna,acquired 2006.145.21:04:46.00:preob 2006.145.21:04:47.13/onsource/TRACKING 2006.145.21:04:47.13:!2006.145.21:04:56 2006.145.21:04:56.00:"tape 2006.145.21:04:56.00:"st=record 2006.145.21:04:56.00:data_valid=on 2006.145.21:04:56.00:midob 2006.145.21:04:56.13/onsource/TRACKING 2006.145.21:04:56.13/wx/16.75,1020.1,85 2006.145.21:04:56.20/cable/+6.5507E-03 2006.145.21:04:57.29/va/01,08,usb,yes,38,41 2006.145.21:04:57.29/va/02,07,usb,yes,41,42 2006.145.21:04:57.29/va/03,08,usb,yes,37,39 2006.145.21:04:57.29/va/04,07,usb,yes,42,44 2006.145.21:04:57.29/va/05,04,usb,yes,37,38 2006.145.21:04:57.29/va/06,04,usb,yes,41,41 2006.145.21:04:57.29/va/07,04,usb,yes,42,43 2006.145.21:04:57.29/va/08,04,usb,yes,36,43 2006.145.21:04:57.52/valo/01,524.99,yes,locked 2006.145.21:04:57.52/valo/02,534.99,yes,locked 2006.145.21:04:57.52/valo/03,564.99,yes,locked 2006.145.21:04:57.52/valo/04,624.99,yes,locked 2006.145.21:04:57.52/valo/05,734.99,yes,locked 2006.145.21:04:57.52/valo/06,814.99,yes,locked 2006.145.21:04:57.52/valo/07,864.99,yes,locked 2006.145.21:04:57.52/valo/08,884.99,yes,locked 2006.145.21:04:58.61/vb/01,03,usb,yes,42,39 2006.145.21:04:58.61/vb/02,04,usb,yes,37,37 2006.145.21:04:58.61/vb/03,04,usb,yes,34,37 2006.145.21:04:58.61/vb/04,04,usb,yes,39,37 2006.145.21:04:58.61/vb/05,04,usb,yes,31,33 2006.145.21:04:58.61/vb/06,04,usb,yes,36,32 2006.145.21:04:58.61/vb/07,04,usb,yes,35,35 2006.145.21:04:58.61/vb/08,04,usb,yes,32,36 2006.145.21:04:58.84/vblo/01,629.99,yes,locked 2006.145.21:04:58.84/vblo/02,634.99,yes,locked 2006.145.21:04:58.84/vblo/03,649.99,yes,locked 2006.145.21:04:58.84/vblo/04,679.99,yes,locked 2006.145.21:04:58.84/vblo/05,709.99,yes,locked 2006.145.21:04:58.84/vblo/06,719.99,yes,locked 2006.145.21:04:58.84/vblo/07,734.99,yes,locked 2006.145.21:04:58.84/vblo/08,744.99,yes,locked 2006.145.21:04:58.99/vabw/8 2006.145.21:04:59.14/vbbw/8 2006.145.21:04:59.23/xfe/off,on,15.2 2006.145.21:04:59.60/ifatt/23,28,28,28 2006.145.21:05:00.07/fmout-gps/S +4.2E-08 2006.145.21:05:00.11:!2006.145.21:05:36 2006.145.21:05:36.01:data_valid=off 2006.145.21:05:36.01:"et 2006.145.21:05:36.02:!+3s 2006.145.21:05:39.03:"tape 2006.145.21:05:39.03:postob 2006.145.21:05:39.21/cable/+6.5498E-03 2006.145.21:05:39.21/wx/16.77,1020.1,84 2006.145.21:05:39.30/fmout-gps/S +4.1E-08 2006.145.21:05:39.30:scan_name=145-2111,jd0605,40 2006.145.21:05:39.30:source=3c345,164258.81,394837.0,2000.0,cw 2006.145.21:05:41.13#flagr#flagr/antenna,new-source 2006.145.21:05:41.14:checkk5 2006.145.21:05:41.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.21:05:42.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.21:05:42.45/chk_autoobs//k5ts3/ autoobs is running! 2006.145.21:05:42.88/chk_autoobs//k5ts4/ autoobs is running! 2006.145.21:05:43.31/chk_obsdata//k5ts1/T1452104??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.21:05:43.74/chk_obsdata//k5ts2/T1452104??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.21:05:44.18/chk_obsdata//k5ts3/T1452104??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.21:05:44.62/chk_obsdata//k5ts4/T1452104??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.21:05:45.39/k5log//k5ts1_log_newline 2006.145.21:05:46.13/k5log//k5ts2_log_newline 2006.145.21:05:46.87/k5log//k5ts3_log_newline 2006.145.21:05:47.62/k5log//k5ts4_log_newline 2006.145.21:05:47.65/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.21:05:47.65:setupk4=1 2006.145.21:05:47.65$setupk4/echo=on 2006.145.21:05:47.65$setupk4/pcalon 2006.145.21:05:47.65$pcalon/"no phase cal control is implemented here 2006.145.21:05:47.65$setupk4/"tpicd=stop 2006.145.21:05:47.65$setupk4/"rec=synch_on 2006.145.21:05:47.65$setupk4/"rec_mode=128 2006.145.21:05:47.65$setupk4/!* 2006.145.21:05:47.65$setupk4/recpk4 2006.145.21:05:47.65$recpk4/recpatch= 2006.145.21:05:47.65$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.21:05:47.65$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.21:05:47.65$setupk4/vck44 2006.145.21:05:47.65$vck44/valo=1,524.99 2006.145.21:05:47.65#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.21:05:47.65#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.21:05:47.65#ibcon#ireg 17 cls_cnt 0 2006.145.21:05:47.65#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.21:05:47.65#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.21:05:47.65#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.21:05:47.69#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.21:05:47.74#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.21:05:47.74#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.21:05:47.74#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.21:05:47.74#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.21:05:47.74$vck44/va=1,8 2006.145.21:05:47.74#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.21:05:47.74#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.21:05:47.74#ibcon#ireg 11 cls_cnt 2 2006.145.21:05:47.74#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.21:05:47.74#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.21:05:47.74#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.21:05:47.76#ibcon#[25=AT01-08\r\n] 2006.145.21:05:47.79#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.21:05:47.79#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.21:05:47.79#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.21:05:47.79#ibcon#ireg 7 cls_cnt 0 2006.145.21:05:47.79#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.21:05:47.91#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.21:05:47.91#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.21:05:47.93#ibcon#[25=USB\r\n] 2006.145.21:05:47.96#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.21:05:47.96#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.21:05:47.96#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.21:05:47.96#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.21:05:47.96$vck44/valo=2,534.99 2006.145.21:05:47.96#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.21:05:47.96#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.21:05:47.96#ibcon#ireg 17 cls_cnt 0 2006.145.21:05:47.96#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.21:05:47.96#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.21:05:47.96#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.21:05:47.99#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.21:05:48.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.21:05:48.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.21:05:48.03#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.21:05:48.03#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.21:05:48.03$vck44/va=2,7 2006.145.21:05:48.03#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.21:05:48.03#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.21:05:48.03#ibcon#ireg 11 cls_cnt 2 2006.145.21:05:48.03#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.21:05:48.08#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.21:05:48.08#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.21:05:48.10#ibcon#[25=AT02-07\r\n] 2006.145.21:05:48.13#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.21:05:48.13#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.21:05:48.13#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.21:05:48.13#ibcon#ireg 7 cls_cnt 0 2006.145.21:05:48.13#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.21:05:48.25#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.21:05:48.25#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.21:05:48.27#ibcon#[25=USB\r\n] 2006.145.21:05:48.30#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.21:05:48.30#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.21:05:48.30#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.21:05:48.30#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.21:05:48.30$vck44/valo=3,564.99 2006.145.21:05:48.30#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.21:05:48.30#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.21:05:48.30#ibcon#ireg 17 cls_cnt 0 2006.145.21:05:48.30#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.21:05:48.30#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.21:05:48.30#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.21:05:48.32#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.21:05:48.36#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.21:05:48.36#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.21:05:48.36#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.21:05:48.36#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.21:05:48.36$vck44/va=3,8 2006.145.21:05:48.36#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.21:05:48.36#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.21:05:48.36#ibcon#ireg 11 cls_cnt 2 2006.145.21:05:48.36#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.21:05:48.42#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.21:05:48.42#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.21:05:48.44#ibcon#[25=AT03-08\r\n] 2006.145.21:05:48.47#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.21:05:48.47#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.21:05:48.47#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.21:05:48.47#ibcon#ireg 7 cls_cnt 0 2006.145.21:05:48.47#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.21:05:48.59#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.21:05:48.59#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.21:05:48.61#ibcon#[25=USB\r\n] 2006.145.21:05:48.64#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.21:05:48.64#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.21:05:48.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.21:05:48.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.21:05:48.64$vck44/valo=4,624.99 2006.145.21:05:48.64#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.21:05:48.64#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.21:05:48.64#ibcon#ireg 17 cls_cnt 0 2006.145.21:05:48.64#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.21:05:48.64#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.21:05:48.64#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.21:05:48.66#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.21:05:48.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.21:05:48.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.21:05:48.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.21:05:48.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.21:05:48.70$vck44/va=4,7 2006.145.21:05:48.70#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.21:05:48.70#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.21:05:48.70#ibcon#ireg 11 cls_cnt 2 2006.145.21:05:48.70#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.21:05:48.76#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.21:05:48.76#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.21:05:48.78#ibcon#[25=AT04-07\r\n] 2006.145.21:05:48.81#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.21:05:48.81#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.21:05:48.81#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.21:05:48.81#ibcon#ireg 7 cls_cnt 0 2006.145.21:05:48.81#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.21:05:48.93#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.21:05:48.93#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.21:05:48.95#ibcon#[25=USB\r\n] 2006.145.21:05:48.98#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.21:05:48.98#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.21:05:48.98#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.21:05:48.98#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.21:05:48.98$vck44/valo=5,734.99 2006.145.21:05:48.98#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.21:05:48.98#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.21:05:48.98#ibcon#ireg 17 cls_cnt 0 2006.145.21:05:48.98#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.21:05:48.98#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.21:05:48.98#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.21:05:49.00#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.21:05:49.04#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.21:05:49.04#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.21:05:49.04#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.21:05:49.04#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.21:05:49.04$vck44/va=5,4 2006.145.21:05:49.04#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.21:05:49.04#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.21:05:49.04#ibcon#ireg 11 cls_cnt 2 2006.145.21:05:49.04#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.21:05:49.10#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.21:05:49.10#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.21:05:49.12#ibcon#[25=AT05-04\r\n] 2006.145.21:05:49.15#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.21:05:49.15#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.21:05:49.15#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.21:05:49.15#ibcon#ireg 7 cls_cnt 0 2006.145.21:05:49.15#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.21:05:49.27#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.21:05:49.27#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.21:05:49.29#ibcon#[25=USB\r\n] 2006.145.21:05:49.32#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.21:05:49.32#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.21:05:49.32#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.21:05:49.32#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.21:05:49.32$vck44/valo=6,814.99 2006.145.21:05:49.32#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.21:05:49.32#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.21:05:49.32#ibcon#ireg 17 cls_cnt 0 2006.145.21:05:49.32#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.21:05:49.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.21:05:49.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.21:05:49.34#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.21:05:49.38#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.21:05:49.38#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.21:05:49.38#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.21:05:49.38#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.21:05:49.38$vck44/va=6,4 2006.145.21:05:49.38#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.21:05:49.38#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.21:05:49.38#ibcon#ireg 11 cls_cnt 2 2006.145.21:05:49.38#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.21:05:49.44#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.21:05:49.44#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.21:05:49.46#ibcon#[25=AT06-04\r\n] 2006.145.21:05:49.49#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.21:05:49.49#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.21:05:49.49#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.21:05:49.49#ibcon#ireg 7 cls_cnt 0 2006.145.21:05:49.49#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.21:05:49.61#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.21:05:49.61#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.21:05:49.63#ibcon#[25=USB\r\n] 2006.145.21:05:49.66#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.21:05:49.66#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.21:05:49.66#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.21:05:49.66#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.21:05:49.66$vck44/valo=7,864.99 2006.145.21:05:49.66#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.21:05:49.66#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.21:05:49.66#ibcon#ireg 17 cls_cnt 0 2006.145.21:05:49.66#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.21:05:49.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.21:05:49.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.21:05:49.68#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.21:05:49.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.21:05:49.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.21:05:49.72#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.21:05:49.72#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.21:05:49.72$vck44/va=7,4 2006.145.21:05:49.72#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.21:05:49.72#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.21:05:49.72#ibcon#ireg 11 cls_cnt 2 2006.145.21:05:49.72#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.21:05:49.78#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.21:05:49.78#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.21:05:49.80#ibcon#[25=AT07-04\r\n] 2006.145.21:05:49.83#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.21:05:49.83#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.21:05:49.83#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.21:05:49.83#ibcon#ireg 7 cls_cnt 0 2006.145.21:05:49.83#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.21:05:49.95#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.21:05:49.95#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.21:05:49.97#ibcon#[25=USB\r\n] 2006.145.21:05:50.00#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.21:05:50.00#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.21:05:50.00#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.21:05:50.00#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.21:05:50.00$vck44/valo=8,884.99 2006.145.21:05:50.00#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.21:05:50.00#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.21:05:50.00#ibcon#ireg 17 cls_cnt 0 2006.145.21:05:50.00#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.21:05:50.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.21:05:50.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.21:05:50.02#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.21:05:50.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.21:05:50.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.21:05:50.06#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.21:05:50.06#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.21:05:50.06$vck44/va=8,4 2006.145.21:05:50.06#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.21:05:50.06#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.21:05:50.06#ibcon#ireg 11 cls_cnt 2 2006.145.21:05:50.06#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.21:05:50.12#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.21:05:50.12#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.21:05:50.14#ibcon#[25=AT08-04\r\n] 2006.145.21:05:50.17#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.21:05:50.17#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.21:05:50.17#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.21:05:50.17#ibcon#ireg 7 cls_cnt 0 2006.145.21:05:50.17#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.21:05:50.29#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.21:05:50.29#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.21:05:50.31#ibcon#[25=USB\r\n] 2006.145.21:05:50.34#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.21:05:50.34#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.21:05:50.34#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.21:05:50.34#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.21:05:50.34$vck44/vblo=1,629.99 2006.145.21:05:50.34#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.21:05:50.34#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.21:05:50.34#ibcon#ireg 17 cls_cnt 0 2006.145.21:05:50.34#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.21:05:50.34#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.21:05:50.34#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.21:05:50.37#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.21:05:50.41#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.21:05:50.41#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.21:05:50.41#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.21:05:50.41#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.21:05:50.41$vck44/vb=1,3 2006.145.21:05:50.41#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.21:05:50.41#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.21:05:50.41#ibcon#ireg 11 cls_cnt 2 2006.145.21:05:50.41#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.21:05:50.41#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.21:05:50.41#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.21:05:50.43#ibcon#[27=AT01-03\r\n] 2006.145.21:05:50.46#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.21:05:50.46#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.21:05:50.46#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.21:05:50.46#ibcon#ireg 7 cls_cnt 0 2006.145.21:05:50.46#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.21:05:50.58#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.21:05:50.58#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.21:05:50.60#ibcon#[27=USB\r\n] 2006.145.21:05:50.63#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.21:05:50.63#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.21:05:50.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.21:05:50.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.21:05:50.63$vck44/vblo=2,634.99 2006.145.21:05:50.63#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.21:05:50.63#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.21:05:50.63#ibcon#ireg 17 cls_cnt 0 2006.145.21:05:50.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.21:05:50.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.21:05:50.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.21:05:50.65#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.21:05:50.69#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.21:05:50.69#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.21:05:50.69#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.21:05:50.69#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.21:05:50.69$vck44/vb=2,4 2006.145.21:05:50.69#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.21:05:50.69#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.21:05:50.69#ibcon#ireg 11 cls_cnt 2 2006.145.21:05:50.69#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.21:05:50.75#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.21:05:50.75#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.21:05:50.77#ibcon#[27=AT02-04\r\n] 2006.145.21:05:50.80#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.21:05:50.80#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.21:05:50.80#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.21:05:50.80#ibcon#ireg 7 cls_cnt 0 2006.145.21:05:50.80#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.21:05:50.92#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.21:05:50.92#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.21:05:50.94#ibcon#[27=USB\r\n] 2006.145.21:05:50.96#abcon#<5=/07 1.4 3.2 16.78 841020.1\r\n> 2006.145.21:05:50.97#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.21:05:50.97#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.21:05:50.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.21:05:50.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.21:05:50.97$vck44/vblo=3,649.99 2006.145.21:05:50.97#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.21:05:50.97#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.21:05:50.97#ibcon#ireg 17 cls_cnt 0 2006.145.21:05:50.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:05:50.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:05:50.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:05:50.98#abcon#{5=INTERFACE CLEAR} 2006.145.21:05:50.99#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.21:05:51.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:05:51.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:05:51.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.21:05:51.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.21:05:51.03$vck44/vb=3,4 2006.145.21:05:51.03#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.21:05:51.03#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.21:05:51.03#ibcon#ireg 11 cls_cnt 2 2006.145.21:05:51.03#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.21:05:51.04#abcon#[5=S1D000X0/0*\r\n] 2006.145.21:05:51.09#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.21:05:51.09#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.21:05:51.11#ibcon#[27=AT03-04\r\n] 2006.145.21:05:51.14#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.21:05:51.14#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.21:05:51.14#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.21:05:51.14#ibcon#ireg 7 cls_cnt 0 2006.145.21:05:51.14#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.21:05:51.26#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.21:05:51.26#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.21:05:51.28#ibcon#[27=USB\r\n] 2006.145.21:05:51.31#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.21:05:51.31#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.21:05:51.31#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.21:05:51.31#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.21:05:51.31$vck44/vblo=4,679.99 2006.145.21:05:51.31#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.21:05:51.31#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.21:05:51.31#ibcon#ireg 17 cls_cnt 0 2006.145.21:05:51.31#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.21:05:51.31#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.21:05:51.31#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.21:05:51.33#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.21:05:51.37#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.21:05:51.37#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.21:05:51.37#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.21:05:51.37#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.21:05:51.37$vck44/vb=4,4 2006.145.21:05:51.37#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.21:05:51.37#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.21:05:51.37#ibcon#ireg 11 cls_cnt 2 2006.145.21:05:51.37#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.21:05:51.43#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.21:05:51.43#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.21:05:51.45#ibcon#[27=AT04-04\r\n] 2006.145.21:05:51.48#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.21:05:51.48#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.21:05:51.48#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.21:05:51.48#ibcon#ireg 7 cls_cnt 0 2006.145.21:05:51.48#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.21:05:51.60#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.21:05:51.60#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.21:05:51.62#ibcon#[27=USB\r\n] 2006.145.21:05:51.65#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.21:05:51.65#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.21:05:51.65#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.21:05:51.65#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.21:05:51.65$vck44/vblo=5,709.99 2006.145.21:05:51.65#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.21:05:51.65#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.21:05:51.65#ibcon#ireg 17 cls_cnt 0 2006.145.21:05:51.65#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.21:05:51.65#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.21:05:51.65#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.21:05:51.67#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.21:05:51.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.21:05:51.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.21:05:51.71#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.21:05:51.71#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.21:05:51.71$vck44/vb=5,4 2006.145.21:05:51.71#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.21:05:51.71#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.21:05:51.71#ibcon#ireg 11 cls_cnt 2 2006.145.21:05:51.71#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.21:05:51.77#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.21:05:51.77#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.21:05:51.79#ibcon#[27=AT05-04\r\n] 2006.145.21:05:51.82#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.21:05:51.82#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.21:05:51.82#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.21:05:51.82#ibcon#ireg 7 cls_cnt 0 2006.145.21:05:51.82#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.21:05:51.94#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.21:05:51.94#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.21:05:51.96#ibcon#[27=USB\r\n] 2006.145.21:05:51.99#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.21:05:51.99#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.21:05:51.99#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.21:05:51.99#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.21:05:51.99$vck44/vblo=6,719.99 2006.145.21:05:51.99#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.21:05:51.99#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.21:05:51.99#ibcon#ireg 17 cls_cnt 0 2006.145.21:05:51.99#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.21:05:51.99#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.21:05:51.99#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.21:05:52.01#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.21:05:52.05#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.21:05:52.05#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.21:05:52.05#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.21:05:52.05#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.21:05:52.05$vck44/vb=6,4 2006.145.21:05:52.05#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.21:05:52.05#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.21:05:52.05#ibcon#ireg 11 cls_cnt 2 2006.145.21:05:52.05#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.21:05:52.11#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.21:05:52.11#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.21:05:52.13#ibcon#[27=AT06-04\r\n] 2006.145.21:05:52.16#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.21:05:52.16#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.21:05:52.16#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.21:05:52.16#ibcon#ireg 7 cls_cnt 0 2006.145.21:05:52.16#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.21:05:52.28#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.21:05:52.28#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.21:05:52.30#ibcon#[27=USB\r\n] 2006.145.21:05:52.33#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.21:05:52.33#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.21:05:52.33#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.21:05:52.33#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.21:05:52.33$vck44/vblo=7,734.99 2006.145.21:05:52.33#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.21:05:52.33#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.21:05:52.33#ibcon#ireg 17 cls_cnt 0 2006.145.21:05:52.33#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.21:05:52.33#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.21:05:52.33#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.21:05:52.35#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.21:05:52.39#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.21:05:52.39#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.21:05:52.39#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.21:05:52.39#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.21:05:52.39$vck44/vb=7,4 2006.145.21:05:52.39#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.21:05:52.39#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.21:05:52.39#ibcon#ireg 11 cls_cnt 2 2006.145.21:05:52.39#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.21:05:52.45#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.21:05:52.45#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.21:05:52.47#ibcon#[27=AT07-04\r\n] 2006.145.21:05:52.50#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.21:05:52.50#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.21:05:52.50#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.21:05:52.50#ibcon#ireg 7 cls_cnt 0 2006.145.21:05:52.50#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.21:05:52.62#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.21:05:52.62#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.21:05:52.64#ibcon#[27=USB\r\n] 2006.145.21:05:52.67#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.21:05:52.67#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.21:05:52.67#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.21:05:52.67#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.21:05:52.67$vck44/vblo=8,744.99 2006.145.21:05:52.67#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.21:05:52.67#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.21:05:52.67#ibcon#ireg 17 cls_cnt 0 2006.145.21:05:52.67#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.21:05:52.67#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.21:05:52.67#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.21:05:52.69#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.21:05:52.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.21:05:52.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.21:05:52.73#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.21:05:52.73#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.21:05:52.73$vck44/vb=8,4 2006.145.21:05:52.73#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.21:05:52.73#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.21:05:52.73#ibcon#ireg 11 cls_cnt 2 2006.145.21:05:52.73#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.21:05:52.79#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.21:05:52.79#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.21:05:52.81#ibcon#[27=AT08-04\r\n] 2006.145.21:05:52.84#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.21:05:52.84#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.21:05:52.84#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.21:05:52.84#ibcon#ireg 7 cls_cnt 0 2006.145.21:05:52.84#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.21:05:52.96#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.21:05:52.96#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.21:05:52.98#ibcon#[27=USB\r\n] 2006.145.21:05:53.01#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.21:05:53.01#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.21:05:53.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.21:05:53.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.21:05:53.01$vck44/vabw=wide 2006.145.21:05:53.01#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.21:05:53.01#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.21:05:53.01#ibcon#ireg 8 cls_cnt 0 2006.145.21:05:53.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.21:05:53.01#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.21:05:53.01#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.21:05:53.03#ibcon#[25=BW32\r\n] 2006.145.21:05:53.06#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.21:05:53.06#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.21:05:53.06#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.21:05:53.06#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.21:05:53.06$vck44/vbbw=wide 2006.145.21:05:53.06#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.21:05:53.06#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.21:05:53.06#ibcon#ireg 8 cls_cnt 0 2006.145.21:05:53.06#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.21:05:53.13#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.21:05:53.13#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.21:05:53.15#ibcon#[27=BW32\r\n] 2006.145.21:05:53.18#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.21:05:53.18#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.21:05:53.18#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.21:05:53.18#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.21:05:53.18$setupk4/ifdk4 2006.145.21:05:53.18$ifdk4/lo= 2006.145.21:05:53.18$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.21:05:53.18$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.21:05:53.18$ifdk4/patch= 2006.145.21:05:53.18$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.21:05:53.18$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.21:05:53.18$setupk4/!*+20s 2006.145.21:06:01.13#abcon#<5=/07 1.4 3.2 16.78 841020.1\r\n> 2006.145.21:06:01.15#abcon#{5=INTERFACE CLEAR} 2006.145.21:06:01.21#abcon#[5=S1D000X0/0*\r\n] 2006.145.21:06:07.66$setupk4/"tpicd 2006.145.21:06:07.66$setupk4/echo=off 2006.145.21:06:07.66$setupk4/xlog=off 2006.145.21:06:07.66:!2006.145.21:10:59 2006.145.21:06:19.13#trakl#Source acquired 2006.145.21:06:21.13#flagr#flagr/antenna,acquired 2006.145.21:10:59.00:preob 2006.145.21:10:59.14/onsource/TRACKING 2006.145.21:10:59.14:!2006.145.21:11:09 2006.145.21:11:09.00:"tape 2006.145.21:11:09.00:"st=record 2006.145.21:11:09.00:data_valid=on 2006.145.21:11:09.00:midob 2006.145.21:11:09.14/onsource/TRACKING 2006.145.21:11:09.14/wx/16.91,1020.1,86 2006.145.21:11:09.33/cable/+6.5505E-03 2006.145.21:11:10.42/va/01,08,usb,yes,30,32 2006.145.21:11:10.42/va/02,07,usb,yes,32,33 2006.145.21:11:10.42/va/03,08,usb,yes,29,31 2006.145.21:11:10.42/va/04,07,usb,yes,33,35 2006.145.21:11:10.42/va/05,04,usb,yes,29,30 2006.145.21:11:10.42/va/06,04,usb,yes,33,32 2006.145.21:11:10.42/va/07,04,usb,yes,33,34 2006.145.21:11:10.42/va/08,04,usb,yes,28,34 2006.145.21:11:10.65/valo/01,524.99,yes,locked 2006.145.21:11:10.65/valo/02,534.99,yes,locked 2006.145.21:11:10.65/valo/03,564.99,yes,locked 2006.145.21:11:10.65/valo/04,624.99,yes,locked 2006.145.21:11:10.65/valo/05,734.99,yes,locked 2006.145.21:11:10.65/valo/06,814.99,yes,locked 2006.145.21:11:10.65/valo/07,864.99,yes,locked 2006.145.21:11:10.65/valo/08,884.99,yes,locked 2006.145.21:11:11.74/vb/01,03,usb,yes,37,35 2006.145.21:11:11.74/vb/02,04,usb,yes,33,32 2006.145.21:11:11.74/vb/03,04,usb,yes,30,33 2006.145.21:11:11.74/vb/04,04,usb,yes,34,33 2006.145.21:11:11.74/vb/05,04,usb,yes,26,29 2006.145.21:11:11.74/vb/06,04,usb,yes,31,27 2006.145.21:11:11.74/vb/07,04,usb,yes,31,30 2006.145.21:11:11.74/vb/08,04,usb,yes,28,32 2006.145.21:11:11.97/vblo/01,629.99,yes,locked 2006.145.21:11:11.97/vblo/02,634.99,yes,locked 2006.145.21:11:11.97/vblo/03,649.99,yes,locked 2006.145.21:11:11.97/vblo/04,679.99,yes,locked 2006.145.21:11:11.97/vblo/05,709.99,yes,locked 2006.145.21:11:11.97/vblo/06,719.99,yes,locked 2006.145.21:11:11.97/vblo/07,734.99,yes,locked 2006.145.21:11:11.97/vblo/08,744.99,yes,locked 2006.145.21:11:12.12/vabw/8 2006.145.21:11:12.27/vbbw/8 2006.145.21:11:12.36/xfe/off,on,14.7 2006.145.21:11:12.73/ifatt/23,28,28,28 2006.145.21:11:13.07/fmout-gps/S +4.0E-08 2006.145.21:11:13.11:!2006.145.21:11:49 2006.145.21:11:49.00:data_valid=off 2006.145.21:11:49.00:"et 2006.145.21:11:49.01:!+3s 2006.145.21:11:52.02:"tape 2006.145.21:11:52.02:postob 2006.145.21:11:52.17/cable/+6.5486E-03 2006.145.21:11:52.17/wx/16.95,1020.1,84 2006.145.21:11:52.23/fmout-gps/S +4.0E-08 2006.145.21:11:52.23:scan_name=145-2113,jd0605,610 2006.145.21:11:52.23:source=1418+546,141946.60,542314.8,2000.0,cw 2006.145.21:11:54.14#flagr#flagr/antenna,new-source 2006.145.21:11:54.14:checkk5 2006.145.21:11:54.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.21:11:55.04/chk_autoobs//k5ts2/ autoobs is running! 2006.145.21:11:55.48/chk_autoobs//k5ts3/ autoobs is running! 2006.145.21:11:55.92/chk_autoobs//k5ts4/ autoobs is running! 2006.145.21:11:56.35/chk_obsdata//k5ts1/T1452111??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.21:11:56.77/chk_obsdata//k5ts2/T1452111??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.21:11:57.21/chk_obsdata//k5ts3/T1452111??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.21:11:57.64/chk_obsdata//k5ts4/T1452111??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.145.21:11:58.41/k5log//k5ts1_log_newline 2006.145.21:11:59.15/k5log//k5ts2_log_newline 2006.145.21:11:59.91/k5log//k5ts3_log_newline 2006.145.21:12:00.65/k5log//k5ts4_log_newline 2006.145.21:12:00.68/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.21:12:00.68:setupk4=1 2006.145.21:12:00.68$setupk4/echo=on 2006.145.21:12:00.68$setupk4/pcalon 2006.145.21:12:00.68$pcalon/"no phase cal control is implemented here 2006.145.21:12:00.68$setupk4/"tpicd=stop 2006.145.21:12:00.68$setupk4/"rec=synch_on 2006.145.21:12:00.68$setupk4/"rec_mode=128 2006.145.21:12:00.68$setupk4/!* 2006.145.21:12:00.68$setupk4/recpk4 2006.145.21:12:00.68$recpk4/recpatch= 2006.145.21:12:00.69$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.21:12:00.69$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.21:12:00.69$setupk4/vck44 2006.145.21:12:00.69$vck44/valo=1,524.99 2006.145.21:12:00.69#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.21:12:00.69#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.21:12:00.69#ibcon#ireg 17 cls_cnt 0 2006.145.21:12:00.69#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.21:12:00.69#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.21:12:00.69#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.21:12:00.72#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.21:12:00.77#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.21:12:00.77#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.21:12:00.77#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.21:12:00.77#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.21:12:00.77$vck44/va=1,8 2006.145.21:12:00.77#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.21:12:00.77#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.21:12:00.77#ibcon#ireg 11 cls_cnt 2 2006.145.21:12:00.77#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.21:12:00.77#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.21:12:00.77#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.21:12:00.79#ibcon#[25=AT01-08\r\n] 2006.145.21:12:00.82#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.21:12:00.82#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.21:12:00.82#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.21:12:00.82#ibcon#ireg 7 cls_cnt 0 2006.145.21:12:00.82#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.21:12:00.94#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.21:12:00.94#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.21:12:00.96#ibcon#[25=USB\r\n] 2006.145.21:12:01.01#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.21:12:01.01#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.21:12:01.01#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.21:12:01.01#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.21:12:01.01$vck44/valo=2,534.99 2006.145.21:12:01.01#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.21:12:01.01#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.21:12:01.01#ibcon#ireg 17 cls_cnt 0 2006.145.21:12:01.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:12:01.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:12:01.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:12:01.03#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.21:12:01.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:12:01.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:12:01.07#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.21:12:01.07#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.21:12:01.07$vck44/va=2,7 2006.145.21:12:01.07#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.21:12:01.07#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.21:12:01.07#ibcon#ireg 11 cls_cnt 2 2006.145.21:12:01.07#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.21:12:01.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.21:12:01.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.21:12:01.15#ibcon#[25=AT02-07\r\n] 2006.145.21:12:01.18#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.21:12:01.18#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.21:12:01.18#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.21:12:01.18#ibcon#ireg 7 cls_cnt 0 2006.145.21:12:01.18#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.21:12:01.30#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.21:12:01.30#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.21:12:01.32#ibcon#[25=USB\r\n] 2006.145.21:12:01.35#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.21:12:01.35#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.21:12:01.35#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.21:12:01.35#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.21:12:01.35$vck44/valo=3,564.99 2006.145.21:12:01.35#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.21:12:01.35#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.21:12:01.35#ibcon#ireg 17 cls_cnt 0 2006.145.21:12:01.35#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.21:12:01.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.21:12:01.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.21:12:01.37#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.21:12:01.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.21:12:01.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.21:12:01.41#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.21:12:01.41#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.21:12:01.41$vck44/va=3,8 2006.145.21:12:01.41#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.21:12:01.41#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.21:12:01.41#ibcon#ireg 11 cls_cnt 2 2006.145.21:12:01.41#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.21:12:01.47#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.21:12:01.47#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.21:12:01.49#ibcon#[25=AT03-08\r\n] 2006.145.21:12:01.52#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.21:12:01.52#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.21:12:01.52#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.21:12:01.52#ibcon#ireg 7 cls_cnt 0 2006.145.21:12:01.52#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.21:12:01.64#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.21:12:01.64#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.21:12:01.66#ibcon#[25=USB\r\n] 2006.145.21:12:01.69#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.21:12:01.69#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.21:12:01.69#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.21:12:01.69#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.21:12:01.69$vck44/valo=4,624.99 2006.145.21:12:01.69#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.21:12:01.69#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.21:12:01.69#ibcon#ireg 17 cls_cnt 0 2006.145.21:12:01.69#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.21:12:01.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.21:12:01.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.21:12:01.71#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.21:12:01.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.21:12:01.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.21:12:01.75#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.21:12:01.75#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.21:12:01.75$vck44/va=4,7 2006.145.21:12:01.75#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.21:12:01.75#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.21:12:01.75#ibcon#ireg 11 cls_cnt 2 2006.145.21:12:01.75#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.21:12:01.81#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.21:12:01.81#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.21:12:01.83#ibcon#[25=AT04-07\r\n] 2006.145.21:12:01.86#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.21:12:01.86#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.21:12:01.86#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.21:12:01.86#ibcon#ireg 7 cls_cnt 0 2006.145.21:12:01.86#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.21:12:01.98#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.21:12:01.98#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.21:12:02.00#ibcon#[25=USB\r\n] 2006.145.21:12:02.03#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.21:12:02.03#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.21:12:02.03#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.21:12:02.03#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.21:12:02.03$vck44/valo=5,734.99 2006.145.21:12:02.03#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.21:12:02.03#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.21:12:02.03#ibcon#ireg 17 cls_cnt 0 2006.145.21:12:02.03#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.21:12:02.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.21:12:02.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.21:12:02.05#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.21:12:02.09#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.21:12:02.09#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.21:12:02.09#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.21:12:02.09#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.21:12:02.09$vck44/va=5,4 2006.145.21:12:02.09#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.21:12:02.09#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.21:12:02.09#ibcon#ireg 11 cls_cnt 2 2006.145.21:12:02.09#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.21:12:02.15#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.21:12:02.15#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.21:12:02.17#ibcon#[25=AT05-04\r\n] 2006.145.21:12:02.20#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.21:12:02.20#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.21:12:02.20#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.21:12:02.20#ibcon#ireg 7 cls_cnt 0 2006.145.21:12:02.20#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.21:12:02.32#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.21:12:02.32#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.21:12:02.34#ibcon#[25=USB\r\n] 2006.145.21:12:02.37#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.21:12:02.37#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.21:12:02.37#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.21:12:02.37#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.21:12:02.37$vck44/valo=6,814.99 2006.145.21:12:02.37#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.21:12:02.37#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.21:12:02.37#ibcon#ireg 17 cls_cnt 0 2006.145.21:12:02.37#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.21:12:02.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.21:12:02.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.21:12:02.40#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.21:12:02.44#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.21:12:02.44#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.21:12:02.44#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.21:12:02.44#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.21:12:02.44$vck44/va=6,4 2006.145.21:12:02.44#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.21:12:02.44#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.21:12:02.44#ibcon#ireg 11 cls_cnt 2 2006.145.21:12:02.44#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.21:12:02.49#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.21:12:02.49#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.21:12:02.51#ibcon#[25=AT06-04\r\n] 2006.145.21:12:02.54#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.21:12:02.54#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.21:12:02.54#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.21:12:02.54#ibcon#ireg 7 cls_cnt 0 2006.145.21:12:02.54#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.21:12:02.66#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.21:12:02.66#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.21:12:02.68#ibcon#[25=USB\r\n] 2006.145.21:12:02.71#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.21:12:02.71#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.21:12:02.71#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.21:12:02.71#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.21:12:02.71$vck44/valo=7,864.99 2006.145.21:12:02.71#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.21:12:02.71#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.21:12:02.71#ibcon#ireg 17 cls_cnt 0 2006.145.21:12:02.71#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.21:12:02.71#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.21:12:02.71#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.21:12:02.73#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.21:12:02.77#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.21:12:02.77#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.21:12:02.77#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.21:12:02.77#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.21:12:02.77$vck44/va=7,4 2006.145.21:12:02.77#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.21:12:02.77#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.21:12:02.77#ibcon#ireg 11 cls_cnt 2 2006.145.21:12:02.77#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.21:12:02.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.21:12:02.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.21:12:02.85#ibcon#[25=AT07-04\r\n] 2006.145.21:12:02.88#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.21:12:02.88#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.21:12:02.88#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.21:12:02.88#ibcon#ireg 7 cls_cnt 0 2006.145.21:12:02.88#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.21:12:03.00#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.21:12:03.00#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.21:12:03.02#ibcon#[25=USB\r\n] 2006.145.21:12:03.05#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.21:12:03.05#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.21:12:03.05#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.21:12:03.05#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.21:12:03.05$vck44/valo=8,884.99 2006.145.21:12:03.05#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.21:12:03.05#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.21:12:03.05#ibcon#ireg 17 cls_cnt 0 2006.145.21:12:03.05#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.21:12:03.05#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.21:12:03.05#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.21:12:03.07#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.21:12:03.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.21:12:03.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.21:12:03.11#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.21:12:03.11#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.21:12:03.11$vck44/va=8,4 2006.145.21:12:03.11#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.21:12:03.11#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.21:12:03.11#ibcon#ireg 11 cls_cnt 2 2006.145.21:12:03.11#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.21:12:03.17#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.21:12:03.17#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.21:12:03.19#ibcon#[25=AT08-04\r\n] 2006.145.21:12:03.22#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.21:12:03.22#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.21:12:03.22#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.21:12:03.22#ibcon#ireg 7 cls_cnt 0 2006.145.21:12:03.22#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.21:12:03.34#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.21:12:03.34#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.21:12:03.36#ibcon#[25=USB\r\n] 2006.145.21:12:03.39#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.21:12:03.39#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.21:12:03.39#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.21:12:03.39#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.21:12:03.39$vck44/vblo=1,629.99 2006.145.21:12:03.39#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.21:12:03.39#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.21:12:03.39#ibcon#ireg 17 cls_cnt 0 2006.145.21:12:03.39#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.21:12:03.39#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.21:12:03.39#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.21:12:03.41#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.21:12:03.45#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.21:12:03.45#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.21:12:03.45#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.21:12:03.45#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.21:12:03.45$vck44/vb=1,3 2006.145.21:12:03.45#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.21:12:03.45#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.21:12:03.45#ibcon#ireg 11 cls_cnt 2 2006.145.21:12:03.45#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.21:12:03.45#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.21:12:03.45#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.21:12:03.47#ibcon#[27=AT01-03\r\n] 2006.145.21:12:03.50#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.21:12:03.50#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.21:12:03.50#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.21:12:03.50#ibcon#ireg 7 cls_cnt 0 2006.145.21:12:03.50#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.21:12:03.62#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.21:12:03.62#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.21:12:03.64#ibcon#[27=USB\r\n] 2006.145.21:12:03.67#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.21:12:03.67#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.21:12:03.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.21:12:03.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.21:12:03.67$vck44/vblo=2,634.99 2006.145.21:12:03.67#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.21:12:03.67#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.21:12:03.67#ibcon#ireg 17 cls_cnt 0 2006.145.21:12:03.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.21:12:03.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.21:12:03.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.21:12:03.69#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.21:12:03.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.21:12:03.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.21:12:03.73#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.21:12:03.73#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.21:12:03.73$vck44/vb=2,4 2006.145.21:12:03.73#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.21:12:03.73#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.21:12:03.73#ibcon#ireg 11 cls_cnt 2 2006.145.21:12:03.73#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.21:12:03.79#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.21:12:03.79#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.21:12:03.81#ibcon#[27=AT02-04\r\n] 2006.145.21:12:03.84#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.21:12:03.84#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.21:12:03.84#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.21:12:03.84#ibcon#ireg 7 cls_cnt 0 2006.145.21:12:03.84#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.21:12:03.96#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.21:12:03.96#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.21:12:03.98#ibcon#[27=USB\r\n] 2006.145.21:12:04.01#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.21:12:04.01#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.21:12:04.01#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.21:12:04.01#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.21:12:04.01$vck44/vblo=3,649.99 2006.145.21:12:04.01#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.21:12:04.01#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.21:12:04.01#ibcon#ireg 17 cls_cnt 0 2006.145.21:12:04.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:12:04.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:12:04.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:12:04.03#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.21:12:04.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:12:04.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:12:04.07#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.21:12:04.07#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.21:12:04.07$vck44/vb=3,4 2006.145.21:12:04.07#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.21:12:04.07#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.21:12:04.07#ibcon#ireg 11 cls_cnt 2 2006.145.21:12:04.07#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.21:12:04.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.21:12:04.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.21:12:04.15#ibcon#[27=AT03-04\r\n] 2006.145.21:12:04.18#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.21:12:04.18#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.21:12:04.18#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.21:12:04.18#ibcon#ireg 7 cls_cnt 0 2006.145.21:12:04.18#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.21:12:04.30#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.21:12:04.30#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.21:12:04.32#ibcon#[27=USB\r\n] 2006.145.21:12:04.35#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.21:12:04.35#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.21:12:04.35#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.21:12:04.35#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.21:12:04.35$vck44/vblo=4,679.99 2006.145.21:12:04.35#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.21:12:04.35#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.21:12:04.35#ibcon#ireg 17 cls_cnt 0 2006.145.21:12:04.35#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.21:12:04.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.21:12:04.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.21:12:04.37#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.21:12:04.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.21:12:04.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.21:12:04.41#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.21:12:04.41#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.21:12:04.41$vck44/vb=4,4 2006.145.21:12:04.41#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.21:12:04.41#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.21:12:04.41#ibcon#ireg 11 cls_cnt 2 2006.145.21:12:04.41#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.21:12:04.47#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.21:12:04.47#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.21:12:04.49#ibcon#[27=AT04-04\r\n] 2006.145.21:12:04.52#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.21:12:04.52#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.21:12:04.52#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.21:12:04.52#ibcon#ireg 7 cls_cnt 0 2006.145.21:12:04.52#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.21:12:04.64#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.21:12:04.64#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.21:12:04.66#ibcon#[27=USB\r\n] 2006.145.21:12:04.69#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.21:12:04.69#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.21:12:04.69#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.21:12:04.69#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.21:12:04.69$vck44/vblo=5,709.99 2006.145.21:12:04.69#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.21:12:04.69#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.21:12:04.69#ibcon#ireg 17 cls_cnt 0 2006.145.21:12:04.69#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.21:12:04.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.21:12:04.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.21:12:04.71#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.21:12:04.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.21:12:04.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.21:12:04.75#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.21:12:04.75#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.21:12:04.75$vck44/vb=5,4 2006.145.21:12:04.75#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.21:12:04.75#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.21:12:04.75#ibcon#ireg 11 cls_cnt 2 2006.145.21:12:04.75#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.21:12:04.81#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.21:12:04.81#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.21:12:04.83#ibcon#[27=AT05-04\r\n] 2006.145.21:12:04.86#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.21:12:04.86#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.21:12:04.86#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.21:12:04.86#ibcon#ireg 7 cls_cnt 0 2006.145.21:12:04.86#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.21:12:04.98#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.21:12:04.98#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.21:12:05.00#ibcon#[27=USB\r\n] 2006.145.21:12:05.03#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.21:12:05.03#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.21:12:05.03#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.21:12:05.03#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.21:12:05.03$vck44/vblo=6,719.99 2006.145.21:12:05.03#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.21:12:05.03#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.21:12:05.03#ibcon#ireg 17 cls_cnt 0 2006.145.21:12:05.03#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.21:12:05.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.21:12:05.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.21:12:05.05#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.21:12:05.09#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.21:12:05.09#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.21:12:05.09#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.21:12:05.09#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.21:12:05.09$vck44/vb=6,4 2006.145.21:12:05.09#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.21:12:05.09#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.21:12:05.09#ibcon#ireg 11 cls_cnt 2 2006.145.21:12:05.09#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.21:12:05.15#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.21:12:05.15#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.21:12:05.17#ibcon#[27=AT06-04\r\n] 2006.145.21:12:05.20#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.21:12:05.20#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.21:12:05.20#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.21:12:05.20#ibcon#ireg 7 cls_cnt 0 2006.145.21:12:05.20#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.21:12:05.32#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.21:12:05.32#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.21:12:05.34#ibcon#[27=USB\r\n] 2006.145.21:12:05.37#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.21:12:05.37#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.21:12:05.37#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.21:12:05.37#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.21:12:05.37$vck44/vblo=7,734.99 2006.145.21:12:05.37#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.21:12:05.37#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.21:12:05.37#ibcon#ireg 17 cls_cnt 0 2006.145.21:12:05.37#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.21:12:05.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.21:12:05.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.21:12:05.39#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.21:12:05.43#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.21:12:05.43#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.21:12:05.43#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.21:12:05.43#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.21:12:05.43$vck44/vb=7,4 2006.145.21:12:05.43#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.21:12:05.43#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.21:12:05.43#ibcon#ireg 11 cls_cnt 2 2006.145.21:12:05.43#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.21:12:05.49#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.21:12:05.49#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.21:12:05.51#ibcon#[27=AT07-04\r\n] 2006.145.21:12:05.54#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.21:12:05.54#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.21:12:05.54#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.21:12:05.54#ibcon#ireg 7 cls_cnt 0 2006.145.21:12:05.54#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.21:12:05.66#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.21:12:05.66#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.21:12:05.68#ibcon#[27=USB\r\n] 2006.145.21:12:05.71#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.21:12:05.71#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.21:12:05.71#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.21:12:05.71#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.21:12:05.71$vck44/vblo=8,744.99 2006.145.21:12:05.71#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.21:12:05.71#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.21:12:05.71#ibcon#ireg 17 cls_cnt 0 2006.145.21:12:05.71#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.21:12:05.71#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.21:12:05.71#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.21:12:05.73#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.21:12:05.77#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.21:12:05.77#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.21:12:05.77#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.21:12:05.77#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.21:12:05.77$vck44/vb=8,4 2006.145.21:12:05.77#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.21:12:05.77#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.21:12:05.77#ibcon#ireg 11 cls_cnt 2 2006.145.21:12:05.77#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.21:12:05.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.21:12:05.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.21:12:05.85#ibcon#[27=AT08-04\r\n] 2006.145.21:12:05.88#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.21:12:05.88#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.21:12:05.88#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.21:12:05.88#ibcon#ireg 7 cls_cnt 0 2006.145.21:12:05.88#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.21:12:06.00#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.21:12:06.00#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.21:12:06.02#ibcon#[27=USB\r\n] 2006.145.21:12:06.05#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.21:12:06.05#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.21:12:06.05#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.21:12:06.05#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.21:12:06.05$vck44/vabw=wide 2006.145.21:12:06.05#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.21:12:06.05#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.21:12:06.05#ibcon#ireg 8 cls_cnt 0 2006.145.21:12:06.05#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.21:12:06.05#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.21:12:06.05#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.21:12:06.07#ibcon#[25=BW32\r\n] 2006.145.21:12:06.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.21:12:06.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.21:12:06.10#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.21:12:06.10#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.21:12:06.10$vck44/vbbw=wide 2006.145.21:12:06.10#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.21:12:06.10#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.21:12:06.10#ibcon#ireg 8 cls_cnt 0 2006.145.21:12:06.10#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:12:06.17#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:12:06.17#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:12:06.19#ibcon#[27=BW32\r\n] 2006.145.21:12:06.22#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:12:06.22#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:12:06.22#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.21:12:06.22#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.21:12:06.22$setupk4/ifdk4 2006.145.21:12:06.22$ifdk4/lo= 2006.145.21:12:06.22$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.21:12:06.22$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.21:12:06.22$ifdk4/patch= 2006.145.21:12:06.22$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.21:12:06.22$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.21:12:06.22$setupk4/!*+20s 2006.145.21:12:07.35#abcon#<5=/07 1.6 3.3 16.96 841020.1\r\n> 2006.145.21:12:07.37#abcon#{5=INTERFACE CLEAR} 2006.145.21:12:07.43#abcon#[5=S1D000X0/0*\r\n] 2006.145.21:12:12.14#trakl#Source acquired 2006.145.21:12:13.14#flagr#flagr/antenna,acquired 2006.145.21:12:17.52#abcon#<5=/07 1.6 3.2 16.97 841020.2\r\n> 2006.145.21:12:17.54#abcon#{5=INTERFACE CLEAR} 2006.145.21:12:17.60#abcon#[5=S1D000X0/0*\r\n] 2006.145.21:12:20.69$setupk4/"tpicd 2006.145.21:12:20.69$setupk4/echo=off 2006.145.21:12:20.69$setupk4/xlog=off 2006.145.21:12:20.69:!2006.145.21:13:15 2006.145.21:13:15.00:preob 2006.145.21:13:15.13/onsource/TRACKING 2006.145.21:13:15.13:!2006.145.21:13:25 2006.145.21:13:25.00:"tape 2006.145.21:13:25.00:"st=record 2006.145.21:13:25.00:data_valid=on 2006.145.21:13:25.00:midob 2006.145.21:13:25.13/onsource/TRACKING 2006.145.21:13:25.13/wx/17.01,1020.1,83 2006.145.21:13:25.32/cable/+6.5492E-03 2006.145.21:13:26.41/va/01,08,usb,yes,32,35 2006.145.21:13:26.41/va/02,07,usb,yes,35,35 2006.145.21:13:26.41/va/03,08,usb,yes,32,33 2006.145.21:13:26.41/va/04,07,usb,yes,36,38 2006.145.21:13:26.41/va/05,04,usb,yes,31,32 2006.145.21:13:26.41/va/06,04,usb,yes,35,35 2006.145.21:13:26.41/va/07,04,usb,yes,35,37 2006.145.21:13:26.41/va/08,04,usb,yes,30,36 2006.145.21:13:26.64/valo/01,524.99,yes,locked 2006.145.21:13:26.64/valo/02,534.99,yes,locked 2006.145.21:13:26.64/valo/03,564.99,yes,locked 2006.145.21:13:26.64/valo/04,624.99,yes,locked 2006.145.21:13:26.64/valo/05,734.99,yes,locked 2006.145.21:13:26.64/valo/06,814.99,yes,locked 2006.145.21:13:26.64/valo/07,864.99,yes,locked 2006.145.21:13:26.64/valo/08,884.99,yes,locked 2006.145.21:13:27.73/vb/01,03,usb,yes,39,36 2006.145.21:13:27.73/vb/02,04,usb,yes,34,34 2006.145.21:13:27.73/vb/03,04,usb,yes,31,34 2006.145.21:13:27.73/vb/04,04,usb,yes,35,34 2006.145.21:13:27.73/vb/05,04,usb,yes,27,30 2006.145.21:13:27.73/vb/06,04,usb,yes,32,28 2006.145.21:13:27.73/vb/07,04,usb,yes,32,32 2006.145.21:13:27.73/vb/08,04,usb,yes,29,33 2006.145.21:13:27.96/vblo/01,629.99,yes,locked 2006.145.21:13:27.96/vblo/02,634.99,yes,locked 2006.145.21:13:27.96/vblo/03,649.99,yes,locked 2006.145.21:13:27.96/vblo/04,679.99,yes,locked 2006.145.21:13:27.96/vblo/05,709.99,yes,locked 2006.145.21:13:27.96/vblo/06,719.99,yes,locked 2006.145.21:13:27.96/vblo/07,734.99,yes,locked 2006.145.21:13:27.96/vblo/08,744.99,yes,locked 2006.145.21:13:28.11/vabw/8 2006.145.21:13:28.26/vbbw/8 2006.145.21:13:28.35/xfe/off,on,14.7 2006.145.21:13:28.73/ifatt/23,28,28,28 2006.145.21:13:29.07/fmout-gps/S +4.2E-08 2006.145.21:13:29.11:!2006.145.21:23:35 2006.145.21:23:35.00:data_valid=off 2006.145.21:23:35.00:"et 2006.145.21:23:35.00:!+3s 2006.145.21:23:38.02:"tape 2006.145.21:23:38.02:postob 2006.145.21:23:38.18/cable/+6.5489E-03 2006.145.21:23:38.22/wx/17.41,1020.1,81 2006.145.21:23:38.29/fmout-gps/S +4.7E-08 2006.145.21:23:38.30:scan_name=145-2124,jd0605,784 2006.145.21:23:38.30:source=1749+096,175132.82,093900.7,2000.0,cw 2006.145.21:23:40.14#flagr#flagr/antenna,new-source 2006.145.21:23:40.14:checkk5 2006.145.21:23:40.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.21:23:41.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.21:23:41.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.21:23:41.91/chk_autoobs//k5ts4/ autoobs is running! 2006.145.21:23:42.64/chk_obsdata//k5ts1/T1452113??a.dat file size is correct (nominal:2440MB, actual:2436MB). 2006.145.21:23:43.37/chk_obsdata//k5ts2/T1452113??b.dat file size is correct (nominal:2440MB, actual:2436MB). 2006.145.21:23:44.12/chk_obsdata//k5ts3/T1452113??c.dat file size is correct (nominal:2440MB, actual:2436MB). 2006.145.21:23:44.86/chk_obsdata//k5ts4/T1452113??d.dat file size is correct (nominal:2440MB, actual:2436MB). 2006.145.21:23:45.63/k5log//k5ts1_log_newline 2006.145.21:23:46.38/k5log//k5ts2_log_newline 2006.145.21:23:47.10/k5log//k5ts3_log_newline 2006.145.21:23:47.83/k5log//k5ts4_log_newline 2006.145.21:23:47.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.21:23:47.86:setupk4=1 2006.145.21:23:47.86$setupk4/echo=on 2006.145.21:23:47.86$setupk4/pcalon 2006.145.21:23:47.86$pcalon/"no phase cal control is implemented here 2006.145.21:23:47.86$setupk4/"tpicd=stop 2006.145.21:23:47.86$setupk4/"rec=synch_on 2006.145.21:23:47.86$setupk4/"rec_mode=128 2006.145.21:23:47.86$setupk4/!* 2006.145.21:23:47.86$setupk4/recpk4 2006.145.21:23:47.86$recpk4/recpatch= 2006.145.21:23:47.86$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.21:23:47.86$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.21:23:47.86$setupk4/vck44 2006.145.21:23:47.86$vck44/valo=1,524.99 2006.145.21:23:47.86#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.21:23:47.86#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.21:23:47.86#ibcon#ireg 17 cls_cnt 0 2006.145.21:23:47.86#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.21:23:47.86#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.21:23:47.86#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.21:23:47.90#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.21:23:47.95#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.21:23:47.95#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.21:23:47.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.21:23:47.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.21:23:47.95$vck44/va=1,8 2006.145.21:23:47.95#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.21:23:47.95#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.21:23:47.95#ibcon#ireg 11 cls_cnt 2 2006.145.21:23:47.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.21:23:47.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.21:23:47.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.21:23:47.97#ibcon#[25=AT01-08\r\n] 2006.145.21:23:48.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.21:23:48.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.21:23:48.00#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.21:23:48.00#ibcon#ireg 7 cls_cnt 0 2006.145.21:23:48.00#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.21:23:48.12#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.21:23:48.12#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.21:23:48.14#ibcon#[25=USB\r\n] 2006.145.21:23:48.17#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.21:23:48.17#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.21:23:48.17#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.21:23:48.17#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.21:23:48.17$vck44/valo=2,534.99 2006.145.21:23:48.17#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.21:23:48.17#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.21:23:48.17#ibcon#ireg 17 cls_cnt 0 2006.145.21:23:48.17#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.21:23:48.17#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.21:23:48.17#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.21:23:48.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.21:23:48.24#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.21:23:48.24#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.21:23:48.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.21:23:48.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.21:23:48.24$vck44/va=2,7 2006.145.21:23:48.24#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.21:23:48.24#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.21:23:48.24#ibcon#ireg 11 cls_cnt 2 2006.145.21:23:48.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.21:23:48.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.21:23:48.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.21:23:48.31#ibcon#[25=AT02-07\r\n] 2006.145.21:23:48.34#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.21:23:48.34#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.21:23:48.34#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.21:23:48.34#ibcon#ireg 7 cls_cnt 0 2006.145.21:23:48.34#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.21:23:48.46#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.21:23:48.46#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.21:23:48.48#ibcon#[25=USB\r\n] 2006.145.21:23:48.51#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.21:23:48.51#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.21:23:48.51#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.21:23:48.51#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.21:23:48.51$vck44/valo=3,564.99 2006.145.21:23:48.51#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.21:23:48.51#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.21:23:48.51#ibcon#ireg 17 cls_cnt 0 2006.145.21:23:48.51#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.21:23:48.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.21:23:48.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.21:23:48.53#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.21:23:48.57#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.21:23:48.57#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.21:23:48.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.21:23:48.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.21:23:48.57$vck44/va=3,8 2006.145.21:23:48.57#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.21:23:48.57#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.21:23:48.57#ibcon#ireg 11 cls_cnt 2 2006.145.21:23:48.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.21:23:48.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.21:23:48.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.21:23:48.65#ibcon#[25=AT03-08\r\n] 2006.145.21:23:48.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.21:23:48.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.21:23:48.68#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.21:23:48.68#ibcon#ireg 7 cls_cnt 0 2006.145.21:23:48.68#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.21:23:48.80#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.21:23:48.80#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.21:23:48.82#ibcon#[25=USB\r\n] 2006.145.21:23:48.85#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.21:23:48.85#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.21:23:48.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.21:23:48.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.21:23:48.85$vck44/valo=4,624.99 2006.145.21:23:48.85#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.21:23:48.85#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.21:23:48.85#ibcon#ireg 17 cls_cnt 0 2006.145.21:23:48.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.21:23:48.85#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.21:23:48.85#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.21:23:48.87#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.21:23:48.91#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.21:23:48.91#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.21:23:48.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.21:23:48.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.21:23:48.91$vck44/va=4,7 2006.145.21:23:48.91#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.21:23:48.91#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.21:23:48.91#ibcon#ireg 11 cls_cnt 2 2006.145.21:23:48.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.21:23:48.97#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.21:23:48.97#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.21:23:48.99#ibcon#[25=AT04-07\r\n] 2006.145.21:23:49.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.21:23:49.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.21:23:49.02#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.21:23:49.02#ibcon#ireg 7 cls_cnt 0 2006.145.21:23:49.02#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.21:23:49.14#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.21:23:49.14#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.21:23:49.16#ibcon#[25=USB\r\n] 2006.145.21:23:49.19#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.21:23:49.19#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.21:23:49.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.21:23:49.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.21:23:49.19$vck44/valo=5,734.99 2006.145.21:23:49.19#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.21:23:49.19#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.21:23:49.19#ibcon#ireg 17 cls_cnt 0 2006.145.21:23:49.19#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.21:23:49.19#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.21:23:49.19#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.21:23:49.21#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.21:23:49.25#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.21:23:49.25#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.21:23:49.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.21:23:49.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.21:23:49.25$vck44/va=5,4 2006.145.21:23:49.25#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.21:23:49.25#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.21:23:49.25#ibcon#ireg 11 cls_cnt 2 2006.145.21:23:49.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.21:23:49.31#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.21:23:49.31#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.21:23:49.33#ibcon#[25=AT05-04\r\n] 2006.145.21:23:49.36#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.21:23:49.36#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.21:23:49.36#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.21:23:49.36#ibcon#ireg 7 cls_cnt 0 2006.145.21:23:49.36#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.21:23:49.39#abcon#<5=/08 1.5 3.5 17.41 811020.1\r\n> 2006.145.21:23:49.41#abcon#{5=INTERFACE CLEAR} 2006.145.21:23:49.48#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.21:23:49.48#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.21:23:49.48#abcon#[5=S1D000X0/0*\r\n] 2006.145.21:23:49.50#ibcon#[25=USB\r\n] 2006.145.21:23:49.53#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.21:23:49.53#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.21:23:49.53#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.21:23:49.53#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.21:23:49.53$vck44/valo=6,814.99 2006.145.21:23:49.53#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.21:23:49.53#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.21:23:49.53#ibcon#ireg 17 cls_cnt 0 2006.145.21:23:49.53#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.21:23:49.53#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.21:23:49.53#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.21:23:49.55#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.21:23:49.59#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.21:23:49.59#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.21:23:49.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.21:23:49.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.21:23:49.59$vck44/va=6,4 2006.145.21:23:49.59#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.21:23:49.59#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.21:23:49.59#ibcon#ireg 11 cls_cnt 2 2006.145.21:23:49.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.21:23:49.65#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.21:23:49.65#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.21:23:49.67#ibcon#[25=AT06-04\r\n] 2006.145.21:23:49.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.21:23:49.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.21:23:49.70#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.21:23:49.70#ibcon#ireg 7 cls_cnt 0 2006.145.21:23:49.70#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.21:23:49.82#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.21:23:49.82#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.21:23:49.84#ibcon#[25=USB\r\n] 2006.145.21:23:49.87#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.21:23:49.87#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.21:23:49.87#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.21:23:49.87#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.21:23:49.87$vck44/valo=7,864.99 2006.145.21:23:49.87#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.21:23:49.87#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.21:23:49.87#ibcon#ireg 17 cls_cnt 0 2006.145.21:23:49.87#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.21:23:49.87#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.21:23:49.87#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.21:23:49.89#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.21:23:49.93#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.21:23:49.93#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.21:23:49.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.21:23:49.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.21:23:49.93$vck44/va=7,4 2006.145.21:23:49.93#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.21:23:49.93#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.21:23:49.93#ibcon#ireg 11 cls_cnt 2 2006.145.21:23:49.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.21:23:49.99#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.21:23:49.99#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.21:23:50.01#ibcon#[25=AT07-04\r\n] 2006.145.21:23:50.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.21:23:50.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.21:23:50.04#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.21:23:50.04#ibcon#ireg 7 cls_cnt 0 2006.145.21:23:50.04#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.21:23:50.16#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.21:23:50.16#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.21:23:50.18#ibcon#[25=USB\r\n] 2006.145.21:23:50.21#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.21:23:50.21#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.21:23:50.21#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.21:23:50.21#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.21:23:50.21$vck44/valo=8,884.99 2006.145.21:23:50.21#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.21:23:50.21#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.21:23:50.21#ibcon#ireg 17 cls_cnt 0 2006.145.21:23:50.21#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.21:23:50.21#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.21:23:50.21#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.21:23:50.23#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.21:23:50.27#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.21:23:50.27#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.21:23:50.27#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.21:23:50.27#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.21:23:50.27$vck44/va=8,4 2006.145.21:23:50.27#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.21:23:50.27#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.21:23:50.27#ibcon#ireg 11 cls_cnt 2 2006.145.21:23:50.27#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.21:23:50.33#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.21:23:50.33#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.21:23:50.35#ibcon#[25=AT08-04\r\n] 2006.145.21:23:50.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.21:23:50.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.21:23:50.38#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.21:23:50.38#ibcon#ireg 7 cls_cnt 0 2006.145.21:23:50.38#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.21:23:50.50#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.21:23:50.50#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.21:23:50.52#ibcon#[25=USB\r\n] 2006.145.21:23:50.55#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.21:23:50.55#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.21:23:50.55#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.21:23:50.55#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.21:23:50.55$vck44/vblo=1,629.99 2006.145.21:23:50.55#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.21:23:50.55#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.21:23:50.55#ibcon#ireg 17 cls_cnt 0 2006.145.21:23:50.55#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.21:23:50.55#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.21:23:50.55#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.21:23:50.57#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.21:23:50.61#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.21:23:50.61#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.21:23:50.61#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.21:23:50.61#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.21:23:50.61$vck44/vb=1,3 2006.145.21:23:50.61#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.21:23:50.61#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.21:23:50.61#ibcon#ireg 11 cls_cnt 2 2006.145.21:23:50.61#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.21:23:50.61#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.21:23:50.61#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.21:23:50.63#ibcon#[27=AT01-03\r\n] 2006.145.21:23:50.66#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.21:23:50.66#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.21:23:50.66#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.21:23:50.66#ibcon#ireg 7 cls_cnt 0 2006.145.21:23:50.66#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.21:23:50.78#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.21:23:50.78#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.21:23:50.80#ibcon#[27=USB\r\n] 2006.145.21:23:50.83#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.21:23:50.83#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.21:23:50.83#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.21:23:50.83#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.21:23:50.83$vck44/vblo=2,634.99 2006.145.21:23:50.83#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.21:23:50.83#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.21:23:50.83#ibcon#ireg 17 cls_cnt 0 2006.145.21:23:50.83#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.21:23:50.83#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.21:23:50.83#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.21:23:50.85#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.21:23:50.89#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.21:23:50.89#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.21:23:50.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.21:23:50.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.21:23:50.89$vck44/vb=2,4 2006.145.21:23:50.89#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.21:23:50.89#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.21:23:50.89#ibcon#ireg 11 cls_cnt 2 2006.145.21:23:50.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.21:23:50.95#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.21:23:50.95#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.21:23:50.97#ibcon#[27=AT02-04\r\n] 2006.145.21:23:51.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.21:23:51.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.21:23:51.00#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.21:23:51.00#ibcon#ireg 7 cls_cnt 0 2006.145.21:23:51.00#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.21:23:51.12#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.21:23:51.12#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.21:23:51.14#ibcon#[27=USB\r\n] 2006.145.21:23:51.17#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.21:23:51.17#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.21:23:51.17#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.21:23:51.17#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.21:23:51.17$vck44/vblo=3,649.99 2006.145.21:23:51.17#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.21:23:51.17#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.21:23:51.17#ibcon#ireg 17 cls_cnt 0 2006.145.21:23:51.17#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.21:23:51.17#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.21:23:51.17#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.21:23:51.19#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.21:23:51.23#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.21:23:51.23#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.21:23:51.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.21:23:51.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.21:23:51.23$vck44/vb=3,4 2006.145.21:23:51.23#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.21:23:51.23#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.21:23:51.23#ibcon#ireg 11 cls_cnt 2 2006.145.21:23:51.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.21:23:51.29#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.21:23:51.29#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.21:23:51.31#ibcon#[27=AT03-04\r\n] 2006.145.21:23:51.34#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.21:23:51.34#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.21:23:51.34#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.21:23:51.34#ibcon#ireg 7 cls_cnt 0 2006.145.21:23:51.34#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.21:23:51.46#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.21:23:51.46#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.21:23:51.48#ibcon#[27=USB\r\n] 2006.145.21:23:51.51#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.21:23:51.51#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.21:23:51.51#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.21:23:51.51#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.21:23:51.51$vck44/vblo=4,679.99 2006.145.21:23:51.51#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.21:23:51.51#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.21:23:51.51#ibcon#ireg 17 cls_cnt 0 2006.145.21:23:51.51#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.21:23:51.51#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.21:23:51.51#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.21:23:51.53#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.21:23:51.57#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.21:23:51.57#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.21:23:51.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.21:23:51.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.21:23:51.57$vck44/vb=4,4 2006.145.21:23:51.57#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.21:23:51.57#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.21:23:51.57#ibcon#ireg 11 cls_cnt 2 2006.145.21:23:51.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.21:23:51.63#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.21:23:51.63#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.21:23:51.65#ibcon#[27=AT04-04\r\n] 2006.145.21:23:51.68#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.21:23:51.68#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.21:23:51.68#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.21:23:51.68#ibcon#ireg 7 cls_cnt 0 2006.145.21:23:51.68#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.21:23:51.80#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.21:23:51.80#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.21:23:51.82#ibcon#[27=USB\r\n] 2006.145.21:23:51.85#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.21:23:51.85#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.21:23:51.85#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.21:23:51.85#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.21:23:51.85$vck44/vblo=5,709.99 2006.145.21:23:51.85#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.21:23:51.85#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.21:23:51.85#ibcon#ireg 17 cls_cnt 0 2006.145.21:23:51.85#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.21:23:51.85#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.21:23:51.85#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.21:23:51.87#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.21:23:51.91#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.21:23:51.91#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.21:23:51.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.21:23:51.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.21:23:51.91$vck44/vb=5,4 2006.145.21:23:51.91#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.21:23:51.91#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.21:23:51.91#ibcon#ireg 11 cls_cnt 2 2006.145.21:23:51.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.21:23:51.97#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.21:23:51.97#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.21:23:51.99#ibcon#[27=AT05-04\r\n] 2006.145.21:23:52.02#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.21:23:52.02#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.21:23:52.02#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.21:23:52.02#ibcon#ireg 7 cls_cnt 0 2006.145.21:23:52.02#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.21:23:52.14#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.21:23:52.14#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.21:23:52.16#ibcon#[27=USB\r\n] 2006.145.21:23:52.19#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.21:23:52.19#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.21:23:52.19#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.21:23:52.19#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.21:23:52.19$vck44/vblo=6,719.99 2006.145.21:23:52.19#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.21:23:52.19#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.21:23:52.19#ibcon#ireg 17 cls_cnt 0 2006.145.21:23:52.19#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.21:23:52.19#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.21:23:52.19#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.21:23:52.21#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.21:23:52.25#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.21:23:52.25#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.21:23:52.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.21:23:52.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.21:23:52.25$vck44/vb=6,4 2006.145.21:23:52.25#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.21:23:52.25#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.21:23:52.25#ibcon#ireg 11 cls_cnt 2 2006.145.21:23:52.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.21:23:52.31#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.21:23:52.31#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.21:23:52.33#ibcon#[27=AT06-04\r\n] 2006.145.21:23:52.36#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.21:23:52.36#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.21:23:52.36#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.21:23:52.36#ibcon#ireg 7 cls_cnt 0 2006.145.21:23:52.36#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.21:23:52.48#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.21:23:52.48#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.21:23:52.50#ibcon#[27=USB\r\n] 2006.145.21:23:52.53#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.21:23:52.53#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.21:23:52.53#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.21:23:52.53#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.21:23:52.53$vck44/vblo=7,734.99 2006.145.21:23:52.53#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.21:23:52.53#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.21:23:52.53#ibcon#ireg 17 cls_cnt 0 2006.145.21:23:52.53#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.21:23:52.53#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.21:23:52.53#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.21:23:52.55#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.21:23:52.59#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.21:23:52.59#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.21:23:52.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.21:23:52.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.21:23:52.59$vck44/vb=7,4 2006.145.21:23:52.59#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.21:23:52.59#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.21:23:52.59#ibcon#ireg 11 cls_cnt 2 2006.145.21:23:52.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.21:23:52.65#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.21:23:52.65#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.21:23:52.67#ibcon#[27=AT07-04\r\n] 2006.145.21:23:52.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.21:23:52.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.21:23:52.70#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.21:23:52.70#ibcon#ireg 7 cls_cnt 0 2006.145.21:23:52.70#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.21:23:52.82#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.21:23:52.82#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.21:23:52.84#ibcon#[27=USB\r\n] 2006.145.21:23:52.87#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.21:23:52.87#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.21:23:52.87#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.21:23:52.87#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.21:23:52.87$vck44/vblo=8,744.99 2006.145.21:23:52.87#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.21:23:52.87#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.21:23:52.87#ibcon#ireg 17 cls_cnt 0 2006.145.21:23:52.87#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.21:23:52.87#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.21:23:52.87#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.21:23:52.89#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.21:23:52.93#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.21:23:52.93#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.21:23:52.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.21:23:52.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.21:23:52.93$vck44/vb=8,4 2006.145.21:23:52.93#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.21:23:52.93#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.21:23:52.93#ibcon#ireg 11 cls_cnt 2 2006.145.21:23:52.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.21:23:52.99#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.21:23:52.99#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.21:23:53.01#ibcon#[27=AT08-04\r\n] 2006.145.21:23:53.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.21:23:53.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.21:23:53.04#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.21:23:53.04#ibcon#ireg 7 cls_cnt 0 2006.145.21:23:53.04#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.21:23:53.16#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.21:23:53.16#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.21:23:53.18#ibcon#[27=USB\r\n] 2006.145.21:23:53.21#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.21:23:53.21#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.21:23:53.21#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.21:23:53.21#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.21:23:53.21$vck44/vabw=wide 2006.145.21:23:53.21#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.21:23:53.21#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.21:23:53.21#ibcon#ireg 8 cls_cnt 0 2006.145.21:23:53.21#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.21:23:53.21#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.21:23:53.21#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.21:23:53.23#ibcon#[25=BW32\r\n] 2006.145.21:23:53.26#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.21:23:53.26#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.21:23:53.26#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.21:23:53.26#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.21:23:53.26$vck44/vbbw=wide 2006.145.21:23:53.26#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.21:23:53.26#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.21:23:53.26#ibcon#ireg 8 cls_cnt 0 2006.145.21:23:53.26#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.21:23:53.33#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.21:23:53.33#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.21:23:53.35#ibcon#[27=BW32\r\n] 2006.145.21:23:53.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.21:23:53.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.21:23:53.38#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.21:23:53.38#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.21:23:53.38$setupk4/ifdk4 2006.145.21:23:53.38$ifdk4/lo= 2006.145.21:23:53.38$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.21:23:53.38$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.21:23:53.38$ifdk4/patch= 2006.145.21:23:53.38$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.21:23:53.38$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.21:23:53.38$setupk4/!*+20s 2006.145.21:23:59.58#abcon#<5=/08 1.5 3.6 17.41 811020.1\r\n> 2006.145.21:23:59.60#abcon#{5=INTERFACE CLEAR} 2006.145.21:23:59.66#abcon#[5=S1D000X0/0*\r\n] 2006.145.21:24:07.87$setupk4/"tpicd 2006.145.21:24:07.87$setupk4/echo=off 2006.145.21:24:07.87$setupk4/xlog=off 2006.145.21:24:07.87:!2006.145.21:24:39 2006.145.21:24:09.14#trakl#Source acquired 2006.145.21:24:11.14#flagr#flagr/antenna,acquired 2006.145.21:24:39.02:preob 2006.145.21:24:40.14/onsource/TRACKING 2006.145.21:24:40.14:!2006.145.21:24:49 2006.145.21:24:49.02:"tape 2006.145.21:24:49.02:"st=record 2006.145.21:24:49.02:data_valid=on 2006.145.21:24:49.02:midob 2006.145.21:24:50.14/onsource/TRACKING 2006.145.21:24:50.14/wx/17.41,1020.1,81 2006.145.21:24:50.33/cable/+6.5496E-03 2006.145.21:24:51.42/va/01,08,usb,yes,31,33 2006.145.21:24:51.42/va/02,07,usb,yes,33,34 2006.145.21:24:51.42/va/03,08,usb,yes,30,31 2006.145.21:24:51.42/va/04,07,usb,yes,34,36 2006.145.21:24:51.42/va/05,04,usb,yes,30,30 2006.145.21:24:51.42/va/06,04,usb,yes,33,33 2006.145.21:24:51.42/va/07,04,usb,yes,34,35 2006.145.21:24:51.42/va/08,04,usb,yes,29,35 2006.145.21:24:51.65/valo/01,524.99,yes,locked 2006.145.21:24:51.65/valo/02,534.99,yes,locked 2006.145.21:24:51.65/valo/03,564.99,yes,locked 2006.145.21:24:51.65/valo/04,624.99,yes,locked 2006.145.21:24:51.65/valo/05,734.99,yes,locked 2006.145.21:24:51.65/valo/06,814.99,yes,locked 2006.145.21:24:51.65/valo/07,864.99,yes,locked 2006.145.21:24:51.65/valo/08,884.99,yes,locked 2006.145.21:24:52.74/vb/01,03,usb,yes,35,32 2006.145.21:24:52.74/vb/02,04,usb,yes,30,30 2006.145.21:24:52.74/vb/03,04,usb,yes,27,30 2006.145.21:24:52.74/vb/04,04,usb,yes,31,30 2006.145.21:24:52.74/vb/05,04,usb,yes,24,27 2006.145.21:24:52.74/vb/06,04,usb,yes,29,25 2006.145.21:24:52.74/vb/07,04,usb,yes,28,28 2006.145.21:24:52.74/vb/08,04,usb,yes,26,29 2006.145.21:24:52.98/vblo/01,629.99,yes,locked 2006.145.21:24:52.98/vblo/02,634.99,yes,locked 2006.145.21:24:52.98/vblo/03,649.99,yes,locked 2006.145.21:24:52.98/vblo/04,679.99,yes,locked 2006.145.21:24:52.98/vblo/05,709.99,yes,locked 2006.145.21:24:52.98/vblo/06,719.99,yes,locked 2006.145.21:24:52.98/vblo/07,734.99,yes,locked 2006.145.21:24:52.98/vblo/08,744.99,yes,locked 2006.145.21:24:53.13/vabw/8 2006.145.21:24:53.28/vbbw/8 2006.145.21:24:53.37/xfe/off,on,15.5 2006.145.21:24:53.75/ifatt/23,28,28,28 2006.145.21:24:54.08/fmout-gps/S +4.6E-08 2006.145.21:24:54.16:!2006.145.21:37:53 2006.145.21:37:53.00:data_valid=off 2006.145.21:37:53.01:"et 2006.145.21:37:53.01:!+3s 2006.145.21:37:56.02:"tape 2006.145.21:37:56.03:postob 2006.145.21:37:56.12/cable/+6.5489E-03 2006.145.21:37:56.13/wx/17.46,1020.2,82 2006.145.21:37:56.21/fmout-gps/S +4.0E-08 2006.145.21:37:56.21:scan_name=145-2139,jd0605,120 2006.145.21:37:56.21:source=2201+315,220314.98,314538.3,2000.0,cw 2006.145.21:37:57.14#flagr#flagr/antenna,new-source 2006.145.21:37:57.15:checkk5 2006.145.21:37:57.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.21:37:58.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.21:37:58.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.21:37:58.92/chk_autoobs//k5ts4/ autoobs is running! 2006.145.21:37:59.64/chk_obsdata//k5ts1/T1452124??a.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.21:38:00.38/chk_obsdata//k5ts2/T1452124??b.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.21:38:01.12/chk_obsdata//k5ts3/T1452124??c.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.21:38:01.89/chk_obsdata//k5ts4/T1452124??d.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.145.21:38:02.65/k5log//k5ts1_log_newline 2006.145.21:38:03.39/k5log//k5ts2_log_newline 2006.145.21:38:04.13/k5log//k5ts3_log_newline 2006.145.21:38:04.89/k5log//k5ts4_log_newline 2006.145.21:38:04.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.21:38:04.91:setupk4=1 2006.145.21:38:04.91$setupk4/echo=on 2006.145.21:38:04.91$setupk4/pcalon 2006.145.21:38:04.91$pcalon/"no phase cal control is implemented here 2006.145.21:38:04.91$setupk4/"tpicd=stop 2006.145.21:38:04.91$setupk4/"rec=synch_on 2006.145.21:38:04.91$setupk4/"rec_mode=128 2006.145.21:38:04.91$setupk4/!* 2006.145.21:38:04.91$setupk4/recpk4 2006.145.21:38:04.91$recpk4/recpatch= 2006.145.21:38:04.92$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.21:38:04.92$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.21:38:04.92$setupk4/vck44 2006.145.21:38:04.92$vck44/valo=1,524.99 2006.145.21:38:04.92#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.21:38:04.92#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.21:38:04.92#ibcon#ireg 17 cls_cnt 0 2006.145.21:38:04.92#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:38:04.92#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:38:04.92#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:38:04.96#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.21:38:05.00#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:38:05.00#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:38:05.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.21:38:05.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.21:38:05.00$vck44/va=1,8 2006.145.21:38:05.00#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.21:38:05.00#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.21:38:05.00#ibcon#ireg 11 cls_cnt 2 2006.145.21:38:05.00#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.21:38:05.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.21:38:05.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.21:38:05.02#ibcon#[25=AT01-08\r\n] 2006.145.21:38:05.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.21:38:05.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.21:38:05.05#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.21:38:05.05#ibcon#ireg 7 cls_cnt 0 2006.145.21:38:05.05#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.21:38:05.19#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.21:38:05.19#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.21:38:05.21#ibcon#[25=USB\r\n] 2006.145.21:38:05.24#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.21:38:05.24#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.21:38:05.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.21:38:05.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.21:38:05.24$vck44/valo=2,534.99 2006.145.21:38:05.24#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.21:38:05.24#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.21:38:05.24#ibcon#ireg 17 cls_cnt 0 2006.145.21:38:05.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.21:38:05.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.21:38:05.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.21:38:05.27#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.21:38:05.31#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.21:38:05.31#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.21:38:05.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.21:38:05.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.21:38:05.31$vck44/va=2,7 2006.145.21:38:05.31#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.21:38:05.31#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.21:38:05.31#ibcon#ireg 11 cls_cnt 2 2006.145.21:38:05.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.21:38:05.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.21:38:05.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.21:38:05.38#ibcon#[25=AT02-07\r\n] 2006.145.21:38:05.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.21:38:05.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.21:38:05.41#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.21:38:05.41#ibcon#ireg 7 cls_cnt 0 2006.145.21:38:05.41#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.21:38:05.53#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.21:38:05.53#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.21:38:05.55#ibcon#[25=USB\r\n] 2006.145.21:38:05.58#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.21:38:05.58#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.21:38:05.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.21:38:05.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.21:38:05.58$vck44/valo=3,564.99 2006.145.21:38:05.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.21:38:05.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.21:38:05.58#ibcon#ireg 17 cls_cnt 0 2006.145.21:38:05.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:38:05.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:38:05.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:38:05.60#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.21:38:05.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:38:05.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:38:05.64#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.21:38:05.64#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.21:38:05.64$vck44/va=3,8 2006.145.21:38:05.64#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.21:38:05.64#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.21:38:05.64#ibcon#ireg 11 cls_cnt 2 2006.145.21:38:05.64#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:38:05.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:38:05.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:38:05.72#ibcon#[25=AT03-08\r\n] 2006.145.21:38:05.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:38:05.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:38:05.75#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.21:38:05.75#ibcon#ireg 7 cls_cnt 0 2006.145.21:38:05.75#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:38:05.87#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:38:05.87#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:38:05.89#ibcon#[25=USB\r\n] 2006.145.21:38:05.92#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:38:05.92#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:38:05.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.21:38:05.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.21:38:05.92$vck44/valo=4,624.99 2006.145.21:38:05.92#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.21:38:05.92#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.21:38:05.92#ibcon#ireg 17 cls_cnt 0 2006.145.21:38:05.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:38:05.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:38:05.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:38:05.94#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.21:38:05.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:38:05.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:38:05.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.21:38:05.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.21:38:05.98$vck44/va=4,7 2006.145.21:38:05.98#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.21:38:05.98#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.21:38:05.98#ibcon#ireg 11 cls_cnt 2 2006.145.21:38:05.98#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:38:06.04#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:38:06.04#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:38:06.06#ibcon#[25=AT04-07\r\n] 2006.145.21:38:06.09#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:38:06.09#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:38:06.09#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.21:38:06.09#ibcon#ireg 7 cls_cnt 0 2006.145.21:38:06.09#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:38:06.21#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:38:06.21#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:38:06.23#ibcon#[25=USB\r\n] 2006.145.21:38:06.26#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:38:06.26#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:38:06.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.21:38:06.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.21:38:06.26$vck44/valo=5,734.99 2006.145.21:38:06.26#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.21:38:06.26#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.21:38:06.26#ibcon#ireg 17 cls_cnt 0 2006.145.21:38:06.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:38:06.26#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:38:06.26#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:38:06.28#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.21:38:06.32#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:38:06.32#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:38:06.32#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.21:38:06.32#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.21:38:06.32$vck44/va=5,4 2006.145.21:38:06.32#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.21:38:06.32#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.21:38:06.32#ibcon#ireg 11 cls_cnt 2 2006.145.21:38:06.32#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:38:06.38#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:38:06.38#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:38:06.40#ibcon#[25=AT05-04\r\n] 2006.145.21:38:06.43#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:38:06.43#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:38:06.43#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.21:38:06.43#ibcon#ireg 7 cls_cnt 0 2006.145.21:38:06.43#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:38:06.55#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:38:06.55#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:38:06.57#ibcon#[25=USB\r\n] 2006.145.21:38:06.60#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:38:06.60#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:38:06.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.21:38:06.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.21:38:06.60$vck44/valo=6,814.99 2006.145.21:38:06.60#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.21:38:06.60#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.21:38:06.60#ibcon#ireg 17 cls_cnt 0 2006.145.21:38:06.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.21:38:06.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.21:38:06.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.21:38:06.63#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.21:38:06.67#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.21:38:06.67#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.21:38:06.67#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.21:38:06.67#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.21:38:06.67$vck44/va=6,4 2006.145.21:38:06.67#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.21:38:06.67#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.21:38:06.67#ibcon#ireg 11 cls_cnt 2 2006.145.21:38:06.67#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.21:38:06.72#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.21:38:06.72#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.21:38:06.74#ibcon#[25=AT06-04\r\n] 2006.145.21:38:06.77#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.21:38:06.77#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.21:38:06.77#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.21:38:06.77#ibcon#ireg 7 cls_cnt 0 2006.145.21:38:06.77#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.21:38:06.89#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.21:38:06.89#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.21:38:06.91#ibcon#[25=USB\r\n] 2006.145.21:38:06.94#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.21:38:06.94#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.21:38:06.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.21:38:06.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.21:38:06.94$vck44/valo=7,864.99 2006.145.21:38:06.94#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.21:38:06.94#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.21:38:06.94#ibcon#ireg 17 cls_cnt 0 2006.145.21:38:06.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:38:06.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:38:06.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:38:06.96#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.21:38:07.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:38:07.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:38:07.00#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.21:38:07.00#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.21:38:07.00$vck44/va=7,4 2006.145.21:38:07.00#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.21:38:07.00#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.21:38:07.00#ibcon#ireg 11 cls_cnt 2 2006.145.21:38:07.00#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:38:07.06#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:38:07.06#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:38:07.08#ibcon#[25=AT07-04\r\n] 2006.145.21:38:07.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:38:07.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:38:07.11#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.21:38:07.11#ibcon#ireg 7 cls_cnt 0 2006.145.21:38:07.11#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:38:07.23#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:38:07.23#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:38:07.25#ibcon#[25=USB\r\n] 2006.145.21:38:07.28#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:38:07.28#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:38:07.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.21:38:07.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.21:38:07.28$vck44/valo=8,884.99 2006.145.21:38:07.28#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.21:38:07.28#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.21:38:07.28#ibcon#ireg 17 cls_cnt 0 2006.145.21:38:07.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:38:07.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:38:07.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:38:07.30#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.21:38:07.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:38:07.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:38:07.34#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.21:38:07.34#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.21:38:07.34$vck44/va=8,4 2006.145.21:38:07.34#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.21:38:07.34#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.21:38:07.34#ibcon#ireg 11 cls_cnt 2 2006.145.21:38:07.34#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.21:38:07.40#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.21:38:07.40#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.21:38:07.42#ibcon#[25=AT08-04\r\n] 2006.145.21:38:07.45#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.21:38:07.45#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.21:38:07.45#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.21:38:07.45#ibcon#ireg 7 cls_cnt 0 2006.145.21:38:07.45#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.21:38:07.57#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.21:38:07.57#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.21:38:07.59#ibcon#[25=USB\r\n] 2006.145.21:38:07.62#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.21:38:07.62#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.21:38:07.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.21:38:07.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.21:38:07.62$vck44/vblo=1,629.99 2006.145.21:38:07.62#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.21:38:07.62#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.21:38:07.62#ibcon#ireg 17 cls_cnt 0 2006.145.21:38:07.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.21:38:07.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.21:38:07.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.21:38:07.65#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.21:38:07.69#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.21:38:07.69#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.21:38:07.69#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.21:38:07.69#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.21:38:07.69$vck44/vb=1,3 2006.145.21:38:07.69#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.21:38:07.69#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.21:38:07.69#ibcon#ireg 11 cls_cnt 2 2006.145.21:38:07.69#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.21:38:07.69#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.21:38:07.69#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.21:38:07.71#ibcon#[27=AT01-03\r\n] 2006.145.21:38:07.74#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.21:38:07.74#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.21:38:07.74#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.21:38:07.74#ibcon#ireg 7 cls_cnt 0 2006.145.21:38:07.74#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.21:38:07.86#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.21:38:07.86#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.21:38:07.88#ibcon#[27=USB\r\n] 2006.145.21:38:07.91#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.21:38:07.91#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.21:38:07.91#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.21:38:07.91#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.21:38:07.91$vck44/vblo=2,634.99 2006.145.21:38:07.91#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.21:38:07.91#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.21:38:07.91#ibcon#ireg 17 cls_cnt 0 2006.145.21:38:07.91#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:38:07.91#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:38:07.91#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:38:07.93#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.21:38:07.97#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:38:07.97#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:38:07.97#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.21:38:07.97#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.21:38:07.97$vck44/vb=2,4 2006.145.21:38:07.97#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.21:38:07.97#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.21:38:07.97#ibcon#ireg 11 cls_cnt 2 2006.145.21:38:07.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.21:38:08.03#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.21:38:08.03#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.21:38:08.05#ibcon#[27=AT02-04\r\n] 2006.145.21:38:08.08#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.21:38:08.08#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.21:38:08.08#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.21:38:08.08#ibcon#ireg 7 cls_cnt 0 2006.145.21:38:08.08#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.21:38:08.20#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.21:38:08.20#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.21:38:08.22#ibcon#[27=USB\r\n] 2006.145.21:38:08.25#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.21:38:08.25#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.21:38:08.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.21:38:08.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.21:38:08.25$vck44/vblo=3,649.99 2006.145.21:38:08.25#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.21:38:08.25#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.21:38:08.25#ibcon#ireg 17 cls_cnt 0 2006.145.21:38:08.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.21:38:08.25#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.21:38:08.25#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.21:38:08.27#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.21:38:08.31#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.21:38:08.31#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.21:38:08.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.21:38:08.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.21:38:08.31$vck44/vb=3,4 2006.145.21:38:08.31#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.21:38:08.31#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.21:38:08.31#ibcon#ireg 11 cls_cnt 2 2006.145.21:38:08.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.21:38:08.37#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.21:38:08.37#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.21:38:08.39#ibcon#[27=AT03-04\r\n] 2006.145.21:38:08.42#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.21:38:08.42#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.21:38:08.42#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.21:38:08.42#ibcon#ireg 7 cls_cnt 0 2006.145.21:38:08.42#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.21:38:08.54#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.21:38:08.54#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.21:38:08.56#ibcon#[27=USB\r\n] 2006.145.21:38:08.59#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.21:38:08.59#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.21:38:08.59#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.21:38:08.59#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.21:38:08.59$vck44/vblo=4,679.99 2006.145.21:38:08.59#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.21:38:08.59#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.21:38:08.59#ibcon#ireg 17 cls_cnt 0 2006.145.21:38:08.59#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:38:08.59#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:38:08.59#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:38:08.61#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.21:38:08.65#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:38:08.65#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:38:08.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.21:38:08.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.21:38:08.65$vck44/vb=4,4 2006.145.21:38:08.65#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.21:38:08.65#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.21:38:08.65#ibcon#ireg 11 cls_cnt 2 2006.145.21:38:08.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:38:08.71#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:38:08.71#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:38:08.73#ibcon#[27=AT04-04\r\n] 2006.145.21:38:08.76#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:38:08.76#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:38:08.76#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.21:38:08.76#ibcon#ireg 7 cls_cnt 0 2006.145.21:38:08.76#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:38:08.88#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:38:08.88#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:38:08.90#ibcon#[27=USB\r\n] 2006.145.21:38:08.93#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:38:08.93#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:38:08.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.21:38:08.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.21:38:08.93$vck44/vblo=5,709.99 2006.145.21:38:08.93#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.21:38:08.93#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.21:38:08.93#ibcon#ireg 17 cls_cnt 0 2006.145.21:38:08.93#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:38:08.93#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:38:08.93#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:38:08.95#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.21:38:08.99#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:38:08.99#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:38:08.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.21:38:08.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.21:38:08.99$vck44/vb=5,4 2006.145.21:38:08.99#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.21:38:08.99#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.21:38:08.99#ibcon#ireg 11 cls_cnt 2 2006.145.21:38:08.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:38:09.05#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:38:09.05#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:38:09.07#ibcon#[27=AT05-04\r\n] 2006.145.21:38:09.10#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:38:09.10#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:38:09.10#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.21:38:09.10#ibcon#ireg 7 cls_cnt 0 2006.145.21:38:09.10#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:38:09.22#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:38:09.22#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:38:09.24#ibcon#[27=USB\r\n] 2006.145.21:38:09.27#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:38:09.27#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:38:09.27#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.21:38:09.27#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.21:38:09.27$vck44/vblo=6,719.99 2006.145.21:38:09.27#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.21:38:09.27#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.21:38:09.27#ibcon#ireg 17 cls_cnt 0 2006.145.21:38:09.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:38:09.27#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:38:09.27#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:38:09.29#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.21:38:09.33#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:38:09.33#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:38:09.33#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.21:38:09.33#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.21:38:09.33$vck44/vb=6,4 2006.145.21:38:09.33#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.21:38:09.33#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.21:38:09.33#ibcon#ireg 11 cls_cnt 2 2006.145.21:38:09.33#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:38:09.39#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:38:09.39#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:38:09.41#ibcon#[27=AT06-04\r\n] 2006.145.21:38:09.44#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:38:09.44#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:38:09.44#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.21:38:09.44#ibcon#ireg 7 cls_cnt 0 2006.145.21:38:09.44#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:38:09.56#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:38:09.56#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:38:09.58#ibcon#[27=USB\r\n] 2006.145.21:38:09.61#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:38:09.61#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:38:09.61#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.21:38:09.61#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.21:38:09.61$vck44/vblo=7,734.99 2006.145.21:38:09.61#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.21:38:09.61#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.21:38:09.61#ibcon#ireg 17 cls_cnt 0 2006.145.21:38:09.61#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.21:38:09.61#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.21:38:09.61#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.21:38:09.63#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.21:38:09.67#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.21:38:09.67#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.21:38:09.67#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.21:38:09.67#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.21:38:09.67$vck44/vb=7,4 2006.145.21:38:09.67#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.21:38:09.67#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.21:38:09.67#ibcon#ireg 11 cls_cnt 2 2006.145.21:38:09.67#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.21:38:09.73#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.21:38:09.73#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.21:38:09.75#ibcon#[27=AT07-04\r\n] 2006.145.21:38:09.78#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.21:38:09.78#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.21:38:09.78#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.21:38:09.78#ibcon#ireg 7 cls_cnt 0 2006.145.21:38:09.78#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.21:38:09.90#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.21:38:09.90#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.21:38:09.92#ibcon#[27=USB\r\n] 2006.145.21:38:09.95#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.21:38:09.95#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.21:38:09.95#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.21:38:09.95#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.21:38:09.95$vck44/vblo=8,744.99 2006.145.21:38:09.95#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.21:38:09.95#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.21:38:09.95#ibcon#ireg 17 cls_cnt 0 2006.145.21:38:09.95#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:38:09.95#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:38:09.95#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:38:09.97#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.21:38:10.01#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:38:10.01#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:38:10.01#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.21:38:10.01#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.21:38:10.01$vck44/vb=8,4 2006.145.21:38:10.01#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.21:38:10.01#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.21:38:10.01#ibcon#ireg 11 cls_cnt 2 2006.145.21:38:10.01#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:38:10.07#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:38:10.07#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:38:10.09#ibcon#[27=AT08-04\r\n] 2006.145.21:38:10.12#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:38:10.12#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:38:10.12#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.21:38:10.12#ibcon#ireg 7 cls_cnt 0 2006.145.21:38:10.12#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:38:10.24#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:38:10.24#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:38:10.26#ibcon#[27=USB\r\n] 2006.145.21:38:10.29#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:38:10.29#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:38:10.29#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.21:38:10.29#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.21:38:10.29$vck44/vabw=wide 2006.145.21:38:10.29#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.21:38:10.29#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.21:38:10.29#ibcon#ireg 8 cls_cnt 0 2006.145.21:38:10.29#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:38:10.29#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:38:10.29#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:38:10.31#ibcon#[25=BW32\r\n] 2006.145.21:38:10.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:38:10.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:38:10.34#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.21:38:10.34#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.21:38:10.34$vck44/vbbw=wide 2006.145.21:38:10.34#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.21:38:10.34#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.21:38:10.34#ibcon#ireg 8 cls_cnt 0 2006.145.21:38:10.34#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.21:38:10.41#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.21:38:10.41#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.21:38:10.43#ibcon#[27=BW32\r\n] 2006.145.21:38:10.46#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.21:38:10.46#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.21:38:10.46#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.21:38:10.46#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.21:38:10.46$setupk4/ifdk4 2006.145.21:38:10.46$ifdk4/lo= 2006.145.21:38:10.46$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.21:38:10.46$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.21:38:10.46$ifdk4/patch= 2006.145.21:38:10.46$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.21:38:10.46$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.21:38:10.46$setupk4/!*+20s 2006.145.21:38:14.37#abcon#<5=/08 1.4 3.7 17.46 821020.2\r\n> 2006.145.21:38:14.39#abcon#{5=INTERFACE CLEAR} 2006.145.21:38:14.45#abcon#[5=S1D000X0/0*\r\n] 2006.145.21:38:24.54#abcon#<5=/08 1.4 3.7 17.46 821020.2\r\n> 2006.145.21:38:24.56#abcon#{5=INTERFACE CLEAR} 2006.145.21:38:24.62#abcon#[5=S1D000X0/0*\r\n] 2006.145.21:38:24.92$setupk4/"tpicd 2006.145.21:38:24.92$setupk4/echo=off 2006.145.21:38:24.92$setupk4/xlog=off 2006.145.21:38:24.92:!2006.145.21:38:52 2006.145.21:38:27.13#trakl#Source acquired 2006.145.21:38:29.13#flagr#flagr/antenna,acquired 2006.145.21:38:52.00:preob 2006.145.21:38:52.13/onsource/TRACKING 2006.145.21:38:52.13:!2006.145.21:39:02 2006.145.21:39:02.00:"tape 2006.145.21:39:02.00:"st=record 2006.145.21:39:02.00:data_valid=on 2006.145.21:39:02.00:midob 2006.145.21:39:02.13/onsource/TRACKING 2006.145.21:39:02.13/wx/17.46,1020.2,81 2006.145.21:39:02.21/cable/+6.5494E-03 2006.145.21:39:03.30/va/01,08,usb,yes,28,30 2006.145.21:39:03.30/va/02,07,usb,yes,30,30 2006.145.21:39:03.30/va/03,08,usb,yes,27,28 2006.145.21:39:03.30/va/04,07,usb,yes,31,32 2006.145.21:39:03.30/va/05,04,usb,yes,27,27 2006.145.21:39:03.30/va/06,04,usb,yes,30,30 2006.145.21:39:03.30/va/07,04,usb,yes,30,32 2006.145.21:39:03.30/va/08,04,usb,yes,26,31 2006.145.21:39:03.53/valo/01,524.99,yes,locked 2006.145.21:39:03.53/valo/02,534.99,yes,locked 2006.145.21:39:03.53/valo/03,564.99,yes,locked 2006.145.21:39:03.53/valo/04,624.99,yes,locked 2006.145.21:39:03.53/valo/05,734.99,yes,locked 2006.145.21:39:03.53/valo/06,814.99,yes,locked 2006.145.21:39:03.53/valo/07,864.99,yes,locked 2006.145.21:39:03.53/valo/08,884.99,yes,locked 2006.145.21:39:04.62/vb/01,03,usb,yes,35,33 2006.145.21:39:04.62/vb/02,04,usb,yes,31,30 2006.145.21:39:04.62/vb/03,04,usb,yes,28,30 2006.145.21:39:04.62/vb/04,04,usb,yes,32,31 2006.145.21:39:04.62/vb/05,04,usb,yes,25,27 2006.145.21:39:04.62/vb/06,04,usb,yes,29,25 2006.145.21:39:04.62/vb/07,04,usb,yes,29,28 2006.145.21:39:04.62/vb/08,04,usb,yes,26,29 2006.145.21:39:04.85/vblo/01,629.99,yes,locked 2006.145.21:39:04.85/vblo/02,634.99,yes,locked 2006.145.21:39:04.85/vblo/03,649.99,yes,locked 2006.145.21:39:04.85/vblo/04,679.99,yes,locked 2006.145.21:39:04.85/vblo/05,709.99,yes,locked 2006.145.21:39:04.85/vblo/06,719.99,yes,locked 2006.145.21:39:04.85/vblo/07,734.99,yes,locked 2006.145.21:39:04.85/vblo/08,744.99,yes,locked 2006.145.21:39:05.00/vabw/8 2006.145.21:39:05.15/vbbw/8 2006.145.21:39:05.24/xfe/off,on,14.2 2006.145.21:39:05.67/ifatt/23,28,28,28 2006.145.21:39:06.07/fmout-gps/S +4.1E-08 2006.145.21:39:06.11:!2006.145.21:41:02 2006.145.21:41:02.01:data_valid=off 2006.145.21:41:02.01:"et 2006.145.21:41:02.01:!+3s 2006.145.21:41:05.02:"tape 2006.145.21:41:05.02:postob 2006.145.21:41:05.13/cable/+6.5485E-03 2006.145.21:41:05.13/wx/17.44,1020.2,82 2006.145.21:41:05.21/fmout-gps/S +4.1E-08 2006.145.21:41:05.21:scan_name=145-2147,jd0605,70 2006.145.21:41:05.21:source=0552+398,055530.81,394849.2,2000.0,cw 2006.145.21:41:06.14:checkk5 2006.145.21:41:06.14#flagr#flagr/antenna,new-source 2006.145.21:41:06.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.21:41:07.04/chk_autoobs//k5ts2/ autoobs is running! 2006.145.21:41:07.48/chk_autoobs//k5ts3/ autoobs is running! 2006.145.21:41:07.91/chk_autoobs//k5ts4/ autoobs is running! 2006.145.21:41:08.34/chk_obsdata//k5ts1/T1452139??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.145.21:41:08.77/chk_obsdata//k5ts2/T1452139??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.145.21:41:09.21/chk_obsdata//k5ts3/T1452139??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.145.21:41:09.67/chk_obsdata//k5ts4/T1452139??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.145.21:41:10.42/k5log//k5ts1_log_newline 2006.145.21:41:11.16/k5log//k5ts2_log_newline 2006.145.21:41:11.89/k5log//k5ts3_log_newline 2006.145.21:41:12.65/k5log//k5ts4_log_newline 2006.145.21:41:12.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.21:41:12.67:setupk4=1 2006.145.21:41:12.67$setupk4/echo=on 2006.145.21:41:12.67$setupk4/pcalon 2006.145.21:41:12.67$pcalon/"no phase cal control is implemented here 2006.145.21:41:12.67$setupk4/"tpicd=stop 2006.145.21:41:12.67$setupk4/"rec=synch_on 2006.145.21:41:12.67$setupk4/"rec_mode=128 2006.145.21:41:12.67$setupk4/!* 2006.145.21:41:12.67$setupk4/recpk4 2006.145.21:41:12.67$recpk4/recpatch= 2006.145.21:41:12.67$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.21:41:12.67$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.21:41:12.67$setupk4/vck44 2006.145.21:41:12.67$vck44/valo=1,524.99 2006.145.21:41:12.67#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.21:41:12.67#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.21:41:12.67#ibcon#ireg 17 cls_cnt 0 2006.145.21:41:12.67#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.21:41:12.67#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.21:41:12.67#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.21:41:12.72#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.21:41:12.76#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.21:41:12.76#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.21:41:12.76#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.21:41:12.76#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.21:41:12.76$vck44/va=1,8 2006.145.21:41:12.76#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.21:41:12.76#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.21:41:12.76#ibcon#ireg 11 cls_cnt 2 2006.145.21:41:12.76#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.21:41:12.76#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.21:41:12.76#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.21:41:12.78#ibcon#[25=AT01-08\r\n] 2006.145.21:41:12.81#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.21:41:12.81#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.21:41:12.81#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.21:41:12.81#ibcon#ireg 7 cls_cnt 0 2006.145.21:41:12.81#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.21:41:12.93#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.21:41:12.93#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.21:41:12.95#ibcon#[25=USB\r\n] 2006.145.21:41:12.98#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.21:41:12.98#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.21:41:12.98#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.21:41:12.98#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.21:41:12.98$vck44/valo=2,534.99 2006.145.21:41:12.98#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.21:41:12.98#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.21:41:12.98#ibcon#ireg 17 cls_cnt 0 2006.145.21:41:12.98#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.21:41:12.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.21:41:12.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.21:41:13.01#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.21:41:13.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.21:41:13.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.21:41:13.05#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.21:41:13.05#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.21:41:13.05$vck44/va=2,7 2006.145.21:41:13.05#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.21:41:13.05#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.21:41:13.05#ibcon#ireg 11 cls_cnt 2 2006.145.21:41:13.05#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.21:41:13.10#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.21:41:13.10#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.21:41:13.12#ibcon#[25=AT02-07\r\n] 2006.145.21:41:13.15#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.21:41:13.15#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.21:41:13.15#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.21:41:13.15#ibcon#ireg 7 cls_cnt 0 2006.145.21:41:13.15#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.21:41:13.27#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.21:41:13.27#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.21:41:13.29#ibcon#[25=USB\r\n] 2006.145.21:41:13.32#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.21:41:13.32#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.21:41:13.32#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.21:41:13.32#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.21:41:13.32$vck44/valo=3,564.99 2006.145.21:41:13.32#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.21:41:13.32#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.21:41:13.32#ibcon#ireg 17 cls_cnt 0 2006.145.21:41:13.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.21:41:13.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.21:41:13.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.21:41:13.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.21:41:13.38#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.21:41:13.38#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.21:41:13.38#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.21:41:13.38#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.21:41:13.38$vck44/va=3,8 2006.145.21:41:13.38#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.21:41:13.38#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.21:41:13.38#ibcon#ireg 11 cls_cnt 2 2006.145.21:41:13.38#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.21:41:13.44#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.21:41:13.44#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.21:41:13.46#ibcon#[25=AT03-08\r\n] 2006.145.21:41:13.49#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.21:41:13.49#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.21:41:13.49#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.21:41:13.49#ibcon#ireg 7 cls_cnt 0 2006.145.21:41:13.49#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.21:41:13.61#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.21:41:13.61#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.21:41:13.63#ibcon#[25=USB\r\n] 2006.145.21:41:13.66#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.21:41:13.66#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.21:41:13.66#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.21:41:13.66#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.21:41:13.66$vck44/valo=4,624.99 2006.145.21:41:13.66#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.21:41:13.66#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.21:41:13.66#ibcon#ireg 17 cls_cnt 0 2006.145.21:41:13.66#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.21:41:13.66#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.21:41:13.66#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.21:41:13.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.21:41:13.72#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.21:41:13.72#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.21:41:13.72#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.21:41:13.72#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.21:41:13.72$vck44/va=4,7 2006.145.21:41:13.72#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.21:41:13.72#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.21:41:13.72#ibcon#ireg 11 cls_cnt 2 2006.145.21:41:13.72#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.21:41:13.78#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.21:41:13.78#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.21:41:13.80#ibcon#[25=AT04-07\r\n] 2006.145.21:41:13.83#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.21:41:13.83#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.21:41:13.83#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.21:41:13.83#ibcon#ireg 7 cls_cnt 0 2006.145.21:41:13.83#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.21:41:13.95#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.21:41:13.95#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.21:41:13.97#ibcon#[25=USB\r\n] 2006.145.21:41:14.00#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.21:41:14.00#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.21:41:14.00#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.21:41:14.00#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.21:41:14.00$vck44/valo=5,734.99 2006.145.21:41:14.00#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.21:41:14.00#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.21:41:14.00#ibcon#ireg 17 cls_cnt 0 2006.145.21:41:14.00#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.21:41:14.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.21:41:14.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.21:41:14.03#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.21:41:14.08#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.21:41:14.08#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.21:41:14.08#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.21:41:14.08#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.21:41:14.08$vck44/va=5,4 2006.145.21:41:14.08#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.21:41:14.08#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.21:41:14.08#ibcon#ireg 11 cls_cnt 2 2006.145.21:41:14.08#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.21:41:14.12#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.21:41:14.12#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.21:41:14.14#ibcon#[25=AT05-04\r\n] 2006.145.21:41:14.17#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.21:41:14.17#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.21:41:14.17#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.21:41:14.17#ibcon#ireg 7 cls_cnt 0 2006.145.21:41:14.17#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.21:41:14.29#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.21:41:14.29#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.21:41:14.31#ibcon#[25=USB\r\n] 2006.145.21:41:14.34#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.21:41:14.34#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.21:41:14.34#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.21:41:14.34#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.21:41:14.34$vck44/valo=6,814.99 2006.145.21:41:14.34#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.21:41:14.34#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.21:41:14.34#ibcon#ireg 17 cls_cnt 0 2006.145.21:41:14.34#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.21:41:14.34#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.21:41:14.34#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.21:41:14.36#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.21:41:14.40#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.21:41:14.40#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.21:41:14.40#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.21:41:14.40#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.21:41:14.40$vck44/va=6,4 2006.145.21:41:14.40#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.21:41:14.40#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.21:41:14.40#ibcon#ireg 11 cls_cnt 2 2006.145.21:41:14.40#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.21:41:14.46#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.21:41:14.46#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.21:41:14.48#ibcon#[25=AT06-04\r\n] 2006.145.21:41:14.51#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.21:41:14.51#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.21:41:14.51#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.21:41:14.51#ibcon#ireg 7 cls_cnt 0 2006.145.21:41:14.51#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.21:41:14.63#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.21:41:14.63#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.21:41:14.65#ibcon#[25=USB\r\n] 2006.145.21:41:14.68#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.21:41:14.68#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.21:41:14.68#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.21:41:14.68#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.21:41:14.68$vck44/valo=7,864.99 2006.145.21:41:14.68#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.21:41:14.68#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.21:41:14.68#ibcon#ireg 17 cls_cnt 0 2006.145.21:41:14.68#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.21:41:14.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.21:41:14.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.21:41:14.70#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.21:41:14.74#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.21:41:14.74#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.21:41:14.74#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.21:41:14.74#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.21:41:14.74$vck44/va=7,4 2006.145.21:41:14.74#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.21:41:14.74#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.21:41:14.74#ibcon#ireg 11 cls_cnt 2 2006.145.21:41:14.74#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.21:41:14.80#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.21:41:14.80#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.21:41:14.82#ibcon#[25=AT07-04\r\n] 2006.145.21:41:14.85#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.21:41:14.85#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.21:41:14.85#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.21:41:14.85#ibcon#ireg 7 cls_cnt 0 2006.145.21:41:14.85#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.21:41:14.97#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.21:41:14.97#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.21:41:14.99#ibcon#[25=USB\r\n] 2006.145.21:41:15.02#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.21:41:15.02#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.21:41:15.02#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.21:41:15.02#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.21:41:15.02$vck44/valo=8,884.99 2006.145.21:41:15.02#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.21:41:15.02#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.21:41:15.02#ibcon#ireg 17 cls_cnt 0 2006.145.21:41:15.02#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.21:41:15.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.21:41:15.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.21:41:15.04#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.21:41:15.08#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.21:41:15.08#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.21:41:15.08#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.21:41:15.08#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.21:41:15.08$vck44/va=8,4 2006.145.21:41:15.08#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.21:41:15.08#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.21:41:15.08#ibcon#ireg 11 cls_cnt 2 2006.145.21:41:15.08#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.21:41:15.15#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.21:41:15.15#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.21:41:15.16#ibcon#[25=AT08-04\r\n] 2006.145.21:41:15.19#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.21:41:15.19#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.21:41:15.19#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.21:41:15.19#ibcon#ireg 7 cls_cnt 0 2006.145.21:41:15.19#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.21:41:15.31#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.21:41:15.31#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.21:41:15.33#ibcon#[25=USB\r\n] 2006.145.21:41:15.36#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.21:41:15.36#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.21:41:15.36#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.21:41:15.36#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.21:41:15.36$vck44/vblo=1,629.99 2006.145.21:41:15.36#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.21:41:15.36#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.21:41:15.36#ibcon#ireg 17 cls_cnt 0 2006.145.21:41:15.36#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.21:41:15.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.21:41:15.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.21:41:15.38#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.21:41:15.42#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.21:41:15.42#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.21:41:15.42#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.21:41:15.42#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.21:41:15.42$vck44/vb=1,3 2006.145.21:41:15.42#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.21:41:15.42#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.21:41:15.42#ibcon#ireg 11 cls_cnt 2 2006.145.21:41:15.42#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.21:41:15.42#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.21:41:15.42#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.21:41:15.44#ibcon#[27=AT01-03\r\n] 2006.145.21:41:15.47#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.21:41:15.47#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.21:41:15.47#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.21:41:15.47#ibcon#ireg 7 cls_cnt 0 2006.145.21:41:15.47#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.21:41:15.59#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.21:41:15.59#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.21:41:15.61#ibcon#[27=USB\r\n] 2006.145.21:41:15.64#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.21:41:15.64#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.21:41:15.64#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.21:41:15.64#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.21:41:15.64$vck44/vblo=2,634.99 2006.145.21:41:15.64#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.21:41:15.64#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.21:41:15.64#ibcon#ireg 17 cls_cnt 0 2006.145.21:41:15.64#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.21:41:15.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.21:41:15.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.21:41:15.66#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.21:41:15.70#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.21:41:15.70#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.21:41:15.70#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.21:41:15.70#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.21:41:15.70$vck44/vb=2,4 2006.145.21:41:15.70#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.21:41:15.70#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.21:41:15.70#ibcon#ireg 11 cls_cnt 2 2006.145.21:41:15.70#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.21:41:15.76#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.21:41:15.76#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.21:41:15.78#ibcon#[27=AT02-04\r\n] 2006.145.21:41:15.81#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.21:41:15.81#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.21:41:15.81#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.21:41:15.81#ibcon#ireg 7 cls_cnt 0 2006.145.21:41:15.81#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.21:41:15.93#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.21:41:15.93#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.21:41:15.95#ibcon#[27=USB\r\n] 2006.145.21:41:15.98#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.21:41:15.98#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.21:41:15.98#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.21:41:15.98#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.21:41:15.98$vck44/vblo=3,649.99 2006.145.21:41:15.98#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.21:41:15.98#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.21:41:15.98#ibcon#ireg 17 cls_cnt 0 2006.145.21:41:15.98#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.21:41:15.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.21:41:15.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.21:41:16.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.21:41:16.04#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.21:41:16.04#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.21:41:16.04#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.21:41:16.04#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.21:41:16.04$vck44/vb=3,4 2006.145.21:41:16.04#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.21:41:16.04#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.21:41:16.04#ibcon#ireg 11 cls_cnt 2 2006.145.21:41:16.04#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.21:41:16.10#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.21:41:16.10#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.21:41:16.12#ibcon#[27=AT03-04\r\n] 2006.145.21:41:16.15#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.21:41:16.15#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.21:41:16.15#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.21:41:16.15#ibcon#ireg 7 cls_cnt 0 2006.145.21:41:16.15#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.21:41:16.27#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.21:41:16.27#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.21:41:16.29#ibcon#[27=USB\r\n] 2006.145.21:41:16.32#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.21:41:16.32#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.21:41:16.32#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.21:41:16.32#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.21:41:16.32$vck44/vblo=4,679.99 2006.145.21:41:16.32#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.21:41:16.32#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.21:41:16.32#ibcon#ireg 17 cls_cnt 0 2006.145.21:41:16.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.21:41:16.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.21:41:16.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.21:41:16.34#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.21:41:16.38#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.21:41:16.38#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.21:41:16.38#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.21:41:16.38#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.21:41:16.38$vck44/vb=4,4 2006.145.21:41:16.38#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.21:41:16.38#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.21:41:16.38#ibcon#ireg 11 cls_cnt 2 2006.145.21:41:16.38#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.21:41:16.44#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.21:41:16.44#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.21:41:16.46#ibcon#[27=AT04-04\r\n] 2006.145.21:41:16.49#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.21:41:16.49#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.21:41:16.49#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.21:41:16.49#ibcon#ireg 7 cls_cnt 0 2006.145.21:41:16.49#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.21:41:16.61#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.21:41:16.61#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.21:41:16.63#ibcon#[27=USB\r\n] 2006.145.21:41:16.66#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.21:41:16.66#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.21:41:16.66#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.21:41:16.66#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.21:41:16.66$vck44/vblo=5,709.99 2006.145.21:41:16.66#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.21:41:16.66#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.21:41:16.66#ibcon#ireg 17 cls_cnt 0 2006.145.21:41:16.66#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.21:41:16.66#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.21:41:16.66#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.21:41:16.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.21:41:16.72#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.21:41:16.72#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.21:41:16.72#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.21:41:16.72#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.21:41:16.72$vck44/vb=5,4 2006.145.21:41:16.72#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.21:41:16.72#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.21:41:16.72#ibcon#ireg 11 cls_cnt 2 2006.145.21:41:16.72#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.21:41:16.78#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.21:41:16.78#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.21:41:16.80#ibcon#[27=AT05-04\r\n] 2006.145.21:41:16.83#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.21:41:16.83#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.21:41:16.83#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.21:41:16.83#ibcon#ireg 7 cls_cnt 0 2006.145.21:41:16.83#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.21:41:16.95#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.21:41:16.95#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.21:41:16.97#ibcon#[27=USB\r\n] 2006.145.21:41:17.00#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.21:41:17.00#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.21:41:17.00#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.21:41:17.00#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.21:41:17.00$vck44/vblo=6,719.99 2006.145.21:41:17.00#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.21:41:17.00#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.21:41:17.00#ibcon#ireg 17 cls_cnt 0 2006.145.21:41:17.00#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.21:41:17.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.21:41:17.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.21:41:17.02#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.21:41:17.06#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.21:41:17.06#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.21:41:17.06#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.21:41:17.06#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.21:41:17.06$vck44/vb=6,4 2006.145.21:41:17.06#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.21:41:17.06#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.21:41:17.06#ibcon#ireg 11 cls_cnt 2 2006.145.21:41:17.06#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.21:41:17.12#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.21:41:17.12#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.21:41:17.14#ibcon#[27=AT06-04\r\n] 2006.145.21:41:17.17#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.21:41:17.17#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.21:41:17.17#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.21:41:17.17#ibcon#ireg 7 cls_cnt 0 2006.145.21:41:17.17#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.21:41:17.29#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.21:41:17.29#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.21:41:17.31#ibcon#[27=USB\r\n] 2006.145.21:41:17.34#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.21:41:17.34#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.21:41:17.34#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.21:41:17.34#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.21:41:17.34$vck44/vblo=7,734.99 2006.145.21:41:17.34#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.21:41:17.34#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.21:41:17.34#ibcon#ireg 17 cls_cnt 0 2006.145.21:41:17.34#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.21:41:17.34#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.21:41:17.34#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.21:41:17.36#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.21:41:17.40#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.21:41:17.40#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.21:41:17.40#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.21:41:17.40#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.21:41:17.40$vck44/vb=7,4 2006.145.21:41:17.40#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.21:41:17.40#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.21:41:17.40#ibcon#ireg 11 cls_cnt 2 2006.145.21:41:17.40#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.21:41:17.46#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.21:41:17.46#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.21:41:17.48#ibcon#[27=AT07-04\r\n] 2006.145.21:41:17.51#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.21:41:17.51#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.21:41:17.51#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.21:41:17.51#ibcon#ireg 7 cls_cnt 0 2006.145.21:41:17.51#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.21:41:17.63#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.21:41:17.63#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.21:41:17.65#ibcon#[27=USB\r\n] 2006.145.21:41:17.68#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.21:41:17.68#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.21:41:17.68#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.21:41:17.68#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.21:41:17.68$vck44/vblo=8,744.99 2006.145.21:41:17.68#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.21:41:17.68#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.21:41:17.68#ibcon#ireg 17 cls_cnt 0 2006.145.21:41:17.68#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.21:41:17.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.21:41:17.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.21:41:17.70#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.21:41:17.74#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.21:41:17.74#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.21:41:17.74#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.21:41:17.74#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.21:41:17.74$vck44/vb=8,4 2006.145.21:41:17.74#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.21:41:17.74#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.21:41:17.74#ibcon#ireg 11 cls_cnt 2 2006.145.21:41:17.74#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.21:41:17.80#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.21:41:17.80#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.21:41:17.82#ibcon#[27=AT08-04\r\n] 2006.145.21:41:17.85#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.21:41:17.85#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.21:41:17.85#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.21:41:17.85#ibcon#ireg 7 cls_cnt 0 2006.145.21:41:17.85#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.21:41:17.88#abcon#<5=/07 1.5 3.7 17.43 821020.2\r\n> 2006.145.21:41:17.90#abcon#{5=INTERFACE CLEAR} 2006.145.21:41:17.96#abcon#[5=S1D000X0/0*\r\n] 2006.145.21:41:17.97#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.21:41:17.97#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.21:41:17.99#ibcon#[27=USB\r\n] 2006.145.21:41:18.02#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.21:41:18.02#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.21:41:18.02#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.21:41:18.02#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.21:41:18.02$vck44/vabw=wide 2006.145.21:41:18.02#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.21:41:18.02#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.21:41:18.02#ibcon#ireg 8 cls_cnt 0 2006.145.21:41:18.02#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.21:41:18.02#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.21:41:18.02#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.21:41:18.04#ibcon#[25=BW32\r\n] 2006.145.21:41:18.07#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.21:41:18.07#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.21:41:18.07#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.21:41:18.07#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.21:41:18.07$vck44/vbbw=wide 2006.145.21:41:18.07#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.21:41:18.07#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.21:41:18.07#ibcon#ireg 8 cls_cnt 0 2006.145.21:41:18.07#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.21:41:18.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.21:41:18.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.21:41:18.16#ibcon#[27=BW32\r\n] 2006.145.21:41:18.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.21:41:18.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.21:41:18.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.21:41:18.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.21:41:18.19$setupk4/ifdk4 2006.145.21:41:18.19$ifdk4/lo= 2006.145.21:41:18.19$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.21:41:18.19$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.21:41:18.19$ifdk4/patch= 2006.145.21:41:18.19$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.21:41:18.19$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.21:41:18.19$setupk4/!*+20s 2006.145.21:41:28.05#abcon#<5=/07 1.5 3.7 17.43 821020.1\r\n> 2006.145.21:41:28.07#abcon#{5=INTERFACE CLEAR} 2006.145.21:41:28.13#abcon#[5=S1D000X0/0*\r\n] 2006.145.21:41:32.68$setupk4/"tpicd 2006.145.21:41:32.68$setupk4/echo=off 2006.145.21:41:32.68$setupk4/xlog=off 2006.145.21:41:32.68:!2006.145.21:47:12 2006.145.21:42:22.14#trakl#Source acquired 2006.145.21:42:23.14#flagr#flagr/antenna,acquired 2006.145.21:47:12.00:preob 2006.145.21:47:12.13/onsource/TRACKING 2006.145.21:47:12.13:!2006.145.21:47:22 2006.145.21:47:22.00:"tape 2006.145.21:47:22.00:"st=record 2006.145.21:47:22.00:data_valid=on 2006.145.21:47:22.00:midob 2006.145.21:47:23.13/onsource/TRACKING 2006.145.21:47:23.13/wx/17.33,1020.2,84 2006.145.21:47:23.29/cable/+6.5473E-03 2006.145.21:47:24.38/va/01,08,usb,yes,31,33 2006.145.21:47:24.38/va/02,07,usb,yes,33,34 2006.145.21:47:24.38/va/03,08,usb,yes,30,32 2006.145.21:47:24.38/va/04,07,usb,yes,34,36 2006.145.21:47:24.38/va/05,04,usb,yes,30,30 2006.145.21:47:24.38/va/06,04,usb,yes,34,33 2006.145.21:47:24.38/va/07,04,usb,yes,34,35 2006.145.21:47:24.38/va/08,04,usb,yes,29,35 2006.145.21:47:24.61/valo/01,524.99,yes,locked 2006.145.21:47:24.61/valo/02,534.99,yes,locked 2006.145.21:47:24.61/valo/03,564.99,yes,locked 2006.145.21:47:24.61/valo/04,624.99,yes,locked 2006.145.21:47:24.61/valo/05,734.99,yes,locked 2006.145.21:47:24.61/valo/06,814.99,yes,locked 2006.145.21:47:24.61/valo/07,864.99,yes,locked 2006.145.21:47:24.61/valo/08,884.99,yes,locked 2006.145.21:47:25.70/vb/01,03,usb,yes,38,35 2006.145.21:47:25.70/vb/02,04,usb,yes,33,33 2006.145.21:47:25.70/vb/03,04,usb,yes,30,33 2006.145.21:47:25.70/vb/04,04,usb,yes,34,33 2006.145.21:47:25.70/vb/05,04,usb,yes,27,29 2006.145.21:47:25.70/vb/06,04,usb,yes,31,27 2006.145.21:47:25.70/vb/07,04,usb,yes,31,31 2006.145.21:47:25.70/vb/08,04,usb,yes,28,32 2006.145.21:47:25.93/vblo/01,629.99,yes,locked 2006.145.21:47:25.93/vblo/02,634.99,yes,locked 2006.145.21:47:25.93/vblo/03,649.99,yes,locked 2006.145.21:47:25.93/vblo/04,679.99,yes,locked 2006.145.21:47:25.93/vblo/05,709.99,yes,locked 2006.145.21:47:25.93/vblo/06,719.99,yes,locked 2006.145.21:47:25.93/vblo/07,734.99,yes,locked 2006.145.21:47:25.93/vblo/08,744.99,yes,locked 2006.145.21:47:26.08/vabw/8 2006.145.21:47:26.23/vbbw/8 2006.145.21:47:26.32/xfe/off,on,14.7 2006.145.21:47:26.71/ifatt/23,28,28,28 2006.145.21:47:27.07/fmout-gps/S +4.2E-08 2006.145.21:47:27.11:!2006.145.21:48:32 2006.145.21:48:32.00:data_valid=off 2006.145.21:48:32.00:"et 2006.145.21:48:32.01:!+3s 2006.145.21:48:35.02:"tape 2006.145.21:48:35.02:postob 2006.145.21:48:35.16/cable/+6.5482E-03 2006.145.21:48:35.16/wx/17.31,1020.2,84 2006.145.21:48:35.23/fmout-gps/S +4.2E-08 2006.145.21:48:35.23:scan_name=145-2154,jd0605,220 2006.145.21:48:35.23:source=1044+719,104827.62,714335.9,2000.0,neutral 2006.145.21:48:37.14#flagr#flagr/antenna,new-source 2006.145.21:48:37.14:checkk5 2006.145.21:48:37.56/chk_autoobs//k5ts1/ autoobs is running! 2006.145.21:48:37.99/chk_autoobs//k5ts2/ autoobs is running! 2006.145.21:48:38.43/chk_autoobs//k5ts3/ autoobs is running! 2006.145.21:48:38.87/chk_autoobs//k5ts4/ autoobs is running! 2006.145.21:48:39.31/chk_obsdata//k5ts1/T1452147??a.dat file size is correct (nominal:280MB, actual:280MB). 2006.145.21:48:39.77/chk_obsdata//k5ts2/T1452147??b.dat file size is correct (nominal:280MB, actual:280MB). 2006.145.21:48:40.21/chk_obsdata//k5ts3/T1452147??c.dat file size is correct (nominal:280MB, actual:280MB). 2006.145.21:48:40.67/chk_obsdata//k5ts4/T1452147??d.dat file size is correct (nominal:280MB, actual:280MB). 2006.145.21:48:41.44/k5log//k5ts1_log_newline 2006.145.21:48:42.20/k5log//k5ts2_log_newline 2006.145.21:48:42.94/k5log//k5ts3_log_newline 2006.145.21:48:43.67/k5log//k5ts4_log_newline 2006.145.21:48:43.69/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.21:48:43.69:setupk4=1 2006.145.21:48:43.69$setupk4/echo=on 2006.145.21:48:43.69$setupk4/pcalon 2006.145.21:48:43.69$pcalon/"no phase cal control is implemented here 2006.145.21:48:43.69$setupk4/"tpicd=stop 2006.145.21:48:43.69$setupk4/"rec=synch_on 2006.145.21:48:43.69$setupk4/"rec_mode=128 2006.145.21:48:43.69$setupk4/!* 2006.145.21:48:43.69$setupk4/recpk4 2006.145.21:48:43.69$recpk4/recpatch= 2006.145.21:48:43.69$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.21:48:43.69$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.21:48:43.69$setupk4/vck44 2006.145.21:48:43.69$vck44/valo=1,524.99 2006.145.21:48:43.69#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.21:48:43.69#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.21:48:43.69#ibcon#ireg 17 cls_cnt 0 2006.145.21:48:43.69#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.21:48:43.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.21:48:43.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.21:48:43.71#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.21:48:43.76#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.21:48:43.76#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.21:48:43.76#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.21:48:43.76#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.21:48:43.76$vck44/va=1,8 2006.145.21:48:43.76#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.21:48:43.76#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.21:48:43.76#ibcon#ireg 11 cls_cnt 2 2006.145.21:48:43.76#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.21:48:43.76#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.21:48:43.76#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.21:48:43.78#ibcon#[25=AT01-08\r\n] 2006.145.21:48:43.81#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.21:48:43.81#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.21:48:43.81#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.21:48:43.81#ibcon#ireg 7 cls_cnt 0 2006.145.21:48:43.81#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.21:48:43.93#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.21:48:43.93#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.21:48:43.95#ibcon#[25=USB\r\n] 2006.145.21:48:43.98#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.21:48:43.98#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.21:48:43.98#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.21:48:43.98#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.21:48:43.98$vck44/valo=2,534.99 2006.145.21:48:43.98#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.21:48:43.98#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.21:48:43.98#ibcon#ireg 17 cls_cnt 0 2006.145.21:48:43.98#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.21:48:43.98#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.21:48:43.98#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.21:48:44.01#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.21:48:44.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.21:48:44.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.21:48:44.05#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.21:48:44.05#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.21:48:44.05$vck44/va=2,7 2006.145.21:48:44.05#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.21:48:44.05#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.21:48:44.05#ibcon#ireg 11 cls_cnt 2 2006.145.21:48:44.05#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.21:48:44.10#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.21:48:44.10#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.21:48:44.12#ibcon#[25=AT02-07\r\n] 2006.145.21:48:44.15#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.21:48:44.15#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.21:48:44.15#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.21:48:44.15#ibcon#ireg 7 cls_cnt 0 2006.145.21:48:44.15#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.21:48:44.27#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.21:48:44.27#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.21:48:44.29#ibcon#[25=USB\r\n] 2006.145.21:48:44.32#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.21:48:44.32#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.21:48:44.32#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.21:48:44.32#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.21:48:44.32$vck44/valo=3,564.99 2006.145.21:48:44.32#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.21:48:44.32#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.21:48:44.32#ibcon#ireg 17 cls_cnt 0 2006.145.21:48:44.32#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:48:44.32#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:48:44.32#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:48:44.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.21:48:44.38#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:48:44.38#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:48:44.38#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.21:48:44.38#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.21:48:44.38$vck44/va=3,8 2006.145.21:48:44.38#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.21:48:44.38#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.21:48:44.38#ibcon#ireg 11 cls_cnt 2 2006.145.21:48:44.38#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.21:48:44.44#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.21:48:44.44#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.21:48:44.46#ibcon#[25=AT03-08\r\n] 2006.145.21:48:44.49#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.21:48:44.49#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.21:48:44.49#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.21:48:44.49#ibcon#ireg 7 cls_cnt 0 2006.145.21:48:44.49#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.21:48:44.61#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.21:48:44.61#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.21:48:44.63#ibcon#[25=USB\r\n] 2006.145.21:48:44.66#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.21:48:44.66#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.21:48:44.66#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.21:48:44.66#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.21:48:44.66$vck44/valo=4,624.99 2006.145.21:48:44.66#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.21:48:44.66#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.21:48:44.66#ibcon#ireg 17 cls_cnt 0 2006.145.21:48:44.66#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.21:48:44.66#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.21:48:44.66#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.21:48:44.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.21:48:44.72#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.21:48:44.72#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.21:48:44.72#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.21:48:44.72#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.21:48:44.72$vck44/va=4,7 2006.145.21:48:44.72#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.21:48:44.72#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.21:48:44.72#ibcon#ireg 11 cls_cnt 2 2006.145.21:48:44.72#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.21:48:44.78#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.21:48:44.78#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.21:48:44.80#ibcon#[25=AT04-07\r\n] 2006.145.21:48:44.83#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.21:48:44.83#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.21:48:44.83#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.21:48:44.83#ibcon#ireg 7 cls_cnt 0 2006.145.21:48:44.83#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.21:48:44.95#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.21:48:44.95#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.21:48:44.97#ibcon#[25=USB\r\n] 2006.145.21:48:45.00#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.21:48:45.00#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.21:48:45.00#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.21:48:45.00#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.21:48:45.00$vck44/valo=5,734.99 2006.145.21:48:45.00#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.21:48:45.00#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.21:48:45.00#ibcon#ireg 17 cls_cnt 0 2006.145.21:48:45.00#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.21:48:45.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.21:48:45.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.21:48:45.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.21:48:45.06#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.21:48:45.06#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.21:48:45.06#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.21:48:45.06#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.21:48:45.06$vck44/va=5,4 2006.145.21:48:45.06#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.21:48:45.06#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.21:48:45.06#ibcon#ireg 11 cls_cnt 2 2006.145.21:48:45.06#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.21:48:45.12#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.21:48:45.12#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.21:48:45.14#ibcon#[25=AT05-04\r\n] 2006.145.21:48:45.18#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.21:48:45.18#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.21:48:45.18#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.21:48:45.18#ibcon#ireg 7 cls_cnt 0 2006.145.21:48:45.18#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.21:48:45.29#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.21:48:45.29#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.21:48:45.31#ibcon#[25=USB\r\n] 2006.145.21:48:45.34#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.21:48:45.34#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.21:48:45.34#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.21:48:45.34#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.21:48:45.34$vck44/valo=6,814.99 2006.145.21:48:45.34#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.21:48:45.34#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.21:48:45.34#ibcon#ireg 17 cls_cnt 0 2006.145.21:48:45.34#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.21:48:45.34#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.21:48:45.34#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.21:48:45.36#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.21:48:45.40#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.21:48:45.40#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.21:48:45.40#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.21:48:45.40#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.21:48:45.40$vck44/va=6,4 2006.145.21:48:45.40#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.21:48:45.40#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.21:48:45.40#ibcon#ireg 11 cls_cnt 2 2006.145.21:48:45.40#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.21:48:45.46#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.21:48:45.46#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.21:48:45.48#ibcon#[25=AT06-04\r\n] 2006.145.21:48:45.51#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.21:48:45.51#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.21:48:45.51#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.21:48:45.51#ibcon#ireg 7 cls_cnt 0 2006.145.21:48:45.51#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.21:48:45.63#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.21:48:45.63#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.21:48:45.64#abcon#<5=/07 1.7 3.6 17.31 841020.2\r\n> 2006.145.21:48:45.65#ibcon#[25=USB\r\n] 2006.145.21:48:45.66#abcon#{5=INTERFACE CLEAR} 2006.145.21:48:45.68#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.21:48:45.68#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.21:48:45.68#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.21:48:45.68#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.21:48:45.68$vck44/valo=7,864.99 2006.145.21:48:45.68#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.21:48:45.68#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.21:48:45.68#ibcon#ireg 17 cls_cnt 0 2006.145.21:48:45.68#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.21:48:45.68#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.21:48:45.68#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.21:48:45.70#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.21:48:45.72#abcon#[5=S1D000X0/0*\r\n] 2006.145.21:48:45.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.21:48:45.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.21:48:45.74#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.21:48:45.74#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.21:48:45.74$vck44/va=7,4 2006.145.21:48:45.74#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.21:48:45.74#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.21:48:45.74#ibcon#ireg 11 cls_cnt 2 2006.145.21:48:45.74#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.21:48:45.80#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.21:48:45.80#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.21:48:45.82#ibcon#[25=AT07-04\r\n] 2006.145.21:48:45.85#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.21:48:45.85#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.21:48:45.85#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.21:48:45.85#ibcon#ireg 7 cls_cnt 0 2006.145.21:48:45.85#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.21:48:45.97#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.21:48:45.97#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.21:48:45.99#ibcon#[25=USB\r\n] 2006.145.21:48:46.02#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.21:48:46.02#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.21:48:46.02#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.21:48:46.02#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.21:48:46.02$vck44/valo=8,884.99 2006.145.21:48:46.02#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.21:48:46.02#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.21:48:46.02#ibcon#ireg 17 cls_cnt 0 2006.145.21:48:46.02#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.21:48:46.02#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.21:48:46.02#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.21:48:46.04#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.21:48:46.08#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.21:48:46.08#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.21:48:46.08#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.21:48:46.08#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.21:48:46.08$vck44/va=8,4 2006.145.21:48:46.08#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.21:48:46.08#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.21:48:46.08#ibcon#ireg 11 cls_cnt 2 2006.145.21:48:46.08#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.21:48:46.14#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.21:48:46.14#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.21:48:46.16#ibcon#[25=AT08-04\r\n] 2006.145.21:48:46.19#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.21:48:46.19#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.21:48:46.19#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.21:48:46.19#ibcon#ireg 7 cls_cnt 0 2006.145.21:48:46.19#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.21:48:46.31#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.21:48:46.31#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.21:48:46.33#ibcon#[25=USB\r\n] 2006.145.21:48:46.36#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.21:48:46.36#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.21:48:46.36#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.21:48:46.36#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.21:48:46.36$vck44/vblo=1,629.99 2006.145.21:48:46.36#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.21:48:46.36#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.21:48:46.36#ibcon#ireg 17 cls_cnt 0 2006.145.21:48:46.36#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.21:48:46.36#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.21:48:46.36#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.21:48:46.38#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.21:48:46.42#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.21:48:46.42#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.21:48:46.42#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.21:48:46.42#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.21:48:46.42$vck44/vb=1,3 2006.145.21:48:46.42#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.21:48:46.42#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.21:48:46.42#ibcon#ireg 11 cls_cnt 2 2006.145.21:48:46.42#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.21:48:46.42#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.21:48:46.42#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.21:48:46.44#ibcon#[27=AT01-03\r\n] 2006.145.21:48:46.47#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.21:48:46.47#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.21:48:46.47#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.21:48:46.47#ibcon#ireg 7 cls_cnt 0 2006.145.21:48:46.47#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.21:48:46.59#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.21:48:46.59#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.21:48:46.61#ibcon#[27=USB\r\n] 2006.145.21:48:46.64#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.21:48:46.64#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.21:48:46.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.21:48:46.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.21:48:46.64$vck44/vblo=2,634.99 2006.145.21:48:46.64#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.21:48:46.64#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.21:48:46.64#ibcon#ireg 17 cls_cnt 0 2006.145.21:48:46.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.21:48:46.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.21:48:46.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.21:48:46.66#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.21:48:46.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.21:48:46.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.21:48:46.70#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.21:48:46.70#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.21:48:46.70$vck44/vb=2,4 2006.145.21:48:46.70#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.21:48:46.70#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.21:48:46.70#ibcon#ireg 11 cls_cnt 2 2006.145.21:48:46.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.21:48:46.76#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.21:48:46.76#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.21:48:46.78#ibcon#[27=AT02-04\r\n] 2006.145.21:48:46.81#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.21:48:46.81#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.21:48:46.81#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.21:48:46.81#ibcon#ireg 7 cls_cnt 0 2006.145.21:48:46.81#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.21:48:46.93#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.21:48:46.93#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.21:48:46.95#ibcon#[27=USB\r\n] 2006.145.21:48:46.98#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.21:48:46.98#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.21:48:46.98#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.21:48:46.98#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.21:48:46.98$vck44/vblo=3,649.99 2006.145.21:48:46.98#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.21:48:46.98#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.21:48:46.98#ibcon#ireg 17 cls_cnt 0 2006.145.21:48:46.98#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:48:46.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:48:46.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:48:47.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.21:48:47.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:48:47.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:48:47.04#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.21:48:47.04#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.21:48:47.04$vck44/vb=3,4 2006.145.21:48:47.04#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.21:48:47.04#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.21:48:47.04#ibcon#ireg 11 cls_cnt 2 2006.145.21:48:47.04#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.21:48:47.10#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.21:48:47.10#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.21:48:47.12#ibcon#[27=AT03-04\r\n] 2006.145.21:48:47.15#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.21:48:47.15#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.21:48:47.15#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.21:48:47.15#ibcon#ireg 7 cls_cnt 0 2006.145.21:48:47.15#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.21:48:47.27#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.21:48:47.27#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.21:48:47.29#ibcon#[27=USB\r\n] 2006.145.21:48:47.32#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.21:48:47.32#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.21:48:47.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.21:48:47.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.21:48:47.32$vck44/vblo=4,679.99 2006.145.21:48:47.32#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.21:48:47.32#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.21:48:47.32#ibcon#ireg 17 cls_cnt 0 2006.145.21:48:47.32#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.21:48:47.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.21:48:47.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.21:48:47.34#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.21:48:47.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.21:48:47.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.21:48:47.38#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.21:48:47.38#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.21:48:47.38$vck44/vb=4,4 2006.145.21:48:47.38#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.21:48:47.38#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.21:48:47.38#ibcon#ireg 11 cls_cnt 2 2006.145.21:48:47.38#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.21:48:47.44#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.21:48:47.44#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.21:48:47.46#ibcon#[27=AT04-04\r\n] 2006.145.21:48:47.49#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.21:48:47.49#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.21:48:47.49#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.21:48:47.49#ibcon#ireg 7 cls_cnt 0 2006.145.21:48:47.49#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.21:48:47.61#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.21:48:47.61#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.21:48:47.63#ibcon#[27=USB\r\n] 2006.145.21:48:47.66#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.21:48:47.66#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.21:48:47.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.21:48:47.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.21:48:47.66$vck44/vblo=5,709.99 2006.145.21:48:47.66#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.21:48:47.66#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.21:48:47.66#ibcon#ireg 17 cls_cnt 0 2006.145.21:48:47.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.21:48:47.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.21:48:47.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.21:48:47.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.21:48:47.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.21:48:47.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.21:48:47.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.21:48:47.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.21:48:47.72$vck44/vb=5,4 2006.145.21:48:47.72#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.21:48:47.72#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.21:48:47.72#ibcon#ireg 11 cls_cnt 2 2006.145.21:48:47.72#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.21:48:47.78#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.21:48:47.78#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.21:48:47.80#ibcon#[27=AT05-04\r\n] 2006.145.21:48:47.83#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.21:48:47.83#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.21:48:47.83#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.21:48:47.83#ibcon#ireg 7 cls_cnt 0 2006.145.21:48:47.83#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.21:48:47.95#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.21:48:47.95#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.21:48:47.97#ibcon#[27=USB\r\n] 2006.145.21:48:48.00#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.21:48:48.00#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.21:48:48.00#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.21:48:48.00#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.21:48:48.00$vck44/vblo=6,719.99 2006.145.21:48:48.00#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.21:48:48.00#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.21:48:48.00#ibcon#ireg 17 cls_cnt 0 2006.145.21:48:48.00#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.21:48:48.00#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.21:48:48.00#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.21:48:48.02#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.21:48:48.06#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.21:48:48.06#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.21:48:48.06#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.21:48:48.06#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.21:48:48.06$vck44/vb=6,4 2006.145.21:48:48.06#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.21:48:48.06#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.21:48:48.06#ibcon#ireg 11 cls_cnt 2 2006.145.21:48:48.06#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.21:48:48.12#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.21:48:48.12#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.21:48:48.14#ibcon#[27=AT06-04\r\n] 2006.145.21:48:48.17#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.21:48:48.17#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.21:48:48.17#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.21:48:48.17#ibcon#ireg 7 cls_cnt 0 2006.145.21:48:48.17#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.21:48:48.29#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.21:48:48.29#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.21:48:48.31#ibcon#[27=USB\r\n] 2006.145.21:48:48.34#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.21:48:48.34#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.21:48:48.34#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.21:48:48.34#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.21:48:48.34$vck44/vblo=7,734.99 2006.145.21:48:48.34#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.21:48:48.34#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.21:48:48.34#ibcon#ireg 17 cls_cnt 0 2006.145.21:48:48.34#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.21:48:48.34#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.21:48:48.34#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.21:48:48.36#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.21:48:48.40#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.21:48:48.40#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.21:48:48.40#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.21:48:48.40#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.21:48:48.40$vck44/vb=7,4 2006.145.21:48:48.40#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.21:48:48.40#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.21:48:48.40#ibcon#ireg 11 cls_cnt 2 2006.145.21:48:48.40#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.21:48:48.46#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.21:48:48.46#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.21:48:48.48#ibcon#[27=AT07-04\r\n] 2006.145.21:48:48.51#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.21:48:48.51#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.21:48:48.51#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.21:48:48.51#ibcon#ireg 7 cls_cnt 0 2006.145.21:48:48.51#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.21:48:48.63#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.21:48:48.63#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.21:48:48.65#ibcon#[27=USB\r\n] 2006.145.21:48:48.68#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.21:48:48.68#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.21:48:48.68#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.21:48:48.68#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.21:48:48.68$vck44/vblo=8,744.99 2006.145.21:48:48.68#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.21:48:48.68#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.21:48:48.68#ibcon#ireg 17 cls_cnt 0 2006.145.21:48:48.68#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.21:48:48.68#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.21:48:48.68#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.21:48:48.70#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.21:48:48.74#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.21:48:48.74#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.21:48:48.74#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.21:48:48.74#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.21:48:48.74$vck44/vb=8,4 2006.145.21:48:48.74#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.21:48:48.74#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.21:48:48.74#ibcon#ireg 11 cls_cnt 2 2006.145.21:48:48.74#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.21:48:48.80#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.21:48:48.80#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.21:48:48.83#ibcon#[27=AT08-04\r\n] 2006.145.21:48:48.86#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.21:48:48.86#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.21:48:48.86#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.21:48:48.86#ibcon#ireg 7 cls_cnt 0 2006.145.21:48:48.86#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.21:48:48.98#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.21:48:48.98#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.21:48:49.00#ibcon#[27=USB\r\n] 2006.145.21:48:49.03#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.21:48:49.03#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.21:48:49.03#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.21:48:49.03#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.21:48:49.03$vck44/vabw=wide 2006.145.21:48:49.03#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.21:48:49.03#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.21:48:49.03#ibcon#ireg 8 cls_cnt 0 2006.145.21:48:49.03#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.21:48:49.03#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.21:48:49.03#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.21:48:49.05#ibcon#[25=BW32\r\n] 2006.145.21:48:49.08#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.21:48:49.08#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.21:48:49.08#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.21:48:49.08#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.21:48:49.08$vck44/vbbw=wide 2006.145.21:48:49.08#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.21:48:49.08#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.21:48:49.08#ibcon#ireg 8 cls_cnt 0 2006.145.21:48:49.08#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:48:49.15#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:48:49.15#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:48:49.17#ibcon#[27=BW32\r\n] 2006.145.21:48:49.20#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:48:49.20#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:48:49.20#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.21:48:49.20#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.21:48:49.20$setupk4/ifdk4 2006.145.21:48:49.20$ifdk4/lo= 2006.145.21:48:49.20$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.21:48:49.20$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.21:48:49.20$ifdk4/patch= 2006.145.21:48:49.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.21:48:49.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.21:48:49.20$setupk4/!*+20s 2006.145.21:48:55.81#abcon#<5=/07 1.7 3.6 17.31 841020.2\r\n> 2006.145.21:48:55.83#abcon#{5=INTERFACE CLEAR} 2006.145.21:48:55.89#abcon#[5=S1D000X0/0*\r\n] 2006.145.21:49:03.70$setupk4/"tpicd 2006.145.21:49:03.70$setupk4/echo=off 2006.145.21:49:03.70$setupk4/xlog=off 2006.145.21:49:03.70:!2006.145.21:54:38 2006.145.21:49:04.14#trakl#Source acquired 2006.145.21:49:05.14#flagr#flagr/antenna,acquired 2006.145.21:54:38.00:preob 2006.145.21:54:39.14/onsource/TRACKING 2006.145.21:54:39.14:!2006.145.21:54:48 2006.145.21:54:48.00:"tape 2006.145.21:54:48.00:"st=record 2006.145.21:54:48.00:data_valid=on 2006.145.21:54:48.00:midob 2006.145.21:54:48.14/onsource/TRACKING 2006.145.21:54:48.14/wx/17.23,1020.1,84 2006.145.21:54:48.25/cable/+6.5473E-03 2006.145.21:54:49.34/va/01,08,usb,yes,30,33 2006.145.21:54:49.34/va/02,07,usb,yes,32,33 2006.145.21:54:49.34/va/03,08,usb,yes,30,31 2006.145.21:54:49.34/va/04,07,usb,yes,34,35 2006.145.21:54:49.34/va/05,04,usb,yes,29,30 2006.145.21:54:49.34/va/06,04,usb,yes,33,33 2006.145.21:54:49.34/va/07,04,usb,yes,33,34 2006.145.21:54:49.34/va/08,04,usb,yes,28,34 2006.145.21:54:49.57/valo/01,524.99,yes,locked 2006.145.21:54:49.57/valo/02,534.99,yes,locked 2006.145.21:54:49.57/valo/03,564.99,yes,locked 2006.145.21:54:49.57/valo/04,624.99,yes,locked 2006.145.21:54:49.57/valo/05,734.99,yes,locked 2006.145.21:54:49.57/valo/06,814.99,yes,locked 2006.145.21:54:49.57/valo/07,864.99,yes,locked 2006.145.21:54:49.57/valo/08,884.99,yes,locked 2006.145.21:54:50.66/vb/01,03,usb,yes,37,37 2006.145.21:54:50.66/vb/02,04,usb,yes,32,33 2006.145.21:54:50.66/vb/03,04,usb,yes,29,32 2006.145.21:54:50.66/vb/04,04,usb,yes,33,32 2006.145.21:54:50.66/vb/05,04,usb,yes,26,29 2006.145.21:54:50.66/vb/06,04,usb,yes,31,27 2006.145.21:54:50.66/vb/07,04,usb,yes,30,30 2006.145.21:54:50.66/vb/08,04,usb,yes,28,31 2006.145.21:54:50.89/vblo/01,629.99,yes,locked 2006.145.21:54:50.89/vblo/02,634.99,yes,locked 2006.145.21:54:50.89/vblo/03,649.99,yes,locked 2006.145.21:54:50.89/vblo/04,679.99,yes,locked 2006.145.21:54:50.89/vblo/05,709.99,yes,locked 2006.145.21:54:50.89/vblo/06,719.99,yes,locked 2006.145.21:54:50.89/vblo/07,734.99,yes,locked 2006.145.21:54:50.89/vblo/08,744.99,yes,locked 2006.145.21:54:51.04/vabw/8 2006.145.21:54:51.19/vbbw/8 2006.145.21:54:51.28/xfe/off,on,14.7 2006.145.21:54:51.68/ifatt/23,28,28,28 2006.145.21:54:52.08/fmout-gps/S +4.1E-08 2006.145.21:54:52.12:!2006.145.21:58:28 2006.145.21:58:28.00:data_valid=off 2006.145.21:58:28.00:"et 2006.145.21:58:28.00:!+3s 2006.145.21:58:31.02:"tape 2006.145.21:58:31.02:postob 2006.145.21:58:31.09/cable/+6.5490E-03 2006.145.21:58:31.09/wx/17.20,1020.2,83 2006.145.21:58:31.17/fmout-gps/S +4.0E-08 2006.145.21:58:31.18:scan_name=145-2159,jd0605,400 2006.145.21:58:31.18:source=0059+581,010245.76,582411.1,2000.0,cw 2006.145.21:58:33.14#flagr#flagr/antenna,new-source 2006.145.21:58:33.14:checkk5 2006.145.21:58:33.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.21:58:34.00/chk_autoobs//k5ts2/ autoobs is running! 2006.145.21:58:34.45/chk_autoobs//k5ts3/ autoobs is running! 2006.145.21:58:34.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.21:58:35.33/chk_obsdata//k5ts1/T1452154??a.dat file size is correct (nominal:880MB, actual:876MB). 2006.145.21:58:35.76/chk_obsdata//k5ts2/T1452154??b.dat file size is correct (nominal:880MB, actual:876MB). 2006.145.21:58:36.21/chk_obsdata//k5ts3/T1452154??c.dat file size is correct (nominal:880MB, actual:876MB). 2006.145.21:58:36.64/chk_obsdata//k5ts4/T1452154??d.dat file size is correct (nominal:880MB, actual:876MB). 2006.145.21:58:37.40/k5log//k5ts1_log_newline 2006.145.21:58:38.14/k5log//k5ts2_log_newline 2006.145.21:58:38.88/k5log//k5ts3_log_newline 2006.145.21:58:39.63/k5log//k5ts4_log_newline 2006.145.21:58:39.65/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.21:58:39.65:setupk4=1 2006.145.21:58:39.65$setupk4/echo=on 2006.145.21:58:39.65$setupk4/pcalon 2006.145.21:58:39.65$pcalon/"no phase cal control is implemented here 2006.145.21:58:39.65$setupk4/"tpicd=stop 2006.145.21:58:39.65$setupk4/"rec=synch_on 2006.145.21:58:39.65$setupk4/"rec_mode=128 2006.145.21:58:39.65$setupk4/!* 2006.145.21:58:39.65$setupk4/recpk4 2006.145.21:58:39.65$recpk4/recpatch= 2006.145.21:58:39.66$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.21:58:39.66$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.21:58:39.66$setupk4/vck44 2006.145.21:58:39.66$vck44/valo=1,524.99 2006.145.21:58:39.66#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.21:58:39.66#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.21:58:39.66#ibcon#ireg 17 cls_cnt 0 2006.145.21:58:39.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:58:39.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:58:39.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:58:39.70#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.21:58:39.75#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:58:39.75#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:58:39.75#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.21:58:39.75#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.21:58:39.75$vck44/va=1,8 2006.145.21:58:39.75#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.21:58:39.75#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.21:58:39.75#ibcon#ireg 11 cls_cnt 2 2006.145.21:58:39.75#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:58:39.75#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:58:39.75#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:58:39.77#ibcon#[25=AT01-08\r\n] 2006.145.21:58:39.80#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:58:39.80#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:58:39.80#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.21:58:39.80#ibcon#ireg 7 cls_cnt 0 2006.145.21:58:39.80#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:58:39.92#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:58:39.92#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:58:39.94#ibcon#[25=USB\r\n] 2006.145.21:58:39.97#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:58:39.97#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:58:39.97#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.21:58:39.97#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.21:58:39.97$vck44/valo=2,534.99 2006.145.21:58:39.97#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.21:58:39.97#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.21:58:39.97#ibcon#ireg 17 cls_cnt 0 2006.145.21:58:39.97#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:58:39.97#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:58:39.97#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:58:40.00#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.21:58:40.04#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:58:40.04#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:58:40.04#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.21:58:40.04#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.21:58:40.04$vck44/va=2,7 2006.145.21:58:40.04#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.21:58:40.04#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.21:58:40.04#ibcon#ireg 11 cls_cnt 2 2006.145.21:58:40.04#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:58:40.09#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:58:40.09#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:58:40.11#ibcon#[25=AT02-07\r\n] 2006.145.21:58:40.14#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:58:40.14#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:58:40.14#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.21:58:40.14#ibcon#ireg 7 cls_cnt 0 2006.145.21:58:40.14#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:58:40.26#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:58:40.26#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:58:40.28#ibcon#[25=USB\r\n] 2006.145.21:58:40.31#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:58:40.31#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:58:40.31#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.21:58:40.31#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.21:58:40.31$vck44/valo=3,564.99 2006.145.21:58:40.31#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.21:58:40.31#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.21:58:40.31#ibcon#ireg 17 cls_cnt 0 2006.145.21:58:40.31#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:58:40.31#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:58:40.31#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:58:40.33#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.21:58:40.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:58:40.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:58:40.37#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.21:58:40.37#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.21:58:40.37$vck44/va=3,8 2006.145.21:58:40.37#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.21:58:40.37#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.21:58:40.37#ibcon#ireg 11 cls_cnt 2 2006.145.21:58:40.37#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:58:40.43#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:58:40.43#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:58:40.45#ibcon#[25=AT03-08\r\n] 2006.145.21:58:40.48#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:58:40.48#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:58:40.48#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.21:58:40.48#ibcon#ireg 7 cls_cnt 0 2006.145.21:58:40.48#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:58:40.60#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:58:40.60#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:58:40.62#ibcon#[25=USB\r\n] 2006.145.21:58:40.65#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:58:40.65#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:58:40.65#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.21:58:40.65#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.21:58:40.65$vck44/valo=4,624.99 2006.145.21:58:40.65#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.21:58:40.65#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.21:58:40.65#ibcon#ireg 17 cls_cnt 0 2006.145.21:58:40.65#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.21:58:40.65#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.21:58:40.65#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.21:58:40.67#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.21:58:40.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.21:58:40.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.21:58:40.71#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.21:58:40.71#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.21:58:40.71$vck44/va=4,7 2006.145.21:58:40.71#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.21:58:40.71#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.21:58:40.71#ibcon#ireg 11 cls_cnt 2 2006.145.21:58:40.71#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.21:58:40.77#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.21:58:40.77#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.21:58:40.79#ibcon#[25=AT04-07\r\n] 2006.145.21:58:40.82#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.21:58:40.82#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.21:58:40.82#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.21:58:40.82#ibcon#ireg 7 cls_cnt 0 2006.145.21:58:40.82#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.21:58:40.94#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.21:58:40.94#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.21:58:40.96#ibcon#[25=USB\r\n] 2006.145.21:58:40.99#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.21:58:40.99#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.21:58:40.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.21:58:40.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.21:58:40.99$vck44/valo=5,734.99 2006.145.21:58:40.99#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.21:58:40.99#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.21:58:40.99#ibcon#ireg 17 cls_cnt 0 2006.145.21:58:40.99#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:58:40.99#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:58:40.99#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:58:41.01#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.21:58:41.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:58:41.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:58:41.05#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.21:58:41.05#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.21:58:41.05$vck44/va=5,4 2006.145.21:58:41.05#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.21:58:41.05#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.21:58:41.05#ibcon#ireg 11 cls_cnt 2 2006.145.21:58:41.05#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:58:41.11#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:58:41.11#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:58:41.13#ibcon#[25=AT05-04\r\n] 2006.145.21:58:41.16#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:58:41.16#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:58:41.16#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.21:58:41.16#ibcon#ireg 7 cls_cnt 0 2006.145.21:58:41.16#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:58:41.29#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:58:41.29#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:58:41.31#ibcon#[25=USB\r\n] 2006.145.21:58:41.34#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:58:41.34#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:58:41.34#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.21:58:41.34#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.21:58:41.34$vck44/valo=6,814.99 2006.145.21:58:41.34#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.21:58:41.34#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.21:58:41.34#ibcon#ireg 17 cls_cnt 0 2006.145.21:58:41.34#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:58:41.34#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:58:41.34#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:58:41.37#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.21:58:41.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:58:41.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:58:41.41#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.21:58:41.41#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.21:58:41.41$vck44/va=6,4 2006.145.21:58:41.41#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.21:58:41.41#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.21:58:41.41#ibcon#ireg 11 cls_cnt 2 2006.145.21:58:41.41#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.21:58:41.46#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.21:58:41.46#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.21:58:41.48#ibcon#[25=AT06-04\r\n] 2006.145.21:58:41.51#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.21:58:41.51#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.21:58:41.51#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.21:58:41.51#ibcon#ireg 7 cls_cnt 0 2006.145.21:58:41.51#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.21:58:41.63#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.21:58:41.63#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.21:58:41.65#ibcon#[25=USB\r\n] 2006.145.21:58:41.68#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.21:58:41.68#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.21:58:41.68#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.21:58:41.68#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.21:58:41.68$vck44/valo=7,864.99 2006.145.21:58:41.68#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.21:58:41.68#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.21:58:41.68#ibcon#ireg 17 cls_cnt 0 2006.145.21:58:41.68#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.21:58:41.68#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.21:58:41.68#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.21:58:41.70#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.21:58:41.74#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.21:58:41.74#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.21:58:41.74#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.21:58:41.74#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.21:58:41.74$vck44/va=7,4 2006.145.21:58:41.74#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.21:58:41.74#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.21:58:41.74#ibcon#ireg 11 cls_cnt 2 2006.145.21:58:41.74#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.21:58:41.80#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.21:58:41.80#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.21:58:41.82#ibcon#[25=AT07-04\r\n] 2006.145.21:58:41.85#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.21:58:41.85#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.21:58:41.85#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.21:58:41.85#ibcon#ireg 7 cls_cnt 0 2006.145.21:58:41.85#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.21:58:41.97#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.21:58:41.97#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.21:58:41.99#ibcon#[25=USB\r\n] 2006.145.21:58:42.02#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.21:58:42.02#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.21:58:42.02#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.21:58:42.02#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.21:58:42.02$vck44/valo=8,884.99 2006.145.21:58:42.02#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.21:58:42.02#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.21:58:42.02#ibcon#ireg 17 cls_cnt 0 2006.145.21:58:42.02#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:58:42.02#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:58:42.02#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:58:42.04#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.21:58:42.08#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:58:42.08#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:58:42.08#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.21:58:42.08#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.21:58:42.08$vck44/va=8,4 2006.145.21:58:42.08#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.21:58:42.08#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.21:58:42.08#ibcon#ireg 11 cls_cnt 2 2006.145.21:58:42.08#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.21:58:42.14#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.21:58:42.14#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.21:58:42.16#ibcon#[25=AT08-04\r\n] 2006.145.21:58:42.19#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.21:58:42.19#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.21:58:42.19#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.21:58:42.19#ibcon#ireg 7 cls_cnt 0 2006.145.21:58:42.19#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.21:58:42.31#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.21:58:42.31#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.21:58:42.33#ibcon#[25=USB\r\n] 2006.145.21:58:42.36#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.21:58:42.36#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.21:58:42.36#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.21:58:42.36#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.21:58:42.36$vck44/vblo=1,629.99 2006.145.21:58:42.36#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.21:58:42.36#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.21:58:42.36#ibcon#ireg 17 cls_cnt 0 2006.145.21:58:42.36#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.21:58:42.36#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.21:58:42.36#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.21:58:42.38#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.21:58:42.42#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.21:58:42.42#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.21:58:42.42#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.21:58:42.42#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.21:58:42.42$vck44/vb=1,3 2006.145.21:58:42.42#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.21:58:42.42#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.21:58:42.42#ibcon#ireg 11 cls_cnt 2 2006.145.21:58:42.42#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.21:58:42.42#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.21:58:42.42#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.21:58:42.44#ibcon#[27=AT01-03\r\n] 2006.145.21:58:42.47#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.21:58:42.47#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.21:58:42.47#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.21:58:42.47#ibcon#ireg 7 cls_cnt 0 2006.145.21:58:42.47#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.21:58:42.59#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.21:58:42.59#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.21:58:42.61#ibcon#[27=USB\r\n] 2006.145.21:58:42.64#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.21:58:42.64#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.21:58:42.64#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.21:58:42.64#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.21:58:42.64$vck44/vblo=2,634.99 2006.145.21:58:42.64#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.21:58:42.64#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.21:58:42.64#ibcon#ireg 17 cls_cnt 0 2006.145.21:58:42.64#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:58:42.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:58:42.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:58:42.66#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.21:58:42.70#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:58:42.70#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.21:58:42.70#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.21:58:42.70#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.21:58:42.70$vck44/vb=2,4 2006.145.21:58:42.70#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.21:58:42.70#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.21:58:42.70#ibcon#ireg 11 cls_cnt 2 2006.145.21:58:42.70#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:58:42.76#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:58:42.76#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:58:42.78#ibcon#[27=AT02-04\r\n] 2006.145.21:58:42.81#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:58:42.81#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.21:58:42.81#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.21:58:42.81#ibcon#ireg 7 cls_cnt 0 2006.145.21:58:42.81#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:58:42.93#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:58:42.93#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:58:42.95#ibcon#[27=USB\r\n] 2006.145.21:58:42.98#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:58:42.98#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.21:58:42.98#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.21:58:42.98#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.21:58:42.98$vck44/vblo=3,649.99 2006.145.21:58:42.98#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.21:58:42.98#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.21:58:42.98#ibcon#ireg 17 cls_cnt 0 2006.145.21:58:42.98#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:58:42.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:58:42.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:58:43.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.21:58:43.04#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:58:43.04#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.21:58:43.04#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.21:58:43.04#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.21:58:43.04$vck44/vb=3,4 2006.145.21:58:43.04#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.21:58:43.04#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.21:58:43.04#ibcon#ireg 11 cls_cnt 2 2006.145.21:58:43.04#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:58:43.10#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:58:43.10#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:58:43.12#ibcon#[27=AT03-04\r\n] 2006.145.21:58:43.15#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:58:43.15#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.21:58:43.15#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.21:58:43.15#ibcon#ireg 7 cls_cnt 0 2006.145.21:58:43.15#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:58:43.27#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:58:43.27#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:58:43.29#ibcon#[27=USB\r\n] 2006.145.21:58:43.32#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:58:43.32#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.21:58:43.32#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.21:58:43.32#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.21:58:43.32$vck44/vblo=4,679.99 2006.145.21:58:43.32#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.21:58:43.32#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.21:58:43.32#ibcon#ireg 17 cls_cnt 0 2006.145.21:58:43.32#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:58:43.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:58:43.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:58:43.34#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.21:58:43.38#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:58:43.38#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.21:58:43.38#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.21:58:43.38#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.21:58:43.38$vck44/vb=4,4 2006.145.21:58:43.38#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.21:58:43.38#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.21:58:43.38#ibcon#ireg 11 cls_cnt 2 2006.145.21:58:43.38#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:58:43.44#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:58:43.44#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:58:43.46#ibcon#[27=AT04-04\r\n] 2006.145.21:58:43.49#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:58:43.49#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.21:58:43.49#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.21:58:43.49#ibcon#ireg 7 cls_cnt 0 2006.145.21:58:43.49#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:58:43.61#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:58:43.61#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:58:43.63#ibcon#[27=USB\r\n] 2006.145.21:58:43.66#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:58:43.66#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.21:58:43.66#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.21:58:43.66#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.21:58:43.66$vck44/vblo=5,709.99 2006.145.21:58:43.66#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.21:58:43.66#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.21:58:43.66#ibcon#ireg 17 cls_cnt 0 2006.145.21:58:43.66#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.21:58:43.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.21:58:43.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.21:58:43.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.21:58:43.72#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.21:58:43.72#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.21:58:43.72#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.21:58:43.72#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.21:58:43.72$vck44/vb=5,4 2006.145.21:58:43.72#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.21:58:43.72#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.21:58:43.72#ibcon#ireg 11 cls_cnt 2 2006.145.21:58:43.72#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.21:58:43.78#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.21:58:43.78#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.21:58:43.80#ibcon#[27=AT05-04\r\n] 2006.145.21:58:43.83#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.21:58:43.83#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.21:58:43.83#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.21:58:43.83#ibcon#ireg 7 cls_cnt 0 2006.145.21:58:43.83#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.21:58:43.95#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.21:58:43.95#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.21:58:43.97#ibcon#[27=USB\r\n] 2006.145.21:58:44.00#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.21:58:44.00#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.21:58:44.00#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.21:58:44.00#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.21:58:44.00$vck44/vblo=6,719.99 2006.145.21:58:44.00#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.21:58:44.00#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.21:58:44.00#ibcon#ireg 17 cls_cnt 0 2006.145.21:58:44.00#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:58:44.00#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:58:44.00#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:58:44.02#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.21:58:44.06#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:58:44.06#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.21:58:44.06#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.21:58:44.06#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.21:58:44.06$vck44/vb=6,4 2006.145.21:58:44.06#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.21:58:44.06#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.21:58:44.06#ibcon#ireg 11 cls_cnt 2 2006.145.21:58:44.06#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:58:44.12#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:58:44.12#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:58:44.14#ibcon#[27=AT06-04\r\n] 2006.145.21:58:44.17#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:58:44.17#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.21:58:44.17#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.21:58:44.17#ibcon#ireg 7 cls_cnt 0 2006.145.21:58:44.17#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:58:44.29#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:58:44.29#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:58:44.31#ibcon#[27=USB\r\n] 2006.145.21:58:44.34#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:58:44.34#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.21:58:44.34#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.21:58:44.34#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.21:58:44.34$vck44/vblo=7,734.99 2006.145.21:58:44.34#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.21:58:44.34#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.21:58:44.34#ibcon#ireg 17 cls_cnt 0 2006.145.21:58:44.34#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:58:44.34#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:58:44.34#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:58:44.36#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.21:58:44.40#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:58:44.40#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.21:58:44.40#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.21:58:44.40#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.21:58:44.40$vck44/vb=7,4 2006.145.21:58:44.40#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.21:58:44.40#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.21:58:44.40#ibcon#ireg 11 cls_cnt 2 2006.145.21:58:44.40#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.21:58:44.46#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.21:58:44.46#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.21:58:44.48#ibcon#[27=AT07-04\r\n] 2006.145.21:58:44.51#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.21:58:44.51#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.21:58:44.51#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.21:58:44.51#ibcon#ireg 7 cls_cnt 0 2006.145.21:58:44.51#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.21:58:44.63#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.21:58:44.63#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.21:58:44.65#ibcon#[27=USB\r\n] 2006.145.21:58:44.68#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.21:58:44.68#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.21:58:44.68#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.21:58:44.68#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.21:58:44.68$vck44/vblo=8,744.99 2006.145.21:58:44.68#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.21:58:44.68#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.21:58:44.68#ibcon#ireg 17 cls_cnt 0 2006.145.21:58:44.68#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.21:58:44.68#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.21:58:44.68#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.21:58:44.70#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.21:58:44.74#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.21:58:44.74#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.21:58:44.74#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.21:58:44.74#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.21:58:44.74$vck44/vb=8,4 2006.145.21:58:44.74#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.21:58:44.74#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.21:58:44.74#ibcon#ireg 11 cls_cnt 2 2006.145.21:58:44.74#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.21:58:44.80#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.21:58:44.80#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.21:58:44.82#ibcon#[27=AT08-04\r\n] 2006.145.21:58:44.85#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.21:58:44.85#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.21:58:44.85#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.21:58:44.85#ibcon#ireg 7 cls_cnt 0 2006.145.21:58:44.85#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.21:58:44.97#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.21:58:44.97#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.21:58:44.99#ibcon#[27=USB\r\n] 2006.145.21:58:45.02#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.21:58:45.02#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.21:58:45.02#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.21:58:45.02#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.21:58:45.02$vck44/vabw=wide 2006.145.21:58:45.02#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.21:58:45.02#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.21:58:45.02#ibcon#ireg 8 cls_cnt 0 2006.145.21:58:45.02#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:58:45.02#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:58:45.02#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:58:45.04#ibcon#[25=BW32\r\n] 2006.145.21:58:45.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:58:45.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.21:58:45.07#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.21:58:45.07#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.21:58:45.07$vck44/vbbw=wide 2006.145.21:58:45.07#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.21:58:45.07#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.21:58:45.07#ibcon#ireg 8 cls_cnt 0 2006.145.21:58:45.07#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:58:45.14#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:58:45.14#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:58:45.16#ibcon#[27=BW32\r\n] 2006.145.21:58:45.19#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:58:45.19#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.21:58:45.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.21:58:45.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.21:58:45.19$setupk4/ifdk4 2006.145.21:58:45.19$ifdk4/lo= 2006.145.21:58:45.19$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.21:58:45.19$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.21:58:45.19$ifdk4/patch= 2006.145.21:58:45.19$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.21:58:45.19$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.21:58:45.19$setupk4/!*+20s 2006.145.21:58:48.59#abcon#<5=/07 1.7 3.3 17.20 841020.2\r\n> 2006.145.21:58:48.61#abcon#{5=INTERFACE CLEAR} 2006.145.21:58:48.67#abcon#[5=S1D000X0/0*\r\n] 2006.145.21:58:58.14#trakl#Source acquired 2006.145.21:58:58.14#flagr#flagr/antenna,acquired 2006.145.21:58:58.76#abcon#<5=/07 1.6 3.3 17.20 841020.2\r\n> 2006.145.21:58:58.78#abcon#{5=INTERFACE CLEAR} 2006.145.21:58:58.84#abcon#[5=S1D000X0/0*\r\n] 2006.145.21:58:59.66$setupk4/"tpicd 2006.145.21:58:59.66$setupk4/echo=off 2006.145.21:58:59.66$setupk4/xlog=off 2006.145.21:58:59.66:!2006.145.21:59:13 2006.145.21:59:13.00:preob 2006.145.21:59:14.14/onsource/TRACKING 2006.145.21:59:14.14:!2006.145.21:59:23 2006.145.21:59:23.00:"tape 2006.145.21:59:23.00:"st=record 2006.145.21:59:23.00:data_valid=on 2006.145.21:59:23.00:midob 2006.145.21:59:23.14/onsource/TRACKING 2006.145.21:59:23.14/wx/17.20,1020.2,84 2006.145.21:59:23.32/cable/+6.5474E-03 2006.145.21:59:24.41/va/01,08,usb,yes,28,30 2006.145.21:59:24.41/va/02,07,usb,yes,30,31 2006.145.21:59:24.41/va/03,08,usb,yes,27,28 2006.145.21:59:24.41/va/04,07,usb,yes,31,32 2006.145.21:59:24.41/va/05,04,usb,yes,27,27 2006.145.21:59:24.41/va/06,04,usb,yes,30,30 2006.145.21:59:24.41/va/07,04,usb,yes,30,32 2006.145.21:59:24.41/va/08,04,usb,yes,26,31 2006.145.21:59:24.64/valo/01,524.99,yes,locked 2006.145.21:59:24.64/valo/02,534.99,yes,locked 2006.145.21:59:24.64/valo/03,564.99,yes,locked 2006.145.21:59:24.64/valo/04,624.99,yes,locked 2006.145.21:59:24.64/valo/05,734.99,yes,locked 2006.145.21:59:24.64/valo/06,814.99,yes,locked 2006.145.21:59:24.64/valo/07,864.99,yes,locked 2006.145.21:59:24.64/valo/08,884.99,yes,locked 2006.145.21:59:25.73/vb/01,03,usb,yes,35,33 2006.145.21:59:25.73/vb/02,04,usb,yes,31,31 2006.145.21:59:25.73/vb/03,04,usb,yes,28,31 2006.145.21:59:25.73/vb/04,04,usb,yes,32,31 2006.145.21:59:25.73/vb/05,04,usb,yes,25,27 2006.145.21:59:25.73/vb/06,04,usb,yes,29,25 2006.145.21:59:25.73/vb/07,04,usb,yes,29,28 2006.145.21:59:25.73/vb/08,04,usb,yes,26,30 2006.145.21:59:25.97/vblo/01,629.99,yes,locked 2006.145.21:59:25.97/vblo/02,634.99,yes,locked 2006.145.21:59:25.97/vblo/03,649.99,yes,locked 2006.145.21:59:25.97/vblo/04,679.99,yes,locked 2006.145.21:59:25.97/vblo/05,709.99,yes,locked 2006.145.21:59:25.97/vblo/06,719.99,yes,locked 2006.145.21:59:25.97/vblo/07,734.99,yes,locked 2006.145.21:59:25.97/vblo/08,744.99,yes,locked 2006.145.21:59:26.12/vabw/8 2006.145.21:59:26.27/vbbw/8 2006.145.21:59:26.36/xfe/off,on,15.0 2006.145.21:59:26.75/ifatt/23,28,28,28 2006.145.21:59:27.08/fmout-gps/S +4.0E-08 2006.145.21:59:27.12:!2006.145.22:06:03 2006.145.22:06:03.00:data_valid=off 2006.145.22:06:03.01:"et 2006.145.22:06:03.01:!+3s 2006.145.22:06:06.04:"tape 2006.145.22:06:06.05:postob 2006.145.22:06:06.21/cable/+6.5480E-03 2006.145.22:06:06.21/wx/17.25,1020.1,83 2006.145.22:06:06.29/fmout-gps/S +4.0E-08 2006.145.22:06:06.30:scan_name=145-2211,jd0605,130 2006.145.22:06:06.30:source=0528+134,053056.42,133155.1,2000.0,cw 2006.145.22:06:08.14#flagr#flagr/antenna,new-source 2006.145.22:06:08.15:checkk5 2006.145.22:06:08.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.22:06:09.05/chk_autoobs//k5ts2/ autoobs is running! 2006.145.22:06:09.49/chk_autoobs//k5ts3/ autoobs is running! 2006.145.22:06:09.91/chk_autoobs//k5ts4/ autoobs is running! 2006.145.22:06:10.33/chk_obsdata//k5ts1/T1452159??a.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.145.22:06:10.77/chk_obsdata//k5ts2/T1452159??b.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.145.22:06:11.22/chk_obsdata//k5ts3/T1452159??c.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.145.22:06:11.65/chk_obsdata//k5ts4/T1452159??d.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.145.22:06:12.40/k5log//k5ts1_log_newline 2006.145.22:06:13.16/k5log//k5ts2_log_newline 2006.145.22:06:13.93/k5log//k5ts3_log_newline 2006.145.22:06:14.67/k5log//k5ts4_log_newline 2006.145.22:06:14.69/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.22:06:14.69:setupk4=1 2006.145.22:06:14.69$setupk4/echo=on 2006.145.22:06:14.69$setupk4/pcalon 2006.145.22:06:14.69$pcalon/"no phase cal control is implemented here 2006.145.22:06:14.69$setupk4/"tpicd=stop 2006.145.22:06:14.69$setupk4/"rec=synch_on 2006.145.22:06:14.69$setupk4/"rec_mode=128 2006.145.22:06:14.69$setupk4/!* 2006.145.22:06:14.69$setupk4/recpk4 2006.145.22:06:14.69$recpk4/recpatch= 2006.145.22:06:14.70$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.22:06:14.70$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.22:06:14.70$setupk4/vck44 2006.145.22:06:14.70$vck44/valo=1,524.99 2006.145.22:06:14.70#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.22:06:14.70#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.22:06:14.70#ibcon#ireg 17 cls_cnt 0 2006.145.22:06:14.70#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.22:06:14.70#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.22:06:14.70#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.22:06:14.74#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.22:06:14.78#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.22:06:14.78#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.22:06:14.78#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.22:06:14.78#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.22:06:14.78$vck44/va=1,8 2006.145.22:06:14.78#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.22:06:14.78#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.22:06:14.78#ibcon#ireg 11 cls_cnt 2 2006.145.22:06:14.78#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.22:06:14.78#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.22:06:14.78#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.22:06:14.80#ibcon#[25=AT01-08\r\n] 2006.145.22:06:14.83#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.22:06:14.83#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.22:06:14.83#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.22:06:14.83#ibcon#ireg 7 cls_cnt 0 2006.145.22:06:14.83#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.22:06:14.95#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.22:06:14.95#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.22:06:14.97#ibcon#[25=USB\r\n] 2006.145.22:06:15.00#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.22:06:15.00#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.22:06:15.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.22:06:15.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.22:06:15.01$vck44/valo=2,534.99 2006.145.22:06:15.01#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.22:06:15.01#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.22:06:15.01#ibcon#ireg 17 cls_cnt 0 2006.145.22:06:15.01#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.22:06:15.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.22:06:15.01#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.22:06:15.04#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.22:06:15.08#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.22:06:15.08#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.22:06:15.08#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.22:06:15.08#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.22:06:15.08$vck44/va=2,7 2006.145.22:06:15.08#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.22:06:15.08#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.22:06:15.08#ibcon#ireg 11 cls_cnt 2 2006.145.22:06:15.08#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.22:06:15.13#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.22:06:15.13#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.22:06:15.14#ibcon#[25=AT02-07\r\n] 2006.145.22:06:15.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.22:06:15.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.22:06:15.17#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.22:06:15.17#ibcon#ireg 7 cls_cnt 0 2006.145.22:06:15.17#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.22:06:15.29#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.22:06:15.29#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.22:06:15.31#ibcon#[25=USB\r\n] 2006.145.22:06:15.34#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.22:06:15.34#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.22:06:15.34#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.22:06:15.34#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.22:06:15.34$vck44/valo=3,564.99 2006.145.22:06:15.34#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.22:06:15.34#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.22:06:15.34#ibcon#ireg 17 cls_cnt 0 2006.145.22:06:15.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.22:06:15.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.22:06:15.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.22:06:15.36#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.22:06:15.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.22:06:15.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.22:06:15.40#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.22:06:15.40#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.22:06:15.40$vck44/va=3,8 2006.145.22:06:15.40#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.22:06:15.40#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.22:06:15.40#ibcon#ireg 11 cls_cnt 2 2006.145.22:06:15.40#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.22:06:15.46#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.22:06:15.46#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.22:06:15.48#ibcon#[25=AT03-08\r\n] 2006.145.22:06:15.51#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.22:06:15.51#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.22:06:15.51#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.22:06:15.51#ibcon#ireg 7 cls_cnt 0 2006.145.22:06:15.51#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.22:06:15.63#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.22:06:15.63#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.22:06:15.65#ibcon#[25=USB\r\n] 2006.145.22:06:15.68#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.22:06:15.68#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.22:06:15.68#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.22:06:15.68#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.22:06:15.68$vck44/valo=4,624.99 2006.145.22:06:15.68#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.22:06:15.68#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.22:06:15.68#ibcon#ireg 17 cls_cnt 0 2006.145.22:06:15.68#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.22:06:15.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.22:06:15.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.22:06:15.70#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.22:06:15.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.22:06:15.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.22:06:15.74#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.22:06:15.74#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.22:06:15.74$vck44/va=4,7 2006.145.22:06:15.74#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.22:06:15.74#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.22:06:15.74#ibcon#ireg 11 cls_cnt 2 2006.145.22:06:15.74#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.22:06:15.80#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.22:06:15.80#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.22:06:15.82#ibcon#[25=AT04-07\r\n] 2006.145.22:06:15.85#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.22:06:15.85#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.22:06:15.85#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.22:06:15.85#ibcon#ireg 7 cls_cnt 0 2006.145.22:06:15.85#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.22:06:15.97#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.22:06:15.97#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.22:06:15.99#ibcon#[25=USB\r\n] 2006.145.22:06:16.02#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.22:06:16.02#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.22:06:16.02#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.22:06:16.02#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.22:06:16.02$vck44/valo=5,734.99 2006.145.22:06:16.02#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.22:06:16.02#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.22:06:16.02#ibcon#ireg 17 cls_cnt 0 2006.145.22:06:16.02#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.22:06:16.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.22:06:16.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.22:06:16.04#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.22:06:16.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.22:06:16.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.22:06:16.08#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.22:06:16.08#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.22:06:16.08$vck44/va=5,4 2006.145.22:06:16.08#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.22:06:16.08#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.22:06:16.08#ibcon#ireg 11 cls_cnt 2 2006.145.22:06:16.08#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.22:06:16.16#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.22:06:16.16#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.22:06:16.17#ibcon#[25=AT05-04\r\n] 2006.145.22:06:16.20#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.22:06:16.20#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.22:06:16.20#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.22:06:16.20#ibcon#ireg 7 cls_cnt 0 2006.145.22:06:16.20#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.22:06:16.31#abcon#<5=/07 1.6 3.8 17.26 831020.1\r\n> 2006.145.22:06:16.32#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.22:06:16.32#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.22:06:16.33#abcon#{5=INTERFACE CLEAR} 2006.145.22:06:16.34#ibcon#[25=USB\r\n] 2006.145.22:06:16.39#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.22:06:16.39#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.22:06:16.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.22:06:16.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.22:06:16.39$vck44/valo=6,814.99 2006.145.22:06:16.39#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.22:06:16.39#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.22:06:16.39#ibcon#ireg 17 cls_cnt 0 2006.145.22:06:16.39#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.22:06:16.39#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.22:06:16.39#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.22:06:16.40#abcon#[5=S1D000X0/0*\r\n] 2006.145.22:06:16.40#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.22:06:16.44#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.22:06:16.44#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.22:06:16.44#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.22:06:16.44#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.22:06:16.44$vck44/va=6,4 2006.145.22:06:16.44#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.22:06:16.44#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.22:06:16.44#ibcon#ireg 11 cls_cnt 2 2006.145.22:06:16.44#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.22:06:16.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.22:06:16.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.22:06:16.53#ibcon#[25=AT06-04\r\n] 2006.145.22:06:16.56#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.22:06:16.56#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.22:06:16.56#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.22:06:16.56#ibcon#ireg 7 cls_cnt 0 2006.145.22:06:16.56#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.22:06:16.68#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.22:06:16.68#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.22:06:16.70#ibcon#[25=USB\r\n] 2006.145.22:06:16.73#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.22:06:16.73#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.22:06:16.73#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.22:06:16.73#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.22:06:16.73$vck44/valo=7,864.99 2006.145.22:06:16.73#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.22:06:16.73#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.22:06:16.73#ibcon#ireg 17 cls_cnt 0 2006.145.22:06:16.73#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.22:06:16.73#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.22:06:16.73#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.22:06:16.75#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.22:06:16.79#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.22:06:16.79#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.22:06:16.79#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.22:06:16.79#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.22:06:16.79$vck44/va=7,4 2006.145.22:06:16.79#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.22:06:16.79#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.22:06:16.79#ibcon#ireg 11 cls_cnt 2 2006.145.22:06:16.79#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.22:06:16.85#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.22:06:16.85#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.22:06:16.87#ibcon#[25=AT07-04\r\n] 2006.145.22:06:16.90#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.22:06:16.90#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.22:06:16.90#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.22:06:16.90#ibcon#ireg 7 cls_cnt 0 2006.145.22:06:16.90#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.22:06:17.02#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.22:06:17.02#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.22:06:17.04#ibcon#[25=USB\r\n] 2006.145.22:06:17.07#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.22:06:17.07#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.22:06:17.07#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.22:06:17.07#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.22:06:17.07$vck44/valo=8,884.99 2006.145.22:06:17.07#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.22:06:17.07#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.22:06:17.07#ibcon#ireg 17 cls_cnt 0 2006.145.22:06:17.07#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.22:06:17.07#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.22:06:17.07#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.22:06:17.09#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.22:06:17.13#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.22:06:17.13#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.22:06:17.13#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.22:06:17.13#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.22:06:17.14$vck44/va=8,4 2006.145.22:06:17.14#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.22:06:17.14#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.22:06:17.14#ibcon#ireg 11 cls_cnt 2 2006.145.22:06:17.14#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.22:06:17.18#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.22:06:17.18#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.22:06:17.20#ibcon#[25=AT08-04\r\n] 2006.145.22:06:17.23#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.22:06:17.23#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.22:06:17.23#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.22:06:17.23#ibcon#ireg 7 cls_cnt 0 2006.145.22:06:17.23#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.22:06:17.35#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.22:06:17.35#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.22:06:17.37#ibcon#[25=USB\r\n] 2006.145.22:06:17.40#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.22:06:17.40#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.22:06:17.40#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.22:06:17.40#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.22:06:17.40$vck44/vblo=1,629.99 2006.145.22:06:17.40#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.22:06:17.40#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.22:06:17.40#ibcon#ireg 17 cls_cnt 0 2006.145.22:06:17.40#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.22:06:17.40#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.22:06:17.40#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.22:06:17.42#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.22:06:17.48#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.22:06:17.48#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.22:06:17.48#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.22:06:17.48#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.22:06:17.48$vck44/vb=1,3 2006.145.22:06:17.48#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.22:06:17.48#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.22:06:17.48#ibcon#ireg 11 cls_cnt 2 2006.145.22:06:17.48#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.22:06:17.48#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.22:06:17.48#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.22:06:17.49#ibcon#[27=AT01-03\r\n] 2006.145.22:06:17.52#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.22:06:17.52#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.22:06:17.52#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.22:06:17.52#ibcon#ireg 7 cls_cnt 0 2006.145.22:06:17.52#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.22:06:17.64#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.22:06:17.64#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.22:06:17.66#ibcon#[27=USB\r\n] 2006.145.22:06:17.69#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.22:06:17.69#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.22:06:17.69#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.22:06:17.69#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.22:06:17.69$vck44/vblo=2,634.99 2006.145.22:06:17.69#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.22:06:17.69#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.22:06:17.69#ibcon#ireg 17 cls_cnt 0 2006.145.22:06:17.69#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.22:06:17.69#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.22:06:17.69#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.22:06:17.71#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.22:06:17.75#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.22:06:17.75#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.22:06:17.75#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.22:06:17.75#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.22:06:17.75$vck44/vb=2,4 2006.145.22:06:17.75#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.22:06:17.75#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.22:06:17.75#ibcon#ireg 11 cls_cnt 2 2006.145.22:06:17.75#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.22:06:17.81#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.22:06:17.81#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.22:06:17.83#ibcon#[27=AT02-04\r\n] 2006.145.22:06:17.86#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.22:06:17.86#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.22:06:17.86#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.22:06:17.86#ibcon#ireg 7 cls_cnt 0 2006.145.22:06:17.86#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.22:06:17.98#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.22:06:17.98#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.22:06:18.00#ibcon#[27=USB\r\n] 2006.145.22:06:18.03#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.22:06:18.03#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.22:06:18.03#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.22:06:18.03#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.22:06:18.03$vck44/vblo=3,649.99 2006.145.22:06:18.03#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.22:06:18.03#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.22:06:18.03#ibcon#ireg 17 cls_cnt 0 2006.145.22:06:18.03#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.22:06:18.03#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.22:06:18.03#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.22:06:18.05#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.22:06:18.09#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.22:06:18.09#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.22:06:18.09#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.22:06:18.09#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.22:06:18.09$vck44/vb=3,4 2006.145.22:06:18.09#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.22:06:18.09#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.22:06:18.09#ibcon#ireg 11 cls_cnt 2 2006.145.22:06:18.09#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.22:06:18.15#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.22:06:18.15#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.22:06:18.17#ibcon#[27=AT03-04\r\n] 2006.145.22:06:18.20#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.22:06:18.20#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.22:06:18.20#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.22:06:18.20#ibcon#ireg 7 cls_cnt 0 2006.145.22:06:18.20#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.22:06:18.32#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.22:06:18.32#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.22:06:18.34#ibcon#[27=USB\r\n] 2006.145.22:06:18.37#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.22:06:18.37#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.22:06:18.37#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.22:06:18.37#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.22:06:18.37$vck44/vblo=4,679.99 2006.145.22:06:18.37#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.22:06:18.37#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.22:06:18.37#ibcon#ireg 17 cls_cnt 0 2006.145.22:06:18.37#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.22:06:18.37#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.22:06:18.37#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.22:06:18.39#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.22:06:18.43#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.22:06:18.43#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.22:06:18.43#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.22:06:18.43#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.22:06:18.43$vck44/vb=4,4 2006.145.22:06:18.43#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.22:06:18.43#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.22:06:18.43#ibcon#ireg 11 cls_cnt 2 2006.145.22:06:18.43#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.22:06:18.49#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.22:06:18.49#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.22:06:18.51#ibcon#[27=AT04-04\r\n] 2006.145.22:06:18.54#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.22:06:18.54#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.22:06:18.54#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.22:06:18.54#ibcon#ireg 7 cls_cnt 0 2006.145.22:06:18.54#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.22:06:18.66#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.22:06:18.66#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.22:06:18.68#ibcon#[27=USB\r\n] 2006.145.22:06:18.71#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.22:06:18.71#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.22:06:18.71#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.22:06:18.71#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.22:06:18.71$vck44/vblo=5,709.99 2006.145.22:06:18.71#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.22:06:18.71#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.22:06:18.71#ibcon#ireg 17 cls_cnt 0 2006.145.22:06:18.71#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.22:06:18.71#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.22:06:18.71#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.22:06:18.73#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.22:06:18.77#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.22:06:18.77#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.22:06:18.77#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.22:06:18.77#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.22:06:18.77$vck44/vb=5,4 2006.145.22:06:18.77#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.22:06:18.77#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.22:06:18.77#ibcon#ireg 11 cls_cnt 2 2006.145.22:06:18.77#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.22:06:18.83#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.22:06:18.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.22:06:18.85#ibcon#[27=AT05-04\r\n] 2006.145.22:06:18.88#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.22:06:18.88#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.22:06:18.88#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.22:06:18.88#ibcon#ireg 7 cls_cnt 0 2006.145.22:06:18.88#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.22:06:19.00#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.22:06:19.00#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.22:06:19.02#ibcon#[27=USB\r\n] 2006.145.22:06:19.05#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.22:06:19.05#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.22:06:19.05#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.22:06:19.05#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.22:06:19.05$vck44/vblo=6,719.99 2006.145.22:06:19.05#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.22:06:19.05#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.22:06:19.05#ibcon#ireg 17 cls_cnt 0 2006.145.22:06:19.05#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.22:06:19.05#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.22:06:19.05#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.22:06:19.07#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.22:06:19.11#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.22:06:19.11#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.22:06:19.11#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.22:06:19.11#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.22:06:19.11$vck44/vb=6,4 2006.145.22:06:19.11#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.22:06:19.11#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.22:06:19.11#ibcon#ireg 11 cls_cnt 2 2006.145.22:06:19.11#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.22:06:19.17#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.22:06:19.17#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.22:06:19.19#ibcon#[27=AT06-04\r\n] 2006.145.22:06:19.22#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.22:06:19.22#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.22:06:19.22#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.22:06:19.22#ibcon#ireg 7 cls_cnt 0 2006.145.22:06:19.22#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.22:06:19.34#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.22:06:19.34#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.22:06:19.36#ibcon#[27=USB\r\n] 2006.145.22:06:19.39#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.22:06:19.39#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.22:06:19.39#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.22:06:19.39#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.22:06:19.39$vck44/vblo=7,734.99 2006.145.22:06:19.39#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.22:06:19.39#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.22:06:19.39#ibcon#ireg 17 cls_cnt 0 2006.145.22:06:19.39#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.22:06:19.39#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.22:06:19.39#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.22:06:19.41#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.22:06:19.45#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.22:06:19.45#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.22:06:19.45#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.22:06:19.45#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.22:06:19.45$vck44/vb=7,4 2006.145.22:06:19.45#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.22:06:19.45#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.22:06:19.45#ibcon#ireg 11 cls_cnt 2 2006.145.22:06:19.45#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.22:06:19.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.22:06:19.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.22:06:19.53#ibcon#[27=AT07-04\r\n] 2006.145.22:06:19.56#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.22:06:19.56#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.22:06:19.56#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.22:06:19.56#ibcon#ireg 7 cls_cnt 0 2006.145.22:06:19.56#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.22:06:19.68#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.22:06:19.68#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.22:06:19.70#ibcon#[27=USB\r\n] 2006.145.22:06:19.73#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.22:06:19.73#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.22:06:19.73#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.22:06:19.73#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.22:06:19.73$vck44/vblo=8,744.99 2006.145.22:06:19.73#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.22:06:19.73#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.22:06:19.73#ibcon#ireg 17 cls_cnt 0 2006.145.22:06:19.73#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.22:06:19.73#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.22:06:19.73#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.22:06:19.75#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.22:06:19.79#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.22:06:19.79#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.22:06:19.79#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.22:06:19.79#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.22:06:19.79$vck44/vb=8,4 2006.145.22:06:19.79#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.22:06:19.79#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.22:06:19.79#ibcon#ireg 11 cls_cnt 2 2006.145.22:06:19.79#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.22:06:19.85#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.22:06:19.85#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.22:06:19.87#ibcon#[27=AT08-04\r\n] 2006.145.22:06:19.90#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.22:06:19.90#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.22:06:19.90#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.22:06:19.90#ibcon#ireg 7 cls_cnt 0 2006.145.22:06:19.90#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.22:06:20.02#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.22:06:20.02#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.22:06:20.04#ibcon#[27=USB\r\n] 2006.145.22:06:20.07#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.22:06:20.07#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.22:06:20.07#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.22:06:20.07#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.22:06:20.07$vck44/vabw=wide 2006.145.22:06:20.07#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.22:06:20.07#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.22:06:20.07#ibcon#ireg 8 cls_cnt 0 2006.145.22:06:20.07#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.22:06:20.07#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.22:06:20.07#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.22:06:20.09#ibcon#[25=BW32\r\n] 2006.145.22:06:20.12#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.22:06:20.12#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.22:06:20.12#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.22:06:20.12#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.22:06:20.12$vck44/vbbw=wide 2006.145.22:06:20.12#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.22:06:20.12#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.22:06:20.12#ibcon#ireg 8 cls_cnt 0 2006.145.22:06:20.12#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:06:20.19#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:06:20.19#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:06:20.21#ibcon#[27=BW32\r\n] 2006.145.22:06:20.24#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:06:20.24#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:06:20.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.22:06:20.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.22:06:20.24$setupk4/ifdk4 2006.145.22:06:20.24$ifdk4/lo= 2006.145.22:06:20.24$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.22:06:20.25$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.22:06:20.25$ifdk4/patch= 2006.145.22:06:20.25$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.22:06:20.25$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.22:06:20.25$setupk4/!*+20s 2006.145.22:06:26.49#abcon#<5=/07 1.6 3.8 17.26 831020.1\r\n> 2006.145.22:06:26.51#abcon#{5=INTERFACE CLEAR} 2006.145.22:06:26.57#abcon#[5=S1D000X0/0*\r\n] 2006.145.22:06:34.71$setupk4/"tpicd 2006.145.22:06:34.71$setupk4/echo=off 2006.145.22:06:34.71$setupk4/xlog=off 2006.145.22:06:34.71:!2006.145.22:11:39 2006.145.22:06:38.14#trakl#Source acquired 2006.145.22:06:39.14#flagr#flagr/antenna,acquired 2006.145.22:11:39.00:preob 2006.145.22:11:40.13/onsource/TRACKING 2006.145.22:11:40.13:!2006.145.22:11:49 2006.145.22:11:49.00:"tape 2006.145.22:11:49.00:"st=record 2006.145.22:11:49.00:data_valid=on 2006.145.22:11:49.00:midob 2006.145.22:11:49.13/onsource/TRACKING 2006.145.22:11:49.13/wx/17.43,1020.0,83 2006.145.22:11:49.32/cable/+6.5485E-03 2006.145.22:11:50.41/va/01,08,usb,yes,33,35 2006.145.22:11:50.41/va/02,07,usb,yes,35,36 2006.145.22:11:50.41/va/03,08,usb,yes,32,33 2006.145.22:11:50.41/va/04,07,usb,yes,36,38 2006.145.22:11:50.41/va/05,04,usb,yes,32,33 2006.145.22:11:50.41/va/06,04,usb,yes,36,36 2006.145.22:11:50.41/va/07,04,usb,yes,36,37 2006.145.22:11:50.41/va/08,04,usb,yes,31,37 2006.145.22:11:50.64/valo/01,524.99,yes,locked 2006.145.22:11:50.64/valo/02,534.99,yes,locked 2006.145.22:11:50.64/valo/03,564.99,yes,locked 2006.145.22:11:50.64/valo/04,624.99,yes,locked 2006.145.22:11:50.64/valo/05,734.99,yes,locked 2006.145.22:11:50.64/valo/06,814.99,yes,locked 2006.145.22:11:50.64/valo/07,864.99,yes,locked 2006.145.22:11:50.64/valo/08,884.99,yes,locked 2006.145.22:11:51.73/vb/01,03,usb,yes,38,62 2006.145.22:11:51.73/vb/02,04,usb,yes,33,54 2006.145.22:11:51.73/vb/03,04,usb,yes,30,36 2006.145.22:11:51.73/vb/04,04,usb,yes,34,33 2006.145.22:11:51.73/vb/05,04,usb,yes,28,30 2006.145.22:11:51.73/vb/06,04,usb,yes,33,29 2006.145.22:11:51.73/vb/07,04,usb,yes,32,32 2006.145.22:11:51.73/vb/08,04,usb,yes,29,33 2006.145.22:11:51.97/vblo/01,629.99,yes,locked 2006.145.22:11:51.97/vblo/02,634.99,yes,locked 2006.145.22:11:51.97/vblo/03,649.99,yes,locked 2006.145.22:11:51.97/vblo/04,679.99,yes,locked 2006.145.22:11:51.97/vblo/05,709.99,yes,locked 2006.145.22:11:51.97/vblo/06,719.99,yes,locked 2006.145.22:11:51.97/vblo/07,734.99,yes,locked 2006.145.22:11:51.97/vblo/08,744.99,yes,locked 2006.145.22:11:52.12/vabw/8 2006.145.22:11:52.27/vbbw/8 2006.145.22:11:52.36/xfe/off,on,14.0 2006.145.22:11:52.73/ifatt/23,28,28,28 2006.145.22:11:53.07/fmout-gps/S +3.7E-08 2006.145.22:11:53.11:!2006.145.22:13:59 2006.145.22:13:59.01:data_valid=off 2006.145.22:13:59.02:"et 2006.145.22:13:59.02:!+3s 2006.145.22:14:02.03:"tape 2006.145.22:14:02.04:postob 2006.145.22:14:02.16/cable/+6.5495E-03 2006.145.22:14:02.17/wx/17.50,1020.1,82 2006.145.22:14:02.23/fmout-gps/S +3.7E-08 2006.145.22:14:02.24:scan_name=145-2214,jd0605,320 2006.145.22:14:02.24:source=cta26,033930.94,-014635.8,2000.0,cw 2006.145.22:14:04.14#flagr#flagr/antenna,new-source 2006.145.22:14:04.15:checkk5 2006.145.22:14:04.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.22:14:05.05/chk_autoobs//k5ts2/ autoobs is running! 2006.145.22:14:05.51/chk_autoobs//k5ts3/ autoobs is running! 2006.145.22:14:05.95/chk_autoobs//k5ts4/ autoobs is running! 2006.145.22:14:06.37/chk_obsdata//k5ts1/T1452211??a.dat file size is correct (nominal:520MB, actual:516MB). 2006.145.22:14:06.82/chk_obsdata//k5ts2/T1452211??b.dat file size is correct (nominal:520MB, actual:516MB). 2006.145.22:14:07.26/chk_obsdata//k5ts3/T1452211??c.dat file size is correct (nominal:520MB, actual:516MB). 2006.145.22:14:07.70/chk_obsdata//k5ts4/T1452211??d.dat file size is correct (nominal:520MB, actual:516MB). 2006.145.22:14:08.47/k5log//k5ts1_log_newline 2006.145.22:14:09.22/k5log//k5ts2_log_newline 2006.145.22:14:09.97/k5log//k5ts3_log_newline 2006.145.22:14:10.71/k5log//k5ts4_log_newline 2006.145.22:14:10.73/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.22:14:10.73:setupk4=1 2006.145.22:14:10.74$setupk4/echo=on 2006.145.22:14:10.74$setupk4/pcalon 2006.145.22:14:10.74$pcalon/"no phase cal control is implemented here 2006.145.22:14:10.74$setupk4/"tpicd=stop 2006.145.22:14:10.74$setupk4/"rec=synch_on 2006.145.22:14:10.74$setupk4/"rec_mode=128 2006.145.22:14:10.74$setupk4/!* 2006.145.22:14:10.74$setupk4/recpk4 2006.145.22:14:10.74$recpk4/recpatch= 2006.145.22:14:10.74$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.22:14:10.74$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.22:14:10.74$setupk4/vck44 2006.145.22:14:10.74$vck44/valo=1,524.99 2006.145.22:14:10.74#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.22:14:10.74#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.22:14:10.74#ibcon#ireg 17 cls_cnt 0 2006.145.22:14:10.74#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:14:10.74#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:14:10.74#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:14:10.75#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.22:14:10.80#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:14:10.80#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:14:10.80#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.22:14:10.80#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.22:14:10.80$vck44/va=1,8 2006.145.22:14:10.80#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.22:14:10.80#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.22:14:10.80#ibcon#ireg 11 cls_cnt 2 2006.145.22:14:10.80#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:14:10.80#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:14:10.80#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:14:10.82#ibcon#[25=AT01-08\r\n] 2006.145.22:14:10.85#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:14:10.85#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:14:10.85#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.22:14:10.85#ibcon#ireg 7 cls_cnt 0 2006.145.22:14:10.85#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:14:10.97#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:14:10.97#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:14:10.99#ibcon#[25=USB\r\n] 2006.145.22:14:11.04#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:14:11.04#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:14:11.04#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.22:14:11.04#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.22:14:11.04$vck44/valo=2,534.99 2006.145.22:14:11.04#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.22:14:11.04#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.22:14:11.04#ibcon#ireg 17 cls_cnt 0 2006.145.22:14:11.04#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:14:11.04#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:14:11.04#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:14:11.06#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.22:14:11.10#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:14:11.10#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:14:11.10#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.22:14:11.10#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.22:14:11.10$vck44/va=2,7 2006.145.22:14:11.10#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.22:14:11.10#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.22:14:11.10#ibcon#ireg 11 cls_cnt 2 2006.145.22:14:11.10#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:14:11.16#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:14:11.16#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:14:11.18#ibcon#[25=AT02-07\r\n] 2006.145.22:14:11.21#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:14:11.21#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:14:11.21#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.22:14:11.21#ibcon#ireg 7 cls_cnt 0 2006.145.22:14:11.21#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:14:11.33#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:14:11.33#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:14:11.35#ibcon#[25=USB\r\n] 2006.145.22:14:11.38#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:14:11.38#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:14:11.38#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.22:14:11.38#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.22:14:11.38$vck44/valo=3,564.99 2006.145.22:14:11.38#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.22:14:11.38#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.22:14:11.38#ibcon#ireg 17 cls_cnt 0 2006.145.22:14:11.38#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:14:11.38#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:14:11.38#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:14:11.40#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.22:14:11.44#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:14:11.44#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:14:11.44#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.22:14:11.44#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.22:14:11.44$vck44/va=3,8 2006.145.22:14:11.44#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.22:14:11.44#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.22:14:11.44#ibcon#ireg 11 cls_cnt 2 2006.145.22:14:11.44#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.22:14:11.50#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.22:14:11.50#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.22:14:11.52#ibcon#[25=AT03-08\r\n] 2006.145.22:14:11.55#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.22:14:11.55#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.22:14:11.55#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.22:14:11.55#ibcon#ireg 7 cls_cnt 0 2006.145.22:14:11.55#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.22:14:11.67#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.22:14:11.67#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.22:14:11.69#ibcon#[25=USB\r\n] 2006.145.22:14:11.72#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.22:14:11.72#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.22:14:11.72#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.22:14:11.72#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.22:14:11.72$vck44/valo=4,624.99 2006.145.22:14:11.72#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.22:14:11.72#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.22:14:11.72#ibcon#ireg 17 cls_cnt 0 2006.145.22:14:11.72#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:14:11.72#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:14:11.72#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:14:11.74#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.22:14:11.78#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:14:11.78#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:14:11.78#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.22:14:11.78#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.22:14:11.78$vck44/va=4,7 2006.145.22:14:11.78#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.22:14:11.78#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.22:14:11.78#ibcon#ireg 11 cls_cnt 2 2006.145.22:14:11.78#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:14:11.84#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:14:11.84#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:14:11.86#ibcon#[25=AT04-07\r\n] 2006.145.22:14:11.89#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:14:11.89#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:14:11.89#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.22:14:11.89#ibcon#ireg 7 cls_cnt 0 2006.145.22:14:11.89#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:14:12.01#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:14:12.01#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:14:12.03#ibcon#[25=USB\r\n] 2006.145.22:14:12.06#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:14:12.06#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:14:12.06#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.22:14:12.06#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.22:14:12.06$vck44/valo=5,734.99 2006.145.22:14:12.06#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.22:14:12.06#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.22:14:12.06#ibcon#ireg 17 cls_cnt 0 2006.145.22:14:12.06#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:14:12.06#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:14:12.06#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:14:12.08#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.22:14:12.12#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:14:12.12#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:14:12.12#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.22:14:12.12#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.22:14:12.12$vck44/va=5,4 2006.145.22:14:12.12#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.22:14:12.12#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.22:14:12.12#ibcon#ireg 11 cls_cnt 2 2006.145.22:14:12.12#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:14:12.18#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:14:12.18#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:14:12.20#ibcon#[25=AT05-04\r\n] 2006.145.22:14:12.23#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:14:12.23#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:14:12.23#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.22:14:12.23#ibcon#ireg 7 cls_cnt 0 2006.145.22:14:12.23#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:14:12.36#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:14:12.36#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:14:12.37#ibcon#[25=USB\r\n] 2006.145.22:14:12.40#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:14:12.40#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:14:12.40#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.22:14:12.40#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.22:14:12.40$vck44/valo=6,814.99 2006.145.22:14:12.40#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.22:14:12.40#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.22:14:12.40#ibcon#ireg 17 cls_cnt 0 2006.145.22:14:12.40#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:14:12.40#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:14:12.40#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:14:12.43#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.22:14:12.47#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:14:12.47#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:14:12.47#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.22:14:12.47#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.22:14:12.47$vck44/va=6,4 2006.145.22:14:12.47#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.22:14:12.47#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.22:14:12.47#ibcon#ireg 11 cls_cnt 2 2006.145.22:14:12.47#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.22:14:12.52#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.22:14:12.52#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.22:14:12.54#ibcon#[25=AT06-04\r\n] 2006.145.22:14:12.57#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.22:14:12.57#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.22:14:12.57#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.22:14:12.57#ibcon#ireg 7 cls_cnt 0 2006.145.22:14:12.57#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.22:14:12.69#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.22:14:12.69#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.22:14:12.71#ibcon#[25=USB\r\n] 2006.145.22:14:12.74#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.22:14:12.74#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.22:14:12.74#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.22:14:12.74#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.22:14:12.74$vck44/valo=7,864.99 2006.145.22:14:12.74#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.22:14:12.74#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.22:14:12.74#ibcon#ireg 17 cls_cnt 0 2006.145.22:14:12.74#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:14:12.74#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:14:12.74#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:14:12.76#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.22:14:12.80#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:14:12.80#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:14:12.80#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.22:14:12.80#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.22:14:12.80$vck44/va=7,4 2006.145.22:14:12.80#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.22:14:12.80#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.22:14:12.80#ibcon#ireg 11 cls_cnt 2 2006.145.22:14:12.80#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.22:14:12.86#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.22:14:12.86#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.22:14:12.88#ibcon#[25=AT07-04\r\n] 2006.145.22:14:12.91#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.22:14:12.91#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.22:14:12.91#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.22:14:12.91#ibcon#ireg 7 cls_cnt 0 2006.145.22:14:12.91#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.22:14:13.03#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.22:14:13.03#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.22:14:13.05#ibcon#[25=USB\r\n] 2006.145.22:14:13.08#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.22:14:13.08#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.22:14:13.08#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.22:14:13.08#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.22:14:13.08$vck44/valo=8,884.99 2006.145.22:14:13.08#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.22:14:13.08#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.22:14:13.08#ibcon#ireg 17 cls_cnt 0 2006.145.22:14:13.08#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.22:14:13.08#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.22:14:13.08#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.22:14:13.10#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.22:14:13.14#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.22:14:13.14#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.22:14:13.14#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.22:14:13.14#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.22:14:13.14$vck44/va=8,4 2006.145.22:14:13.14#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.22:14:13.14#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.22:14:13.14#ibcon#ireg 11 cls_cnt 2 2006.145.22:14:13.14#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.22:14:13.20#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.22:14:13.20#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.22:14:13.22#ibcon#[25=AT08-04\r\n] 2006.145.22:14:13.25#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.22:14:13.25#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.22:14:13.25#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.22:14:13.25#ibcon#ireg 7 cls_cnt 0 2006.145.22:14:13.25#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.22:14:13.37#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.22:14:13.37#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.22:14:13.39#ibcon#[25=USB\r\n] 2006.145.22:14:13.42#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.22:14:13.42#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.22:14:13.42#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.22:14:13.42#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.22:14:13.42$vck44/vblo=1,629.99 2006.145.22:14:13.42#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.22:14:13.42#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.22:14:13.42#ibcon#ireg 17 cls_cnt 0 2006.145.22:14:13.42#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:14:13.42#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:14:13.42#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:14:13.44#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.22:14:13.48#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:14:13.48#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:14:13.48#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.22:14:13.48#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.22:14:13.48$vck44/vb=1,3 2006.145.22:14:13.48#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.22:14:13.48#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.22:14:13.48#ibcon#ireg 11 cls_cnt 2 2006.145.22:14:13.48#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.22:14:13.48#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.22:14:13.48#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.22:14:13.51#ibcon#[27=AT01-03\r\n] 2006.145.22:14:13.53#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.22:14:13.53#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.22:14:13.53#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.22:14:13.53#ibcon#ireg 7 cls_cnt 0 2006.145.22:14:13.53#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.22:14:13.65#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.22:14:13.65#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.22:14:13.67#ibcon#[27=USB\r\n] 2006.145.22:14:13.70#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.22:14:13.70#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.22:14:13.70#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.22:14:13.70#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.22:14:13.70$vck44/vblo=2,634.99 2006.145.22:14:13.70#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.22:14:13.70#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.22:14:13.70#ibcon#ireg 17 cls_cnt 0 2006.145.22:14:13.70#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:14:13.70#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:14:13.70#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:14:13.72#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.22:14:13.76#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:14:13.76#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:14:13.76#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.22:14:13.76#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.22:14:13.76$vck44/vb=2,4 2006.145.22:14:13.76#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.22:14:13.76#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.22:14:13.76#ibcon#ireg 11 cls_cnt 2 2006.145.22:14:13.76#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:14:13.82#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:14:13.82#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:14:13.84#ibcon#[27=AT02-04\r\n] 2006.145.22:14:13.87#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:14:13.87#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:14:13.87#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.22:14:13.87#ibcon#ireg 7 cls_cnt 0 2006.145.22:14:13.87#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:14:13.99#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:14:13.99#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:14:14.01#ibcon#[27=USB\r\n] 2006.145.22:14:14.04#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:14:14.04#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:14:14.04#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.22:14:14.04#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.22:14:14.04$vck44/vblo=3,649.99 2006.145.22:14:14.04#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.22:14:14.04#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.22:14:14.04#ibcon#ireg 17 cls_cnt 0 2006.145.22:14:14.04#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:14:14.04#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:14:14.04#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:14:14.06#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.22:14:14.10#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:14:14.10#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:14:14.10#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.22:14:14.10#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.22:14:14.10$vck44/vb=3,4 2006.145.22:14:14.10#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.22:14:14.10#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.22:14:14.10#ibcon#ireg 11 cls_cnt 2 2006.145.22:14:14.10#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:14:14.16#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:14:14.16#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:14:14.18#ibcon#[27=AT03-04\r\n] 2006.145.22:14:14.21#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:14:14.21#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:14:14.21#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.22:14:14.21#ibcon#ireg 7 cls_cnt 0 2006.145.22:14:14.21#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:14:14.33#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:14:14.33#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:14:14.35#ibcon#[27=USB\r\n] 2006.145.22:14:14.38#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:14:14.38#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:14:14.38#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.22:14:14.38#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.22:14:14.38$vck44/vblo=4,679.99 2006.145.22:14:14.38#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.22:14:14.38#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.22:14:14.38#ibcon#ireg 17 cls_cnt 0 2006.145.22:14:14.38#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:14:14.38#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:14:14.38#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:14:14.40#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.22:14:14.44#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:14:14.44#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:14:14.44#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.22:14:14.44#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.22:14:14.44$vck44/vb=4,4 2006.145.22:14:14.44#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.22:14:14.44#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.22:14:14.44#ibcon#ireg 11 cls_cnt 2 2006.145.22:14:14.44#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.22:14:14.50#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.22:14:14.50#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.22:14:14.52#ibcon#[27=AT04-04\r\n] 2006.145.22:14:14.55#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.22:14:14.55#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.22:14:14.55#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.22:14:14.55#ibcon#ireg 7 cls_cnt 0 2006.145.22:14:14.55#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.22:14:14.67#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.22:14:14.67#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.22:14:14.69#ibcon#[27=USB\r\n] 2006.145.22:14:14.72#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.22:14:14.72#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.22:14:14.72#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.22:14:14.72#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.22:14:14.72$vck44/vblo=5,709.99 2006.145.22:14:14.72#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.22:14:14.72#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.22:14:14.72#ibcon#ireg 17 cls_cnt 0 2006.145.22:14:14.72#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:14:14.72#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:14:14.72#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:14:14.74#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.22:14:14.78#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:14:14.78#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:14:14.78#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.22:14:14.78#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.22:14:14.78$vck44/vb=5,4 2006.145.22:14:14.78#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.22:14:14.78#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.22:14:14.78#ibcon#ireg 11 cls_cnt 2 2006.145.22:14:14.78#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:14:14.84#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:14:14.84#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:14:14.86#ibcon#[27=AT05-04\r\n] 2006.145.22:14:14.89#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:14:14.89#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:14:14.89#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.22:14:14.89#ibcon#ireg 7 cls_cnt 0 2006.145.22:14:14.89#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:14:15.01#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:14:15.01#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:14:15.03#ibcon#[27=USB\r\n] 2006.145.22:14:15.06#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:14:15.06#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:14:15.06#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.22:14:15.06#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.22:14:15.06$vck44/vblo=6,719.99 2006.145.22:14:15.06#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.22:14:15.06#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.22:14:15.06#ibcon#ireg 17 cls_cnt 0 2006.145.22:14:15.06#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:14:15.06#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:14:15.06#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:14:15.08#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.22:14:15.12#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:14:15.12#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:14:15.12#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.22:14:15.12#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.22:14:15.12$vck44/vb=6,4 2006.145.22:14:15.12#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.22:14:15.12#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.22:14:15.12#ibcon#ireg 11 cls_cnt 2 2006.145.22:14:15.12#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:14:15.18#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:14:15.18#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:14:15.20#ibcon#[27=AT06-04\r\n] 2006.145.22:14:15.23#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:14:15.23#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:14:15.23#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.22:14:15.23#ibcon#ireg 7 cls_cnt 0 2006.145.22:14:15.23#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:14:15.35#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:14:15.35#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:14:15.37#ibcon#[27=USB\r\n] 2006.145.22:14:15.40#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:14:15.40#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:14:15.40#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.22:14:15.40#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.22:14:15.40$vck44/vblo=7,734.99 2006.145.22:14:15.40#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.22:14:15.40#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.22:14:15.40#ibcon#ireg 17 cls_cnt 0 2006.145.22:14:15.40#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:14:15.40#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:14:15.40#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:14:15.42#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.22:14:15.46#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:14:15.46#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:14:15.46#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.22:14:15.46#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.22:14:15.46$vck44/vb=7,4 2006.145.22:14:15.46#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.22:14:15.46#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.22:14:15.46#ibcon#ireg 11 cls_cnt 2 2006.145.22:14:15.46#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.22:14:15.52#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.22:14:15.52#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.22:14:15.54#ibcon#[27=AT07-04\r\n] 2006.145.22:14:15.57#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.22:14:15.57#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.22:14:15.57#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.22:14:15.57#ibcon#ireg 7 cls_cnt 0 2006.145.22:14:15.57#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.22:14:15.69#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.22:14:15.69#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.22:14:15.71#ibcon#[27=USB\r\n] 2006.145.22:14:15.74#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.22:14:15.74#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.22:14:15.74#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.22:14:15.74#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.22:14:15.74$vck44/vblo=8,744.99 2006.145.22:14:15.74#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.22:14:15.74#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.22:14:15.74#ibcon#ireg 17 cls_cnt 0 2006.145.22:14:15.74#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:14:15.74#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:14:15.74#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:14:15.76#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.22:14:15.80#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:14:15.80#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:14:15.80#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.22:14:15.80#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.22:14:15.80$vck44/vb=8,4 2006.145.22:14:15.80#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.22:14:15.80#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.22:14:15.80#ibcon#ireg 11 cls_cnt 2 2006.145.22:14:15.80#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.22:14:15.86#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.22:14:15.86#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.22:14:15.88#ibcon#[27=AT08-04\r\n] 2006.145.22:14:15.91#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.22:14:15.91#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.22:14:15.91#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.22:14:15.91#ibcon#ireg 7 cls_cnt 0 2006.145.22:14:15.91#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.22:14:16.03#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.22:14:16.03#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.22:14:16.05#ibcon#[27=USB\r\n] 2006.145.22:14:16.08#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.22:14:16.08#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.22:14:16.08#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.22:14:16.08#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.22:14:16.08$vck44/vabw=wide 2006.145.22:14:16.08#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.22:14:16.08#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.22:14:16.08#ibcon#ireg 8 cls_cnt 0 2006.145.22:14:16.08#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.22:14:16.08#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.22:14:16.08#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.22:14:16.10#ibcon#[25=BW32\r\n] 2006.145.22:14:16.13#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.22:14:16.13#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.22:14:16.13#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.22:14:16.13#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.22:14:16.13$vck44/vbbw=wide 2006.145.22:14:16.13#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.22:14:16.13#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.22:14:16.13#ibcon#ireg 8 cls_cnt 0 2006.145.22:14:16.13#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.22:14:16.20#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.22:14:16.20#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.22:14:16.22#ibcon#[27=BW32\r\n] 2006.145.22:14:16.25#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.22:14:16.25#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.22:14:16.25#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.22:14:16.25#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.22:14:16.25$setupk4/ifdk4 2006.145.22:14:16.25$ifdk4/lo= 2006.145.22:14:16.25$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.22:14:16.25$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.22:14:16.25$ifdk4/patch= 2006.145.22:14:16.25$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.22:14:16.25$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.22:14:16.25$setupk4/!*+20s 2006.145.22:14:17.23#abcon#<5=/07 1.5 3.2 17.51 821020.1\r\n> 2006.145.22:14:17.25#abcon#{5=INTERFACE CLEAR} 2006.145.22:14:17.31#abcon#[5=S1D000X0/0*\r\n] 2006.145.22:14:23.14#trakl#Source acquired 2006.145.22:14:23.14#flagr#flagr/antenna,acquired 2006.145.22:14:27.40#abcon#<5=/07 1.5 3.2 17.52 821020.1\r\n> 2006.145.22:14:27.42#abcon#{5=INTERFACE CLEAR} 2006.145.22:14:27.48#abcon#[5=S1D000X0/0*\r\n] 2006.145.22:14:30.75$setupk4/"tpicd 2006.145.22:14:30.75$setupk4/echo=off 2006.145.22:14:30.75$setupk4/xlog=off 2006.145.22:14:30.75:!2006.145.22:14:32 2006.145.22:14:32.00:preob 2006.145.22:14:33.14/onsource/TRACKING 2006.145.22:14:33.14:!2006.145.22:14:42 2006.145.22:14:42.00:"tape 2006.145.22:14:42.00:"st=record 2006.145.22:14:42.00:data_valid=on 2006.145.22:14:42.00:midob 2006.145.22:14:42.14/onsource/TRACKING 2006.145.22:14:42.14/wx/17.52,1020.1,82 2006.145.22:14:42.22/cable/+6.5484E-03 2006.145.22:14:43.31/va/01,08,usb,yes,29,32 2006.145.22:14:43.31/va/02,07,usb,yes,31,32 2006.145.22:14:43.31/va/03,08,usb,yes,29,30 2006.145.22:14:43.31/va/04,07,usb,yes,33,34 2006.145.22:14:43.31/va/05,04,usb,yes,28,29 2006.145.22:14:43.31/va/06,04,usb,yes,32,32 2006.145.22:14:43.31/va/07,04,usb,yes,32,33 2006.145.22:14:43.31/va/08,04,usb,yes,27,33 2006.145.22:14:43.54/valo/01,524.99,yes,locked 2006.145.22:14:43.54/valo/02,534.99,yes,locked 2006.145.22:14:43.54/valo/03,564.99,yes,locked 2006.145.22:14:43.54/valo/04,624.99,yes,locked 2006.145.22:14:43.54/valo/05,734.99,yes,locked 2006.145.22:14:43.54/valo/06,814.99,yes,locked 2006.145.22:14:43.54/valo/07,864.99,yes,locked 2006.145.22:14:43.54/valo/08,884.99,yes,locked 2006.145.22:14:44.63/vb/01,03,usb,yes,37,34 2006.145.22:14:44.63/vb/02,04,usb,yes,32,32 2006.145.22:14:44.63/vb/03,04,usb,yes,29,32 2006.145.22:14:44.63/vb/04,04,usb,yes,33,32 2006.145.22:14:44.63/vb/05,04,usb,yes,26,28 2006.145.22:14:44.63/vb/06,04,usb,yes,30,26 2006.145.22:14:44.63/vb/07,04,usb,yes,30,30 2006.145.22:14:44.63/vb/08,04,usb,yes,28,31 2006.145.22:14:44.86/vblo/01,629.99,yes,locked 2006.145.22:14:44.86/vblo/02,634.99,yes,locked 2006.145.22:14:44.86/vblo/03,649.99,yes,locked 2006.145.22:14:44.86/vblo/04,679.99,yes,locked 2006.145.22:14:44.86/vblo/05,709.99,yes,locked 2006.145.22:14:44.86/vblo/06,719.99,yes,locked 2006.145.22:14:44.86/vblo/07,734.99,yes,locked 2006.145.22:14:44.86/vblo/08,744.99,yes,locked 2006.145.22:14:45.01/vabw/8 2006.145.22:14:45.16/vbbw/8 2006.145.22:14:45.25/xfe/off,on,15.2 2006.145.22:14:45.64/ifatt/23,28,28,28 2006.145.22:14:46.07/fmout-gps/S +3.7E-08 2006.145.22:14:46.11:!2006.145.22:20:02 2006.145.22:20:02.00:data_valid=off 2006.145.22:20:02.00:"et 2006.145.22:20:02.01:!+3s 2006.145.22:20:05.02:"tape 2006.145.22:20:05.02:postob 2006.145.22:20:05.18/cable/+6.5458E-03 2006.145.22:20:05.19/wx/17.75,1020.2,80 2006.145.22:20:05.27/fmout-gps/S +3.9E-08 2006.145.22:20:05.27:scan_name=145-2228,jd0605,190 2006.145.22:20:05.28:source=3c446,222547.26,-045701.4,2000.0,cw 2006.145.22:20:06.13#flagr#flagr/antenna,new-source 2006.145.22:20:06.14:checkk5 2006.145.22:20:06.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.22:20:07.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.22:20:07.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.22:20:07.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.22:20:08.33/chk_obsdata//k5ts1/T1452214??a.dat file size is correct (nominal:1280MB, actual:1276MB). 2006.145.22:20:08.77/chk_obsdata//k5ts2/T1452214??b.dat file size is correct (nominal:1280MB, actual:1276MB). 2006.145.22:20:09.21/chk_obsdata//k5ts3/T1452214??c.dat file size is correct (nominal:1280MB, actual:1276MB). 2006.145.22:20:09.64/chk_obsdata//k5ts4/T1452214??d.dat file size is correct (nominal:1280MB, actual:1276MB). 2006.145.22:20:10.39/k5log//k5ts1_log_newline 2006.145.22:20:11.15/k5log//k5ts2_log_newline 2006.145.22:20:11.89/k5log//k5ts3_log_newline 2006.145.22:20:12.62/k5log//k5ts4_log_newline 2006.145.22:20:12.65/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.22:20:12.65:setupk4=1 2006.145.22:20:12.65$setupk4/echo=on 2006.145.22:20:12.65$setupk4/pcalon 2006.145.22:20:12.65$pcalon/"no phase cal control is implemented here 2006.145.22:20:12.65$setupk4/"tpicd=stop 2006.145.22:20:12.65$setupk4/"rec=synch_on 2006.145.22:20:12.65$setupk4/"rec_mode=128 2006.145.22:20:12.65$setupk4/!* 2006.145.22:20:12.65$setupk4/recpk4 2006.145.22:20:12.65$recpk4/recpatch= 2006.145.22:20:12.65$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.22:20:12.65$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.22:20:12.65$setupk4/vck44 2006.145.22:20:12.65$vck44/valo=1,524.99 2006.145.22:20:12.65#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.22:20:12.65#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.22:20:12.65#ibcon#ireg 17 cls_cnt 0 2006.145.22:20:12.65#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:20:12.65#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:20:12.65#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:20:12.69#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.22:20:12.74#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:20:12.74#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:20:12.74#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.22:20:12.74#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.22:20:12.74$vck44/va=1,8 2006.145.22:20:12.74#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.22:20:12.74#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.22:20:12.74#ibcon#ireg 11 cls_cnt 2 2006.145.22:20:12.74#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.22:20:12.74#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.22:20:12.74#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.22:20:12.76#ibcon#[25=AT01-08\r\n] 2006.145.22:20:12.79#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.22:20:12.79#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.22:20:12.79#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.22:20:12.79#ibcon#ireg 7 cls_cnt 0 2006.145.22:20:12.79#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.22:20:12.91#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.22:20:12.91#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.22:20:12.93#ibcon#[25=USB\r\n] 2006.145.22:20:12.96#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.22:20:12.96#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.22:20:12.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.22:20:12.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.22:20:12.96$vck44/valo=2,534.99 2006.145.22:20:12.96#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.22:20:12.96#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.22:20:12.96#ibcon#ireg 17 cls_cnt 0 2006.145.22:20:12.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.22:20:12.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.22:20:12.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.22:20:12.99#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.22:20:13.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.22:20:13.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.22:20:13.03#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.22:20:13.03#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.22:20:13.03$vck44/va=2,7 2006.145.22:20:13.03#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.22:20:13.03#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.22:20:13.03#ibcon#ireg 11 cls_cnt 2 2006.145.22:20:13.03#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.22:20:13.08#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.22:20:13.08#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.22:20:13.10#ibcon#[25=AT02-07\r\n] 2006.145.22:20:13.13#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.22:20:13.13#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.22:20:13.13#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.22:20:13.13#ibcon#ireg 7 cls_cnt 0 2006.145.22:20:13.13#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.22:20:13.25#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.22:20:13.25#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.22:20:13.27#ibcon#[25=USB\r\n] 2006.145.22:20:13.30#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.22:20:13.30#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.22:20:13.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.22:20:13.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.22:20:13.30$vck44/valo=3,564.99 2006.145.22:20:13.30#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.22:20:13.30#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.22:20:13.30#ibcon#ireg 17 cls_cnt 0 2006.145.22:20:13.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:20:13.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:20:13.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:20:13.32#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.22:20:13.33#abcon#<5=/08 1.5 3.2 17.75 791020.2\r\n> 2006.145.22:20:13.35#abcon#{5=INTERFACE CLEAR} 2006.145.22:20:13.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:20:13.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:20:13.36#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.22:20:13.36#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.22:20:13.36$vck44/va=3,8 2006.145.22:20:13.36#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.22:20:13.36#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.22:20:13.36#ibcon#ireg 11 cls_cnt 2 2006.145.22:20:13.36#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.22:20:13.41#abcon#[5=S1D000X0/0*\r\n] 2006.145.22:20:13.42#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.22:20:13.42#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.22:20:13.44#ibcon#[25=AT03-08\r\n] 2006.145.22:20:13.47#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.22:20:13.47#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.22:20:13.47#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.22:20:13.47#ibcon#ireg 7 cls_cnt 0 2006.145.22:20:13.47#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.22:20:13.59#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.22:20:13.59#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.22:20:13.61#ibcon#[25=USB\r\n] 2006.145.22:20:13.64#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.22:20:13.64#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.22:20:13.64#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.22:20:13.64#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.22:20:13.64$vck44/valo=4,624.99 2006.145.22:20:13.64#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.22:20:13.64#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.22:20:13.64#ibcon#ireg 17 cls_cnt 0 2006.145.22:20:13.64#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:20:13.64#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:20:13.64#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:20:13.66#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.22:20:13.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:20:13.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:20:13.70#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.22:20:13.70#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.22:20:13.70$vck44/va=4,7 2006.145.22:20:13.70#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.22:20:13.70#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.22:20:13.70#ibcon#ireg 11 cls_cnt 2 2006.145.22:20:13.70#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.22:20:13.76#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.22:20:13.76#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.22:20:13.78#ibcon#[25=AT04-07\r\n] 2006.145.22:20:13.81#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.22:20:13.81#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.22:20:13.81#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.22:20:13.81#ibcon#ireg 7 cls_cnt 0 2006.145.22:20:13.81#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.22:20:13.93#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.22:20:13.93#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.22:20:13.95#ibcon#[25=USB\r\n] 2006.145.22:20:13.98#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.22:20:13.98#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.22:20:13.98#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.22:20:13.98#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.22:20:13.98$vck44/valo=5,734.99 2006.145.22:20:13.98#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.22:20:13.98#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.22:20:13.98#ibcon#ireg 17 cls_cnt 0 2006.145.22:20:13.98#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:20:13.98#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:20:13.98#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:20:14.00#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.22:20:14.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:20:14.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:20:14.04#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.22:20:14.04#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.22:20:14.04$vck44/va=5,4 2006.145.22:20:14.04#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.22:20:14.04#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.22:20:14.04#ibcon#ireg 11 cls_cnt 2 2006.145.22:20:14.04#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.22:20:14.10#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.22:20:14.10#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.22:20:14.12#ibcon#[25=AT05-04\r\n] 2006.145.22:20:14.15#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.22:20:14.15#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.22:20:14.15#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.22:20:14.15#ibcon#ireg 7 cls_cnt 0 2006.145.22:20:14.15#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.22:20:14.27#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.22:20:14.27#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.22:20:14.29#ibcon#[25=USB\r\n] 2006.145.22:20:14.32#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.22:20:14.32#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.22:20:14.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.22:20:14.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.22:20:14.32$vck44/valo=6,814.99 2006.145.22:20:14.32#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.22:20:14.32#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.22:20:14.32#ibcon#ireg 17 cls_cnt 0 2006.145.22:20:14.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:20:14.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:20:14.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:20:14.34#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.22:20:14.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:20:14.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:20:14.38#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.22:20:14.38#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.22:20:14.38$vck44/va=6,4 2006.145.22:20:14.38#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.22:20:14.38#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.22:20:14.38#ibcon#ireg 11 cls_cnt 2 2006.145.22:20:14.38#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:20:14.44#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:20:14.44#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:20:14.46#ibcon#[25=AT06-04\r\n] 2006.145.22:20:14.49#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:20:14.49#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:20:14.49#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.22:20:14.49#ibcon#ireg 7 cls_cnt 0 2006.145.22:20:14.49#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:20:14.61#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:20:14.61#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:20:14.63#ibcon#[25=USB\r\n] 2006.145.22:20:14.66#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:20:14.66#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:20:14.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.22:20:14.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.22:20:14.66$vck44/valo=7,864.99 2006.145.22:20:14.66#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.22:20:14.66#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.22:20:14.66#ibcon#ireg 17 cls_cnt 0 2006.145.22:20:14.66#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:20:14.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:20:14.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:20:14.68#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.22:20:14.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:20:14.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:20:14.72#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.22:20:14.72#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.22:20:14.72$vck44/va=7,4 2006.145.22:20:14.72#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.22:20:14.72#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.22:20:14.72#ibcon#ireg 11 cls_cnt 2 2006.145.22:20:14.72#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:20:14.78#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:20:14.78#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:20:14.80#ibcon#[25=AT07-04\r\n] 2006.145.22:20:14.83#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:20:14.83#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:20:14.83#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.22:20:14.83#ibcon#ireg 7 cls_cnt 0 2006.145.22:20:14.83#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:20:14.95#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:20:14.95#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:20:14.97#ibcon#[25=USB\r\n] 2006.145.22:20:15.00#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:20:15.00#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:20:15.00#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.22:20:15.00#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.22:20:15.00$vck44/valo=8,884.99 2006.145.22:20:15.00#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.22:20:15.00#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.22:20:15.00#ibcon#ireg 17 cls_cnt 0 2006.145.22:20:15.00#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:20:15.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:20:15.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:20:15.02#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.22:20:15.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:20:15.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:20:15.06#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.22:20:15.06#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.22:20:15.06$vck44/va=8,4 2006.145.22:20:15.06#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.22:20:15.06#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.22:20:15.06#ibcon#ireg 11 cls_cnt 2 2006.145.22:20:15.06#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.22:20:15.13#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.22:20:15.13#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.22:20:15.15#ibcon#[25=AT08-04\r\n] 2006.145.22:20:15.18#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.22:20:15.18#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.22:20:15.18#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.22:20:15.18#ibcon#ireg 7 cls_cnt 0 2006.145.22:20:15.18#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.22:20:15.30#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.22:20:15.30#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.22:20:15.32#ibcon#[25=USB\r\n] 2006.145.22:20:15.37#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.22:20:15.37#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.22:20:15.37#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.22:20:15.37#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.22:20:15.37$vck44/vblo=1,629.99 2006.145.22:20:15.37#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.22:20:15.37#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.22:20:15.37#ibcon#ireg 17 cls_cnt 0 2006.145.22:20:15.37#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:20:15.37#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:20:15.37#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:20:15.38#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.22:20:15.42#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:20:15.42#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:20:15.42#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.22:20:15.42#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.22:20:15.42$vck44/vb=1,3 2006.145.22:20:15.42#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.22:20:15.42#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.22:20:15.42#ibcon#ireg 11 cls_cnt 2 2006.145.22:20:15.42#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.22:20:15.42#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.22:20:15.42#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.22:20:15.44#ibcon#[27=AT01-03\r\n] 2006.145.22:20:15.47#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.22:20:15.47#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.22:20:15.47#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.22:20:15.47#ibcon#ireg 7 cls_cnt 0 2006.145.22:20:15.47#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.22:20:15.59#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.22:20:15.59#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.22:20:15.61#ibcon#[27=USB\r\n] 2006.145.22:20:15.64#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.22:20:15.64#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.22:20:15.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.22:20:15.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.22:20:15.64$vck44/vblo=2,634.99 2006.145.22:20:15.64#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.22:20:15.64#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.22:20:15.64#ibcon#ireg 17 cls_cnt 0 2006.145.22:20:15.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.22:20:15.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.22:20:15.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.22:20:15.66#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.22:20:15.70#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.22:20:15.70#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.22:20:15.70#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.22:20:15.70#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.22:20:15.70$vck44/vb=2,4 2006.145.22:20:15.70#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.22:20:15.70#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.22:20:15.70#ibcon#ireg 11 cls_cnt 2 2006.145.22:20:15.70#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.22:20:15.76#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.22:20:15.76#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.22:20:15.78#ibcon#[27=AT02-04\r\n] 2006.145.22:20:15.81#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.22:20:15.81#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.22:20:15.81#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.22:20:15.81#ibcon#ireg 7 cls_cnt 0 2006.145.22:20:15.81#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.22:20:15.93#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.22:20:15.93#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.22:20:15.95#ibcon#[27=USB\r\n] 2006.145.22:20:15.98#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.22:20:15.98#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.22:20:15.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.22:20:15.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.22:20:15.98$vck44/vblo=3,649.99 2006.145.22:20:15.98#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.22:20:15.98#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.22:20:15.98#ibcon#ireg 17 cls_cnt 0 2006.145.22:20:15.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.22:20:15.98#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.22:20:15.98#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.22:20:16.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.22:20:16.04#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.22:20:16.04#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.22:20:16.04#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.22:20:16.04#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.22:20:16.04$vck44/vb=3,4 2006.145.22:20:16.04#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.22:20:16.04#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.22:20:16.04#ibcon#ireg 11 cls_cnt 2 2006.145.22:20:16.04#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.22:20:16.10#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.22:20:16.10#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.22:20:16.12#ibcon#[27=AT03-04\r\n] 2006.145.22:20:16.15#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.22:20:16.15#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.22:20:16.15#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.22:20:16.15#ibcon#ireg 7 cls_cnt 0 2006.145.22:20:16.15#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.22:20:16.27#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.22:20:16.27#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.22:20:16.29#ibcon#[27=USB\r\n] 2006.145.22:20:16.32#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.22:20:16.32#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.22:20:16.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.22:20:16.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.22:20:16.32$vck44/vblo=4,679.99 2006.145.22:20:16.32#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.22:20:16.32#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.22:20:16.32#ibcon#ireg 17 cls_cnt 0 2006.145.22:20:16.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.22:20:16.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.22:20:16.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.22:20:16.34#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.22:20:16.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.22:20:16.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.22:20:16.38#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.22:20:16.38#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.22:20:16.38$vck44/vb=4,4 2006.145.22:20:16.38#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.22:20:16.38#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.22:20:16.38#ibcon#ireg 11 cls_cnt 2 2006.145.22:20:16.38#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.22:20:16.44#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.22:20:16.44#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.22:20:16.46#ibcon#[27=AT04-04\r\n] 2006.145.22:20:16.49#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.22:20:16.49#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.22:20:16.49#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.22:20:16.49#ibcon#ireg 7 cls_cnt 0 2006.145.22:20:16.49#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.22:20:16.61#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.22:20:16.61#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.22:20:16.63#ibcon#[27=USB\r\n] 2006.145.22:20:16.66#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.22:20:16.66#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.22:20:16.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.22:20:16.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.22:20:16.66$vck44/vblo=5,709.99 2006.145.22:20:16.66#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.22:20:16.66#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.22:20:16.66#ibcon#ireg 17 cls_cnt 0 2006.145.22:20:16.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:20:16.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:20:16.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:20:16.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.22:20:16.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:20:16.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:20:16.72#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.22:20:16.72#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.22:20:16.72$vck44/vb=5,4 2006.145.22:20:16.72#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.22:20:16.72#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.22:20:16.72#ibcon#ireg 11 cls_cnt 2 2006.145.22:20:16.72#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.22:20:16.78#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.22:20:16.78#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.22:20:16.80#ibcon#[27=AT05-04\r\n] 2006.145.22:20:16.83#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.22:20:16.83#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.22:20:16.83#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.22:20:16.83#ibcon#ireg 7 cls_cnt 0 2006.145.22:20:16.83#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.22:20:16.95#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.22:20:16.95#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.22:20:16.97#ibcon#[27=USB\r\n] 2006.145.22:20:17.00#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.22:20:17.00#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.22:20:17.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.22:20:17.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.22:20:17.00$vck44/vblo=6,719.99 2006.145.22:20:17.00#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.22:20:17.00#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.22:20:17.00#ibcon#ireg 17 cls_cnt 0 2006.145.22:20:17.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:20:17.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:20:17.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:20:17.02#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.22:20:17.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:20:17.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:20:17.06#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.22:20:17.06#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.22:20:17.06$vck44/vb=6,4 2006.145.22:20:17.06#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.22:20:17.06#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.22:20:17.06#ibcon#ireg 11 cls_cnt 2 2006.145.22:20:17.06#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.22:20:17.12#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.22:20:17.12#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.22:20:17.14#ibcon#[27=AT06-04\r\n] 2006.145.22:20:17.17#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.22:20:17.17#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.22:20:17.17#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.22:20:17.17#ibcon#ireg 7 cls_cnt 0 2006.145.22:20:17.17#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.22:20:17.29#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.22:20:17.29#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.22:20:17.31#ibcon#[27=USB\r\n] 2006.145.22:20:17.34#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.22:20:17.34#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.22:20:17.34#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.22:20:17.34#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.22:20:17.34$vck44/vblo=7,734.99 2006.145.22:20:17.34#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.22:20:17.34#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.22:20:17.34#ibcon#ireg 17 cls_cnt 0 2006.145.22:20:17.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:20:17.34#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:20:17.34#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:20:17.36#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.22:20:17.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:20:17.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:20:17.40#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.22:20:17.40#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.22:20:17.40$vck44/vb=7,4 2006.145.22:20:17.40#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.22:20:17.40#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.22:20:17.40#ibcon#ireg 11 cls_cnt 2 2006.145.22:20:17.40#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:20:17.46#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:20:17.46#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:20:17.48#ibcon#[27=AT07-04\r\n] 2006.145.22:20:17.51#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:20:17.51#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:20:17.51#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.22:20:17.51#ibcon#ireg 7 cls_cnt 0 2006.145.22:20:17.51#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:20:17.63#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:20:17.63#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:20:17.65#ibcon#[27=USB\r\n] 2006.145.22:20:17.68#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:20:17.68#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:20:17.68#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.22:20:17.68#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.22:20:17.68$vck44/vblo=8,744.99 2006.145.22:20:17.68#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.22:20:17.68#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.22:20:17.68#ibcon#ireg 17 cls_cnt 0 2006.145.22:20:17.68#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:20:17.68#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:20:17.68#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:20:17.70#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.22:20:17.74#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:20:17.74#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:20:17.74#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.22:20:17.74#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.22:20:17.74$vck44/vb=8,4 2006.145.22:20:17.74#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.22:20:17.74#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.22:20:17.74#ibcon#ireg 11 cls_cnt 2 2006.145.22:20:17.74#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:20:17.80#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:20:17.80#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:20:17.82#ibcon#[27=AT08-04\r\n] 2006.145.22:20:17.85#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:20:17.85#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:20:17.85#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.22:20:17.85#ibcon#ireg 7 cls_cnt 0 2006.145.22:20:17.85#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:20:17.97#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:20:17.97#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:20:17.99#ibcon#[27=USB\r\n] 2006.145.22:20:18.02#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:20:18.02#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:20:18.02#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.22:20:18.02#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.22:20:18.02$vck44/vabw=wide 2006.145.22:20:18.02#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.22:20:18.02#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.22:20:18.02#ibcon#ireg 8 cls_cnt 0 2006.145.22:20:18.02#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:20:18.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:20:18.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:20:18.04#ibcon#[25=BW32\r\n] 2006.145.22:20:18.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:20:18.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:20:18.07#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.22:20:18.07#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.22:20:18.07$vck44/vbbw=wide 2006.145.22:20:18.07#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.22:20:18.07#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.22:20:18.07#ibcon#ireg 8 cls_cnt 0 2006.145.22:20:18.07#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.22:20:18.14#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.22:20:18.14#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.22:20:18.16#ibcon#[27=BW32\r\n] 2006.145.22:20:18.19#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.22:20:18.19#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.22:20:18.19#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.22:20:18.19#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.22:20:18.19$setupk4/ifdk4 2006.145.22:20:18.19$ifdk4/lo= 2006.145.22:20:18.19$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.22:20:18.19$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.22:20:18.19$ifdk4/patch= 2006.145.22:20:18.19$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.22:20:18.19$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.22:20:18.19$setupk4/!*+20s 2006.145.22:20:23.50#abcon#<5=/08 1.5 3.2 17.76 791020.2\r\n> 2006.145.22:20:23.52#abcon#{5=INTERFACE CLEAR} 2006.145.22:20:23.59#abcon#[5=S1D000X0/0*\r\n] 2006.145.22:20:32.66$setupk4/"tpicd 2006.145.22:20:32.66$setupk4/echo=off 2006.145.22:20:32.66$setupk4/xlog=off 2006.145.22:20:32.66:!2006.145.22:28:24 2006.145.22:20:46.13#trakl#Source acquired 2006.145.22:20:46.13#flagr#flagr/antenna,acquired 2006.145.22:28:24.00:preob 2006.145.22:28:24.13/onsource/TRACKING 2006.145.22:28:24.13:!2006.145.22:28:34 2006.145.22:28:34.00:"tape 2006.145.22:28:34.00:"st=record 2006.145.22:28:34.00:data_valid=on 2006.145.22:28:34.00:midob 2006.145.22:28:35.13/onsource/TRACKING 2006.145.22:28:35.13/wx/17.91,1020.4,79 2006.145.22:28:35.29/cable/+6.5497E-03 2006.145.22:28:36.38/va/01,08,usb,yes,29,31 2006.145.22:28:36.38/va/02,07,usb,yes,31,31 2006.145.22:28:36.38/va/03,08,usb,yes,28,29 2006.145.22:28:36.38/va/04,07,usb,yes,32,33 2006.145.22:28:36.38/va/05,04,usb,yes,28,28 2006.145.22:28:36.38/va/06,04,usb,yes,31,31 2006.145.22:28:36.38/va/07,04,usb,yes,31,32 2006.145.22:28:36.38/va/08,04,usb,yes,27,32 2006.145.22:28:36.61/valo/01,524.99,yes,locked 2006.145.22:28:36.61/valo/02,534.99,yes,locked 2006.145.22:28:36.61/valo/03,564.99,yes,locked 2006.145.22:28:36.61/valo/04,624.99,yes,locked 2006.145.22:28:36.61/valo/05,734.99,yes,locked 2006.145.22:28:36.61/valo/06,814.99,yes,locked 2006.145.22:28:36.61/valo/07,864.99,yes,locked 2006.145.22:28:36.61/valo/08,884.99,yes,locked 2006.145.22:28:37.70/vb/01,03,usb,yes,36,34 2006.145.22:28:37.70/vb/02,04,usb,yes,31,31 2006.145.22:28:37.70/vb/03,04,usb,yes,28,31 2006.145.22:28:37.70/vb/04,04,usb,yes,33,32 2006.145.22:28:37.70/vb/05,04,usb,yes,25,28 2006.145.22:28:37.70/vb/06,04,usb,yes,30,26 2006.145.22:28:37.70/vb/07,04,usb,yes,29,29 2006.145.22:28:37.70/vb/08,04,usb,yes,27,30 2006.145.22:28:37.93/vblo/01,629.99,yes,locked 2006.145.22:28:37.93/vblo/02,634.99,yes,locked 2006.145.22:28:37.93/vblo/03,649.99,yes,locked 2006.145.22:28:37.93/vblo/04,679.99,yes,locked 2006.145.22:28:37.93/vblo/05,709.99,yes,locked 2006.145.22:28:37.93/vblo/06,719.99,yes,locked 2006.145.22:28:37.93/vblo/07,734.99,yes,locked 2006.145.22:28:37.93/vblo/08,744.99,yes,locked 2006.145.22:28:38.08/vabw/8 2006.145.22:28:38.23/vbbw/8 2006.145.22:28:38.32/xfe/off,on,14.7 2006.145.22:28:38.69/ifatt/23,28,28,28 2006.145.22:28:39.08/fmout-gps/S +3.9E-08 2006.145.22:28:39.12:!2006.145.22:31:44 2006.145.22:31:44.00:data_valid=off 2006.145.22:31:44.00:"et 2006.145.22:31:44.01:!+3s 2006.145.22:31:47.02:"tape 2006.145.22:31:47.02:postob 2006.145.22:31:47.20/cable/+6.5510E-03 2006.145.22:31:47.20/wx/17.89,1020.5,79 2006.145.22:31:48.08/fmout-gps/S +4.0E-08 2006.145.22:31:48.08:scan_name=145-2234,jd0605,70 2006.145.22:31:48.08:source=2136+141,213901.31,142336.0,2000.0,cw 2006.145.22:31:49.14#flagr#flagr/antenna,new-source 2006.145.22:31:49.14:checkk5 2006.145.22:31:49.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.22:31:50.00/chk_autoobs//k5ts2/ autoobs is running! 2006.145.22:31:50.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.22:31:50.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.22:31:51.32/chk_obsdata//k5ts1/T1452228??a.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.22:31:51.76/chk_obsdata//k5ts2/T1452228??b.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.22:31:52.20/chk_obsdata//k5ts3/T1452228??c.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.22:31:52.65/chk_obsdata//k5ts4/T1452228??d.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.22:31:53.42/k5log//k5ts1_log_newline 2006.145.22:31:54.16/k5log//k5ts2_log_newline 2006.145.22:31:54.90/k5log//k5ts3_log_newline 2006.145.22:31:55.65/k5log//k5ts4_log_newline 2006.145.22:31:55.68/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.22:31:55.68:setupk4=1 2006.145.22:31:55.68$setupk4/echo=on 2006.145.22:31:55.68$setupk4/pcalon 2006.145.22:31:55.68$pcalon/"no phase cal control is implemented here 2006.145.22:31:55.68$setupk4/"tpicd=stop 2006.145.22:31:55.68$setupk4/"rec=synch_on 2006.145.22:31:55.68$setupk4/"rec_mode=128 2006.145.22:31:55.68$setupk4/!* 2006.145.22:31:55.68$setupk4/recpk4 2006.145.22:31:55.68$recpk4/recpatch= 2006.145.22:31:55.68$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.22:31:55.68$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.22:31:55.68$setupk4/vck44 2006.145.22:31:55.68$vck44/valo=1,524.99 2006.145.22:31:55.68#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.22:31:55.68#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.22:31:55.68#ibcon#ireg 17 cls_cnt 0 2006.145.22:31:55.68#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.22:31:55.68#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.22:31:55.68#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.22:31:55.72#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.22:31:55.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.22:31:55.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.22:31:55.77#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.22:31:55.77#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.22:31:55.77$vck44/va=1,8 2006.145.22:31:55.77#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.22:31:55.77#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.22:31:55.77#ibcon#ireg 11 cls_cnt 2 2006.145.22:31:55.77#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.22:31:55.77#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.22:31:55.77#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.22:31:55.79#ibcon#[25=AT01-08\r\n] 2006.145.22:31:55.82#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.22:31:55.82#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.22:31:55.82#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.22:31:55.82#ibcon#ireg 7 cls_cnt 0 2006.145.22:31:55.82#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.22:31:55.94#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.22:31:55.94#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.22:31:55.96#ibcon#[25=USB\r\n] 2006.145.22:31:55.99#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.22:31:55.99#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.22:31:55.99#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.22:31:55.99#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.22:31:55.99$vck44/valo=2,534.99 2006.145.22:31:55.99#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.22:31:55.99#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.22:31:55.99#ibcon#ireg 17 cls_cnt 0 2006.145.22:31:55.99#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.22:31:55.99#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.22:31:55.99#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.22:31:56.02#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.22:31:56.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.22:31:56.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.22:31:56.06#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.22:31:56.06#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.22:31:56.06$vck44/va=2,7 2006.145.22:31:56.06#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.22:31:56.06#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.22:31:56.06#ibcon#ireg 11 cls_cnt 2 2006.145.22:31:56.06#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.22:31:56.11#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.22:31:56.11#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.22:31:56.13#ibcon#[25=AT02-07\r\n] 2006.145.22:31:56.16#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.22:31:56.16#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.22:31:56.16#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.22:31:56.16#ibcon#ireg 7 cls_cnt 0 2006.145.22:31:56.16#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.22:31:56.28#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.22:31:56.28#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.22:31:56.30#ibcon#[25=USB\r\n] 2006.145.22:31:56.33#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.22:31:56.33#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.22:31:56.33#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.22:31:56.33#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.22:31:56.33$vck44/valo=3,564.99 2006.145.22:31:56.33#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.22:31:56.33#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.22:31:56.33#ibcon#ireg 17 cls_cnt 0 2006.145.22:31:56.33#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.22:31:56.33#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.22:31:56.33#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.22:31:56.35#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.22:31:56.39#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.22:31:56.39#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.22:31:56.39#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.22:31:56.39#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.22:31:56.39$vck44/va=3,8 2006.145.22:31:56.39#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.22:31:56.39#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.22:31:56.39#ibcon#ireg 11 cls_cnt 2 2006.145.22:31:56.39#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.22:31:56.45#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.22:31:56.45#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.22:31:56.47#ibcon#[25=AT03-08\r\n] 2006.145.22:31:56.50#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.22:31:56.50#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.22:31:56.50#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.22:31:56.50#ibcon#ireg 7 cls_cnt 0 2006.145.22:31:56.50#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.22:31:56.62#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.22:31:56.62#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.22:31:56.64#ibcon#[25=USB\r\n] 2006.145.22:31:56.67#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.22:31:56.67#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.22:31:56.67#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.22:31:56.67#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.22:31:56.67$vck44/valo=4,624.99 2006.145.22:31:56.67#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.22:31:56.67#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.22:31:56.67#ibcon#ireg 17 cls_cnt 0 2006.145.22:31:56.67#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.22:31:56.67#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.22:31:56.67#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.22:31:56.69#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.22:31:56.73#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.22:31:56.73#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.22:31:56.73#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.22:31:56.73#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.22:31:56.73$vck44/va=4,7 2006.145.22:31:56.73#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.22:31:56.73#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.22:31:56.73#ibcon#ireg 11 cls_cnt 2 2006.145.22:31:56.73#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:31:56.79#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:31:56.79#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:31:56.81#ibcon#[25=AT04-07\r\n] 2006.145.22:31:56.84#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:31:56.84#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:31:56.84#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.22:31:56.84#ibcon#ireg 7 cls_cnt 0 2006.145.22:31:56.84#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:31:56.96#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:31:56.96#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:31:56.98#ibcon#[25=USB\r\n] 2006.145.22:31:57.01#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:31:57.01#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:31:57.01#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.22:31:57.01#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.22:31:57.01$vck44/valo=5,734.99 2006.145.22:31:57.01#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.22:31:57.01#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.22:31:57.01#ibcon#ireg 17 cls_cnt 0 2006.145.22:31:57.01#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.22:31:57.01#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.22:31:57.01#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.22:31:57.03#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.22:31:57.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.22:31:57.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.22:31:57.07#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.22:31:57.07#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.22:31:57.07$vck44/va=5,4 2006.145.22:31:57.07#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.22:31:57.07#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.22:31:57.07#ibcon#ireg 11 cls_cnt 2 2006.145.22:31:57.07#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.22:31:57.13#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.22:31:57.13#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.22:31:57.15#ibcon#[25=AT05-04\r\n] 2006.145.22:31:57.18#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.22:31:57.18#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.22:31:57.18#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.22:31:57.18#ibcon#ireg 7 cls_cnt 0 2006.145.22:31:57.18#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.22:31:57.30#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.22:31:57.30#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.22:31:57.32#ibcon#[25=USB\r\n] 2006.145.22:31:57.35#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.22:31:57.35#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.22:31:57.35#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.22:31:57.35#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.22:31:57.35$vck44/valo=6,814.99 2006.145.22:31:57.35#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.22:31:57.35#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.22:31:57.35#ibcon#ireg 17 cls_cnt 0 2006.145.22:31:57.35#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.22:31:57.35#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.22:31:57.35#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.22:31:57.37#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.22:31:57.41#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.22:31:57.41#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.22:31:57.41#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.22:31:57.41#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.22:31:57.41$vck44/va=6,4 2006.145.22:31:57.41#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.22:31:57.41#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.22:31:57.41#ibcon#ireg 11 cls_cnt 2 2006.145.22:31:57.41#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.22:31:57.47#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.22:31:57.47#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.22:31:57.49#ibcon#[25=AT06-04\r\n] 2006.145.22:31:57.52#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.22:31:57.52#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.22:31:57.52#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.22:31:57.52#ibcon#ireg 7 cls_cnt 0 2006.145.22:31:57.52#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.22:31:57.64#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.22:31:57.64#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.22:31:57.66#ibcon#[25=USB\r\n] 2006.145.22:31:57.69#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.22:31:57.69#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.22:31:57.69#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.22:31:57.69#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.22:31:57.69$vck44/valo=7,864.99 2006.145.22:31:57.69#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.22:31:57.69#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.22:31:57.69#ibcon#ireg 17 cls_cnt 0 2006.145.22:31:57.69#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.22:31:57.69#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.22:31:57.69#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.22:31:57.71#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.22:31:57.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.22:31:57.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.22:31:57.75#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.22:31:57.75#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.22:31:57.75$vck44/va=7,4 2006.145.22:31:57.75#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.22:31:57.75#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.22:31:57.75#ibcon#ireg 11 cls_cnt 2 2006.145.22:31:57.75#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.22:31:57.81#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.22:31:57.81#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.22:31:57.83#ibcon#[25=AT07-04\r\n] 2006.145.22:31:57.86#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.22:31:57.86#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.22:31:57.86#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.22:31:57.86#ibcon#ireg 7 cls_cnt 0 2006.145.22:31:57.86#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.22:31:57.98#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.22:31:57.98#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.22:31:57.99#abcon#<5=/08 1.5 3.5 17.89 791020.5\r\n> 2006.145.22:31:58.00#ibcon#[25=USB\r\n] 2006.145.22:31:58.01#abcon#{5=INTERFACE CLEAR} 2006.145.22:31:58.03#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.22:31:58.03#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.22:31:58.03#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.22:31:58.03#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.22:31:58.03$vck44/valo=8,884.99 2006.145.22:31:58.03#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.22:31:58.03#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.22:31:58.03#ibcon#ireg 17 cls_cnt 0 2006.145.22:31:58.03#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:31:58.03#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:31:58.03#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:31:58.05#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.22:31:58.07#abcon#[5=S1D000X0/0*\r\n] 2006.145.22:31:58.09#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:31:58.09#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:31:58.09#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.22:31:58.09#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.22:31:58.09$vck44/va=8,4 2006.145.22:31:58.09#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.22:31:58.09#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.22:31:58.09#ibcon#ireg 11 cls_cnt 2 2006.145.22:31:58.09#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.22:31:58.15#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.22:31:58.15#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.22:31:58.17#ibcon#[25=AT08-04\r\n] 2006.145.22:31:58.20#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.22:31:58.20#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.22:31:58.20#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.22:31:58.20#ibcon#ireg 7 cls_cnt 0 2006.145.22:31:58.20#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.22:31:58.32#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.22:31:58.32#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.22:31:58.34#ibcon#[25=USB\r\n] 2006.145.22:31:58.37#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.22:31:58.37#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.22:31:58.37#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.22:31:58.37#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.22:31:58.37$vck44/vblo=1,629.99 2006.145.22:31:58.37#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.22:31:58.37#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.22:31:58.37#ibcon#ireg 17 cls_cnt 0 2006.145.22:31:58.37#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.22:31:58.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.22:31:58.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.22:31:58.39#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.22:31:58.43#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.22:31:58.43#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.22:31:58.43#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.22:31:58.43#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.22:31:58.43$vck44/vb=1,3 2006.145.22:31:58.43#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.22:31:58.43#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.22:31:58.43#ibcon#ireg 11 cls_cnt 2 2006.145.22:31:58.43#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.22:31:58.43#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.22:31:58.43#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.22:31:58.45#ibcon#[27=AT01-03\r\n] 2006.145.22:31:58.48#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.22:31:58.48#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.22:31:58.48#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.22:31:58.48#ibcon#ireg 7 cls_cnt 0 2006.145.22:31:58.48#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.22:31:58.60#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.22:31:58.60#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.22:31:58.62#ibcon#[27=USB\r\n] 2006.145.22:31:58.65#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.22:31:58.65#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.22:31:58.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.22:31:58.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.22:31:58.65$vck44/vblo=2,634.99 2006.145.22:31:58.65#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.22:31:58.65#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.22:31:58.65#ibcon#ireg 17 cls_cnt 0 2006.145.22:31:58.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.22:31:58.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.22:31:58.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.22:31:58.67#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.22:31:58.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.22:31:58.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.22:31:58.71#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.22:31:58.71#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.22:31:58.71$vck44/vb=2,4 2006.145.22:31:58.71#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.22:31:58.71#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.22:31:58.71#ibcon#ireg 11 cls_cnt 2 2006.145.22:31:58.71#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.22:31:58.77#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.22:31:58.77#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.22:31:58.79#ibcon#[27=AT02-04\r\n] 2006.145.22:31:58.82#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.22:31:58.82#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.22:31:58.82#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.22:31:58.82#ibcon#ireg 7 cls_cnt 0 2006.145.22:31:58.82#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.22:31:58.94#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.22:31:58.94#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.22:31:58.96#ibcon#[27=USB\r\n] 2006.145.22:31:58.99#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.22:31:58.99#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.22:31:58.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.22:31:58.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.22:31:58.99$vck44/vblo=3,649.99 2006.145.22:31:58.99#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.22:31:58.99#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.22:31:58.99#ibcon#ireg 17 cls_cnt 0 2006.145.22:31:58.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.22:31:58.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.22:31:58.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.22:31:59.01#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.22:31:59.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.22:31:59.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.22:31:59.05#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.22:31:59.05#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.22:31:59.05$vck44/vb=3,4 2006.145.22:31:59.05#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.22:31:59.05#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.22:31:59.05#ibcon#ireg 11 cls_cnt 2 2006.145.22:31:59.05#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.22:31:59.11#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.22:31:59.11#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.22:31:59.13#ibcon#[27=AT03-04\r\n] 2006.145.22:31:59.16#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.22:31:59.16#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.22:31:59.16#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.22:31:59.16#ibcon#ireg 7 cls_cnt 0 2006.145.22:31:59.16#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.22:31:59.28#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.22:31:59.28#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.22:31:59.30#ibcon#[27=USB\r\n] 2006.145.22:31:59.33#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.22:31:59.33#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.22:31:59.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.22:31:59.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.22:31:59.33$vck44/vblo=4,679.99 2006.145.22:31:59.33#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.22:31:59.33#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.22:31:59.33#ibcon#ireg 17 cls_cnt 0 2006.145.22:31:59.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.22:31:59.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.22:31:59.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.22:31:59.35#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.22:31:59.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.22:31:59.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.22:31:59.39#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.22:31:59.39#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.22:31:59.39$vck44/vb=4,4 2006.145.22:31:59.39#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.22:31:59.39#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.22:31:59.39#ibcon#ireg 11 cls_cnt 2 2006.145.22:31:59.39#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:31:59.45#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:31:59.45#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:31:59.47#ibcon#[27=AT04-04\r\n] 2006.145.22:31:59.50#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:31:59.50#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:31:59.50#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.22:31:59.50#ibcon#ireg 7 cls_cnt 0 2006.145.22:31:59.50#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:31:59.62#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:31:59.62#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:31:59.64#ibcon#[27=USB\r\n] 2006.145.22:31:59.67#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:31:59.67#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:31:59.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.22:31:59.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.22:31:59.67$vck44/vblo=5,709.99 2006.145.22:31:59.67#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.22:31:59.67#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.22:31:59.67#ibcon#ireg 17 cls_cnt 0 2006.145.22:31:59.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.22:31:59.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.22:31:59.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.22:31:59.69#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.22:31:59.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.22:31:59.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.22:31:59.73#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.22:31:59.73#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.22:31:59.73$vck44/vb=5,4 2006.145.22:31:59.73#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.22:31:59.73#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.22:31:59.73#ibcon#ireg 11 cls_cnt 2 2006.145.22:31:59.73#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.22:31:59.79#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.22:31:59.79#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.22:31:59.81#ibcon#[27=AT05-04\r\n] 2006.145.22:31:59.84#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.22:31:59.84#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.22:31:59.84#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.22:31:59.84#ibcon#ireg 7 cls_cnt 0 2006.145.22:31:59.84#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.22:31:59.96#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.22:31:59.96#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.22:31:59.98#ibcon#[27=USB\r\n] 2006.145.22:32:00.01#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.22:32:00.01#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.22:32:00.01#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.22:32:00.01#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.22:32:00.01$vck44/vblo=6,719.99 2006.145.22:32:00.01#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.22:32:00.01#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.22:32:00.01#ibcon#ireg 17 cls_cnt 0 2006.145.22:32:00.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.22:32:00.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.22:32:00.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.22:32:00.03#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.22:32:00.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.22:32:00.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.22:32:00.07#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.22:32:00.07#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.22:32:00.07$vck44/vb=6,4 2006.145.22:32:00.07#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.22:32:00.07#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.22:32:00.07#ibcon#ireg 11 cls_cnt 2 2006.145.22:32:00.07#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.22:32:00.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.22:32:00.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.22:32:00.15#ibcon#[27=AT06-04\r\n] 2006.145.22:32:00.18#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.22:32:00.18#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.22:32:00.18#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.22:32:00.18#ibcon#ireg 7 cls_cnt 0 2006.145.22:32:00.18#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.22:32:00.30#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.22:32:00.30#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.22:32:00.32#ibcon#[27=USB\r\n] 2006.145.22:32:00.35#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.22:32:00.35#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.22:32:00.35#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.22:32:00.35#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.22:32:00.35$vck44/vblo=7,734.99 2006.145.22:32:00.35#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.22:32:00.35#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.22:32:00.35#ibcon#ireg 17 cls_cnt 0 2006.145.22:32:00.35#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.22:32:00.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.22:32:00.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.22:32:00.37#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.22:32:00.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.22:32:00.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.22:32:00.41#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.22:32:00.41#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.22:32:00.41$vck44/vb=7,4 2006.145.22:32:00.41#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.22:32:00.41#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.22:32:00.41#ibcon#ireg 11 cls_cnt 2 2006.145.22:32:00.41#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.22:32:00.47#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.22:32:00.47#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.22:32:00.49#ibcon#[27=AT07-04\r\n] 2006.145.22:32:00.52#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.22:32:00.52#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.22:32:00.52#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.22:32:00.52#ibcon#ireg 7 cls_cnt 0 2006.145.22:32:00.52#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.22:32:00.64#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.22:32:00.64#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.22:32:00.66#ibcon#[27=USB\r\n] 2006.145.22:32:00.69#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.22:32:00.69#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.22:32:00.69#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.22:32:00.69#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.22:32:00.69$vck44/vblo=8,744.99 2006.145.22:32:00.69#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.22:32:00.69#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.22:32:00.69#ibcon#ireg 17 cls_cnt 0 2006.145.22:32:00.69#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.22:32:00.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.22:32:00.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.22:32:00.71#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.22:32:00.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.22:32:00.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.22:32:00.75#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.22:32:00.75#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.22:32:00.75$vck44/vb=8,4 2006.145.22:32:00.75#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.22:32:00.75#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.22:32:00.75#ibcon#ireg 11 cls_cnt 2 2006.145.22:32:00.75#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.22:32:00.81#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.22:32:00.81#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.22:32:00.83#ibcon#[27=AT08-04\r\n] 2006.145.22:32:00.86#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.22:32:00.86#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.22:32:00.86#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.22:32:00.86#ibcon#ireg 7 cls_cnt 0 2006.145.22:32:00.86#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.22:32:00.98#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.22:32:00.98#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.22:32:01.00#ibcon#[27=USB\r\n] 2006.145.22:32:01.03#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.22:32:01.03#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.22:32:01.03#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.22:32:01.03#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.22:32:01.03$vck44/vabw=wide 2006.145.22:32:01.03#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.22:32:01.03#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.22:32:01.03#ibcon#ireg 8 cls_cnt 0 2006.145.22:32:01.03#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.22:32:01.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.22:32:01.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.22:32:01.05#ibcon#[25=BW32\r\n] 2006.145.22:32:01.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.22:32:01.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.22:32:01.08#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.22:32:01.08#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.22:32:01.08$vck44/vbbw=wide 2006.145.22:32:01.08#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.22:32:01.08#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.22:32:01.08#ibcon#ireg 8 cls_cnt 0 2006.145.22:32:01.08#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:32:01.15#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:32:01.15#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:32:01.17#ibcon#[27=BW32\r\n] 2006.145.22:32:01.20#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:32:01.20#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:32:01.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.22:32:01.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.22:32:01.20$setupk4/ifdk4 2006.145.22:32:01.20$ifdk4/lo= 2006.145.22:32:01.20$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.22:32:01.20$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.22:32:01.20$ifdk4/patch= 2006.145.22:32:01.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.22:32:01.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.22:32:01.20$setupk4/!*+20s 2006.145.22:32:08.14#trakl#Source acquired 2006.145.22:32:08.14#flagr#flagr/antenna,acquired 2006.145.22:32:08.16#abcon#<5=/08 1.5 3.5 17.89 791020.5\r\n> 2006.145.22:32:08.18#abcon#{5=INTERFACE CLEAR} 2006.145.22:32:08.24#abcon#[5=S1D000X0/0*\r\n] 2006.145.22:32:15.69$setupk4/"tpicd 2006.145.22:32:15.69$setupk4/echo=off 2006.145.22:32:15.69$setupk4/xlog=off 2006.145.22:32:15.69:!2006.145.22:34:00 2006.145.22:34:00.00:preob 2006.145.22:34:00.14/onsource/TRACKING 2006.145.22:34:00.14:!2006.145.22:34:10 2006.145.22:34:10.00:"tape 2006.145.22:34:10.00:"st=record 2006.145.22:34:10.00:data_valid=on 2006.145.22:34:10.00:midob 2006.145.22:34:11.14/onsource/TRACKING 2006.145.22:34:11.14/wx/17.87,1020.5,81 2006.145.22:34:11.37/cable/+6.5493E-03 2006.145.22:34:12.46/va/01,08,usb,yes,28,30 2006.145.22:34:12.46/va/02,07,usb,yes,30,31 2006.145.22:34:12.46/va/03,08,usb,yes,27,29 2006.145.22:34:12.46/va/04,07,usb,yes,31,33 2006.145.22:34:12.46/va/05,04,usb,yes,27,28 2006.145.22:34:12.46/va/06,04,usb,yes,30,30 2006.145.22:34:12.46/va/07,04,usb,yes,31,32 2006.145.22:34:12.46/va/08,04,usb,yes,26,32 2006.145.22:34:12.69/valo/01,524.99,yes,locked 2006.145.22:34:12.69/valo/02,534.99,yes,locked 2006.145.22:34:12.69/valo/03,564.99,yes,locked 2006.145.22:34:12.69/valo/04,624.99,yes,locked 2006.145.22:34:12.69/valo/05,734.99,yes,locked 2006.145.22:34:12.69/valo/06,814.99,yes,locked 2006.145.22:34:12.69/valo/07,864.99,yes,locked 2006.145.22:34:12.69/valo/08,884.99,yes,locked 2006.145.22:34:13.78/vb/01,03,usb,yes,35,33 2006.145.22:34:13.78/vb/02,04,usb,yes,31,31 2006.145.22:34:13.78/vb/03,04,usb,yes,28,31 2006.145.22:34:13.78/vb/04,04,usb,yes,32,31 2006.145.22:34:13.78/vb/05,04,usb,yes,25,27 2006.145.22:34:13.78/vb/06,04,usb,yes,29,26 2006.145.22:34:13.78/vb/07,04,usb,yes,29,29 2006.145.22:34:13.78/vb/08,04,usb,yes,27,30 2006.145.22:34:14.01/vblo/01,629.99,yes,locked 2006.145.22:34:14.01/vblo/02,634.99,yes,locked 2006.145.22:34:14.01/vblo/03,649.99,yes,locked 2006.145.22:34:14.01/vblo/04,679.99,yes,locked 2006.145.22:34:14.01/vblo/05,709.99,yes,locked 2006.145.22:34:14.01/vblo/06,719.99,yes,locked 2006.145.22:34:14.01/vblo/07,734.99,yes,locked 2006.145.22:34:14.01/vblo/08,744.99,yes,locked 2006.145.22:34:14.16/vabw/8 2006.145.22:34:14.31/vbbw/8 2006.145.22:34:14.40/xfe/off,on,15.5 2006.145.22:34:14.78/ifatt/23,28,28,28 2006.145.22:34:15.08/fmout-gps/S +3.9E-08 2006.145.22:34:15.16:!2006.145.22:35:20 2006.145.22:35:20.00:data_valid=off 2006.145.22:35:20.00:"et 2006.145.22:35:20.00:!+3s 2006.145.22:35:23.02:"tape 2006.145.22:35:23.02:postob 2006.145.22:35:23.12/cable/+6.5492E-03 2006.145.22:35:23.12/wx/17.88,1020.5,81 2006.145.22:35:24.08/fmout-gps/S +3.9E-08 2006.145.22:35:24.08:scan_name=145-2239,jd0605,120 2006.145.22:35:24.08:source=2201+315,220314.98,314538.3,2000.0,cw 2006.145.22:35:25.14#flagr#flagr/antenna,new-source 2006.145.22:35:25.14:checkk5 2006.145.22:35:25.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.22:35:26.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.22:35:26.45/chk_autoobs//k5ts3/ autoobs is running! 2006.145.22:35:26.90/chk_autoobs//k5ts4/ autoobs is running! 2006.145.22:35:27.32/chk_obsdata//k5ts1/T1452234??a.dat file size is correct (nominal:280MB, actual:280MB). 2006.145.22:35:27.76/chk_obsdata//k5ts2/T1452234??b.dat file size is correct (nominal:280MB, actual:280MB). 2006.145.22:35:28.20/chk_obsdata//k5ts3/T1452234??c.dat file size is correct (nominal:280MB, actual:280MB). 2006.145.22:35:28.64/chk_obsdata//k5ts4/T1452234??d.dat file size is correct (nominal:280MB, actual:280MB). 2006.145.22:35:29.43/k5log//k5ts1_log_newline 2006.145.22:35:30.17/k5log//k5ts2_log_newline 2006.145.22:35:30.91/k5log//k5ts3_log_newline 2006.145.22:35:31.65/k5log//k5ts4_log_newline 2006.145.22:35:31.68/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.22:35:31.68:setupk4=1 2006.145.22:35:31.68$setupk4/echo=on 2006.145.22:35:31.68$setupk4/pcalon 2006.145.22:35:31.68$pcalon/"no phase cal control is implemented here 2006.145.22:35:31.68$setupk4/"tpicd=stop 2006.145.22:35:31.68$setupk4/"rec=synch_on 2006.145.22:35:31.68$setupk4/"rec_mode=128 2006.145.22:35:31.68$setupk4/!* 2006.145.22:35:31.68$setupk4/recpk4 2006.145.22:35:31.68$recpk4/recpatch= 2006.145.22:35:31.68$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.22:35:31.68$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.22:35:31.68$setupk4/vck44 2006.145.22:35:31.68$vck44/valo=1,524.99 2006.145.22:35:31.68#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.22:35:31.68#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.22:35:31.68#ibcon#ireg 17 cls_cnt 0 2006.145.22:35:31.68#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:35:31.68#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:35:31.68#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:35:31.72#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.22:35:31.77#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:35:31.77#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:35:31.77#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.22:35:31.77#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.22:35:31.77$vck44/va=1,8 2006.145.22:35:31.77#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.22:35:31.77#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.22:35:31.77#ibcon#ireg 11 cls_cnt 2 2006.145.22:35:31.77#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:35:31.77#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:35:31.77#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:35:31.79#ibcon#[25=AT01-08\r\n] 2006.145.22:35:31.81#abcon#<5=/08 1.5 3.5 17.88 821020.5\r\n> 2006.145.22:35:31.82#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:35:31.82#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:35:31.82#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.22:35:31.82#ibcon#ireg 7 cls_cnt 0 2006.145.22:35:31.82#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:35:31.83#abcon#{5=INTERFACE CLEAR} 2006.145.22:35:31.89#abcon#[5=S1D000X0/0*\r\n] 2006.145.22:35:31.94#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:35:31.94#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:35:31.96#ibcon#[25=USB\r\n] 2006.145.22:35:31.99#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:35:31.99#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:35:31.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.22:35:31.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.22:35:31.99$vck44/valo=2,534.99 2006.145.22:35:31.99#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.22:35:31.99#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.22:35:31.99#ibcon#ireg 17 cls_cnt 0 2006.145.22:35:31.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:35:31.99#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:35:31.99#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:35:32.02#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.22:35:32.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:35:32.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:35:32.06#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.22:35:32.06#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.22:35:32.06$vck44/va=2,7 2006.145.22:35:32.06#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.22:35:32.06#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.22:35:32.06#ibcon#ireg 11 cls_cnt 2 2006.145.22:35:32.06#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.22:35:32.11#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.22:35:32.11#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.22:35:32.13#ibcon#[25=AT02-07\r\n] 2006.145.22:35:32.16#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.22:35:32.16#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.22:35:32.16#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.22:35:32.16#ibcon#ireg 7 cls_cnt 0 2006.145.22:35:32.16#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.22:35:32.28#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.22:35:32.28#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.22:35:32.30#ibcon#[25=USB\r\n] 2006.145.22:35:32.33#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.22:35:32.33#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.22:35:32.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.22:35:32.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.22:35:32.33$vck44/valo=3,564.99 2006.145.22:35:32.33#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.22:35:32.33#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.22:35:32.33#ibcon#ireg 17 cls_cnt 0 2006.145.22:35:32.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:35:32.33#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:35:32.33#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:35:32.35#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.22:35:32.39#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:35:32.39#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:35:32.39#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.22:35:32.39#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.22:35:32.39$vck44/va=3,8 2006.145.22:35:32.39#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.22:35:32.39#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.22:35:32.39#ibcon#ireg 11 cls_cnt 2 2006.145.22:35:32.39#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:35:32.45#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:35:32.45#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:35:32.47#ibcon#[25=AT03-08\r\n] 2006.145.22:35:32.50#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:35:32.50#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:35:32.50#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.22:35:32.50#ibcon#ireg 7 cls_cnt 0 2006.145.22:35:32.50#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:35:32.62#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:35:32.62#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:35:32.64#ibcon#[25=USB\r\n] 2006.145.22:35:32.67#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:35:32.67#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:35:32.67#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.22:35:32.67#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.22:35:32.67$vck44/valo=4,624.99 2006.145.22:35:32.67#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.22:35:32.67#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.22:35:32.67#ibcon#ireg 17 cls_cnt 0 2006.145.22:35:32.67#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:35:32.67#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:35:32.67#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:35:32.69#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.22:35:32.73#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:35:32.73#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:35:32.73#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.22:35:32.73#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.22:35:32.73$vck44/va=4,7 2006.145.22:35:32.73#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.22:35:32.73#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.22:35:32.73#ibcon#ireg 11 cls_cnt 2 2006.145.22:35:32.73#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:35:32.79#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:35:32.79#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:35:32.81#ibcon#[25=AT04-07\r\n] 2006.145.22:35:32.84#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:35:32.84#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:35:32.84#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.22:35:32.84#ibcon#ireg 7 cls_cnt 0 2006.145.22:35:32.84#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:35:32.96#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:35:32.96#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:35:32.98#ibcon#[25=USB\r\n] 2006.145.22:35:33.01#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:35:33.01#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:35:33.01#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.22:35:33.01#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.22:35:33.01$vck44/valo=5,734.99 2006.145.22:35:33.01#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.22:35:33.01#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.22:35:33.01#ibcon#ireg 17 cls_cnt 0 2006.145.22:35:33.01#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:35:33.01#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:35:33.01#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:35:33.03#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.22:35:33.07#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:35:33.07#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:35:33.07#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.22:35:33.07#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.22:35:33.07$vck44/va=5,4 2006.145.22:35:33.07#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.22:35:33.07#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.22:35:33.07#ibcon#ireg 11 cls_cnt 2 2006.145.22:35:33.07#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.22:35:33.13#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.22:35:33.13#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.22:35:33.15#ibcon#[25=AT05-04\r\n] 2006.145.22:35:33.18#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.22:35:33.18#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.22:35:33.18#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.22:35:33.18#ibcon#ireg 7 cls_cnt 0 2006.145.22:35:33.18#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.22:35:33.30#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.22:35:33.30#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.22:35:33.32#ibcon#[25=USB\r\n] 2006.145.22:35:33.35#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.22:35:33.35#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.22:35:33.35#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.22:35:33.35#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.22:35:33.35$vck44/valo=6,814.99 2006.145.22:35:33.35#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.22:35:33.35#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.22:35:33.35#ibcon#ireg 17 cls_cnt 0 2006.145.22:35:33.35#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:35:33.35#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:35:33.35#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:35:33.37#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.22:35:33.41#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:35:33.41#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:35:33.41#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.22:35:33.41#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.22:35:33.41$vck44/va=6,4 2006.145.22:35:33.41#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.22:35:33.41#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.22:35:33.41#ibcon#ireg 11 cls_cnt 2 2006.145.22:35:33.41#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:35:33.47#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:35:33.47#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:35:33.49#ibcon#[25=AT06-04\r\n] 2006.145.22:35:33.52#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:35:33.52#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:35:33.52#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.22:35:33.52#ibcon#ireg 7 cls_cnt 0 2006.145.22:35:33.52#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:35:33.64#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:35:33.64#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:35:33.66#ibcon#[25=USB\r\n] 2006.145.22:35:33.69#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:35:33.69#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:35:33.69#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.22:35:33.69#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.22:35:33.69$vck44/valo=7,864.99 2006.145.22:35:33.69#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.22:35:33.69#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.22:35:33.69#ibcon#ireg 17 cls_cnt 0 2006.145.22:35:33.69#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:35:33.69#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:35:33.69#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:35:33.71#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.22:35:33.75#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:35:33.75#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:35:33.75#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.22:35:33.75#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.22:35:33.75$vck44/va=7,4 2006.145.22:35:33.75#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.22:35:33.75#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.22:35:33.75#ibcon#ireg 11 cls_cnt 2 2006.145.22:35:33.75#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:35:33.81#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:35:33.81#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:35:33.83#ibcon#[25=AT07-04\r\n] 2006.145.22:35:33.86#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:35:33.86#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:35:33.86#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.22:35:33.86#ibcon#ireg 7 cls_cnt 0 2006.145.22:35:33.86#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:35:33.98#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:35:33.98#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:35:34.00#ibcon#[25=USB\r\n] 2006.145.22:35:34.03#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:35:34.03#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:35:34.03#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.22:35:34.03#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.22:35:34.03$vck44/valo=8,884.99 2006.145.22:35:34.03#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.22:35:34.03#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.22:35:34.03#ibcon#ireg 17 cls_cnt 0 2006.145.22:35:34.03#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:35:34.03#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:35:34.03#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:35:34.05#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.22:35:34.09#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:35:34.09#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:35:34.09#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.22:35:34.09#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.22:35:34.09$vck44/va=8,4 2006.145.22:35:34.09#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.22:35:34.09#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.22:35:34.09#ibcon#ireg 11 cls_cnt 2 2006.145.22:35:34.09#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.22:35:34.15#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.22:35:34.15#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.22:35:34.17#ibcon#[25=AT08-04\r\n] 2006.145.22:35:34.20#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.22:35:34.20#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.22:35:34.20#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.22:35:34.20#ibcon#ireg 7 cls_cnt 0 2006.145.22:35:34.20#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.22:35:34.32#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.22:35:34.32#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.22:35:34.34#ibcon#[25=USB\r\n] 2006.145.22:35:34.37#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.22:35:34.37#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.22:35:34.37#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.22:35:34.37#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.22:35:34.37$vck44/vblo=1,629.99 2006.145.22:35:34.37#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.22:35:34.37#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.22:35:34.37#ibcon#ireg 17 cls_cnt 0 2006.145.22:35:34.37#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:35:34.37#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:35:34.37#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:35:34.40#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.22:35:34.44#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:35:34.44#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:35:34.44#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.22:35:34.44#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.22:35:34.44$vck44/vb=1,3 2006.145.22:35:34.44#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.22:35:34.44#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.22:35:34.44#ibcon#ireg 11 cls_cnt 2 2006.145.22:35:34.44#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.22:35:34.44#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.22:35:34.44#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.22:35:34.46#ibcon#[27=AT01-03\r\n] 2006.145.22:35:34.49#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.22:35:34.49#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.22:35:34.49#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.22:35:34.49#ibcon#ireg 7 cls_cnt 0 2006.145.22:35:34.49#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.22:35:34.61#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.22:35:34.61#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.22:35:34.63#ibcon#[27=USB\r\n] 2006.145.22:35:34.66#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.22:35:34.66#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.22:35:34.66#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.22:35:34.66#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.22:35:34.66$vck44/vblo=2,634.99 2006.145.22:35:34.66#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.22:35:34.66#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.22:35:34.66#ibcon#ireg 17 cls_cnt 0 2006.145.22:35:34.66#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.22:35:34.66#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.22:35:34.66#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.22:35:34.68#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.22:35:34.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.22:35:34.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.22:35:34.72#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.22:35:34.72#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.22:35:34.72$vck44/vb=2,4 2006.145.22:35:34.72#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.22:35:34.72#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.22:35:34.72#ibcon#ireg 11 cls_cnt 2 2006.145.22:35:34.72#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.22:35:34.78#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.22:35:34.78#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.22:35:34.80#ibcon#[27=AT02-04\r\n] 2006.145.22:35:34.83#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.22:35:34.83#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.22:35:34.83#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.22:35:34.83#ibcon#ireg 7 cls_cnt 0 2006.145.22:35:34.83#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.22:35:34.95#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.22:35:34.95#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.22:35:34.97#ibcon#[27=USB\r\n] 2006.145.22:35:35.00#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.22:35:35.00#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.22:35:35.00#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.22:35:35.00#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.22:35:35.00$vck44/vblo=3,649.99 2006.145.22:35:35.00#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.22:35:35.00#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.22:35:35.00#ibcon#ireg 17 cls_cnt 0 2006.145.22:35:35.00#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:35:35.00#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:35:35.00#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:35:35.02#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.22:35:35.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:35:35.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:35:35.06#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.22:35:35.06#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.22:35:35.06$vck44/vb=3,4 2006.145.22:35:35.06#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.22:35:35.06#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.22:35:35.06#ibcon#ireg 11 cls_cnt 2 2006.145.22:35:35.06#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.22:35:35.12#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.22:35:35.12#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.22:35:35.14#ibcon#[27=AT03-04\r\n] 2006.145.22:35:35.17#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.22:35:35.17#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.22:35:35.17#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.22:35:35.17#ibcon#ireg 7 cls_cnt 0 2006.145.22:35:35.17#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.22:35:35.29#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.22:35:35.29#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.22:35:35.31#ibcon#[27=USB\r\n] 2006.145.22:35:35.34#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.22:35:35.34#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.22:35:35.34#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.22:35:35.34#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.22:35:35.34$vck44/vblo=4,679.99 2006.145.22:35:35.34#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.22:35:35.34#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.22:35:35.34#ibcon#ireg 17 cls_cnt 0 2006.145.22:35:35.34#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:35:35.34#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:35:35.34#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:35:35.36#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.22:35:35.40#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:35:35.40#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:35:35.40#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.22:35:35.40#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.22:35:35.40$vck44/vb=4,4 2006.145.22:35:35.40#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.22:35:35.40#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.22:35:35.40#ibcon#ireg 11 cls_cnt 2 2006.145.22:35:35.40#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:35:35.46#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:35:35.46#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:35:35.48#ibcon#[27=AT04-04\r\n] 2006.145.22:35:35.51#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:35:35.51#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:35:35.51#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.22:35:35.51#ibcon#ireg 7 cls_cnt 0 2006.145.22:35:35.51#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:35:35.63#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:35:35.63#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:35:35.65#ibcon#[27=USB\r\n] 2006.145.22:35:35.68#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:35:35.68#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:35:35.68#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.22:35:35.68#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.22:35:35.68$vck44/vblo=5,709.99 2006.145.22:35:35.68#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.22:35:35.68#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.22:35:35.68#ibcon#ireg 17 cls_cnt 0 2006.145.22:35:35.68#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:35:35.68#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:35:35.68#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:35:35.70#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.22:35:35.74#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:35:35.74#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:35:35.74#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.22:35:35.74#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.22:35:35.74$vck44/vb=5,4 2006.145.22:35:35.74#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.22:35:35.74#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.22:35:35.74#ibcon#ireg 11 cls_cnt 2 2006.145.22:35:35.74#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:35:35.80#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:35:35.80#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:35:35.82#ibcon#[27=AT05-04\r\n] 2006.145.22:35:35.85#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:35:35.85#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:35:35.85#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.22:35:35.85#ibcon#ireg 7 cls_cnt 0 2006.145.22:35:35.85#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:35:35.97#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:35:35.97#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:35:35.99#ibcon#[27=USB\r\n] 2006.145.22:35:36.02#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:35:36.02#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:35:36.02#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.22:35:36.02#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.22:35:36.02$vck44/vblo=6,719.99 2006.145.22:35:36.02#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.22:35:36.02#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.22:35:36.02#ibcon#ireg 17 cls_cnt 0 2006.145.22:35:36.02#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:35:36.02#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:35:36.02#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:35:36.04#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.22:35:36.08#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:35:36.08#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:35:36.08#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.22:35:36.08#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.22:35:36.08$vck44/vb=6,4 2006.145.22:35:36.08#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.22:35:36.08#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.22:35:36.08#ibcon#ireg 11 cls_cnt 2 2006.145.22:35:36.08#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.22:35:36.14#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.22:35:36.14#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.22:35:36.16#ibcon#[27=AT06-04\r\n] 2006.145.22:35:36.19#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.22:35:36.19#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.22:35:36.19#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.22:35:36.19#ibcon#ireg 7 cls_cnt 0 2006.145.22:35:36.19#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.22:35:36.31#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.22:35:36.31#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.22:35:36.33#ibcon#[27=USB\r\n] 2006.145.22:35:36.36#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.22:35:36.36#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.22:35:36.36#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.22:35:36.36#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.22:35:36.36$vck44/vblo=7,734.99 2006.145.22:35:36.36#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.22:35:36.36#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.22:35:36.36#ibcon#ireg 17 cls_cnt 0 2006.145.22:35:36.36#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:35:36.36#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:35:36.36#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:35:36.38#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.22:35:36.42#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:35:36.42#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:35:36.42#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.22:35:36.42#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.22:35:36.42$vck44/vb=7,4 2006.145.22:35:36.42#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.22:35:36.42#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.22:35:36.42#ibcon#ireg 11 cls_cnt 2 2006.145.22:35:36.42#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:35:36.48#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:35:36.48#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:35:36.50#ibcon#[27=AT07-04\r\n] 2006.145.22:35:36.53#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:35:36.53#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:35:36.53#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.22:35:36.53#ibcon#ireg 7 cls_cnt 0 2006.145.22:35:36.53#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:35:36.65#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:35:36.65#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:35:36.67#ibcon#[27=USB\r\n] 2006.145.22:35:36.70#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:35:36.70#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:35:36.70#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.22:35:36.70#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.22:35:36.70$vck44/vblo=8,744.99 2006.145.22:35:36.70#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.22:35:36.70#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.22:35:36.70#ibcon#ireg 17 cls_cnt 0 2006.145.22:35:36.70#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:35:36.70#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:35:36.70#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:35:36.72#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.22:35:36.76#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:35:36.76#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:35:36.76#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.22:35:36.76#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.22:35:36.76$vck44/vb=8,4 2006.145.22:35:36.76#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.22:35:36.76#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.22:35:36.76#ibcon#ireg 11 cls_cnt 2 2006.145.22:35:36.76#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:35:36.82#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:35:36.82#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:35:36.84#ibcon#[27=AT08-04\r\n] 2006.145.22:35:36.87#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:35:36.87#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:35:36.87#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.22:35:36.87#ibcon#ireg 7 cls_cnt 0 2006.145.22:35:36.87#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:35:36.99#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:35:36.99#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:35:37.01#ibcon#[27=USB\r\n] 2006.145.22:35:37.04#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:35:37.04#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:35:37.04#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.22:35:37.04#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.22:35:37.04$vck44/vabw=wide 2006.145.22:35:37.04#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.22:35:37.04#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.22:35:37.04#ibcon#ireg 8 cls_cnt 0 2006.145.22:35:37.04#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:35:37.04#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:35:37.04#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:35:37.06#ibcon#[25=BW32\r\n] 2006.145.22:35:37.09#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:35:37.09#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:35:37.09#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.22:35:37.09#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.22:35:37.09$vck44/vbbw=wide 2006.145.22:35:37.09#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.22:35:37.09#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.22:35:37.09#ibcon#ireg 8 cls_cnt 0 2006.145.22:35:37.09#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.22:35:37.16#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.22:35:37.16#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.22:35:37.18#ibcon#[27=BW32\r\n] 2006.145.22:35:37.21#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.22:35:37.21#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.22:35:37.21#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.22:35:37.21#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.22:35:37.21$setupk4/ifdk4 2006.145.22:35:37.21$ifdk4/lo= 2006.145.22:35:37.21$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.22:35:37.21$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.22:35:37.21$ifdk4/patch= 2006.145.22:35:37.21$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.22:35:37.21$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.22:35:37.21$setupk4/!*+20s 2006.145.22:35:41.98#abcon#<5=/08 1.5 3.5 17.88 811020.5\r\n> 2006.145.22:35:42.00#abcon#{5=INTERFACE CLEAR} 2006.145.22:35:42.08#abcon#[5=S1D000X0/0*\r\n] 2006.145.22:35:42.14#trakl#Source acquired 2006.145.22:35:44.14#flagr#flagr/antenna,acquired 2006.145.22:35:51.69$setupk4/"tpicd 2006.145.22:35:51.69$setupk4/echo=off 2006.145.22:35:51.69$setupk4/xlog=off 2006.145.22:35:51.69:!2006.145.22:39:06 2006.145.22:39:06.00:preob 2006.145.22:39:06.14/onsource/TRACKING 2006.145.22:39:06.14:!2006.145.22:39:16 2006.145.22:39:16.00:"tape 2006.145.22:39:16.00:"st=record 2006.145.22:39:16.00:data_valid=on 2006.145.22:39:16.00:midob 2006.145.22:39:17.14/onsource/TRACKING 2006.145.22:39:17.14/wx/17.87,1020.5,81 2006.145.22:39:17.33/cable/+6.5482E-03 2006.145.22:39:18.42/va/01,08,usb,yes,28,30 2006.145.22:39:18.42/va/02,07,usb,yes,30,31 2006.145.22:39:18.42/va/03,08,usb,yes,27,28 2006.145.22:39:18.42/va/04,07,usb,yes,31,33 2006.145.22:39:18.42/va/05,04,usb,yes,27,27 2006.145.22:39:18.42/va/06,04,usb,yes,30,30 2006.145.22:39:18.42/va/07,04,usb,yes,31,32 2006.145.22:39:18.42/va/08,04,usb,yes,26,31 2006.145.22:39:18.65/valo/01,524.99,yes,locked 2006.145.22:39:18.65/valo/02,534.99,yes,locked 2006.145.22:39:18.65/valo/03,564.99,yes,locked 2006.145.22:39:18.65/valo/04,624.99,yes,locked 2006.145.22:39:18.65/valo/05,734.99,yes,locked 2006.145.22:39:18.65/valo/06,814.99,yes,locked 2006.145.22:39:18.65/valo/07,864.99,yes,locked 2006.145.22:39:18.65/valo/08,884.99,yes,locked 2006.145.22:39:19.74/vb/01,03,usb,yes,35,33 2006.145.22:39:19.74/vb/02,04,usb,yes,31,31 2006.145.22:39:19.74/vb/03,04,usb,yes,28,31 2006.145.22:39:19.74/vb/04,04,usb,yes,32,31 2006.145.22:39:19.74/vb/05,04,usb,yes,25,27 2006.145.22:39:19.74/vb/06,04,usb,yes,29,25 2006.145.22:39:19.74/vb/07,04,usb,yes,29,28 2006.145.22:39:19.74/vb/08,04,usb,yes,26,30 2006.145.22:39:19.97/vblo/01,629.99,yes,locked 2006.145.22:39:19.97/vblo/02,634.99,yes,locked 2006.145.22:39:19.97/vblo/03,649.99,yes,locked 2006.145.22:39:19.97/vblo/04,679.99,yes,locked 2006.145.22:39:19.97/vblo/05,709.99,yes,locked 2006.145.22:39:19.97/vblo/06,719.99,yes,locked 2006.145.22:39:19.97/vblo/07,734.99,yes,locked 2006.145.22:39:19.97/vblo/08,744.99,yes,locked 2006.145.22:39:20.12/vabw/8 2006.145.22:39:20.27/vbbw/8 2006.145.22:39:20.36/xfe/off,on,14.5 2006.145.22:39:20.74/ifatt/23,28,28,28 2006.145.22:39:21.08/fmout-gps/S +3.8E-08 2006.145.22:39:21.14:!2006.145.22:41:16 2006.145.22:41:16.02:data_valid=off 2006.145.22:41:16.02:"et 2006.145.22:41:16.02:!+3s 2006.145.22:41:19.05:"tape 2006.145.22:41:19.09:postob 2006.145.22:41:19.16/cable/+6.5505E-03 2006.145.22:41:19.17/wx/17.89,1020.5,81 2006.145.22:41:19.22/fmout-gps/S +3.7E-08 2006.145.22:41:19.23:scan_name=145-2246,jd0605,80 2006.145.22:41:19.23:source=2121+053,212344.52,053522.1,2000.0,cw 2006.145.22:41:20.15#flagr#flagr/antenna,new-source 2006.145.22:41:20.15:checkk5 2006.145.22:41:20.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.22:41:21.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.22:41:21.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.22:41:21.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.22:41:22.33/chk_obsdata//k5ts1/T1452239??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.22:41:22.78/chk_obsdata//k5ts2/T1452239??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.22:41:23.22/chk_obsdata//k5ts3/T1452239??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.22:41:23.67/chk_obsdata//k5ts4/T1452239??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.22:41:24.44/k5log//k5ts1_log_newline 2006.145.22:41:25.19/k5log//k5ts2_log_newline 2006.145.22:41:25.92/k5log//k5ts3_log_newline 2006.145.22:41:26.67/k5log//k5ts4_log_newline 2006.145.22:41:26.69/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.22:41:26.69:setupk4=1 2006.145.22:41:26.69$setupk4/echo=on 2006.145.22:41:26.69$setupk4/pcalon 2006.145.22:41:26.69$pcalon/"no phase cal control is implemented here 2006.145.22:41:26.69$setupk4/"tpicd=stop 2006.145.22:41:26.69$setupk4/"rec=synch_on 2006.145.22:41:26.69$setupk4/"rec_mode=128 2006.145.22:41:26.69$setupk4/!* 2006.145.22:41:26.69$setupk4/recpk4 2006.145.22:41:26.69$recpk4/recpatch= 2006.145.22:41:26.70$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.22:41:26.70$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.22:41:26.70$setupk4/vck44 2006.145.22:41:26.70$vck44/valo=1,524.99 2006.145.22:41:26.70#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.22:41:26.70#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.22:41:26.70#ibcon#ireg 17 cls_cnt 0 2006.145.22:41:26.70#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:41:26.70#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:41:26.70#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:41:26.73#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.22:41:26.78#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:41:26.78#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:41:26.78#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.22:41:26.78#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.22:41:26.78$vck44/va=1,8 2006.145.22:41:26.79#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.22:41:26.79#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.22:41:26.79#ibcon#ireg 11 cls_cnt 2 2006.145.22:41:26.79#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:41:26.79#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:41:26.79#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:41:26.80#ibcon#[25=AT01-08\r\n] 2006.145.22:41:26.83#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:41:26.83#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:41:26.83#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.22:41:26.83#ibcon#ireg 7 cls_cnt 0 2006.145.22:41:26.83#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:41:26.96#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:41:26.96#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:41:26.97#ibcon#[25=USB\r\n] 2006.145.22:41:27.00#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:41:27.00#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:41:27.00#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.22:41:27.00#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.22:41:27.00$vck44/valo=2,534.99 2006.145.22:41:27.01#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.22:41:27.01#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.22:41:27.01#ibcon#ireg 17 cls_cnt 0 2006.145.22:41:27.01#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:41:27.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:41:27.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:41:27.04#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.22:41:27.08#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:41:27.08#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:41:27.08#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.22:41:27.08#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.22:41:27.08$vck44/va=2,7 2006.145.22:41:27.08#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.22:41:27.09#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.22:41:27.09#ibcon#ireg 11 cls_cnt 2 2006.145.22:41:27.09#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:41:27.11#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:41:27.11#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:41:27.13#ibcon#[25=AT02-07\r\n] 2006.145.22:41:27.16#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:41:27.16#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:41:27.16#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.22:41:27.16#ibcon#ireg 7 cls_cnt 0 2006.145.22:41:27.16#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:41:27.28#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:41:27.28#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:41:27.30#ibcon#[25=USB\r\n] 2006.145.22:41:27.33#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:41:27.33#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:41:27.33#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.22:41:27.33#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.22:41:27.33$vck44/valo=3,564.99 2006.145.22:41:27.34#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.22:41:27.34#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.22:41:27.34#ibcon#ireg 17 cls_cnt 0 2006.145.22:41:27.34#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:41:27.34#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:41:27.34#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:41:27.35#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.22:41:27.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:41:27.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:41:27.39#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.22:41:27.39#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.22:41:27.39$vck44/va=3,8 2006.145.22:41:27.40#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.22:41:27.40#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.22:41:27.40#ibcon#ireg 11 cls_cnt 2 2006.145.22:41:27.40#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.22:41:27.44#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.22:41:27.44#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.22:41:27.46#ibcon#[25=AT03-08\r\n] 2006.145.22:41:27.49#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.22:41:27.49#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.22:41:27.49#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.22:41:27.49#ibcon#ireg 7 cls_cnt 0 2006.145.22:41:27.49#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.22:41:27.61#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.22:41:27.61#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.22:41:27.63#ibcon#[25=USB\r\n] 2006.145.22:41:27.66#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.22:41:27.66#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.22:41:27.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.22:41:27.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.22:41:27.66$vck44/valo=4,624.99 2006.145.22:41:27.66#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.22:41:27.67#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.22:41:27.67#ibcon#ireg 17 cls_cnt 0 2006.145.22:41:27.67#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:41:27.67#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:41:27.67#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:41:27.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.22:41:27.72#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:41:27.72#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:41:27.72#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.22:41:27.72#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.22:41:27.72$vck44/va=4,7 2006.145.22:41:27.73#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.22:41:27.73#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.22:41:27.73#ibcon#ireg 11 cls_cnt 2 2006.145.22:41:27.73#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.22:41:27.77#abcon#<5=/07 1.4 3.7 17.89 821020.5\r\n> 2006.145.22:41:27.77#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.22:41:27.77#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.22:41:27.79#ibcon#[25=AT04-07\r\n] 2006.145.22:41:27.79#abcon#{5=INTERFACE CLEAR} 2006.145.22:41:27.82#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.22:41:27.82#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.22:41:27.82#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.22:41:27.82#ibcon#ireg 7 cls_cnt 0 2006.145.22:41:27.82#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.22:41:27.85#abcon#[5=S1D000X0/0*\r\n] 2006.145.22:41:27.94#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.22:41:27.94#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.22:41:27.96#ibcon#[25=USB\r\n] 2006.145.22:41:27.99#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.22:41:27.99#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.22:41:27.99#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.22:41:27.99#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.22:41:27.99$vck44/valo=5,734.99 2006.145.22:41:27.99#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.22:41:27.99#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.22:41:27.99#ibcon#ireg 17 cls_cnt 0 2006.145.22:41:27.99#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.22:41:28.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.22:41:28.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.22:41:28.01#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.22:41:28.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.22:41:28.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.22:41:28.05#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.22:41:28.05#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.22:41:28.05$vck44/va=5,4 2006.145.22:41:28.05#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.22:41:28.05#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.22:41:28.05#ibcon#ireg 11 cls_cnt 2 2006.145.22:41:28.05#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.22:41:28.12#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.22:41:28.12#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.22:41:28.14#ibcon#[25=AT05-04\r\n] 2006.145.22:41:28.17#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.22:41:28.17#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.22:41:28.17#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.22:41:28.17#ibcon#ireg 7 cls_cnt 0 2006.145.22:41:28.17#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.22:41:28.29#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.22:41:28.29#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.22:41:28.31#ibcon#[25=USB\r\n] 2006.145.22:41:28.34#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.22:41:28.34#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.22:41:28.34#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.22:41:28.34#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.22:41:28.34$vck44/valo=6,814.99 2006.145.22:41:28.35#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.22:41:28.35#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.22:41:28.35#ibcon#ireg 17 cls_cnt 0 2006.145.22:41:28.35#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.22:41:28.35#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.22:41:28.35#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.22:41:28.36#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.22:41:28.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.22:41:28.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.22:41:28.40#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.22:41:28.40#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.22:41:28.40$vck44/va=6,4 2006.145.22:41:28.40#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.22:41:28.41#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.22:41:28.41#ibcon#ireg 11 cls_cnt 2 2006.145.22:41:28.41#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.22:41:28.45#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.22:41:28.45#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.22:41:28.47#ibcon#[25=AT06-04\r\n] 2006.145.22:41:28.50#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.22:41:28.50#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.22:41:28.50#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.22:41:28.50#ibcon#ireg 7 cls_cnt 0 2006.145.22:41:28.50#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.22:41:28.62#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.22:41:28.62#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.22:41:28.64#ibcon#[25=USB\r\n] 2006.145.22:41:28.67#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.22:41:28.67#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.22:41:28.67#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.22:41:28.67#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.22:41:28.67$vck44/valo=7,864.99 2006.145.22:41:28.68#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.22:41:28.68#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.22:41:28.68#ibcon#ireg 17 cls_cnt 0 2006.145.22:41:28.68#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:41:28.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:41:28.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:41:28.69#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.22:41:28.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:41:28.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:41:28.73#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.22:41:28.73#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.22:41:28.73$vck44/va=7,4 2006.145.22:41:28.73#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.22:41:28.73#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.22:41:28.73#ibcon#ireg 11 cls_cnt 2 2006.145.22:41:28.74#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.22:41:28.78#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.22:41:28.78#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.22:41:28.80#ibcon#[25=AT07-04\r\n] 2006.145.22:41:28.83#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.22:41:28.83#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.22:41:28.83#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.22:41:28.83#ibcon#ireg 7 cls_cnt 0 2006.145.22:41:28.83#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.22:41:28.95#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.22:41:28.95#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.22:41:28.97#ibcon#[25=USB\r\n] 2006.145.22:41:29.00#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.22:41:29.00#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.22:41:29.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.22:41:29.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.22:41:29.00$vck44/valo=8,884.99 2006.145.22:41:29.01#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.22:41:29.01#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.22:41:29.01#ibcon#ireg 17 cls_cnt 0 2006.145.22:41:29.01#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:41:29.01#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:41:29.01#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:41:29.02#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.22:41:29.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:41:29.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:41:29.06#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.22:41:29.06#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.22:41:29.06$vck44/va=8,4 2006.145.22:41:29.07#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.22:41:29.07#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.22:41:29.07#ibcon#ireg 11 cls_cnt 2 2006.145.22:41:29.07#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.22:41:29.11#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.22:41:29.11#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.22:41:29.13#ibcon#[25=AT08-04\r\n] 2006.145.22:41:29.16#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.22:41:29.16#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.22:41:29.16#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.22:41:29.16#ibcon#ireg 7 cls_cnt 0 2006.145.22:41:29.16#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.22:41:29.28#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.22:41:29.28#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.22:41:29.30#ibcon#[25=USB\r\n] 2006.145.22:41:29.33#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.22:41:29.33#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.22:41:29.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.22:41:29.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.22:41:29.33$vck44/vblo=1,629.99 2006.145.22:41:29.33#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.22:41:29.33#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.22:41:29.34#ibcon#ireg 17 cls_cnt 0 2006.145.22:41:29.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:41:29.34#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:41:29.34#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:41:29.37#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.22:41:29.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:41:29.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:41:29.41#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.22:41:29.41#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.22:41:29.41$vck44/vb=1,3 2006.145.22:41:29.42#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.22:41:29.42#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.22:41:29.42#ibcon#ireg 11 cls_cnt 2 2006.145.22:41:29.42#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:41:29.42#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:41:29.42#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:41:29.44#ibcon#[27=AT01-03\r\n] 2006.145.22:41:29.46#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:41:29.46#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:41:29.46#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.22:41:29.46#ibcon#ireg 7 cls_cnt 0 2006.145.22:41:29.46#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:41:29.58#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:41:29.58#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:41:29.60#ibcon#[27=USB\r\n] 2006.145.22:41:29.63#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:41:29.63#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:41:29.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.22:41:29.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.22:41:29.63$vck44/vblo=2,634.99 2006.145.22:41:29.64#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.22:41:29.64#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.22:41:29.64#ibcon#ireg 17 cls_cnt 0 2006.145.22:41:29.64#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:41:29.64#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:41:29.64#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:41:29.65#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.22:41:29.69#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:41:29.69#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:41:29.69#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.22:41:29.69#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.22:41:29.69$vck44/vb=2,4 2006.145.22:41:29.69#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.22:41:29.69#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.22:41:29.69#ibcon#ireg 11 cls_cnt 2 2006.145.22:41:29.70#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:41:29.74#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:41:29.74#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:41:29.76#ibcon#[27=AT02-04\r\n] 2006.145.22:41:29.79#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:41:29.79#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:41:29.79#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.22:41:29.79#ibcon#ireg 7 cls_cnt 0 2006.145.22:41:29.79#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:41:29.92#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:41:29.92#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:41:29.93#ibcon#[27=USB\r\n] 2006.145.22:41:29.96#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:41:29.96#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:41:29.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.22:41:29.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.22:41:29.96$vck44/vblo=3,649.99 2006.145.22:41:29.96#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.22:41:29.96#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.22:41:29.96#ibcon#ireg 17 cls_cnt 0 2006.145.22:41:29.97#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:41:29.97#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:41:29.97#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:41:29.98#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.22:41:30.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:41:30.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:41:30.02#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.22:41:30.02#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.22:41:30.02$vck44/vb=3,4 2006.145.22:41:30.02#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.22:41:30.02#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.22:41:30.02#ibcon#ireg 11 cls_cnt 2 2006.145.22:41:30.03#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.22:41:30.08#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.22:41:30.08#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.22:41:30.10#ibcon#[27=AT03-04\r\n] 2006.145.22:41:30.13#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.22:41:30.13#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.22:41:30.13#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.22:41:30.13#ibcon#ireg 7 cls_cnt 0 2006.145.22:41:30.13#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.22:41:30.25#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.22:41:30.25#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.22:41:30.27#ibcon#[27=USB\r\n] 2006.145.22:41:30.30#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.22:41:30.30#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.22:41:30.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.22:41:30.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.22:41:30.30$vck44/vblo=4,679.99 2006.145.22:41:30.31#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.22:41:30.31#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.22:41:30.31#ibcon#ireg 17 cls_cnt 0 2006.145.22:41:30.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:41:30.31#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:41:30.31#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:41:30.32#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.22:41:30.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:41:30.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:41:30.36#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.22:41:30.36#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.22:41:30.36$vck44/vb=4,4 2006.145.22:41:30.37#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.22:41:30.37#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.22:41:30.37#ibcon#ireg 11 cls_cnt 2 2006.145.22:41:30.37#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.22:41:30.41#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.22:41:30.41#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.22:41:30.43#ibcon#[27=AT04-04\r\n] 2006.145.22:41:30.46#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.22:41:30.46#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.22:41:30.46#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.22:41:30.46#ibcon#ireg 7 cls_cnt 0 2006.145.22:41:30.46#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.22:41:30.58#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.22:41:30.58#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.22:41:30.60#ibcon#[27=USB\r\n] 2006.145.22:41:30.63#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.22:41:30.63#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.22:41:30.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.22:41:30.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.22:41:30.63$vck44/vblo=5,709.99 2006.145.22:41:30.64#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.22:41:30.64#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.22:41:30.64#ibcon#ireg 17 cls_cnt 0 2006.145.22:41:30.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.22:41:30.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.22:41:30.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.22:41:30.65#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.22:41:30.69#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.22:41:30.69#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.22:41:30.69#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.22:41:30.69#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.22:41:30.69$vck44/vb=5,4 2006.145.22:41:30.69#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.22:41:30.69#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.22:41:30.70#ibcon#ireg 11 cls_cnt 2 2006.145.22:41:30.70#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.22:41:30.74#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.22:41:30.74#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.22:41:30.76#ibcon#[27=AT05-04\r\n] 2006.145.22:41:30.79#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.22:41:30.79#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.22:41:30.79#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.22:41:30.79#ibcon#ireg 7 cls_cnt 0 2006.145.22:41:30.79#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.22:41:30.91#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.22:41:30.91#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.22:41:30.93#ibcon#[27=USB\r\n] 2006.145.22:41:30.96#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.22:41:30.96#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.22:41:30.96#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.22:41:30.96#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.22:41:30.96$vck44/vblo=6,719.99 2006.145.22:41:30.97#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.22:41:30.97#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.22:41:30.97#ibcon#ireg 17 cls_cnt 0 2006.145.22:41:30.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.22:41:30.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.22:41:30.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.22:41:30.98#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.22:41:31.02#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.22:41:31.02#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.22:41:31.02#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.22:41:31.02#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.22:41:31.02$vck44/vb=6,4 2006.145.22:41:31.02#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.22:41:31.02#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.22:41:31.02#ibcon#ireg 11 cls_cnt 2 2006.145.22:41:31.02#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.22:41:31.08#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.22:41:31.08#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.22:41:31.10#ibcon#[27=AT06-04\r\n] 2006.145.22:41:31.13#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.22:41:31.13#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.22:41:31.13#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.22:41:31.13#ibcon#ireg 7 cls_cnt 0 2006.145.22:41:31.13#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.22:41:31.25#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.22:41:31.25#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.22:41:31.27#ibcon#[27=USB\r\n] 2006.145.22:41:31.30#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.22:41:31.30#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.22:41:31.30#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.22:41:31.30#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.22:41:31.30$vck44/vblo=7,734.99 2006.145.22:41:31.30#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.22:41:31.30#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.22:41:31.30#ibcon#ireg 17 cls_cnt 0 2006.145.22:41:31.30#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.22:41:31.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.22:41:31.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.22:41:31.32#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.22:41:31.36#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.22:41:31.36#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.22:41:31.36#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.22:41:31.36#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.22:41:31.36$vck44/vb=7,4 2006.145.22:41:31.36#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.22:41:31.36#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.22:41:31.36#ibcon#ireg 11 cls_cnt 2 2006.145.22:41:31.36#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.22:41:31.42#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.22:41:31.42#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.22:41:31.44#ibcon#[27=AT07-04\r\n] 2006.145.22:41:31.47#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.22:41:31.47#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.22:41:31.47#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.22:41:31.47#ibcon#ireg 7 cls_cnt 0 2006.145.22:41:31.47#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.22:41:31.59#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.22:41:31.59#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.22:41:31.61#ibcon#[27=USB\r\n] 2006.145.22:41:31.64#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.22:41:31.64#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.22:41:31.64#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.22:41:31.64#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.22:41:31.64$vck44/vblo=8,744.99 2006.145.22:41:31.65#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.22:41:31.65#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.22:41:31.65#ibcon#ireg 17 cls_cnt 0 2006.145.22:41:31.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:41:31.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:41:31.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:41:31.66#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.22:41:31.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:41:31.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:41:31.70#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.22:41:31.70#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.22:41:31.70$vck44/vb=8,4 2006.145.22:41:31.70#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.22:41:31.70#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.22:41:31.70#ibcon#ireg 11 cls_cnt 2 2006.145.22:41:31.71#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.22:41:31.75#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.22:41:31.75#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.22:41:31.77#ibcon#[27=AT08-04\r\n] 2006.145.22:41:31.80#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.22:41:31.80#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.22:41:31.80#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.22:41:31.80#ibcon#ireg 7 cls_cnt 0 2006.145.22:41:31.80#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.22:41:31.92#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.22:41:31.92#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.22:41:31.94#ibcon#[27=USB\r\n] 2006.145.22:41:31.97#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.22:41:31.97#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.22:41:31.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.22:41:31.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.22:41:31.97$vck44/vabw=wide 2006.145.22:41:31.97#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.22:41:31.97#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.22:41:31.98#ibcon#ireg 8 cls_cnt 0 2006.145.22:41:31.98#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:41:31.98#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:41:31.98#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:41:31.99#ibcon#[25=BW32\r\n] 2006.145.22:41:32.02#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:41:32.02#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:41:32.02#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.22:41:32.02#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.22:41:32.02$vck44/vbbw=wide 2006.145.22:41:32.02#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.22:41:32.02#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.22:41:32.02#ibcon#ireg 8 cls_cnt 0 2006.145.22:41:32.03#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.22:41:32.09#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.22:41:32.09#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.22:41:32.11#ibcon#[27=BW32\r\n] 2006.145.22:41:32.14#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.22:41:32.14#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.22:41:32.14#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.22:41:32.14#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.22:41:32.14$setupk4/ifdk4 2006.145.22:41:32.15$ifdk4/lo= 2006.145.22:41:32.15$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.22:41:32.15$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.22:41:32.15$ifdk4/patch= 2006.145.22:41:32.15$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.22:41:32.15$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.22:41:32.15$setupk4/!*+20s 2006.145.22:41:37.94#abcon#<5=/07 1.3 3.7 17.89 821020.5\r\n> 2006.145.22:41:37.96#abcon#{5=INTERFACE CLEAR} 2006.145.22:41:38.02#abcon#[5=S1D000X0/0*\r\n] 2006.145.22:41:39.14#trakl#Source acquired 2006.145.22:41:40.15#flagr#flagr/antenna,acquired 2006.145.22:41:46.71$setupk4/"tpicd 2006.145.22:41:46.71$setupk4/echo=off 2006.145.22:41:46.71$setupk4/xlog=off 2006.145.22:41:46.71:!2006.145.22:46:42 2006.145.22:46:42.00:preob 2006.145.22:46:42.13/onsource/TRACKING 2006.145.22:46:42.13:!2006.145.22:46:52 2006.145.22:46:52.00:"tape 2006.145.22:46:52.00:"st=record 2006.145.22:46:52.00:data_valid=on 2006.145.22:46:52.00:midob 2006.145.22:46:52.13/onsource/TRACKING 2006.145.22:46:52.13/wx/17.93,1020.6,81 2006.145.22:46:52.32/cable/+6.5474E-03 2006.145.22:46:53.41/va/01,08,usb,yes,28,31 2006.145.22:46:53.41/va/02,07,usb,yes,30,31 2006.145.22:46:53.41/va/03,08,usb,yes,28,29 2006.145.22:46:53.41/va/04,07,usb,yes,32,33 2006.145.22:46:53.41/va/05,04,usb,yes,27,28 2006.145.22:46:53.41/va/06,04,usb,yes,31,31 2006.145.22:46:53.41/va/07,04,usb,yes,31,32 2006.145.22:46:53.41/va/08,04,usb,yes,27,32 2006.145.22:46:53.64/valo/01,524.99,yes,locked 2006.145.22:46:53.64/valo/02,534.99,yes,locked 2006.145.22:46:53.64/valo/03,564.99,yes,locked 2006.145.22:46:53.64/valo/04,624.99,yes,locked 2006.145.22:46:53.64/valo/05,734.99,yes,locked 2006.145.22:46:53.64/valo/06,814.99,yes,locked 2006.145.22:46:53.64/valo/07,864.99,yes,locked 2006.145.22:46:53.64/valo/08,884.99,yes,locked 2006.145.22:46:54.73/vb/01,03,usb,yes,36,33 2006.145.22:46:54.73/vb/02,04,usb,yes,31,31 2006.145.22:46:54.73/vb/03,04,usb,yes,28,31 2006.145.22:46:54.73/vb/04,04,usb,yes,33,31 2006.145.22:46:54.73/vb/05,04,usb,yes,25,28 2006.145.22:46:54.73/vb/06,04,usb,yes,29,26 2006.145.22:46:54.73/vb/07,04,usb,yes,29,29 2006.145.22:46:54.73/vb/08,04,usb,yes,27,30 2006.145.22:46:54.96/vblo/01,629.99,yes,locked 2006.145.22:46:54.96/vblo/02,634.99,yes,locked 2006.145.22:46:54.96/vblo/03,649.99,yes,locked 2006.145.22:46:54.96/vblo/04,679.99,yes,locked 2006.145.22:46:54.96/vblo/05,709.99,yes,locked 2006.145.22:46:54.96/vblo/06,719.99,yes,locked 2006.145.22:46:54.96/vblo/07,734.99,yes,locked 2006.145.22:46:54.96/vblo/08,744.99,yes,locked 2006.145.22:46:55.11/vabw/8 2006.145.22:46:55.26/vbbw/8 2006.145.22:46:55.41/xfe/off,on,15.2 2006.145.22:46:55.78/ifatt/23,28,28,28 2006.145.22:46:56.07/fmout-gps/S +3.6E-08 2006.145.22:46:56.12:!2006.145.22:48:12 2006.145.22:48:12.01:data_valid=off 2006.145.22:48:12.02:"et 2006.145.22:48:12.02:!+3s 2006.145.22:48:15.04:"tape 2006.145.22:48:15.04:postob 2006.145.22:48:15.12/cable/+6.5479E-03 2006.145.22:48:15.12/wx/17.94,1020.6,80 2006.145.22:48:15.20/fmout-gps/S +3.6E-08 2006.145.22:48:15.20:scan_name=145-2249,jd0605,50 2006.145.22:48:15.20:source=3c345,164258.81,394837.0,2000.0,cw 2006.145.22:48:16.14#flagr#flagr/antenna,new-source 2006.145.22:48:16.14:checkk5 2006.145.22:48:16.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.22:48:17.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.22:48:17.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.22:48:17.88/chk_autoobs//k5ts4/ autoobs is running! 2006.145.22:48:18.32/chk_obsdata//k5ts1/T1452246??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.22:48:18.76/chk_obsdata//k5ts2/T1452246??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.22:48:19.19/chk_obsdata//k5ts3/T1452246??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.22:48:19.64/chk_obsdata//k5ts4/T1452246??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.145.22:48:20.42/k5log//k5ts1_log_newline 2006.145.22:48:21.18/k5log//k5ts2_log_newline 2006.145.22:48:21.92/k5log//k5ts3_log_newline 2006.145.22:48:22.68/k5log//k5ts4_log_newline 2006.145.22:48:22.71/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.22:48:22.71:setupk4=1 2006.145.22:48:22.71$setupk4/echo=on 2006.145.22:48:22.71$setupk4/pcalon 2006.145.22:48:22.71$pcalon/"no phase cal control is implemented here 2006.145.22:48:22.71$setupk4/"tpicd=stop 2006.145.22:48:22.71$setupk4/"rec=synch_on 2006.145.22:48:22.71$setupk4/"rec_mode=128 2006.145.22:48:22.71$setupk4/!* 2006.145.22:48:22.71$setupk4/recpk4 2006.145.22:48:22.71$recpk4/recpatch= 2006.145.22:48:22.71$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.22:48:22.71$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.22:48:22.71$setupk4/vck44 2006.145.22:48:22.71$vck44/valo=1,524.99 2006.145.22:48:22.71#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.22:48:22.71#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.22:48:22.71#ibcon#ireg 17 cls_cnt 0 2006.145.22:48:22.71#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.22:48:22.71#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.22:48:22.71#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.22:48:22.75#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.22:48:22.80#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.22:48:22.80#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.22:48:22.80#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.22:48:22.80#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.22:48:22.80$vck44/va=1,8 2006.145.22:48:22.80#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.22:48:22.80#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.22:48:22.80#ibcon#ireg 11 cls_cnt 2 2006.145.22:48:22.80#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.22:48:22.80#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.22:48:22.80#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.22:48:22.82#ibcon#[25=AT01-08\r\n] 2006.145.22:48:22.85#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.22:48:22.85#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.22:48:22.85#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.22:48:22.85#ibcon#ireg 7 cls_cnt 0 2006.145.22:48:22.85#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.22:48:22.98#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.22:48:22.98#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.22:48:22.99#ibcon#[25=USB\r\n] 2006.145.22:48:23.02#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.22:48:23.02#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.22:48:23.02#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.22:48:23.02#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.22:48:23.02$vck44/valo=2,534.99 2006.145.22:48:23.02#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.22:48:23.02#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.22:48:23.02#ibcon#ireg 17 cls_cnt 0 2006.145.22:48:23.02#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.22:48:23.02#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.22:48:23.02#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.22:48:23.05#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.22:48:23.09#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.22:48:23.09#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.22:48:23.09#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.22:48:23.09#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.22:48:23.09$vck44/va=2,7 2006.145.22:48:23.09#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.22:48:23.09#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.22:48:23.09#ibcon#ireg 11 cls_cnt 2 2006.145.22:48:23.09#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.22:48:23.15#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.22:48:23.15#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.22:48:23.18#ibcon#[25=AT02-07\r\n] 2006.145.22:48:23.20#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.22:48:23.20#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.22:48:23.20#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.22:48:23.20#ibcon#ireg 7 cls_cnt 0 2006.145.22:48:23.20#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.22:48:23.32#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.22:48:23.32#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.22:48:23.34#ibcon#[25=USB\r\n] 2006.145.22:48:23.37#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.22:48:23.37#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.22:48:23.37#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.22:48:23.37#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.22:48:23.37$vck44/valo=3,564.99 2006.145.22:48:23.37#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.22:48:23.37#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.22:48:23.37#ibcon#ireg 17 cls_cnt 0 2006.145.22:48:23.37#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.22:48:23.37#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.22:48:23.37#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.22:48:23.39#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.22:48:23.43#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.22:48:23.43#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.22:48:23.43#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.22:48:23.43#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.22:48:23.43$vck44/va=3,8 2006.145.22:48:23.43#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.22:48:23.43#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.22:48:23.43#ibcon#ireg 11 cls_cnt 2 2006.145.22:48:23.43#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.22:48:23.49#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.22:48:23.49#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.22:48:23.51#ibcon#[25=AT03-08\r\n] 2006.145.22:48:23.54#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.22:48:23.54#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.22:48:23.54#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.22:48:23.54#ibcon#ireg 7 cls_cnt 0 2006.145.22:48:23.54#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.22:48:23.66#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.22:48:23.66#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.22:48:23.68#ibcon#[25=USB\r\n] 2006.145.22:48:23.71#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.22:48:23.71#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.22:48:23.71#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.22:48:23.71#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.22:48:23.71$vck44/valo=4,624.99 2006.145.22:48:23.71#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.22:48:23.71#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.22:48:23.71#ibcon#ireg 17 cls_cnt 0 2006.145.22:48:23.71#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.22:48:23.71#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.22:48:23.71#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.22:48:23.73#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.22:48:23.77#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.22:48:23.77#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.22:48:23.77#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.22:48:23.77#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.22:48:23.77$vck44/va=4,7 2006.145.22:48:23.77#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.22:48:23.77#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.22:48:23.77#ibcon#ireg 11 cls_cnt 2 2006.145.22:48:23.77#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.22:48:23.83#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.22:48:23.83#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.22:48:23.85#ibcon#[25=AT04-07\r\n] 2006.145.22:48:23.88#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.22:48:23.88#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.22:48:23.88#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.22:48:23.88#ibcon#ireg 7 cls_cnt 0 2006.145.22:48:23.88#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.22:48:24.00#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.22:48:24.00#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.22:48:24.02#ibcon#[25=USB\r\n] 2006.145.22:48:24.05#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.22:48:24.05#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.22:48:24.05#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.22:48:24.05#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.22:48:24.05$vck44/valo=5,734.99 2006.145.22:48:24.05#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.22:48:24.05#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.22:48:24.05#ibcon#ireg 17 cls_cnt 0 2006.145.22:48:24.05#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.22:48:24.05#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.22:48:24.05#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.22:48:24.07#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.22:48:24.11#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.22:48:24.11#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.22:48:24.11#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.22:48:24.11#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.22:48:24.11$vck44/va=5,4 2006.145.22:48:24.11#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.22:48:24.11#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.22:48:24.11#ibcon#ireg 11 cls_cnt 2 2006.145.22:48:24.11#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.22:48:24.17#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.22:48:24.17#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.22:48:24.19#ibcon#[25=AT05-04\r\n] 2006.145.22:48:24.22#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.22:48:24.22#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.22:48:24.22#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.22:48:24.22#ibcon#ireg 7 cls_cnt 0 2006.145.22:48:24.22#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.22:48:24.36#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.22:48:24.36#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.22:48:24.37#ibcon#[25=USB\r\n] 2006.145.22:48:24.40#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.22:48:24.40#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.22:48:24.40#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.22:48:24.40#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.22:48:24.40$vck44/valo=6,814.99 2006.145.22:48:24.40#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.22:48:24.40#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.22:48:24.40#ibcon#ireg 17 cls_cnt 0 2006.145.22:48:24.40#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.22:48:24.40#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.22:48:24.40#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.22:48:24.43#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.22:48:24.47#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.22:48:24.47#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.22:48:24.47#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.22:48:24.47#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.22:48:24.47$vck44/va=6,4 2006.145.22:48:24.47#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.22:48:24.47#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.22:48:24.47#ibcon#ireg 11 cls_cnt 2 2006.145.22:48:24.47#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.22:48:24.52#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.22:48:24.52#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.22:48:24.54#ibcon#[25=AT06-04\r\n] 2006.145.22:48:24.57#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.22:48:24.57#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.22:48:24.57#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.22:48:24.57#ibcon#ireg 7 cls_cnt 0 2006.145.22:48:24.57#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.22:48:24.69#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.22:48:24.69#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.22:48:24.71#ibcon#[25=USB\r\n] 2006.145.22:48:24.74#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.22:48:24.74#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.22:48:24.74#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.22:48:24.74#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.22:48:24.74$vck44/valo=7,864.99 2006.145.22:48:24.74#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.22:48:24.74#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.22:48:24.74#ibcon#ireg 17 cls_cnt 0 2006.145.22:48:24.74#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.22:48:24.74#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.22:48:24.74#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.22:48:24.76#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.22:48:24.80#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.22:48:24.80#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.22:48:24.80#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.22:48:24.80#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.22:48:24.80$vck44/va=7,4 2006.145.22:48:24.80#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.22:48:24.80#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.22:48:24.80#ibcon#ireg 11 cls_cnt 2 2006.145.22:48:24.80#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.22:48:24.86#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.22:48:24.86#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.22:48:24.88#ibcon#[25=AT07-04\r\n] 2006.145.22:48:24.91#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.22:48:24.91#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.22:48:24.91#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.22:48:24.91#ibcon#ireg 7 cls_cnt 0 2006.145.22:48:24.91#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.22:48:25.03#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.22:48:25.03#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.22:48:25.05#ibcon#[25=USB\r\n] 2006.145.22:48:25.08#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.22:48:25.08#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.22:48:25.08#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.22:48:25.08#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.22:48:25.08$vck44/valo=8,884.99 2006.145.22:48:25.08#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.22:48:25.08#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.22:48:25.08#ibcon#ireg 17 cls_cnt 0 2006.145.22:48:25.08#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.22:48:25.08#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.22:48:25.08#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.22:48:25.10#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.22:48:25.14#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.22:48:25.14#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.22:48:25.14#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.22:48:25.14#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.22:48:25.14$vck44/va=8,4 2006.145.22:48:25.14#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.22:48:25.14#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.22:48:25.14#ibcon#ireg 11 cls_cnt 2 2006.145.22:48:25.14#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:48:25.20#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:48:25.20#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:48:25.22#ibcon#[25=AT08-04\r\n] 2006.145.22:48:25.25#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:48:25.25#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:48:25.25#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.22:48:25.25#ibcon#ireg 7 cls_cnt 0 2006.145.22:48:25.25#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:48:25.37#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:48:25.37#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:48:25.39#ibcon#[25=USB\r\n] 2006.145.22:48:25.42#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:48:25.42#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:48:25.42#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.22:48:25.42#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.22:48:25.42$vck44/vblo=1,629.99 2006.145.22:48:25.42#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.22:48:25.42#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.22:48:25.42#ibcon#ireg 17 cls_cnt 0 2006.145.22:48:25.42#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.22:48:25.42#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.22:48:25.42#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.22:48:25.44#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.22:48:25.48#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.22:48:25.48#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.22:48:25.48#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.22:48:25.48#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.22:48:25.48$vck44/vb=1,3 2006.145.22:48:25.48#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.22:48:25.48#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.22:48:25.48#ibcon#ireg 11 cls_cnt 2 2006.145.22:48:25.48#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.22:48:25.48#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.22:48:25.48#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.22:48:25.50#ibcon#[27=AT01-03\r\n] 2006.145.22:48:25.53#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.22:48:25.53#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.22:48:25.53#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.22:48:25.53#ibcon#ireg 7 cls_cnt 0 2006.145.22:48:25.53#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.22:48:25.65#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.22:48:25.65#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.22:48:25.67#ibcon#[27=USB\r\n] 2006.145.22:48:25.70#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.22:48:25.70#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.22:48:25.70#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.22:48:25.70#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.22:48:25.70$vck44/vblo=2,634.99 2006.145.22:48:25.70#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.22:48:25.70#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.22:48:25.70#ibcon#ireg 17 cls_cnt 0 2006.145.22:48:25.70#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.22:48:25.70#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.22:48:25.70#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.22:48:25.72#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.22:48:25.76#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.22:48:25.76#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.22:48:25.76#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.22:48:25.76#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.22:48:25.76$vck44/vb=2,4 2006.145.22:48:25.76#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.22:48:25.76#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.22:48:25.76#ibcon#ireg 11 cls_cnt 2 2006.145.22:48:25.76#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.22:48:25.82#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.22:48:25.82#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.22:48:25.84#ibcon#[27=AT02-04\r\n] 2006.145.22:48:25.87#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.22:48:25.87#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.22:48:25.87#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.22:48:25.87#ibcon#ireg 7 cls_cnt 0 2006.145.22:48:25.87#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.22:48:25.99#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.22:48:25.99#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.22:48:26.01#ibcon#[27=USB\r\n] 2006.145.22:48:26.04#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.22:48:26.04#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.22:48:26.04#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.22:48:26.04#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.22:48:26.04$vck44/vblo=3,649.99 2006.145.22:48:26.04#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.22:48:26.04#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.22:48:26.04#ibcon#ireg 17 cls_cnt 0 2006.145.22:48:26.04#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.22:48:26.04#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.22:48:26.04#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.22:48:26.06#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.22:48:26.10#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.22:48:26.10#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.22:48:26.10#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.22:48:26.10#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.22:48:26.10$vck44/vb=3,4 2006.145.22:48:26.10#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.22:48:26.10#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.22:48:26.10#ibcon#ireg 11 cls_cnt 2 2006.145.22:48:26.10#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.22:48:26.16#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.22:48:26.16#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.22:48:26.18#ibcon#[27=AT03-04\r\n] 2006.145.22:48:26.21#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.22:48:26.21#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.22:48:26.21#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.22:48:26.21#ibcon#ireg 7 cls_cnt 0 2006.145.22:48:26.21#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.22:48:26.33#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.22:48:26.33#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.22:48:26.35#ibcon#[27=USB\r\n] 2006.145.22:48:26.38#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.22:48:26.38#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.22:48:26.38#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.22:48:26.38#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.22:48:26.38$vck44/vblo=4,679.99 2006.145.22:48:26.38#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.22:48:26.38#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.22:48:26.38#ibcon#ireg 17 cls_cnt 0 2006.145.22:48:26.38#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.22:48:26.38#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.22:48:26.38#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.22:48:26.40#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.22:48:26.44#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.22:48:26.44#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.22:48:26.44#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.22:48:26.44#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.22:48:26.44$vck44/vb=4,4 2006.145.22:48:26.44#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.22:48:26.44#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.22:48:26.44#ibcon#ireg 11 cls_cnt 2 2006.145.22:48:26.44#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.22:48:26.50#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.22:48:26.50#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.22:48:26.52#ibcon#[27=AT04-04\r\n] 2006.145.22:48:26.55#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.22:48:26.55#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.22:48:26.55#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.22:48:26.55#ibcon#ireg 7 cls_cnt 0 2006.145.22:48:26.55#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.22:48:26.67#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.22:48:26.67#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.22:48:26.69#ibcon#[27=USB\r\n] 2006.145.22:48:26.72#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.22:48:26.72#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.22:48:26.72#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.22:48:26.72#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.22:48:26.72$vck44/vblo=5,709.99 2006.145.22:48:26.72#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.22:48:26.72#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.22:48:26.72#ibcon#ireg 17 cls_cnt 0 2006.145.22:48:26.72#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.22:48:26.72#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.22:48:26.72#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.22:48:26.74#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.22:48:26.78#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.22:48:26.78#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.22:48:26.78#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.22:48:26.78#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.22:48:26.78$vck44/vb=5,4 2006.145.22:48:26.78#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.22:48:26.78#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.22:48:26.78#ibcon#ireg 11 cls_cnt 2 2006.145.22:48:26.78#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.22:48:26.84#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.22:48:26.84#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.22:48:26.86#ibcon#[27=AT05-04\r\n] 2006.145.22:48:26.89#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.22:48:26.89#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.22:48:26.89#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.22:48:26.89#ibcon#ireg 7 cls_cnt 0 2006.145.22:48:26.89#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.22:48:27.01#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.22:48:27.01#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.22:48:27.03#ibcon#[27=USB\r\n] 2006.145.22:48:27.06#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.22:48:27.06#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.22:48:27.06#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.22:48:27.06#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.22:48:27.06$vck44/vblo=6,719.99 2006.145.22:48:27.06#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.22:48:27.06#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.22:48:27.06#ibcon#ireg 17 cls_cnt 0 2006.145.22:48:27.06#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.22:48:27.06#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.22:48:27.06#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.22:48:27.08#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.22:48:27.12#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.22:48:27.12#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.22:48:27.12#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.22:48:27.12#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.22:48:27.12$vck44/vb=6,4 2006.145.22:48:27.12#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.22:48:27.12#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.22:48:27.12#ibcon#ireg 11 cls_cnt 2 2006.145.22:48:27.12#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.22:48:27.18#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.22:48:27.18#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.22:48:27.20#ibcon#[27=AT06-04\r\n] 2006.145.22:48:27.23#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.22:48:27.23#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.22:48:27.23#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.22:48:27.23#ibcon#ireg 7 cls_cnt 0 2006.145.22:48:27.23#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.22:48:27.35#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.22:48:27.35#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.22:48:27.37#ibcon#[27=USB\r\n] 2006.145.22:48:27.40#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.22:48:27.40#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.22:48:27.40#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.22:48:27.40#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.22:48:27.40$vck44/vblo=7,734.99 2006.145.22:48:27.40#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.22:48:27.40#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.22:48:27.40#ibcon#ireg 17 cls_cnt 0 2006.145.22:48:27.40#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.22:48:27.40#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.22:48:27.40#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.22:48:27.42#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.22:48:27.46#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.22:48:27.46#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.22:48:27.46#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.22:48:27.46#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.22:48:27.46$vck44/vb=7,4 2006.145.22:48:27.46#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.22:48:27.46#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.22:48:27.46#ibcon#ireg 11 cls_cnt 2 2006.145.22:48:27.46#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.22:48:27.52#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.22:48:27.52#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.22:48:27.54#ibcon#[27=AT07-04\r\n] 2006.145.22:48:27.57#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.22:48:27.57#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.22:48:27.57#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.22:48:27.57#ibcon#ireg 7 cls_cnt 0 2006.145.22:48:27.57#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.22:48:27.69#abcon#<5=/07 1.3 3.3 17.94 811020.6\r\n> 2006.145.22:48:27.69#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.22:48:27.69#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.22:48:27.71#ibcon#[27=USB\r\n] 2006.145.22:48:27.71#abcon#{5=INTERFACE CLEAR} 2006.145.22:48:27.74#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.22:48:27.74#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.22:48:27.74#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.22:48:27.74#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.22:48:27.74$vck44/vblo=8,744.99 2006.145.22:48:27.74#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.22:48:27.74#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.22:48:27.74#ibcon#ireg 17 cls_cnt 0 2006.145.22:48:27.74#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:48:27.74#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:48:27.74#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:48:27.76#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.22:48:27.77#abcon#[5=S1D000X0/0*\r\n] 2006.145.22:48:27.80#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:48:27.80#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:48:27.80#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.22:48:27.80#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.22:48:27.80$vck44/vb=8,4 2006.145.22:48:27.80#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.22:48:27.80#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.22:48:27.80#ibcon#ireg 11 cls_cnt 2 2006.145.22:48:27.80#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:48:27.86#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:48:27.86#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:48:27.88#ibcon#[27=AT08-04\r\n] 2006.145.22:48:27.91#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:48:27.91#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:48:27.91#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.22:48:27.91#ibcon#ireg 7 cls_cnt 0 2006.145.22:48:27.91#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:48:28.03#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:48:28.03#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:48:28.05#ibcon#[27=USB\r\n] 2006.145.22:48:28.08#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:48:28.08#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:48:28.08#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.22:48:28.08#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.22:48:28.08$vck44/vabw=wide 2006.145.22:48:28.08#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.22:48:28.08#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.22:48:28.08#ibcon#ireg 8 cls_cnt 0 2006.145.22:48:28.08#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.22:48:28.08#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.22:48:28.08#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.22:48:28.10#ibcon#[25=BW32\r\n] 2006.145.22:48:28.13#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.22:48:28.13#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.22:48:28.13#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.22:48:28.13#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.22:48:28.13$vck44/vbbw=wide 2006.145.22:48:28.13#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.22:48:28.13#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.22:48:28.13#ibcon#ireg 8 cls_cnt 0 2006.145.22:48:28.13#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:48:28.20#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:48:28.20#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:48:28.22#ibcon#[27=BW32\r\n] 2006.145.22:48:28.25#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:48:28.25#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:48:28.25#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.22:48:28.25#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.22:48:28.25$setupk4/ifdk4 2006.145.22:48:28.25$ifdk4/lo= 2006.145.22:48:28.25$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.22:48:28.25$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.22:48:28.25$ifdk4/patch= 2006.145.22:48:28.25$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.22:48:28.25$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.22:48:28.25$setupk4/!*+20s 2006.145.22:48:37.86#abcon#<5=/07 1.3 3.3 17.95 811020.6\r\n> 2006.145.22:48:37.88#abcon#{5=INTERFACE CLEAR} 2006.145.22:48:37.94#abcon#[5=S1D000X0/0*\r\n] 2006.145.22:48:42.72$setupk4/"tpicd 2006.145.22:48:42.72$setupk4/echo=off 2006.145.22:48:42.72$setupk4/xlog=off 2006.145.22:48:42.72:!2006.145.22:49:28 2006.145.22:48:48.14#trakl#Source acquired 2006.145.22:48:50.14#flagr#flagr/antenna,acquired 2006.145.22:49:28.00:preob 2006.145.22:49:28.14/onsource/TRACKING 2006.145.22:49:28.14:!2006.145.22:49:38 2006.145.22:49:38.00:"tape 2006.145.22:49:38.00:"st=record 2006.145.22:49:38.00:data_valid=on 2006.145.22:49:38.00:midob 2006.145.22:49:38.14/onsource/TRACKING 2006.145.22:49:38.14/wx/17.96,1020.6,81 2006.145.22:49:38.33/cable/+6.5489E-03 2006.145.22:49:39.42/va/01,08,usb,yes,48,51 2006.145.22:49:39.42/va/02,07,usb,yes,51,52 2006.145.22:49:39.42/va/03,08,usb,yes,47,49 2006.145.22:49:39.42/va/04,07,usb,yes,53,56 2006.145.22:49:39.42/va/05,04,usb,yes,47,48 2006.145.22:49:39.42/va/06,04,usb,yes,52,52 2006.145.22:49:39.42/va/07,04,usb,yes,52,54 2006.145.22:49:39.42/va/08,04,usb,yes,45,53 2006.145.22:49:39.65/valo/01,524.99,yes,locked 2006.145.22:49:39.65/valo/02,534.99,yes,locked 2006.145.22:49:39.65/valo/03,564.99,yes,locked 2006.145.22:49:39.65/valo/04,624.99,yes,locked 2006.145.22:49:39.65/valo/05,734.99,yes,locked 2006.145.22:49:39.65/valo/06,814.99,yes,locked 2006.145.22:49:39.65/valo/07,864.99,yes,locked 2006.145.22:49:39.65/valo/08,884.99,yes,locked 2006.145.22:49:40.74/vb/01,03,usb,yes,52,54 2006.145.22:49:40.74/vb/02,04,usb,yes,46,49 2006.145.22:49:40.74/vb/03,04,usb,yes,42,46 2006.145.22:49:40.74/vb/04,04,usb,yes,47,46 2006.145.22:49:40.74/vb/05,04,usb,yes,38,41 2006.145.22:49:40.74/vb/06,04,usb,yes,44,39 2006.145.22:49:40.74/vb/07,04,usb,yes,43,43 2006.145.22:49:40.74/vb/08,04,usb,yes,39,44 2006.145.22:49:40.97/vblo/01,629.99,yes,locked 2006.145.22:49:40.97/vblo/02,634.99,yes,locked 2006.145.22:49:40.97/vblo/03,649.99,yes,locked 2006.145.22:49:40.97/vblo/04,679.99,yes,locked 2006.145.22:49:40.97/vblo/05,709.99,yes,locked 2006.145.22:49:40.97/vblo/06,719.99,yes,locked 2006.145.22:49:40.97/vblo/07,734.99,yes,locked 2006.145.22:49:40.97/vblo/08,744.99,yes,locked 2006.145.22:49:41.12/vabw/8 2006.145.22:49:41.27/vbbw/8 2006.145.22:49:41.38/xfe/off,on,15.2 2006.145.22:49:41.75/ifatt/23,28,28,28 2006.145.22:49:42.07/fmout-gps/S +3.4E-08 2006.145.22:49:42.11:!2006.145.22:50:28 2006.145.22:50:28.01:data_valid=off 2006.145.22:50:28.02:"et 2006.145.22:50:28.02:!+3s 2006.145.22:50:31.03:"tape 2006.145.22:50:31.04:postob 2006.145.22:50:31.21/cable/+6.5495E-03 2006.145.22:50:31.22/wx/17.97,1020.6,82 2006.145.22:50:31.29/fmout-gps/S +3.4E-08 2006.145.22:50:31.29:scan_name=145-2254,jd0605,100 2006.145.22:50:31.29:source=0528+134,053056.42,133155.1,2000.0,cw 2006.145.22:50:32.14#flagr#flagr/antenna,new-source 2006.145.22:50:32.14:checkk5 2006.145.22:50:32.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.22:50:33.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.22:50:33.48/chk_autoobs//k5ts3/ autoobs is running! 2006.145.22:50:33.92/chk_autoobs//k5ts4/ autoobs is running! 2006.145.22:50:34.36/chk_obsdata//k5ts1/T1452249??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.145.22:50:34.80/chk_obsdata//k5ts2/T1452249??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.145.22:50:35.27/chk_obsdata//k5ts3/T1452249??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.145.22:50:35.71/chk_obsdata//k5ts4/T1452249??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.145.22:50:36.49/k5log//k5ts1_log_newline 2006.145.22:50:37.25/k5log//k5ts2_log_newline 2006.145.22:50:38.01/k5log//k5ts3_log_newline 2006.145.22:50:38.76/k5log//k5ts4_log_newline 2006.145.22:50:38.79/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.22:50:38.79:setupk4=1 2006.145.22:50:38.79$setupk4/echo=on 2006.145.22:50:38.79$setupk4/pcalon 2006.145.22:50:38.79$pcalon/"no phase cal control is implemented here 2006.145.22:50:38.79$setupk4/"tpicd=stop 2006.145.22:50:38.79$setupk4/"rec=synch_on 2006.145.22:50:38.79$setupk4/"rec_mode=128 2006.145.22:50:38.79$setupk4/!* 2006.145.22:50:38.79$setupk4/recpk4 2006.145.22:50:38.79$recpk4/recpatch= 2006.145.22:50:38.79$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.22:50:38.79$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.22:50:38.79$setupk4/vck44 2006.145.22:50:38.79$vck44/valo=1,524.99 2006.145.22:50:38.79#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.22:50:38.79#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.22:50:38.79#ibcon#ireg 17 cls_cnt 0 2006.145.22:50:38.79#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:50:38.79#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:50:38.79#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:50:38.83#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.22:50:38.88#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:50:38.88#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:50:38.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.22:50:38.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.22:50:38.88$vck44/va=1,8 2006.145.22:50:38.88#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.22:50:38.88#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.22:50:38.88#ibcon#ireg 11 cls_cnt 2 2006.145.22:50:38.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:50:38.88#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:50:38.88#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:50:38.90#ibcon#[25=AT01-08\r\n] 2006.145.22:50:38.93#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:50:38.93#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:50:38.93#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.22:50:38.93#ibcon#ireg 7 cls_cnt 0 2006.145.22:50:38.93#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:50:39.05#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:50:39.05#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:50:39.07#ibcon#[25=USB\r\n] 2006.145.22:50:39.12#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:50:39.12#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:50:39.12#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.22:50:39.12#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.22:50:39.12$vck44/valo=2,534.99 2006.145.22:50:39.12#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.22:50:39.12#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.22:50:39.12#ibcon#ireg 17 cls_cnt 0 2006.145.22:50:39.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:50:39.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:50:39.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:50:39.14#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.22:50:39.18#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:50:39.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:50:39.18#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.22:50:39.18#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.22:50:39.18$vck44/va=2,7 2006.145.22:50:39.18#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.22:50:39.18#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.22:50:39.18#ibcon#ireg 11 cls_cnt 2 2006.145.22:50:39.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:50:39.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:50:39.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:50:39.26#ibcon#[25=AT02-07\r\n] 2006.145.22:50:39.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:50:39.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:50:39.29#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.22:50:39.29#ibcon#ireg 7 cls_cnt 0 2006.145.22:50:39.29#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:50:39.41#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:50:39.41#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:50:39.43#ibcon#[25=USB\r\n] 2006.145.22:50:39.46#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:50:39.46#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:50:39.46#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.22:50:39.46#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.22:50:39.46$vck44/valo=3,564.99 2006.145.22:50:39.46#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.22:50:39.46#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.22:50:39.46#ibcon#ireg 17 cls_cnt 0 2006.145.22:50:39.46#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:50:39.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:50:39.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:50:39.48#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.22:50:39.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:50:39.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:50:39.52#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.22:50:39.52#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.22:50:39.52$vck44/va=3,8 2006.145.22:50:39.52#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.22:50:39.52#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.22:50:39.52#ibcon#ireg 11 cls_cnt 2 2006.145.22:50:39.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.22:50:39.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.22:50:39.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.22:50:39.60#ibcon#[25=AT03-08\r\n] 2006.145.22:50:39.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.22:50:39.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.22:50:39.63#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.22:50:39.63#ibcon#ireg 7 cls_cnt 0 2006.145.22:50:39.63#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.22:50:39.75#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.22:50:39.75#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.22:50:39.77#ibcon#[25=USB\r\n] 2006.145.22:50:39.80#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.22:50:39.80#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.22:50:39.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.22:50:39.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.22:50:39.80$vck44/valo=4,624.99 2006.145.22:50:39.80#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.22:50:39.80#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.22:50:39.80#ibcon#ireg 17 cls_cnt 0 2006.145.22:50:39.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:50:39.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:50:39.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:50:39.82#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.22:50:39.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:50:39.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:50:39.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.22:50:39.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.22:50:39.86$vck44/va=4,7 2006.145.22:50:39.86#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.22:50:39.86#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.22:50:39.86#ibcon#ireg 11 cls_cnt 2 2006.145.22:50:39.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:50:39.90#abcon#<5=/07 1.3 3.3 17.98 821020.6\r\n> 2006.145.22:50:39.92#abcon#{5=INTERFACE CLEAR} 2006.145.22:50:39.92#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:50:39.92#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:50:39.94#ibcon#[25=AT04-07\r\n] 2006.145.22:50:39.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:50:39.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.22:50:39.97#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.22:50:39.97#ibcon#ireg 7 cls_cnt 0 2006.145.22:50:39.97#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:50:39.98#abcon#[5=S1D000X0/0*\r\n] 2006.145.22:50:40.09#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:50:40.09#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:50:40.11#ibcon#[25=USB\r\n] 2006.145.22:50:40.14#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:50:40.14#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.22:50:40.14#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.22:50:40.14#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.22:50:40.14$vck44/valo=5,734.99 2006.145.22:50:40.14#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.22:50:40.14#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.22:50:40.14#ibcon#ireg 17 cls_cnt 0 2006.145.22:50:40.14#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:50:40.14#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:50:40.14#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:50:40.16#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.22:50:40.20#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:50:40.20#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:50:40.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.22:50:40.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.22:50:40.20$vck44/va=5,4 2006.145.22:50:40.20#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.22:50:40.20#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.22:50:40.20#ibcon#ireg 11 cls_cnt 2 2006.145.22:50:40.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.22:50:40.28#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.22:50:40.28#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.22:50:40.29#ibcon#[25=AT05-04\r\n] 2006.145.22:50:40.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.22:50:40.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.22:50:40.32#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.22:50:40.32#ibcon#ireg 7 cls_cnt 0 2006.145.22:50:40.32#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.22:50:40.44#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.22:50:40.44#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.22:50:40.46#ibcon#[25=USB\r\n] 2006.145.22:50:40.51#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.22:50:40.51#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.22:50:40.51#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.22:50:40.51#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.22:50:40.51$vck44/valo=6,814.99 2006.145.22:50:40.51#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.22:50:40.51#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.22:50:40.51#ibcon#ireg 17 cls_cnt 0 2006.145.22:50:40.51#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:50:40.51#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:50:40.51#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:50:40.52#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.22:50:40.56#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:50:40.56#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:50:40.56#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.22:50:40.56#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.22:50:40.56$vck44/va=6,4 2006.145.22:50:40.56#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.22:50:40.56#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.22:50:40.56#ibcon#ireg 11 cls_cnt 2 2006.145.22:50:40.56#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:50:40.63#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:50:40.63#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:50:40.65#ibcon#[25=AT06-04\r\n] 2006.145.22:50:40.68#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:50:40.68#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:50:40.68#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.22:50:40.68#ibcon#ireg 7 cls_cnt 0 2006.145.22:50:40.68#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:50:40.80#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:50:40.80#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:50:40.82#ibcon#[25=USB\r\n] 2006.145.22:50:40.85#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:50:40.85#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:50:40.85#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.22:50:40.85#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.22:50:40.85$vck44/valo=7,864.99 2006.145.22:50:40.85#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.22:50:40.85#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.22:50:40.85#ibcon#ireg 17 cls_cnt 0 2006.145.22:50:40.85#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:50:40.85#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:50:40.85#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:50:40.87#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.22:50:40.91#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:50:40.91#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:50:40.91#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.22:50:40.91#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.22:50:40.91$vck44/va=7,4 2006.145.22:50:40.91#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.22:50:40.91#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.22:50:40.91#ibcon#ireg 11 cls_cnt 2 2006.145.22:50:40.91#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:50:40.97#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:50:40.97#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:50:40.99#ibcon#[25=AT07-04\r\n] 2006.145.22:50:41.02#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:50:41.02#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:50:41.02#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.22:50:41.02#ibcon#ireg 7 cls_cnt 0 2006.145.22:50:41.02#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:50:41.14#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:50:41.14#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:50:41.16#ibcon#[25=USB\r\n] 2006.145.22:50:41.19#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:50:41.19#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:50:41.19#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.22:50:41.19#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.22:50:41.19$vck44/valo=8,884.99 2006.145.22:50:41.19#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.22:50:41.19#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.22:50:41.19#ibcon#ireg 17 cls_cnt 0 2006.145.22:50:41.19#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:50:41.19#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:50:41.19#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:50:41.21#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.22:50:41.25#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:50:41.25#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:50:41.25#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.22:50:41.25#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.22:50:41.25$vck44/va=8,4 2006.145.22:50:41.25#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.22:50:41.25#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.22:50:41.25#ibcon#ireg 11 cls_cnt 2 2006.145.22:50:41.25#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.22:50:41.31#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.22:50:41.31#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.22:50:41.33#ibcon#[25=AT08-04\r\n] 2006.145.22:50:41.36#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.22:50:41.36#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.22:50:41.36#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.22:50:41.36#ibcon#ireg 7 cls_cnt 0 2006.145.22:50:41.36#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.22:50:41.48#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.22:50:41.48#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.22:50:41.50#ibcon#[25=USB\r\n] 2006.145.22:50:41.53#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.22:50:41.53#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.22:50:41.53#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.22:50:41.53#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.22:50:41.53$vck44/vblo=1,629.99 2006.145.22:50:41.53#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.22:50:41.53#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.22:50:41.53#ibcon#ireg 17 cls_cnt 0 2006.145.22:50:41.53#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:50:41.53#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:50:41.53#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:50:41.55#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.22:50:41.59#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:50:41.59#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.22:50:41.59#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.22:50:41.59#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.22:50:41.59$vck44/vb=1,3 2006.145.22:50:41.59#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.22:50:41.59#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.22:50:41.59#ibcon#ireg 11 cls_cnt 2 2006.145.22:50:41.59#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:50:41.59#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:50:41.59#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:50:41.61#ibcon#[27=AT01-03\r\n] 2006.145.22:50:41.64#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:50:41.64#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.22:50:41.64#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.22:50:41.64#ibcon#ireg 7 cls_cnt 0 2006.145.22:50:41.64#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:50:41.76#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:50:41.76#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:50:41.78#ibcon#[27=USB\r\n] 2006.145.22:50:41.81#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:50:41.81#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.22:50:41.81#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.22:50:41.81#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.22:50:41.81$vck44/vblo=2,634.99 2006.145.22:50:41.81#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.22:50:41.81#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.22:50:41.81#ibcon#ireg 17 cls_cnt 0 2006.145.22:50:41.81#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:50:41.81#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:50:41.81#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:50:41.83#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.22:50:41.87#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:50:41.87#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.22:50:41.87#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.22:50:41.87#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.22:50:41.87$vck44/vb=2,4 2006.145.22:50:41.87#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.22:50:41.87#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.22:50:41.87#ibcon#ireg 11 cls_cnt 2 2006.145.22:50:41.87#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:50:41.93#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:50:41.93#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:50:41.95#ibcon#[27=AT02-04\r\n] 2006.145.22:50:41.98#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:50:41.98#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.22:50:41.98#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.22:50:41.98#ibcon#ireg 7 cls_cnt 0 2006.145.22:50:41.98#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:50:42.10#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:50:42.10#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:50:42.12#ibcon#[27=USB\r\n] 2006.145.22:50:42.15#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:50:42.15#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.22:50:42.15#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.22:50:42.15#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.22:50:42.15$vck44/vblo=3,649.99 2006.145.22:50:42.15#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.22:50:42.15#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.22:50:42.15#ibcon#ireg 17 cls_cnt 0 2006.145.22:50:42.15#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:50:42.15#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:50:42.15#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:50:42.17#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.22:50:42.21#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:50:42.21#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.22:50:42.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.22:50:42.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.22:50:42.21$vck44/vb=3,4 2006.145.22:50:42.21#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.22:50:42.21#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.22:50:42.21#ibcon#ireg 11 cls_cnt 2 2006.145.22:50:42.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.22:50:42.27#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.22:50:42.27#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.22:50:42.29#ibcon#[27=AT03-04\r\n] 2006.145.22:50:42.32#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.22:50:42.32#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.22:50:42.32#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.22:50:42.32#ibcon#ireg 7 cls_cnt 0 2006.145.22:50:42.32#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.22:50:42.44#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.22:50:42.44#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.22:50:42.46#ibcon#[27=USB\r\n] 2006.145.22:50:42.49#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.22:50:42.49#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.22:50:42.49#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.22:50:42.49#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.22:50:42.49$vck44/vblo=4,679.99 2006.145.22:50:42.49#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.22:50:42.49#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.22:50:42.49#ibcon#ireg 17 cls_cnt 0 2006.145.22:50:42.49#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:50:42.49#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:50:42.49#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:50:42.51#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.22:50:42.55#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:50:42.55#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.22:50:42.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.22:50:42.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.22:50:42.55$vck44/vb=4,4 2006.145.22:50:42.55#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.22:50:42.55#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.22:50:42.55#ibcon#ireg 11 cls_cnt 2 2006.145.22:50:42.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.22:50:42.61#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.22:50:42.61#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.22:50:42.63#ibcon#[27=AT04-04\r\n] 2006.145.22:50:42.66#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.22:50:42.66#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.22:50:42.66#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.22:50:42.66#ibcon#ireg 7 cls_cnt 0 2006.145.22:50:42.66#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.22:50:42.78#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.22:50:42.78#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.22:50:42.80#ibcon#[27=USB\r\n] 2006.145.22:50:42.83#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.22:50:42.83#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.22:50:42.83#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.22:50:42.83#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.22:50:42.83$vck44/vblo=5,709.99 2006.145.22:50:42.83#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.22:50:42.83#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.22:50:42.83#ibcon#ireg 17 cls_cnt 0 2006.145.22:50:42.83#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.22:50:42.83#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.22:50:42.83#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.22:50:42.85#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.22:50:42.89#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.22:50:42.89#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.22:50:42.89#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.22:50:42.89#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.22:50:42.89$vck44/vb=5,4 2006.145.22:50:42.89#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.22:50:42.89#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.22:50:42.89#ibcon#ireg 11 cls_cnt 2 2006.145.22:50:42.89#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.22:50:42.95#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.22:50:42.95#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.22:50:42.97#ibcon#[27=AT05-04\r\n] 2006.145.22:50:43.00#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.22:50:43.00#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.22:50:43.00#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.22:50:43.00#ibcon#ireg 7 cls_cnt 0 2006.145.22:50:43.00#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.22:50:43.12#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.22:50:43.12#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.22:50:43.14#ibcon#[27=USB\r\n] 2006.145.22:50:43.17#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.22:50:43.17#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.22:50:43.17#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.22:50:43.17#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.22:50:43.17$vck44/vblo=6,719.99 2006.145.22:50:43.17#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.22:50:43.17#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.22:50:43.17#ibcon#ireg 17 cls_cnt 0 2006.145.22:50:43.17#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:50:43.17#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:50:43.17#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:50:43.19#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.22:50:43.23#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:50:43.23#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.22:50:43.23#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.22:50:43.23#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.22:50:43.23$vck44/vb=6,4 2006.145.22:50:43.23#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.22:50:43.23#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.22:50:43.23#ibcon#ireg 11 cls_cnt 2 2006.145.22:50:43.23#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.22:50:43.29#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.22:50:43.29#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.22:50:43.31#ibcon#[27=AT06-04\r\n] 2006.145.22:50:43.34#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.22:50:43.34#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.22:50:43.34#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.22:50:43.34#ibcon#ireg 7 cls_cnt 0 2006.145.22:50:43.34#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.22:50:43.47#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.22:50:43.47#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.22:50:43.48#ibcon#[27=USB\r\n] 2006.145.22:50:43.51#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.22:50:43.51#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.22:50:43.51#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.22:50:43.51#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.22:50:43.51$vck44/vblo=7,734.99 2006.145.22:50:43.51#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.22:50:43.51#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.22:50:43.51#ibcon#ireg 17 cls_cnt 0 2006.145.22:50:43.51#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:50:43.51#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:50:43.51#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:50:43.53#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.22:50:43.57#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:50:43.57#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.22:50:43.57#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.22:50:43.57#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.22:50:43.57$vck44/vb=7,4 2006.145.22:50:43.57#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.22:50:43.57#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.22:50:43.57#ibcon#ireg 11 cls_cnt 2 2006.145.22:50:43.57#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:50:43.63#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:50:43.63#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:50:43.65#ibcon#[27=AT07-04\r\n] 2006.145.22:50:43.68#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:50:43.68#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.22:50:43.68#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.22:50:43.68#ibcon#ireg 7 cls_cnt 0 2006.145.22:50:43.68#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:50:43.80#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:50:43.80#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:50:43.82#ibcon#[27=USB\r\n] 2006.145.22:50:43.85#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:50:43.85#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.22:50:43.85#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.22:50:43.85#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.22:50:43.85$vck44/vblo=8,744.99 2006.145.22:50:43.85#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.22:50:43.85#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.22:50:43.85#ibcon#ireg 17 cls_cnt 0 2006.145.22:50:43.85#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:50:43.85#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:50:43.85#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:50:43.87#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.22:50:43.91#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:50:43.91#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.22:50:43.91#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.22:50:43.91#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.22:50:43.91$vck44/vb=8,4 2006.145.22:50:43.91#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.22:50:43.91#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.22:50:43.91#ibcon#ireg 11 cls_cnt 2 2006.145.22:50:43.91#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:50:43.97#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:50:43.97#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:50:43.99#ibcon#[27=AT08-04\r\n] 2006.145.22:50:44.02#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:50:44.02#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.22:50:44.02#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.22:50:44.02#ibcon#ireg 7 cls_cnt 0 2006.145.22:50:44.02#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:50:44.14#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:50:44.14#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:50:44.16#ibcon#[27=USB\r\n] 2006.145.22:50:44.19#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:50:44.19#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.22:50:44.19#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.22:50:44.19#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.22:50:44.19$vck44/vabw=wide 2006.145.22:50:44.19#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.22:50:44.19#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.22:50:44.19#ibcon#ireg 8 cls_cnt 0 2006.145.22:50:44.19#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:50:44.19#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:50:44.19#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:50:44.21#ibcon#[25=BW32\r\n] 2006.145.22:50:44.24#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:50:44.24#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.22:50:44.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.22:50:44.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.22:50:44.24$vck44/vbbw=wide 2006.145.22:50:44.24#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.22:50:44.24#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.22:50:44.24#ibcon#ireg 8 cls_cnt 0 2006.145.22:50:44.24#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.22:50:44.31#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.22:50:44.31#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.22:50:44.33#ibcon#[27=BW32\r\n] 2006.145.22:50:44.36#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.22:50:44.36#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.22:50:44.36#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.22:50:44.36#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.22:50:44.36$setupk4/ifdk4 2006.145.22:50:44.36$ifdk4/lo= 2006.145.22:50:44.36$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.22:50:44.36$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.22:50:44.36$ifdk4/patch= 2006.145.22:50:44.36$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.22:50:44.36$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.22:50:44.36$setupk4/!*+20s 2006.145.22:50:50.27#abcon#<5=/07 1.3 3.3 17.99 811020.6\r\n> 2006.145.22:50:50.29#abcon#{5=INTERFACE CLEAR} 2006.145.22:50:50.35#abcon#[5=S1D000X0/0*\r\n] 2006.145.22:50:58.80$setupk4/"tpicd 2006.145.22:50:58.80$setupk4/echo=off 2006.145.22:50:58.80$setupk4/xlog=off 2006.145.22:50:58.80:!2006.145.22:54:13 2006.145.22:51:52.14#trakl#Source acquired 2006.145.22:51:54.14#flagr#flagr/antenna,acquired 2006.145.22:54:13.00:preob 2006.145.22:54:13.13/onsource/TRACKING 2006.145.22:54:13.13:!2006.145.22:54:23 2006.145.22:54:23.00:"tape 2006.145.22:54:23.00:"st=record 2006.145.22:54:23.00:data_valid=on 2006.145.22:54:23.00:midob 2006.145.22:54:24.13/onsource/TRACKING 2006.145.22:54:24.13/wx/18.09,1020.8,80 2006.145.22:54:24.34/cable/+6.5489E-03 2006.145.22:54:25.43/va/01,08,usb,yes,30,33 2006.145.22:54:25.43/va/02,07,usb,yes,33,33 2006.145.22:54:25.43/va/03,08,usb,yes,30,31 2006.145.22:54:25.43/va/04,07,usb,yes,34,35 2006.145.22:54:25.43/va/05,04,usb,yes,29,30 2006.145.22:54:25.43/va/06,04,usb,yes,33,33 2006.145.22:54:25.43/va/07,04,usb,yes,33,35 2006.145.22:54:25.43/va/08,04,usb,yes,28,34 2006.145.22:54:25.66/valo/01,524.99,yes,locked 2006.145.22:54:25.66/valo/02,534.99,yes,locked 2006.145.22:54:25.66/valo/03,564.99,yes,locked 2006.145.22:54:25.66/valo/04,624.99,yes,locked 2006.145.22:54:25.66/valo/05,734.99,yes,locked 2006.145.22:54:25.66/valo/06,814.99,yes,locked 2006.145.22:54:25.66/valo/07,864.99,yes,locked 2006.145.22:54:25.66/valo/08,884.99,yes,locked 2006.145.22:54:26.75/vb/01,03,usb,yes,37,35 2006.145.22:54:26.75/vb/02,04,usb,yes,32,32 2006.145.22:54:26.75/vb/03,04,usb,yes,29,32 2006.145.22:54:26.75/vb/04,04,usb,yes,34,33 2006.145.22:54:26.75/vb/05,04,usb,yes,26,29 2006.145.22:54:26.75/vb/06,04,usb,yes,31,27 2006.145.22:54:26.75/vb/07,04,usb,yes,30,30 2006.145.22:54:26.75/vb/08,04,usb,yes,28,31 2006.145.22:54:26.99/vblo/01,629.99,yes,locked 2006.145.22:54:26.99/vblo/02,634.99,yes,locked 2006.145.22:54:26.99/vblo/03,649.99,yes,locked 2006.145.22:54:26.99/vblo/04,679.99,yes,locked 2006.145.22:54:26.99/vblo/05,709.99,yes,locked 2006.145.22:54:26.99/vblo/06,719.99,yes,locked 2006.145.22:54:26.99/vblo/07,734.99,yes,locked 2006.145.22:54:26.99/vblo/08,744.99,yes,locked 2006.145.22:54:27.14/vabw/8 2006.145.22:54:27.29/vbbw/8 2006.145.22:54:27.38/xfe/off,on,15.2 2006.145.22:54:27.75/ifatt/23,28,28,28 2006.145.22:54:28.07/fmout-gps/S +3.1E-08 2006.145.22:54:28.15:!2006.145.22:56:03 2006.145.22:56:03.01:data_valid=off 2006.145.22:56:03.02:"et 2006.145.22:56:03.02:!+3s 2006.145.22:56:06.03:"tape 2006.145.22:56:06.03:postob 2006.145.22:56:06.20/cable/+6.5465E-03 2006.145.22:56:06.21/wx/18.14,1020.8,80 2006.145.22:56:06.26/fmout-gps/S +3.0E-08 2006.145.22:56:06.26:scan_name=145-2302,jd0605,50 2006.145.22:56:06.26:source=0552+398,055530.81,394849.2,2000.0,cw 2006.145.22:56:08.14#flagr#flagr/antenna,new-source 2006.145.22:56:08.15:checkk5 2006.145.22:56:08.57/chk_autoobs//k5ts1/ autoobs is running! 2006.145.22:56:09.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.22:56:09.72/chk_autoobs//k5ts3/ autoobs is running! 2006.145.22:56:10.17/chk_autoobs//k5ts4/ autoobs is running! 2006.145.22:56:10.59/chk_obsdata//k5ts1/T1452254??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.22:56:11.04/chk_obsdata//k5ts2/T1452254??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.22:56:11.48/chk_obsdata//k5ts3/T1452254??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.22:56:11.93/chk_obsdata//k5ts4/T1452254??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.145.22:56:12.67/k5log//k5ts1_log_newline 2006.145.22:56:13.42/k5log//k5ts2_log_newline 2006.145.22:56:14.17/k5log//k5ts3_log_newline 2006.145.22:56:14.91/k5log//k5ts4_log_newline 2006.145.22:56:14.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.22:56:14.93:setupk4=1 2006.145.22:56:14.93$setupk4/echo=on 2006.145.22:56:14.93$setupk4/pcalon 2006.145.22:56:14.93$pcalon/"no phase cal control is implemented here 2006.145.22:56:14.93$setupk4/"tpicd=stop 2006.145.22:56:14.93$setupk4/"rec=synch_on 2006.145.22:56:14.93$setupk4/"rec_mode=128 2006.145.22:56:14.93$setupk4/!* 2006.145.22:56:14.93$setupk4/recpk4 2006.145.22:56:14.93$recpk4/recpatch= 2006.145.22:56:14.94$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.22:56:14.94$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.22:56:14.94$setupk4/vck44 2006.145.22:56:14.94$vck44/valo=1,524.99 2006.145.22:56:14.94#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.22:56:14.94#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.22:56:14.94#ibcon#ireg 17 cls_cnt 0 2006.145.22:56:14.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.22:56:14.94#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.22:56:14.94#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.22:56:14.99#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.22:56:15.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.22:56:15.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.22:56:15.04#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.22:56:15.04#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.22:56:15.05$vck44/va=1,8 2006.145.22:56:15.05#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.22:56:15.05#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.22:56:15.05#ibcon#ireg 11 cls_cnt 2 2006.145.22:56:15.05#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.22:56:15.05#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.22:56:15.05#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.22:56:15.08#ibcon#[25=AT01-08\r\n] 2006.145.22:56:15.11#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.22:56:15.11#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.22:56:15.11#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.22:56:15.11#ibcon#ireg 7 cls_cnt 0 2006.145.22:56:15.11#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.22:56:15.23#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.22:56:15.23#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.22:56:15.25#ibcon#[25=USB\r\n] 2006.145.22:56:15.28#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.22:56:15.28#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.22:56:15.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.22:56:15.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.22:56:15.28$vck44/valo=2,534.99 2006.145.22:56:15.28#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.22:56:15.28#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.22:56:15.28#ibcon#ireg 17 cls_cnt 0 2006.145.22:56:15.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.22:56:15.28#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.22:56:15.28#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.22:56:15.30#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.22:56:15.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.22:56:15.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.22:56:15.34#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.22:56:15.34#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.22:56:15.34$vck44/va=2,7 2006.145.22:56:15.34#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.22:56:15.34#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.22:56:15.34#ibcon#ireg 11 cls_cnt 2 2006.145.22:56:15.34#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.22:56:15.40#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.22:56:15.40#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.22:56:15.42#ibcon#[25=AT02-07\r\n] 2006.145.22:56:15.45#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.22:56:15.45#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.22:56:15.45#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.22:56:15.45#ibcon#ireg 7 cls_cnt 0 2006.145.22:56:15.45#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.22:56:15.57#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.22:56:15.57#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.22:56:15.59#ibcon#[25=USB\r\n] 2006.145.22:56:15.62#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.22:56:15.62#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.22:56:15.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.22:56:15.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.22:56:15.62$vck44/valo=3,564.99 2006.145.22:56:15.62#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.22:56:15.62#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.22:56:15.62#ibcon#ireg 17 cls_cnt 0 2006.145.22:56:15.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.22:56:15.62#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.22:56:15.62#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.22:56:15.64#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.22:56:15.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.22:56:15.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.22:56:15.68#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.22:56:15.68#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.22:56:15.68$vck44/va=3,8 2006.145.22:56:15.68#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.22:56:15.68#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.22:56:15.68#ibcon#ireg 11 cls_cnt 2 2006.145.22:56:15.68#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.22:56:15.74#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.22:56:15.74#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.22:56:15.76#ibcon#[25=AT03-08\r\n] 2006.145.22:56:15.79#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.22:56:15.79#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.22:56:15.79#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.22:56:15.79#ibcon#ireg 7 cls_cnt 0 2006.145.22:56:15.79#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.22:56:15.80#abcon#<5=/08 1.3 3.1 18.14 801020.8\r\n> 2006.145.22:56:15.82#abcon#{5=INTERFACE CLEAR} 2006.145.22:56:15.88#abcon#[5=S1D000X0/0*\r\n] 2006.145.22:56:15.91#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.22:56:15.91#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.22:56:15.93#ibcon#[25=USB\r\n] 2006.145.22:56:15.96#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.22:56:15.96#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.22:56:15.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.22:56:15.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.22:56:15.96$vck44/valo=4,624.99 2006.145.22:56:15.96#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.22:56:15.96#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.22:56:15.96#ibcon#ireg 17 cls_cnt 0 2006.145.22:56:15.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:56:15.96#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:56:15.96#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:56:15.98#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.22:56:16.02#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:56:16.02#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:56:16.02#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.22:56:16.02#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.22:56:16.02$vck44/va=4,7 2006.145.22:56:16.02#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.22:56:16.02#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.22:56:16.02#ibcon#ireg 11 cls_cnt 2 2006.145.22:56:16.02#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.22:56:16.08#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.22:56:16.08#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.22:56:16.10#ibcon#[25=AT04-07\r\n] 2006.145.22:56:16.13#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.22:56:16.13#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.22:56:16.13#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.22:56:16.13#ibcon#ireg 7 cls_cnt 0 2006.145.22:56:16.13#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.22:56:16.25#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.22:56:16.25#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.22:56:16.27#ibcon#[25=USB\r\n] 2006.145.22:56:16.30#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.22:56:16.30#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.22:56:16.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.22:56:16.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.22:56:16.30$vck44/valo=5,734.99 2006.145.22:56:16.30#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.22:56:16.30#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.22:56:16.30#ibcon#ireg 17 cls_cnt 0 2006.145.22:56:16.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:56:16.30#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:56:16.30#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:56:16.33#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.22:56:16.37#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:56:16.37#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:56:16.37#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.22:56:16.37#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.22:56:16.37$vck44/va=5,4 2006.145.22:56:16.37#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.22:56:16.37#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.22:56:16.37#ibcon#ireg 11 cls_cnt 2 2006.145.22:56:16.37#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:56:16.42#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:56:16.42#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:56:16.44#ibcon#[25=AT05-04\r\n] 2006.145.22:56:16.47#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:56:16.47#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:56:16.47#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.22:56:16.47#ibcon#ireg 7 cls_cnt 0 2006.145.22:56:16.47#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:56:16.59#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:56:16.59#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:56:16.61#ibcon#[25=USB\r\n] 2006.145.22:56:16.64#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:56:16.64#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:56:16.64#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.22:56:16.64#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.22:56:16.64$vck44/valo=6,814.99 2006.145.22:56:16.64#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.22:56:16.64#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.22:56:16.64#ibcon#ireg 17 cls_cnt 0 2006.145.22:56:16.64#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:56:16.64#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:56:16.64#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:56:16.66#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.22:56:16.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:56:16.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:56:16.70#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.22:56:16.70#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.22:56:16.70$vck44/va=6,4 2006.145.22:56:16.70#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.22:56:16.70#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.22:56:16.70#ibcon#ireg 11 cls_cnt 2 2006.145.22:56:16.70#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:56:16.76#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:56:16.76#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:56:16.78#ibcon#[25=AT06-04\r\n] 2006.145.22:56:16.81#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:56:16.81#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:56:16.81#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.22:56:16.81#ibcon#ireg 7 cls_cnt 0 2006.145.22:56:16.81#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:56:16.93#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:56:16.93#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:56:16.95#ibcon#[25=USB\r\n] 2006.145.22:56:16.98#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:56:16.98#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:56:16.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.22:56:16.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.22:56:16.98$vck44/valo=7,864.99 2006.145.22:56:16.98#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.22:56:16.98#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.22:56:16.98#ibcon#ireg 17 cls_cnt 0 2006.145.22:56:16.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:56:16.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:56:16.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:56:17.00#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.22:56:17.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:56:17.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:56:17.04#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.22:56:17.04#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.22:56:17.04$vck44/va=7,4 2006.145.22:56:17.04#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.22:56:17.04#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.22:56:17.04#ibcon#ireg 11 cls_cnt 2 2006.145.22:56:17.04#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.22:56:17.10#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.22:56:17.10#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.22:56:17.12#ibcon#[25=AT07-04\r\n] 2006.145.22:56:17.15#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.22:56:17.15#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.22:56:17.15#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.22:56:17.15#ibcon#ireg 7 cls_cnt 0 2006.145.22:56:17.15#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.22:56:17.27#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.22:56:17.27#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.22:56:17.29#ibcon#[25=USB\r\n] 2006.145.22:56:17.32#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.22:56:17.32#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.22:56:17.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.22:56:17.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.22:56:17.32$vck44/valo=8,884.99 2006.145.22:56:17.32#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.22:56:17.32#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.22:56:17.32#ibcon#ireg 17 cls_cnt 0 2006.145.22:56:17.32#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:56:17.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:56:17.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:56:17.34#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.22:56:17.38#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:56:17.38#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:56:17.38#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.22:56:17.38#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.22:56:17.38$vck44/va=8,4 2006.145.22:56:17.38#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.22:56:17.38#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.22:56:17.38#ibcon#ireg 11 cls_cnt 2 2006.145.22:56:17.38#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.22:56:17.44#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.22:56:17.44#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.22:56:17.46#ibcon#[25=AT08-04\r\n] 2006.145.22:56:17.49#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.22:56:17.49#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.22:56:17.49#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.22:56:17.49#ibcon#ireg 7 cls_cnt 0 2006.145.22:56:17.49#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.22:56:17.61#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.22:56:17.61#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.22:56:17.63#ibcon#[25=USB\r\n] 2006.145.22:56:17.66#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.22:56:17.66#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.22:56:17.66#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.22:56:17.66#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.22:56:17.66$vck44/vblo=1,629.99 2006.145.22:56:17.66#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.22:56:17.66#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.22:56:17.66#ibcon#ireg 17 cls_cnt 0 2006.145.22:56:17.66#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.22:56:17.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.22:56:17.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.22:56:17.69#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.22:56:17.73#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.22:56:17.73#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.22:56:17.73#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.22:56:17.73#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.22:56:17.73$vck44/vb=1,3 2006.145.22:56:17.73#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.22:56:17.73#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.22:56:17.73#ibcon#ireg 11 cls_cnt 2 2006.145.22:56:17.73#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.22:56:17.73#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.22:56:17.73#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.22:56:17.75#ibcon#[27=AT01-03\r\n] 2006.145.22:56:17.78#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.22:56:17.78#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.22:56:17.78#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.22:56:17.78#ibcon#ireg 7 cls_cnt 0 2006.145.22:56:17.78#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.22:56:17.90#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.22:56:17.90#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.22:56:17.92#ibcon#[27=USB\r\n] 2006.145.22:56:17.95#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.22:56:17.95#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.22:56:17.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.22:56:17.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.22:56:17.95$vck44/vblo=2,634.99 2006.145.22:56:17.95#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.22:56:17.95#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.22:56:17.95#ibcon#ireg 17 cls_cnt 0 2006.145.22:56:17.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.22:56:17.95#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.22:56:17.95#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.22:56:17.97#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.22:56:18.01#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.22:56:18.01#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.22:56:18.01#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.22:56:18.01#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.22:56:18.01$vck44/vb=2,4 2006.145.22:56:18.01#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.22:56:18.01#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.22:56:18.01#ibcon#ireg 11 cls_cnt 2 2006.145.22:56:18.01#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.22:56:18.07#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.22:56:18.07#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.22:56:18.09#ibcon#[27=AT02-04\r\n] 2006.145.22:56:18.12#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.22:56:18.12#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.22:56:18.12#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.22:56:18.12#ibcon#ireg 7 cls_cnt 0 2006.145.22:56:18.12#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.22:56:18.24#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.22:56:18.24#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.22:56:18.26#ibcon#[27=USB\r\n] 2006.145.22:56:18.29#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.22:56:18.29#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.22:56:18.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.22:56:18.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.22:56:18.29$vck44/vblo=3,649.99 2006.145.22:56:18.29#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.22:56:18.29#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.22:56:18.29#ibcon#ireg 17 cls_cnt 0 2006.145.22:56:18.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.22:56:18.29#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.22:56:18.29#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.22:56:18.31#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.22:56:18.35#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.22:56:18.35#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.22:56:18.35#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.22:56:18.35#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.22:56:18.35$vck44/vb=3,4 2006.145.22:56:18.35#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.22:56:18.35#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.22:56:18.35#ibcon#ireg 11 cls_cnt 2 2006.145.22:56:18.35#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.22:56:18.41#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.22:56:18.41#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.22:56:18.43#ibcon#[27=AT03-04\r\n] 2006.145.22:56:18.46#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.22:56:18.46#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.22:56:18.46#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.22:56:18.46#ibcon#ireg 7 cls_cnt 0 2006.145.22:56:18.46#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.22:56:18.58#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.22:56:18.58#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.22:56:18.60#ibcon#[27=USB\r\n] 2006.145.22:56:18.63#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.22:56:18.63#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.22:56:18.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.22:56:18.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.22:56:18.63$vck44/vblo=4,679.99 2006.145.22:56:18.63#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.22:56:18.63#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.22:56:18.63#ibcon#ireg 17 cls_cnt 0 2006.145.22:56:18.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:56:18.63#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:56:18.63#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:56:18.65#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.22:56:18.69#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:56:18.69#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.22:56:18.69#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.22:56:18.69#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.22:56:18.69$vck44/vb=4,4 2006.145.22:56:18.69#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.22:56:18.69#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.22:56:18.69#ibcon#ireg 11 cls_cnt 2 2006.145.22:56:18.69#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.22:56:18.75#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.22:56:18.75#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.22:56:18.77#ibcon#[27=AT04-04\r\n] 2006.145.22:56:18.80#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.22:56:18.80#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.22:56:18.80#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.22:56:18.80#ibcon#ireg 7 cls_cnt 0 2006.145.22:56:18.80#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.22:56:18.92#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.22:56:18.92#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.22:56:18.94#ibcon#[27=USB\r\n] 2006.145.22:56:18.97#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.22:56:18.97#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.22:56:18.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.22:56:18.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.22:56:18.97$vck44/vblo=5,709.99 2006.145.22:56:18.97#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.22:56:18.97#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.22:56:18.97#ibcon#ireg 17 cls_cnt 0 2006.145.22:56:18.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:56:18.97#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:56:18.97#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:56:18.99#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.22:56:19.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:56:19.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.22:56:19.03#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.22:56:19.03#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.22:56:19.03$vck44/vb=5,4 2006.145.22:56:19.03#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.22:56:19.03#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.22:56:19.03#ibcon#ireg 11 cls_cnt 2 2006.145.22:56:19.03#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.22:56:19.09#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.22:56:19.09#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.22:56:19.11#ibcon#[27=AT05-04\r\n] 2006.145.22:56:19.14#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.22:56:19.14#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.22:56:19.14#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.22:56:19.14#ibcon#ireg 7 cls_cnt 0 2006.145.22:56:19.14#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.22:56:19.26#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.22:56:19.26#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.22:56:19.28#ibcon#[27=USB\r\n] 2006.145.22:56:19.31#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.22:56:19.31#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.22:56:19.31#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.22:56:19.31#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.22:56:19.31$vck44/vblo=6,719.99 2006.145.22:56:19.31#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.22:56:19.31#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.22:56:19.31#ibcon#ireg 17 cls_cnt 0 2006.145.22:56:19.31#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:56:19.31#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:56:19.31#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:56:19.33#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.22:56:19.37#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:56:19.37#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.22:56:19.37#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.22:56:19.37#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.22:56:19.37$vck44/vb=6,4 2006.145.22:56:19.37#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.22:56:19.37#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.22:56:19.37#ibcon#ireg 11 cls_cnt 2 2006.145.22:56:19.37#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:56:19.43#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:56:19.43#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:56:19.45#ibcon#[27=AT06-04\r\n] 2006.145.22:56:19.48#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:56:19.48#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.22:56:19.48#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.22:56:19.48#ibcon#ireg 7 cls_cnt 0 2006.145.22:56:19.48#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:56:19.60#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:56:19.60#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:56:19.62#ibcon#[27=USB\r\n] 2006.145.22:56:19.65#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:56:19.65#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.22:56:19.65#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.22:56:19.65#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.22:56:19.65$vck44/vblo=7,734.99 2006.145.22:56:19.65#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.22:56:19.65#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.22:56:19.65#ibcon#ireg 17 cls_cnt 0 2006.145.22:56:19.65#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:56:19.65#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:56:19.65#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:56:19.67#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.22:56:19.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:56:19.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.22:56:19.71#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.22:56:19.71#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.22:56:19.71$vck44/vb=7,4 2006.145.22:56:19.71#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.22:56:19.71#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.22:56:19.71#ibcon#ireg 11 cls_cnt 2 2006.145.22:56:19.71#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:56:19.77#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:56:19.77#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:56:19.79#ibcon#[27=AT07-04\r\n] 2006.145.22:56:19.82#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:56:19.82#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.22:56:19.82#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.22:56:19.82#ibcon#ireg 7 cls_cnt 0 2006.145.22:56:19.82#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:56:19.94#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:56:19.94#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:56:19.96#ibcon#[27=USB\r\n] 2006.145.22:56:19.99#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:56:19.99#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.22:56:19.99#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.22:56:19.99#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.22:56:19.99$vck44/vblo=8,744.99 2006.145.22:56:19.99#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.22:56:19.99#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.22:56:19.99#ibcon#ireg 17 cls_cnt 0 2006.145.22:56:19.99#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:56:19.99#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:56:19.99#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:56:20.01#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.22:56:20.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:56:20.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.22:56:20.05#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.22:56:20.05#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.22:56:20.05$vck44/vb=8,4 2006.145.22:56:20.05#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.22:56:20.05#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.22:56:20.05#ibcon#ireg 11 cls_cnt 2 2006.145.22:56:20.05#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.22:56:20.11#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.22:56:20.11#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.22:56:20.13#ibcon#[27=AT08-04\r\n] 2006.145.22:56:20.16#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.22:56:20.16#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.22:56:20.16#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.22:56:20.16#ibcon#ireg 7 cls_cnt 0 2006.145.22:56:20.16#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.22:56:20.28#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.22:56:20.28#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.22:56:20.30#ibcon#[27=USB\r\n] 2006.145.22:56:20.33#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.22:56:20.33#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.22:56:20.33#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.22:56:20.33#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.22:56:20.33$vck44/vabw=wide 2006.145.22:56:20.33#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.22:56:20.33#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.22:56:20.33#ibcon#ireg 8 cls_cnt 0 2006.145.22:56:20.33#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:56:20.33#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:56:20.33#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:56:20.35#ibcon#[25=BW32\r\n] 2006.145.22:56:20.38#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:56:20.38#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.22:56:20.38#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.22:56:20.38#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.22:56:20.38$vck44/vbbw=wide 2006.145.22:56:20.38#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.22:56:20.38#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.22:56:20.38#ibcon#ireg 8 cls_cnt 0 2006.145.22:56:20.38#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.22:56:20.45#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.22:56:20.45#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.22:56:20.47#ibcon#[27=BW32\r\n] 2006.145.22:56:20.50#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.22:56:20.50#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.22:56:20.50#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.22:56:20.50#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.22:56:20.50$setupk4/ifdk4 2006.145.22:56:20.50$ifdk4/lo= 2006.145.22:56:20.50$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.22:56:20.50$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.22:56:20.50$ifdk4/patch= 2006.145.22:56:20.50$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.22:56:20.50$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.22:56:20.50$setupk4/!*+20s 2006.145.22:56:25.97#abcon#<5=/07 1.3 3.1 18.15 801020.9\r\n> 2006.145.22:56:25.99#abcon#{5=INTERFACE CLEAR} 2006.145.22:56:26.05#abcon#[5=S1D000X0/0*\r\n] 2006.145.22:56:26.14#trakl#Source acquired 2006.145.22:56:27.14#flagr#flagr/antenna,acquired 2006.145.22:56:34.94$setupk4/"tpicd 2006.145.22:56:34.94$setupk4/echo=off 2006.145.22:56:34.94$setupk4/xlog=off 2006.145.22:56:34.94:!2006.145.23:01:59 2006.145.23:01:59.00:preob 2006.145.23:01:59.14/onsource/TRACKING 2006.145.23:01:59.14:!2006.145.23:02:09 2006.145.23:02:09.00:"tape 2006.145.23:02:09.00:"st=record 2006.145.23:02:09.00:data_valid=on 2006.145.23:02:09.00:midob 2006.145.23:02:09.14/onsource/TRACKING 2006.145.23:02:09.14/wx/18.31,1020.7,78 2006.145.23:02:09.33/cable/+6.5469E-03 2006.145.23:02:10.42/va/01,08,usb,yes,29,31 2006.145.23:02:10.42/va/02,07,usb,yes,31,32 2006.145.23:02:10.42/va/03,08,usb,yes,29,30 2006.145.23:02:10.42/va/04,07,usb,yes,32,34 2006.145.23:02:10.42/va/05,04,usb,yes,28,29 2006.145.23:02:10.42/va/06,04,usb,yes,32,32 2006.145.23:02:10.42/va/07,04,usb,yes,32,33 2006.145.23:02:10.42/va/08,04,usb,yes,27,33 2006.145.23:02:10.65/valo/01,524.99,yes,locked 2006.145.23:02:10.65/valo/02,534.99,yes,locked 2006.145.23:02:10.65/valo/03,564.99,yes,locked 2006.145.23:02:10.65/valo/04,624.99,yes,locked 2006.145.23:02:10.65/valo/05,734.99,yes,locked 2006.145.23:02:10.65/valo/06,814.99,yes,locked 2006.145.23:02:10.65/valo/07,864.99,yes,locked 2006.145.23:02:10.65/valo/08,884.99,yes,locked 2006.145.23:02:11.74/vb/01,03,usb,yes,36,34 2006.145.23:02:11.74/vb/02,04,usb,yes,32,32 2006.145.23:02:11.74/vb/03,04,usb,yes,29,32 2006.145.23:02:11.74/vb/04,04,usb,yes,33,32 2006.145.23:02:11.74/vb/05,04,usb,yes,26,28 2006.145.23:02:11.74/vb/06,04,usb,yes,30,26 2006.145.23:02:11.74/vb/07,04,usb,yes,30,30 2006.145.23:02:11.74/vb/08,04,usb,yes,28,31 2006.145.23:02:11.97/vblo/01,629.99,yes,locked 2006.145.23:02:11.97/vblo/02,634.99,yes,locked 2006.145.23:02:11.97/vblo/03,649.99,yes,locked 2006.145.23:02:11.97/vblo/04,679.99,yes,locked 2006.145.23:02:11.97/vblo/05,709.99,yes,locked 2006.145.23:02:11.97/vblo/06,719.99,yes,locked 2006.145.23:02:11.97/vblo/07,734.99,yes,locked 2006.145.23:02:11.97/vblo/08,744.99,yes,locked 2006.145.23:02:12.12/vabw/8 2006.145.23:02:12.27/vbbw/8 2006.145.23:02:12.36/xfe/off,on,16.0 2006.145.23:02:12.74/ifatt/23,28,28,28 2006.145.23:02:13.08/fmout-gps/S +3.3E-08 2006.145.23:02:13.12:!2006.145.23:02:59 2006.145.23:02:59.01:data_valid=off 2006.145.23:02:59.01:"et 2006.145.23:02:59.02:!+3s 2006.145.23:03:02.03:"tape 2006.145.23:03:02.03:postob 2006.145.23:03:02.17/cable/+6.5471E-03 2006.145.23:03:02.17/wx/18.33,1020.8,78 2006.145.23:03:02.26/fmout-gps/S +3.3E-08 2006.145.23:03:02.26:scan_name=145-2306,jd0605,280 2006.145.23:03:02.26:source=cta26,033930.94,-014635.8,2000.0,cw 2006.145.23:03:03.13#flagr#flagr/antenna,new-source 2006.145.23:03:03.13:checkk5 2006.145.23:03:03.57/chk_autoobs//k5ts1/ autoobs is running! 2006.145.23:03:04.00/chk_autoobs//k5ts2/ autoobs is running! 2006.145.23:03:04.44/chk_autoobs//k5ts3/ autoobs is running! 2006.145.23:03:04.86/chk_autoobs//k5ts4/ autoobs is running! 2006.145.23:03:05.29/chk_obsdata//k5ts1/T1452302??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.23:03:05.70/chk_obsdata//k5ts2/T1452302??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.23:03:06.15/chk_obsdata//k5ts3/T1452302??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.23:03:06.59/chk_obsdata//k5ts4/T1452302??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.145.23:03:07.33/k5log//k5ts1_log_newline 2006.145.23:03:08.07/k5log//k5ts2_log_newline 2006.145.23:03:08.82/k5log//k5ts3_log_newline 2006.145.23:03:09.59/k5log//k5ts4_log_newline 2006.145.23:03:09.61/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.23:03:09.61:setupk4=1 2006.145.23:03:09.61$setupk4/echo=on 2006.145.23:03:09.61$setupk4/pcalon 2006.145.23:03:09.61$pcalon/"no phase cal control is implemented here 2006.145.23:03:09.61$setupk4/"tpicd=stop 2006.145.23:03:09.61$setupk4/"rec=synch_on 2006.145.23:03:09.61$setupk4/"rec_mode=128 2006.145.23:03:09.61$setupk4/!* 2006.145.23:03:09.61$setupk4/recpk4 2006.145.23:03:09.61$recpk4/recpatch= 2006.145.23:03:09.61$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.23:03:09.61$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.23:03:09.61$setupk4/vck44 2006.145.23:03:09.61$vck44/valo=1,524.99 2006.145.23:03:09.61#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.23:03:09.61#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.23:03:09.61#ibcon#ireg 17 cls_cnt 0 2006.145.23:03:09.61#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.23:03:09.61#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.23:03:09.61#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.23:03:09.65#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.23:03:09.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.23:03:09.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.23:03:09.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.23:03:09.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.23:03:09.70$vck44/va=1,8 2006.145.23:03:09.70#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.23:03:09.70#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.23:03:09.70#ibcon#ireg 11 cls_cnt 2 2006.145.23:03:09.70#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.23:03:09.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.23:03:09.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.23:03:09.72#ibcon#[25=AT01-08\r\n] 2006.145.23:03:09.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.23:03:09.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.23:03:09.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.23:03:09.75#ibcon#ireg 7 cls_cnt 0 2006.145.23:03:09.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.23:03:09.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.23:03:09.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.23:03:09.89#ibcon#[25=USB\r\n] 2006.145.23:03:09.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.23:03:09.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.23:03:09.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.23:03:09.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.23:03:09.92$vck44/valo=2,534.99 2006.145.23:03:09.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.23:03:09.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.23:03:09.92#ibcon#ireg 17 cls_cnt 0 2006.145.23:03:09.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.23:03:09.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.23:03:09.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.23:03:09.95#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.23:03:09.99#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.23:03:09.99#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.23:03:09.99#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.23:03:09.99#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.23:03:09.99$vck44/va=2,7 2006.145.23:03:09.99#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.23:03:09.99#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.23:03:09.99#ibcon#ireg 11 cls_cnt 2 2006.145.23:03:09.99#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.23:03:10.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.23:03:10.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.23:03:10.06#ibcon#[25=AT02-07\r\n] 2006.145.23:03:10.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.23:03:10.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.23:03:10.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.23:03:10.09#ibcon#ireg 7 cls_cnt 0 2006.145.23:03:10.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.23:03:10.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.23:03:10.21#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.23:03:10.23#ibcon#[25=USB\r\n] 2006.145.23:03:10.26#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.23:03:10.26#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.23:03:10.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.23:03:10.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.23:03:10.26$vck44/valo=3,564.99 2006.145.23:03:10.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.23:03:10.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.23:03:10.26#ibcon#ireg 17 cls_cnt 0 2006.145.23:03:10.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.23:03:10.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.23:03:10.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.23:03:10.28#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.23:03:10.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.23:03:10.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.23:03:10.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.23:03:10.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.23:03:10.32$vck44/va=3,8 2006.145.23:03:10.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.23:03:10.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.23:03:10.32#ibcon#ireg 11 cls_cnt 2 2006.145.23:03:10.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.23:03:10.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.23:03:10.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.23:03:10.40#ibcon#[25=AT03-08\r\n] 2006.145.23:03:10.43#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.23:03:10.43#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.23:03:10.43#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.23:03:10.43#ibcon#ireg 7 cls_cnt 0 2006.145.23:03:10.43#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.23:03:10.55#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.23:03:10.55#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.23:03:10.57#ibcon#[25=USB\r\n] 2006.145.23:03:10.60#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.23:03:10.60#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.23:03:10.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.23:03:10.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.23:03:10.60$vck44/valo=4,624.99 2006.145.23:03:10.60#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.23:03:10.60#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.23:03:10.60#ibcon#ireg 17 cls_cnt 0 2006.145.23:03:10.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.23:03:10.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.23:03:10.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.23:03:10.62#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.23:03:10.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.23:03:10.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.23:03:10.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.23:03:10.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.23:03:10.66$vck44/va=4,7 2006.145.23:03:10.66#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.23:03:10.66#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.23:03:10.66#ibcon#ireg 11 cls_cnt 2 2006.145.23:03:10.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.23:03:10.72#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.23:03:10.72#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.23:03:10.74#ibcon#[25=AT04-07\r\n] 2006.145.23:03:10.77#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.23:03:10.77#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.23:03:10.77#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.23:03:10.77#ibcon#ireg 7 cls_cnt 0 2006.145.23:03:10.77#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.23:03:10.89#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.23:03:10.89#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.23:03:10.91#ibcon#[25=USB\r\n] 2006.145.23:03:10.94#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.23:03:10.94#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.23:03:10.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.23:03:10.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.23:03:10.94$vck44/valo=5,734.99 2006.145.23:03:10.94#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.23:03:10.94#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.23:03:10.94#ibcon#ireg 17 cls_cnt 0 2006.145.23:03:10.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.23:03:10.94#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.23:03:10.94#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.23:03:10.96#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.23:03:11.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.23:03:11.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.23:03:11.00#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.23:03:11.00#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.23:03:11.00$vck44/va=5,4 2006.145.23:03:11.00#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.23:03:11.00#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.23:03:11.00#ibcon#ireg 11 cls_cnt 2 2006.145.23:03:11.00#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.23:03:11.06#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.23:03:11.06#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.23:03:11.08#ibcon#[25=AT05-04\r\n] 2006.145.23:03:11.11#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.23:03:11.11#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.23:03:11.11#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.23:03:11.11#ibcon#ireg 7 cls_cnt 0 2006.145.23:03:11.11#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.23:03:11.23#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.23:03:11.23#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.23:03:11.25#ibcon#[25=USB\r\n] 2006.145.23:03:11.28#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.23:03:11.28#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.23:03:11.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.23:03:11.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.23:03:11.28$vck44/valo=6,814.99 2006.145.23:03:11.28#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.23:03:11.28#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.23:03:11.28#ibcon#ireg 17 cls_cnt 0 2006.145.23:03:11.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.23:03:11.28#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.23:03:11.28#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.23:03:11.30#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.23:03:11.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.23:03:11.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.23:03:11.34#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.23:03:11.34#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.23:03:11.34$vck44/va=6,4 2006.145.23:03:11.34#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.23:03:11.34#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.23:03:11.34#ibcon#ireg 11 cls_cnt 2 2006.145.23:03:11.34#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.23:03:11.40#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.23:03:11.40#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.23:03:11.42#ibcon#[25=AT06-04\r\n] 2006.145.23:03:11.45#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.23:03:11.45#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.23:03:11.45#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.23:03:11.45#ibcon#ireg 7 cls_cnt 0 2006.145.23:03:11.45#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.23:03:11.57#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.23:03:11.57#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.23:03:11.59#ibcon#[25=USB\r\n] 2006.145.23:03:11.62#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.23:03:11.62#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.23:03:11.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.23:03:11.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.23:03:11.62$vck44/valo=7,864.99 2006.145.23:03:11.62#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.23:03:11.62#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.23:03:11.62#ibcon#ireg 17 cls_cnt 0 2006.145.23:03:11.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.23:03:11.62#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.23:03:11.62#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.23:03:11.64#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.23:03:11.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.23:03:11.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.23:03:11.68#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.23:03:11.68#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.23:03:11.68$vck44/va=7,4 2006.145.23:03:11.68#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.23:03:11.68#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.23:03:11.68#ibcon#ireg 11 cls_cnt 2 2006.145.23:03:11.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.23:03:11.74#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.23:03:11.74#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.23:03:11.76#ibcon#[25=AT07-04\r\n] 2006.145.23:03:11.79#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.23:03:11.79#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.23:03:11.79#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.23:03:11.79#ibcon#ireg 7 cls_cnt 0 2006.145.23:03:11.79#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.23:03:11.91#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.23:03:11.91#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.23:03:11.93#ibcon#[25=USB\r\n] 2006.145.23:03:11.96#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.23:03:11.96#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.23:03:11.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.23:03:11.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.23:03:11.96$vck44/valo=8,884.99 2006.145.23:03:11.96#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.23:03:11.96#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.23:03:11.96#ibcon#ireg 17 cls_cnt 0 2006.145.23:03:11.96#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.23:03:11.96#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.23:03:11.96#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.23:03:11.98#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.23:03:12.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.23:03:12.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.23:03:12.02#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.23:03:12.02#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.23:03:12.02$vck44/va=8,4 2006.145.23:03:12.02#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.23:03:12.02#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.23:03:12.02#ibcon#ireg 11 cls_cnt 2 2006.145.23:03:12.02#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.23:03:12.08#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.23:03:12.08#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.23:03:12.10#ibcon#[25=AT08-04\r\n] 2006.145.23:03:12.13#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.23:03:12.13#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.23:03:12.13#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.23:03:12.13#ibcon#ireg 7 cls_cnt 0 2006.145.23:03:12.13#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.23:03:12.25#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.23:03:12.25#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.23:03:12.27#ibcon#[25=USB\r\n] 2006.145.23:03:12.30#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.23:03:12.30#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.23:03:12.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.23:03:12.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.23:03:12.30$vck44/vblo=1,629.99 2006.145.23:03:12.30#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.23:03:12.30#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.23:03:12.30#ibcon#ireg 17 cls_cnt 0 2006.145.23:03:12.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.23:03:12.30#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.23:03:12.30#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.23:03:12.32#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.23:03:12.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.23:03:12.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.23:03:12.36#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.23:03:12.36#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.23:03:12.36$vck44/vb=1,3 2006.145.23:03:12.36#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.23:03:12.36#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.23:03:12.36#ibcon#ireg 11 cls_cnt 2 2006.145.23:03:12.36#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.23:03:12.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.23:03:12.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.23:03:12.38#ibcon#[27=AT01-03\r\n] 2006.145.23:03:12.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.23:03:12.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.23:03:12.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.23:03:12.41#ibcon#ireg 7 cls_cnt 0 2006.145.23:03:12.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.23:03:12.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.23:03:12.53#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.23:03:12.55#ibcon#[27=USB\r\n] 2006.145.23:03:12.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.23:03:12.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.23:03:12.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.23:03:12.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.23:03:12.58$vck44/vblo=2,634.99 2006.145.23:03:12.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.23:03:12.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.23:03:12.58#ibcon#ireg 17 cls_cnt 0 2006.145.23:03:12.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.23:03:12.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.23:03:12.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.23:03:12.60#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.23:03:12.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.23:03:12.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.23:03:12.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.23:03:12.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.23:03:12.64$vck44/vb=2,4 2006.145.23:03:12.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.23:03:12.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.23:03:12.64#ibcon#ireg 11 cls_cnt 2 2006.145.23:03:12.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.23:03:12.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.23:03:12.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.23:03:12.72#ibcon#[27=AT02-04\r\n] 2006.145.23:03:12.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.23:03:12.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.23:03:12.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.23:03:12.75#ibcon#ireg 7 cls_cnt 0 2006.145.23:03:12.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.23:03:12.82#abcon#<5=/08 1.3 3.5 18.34 781020.8\r\n> 2006.145.23:03:12.84#abcon#{5=INTERFACE CLEAR} 2006.145.23:03:12.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.23:03:12.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.23:03:12.89#ibcon#[27=USB\r\n] 2006.145.23:03:12.90#abcon#[5=S1D000X0/0*\r\n] 2006.145.23:03:12.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.23:03:12.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.23:03:12.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.23:03:12.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.23:03:12.92$vck44/vblo=3,649.99 2006.145.23:03:12.92#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.23:03:12.92#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.23:03:12.92#ibcon#ireg 17 cls_cnt 0 2006.145.23:03:12.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.23:03:12.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.23:03:12.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.23:03:12.94#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.23:03:12.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.23:03:12.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.23:03:12.98#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.23:03:12.98#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.23:03:12.98$vck44/vb=3,4 2006.145.23:03:12.98#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.23:03:12.98#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.23:03:12.98#ibcon#ireg 11 cls_cnt 2 2006.145.23:03:12.98#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.23:03:13.04#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.23:03:13.04#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.23:03:13.06#ibcon#[27=AT03-04\r\n] 2006.145.23:03:13.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.23:03:13.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.23:03:13.09#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.23:03:13.09#ibcon#ireg 7 cls_cnt 0 2006.145.23:03:13.09#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.23:03:13.21#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.23:03:13.21#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.23:03:13.23#ibcon#[27=USB\r\n] 2006.145.23:03:13.26#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.23:03:13.26#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.23:03:13.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.23:03:13.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.23:03:13.26$vck44/vblo=4,679.99 2006.145.23:03:13.26#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.23:03:13.26#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.23:03:13.26#ibcon#ireg 17 cls_cnt 0 2006.145.23:03:13.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.23:03:13.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.23:03:13.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.23:03:13.28#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.23:03:13.32#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.23:03:13.32#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.23:03:13.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.23:03:13.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.23:03:13.32$vck44/vb=4,4 2006.145.23:03:13.32#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.23:03:13.32#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.23:03:13.32#ibcon#ireg 11 cls_cnt 2 2006.145.23:03:13.32#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.23:03:13.38#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.23:03:13.38#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.23:03:13.40#ibcon#[27=AT04-04\r\n] 2006.145.23:03:13.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.23:03:13.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.23:03:13.43#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.23:03:13.43#ibcon#ireg 7 cls_cnt 0 2006.145.23:03:13.43#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.23:03:13.55#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.23:03:13.55#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.23:03:13.57#ibcon#[27=USB\r\n] 2006.145.23:03:13.60#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.23:03:13.60#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.23:03:13.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.23:03:13.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.23:03:13.60$vck44/vblo=5,709.99 2006.145.23:03:13.60#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.23:03:13.60#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.23:03:13.60#ibcon#ireg 17 cls_cnt 0 2006.145.23:03:13.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.23:03:13.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.23:03:13.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.23:03:13.62#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.23:03:13.66#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.23:03:13.66#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.23:03:13.66#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.23:03:13.66#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.23:03:13.66$vck44/vb=5,4 2006.145.23:03:13.66#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.23:03:13.66#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.23:03:13.66#ibcon#ireg 11 cls_cnt 2 2006.145.23:03:13.66#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.23:03:13.72#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.23:03:13.72#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.23:03:13.74#ibcon#[27=AT05-04\r\n] 2006.145.23:03:13.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.23:03:13.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.23:03:13.77#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.23:03:13.77#ibcon#ireg 7 cls_cnt 0 2006.145.23:03:13.77#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.23:03:13.89#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.23:03:13.89#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.23:03:13.91#ibcon#[27=USB\r\n] 2006.145.23:03:13.94#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.23:03:13.94#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.23:03:13.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.23:03:13.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.23:03:13.94$vck44/vblo=6,719.99 2006.145.23:03:13.94#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.23:03:13.94#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.23:03:13.94#ibcon#ireg 17 cls_cnt 0 2006.145.23:03:13.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.23:03:13.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.23:03:13.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.23:03:13.96#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.23:03:14.00#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.23:03:14.00#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.23:03:14.00#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.23:03:14.00#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.23:03:14.00$vck44/vb=6,4 2006.145.23:03:14.00#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.23:03:14.00#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.23:03:14.00#ibcon#ireg 11 cls_cnt 2 2006.145.23:03:14.00#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.23:03:14.06#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.23:03:14.06#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.23:03:14.08#ibcon#[27=AT06-04\r\n] 2006.145.23:03:14.11#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.23:03:14.11#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.23:03:14.11#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.23:03:14.11#ibcon#ireg 7 cls_cnt 0 2006.145.23:03:14.11#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.23:03:14.23#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.23:03:14.23#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.23:03:14.25#ibcon#[27=USB\r\n] 2006.145.23:03:14.28#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.23:03:14.28#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.23:03:14.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.23:03:14.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.23:03:14.28$vck44/vblo=7,734.99 2006.145.23:03:14.28#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.23:03:14.28#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.23:03:14.28#ibcon#ireg 17 cls_cnt 0 2006.145.23:03:14.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.23:03:14.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.23:03:14.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.23:03:14.30#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.23:03:14.34#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.23:03:14.34#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.23:03:14.34#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.23:03:14.34#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.23:03:14.34$vck44/vb=7,4 2006.145.23:03:14.34#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.23:03:14.34#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.23:03:14.34#ibcon#ireg 11 cls_cnt 2 2006.145.23:03:14.34#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.23:03:14.40#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.23:03:14.40#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.23:03:14.42#ibcon#[27=AT07-04\r\n] 2006.145.23:03:14.45#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.23:03:14.45#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.23:03:14.45#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.23:03:14.45#ibcon#ireg 7 cls_cnt 0 2006.145.23:03:14.45#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.23:03:14.57#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.23:03:14.57#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.23:03:14.59#ibcon#[27=USB\r\n] 2006.145.23:03:14.62#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.23:03:14.62#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.23:03:14.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.23:03:14.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.23:03:14.62$vck44/vblo=8,744.99 2006.145.23:03:14.62#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.23:03:14.62#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.23:03:14.62#ibcon#ireg 17 cls_cnt 0 2006.145.23:03:14.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.23:03:14.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.23:03:14.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.23:03:14.64#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.23:03:14.68#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.23:03:14.68#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.23:03:14.68#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.23:03:14.68#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.23:03:14.68$vck44/vb=8,4 2006.145.23:03:14.68#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.23:03:14.68#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.23:03:14.68#ibcon#ireg 11 cls_cnt 2 2006.145.23:03:14.68#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.23:03:14.74#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.23:03:14.74#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.23:03:14.76#ibcon#[27=AT08-04\r\n] 2006.145.23:03:14.79#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.23:03:14.79#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.23:03:14.79#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.23:03:14.79#ibcon#ireg 7 cls_cnt 0 2006.145.23:03:14.79#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.23:03:14.91#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.23:03:14.91#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.23:03:14.93#ibcon#[27=USB\r\n] 2006.145.23:03:14.96#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.23:03:14.96#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.23:03:14.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.23:03:14.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.23:03:14.96$vck44/vabw=wide 2006.145.23:03:14.96#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.23:03:14.96#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.23:03:14.96#ibcon#ireg 8 cls_cnt 0 2006.145.23:03:14.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.23:03:14.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.23:03:14.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.23:03:14.99#ibcon#[25=BW32\r\n] 2006.145.23:03:15.02#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.23:03:15.02#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.23:03:15.02#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.23:03:15.02#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.23:03:15.02$vck44/vbbw=wide 2006.145.23:03:15.02#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.23:03:15.02#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.23:03:15.02#ibcon#ireg 8 cls_cnt 0 2006.145.23:03:15.02#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.23:03:15.08#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.23:03:15.08#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.23:03:15.10#ibcon#[27=BW32\r\n] 2006.145.23:03:15.13#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.23:03:15.13#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.23:03:15.13#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.23:03:15.13#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.23:03:15.13$setupk4/ifdk4 2006.145.23:03:15.13$ifdk4/lo= 2006.145.23:03:15.13$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.23:03:15.13$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.23:03:15.13$ifdk4/patch= 2006.145.23:03:15.13$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.23:03:15.13$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.23:03:15.13$setupk4/!*+20s 2006.145.23:03:22.99#abcon#<5=/08 1.3 3.5 18.35 771020.8\r\n> 2006.145.23:03:23.01#abcon#{5=INTERFACE CLEAR} 2006.145.23:03:23.07#abcon#[5=S1D000X0/0*\r\n] 2006.145.23:03:29.62$setupk4/"tpicd 2006.145.23:03:29.62$setupk4/echo=off 2006.145.23:03:29.62$setupk4/xlog=off 2006.145.23:03:29.62:!2006.145.23:06:15 2006.145.23:03:34.13#trakl#Source acquired 2006.145.23:03:34.13#flagr#flagr/antenna,acquired 2006.145.23:06:15.00:preob 2006.145.23:06:15.14/onsource/TRACKING 2006.145.23:06:15.14:!2006.145.23:06:25 2006.145.23:06:25.00:"tape 2006.145.23:06:25.00:"st=record 2006.145.23:06:25.00:data_valid=on 2006.145.23:06:25.00:midob 2006.145.23:06:25.14/onsource/TRACKING 2006.145.23:06:25.14/wx/18.42,1020.9,77 2006.145.23:06:25.25/cable/+6.5502E-03 2006.145.23:06:26.34/va/01,08,usb,yes,29,31 2006.145.23:06:26.34/va/02,07,usb,yes,31,31 2006.145.23:06:26.34/va/03,08,usb,yes,28,29 2006.145.23:06:26.34/va/04,07,usb,yes,32,33 2006.145.23:06:26.34/va/05,04,usb,yes,28,28 2006.145.23:06:26.34/va/06,04,usb,yes,31,31 2006.145.23:06:26.34/va/07,04,usb,yes,31,33 2006.145.23:06:26.34/va/08,04,usb,yes,27,32 2006.145.23:06:26.57/valo/01,524.99,yes,locked 2006.145.23:06:26.57/valo/02,534.99,yes,locked 2006.145.23:06:26.57/valo/03,564.99,yes,locked 2006.145.23:06:26.57/valo/04,624.99,yes,locked 2006.145.23:06:26.57/valo/05,734.99,yes,locked 2006.145.23:06:26.57/valo/06,814.99,yes,locked 2006.145.23:06:26.57/valo/07,864.99,yes,locked 2006.145.23:06:26.57/valo/08,884.99,yes,locked 2006.145.23:06:27.66/vb/01,03,usb,yes,36,34 2006.145.23:06:27.66/vb/02,04,usb,yes,31,31 2006.145.23:06:27.66/vb/03,04,usb,yes,28,31 2006.145.23:06:27.66/vb/04,04,usb,yes,33,32 2006.145.23:06:27.66/vb/05,04,usb,yes,25,28 2006.145.23:06:27.66/vb/06,04,usb,yes,30,26 2006.145.23:06:27.66/vb/07,04,usb,yes,30,29 2006.145.23:06:27.66/vb/08,04,usb,yes,27,30 2006.145.23:06:27.90/vblo/01,629.99,yes,locked 2006.145.23:06:27.90/vblo/02,634.99,yes,locked 2006.145.23:06:27.90/vblo/03,649.99,yes,locked 2006.145.23:06:27.90/vblo/04,679.99,yes,locked 2006.145.23:06:27.90/vblo/05,709.99,yes,locked 2006.145.23:06:27.90/vblo/06,719.99,yes,locked 2006.145.23:06:27.90/vblo/07,734.99,yes,locked 2006.145.23:06:27.90/vblo/08,744.99,yes,locked 2006.145.23:06:28.05/vabw/8 2006.145.23:06:28.20/vbbw/8 2006.145.23:06:28.29/xfe/off,on,14.5 2006.145.23:06:28.68/ifatt/23,28,28,28 2006.145.23:06:29.07/fmout-gps/S +3.3E-08 2006.145.23:06:29.15:!2006.145.23:11:05 2006.145.23:11:05.00:data_valid=off 2006.145.23:11:05.00:"et 2006.145.23:11:05.00:!+3s 2006.145.23:11:08.02:"tape 2006.145.23:11:08.02:postob 2006.145.23:11:08.09/cable/+6.5489E-03 2006.145.23:11:08.10/wx/18.57,1021.0,77 2006.145.23:11:09.08/fmout-gps/S +3.3E-08 2006.145.23:11:09.08:scan_name=145-2320,jd0605,190 2006.145.23:11:09.09:source=3c446,222547.26,-045701.4,2000.0,cw 2006.145.23:11:10.13#flagr#flagr/antenna,new-source 2006.145.23:11:10.13:checkk5 2006.145.23:11:10.57/chk_autoobs//k5ts1/ autoobs is running! 2006.145.23:11:11.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.23:11:11.46/chk_autoobs//k5ts3/ autoobs is running! 2006.145.23:11:11.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.23:11:12.31/chk_obsdata//k5ts1/T1452306??a.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.145.23:11:12.75/chk_obsdata//k5ts2/T1452306??b.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.145.23:11:13.20/chk_obsdata//k5ts3/T1452306??c.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.145.23:11:13.63/chk_obsdata//k5ts4/T1452306??d.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.145.23:11:14.39/k5log//k5ts1_log_newline 2006.145.23:11:15.14/k5log//k5ts2_log_newline 2006.145.23:11:15.87/k5log//k5ts3_log_newline 2006.145.23:11:16.61/k5log//k5ts4_log_newline 2006.145.23:11:16.63/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.23:11:16.63:setupk4=1 2006.145.23:11:16.63$setupk4/echo=on 2006.145.23:11:16.63$setupk4/pcalon 2006.145.23:11:16.63$pcalon/"no phase cal control is implemented here 2006.145.23:11:16.63$setupk4/"tpicd=stop 2006.145.23:11:16.63$setupk4/"rec=synch_on 2006.145.23:11:16.63$setupk4/"rec_mode=128 2006.145.23:11:16.63$setupk4/!* 2006.145.23:11:16.63$setupk4/recpk4 2006.145.23:11:16.63$recpk4/recpatch= 2006.145.23:11:16.64$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.23:11:16.64$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.23:11:16.64$setupk4/vck44 2006.145.23:11:16.64$vck44/valo=1,524.99 2006.145.23:11:16.64#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.23:11:16.64#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.23:11:16.64#ibcon#ireg 17 cls_cnt 0 2006.145.23:11:16.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.23:11:16.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.23:11:16.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.23:11:16.68#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.23:11:16.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.23:11:16.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.23:11:16.73#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.23:11:16.73#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.23:11:16.73$vck44/va=1,8 2006.145.23:11:16.73#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.23:11:16.73#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.23:11:16.73#ibcon#ireg 11 cls_cnt 2 2006.145.23:11:16.73#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.23:11:16.73#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.23:11:16.73#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.23:11:16.75#ibcon#[25=AT01-08\r\n] 2006.145.23:11:16.78#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.23:11:16.78#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.23:11:16.78#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.23:11:16.78#ibcon#ireg 7 cls_cnt 0 2006.145.23:11:16.78#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.23:11:16.90#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.23:11:16.90#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.23:11:16.92#ibcon#[25=USB\r\n] 2006.145.23:11:16.95#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.23:11:16.95#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.23:11:16.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.23:11:16.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.23:11:16.95$vck44/valo=2,534.99 2006.145.23:11:16.95#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.23:11:16.95#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.23:11:16.95#ibcon#ireg 17 cls_cnt 0 2006.145.23:11:16.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.23:11:16.95#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.23:11:16.95#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.23:11:16.98#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.23:11:17.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.23:11:17.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.23:11:17.02#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.23:11:17.02#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.23:11:17.02$vck44/va=2,7 2006.145.23:11:17.02#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.23:11:17.02#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.23:11:17.02#ibcon#ireg 11 cls_cnt 2 2006.145.23:11:17.02#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.23:11:17.07#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.23:11:17.07#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.23:11:17.09#ibcon#[25=AT02-07\r\n] 2006.145.23:11:17.12#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.23:11:17.12#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.23:11:17.12#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.23:11:17.12#ibcon#ireg 7 cls_cnt 0 2006.145.23:11:17.12#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.23:11:17.24#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.23:11:17.24#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.23:11:17.26#ibcon#[25=USB\r\n] 2006.145.23:11:17.29#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.23:11:17.29#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.23:11:17.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.23:11:17.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.23:11:17.29$vck44/valo=3,564.99 2006.145.23:11:17.29#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.23:11:17.29#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.23:11:17.29#ibcon#ireg 17 cls_cnt 0 2006.145.23:11:17.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.23:11:17.29#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.23:11:17.29#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.23:11:17.31#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.23:11:17.35#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.23:11:17.35#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.23:11:17.35#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.23:11:17.35#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.23:11:17.35$vck44/va=3,8 2006.145.23:11:17.35#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.23:11:17.35#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.23:11:17.35#ibcon#ireg 11 cls_cnt 2 2006.145.23:11:17.35#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.23:11:17.41#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.23:11:17.41#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.23:11:17.43#ibcon#[25=AT03-08\r\n] 2006.145.23:11:17.46#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.23:11:17.46#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.23:11:17.46#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.23:11:17.46#ibcon#ireg 7 cls_cnt 0 2006.145.23:11:17.46#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.23:11:17.58#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.23:11:17.58#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.23:11:17.60#ibcon#[25=USB\r\n] 2006.145.23:11:17.63#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.23:11:17.63#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.23:11:17.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.23:11:17.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.23:11:17.63$vck44/valo=4,624.99 2006.145.23:11:17.63#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.23:11:17.63#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.23:11:17.63#ibcon#ireg 17 cls_cnt 0 2006.145.23:11:17.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.23:11:17.63#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.23:11:17.63#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.23:11:17.65#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.23:11:17.69#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.23:11:17.69#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.23:11:17.69#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.23:11:17.69#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.23:11:17.69$vck44/va=4,7 2006.145.23:11:17.69#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.23:11:17.69#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.23:11:17.69#ibcon#ireg 11 cls_cnt 2 2006.145.23:11:17.69#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.23:11:17.75#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.23:11:17.75#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.23:11:17.77#ibcon#[25=AT04-07\r\n] 2006.145.23:11:17.80#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.23:11:17.80#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.23:11:17.80#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.23:11:17.80#ibcon#ireg 7 cls_cnt 0 2006.145.23:11:17.80#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.23:11:17.92#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.23:11:17.92#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.23:11:17.94#ibcon#[25=USB\r\n] 2006.145.23:11:17.97#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.23:11:17.97#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.23:11:17.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.23:11:17.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.23:11:17.97$vck44/valo=5,734.99 2006.145.23:11:17.97#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.23:11:17.97#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.23:11:17.97#ibcon#ireg 17 cls_cnt 0 2006.145.23:11:17.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.23:11:17.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.23:11:17.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.23:11:17.99#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.23:11:18.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.23:11:18.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.23:11:18.03#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.23:11:18.03#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.23:11:18.03$vck44/va=5,4 2006.145.23:11:18.03#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.23:11:18.03#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.23:11:18.03#ibcon#ireg 11 cls_cnt 2 2006.145.23:11:18.03#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.23:11:18.09#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.23:11:18.09#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.23:11:18.11#ibcon#[25=AT05-04\r\n] 2006.145.23:11:18.14#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.23:11:18.14#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.23:11:18.14#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.23:11:18.14#ibcon#ireg 7 cls_cnt 0 2006.145.23:11:18.14#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.23:11:18.26#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.23:11:18.26#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.23:11:18.28#ibcon#[25=USB\r\n] 2006.145.23:11:18.31#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.23:11:18.31#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.23:11:18.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.23:11:18.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.23:11:18.31$vck44/valo=6,814.99 2006.145.23:11:18.31#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.23:11:18.31#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.23:11:18.31#ibcon#ireg 17 cls_cnt 0 2006.145.23:11:18.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.23:11:18.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.23:11:18.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.23:11:18.33#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.23:11:18.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.23:11:18.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.23:11:18.37#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.23:11:18.37#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.23:11:18.37$vck44/va=6,4 2006.145.23:11:18.37#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.23:11:18.37#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.23:11:18.37#ibcon#ireg 11 cls_cnt 2 2006.145.23:11:18.37#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.23:11:18.43#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.23:11:18.43#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.23:11:18.45#ibcon#[25=AT06-04\r\n] 2006.145.23:11:18.48#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.23:11:18.48#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.23:11:18.48#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.23:11:18.48#ibcon#ireg 7 cls_cnt 0 2006.145.23:11:18.48#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.23:11:18.60#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.23:11:18.60#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.23:11:18.62#ibcon#[25=USB\r\n] 2006.145.23:11:18.65#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.23:11:18.65#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.23:11:18.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.23:11:18.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.23:11:18.65$vck44/valo=7,864.99 2006.145.23:11:18.65#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.23:11:18.65#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.23:11:18.65#ibcon#ireg 17 cls_cnt 0 2006.145.23:11:18.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.23:11:18.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.23:11:18.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.23:11:18.67#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.23:11:18.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.23:11:18.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.23:11:18.71#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.23:11:18.71#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.23:11:18.71$vck44/va=7,4 2006.145.23:11:18.71#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.23:11:18.71#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.23:11:18.71#ibcon#ireg 11 cls_cnt 2 2006.145.23:11:18.71#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.23:11:18.77#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.23:11:18.77#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.23:11:18.79#ibcon#[25=AT07-04\r\n] 2006.145.23:11:18.82#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.23:11:18.82#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.23:11:18.82#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.23:11:18.82#ibcon#ireg 7 cls_cnt 0 2006.145.23:11:18.82#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.23:11:18.94#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.23:11:18.94#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.23:11:18.96#ibcon#[25=USB\r\n] 2006.145.23:11:18.99#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.23:11:18.99#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.23:11:18.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.23:11:18.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.23:11:18.99$vck44/valo=8,884.99 2006.145.23:11:18.99#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.23:11:18.99#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.23:11:18.99#ibcon#ireg 17 cls_cnt 0 2006.145.23:11:18.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.23:11:18.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.23:11:18.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.23:11:19.01#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.23:11:19.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.23:11:19.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.23:11:19.05#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.23:11:19.05#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.23:11:19.05$vck44/va=8,4 2006.145.23:11:19.05#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.23:11:19.05#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.23:11:19.05#ibcon#ireg 11 cls_cnt 2 2006.145.23:11:19.05#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.23:11:19.11#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.23:11:19.11#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.23:11:19.13#ibcon#[25=AT08-04\r\n] 2006.145.23:11:19.16#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.23:11:19.16#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.23:11:19.16#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.23:11:19.16#ibcon#ireg 7 cls_cnt 0 2006.145.23:11:19.16#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.23:11:19.28#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.23:11:19.28#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.23:11:19.31#ibcon#[25=USB\r\n] 2006.145.23:11:19.35#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.23:11:19.35#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.23:11:19.35#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.23:11:19.35#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.23:11:19.35$vck44/vblo=1,629.99 2006.145.23:11:19.35#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.23:11:19.35#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.23:11:19.35#ibcon#ireg 17 cls_cnt 0 2006.145.23:11:19.35#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.23:11:19.35#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.23:11:19.35#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.23:11:19.37#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.23:11:19.41#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.23:11:19.41#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.23:11:19.41#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.23:11:19.41#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.23:11:19.41$vck44/vb=1,3 2006.145.23:11:19.41#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.23:11:19.41#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.23:11:19.41#ibcon#ireg 11 cls_cnt 2 2006.145.23:11:19.41#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.23:11:19.41#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.23:11:19.41#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.23:11:19.43#ibcon#[27=AT01-03\r\n] 2006.145.23:11:19.46#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.23:11:19.46#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.23:11:19.46#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.23:11:19.46#ibcon#ireg 7 cls_cnt 0 2006.145.23:11:19.46#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.23:11:19.58#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.23:11:19.58#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.23:11:19.60#ibcon#[27=USB\r\n] 2006.145.23:11:19.63#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.23:11:19.63#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.23:11:19.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.23:11:19.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.23:11:19.63$vck44/vblo=2,634.99 2006.145.23:11:19.63#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.23:11:19.63#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.23:11:19.63#ibcon#ireg 17 cls_cnt 0 2006.145.23:11:19.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.23:11:19.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.23:11:19.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.23:11:19.65#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.23:11:19.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.23:11:19.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.23:11:19.69#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.23:11:19.69#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.23:11:19.69$vck44/vb=2,4 2006.145.23:11:19.69#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.23:11:19.69#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.23:11:19.69#ibcon#ireg 11 cls_cnt 2 2006.145.23:11:19.69#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.23:11:19.75#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.23:11:19.75#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.23:11:19.77#ibcon#[27=AT02-04\r\n] 2006.145.23:11:19.80#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.23:11:19.80#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.23:11:19.80#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.23:11:19.80#ibcon#ireg 7 cls_cnt 0 2006.145.23:11:19.80#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.23:11:19.92#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.23:11:19.92#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.23:11:19.94#ibcon#[27=USB\r\n] 2006.145.23:11:19.97#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.23:11:19.97#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.23:11:19.97#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.23:11:19.97#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.23:11:19.97$vck44/vblo=3,649.99 2006.145.23:11:19.97#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.23:11:19.97#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.23:11:19.97#ibcon#ireg 17 cls_cnt 0 2006.145.23:11:19.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.23:11:19.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.23:11:19.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.23:11:19.99#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.23:11:20.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.23:11:20.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.23:11:20.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.23:11:20.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.23:11:20.03$vck44/vb=3,4 2006.145.23:11:20.03#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.23:11:20.03#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.23:11:20.03#ibcon#ireg 11 cls_cnt 2 2006.145.23:11:20.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.23:11:20.09#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.23:11:20.09#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.23:11:20.11#ibcon#[27=AT03-04\r\n] 2006.145.23:11:20.14#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.23:11:20.14#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.23:11:20.14#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.23:11:20.14#ibcon#ireg 7 cls_cnt 0 2006.145.23:11:20.14#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.23:11:20.26#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.23:11:20.26#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.23:11:20.28#ibcon#[27=USB\r\n] 2006.145.23:11:20.31#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.23:11:20.31#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.23:11:20.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.23:11:20.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.23:11:20.31$vck44/vblo=4,679.99 2006.145.23:11:20.31#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.23:11:20.31#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.23:11:20.31#ibcon#ireg 17 cls_cnt 0 2006.145.23:11:20.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.23:11:20.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.23:11:20.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.23:11:20.33#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.23:11:20.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.23:11:20.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.23:11:20.37#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.23:11:20.37#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.23:11:20.37$vck44/vb=4,4 2006.145.23:11:20.37#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.23:11:20.37#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.23:11:20.37#ibcon#ireg 11 cls_cnt 2 2006.145.23:11:20.37#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.23:11:20.43#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.23:11:20.43#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.23:11:20.45#ibcon#[27=AT04-04\r\n] 2006.145.23:11:20.48#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.23:11:20.48#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.23:11:20.48#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.23:11:20.48#ibcon#ireg 7 cls_cnt 0 2006.145.23:11:20.48#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.23:11:20.60#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.23:11:20.60#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.23:11:20.62#ibcon#[27=USB\r\n] 2006.145.23:11:20.65#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.23:11:20.65#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.23:11:20.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.23:11:20.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.23:11:20.65$vck44/vblo=5,709.99 2006.145.23:11:20.65#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.23:11:20.65#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.23:11:20.65#ibcon#ireg 17 cls_cnt 0 2006.145.23:11:20.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.23:11:20.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.23:11:20.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.23:11:20.67#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.23:11:20.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.23:11:20.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.23:11:20.71#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.23:11:20.71#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.23:11:20.71$vck44/vb=5,4 2006.145.23:11:20.71#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.23:11:20.71#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.23:11:20.71#ibcon#ireg 11 cls_cnt 2 2006.145.23:11:20.71#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.23:11:20.77#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.23:11:20.77#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.23:11:20.79#ibcon#[27=AT05-04\r\n] 2006.145.23:11:20.82#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.23:11:20.82#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.23:11:20.82#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.23:11:20.82#ibcon#ireg 7 cls_cnt 0 2006.145.23:11:20.82#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.23:11:20.94#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.23:11:20.94#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.23:11:20.96#ibcon#[27=USB\r\n] 2006.145.23:11:20.99#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.23:11:20.99#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.23:11:20.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.23:11:20.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.23:11:20.99$vck44/vblo=6,719.99 2006.145.23:11:20.99#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.23:11:20.99#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.23:11:20.99#ibcon#ireg 17 cls_cnt 0 2006.145.23:11:20.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.23:11:20.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.23:11:20.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.23:11:21.01#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.23:11:21.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.23:11:21.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.23:11:21.05#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.23:11:21.05#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.23:11:21.05$vck44/vb=6,4 2006.145.23:11:21.05#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.23:11:21.05#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.23:11:21.05#ibcon#ireg 11 cls_cnt 2 2006.145.23:11:21.05#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.23:11:21.11#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.23:11:21.11#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.23:11:21.13#ibcon#[27=AT06-04\r\n] 2006.145.23:11:21.16#abcon#<5=/08 1.2 4.0 18.58 761021.0\r\n> 2006.145.23:11:21.16#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.23:11:21.16#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.23:11:21.16#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.23:11:21.16#ibcon#ireg 7 cls_cnt 0 2006.145.23:11:21.16#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.23:11:21.18#abcon#{5=INTERFACE CLEAR} 2006.145.23:11:21.24#abcon#[5=S1D000X0/0*\r\n] 2006.145.23:11:21.28#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.23:11:21.28#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.23:11:21.30#ibcon#[27=USB\r\n] 2006.145.23:11:21.33#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.23:11:21.33#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.23:11:21.33#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.23:11:21.33#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.23:11:21.33$vck44/vblo=7,734.99 2006.145.23:11:21.33#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.23:11:21.33#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.23:11:21.33#ibcon#ireg 17 cls_cnt 0 2006.145.23:11:21.33#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.23:11:21.33#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.23:11:21.33#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.23:11:21.35#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.23:11:21.39#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.23:11:21.39#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.23:11:21.39#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.23:11:21.39#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.23:11:21.39$vck44/vb=7,4 2006.145.23:11:21.39#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.23:11:21.39#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.23:11:21.39#ibcon#ireg 11 cls_cnt 2 2006.145.23:11:21.39#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.23:11:21.45#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.23:11:21.45#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.23:11:21.47#ibcon#[27=AT07-04\r\n] 2006.145.23:11:21.50#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.23:11:21.50#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.23:11:21.50#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.23:11:21.50#ibcon#ireg 7 cls_cnt 0 2006.145.23:11:21.50#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.23:11:21.62#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.23:11:21.62#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.23:11:21.64#ibcon#[27=USB\r\n] 2006.145.23:11:21.67#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.23:11:21.67#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.23:11:21.67#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.23:11:21.67#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.23:11:21.67$vck44/vblo=8,744.99 2006.145.23:11:21.67#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.23:11:21.67#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.23:11:21.67#ibcon#ireg 17 cls_cnt 0 2006.145.23:11:21.67#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.23:11:21.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.23:11:21.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.23:11:21.69#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.23:11:21.73#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.23:11:21.73#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.23:11:21.73#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.23:11:21.73#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.23:11:21.73$vck44/vb=8,4 2006.145.23:11:21.73#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.23:11:21.73#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.23:11:21.73#ibcon#ireg 11 cls_cnt 2 2006.145.23:11:21.73#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.23:11:21.79#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.23:11:21.79#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.23:11:21.81#ibcon#[27=AT08-04\r\n] 2006.145.23:11:21.84#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.23:11:21.84#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.23:11:21.84#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.23:11:21.84#ibcon#ireg 7 cls_cnt 0 2006.145.23:11:21.84#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.23:11:21.96#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.23:11:21.96#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.23:11:21.98#ibcon#[27=USB\r\n] 2006.145.23:11:22.01#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.23:11:22.01#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.23:11:22.01#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.23:11:22.01#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.23:11:22.01$vck44/vabw=wide 2006.145.23:11:22.01#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.23:11:22.01#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.23:11:22.01#ibcon#ireg 8 cls_cnt 0 2006.145.23:11:22.01#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.23:11:22.01#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.23:11:22.01#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.23:11:22.03#ibcon#[25=BW32\r\n] 2006.145.23:11:22.06#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.23:11:22.06#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.23:11:22.06#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.23:11:22.06#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.23:11:22.06$vck44/vbbw=wide 2006.145.23:11:22.06#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.23:11:22.06#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.23:11:22.06#ibcon#ireg 8 cls_cnt 0 2006.145.23:11:22.06#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.23:11:22.13#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.23:11:22.13#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.23:11:22.15#ibcon#[27=BW32\r\n] 2006.145.23:11:22.18#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.23:11:22.18#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.23:11:22.18#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.23:11:22.18#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.23:11:22.18$setupk4/ifdk4 2006.145.23:11:22.18$ifdk4/lo= 2006.145.23:11:22.18$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.23:11:22.18$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.23:11:22.18$ifdk4/patch= 2006.145.23:11:22.18$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.23:11:22.18$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.23:11:22.18$setupk4/!*+20s 2006.145.23:11:31.33#abcon#<5=/08 1.2 4.0 18.58 761021.0\r\n> 2006.145.23:11:31.35#abcon#{5=INTERFACE CLEAR} 2006.145.23:11:31.41#abcon#[5=S1D000X0/0*\r\n] 2006.145.23:11:36.64$setupk4/"tpicd 2006.145.23:11:36.64$setupk4/echo=off 2006.145.23:11:36.64$setupk4/xlog=off 2006.145.23:11:36.64:!2006.145.23:20:08 2006.145.23:11:51.13#trakl#Source acquired 2006.145.23:11:53.13#flagr#flagr/antenna,acquired 2006.145.23:20:08.01:preob 2006.145.23:20:09.13/onsource/TRACKING 2006.145.23:20:09.14:!2006.145.23:20:18 2006.145.23:20:18.01:"tape 2006.145.23:20:18.01:"st=record 2006.145.23:20:18.02:data_valid=on 2006.145.23:20:18.02:midob 2006.145.23:20:19.13/onsource/TRACKING 2006.145.23:20:19.14/wx/18.81,1020.9,77 2006.145.23:20:19.25/cable/+6.5493E-03 2006.145.23:20:20.34/va/01,08,usb,yes,29,31 2006.145.23:20:20.34/va/02,07,usb,yes,31,32 2006.145.23:20:20.34/va/03,08,usb,yes,28,29 2006.145.23:20:20.34/va/04,07,usb,yes,32,33 2006.145.23:20:20.34/va/05,04,usb,yes,28,28 2006.145.23:20:20.34/va/06,04,usb,yes,31,31 2006.145.23:20:20.34/va/07,04,usb,yes,31,33 2006.145.23:20:20.34/va/08,04,usb,yes,27,32 2006.145.23:20:20.57/valo/01,524.99,yes,locked 2006.145.23:20:20.57/valo/02,534.99,yes,locked 2006.145.23:20:20.57/valo/03,564.99,yes,locked 2006.145.23:20:20.57/valo/04,624.99,yes,locked 2006.145.23:20:20.57/valo/05,734.99,yes,locked 2006.145.23:20:20.57/valo/06,814.99,yes,locked 2006.145.23:20:20.57/valo/07,864.99,yes,locked 2006.145.23:20:20.57/valo/08,884.99,yes,locked 2006.145.23:20:21.66/vb/01,03,usb,yes,37,34 2006.145.23:20:21.66/vb/02,04,usb,yes,32,32 2006.145.23:20:21.66/vb/03,04,usb,yes,28,32 2006.145.23:20:21.66/vb/04,04,usb,yes,33,32 2006.145.23:20:21.66/vb/05,04,usb,yes,25,28 2006.145.23:20:21.66/vb/06,04,usb,yes,30,26 2006.145.23:20:21.66/vb/07,04,usb,yes,29,29 2006.145.23:20:21.66/vb/08,04,usb,yes,27,30 2006.145.23:20:21.89/vblo/01,629.99,yes,locked 2006.145.23:20:21.89/vblo/02,634.99,yes,locked 2006.145.23:20:21.89/vblo/03,649.99,yes,locked 2006.145.23:20:21.89/vblo/04,679.99,yes,locked 2006.145.23:20:21.89/vblo/05,709.99,yes,locked 2006.145.23:20:21.89/vblo/06,719.99,yes,locked 2006.145.23:20:21.89/vblo/07,734.99,yes,locked 2006.145.23:20:21.89/vblo/08,744.99,yes,locked 2006.145.23:20:22.04/vabw/8 2006.145.23:20:22.19/vbbw/8 2006.145.23:20:22.40/xfe/off,on,15.0 2006.145.23:20:22.79/ifatt/23,28,28,28 2006.145.23:20:23.07/fmout-gps/S +3.8E-08 2006.145.23:20:23.12:!2006.145.23:23:28 2006.145.23:23:28.01:data_valid=off 2006.145.23:23:28.02:"et 2006.145.23:23:28.02:!+3s 2006.145.23:23:31.05:"tape 2006.145.23:23:31.06:postob 2006.145.23:23:31.14/cable/+6.5484E-03 2006.145.23:23:31.14/wx/18.90,1020.8,74 2006.145.23:23:31.22/fmout-gps/S +3.9E-08 2006.145.23:23:31.22:scan_name=145-2326,jd0605,70 2006.145.23:23:31.23:source=2136+141,213901.31,142336.0,2000.0,cw 2006.145.23:23:32.14#flagr#flagr/antenna,new-source 2006.145.23:23:32.15:checkk5 2006.145.23:23:32.59/chk_autoobs//k5ts1/ autoobs is running! 2006.145.23:23:33.04/chk_autoobs//k5ts2/ autoobs is running! 2006.145.23:23:33.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.23:23:33.91/chk_autoobs//k5ts4/ autoobs is running! 2006.145.23:23:34.33/chk_obsdata//k5ts1/T1452320??a.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.23:23:34.78/chk_obsdata//k5ts2/T1452320??b.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.23:23:35.22/chk_obsdata//k5ts3/T1452320??c.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.23:23:35.68/chk_obsdata//k5ts4/T1452320??d.dat file size is correct (nominal:760MB, actual:756MB). 2006.145.23:23:36.48/k5log//k5ts1_log_newline 2006.145.23:23:37.22/k5log//k5ts2_log_newline 2006.145.23:23:37.96/k5log//k5ts3_log_newline 2006.145.23:23:38.71/k5log//k5ts4_log_newline 2006.145.23:23:38.73/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.23:23:38.73:setupk4=1 2006.145.23:23:38.73$setupk4/echo=on 2006.145.23:23:38.73$setupk4/pcalon 2006.145.23:23:38.73$pcalon/"no phase cal control is implemented here 2006.145.23:23:38.73$setupk4/"tpicd=stop 2006.145.23:23:38.73$setupk4/"rec=synch_on 2006.145.23:23:38.73$setupk4/"rec_mode=128 2006.145.23:23:38.73$setupk4/!* 2006.145.23:23:38.73$setupk4/recpk4 2006.145.23:23:38.73$recpk4/recpatch= 2006.145.23:23:38.74$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.23:23:38.74$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.23:23:38.74$setupk4/vck44 2006.145.23:23:38.74$vck44/valo=1,524.99 2006.145.23:23:38.74#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.23:23:38.74#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.23:23:38.74#ibcon#ireg 17 cls_cnt 0 2006.145.23:23:38.74#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.23:23:38.74#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.23:23:38.74#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.23:23:38.78#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.23:23:38.82#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.23:23:38.82#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.23:23:38.82#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.23:23:38.82#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.23:23:38.82$vck44/va=1,8 2006.145.23:23:38.82#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.23:23:38.82#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.23:23:38.82#ibcon#ireg 11 cls_cnt 2 2006.145.23:23:38.82#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.23:23:38.82#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.23:23:38.82#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.23:23:38.84#ibcon#[25=AT01-08\r\n] 2006.145.23:23:38.87#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.23:23:38.87#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.23:23:38.87#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.23:23:38.87#ibcon#ireg 7 cls_cnt 0 2006.145.23:23:38.87#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.23:23:38.99#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.23:23:38.99#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.23:23:39.01#ibcon#[25=USB\r\n] 2006.145.23:23:39.06#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.23:23:39.06#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.23:23:39.06#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.23:23:39.06#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.23:23:39.06$vck44/valo=2,534.99 2006.145.23:23:39.06#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.23:23:39.06#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.23:23:39.06#ibcon#ireg 17 cls_cnt 0 2006.145.23:23:39.06#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.23:23:39.06#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.23:23:39.06#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.23:23:39.07#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.23:23:39.11#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.23:23:39.11#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.23:23:39.11#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.23:23:39.11#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.23:23:39.11$vck44/va=2,7 2006.145.23:23:39.11#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.23:23:39.11#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.23:23:39.11#ibcon#ireg 11 cls_cnt 2 2006.145.23:23:39.11#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.23:23:39.18#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.23:23:39.18#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.23:23:39.20#ibcon#[25=AT02-07\r\n] 2006.145.23:23:39.23#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.23:23:39.23#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.23:23:39.23#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.23:23:39.23#ibcon#ireg 7 cls_cnt 0 2006.145.23:23:39.23#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.23:23:39.35#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.23:23:39.35#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.23:23:39.37#ibcon#[25=USB\r\n] 2006.145.23:23:39.40#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.23:23:39.40#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.23:23:39.40#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.23:23:39.40#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.23:23:39.40$vck44/valo=3,564.99 2006.145.23:23:39.40#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.23:23:39.40#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.23:23:39.40#ibcon#ireg 17 cls_cnt 0 2006.145.23:23:39.40#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.23:23:39.40#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.23:23:39.40#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.23:23:39.42#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.23:23:39.46#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.23:23:39.46#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.23:23:39.46#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.23:23:39.46#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.23:23:39.46$vck44/va=3,8 2006.145.23:23:39.46#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.23:23:39.46#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.23:23:39.46#ibcon#ireg 11 cls_cnt 2 2006.145.23:23:39.46#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.23:23:39.52#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.23:23:39.52#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.23:23:39.54#ibcon#[25=AT03-08\r\n] 2006.145.23:23:39.57#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.23:23:39.57#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.23:23:39.57#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.23:23:39.57#ibcon#ireg 7 cls_cnt 0 2006.145.23:23:39.57#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.23:23:39.69#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.23:23:39.69#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.23:23:39.71#ibcon#[25=USB\r\n] 2006.145.23:23:39.74#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.23:23:39.74#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.23:23:39.74#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.23:23:39.74#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.23:23:39.74$vck44/valo=4,624.99 2006.145.23:23:39.74#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.23:23:39.74#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.23:23:39.74#ibcon#ireg 17 cls_cnt 0 2006.145.23:23:39.74#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.23:23:39.74#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.23:23:39.74#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.23:23:39.76#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.23:23:39.80#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.23:23:39.80#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.23:23:39.80#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.23:23:39.80#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.23:23:39.80$vck44/va=4,7 2006.145.23:23:39.80#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.23:23:39.80#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.23:23:39.80#ibcon#ireg 11 cls_cnt 2 2006.145.23:23:39.80#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.23:23:39.86#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.23:23:39.86#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.23:23:39.88#ibcon#[25=AT04-07\r\n] 2006.145.23:23:39.91#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.23:23:39.91#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.23:23:39.91#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.23:23:39.91#ibcon#ireg 7 cls_cnt 0 2006.145.23:23:39.91#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.23:23:40.03#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.23:23:40.03#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.23:23:40.05#ibcon#[25=USB\r\n] 2006.145.23:23:40.08#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.23:23:40.08#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.23:23:40.08#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.23:23:40.08#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.23:23:40.08$vck44/valo=5,734.99 2006.145.23:23:40.08#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.23:23:40.08#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.23:23:40.08#ibcon#ireg 17 cls_cnt 0 2006.145.23:23:40.08#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.23:23:40.08#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.23:23:40.08#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.23:23:40.10#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.23:23:40.15#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.23:23:40.15#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.23:23:40.15#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.23:23:40.15#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.23:23:40.15$vck44/va=5,4 2006.145.23:23:40.15#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.23:23:40.15#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.23:23:40.15#ibcon#ireg 11 cls_cnt 2 2006.145.23:23:40.15#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.23:23:40.19#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.23:23:40.19#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.23:23:40.21#ibcon#[25=AT05-04\r\n] 2006.145.23:23:40.25#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.23:23:40.25#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.23:23:40.25#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.23:23:40.25#ibcon#ireg 7 cls_cnt 0 2006.145.23:23:40.25#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.23:23:40.36#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.23:23:40.36#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.23:23:40.38#ibcon#[25=USB\r\n] 2006.145.23:23:40.44#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.23:23:40.44#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.23:23:40.44#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.23:23:40.44#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.23:23:40.44$vck44/valo=6,814.99 2006.145.23:23:40.44#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.23:23:40.44#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.23:23:40.44#ibcon#ireg 17 cls_cnt 0 2006.145.23:23:40.44#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.23:23:40.44#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.23:23:40.44#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.23:23:40.45#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.23:23:40.49#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.23:23:40.49#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.23:23:40.49#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.23:23:40.49#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.23:23:40.49$vck44/va=6,4 2006.145.23:23:40.49#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.23:23:40.49#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.23:23:40.49#ibcon#ireg 11 cls_cnt 2 2006.145.23:23:40.49#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.23:23:40.56#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.23:23:40.56#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.23:23:40.58#ibcon#[25=AT06-04\r\n] 2006.145.23:23:40.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.23:23:40.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.23:23:40.61#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.23:23:40.61#ibcon#ireg 7 cls_cnt 0 2006.145.23:23:40.61#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.23:23:40.73#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.23:23:40.73#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.23:23:40.75#ibcon#[25=USB\r\n] 2006.145.23:23:40.78#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.23:23:40.78#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.23:23:40.78#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.23:23:40.78#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.23:23:40.78$vck44/valo=7,864.99 2006.145.23:23:40.78#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.23:23:40.78#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.23:23:40.78#ibcon#ireg 17 cls_cnt 0 2006.145.23:23:40.78#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.23:23:40.78#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.23:23:40.78#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.23:23:40.80#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.23:23:40.84#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.23:23:40.84#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.23:23:40.84#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.23:23:40.84#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.23:23:40.84$vck44/va=7,4 2006.145.23:23:40.84#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.23:23:40.84#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.23:23:40.84#ibcon#ireg 11 cls_cnt 2 2006.145.23:23:40.84#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.23:23:40.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.23:23:40.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.23:23:40.92#ibcon#[25=AT07-04\r\n] 2006.145.23:23:40.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.23:23:40.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.23:23:40.95#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.23:23:40.95#ibcon#ireg 7 cls_cnt 0 2006.145.23:23:40.95#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.23:23:41.07#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.23:23:41.07#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.23:23:41.09#ibcon#[25=USB\r\n] 2006.145.23:23:41.12#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.23:23:41.12#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.23:23:41.12#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.23:23:41.12#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.23:23:41.12$vck44/valo=8,884.99 2006.145.23:23:41.12#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.23:23:41.12#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.23:23:41.12#ibcon#ireg 17 cls_cnt 0 2006.145.23:23:41.12#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.23:23:41.12#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.23:23:41.12#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.23:23:41.14#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.23:23:41.18#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.23:23:41.18#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.23:23:41.18#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.23:23:41.18#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.23:23:41.18$vck44/va=8,4 2006.145.23:23:41.18#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.23:23:41.18#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.23:23:41.18#ibcon#ireg 11 cls_cnt 2 2006.145.23:23:41.18#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.23:23:41.24#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.23:23:41.24#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.23:23:41.26#ibcon#[25=AT08-04\r\n] 2006.145.23:23:41.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.23:23:41.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.23:23:41.29#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.23:23:41.29#ibcon#ireg 7 cls_cnt 0 2006.145.23:23:41.29#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.23:23:41.41#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.23:23:41.41#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.23:23:41.43#ibcon#[25=USB\r\n] 2006.145.23:23:41.46#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.23:23:41.46#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.23:23:41.46#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.23:23:41.46#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.23:23:41.46$vck44/vblo=1,629.99 2006.145.23:23:41.46#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.23:23:41.46#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.23:23:41.46#ibcon#ireg 17 cls_cnt 0 2006.145.23:23:41.46#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.23:23:41.46#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.23:23:41.46#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.23:23:41.48#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.23:23:41.52#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.23:23:41.52#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.23:23:41.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.23:23:41.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.23:23:41.52$vck44/vb=1,3 2006.145.23:23:41.52#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.23:23:41.52#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.23:23:41.52#ibcon#ireg 11 cls_cnt 2 2006.145.23:23:41.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.23:23:41.52#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.23:23:41.52#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.23:23:41.54#ibcon#[27=AT01-03\r\n] 2006.145.23:23:41.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.23:23:41.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.23:23:41.57#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.23:23:41.57#ibcon#ireg 7 cls_cnt 0 2006.145.23:23:41.57#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.23:23:41.69#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.23:23:41.69#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.23:23:41.71#ibcon#[27=USB\r\n] 2006.145.23:23:41.74#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.23:23:41.74#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.23:23:41.74#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.23:23:41.74#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.23:23:41.74$vck44/vblo=2,634.99 2006.145.23:23:41.74#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.23:23:41.74#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.23:23:41.74#ibcon#ireg 17 cls_cnt 0 2006.145.23:23:41.74#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.23:23:41.74#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.23:23:41.74#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.23:23:41.76#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.23:23:41.80#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.23:23:41.80#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.23:23:41.80#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.23:23:41.80#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.23:23:41.80$vck44/vb=2,4 2006.145.23:23:41.80#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.23:23:41.80#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.23:23:41.80#ibcon#ireg 11 cls_cnt 2 2006.145.23:23:41.80#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.23:23:41.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.23:23:41.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.23:23:41.88#ibcon#[27=AT02-04\r\n] 2006.145.23:23:41.91#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.23:23:41.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.23:23:41.91#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.23:23:41.91#ibcon#ireg 7 cls_cnt 0 2006.145.23:23:41.91#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.23:23:42.03#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.23:23:42.03#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.23:23:42.05#ibcon#[27=USB\r\n] 2006.145.23:23:42.08#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.23:23:42.08#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.23:23:42.08#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.23:23:42.08#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.23:23:42.08$vck44/vblo=3,649.99 2006.145.23:23:42.08#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.23:23:42.08#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.23:23:42.08#ibcon#ireg 17 cls_cnt 0 2006.145.23:23:42.08#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.23:23:42.08#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.23:23:42.08#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.23:23:42.10#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.23:23:42.14#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.23:23:42.14#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.23:23:42.14#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.23:23:42.14#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.23:23:42.14$vck44/vb=3,4 2006.145.23:23:42.14#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.23:23:42.14#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.23:23:42.14#ibcon#ireg 11 cls_cnt 2 2006.145.23:23:42.14#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.23:23:42.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.23:23:42.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.23:23:42.22#ibcon#[27=AT03-04\r\n] 2006.145.23:23:42.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.23:23:42.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.23:23:42.25#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.23:23:42.25#ibcon#ireg 7 cls_cnt 0 2006.145.23:23:42.25#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.23:23:42.37#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.23:23:42.37#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.23:23:42.39#ibcon#[27=USB\r\n] 2006.145.23:23:42.42#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.23:23:42.42#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.23:23:42.42#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.23:23:42.42#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.23:23:42.42$vck44/vblo=4,679.99 2006.145.23:23:42.42#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.23:23:42.42#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.23:23:42.42#ibcon#ireg 17 cls_cnt 0 2006.145.23:23:42.42#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.23:23:42.42#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.23:23:42.42#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.23:23:42.44#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.23:23:42.48#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.23:23:42.48#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.23:23:42.48#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.23:23:42.48#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.23:23:42.48$vck44/vb=4,4 2006.145.23:23:42.48#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.23:23:42.48#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.23:23:42.48#ibcon#ireg 11 cls_cnt 2 2006.145.23:23:42.48#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.23:23:42.54#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.23:23:42.54#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.23:23:42.56#ibcon#[27=AT04-04\r\n] 2006.145.23:23:42.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.23:23:42.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.23:23:42.59#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.23:23:42.59#ibcon#ireg 7 cls_cnt 0 2006.145.23:23:42.59#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.23:23:42.71#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.23:23:42.71#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.23:23:42.73#ibcon#[27=USB\r\n] 2006.145.23:23:42.76#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.23:23:42.76#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.23:23:42.76#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.23:23:42.76#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.23:23:42.76$vck44/vblo=5,709.99 2006.145.23:23:42.76#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.23:23:42.76#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.23:23:42.76#ibcon#ireg 17 cls_cnt 0 2006.145.23:23:42.76#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.23:23:42.76#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.23:23:42.76#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.23:23:42.78#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.23:23:42.82#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.23:23:42.82#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.23:23:42.82#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.23:23:42.82#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.23:23:42.82$vck44/vb=5,4 2006.145.23:23:42.82#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.23:23:42.82#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.23:23:42.82#ibcon#ireg 11 cls_cnt 2 2006.145.23:23:42.82#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.23:23:42.88#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.23:23:42.88#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.23:23:42.90#ibcon#[27=AT05-04\r\n] 2006.145.23:23:42.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.23:23:42.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.23:23:42.93#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.23:23:42.93#ibcon#ireg 7 cls_cnt 0 2006.145.23:23:42.93#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.23:23:43.05#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.23:23:43.05#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.23:23:43.07#ibcon#[27=USB\r\n] 2006.145.23:23:43.10#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.23:23:43.10#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.23:23:43.10#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.23:23:43.10#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.23:23:43.10$vck44/vblo=6,719.99 2006.145.23:23:43.10#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.23:23:43.10#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.23:23:43.10#ibcon#ireg 17 cls_cnt 0 2006.145.23:23:43.10#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.23:23:43.10#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.23:23:43.10#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.23:23:43.14#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.23:23:43.17#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.23:23:43.17#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.23:23:43.17#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.23:23:43.17#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.23:23:43.17$vck44/vb=6,4 2006.145.23:23:43.17#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.23:23:43.17#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.23:23:43.17#ibcon#ireg 11 cls_cnt 2 2006.145.23:23:43.17#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.23:23:43.22#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.23:23:43.22#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.23:23:43.24#ibcon#[27=AT06-04\r\n] 2006.145.23:23:43.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.23:23:43.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.23:23:43.27#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.23:23:43.27#ibcon#ireg 7 cls_cnt 0 2006.145.23:23:43.27#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.23:23:43.39#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.23:23:43.39#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.23:23:43.41#ibcon#[27=USB\r\n] 2006.145.23:23:43.44#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.23:23:43.44#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.23:23:43.44#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.23:23:43.44#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.23:23:43.44$vck44/vblo=7,734.99 2006.145.23:23:43.44#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.23:23:43.44#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.23:23:43.44#ibcon#ireg 17 cls_cnt 0 2006.145.23:23:43.44#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.23:23:43.44#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.23:23:43.44#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.23:23:43.46#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.23:23:43.50#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.23:23:43.50#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.23:23:43.50#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.23:23:43.50#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.23:23:43.50$vck44/vb=7,4 2006.145.23:23:43.50#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.23:23:43.50#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.23:23:43.50#ibcon#ireg 11 cls_cnt 2 2006.145.23:23:43.50#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.23:23:43.56#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.23:23:43.56#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.23:23:43.58#ibcon#[27=AT07-04\r\n] 2006.145.23:23:43.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.23:23:43.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.23:23:43.61#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.23:23:43.61#ibcon#ireg 7 cls_cnt 0 2006.145.23:23:43.61#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.23:23:43.73#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.23:23:43.73#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.23:23:43.75#ibcon#[27=USB\r\n] 2006.145.23:23:43.78#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.23:23:43.78#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.23:23:43.78#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.23:23:43.78#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.23:23:43.78$vck44/vblo=8,744.99 2006.145.23:23:43.78#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.23:23:43.78#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.23:23:43.78#ibcon#ireg 17 cls_cnt 0 2006.145.23:23:43.78#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.23:23:43.78#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.23:23:43.78#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.23:23:43.80#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.23:23:43.84#abcon#<5=/08 1.3 4.5 18.91 741020.8\r\n> 2006.145.23:23:43.84#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.23:23:43.84#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.23:23:43.84#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.23:23:43.84#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.23:23:43.84$vck44/vb=8,4 2006.145.23:23:43.84#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.23:23:43.84#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.23:23:43.84#ibcon#ireg 11 cls_cnt 2 2006.145.23:23:43.84#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.23:23:43.86#abcon#{5=INTERFACE CLEAR} 2006.145.23:23:43.90#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.23:23:43.90#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.23:23:43.92#ibcon#[27=AT08-04\r\n] 2006.145.23:23:43.92#abcon#[5=S1D000X0/0*\r\n] 2006.145.23:23:43.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.23:23:43.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.23:23:43.95#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.23:23:43.95#ibcon#ireg 7 cls_cnt 0 2006.145.23:23:43.95#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.23:23:44.07#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.23:23:44.07#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.23:23:44.09#ibcon#[27=USB\r\n] 2006.145.23:23:44.12#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.23:23:44.12#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.23:23:44.12#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.23:23:44.12#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.23:23:44.12$vck44/vabw=wide 2006.145.23:23:44.12#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.23:23:44.12#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.23:23:44.12#ibcon#ireg 8 cls_cnt 0 2006.145.23:23:44.12#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.23:23:44.12#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.23:23:44.12#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.23:23:44.14#ibcon#[25=BW32\r\n] 2006.145.23:23:44.17#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.23:23:44.17#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.23:23:44.17#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.23:23:44.17#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.23:23:44.17$vck44/vbbw=wide 2006.145.23:23:44.17#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.23:23:44.17#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.23:23:44.17#ibcon#ireg 8 cls_cnt 0 2006.145.23:23:44.17#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.23:23:44.24#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.23:23:44.24#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.23:23:44.26#ibcon#[27=BW32\r\n] 2006.145.23:23:44.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.23:23:44.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.23:23:44.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.23:23:44.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.23:23:44.29$setupk4/ifdk4 2006.145.23:23:44.29$ifdk4/lo= 2006.145.23:23:44.29$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.23:23:44.29$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.23:23:44.29$ifdk4/patch= 2006.145.23:23:44.29$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.23:23:44.29$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.23:23:44.30$setupk4/!*+20s 2006.145.23:23:50.14#trakl#Source acquired 2006.145.23:23:52.14#flagr#flagr/antenna,acquired 2006.145.23:23:54.01#abcon#<5=/08 1.4 5.5 18.92 731020.8\r\n> 2006.145.23:23:54.03#abcon#{5=INTERFACE CLEAR} 2006.145.23:23:54.09#abcon#[5=S1D000X0/0*\r\n] 2006.145.23:23:58.75$setupk4/"tpicd 2006.145.23:23:58.75$setupk4/echo=off 2006.145.23:23:58.75$setupk4/xlog=off 2006.145.23:23:58.75:!2006.145.23:25:54 2006.145.23:25:54.00:preob 2006.145.23:25:54.14/onsource/TRACKING 2006.145.23:25:54.14:!2006.145.23:26:04 2006.145.23:26:04.00:"tape 2006.145.23:26:04.00:"st=record 2006.145.23:26:04.00:data_valid=on 2006.145.23:26:04.00:midob 2006.145.23:26:04.14/onsource/TRACKING 2006.145.23:26:04.14/wx/18.96,1020.7,73 2006.145.23:26:04.36/cable/+6.5482E-03 2006.145.23:26:05.45/va/01,08,usb,yes,28,31 2006.145.23:26:05.45/va/02,07,usb,yes,30,31 2006.145.23:26:05.45/va/03,08,usb,yes,28,29 2006.145.23:26:05.45/va/04,07,usb,yes,31,33 2006.145.23:26:05.45/va/05,04,usb,yes,27,28 2006.145.23:26:05.45/va/06,04,usb,yes,31,31 2006.145.23:26:05.45/va/07,04,usb,yes,31,32 2006.145.23:26:05.45/va/08,04,usb,yes,26,32 2006.145.23:26:05.68/valo/01,524.99,yes,locked 2006.145.23:26:05.68/valo/02,534.99,yes,locked 2006.145.23:26:05.68/valo/03,564.99,yes,locked 2006.145.23:26:05.68/valo/04,624.99,yes,locked 2006.145.23:26:05.68/valo/05,734.99,yes,locked 2006.145.23:26:05.68/valo/06,814.99,yes,locked 2006.145.23:26:05.68/valo/07,864.99,yes,locked 2006.145.23:26:05.68/valo/08,884.99,yes,locked 2006.145.23:26:06.77/vb/01,03,usb,yes,36,33 2006.145.23:26:06.77/vb/02,04,usb,yes,31,31 2006.145.23:26:06.77/vb/03,04,usb,yes,28,31 2006.145.23:26:06.77/vb/04,04,usb,yes,33,32 2006.145.23:26:06.77/vb/05,04,usb,yes,25,28 2006.145.23:26:06.77/vb/06,04,usb,yes,30,26 2006.145.23:26:06.77/vb/07,04,usb,yes,29,29 2006.145.23:26:06.77/vb/08,04,usb,yes,27,30 2006.145.23:26:07.00/vblo/01,629.99,yes,locked 2006.145.23:26:07.00/vblo/02,634.99,yes,locked 2006.145.23:26:07.00/vblo/03,649.99,yes,locked 2006.145.23:26:07.00/vblo/04,679.99,yes,locked 2006.145.23:26:07.00/vblo/05,709.99,yes,locked 2006.145.23:26:07.00/vblo/06,719.99,yes,locked 2006.145.23:26:07.00/vblo/07,734.99,yes,locked 2006.145.23:26:07.00/vblo/08,744.99,yes,locked 2006.145.23:26:07.15/vabw/8 2006.145.23:26:07.30/vbbw/8 2006.145.23:26:07.39/xfe/off,on,14.0 2006.145.23:26:07.77/ifatt/23,28,28,28 2006.145.23:26:08.07/fmout-gps/S +3.9E-08 2006.145.23:26:08.15:!2006.145.23:27:14 2006.145.23:27:14.01:data_valid=off 2006.145.23:27:14.02:"et 2006.145.23:27:14.02:!+3s 2006.145.23:27:17.03:"tape 2006.145.23:27:17.04:postob 2006.145.23:27:17.17/cable/+6.5494E-03 2006.145.23:27:17.18/wx/18.99,1020.7,75 2006.145.23:27:17.27/fmout-gps/S +4.0E-08 2006.145.23:27:17.27:scan_name=145-2331,jd0605,120 2006.145.23:27:17.28:source=2201+315,220314.98,314538.3,2000.0,cw 2006.145.23:27:19.14#flagr#flagr/antenna,new-source 2006.145.23:27:19.15:checkk5 2006.145.23:27:19.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.23:27:20.03/chk_autoobs//k5ts2/ autoobs is running! 2006.145.23:27:20.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.23:27:20.89/chk_autoobs//k5ts4/ autoobs is running! 2006.145.23:27:21.31/chk_obsdata//k5ts1/T1452326??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.23:27:21.73/chk_obsdata//k5ts2/T1452326??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.23:27:22.16/chk_obsdata//k5ts3/T1452326??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.23:27:22.60/chk_obsdata//k5ts4/T1452326??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.145.23:27:23.36/k5log//k5ts1_log_newline 2006.145.23:27:24.10/k5log//k5ts2_log_newline 2006.145.23:27:24.83/k5log//k5ts3_log_newline 2006.145.23:27:25.59/k5log//k5ts4_log_newline 2006.145.23:27:25.62/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.23:27:25.62:setupk4=1 2006.145.23:27:25.62$setupk4/echo=on 2006.145.23:27:25.62$setupk4/pcalon 2006.145.23:27:25.62$pcalon/"no phase cal control is implemented here 2006.145.23:27:25.62$setupk4/"tpicd=stop 2006.145.23:27:25.62$setupk4/"rec=synch_on 2006.145.23:27:25.62$setupk4/"rec_mode=128 2006.145.23:27:25.62$setupk4/!* 2006.145.23:27:25.62$setupk4/recpk4 2006.145.23:27:25.62$recpk4/recpatch= 2006.145.23:27:25.62$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.23:27:25.62$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.23:27:25.62$setupk4/vck44 2006.145.23:27:25.62$vck44/valo=1,524.99 2006.145.23:27:25.62#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.23:27:25.62#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.23:27:25.62#ibcon#ireg 17 cls_cnt 0 2006.145.23:27:25.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.23:27:25.62#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.23:27:25.62#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.23:27:25.63#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.23:27:25.68#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.23:27:25.68#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.23:27:25.68#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.23:27:25.68#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.23:27:25.68$vck44/va=1,8 2006.145.23:27:25.68#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.23:27:25.68#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.23:27:25.68#ibcon#ireg 11 cls_cnt 2 2006.145.23:27:25.68#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.23:27:25.68#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.23:27:25.68#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.23:27:25.70#ibcon#[25=AT01-08\r\n] 2006.145.23:27:25.73#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.23:27:25.73#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.23:27:25.73#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.23:27:25.73#ibcon#ireg 7 cls_cnt 0 2006.145.23:27:25.73#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.23:27:25.85#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.23:27:25.85#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.23:27:25.87#ibcon#[25=USB\r\n] 2006.145.23:27:25.90#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.23:27:25.90#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.23:27:25.90#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.23:27:25.90#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.23:27:25.90$vck44/valo=2,534.99 2006.145.23:27:25.90#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.23:27:25.90#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.23:27:25.90#ibcon#ireg 17 cls_cnt 0 2006.145.23:27:25.90#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.23:27:25.90#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.23:27:25.90#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.23:27:25.94#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.23:27:25.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.23:27:25.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.23:27:25.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.23:27:25.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.23:27:25.97$vck44/va=2,7 2006.145.23:27:25.97#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.23:27:25.97#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.23:27:25.97#ibcon#ireg 11 cls_cnt 2 2006.145.23:27:25.97#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.23:27:26.03#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.23:27:26.03#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.23:27:26.04#ibcon#[25=AT02-07\r\n] 2006.145.23:27:26.07#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.23:27:26.07#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.23:27:26.07#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.23:27:26.07#ibcon#ireg 7 cls_cnt 0 2006.145.23:27:26.07#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.23:27:26.19#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.23:27:26.19#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.23:27:26.21#ibcon#[25=USB\r\n] 2006.145.23:27:26.24#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.23:27:26.24#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.23:27:26.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.23:27:26.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.23:27:26.24$vck44/valo=3,564.99 2006.145.23:27:26.24#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.23:27:26.24#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.23:27:26.24#ibcon#ireg 17 cls_cnt 0 2006.145.23:27:26.24#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.23:27:26.24#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.23:27:26.24#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.23:27:26.26#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.23:27:26.30#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.23:27:26.30#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.23:27:26.30#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.23:27:26.30#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.23:27:26.30$vck44/va=3,8 2006.145.23:27:26.30#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.23:27:26.30#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.23:27:26.30#ibcon#ireg 11 cls_cnt 2 2006.145.23:27:26.30#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.23:27:26.36#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.23:27:26.36#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.23:27:26.38#ibcon#[25=AT03-08\r\n] 2006.145.23:27:26.41#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.23:27:26.41#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.23:27:26.41#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.23:27:26.41#ibcon#ireg 7 cls_cnt 0 2006.145.23:27:26.41#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.23:27:26.53#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.23:27:26.53#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.23:27:26.55#ibcon#[25=USB\r\n] 2006.145.23:27:26.58#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.23:27:26.58#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.23:27:26.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.23:27:26.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.23:27:26.58$vck44/valo=4,624.99 2006.145.23:27:26.58#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.23:27:26.58#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.23:27:26.58#ibcon#ireg 17 cls_cnt 0 2006.145.23:27:26.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.23:27:26.58#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.23:27:26.58#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.23:27:26.60#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.23:27:26.64#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.23:27:26.64#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.23:27:26.64#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.23:27:26.64#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.23:27:26.64$vck44/va=4,7 2006.145.23:27:26.64#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.23:27:26.64#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.23:27:26.64#ibcon#ireg 11 cls_cnt 2 2006.145.23:27:26.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.23:27:26.70#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.23:27:26.70#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.23:27:26.72#ibcon#[25=AT04-07\r\n] 2006.145.23:27:26.75#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.23:27:26.75#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.23:27:26.75#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.23:27:26.75#ibcon#ireg 7 cls_cnt 0 2006.145.23:27:26.75#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.23:27:26.87#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.23:27:26.87#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.23:27:26.89#ibcon#[25=USB\r\n] 2006.145.23:27:26.92#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.23:27:26.92#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.23:27:26.92#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.23:27:26.92#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.23:27:26.92$vck44/valo=5,734.99 2006.145.23:27:26.92#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.23:27:26.92#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.23:27:26.92#ibcon#ireg 17 cls_cnt 0 2006.145.23:27:26.92#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.23:27:26.92#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.23:27:26.92#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.23:27:26.94#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.23:27:26.98#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.23:27:26.98#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.23:27:26.98#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.23:27:26.98#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.23:27:26.98$vck44/va=5,4 2006.145.23:27:26.98#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.23:27:26.98#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.23:27:26.98#ibcon#ireg 11 cls_cnt 2 2006.145.23:27:26.98#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.23:27:27.04#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.23:27:27.04#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.23:27:27.06#ibcon#[25=AT05-04\r\n] 2006.145.23:27:27.09#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.23:27:27.09#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.23:27:27.09#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.23:27:27.09#ibcon#ireg 7 cls_cnt 0 2006.145.23:27:27.09#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.23:27:27.21#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.23:27:27.21#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.23:27:27.23#ibcon#[25=USB\r\n] 2006.145.23:27:27.26#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.23:27:27.26#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.23:27:27.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.23:27:27.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.23:27:27.26$vck44/valo=6,814.99 2006.145.23:27:27.26#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.23:27:27.26#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.23:27:27.26#ibcon#ireg 17 cls_cnt 0 2006.145.23:27:27.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.23:27:27.26#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.23:27:27.26#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.23:27:27.28#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.23:27:27.32#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.23:27:27.32#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.23:27:27.32#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.23:27:27.32#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.23:27:27.32$vck44/va=6,4 2006.145.23:27:27.32#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.23:27:27.32#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.23:27:27.32#ibcon#ireg 11 cls_cnt 2 2006.145.23:27:27.32#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.23:27:27.38#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.23:27:27.38#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.23:27:27.40#ibcon#[25=AT06-04\r\n] 2006.145.23:27:27.43#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.23:27:27.43#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.23:27:27.43#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.23:27:27.43#ibcon#ireg 7 cls_cnt 0 2006.145.23:27:27.43#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.23:27:27.55#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.23:27:27.55#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.23:27:27.57#ibcon#[25=USB\r\n] 2006.145.23:27:27.58#abcon#<5=/08 1.5 5.5 19.00 751020.6\r\n> 2006.145.23:27:27.60#abcon#{5=INTERFACE CLEAR} 2006.145.23:27:27.60#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.23:27:27.60#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.23:27:27.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.23:27:27.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.23:27:27.60$vck44/valo=7,864.99 2006.145.23:27:27.60#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.23:27:27.60#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.23:27:27.60#ibcon#ireg 17 cls_cnt 0 2006.145.23:27:27.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.23:27:27.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.23:27:27.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.23:27:27.62#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.23:27:27.66#abcon#[5=S1D000X0/0*\r\n] 2006.145.23:27:27.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.23:27:27.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.23:27:27.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.23:27:27.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.23:27:27.66$vck44/va=7,4 2006.145.23:27:27.66#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.23:27:27.66#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.23:27:27.66#ibcon#ireg 11 cls_cnt 2 2006.145.23:27:27.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.23:27:27.72#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.23:27:27.72#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.23:27:27.74#ibcon#[25=AT07-04\r\n] 2006.145.23:27:27.77#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.23:27:27.77#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.23:27:27.77#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.23:27:27.77#ibcon#ireg 7 cls_cnt 0 2006.145.23:27:27.77#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.23:27:27.89#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.23:27:27.89#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.23:27:27.91#ibcon#[25=USB\r\n] 2006.145.23:27:27.94#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.23:27:27.94#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.23:27:27.94#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.23:27:27.94#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.23:27:27.94$vck44/valo=8,884.99 2006.145.23:27:27.94#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.23:27:27.94#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.23:27:27.94#ibcon#ireg 17 cls_cnt 0 2006.145.23:27:27.94#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.23:27:27.94#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.23:27:27.94#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.23:27:27.96#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.23:27:28.00#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.23:27:28.00#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.23:27:28.00#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.23:27:28.00#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.23:27:28.00$vck44/va=8,4 2006.145.23:27:28.00#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.145.23:27:28.00#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.145.23:27:28.00#ibcon#ireg 11 cls_cnt 2 2006.145.23:27:28.00#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.23:27:28.06#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.145.23:27:28.06#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.23:27:28.08#ibcon#[25=AT08-04\r\n] 2006.145.23:27:28.11#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.145.23:27:28.11#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.145.23:27:28.11#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.145.23:27:28.11#ibcon#ireg 7 cls_cnt 0 2006.145.23:27:28.11#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.23:27:28.25#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.145.23:27:28.25#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.23:27:28.26#ibcon#[25=USB\r\n] 2006.145.23:27:28.29#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.145.23:27:28.29#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.145.23:27:28.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.23:27:28.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.23:27:28.29$vck44/vblo=1,629.99 2006.145.23:27:28.29#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.145.23:27:28.29#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.145.23:27:28.29#ibcon#ireg 17 cls_cnt 0 2006.145.23:27:28.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.23:27:28.29#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.145.23:27:28.29#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.23:27:28.31#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.23:27:28.35#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.145.23:27:28.35#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.145.23:27:28.35#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.23:27:28.35#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.23:27:28.35$vck44/vb=1,3 2006.145.23:27:28.36#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.145.23:27:28.36#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.145.23:27:28.36#ibcon#ireg 11 cls_cnt 2 2006.145.23:27:28.36#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.23:27:28.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.145.23:27:28.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.23:27:28.37#ibcon#[27=AT01-03\r\n] 2006.145.23:27:28.40#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.145.23:27:28.40#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.145.23:27:28.40#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.145.23:27:28.40#ibcon#ireg 7 cls_cnt 0 2006.145.23:27:28.40#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.23:27:28.52#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.145.23:27:28.52#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.23:27:28.54#ibcon#[27=USB\r\n] 2006.145.23:27:28.57#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.145.23:27:28.57#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.145.23:27:28.57#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.23:27:28.57#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.23:27:28.57$vck44/vblo=2,634.99 2006.145.23:27:28.57#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.145.23:27:28.57#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.145.23:27:28.57#ibcon#ireg 17 cls_cnt 0 2006.145.23:27:28.57#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.23:27:28.57#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.145.23:27:28.57#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.23:27:28.59#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.23:27:28.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.145.23:27:28.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.145.23:27:28.63#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.23:27:28.63#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.23:27:28.63$vck44/vb=2,4 2006.145.23:27:28.63#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.145.23:27:28.63#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.145.23:27:28.63#ibcon#ireg 11 cls_cnt 2 2006.145.23:27:28.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.23:27:28.69#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.145.23:27:28.69#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.23:27:28.71#ibcon#[27=AT02-04\r\n] 2006.145.23:27:28.74#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.145.23:27:28.74#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.145.23:27:28.74#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.145.23:27:28.74#ibcon#ireg 7 cls_cnt 0 2006.145.23:27:28.74#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.23:27:28.86#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.145.23:27:28.86#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.23:27:28.88#ibcon#[27=USB\r\n] 2006.145.23:27:28.91#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.145.23:27:28.91#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.145.23:27:28.91#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.23:27:28.91#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.23:27:28.91$vck44/vblo=3,649.99 2006.145.23:27:28.91#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.145.23:27:28.91#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.145.23:27:28.91#ibcon#ireg 17 cls_cnt 0 2006.145.23:27:28.91#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.23:27:28.91#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.145.23:27:28.91#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.23:27:28.93#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.23:27:28.97#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.145.23:27:28.97#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.145.23:27:28.97#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.23:27:28.97#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.23:27:28.97$vck44/vb=3,4 2006.145.23:27:28.97#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.145.23:27:28.97#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.145.23:27:28.97#ibcon#ireg 11 cls_cnt 2 2006.145.23:27:28.97#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.23:27:29.03#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.145.23:27:29.03#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.23:27:29.05#ibcon#[27=AT03-04\r\n] 2006.145.23:27:29.08#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.145.23:27:29.08#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.145.23:27:29.08#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.145.23:27:29.08#ibcon#ireg 7 cls_cnt 0 2006.145.23:27:29.08#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.23:27:29.20#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.145.23:27:29.20#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.23:27:29.22#ibcon#[27=USB\r\n] 2006.145.23:27:29.25#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.145.23:27:29.25#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.145.23:27:29.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.23:27:29.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.23:27:29.25$vck44/vblo=4,679.99 2006.145.23:27:29.25#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.145.23:27:29.25#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.145.23:27:29.25#ibcon#ireg 17 cls_cnt 0 2006.145.23:27:29.25#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.23:27:29.25#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.145.23:27:29.25#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.23:27:29.27#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.23:27:29.31#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.145.23:27:29.31#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.145.23:27:29.31#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.23:27:29.31#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.23:27:29.31$vck44/vb=4,4 2006.145.23:27:29.31#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.23:27:29.31#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.23:27:29.31#ibcon#ireg 11 cls_cnt 2 2006.145.23:27:29.31#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.23:27:29.37#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.23:27:29.37#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.23:27:29.39#ibcon#[27=AT04-04\r\n] 2006.145.23:27:29.42#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.23:27:29.42#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.23:27:29.42#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.23:27:29.42#ibcon#ireg 7 cls_cnt 0 2006.145.23:27:29.42#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.23:27:29.54#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.23:27:29.54#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.23:27:29.56#ibcon#[27=USB\r\n] 2006.145.23:27:29.59#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.23:27:29.59#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.23:27:29.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.23:27:29.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.23:27:29.59$vck44/vblo=5,709.99 2006.145.23:27:29.59#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.145.23:27:29.59#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.145.23:27:29.59#ibcon#ireg 17 cls_cnt 0 2006.145.23:27:29.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.23:27:29.59#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.145.23:27:29.59#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.23:27:29.61#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.23:27:29.65#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.145.23:27:29.65#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.145.23:27:29.65#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.23:27:29.65#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.23:27:29.65$vck44/vb=5,4 2006.145.23:27:29.65#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.145.23:27:29.65#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.145.23:27:29.65#ibcon#ireg 11 cls_cnt 2 2006.145.23:27:29.65#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.23:27:29.71#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.145.23:27:29.71#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.23:27:29.73#ibcon#[27=AT05-04\r\n] 2006.145.23:27:29.76#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.145.23:27:29.76#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.145.23:27:29.76#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.145.23:27:29.76#ibcon#ireg 7 cls_cnt 0 2006.145.23:27:29.76#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.23:27:29.88#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.145.23:27:29.88#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.23:27:29.90#ibcon#[27=USB\r\n] 2006.145.23:27:29.93#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.145.23:27:29.93#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.145.23:27:29.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.23:27:29.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.23:27:29.93$vck44/vblo=6,719.99 2006.145.23:27:29.93#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.145.23:27:29.93#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.145.23:27:29.93#ibcon#ireg 17 cls_cnt 0 2006.145.23:27:29.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.23:27:29.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.145.23:27:29.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.23:27:29.95#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.23:27:29.99#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.145.23:27:29.99#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.145.23:27:29.99#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.23:27:29.99#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.23:27:29.99$vck44/vb=6,4 2006.145.23:27:29.99#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.145.23:27:29.99#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.145.23:27:29.99#ibcon#ireg 11 cls_cnt 2 2006.145.23:27:29.99#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.23:27:30.05#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.145.23:27:30.05#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.23:27:30.07#ibcon#[27=AT06-04\r\n] 2006.145.23:27:30.10#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.145.23:27:30.10#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.145.23:27:30.10#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.145.23:27:30.10#ibcon#ireg 7 cls_cnt 0 2006.145.23:27:30.10#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.23:27:30.22#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.145.23:27:30.22#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.23:27:30.24#ibcon#[27=USB\r\n] 2006.145.23:27:30.27#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.145.23:27:30.27#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.145.23:27:30.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.23:27:30.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.23:27:30.27$vck44/vblo=7,734.99 2006.145.23:27:30.27#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.23:27:30.27#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.23:27:30.27#ibcon#ireg 17 cls_cnt 0 2006.145.23:27:30.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.23:27:30.27#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.23:27:30.27#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.23:27:30.29#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.23:27:30.33#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.23:27:30.33#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.23:27:30.33#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.23:27:30.33#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.23:27:30.33$vck44/vb=7,4 2006.145.23:27:30.33#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.145.23:27:30.33#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.145.23:27:30.33#ibcon#ireg 11 cls_cnt 2 2006.145.23:27:30.33#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.23:27:30.39#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.145.23:27:30.39#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.23:27:30.41#ibcon#[27=AT07-04\r\n] 2006.145.23:27:30.44#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.145.23:27:30.44#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.145.23:27:30.44#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.145.23:27:30.44#ibcon#ireg 7 cls_cnt 0 2006.145.23:27:30.44#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.23:27:30.56#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.145.23:27:30.56#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.23:27:30.58#ibcon#[27=USB\r\n] 2006.145.23:27:30.61#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.145.23:27:30.61#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.145.23:27:30.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.23:27:30.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.23:27:30.61$vck44/vblo=8,744.99 2006.145.23:27:30.61#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.145.23:27:30.61#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.145.23:27:30.61#ibcon#ireg 17 cls_cnt 0 2006.145.23:27:30.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.23:27:30.61#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.145.23:27:30.61#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.23:27:30.63#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.23:27:30.67#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.145.23:27:30.67#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.145.23:27:30.67#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.23:27:30.67#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.23:27:30.67$vck44/vb=8,4 2006.145.23:27:30.67#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.145.23:27:30.67#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.145.23:27:30.67#ibcon#ireg 11 cls_cnt 2 2006.145.23:27:30.67#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.23:27:30.73#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.145.23:27:30.73#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.23:27:30.75#ibcon#[27=AT08-04\r\n] 2006.145.23:27:30.78#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.145.23:27:30.78#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.145.23:27:30.78#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.145.23:27:30.78#ibcon#ireg 7 cls_cnt 0 2006.145.23:27:30.78#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.23:27:30.90#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.145.23:27:30.90#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.23:27:30.92#ibcon#[27=USB\r\n] 2006.145.23:27:30.95#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.145.23:27:30.95#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.145.23:27:30.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.23:27:30.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.23:27:30.95$vck44/vabw=wide 2006.145.23:27:30.95#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.145.23:27:30.95#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.145.23:27:30.95#ibcon#ireg 8 cls_cnt 0 2006.145.23:27:30.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.23:27:30.95#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.145.23:27:30.95#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.23:27:30.97#ibcon#[25=BW32\r\n] 2006.145.23:27:31.00#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.145.23:27:31.00#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.145.23:27:31.00#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.23:27:31.00#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.23:27:31.00$vck44/vbbw=wide 2006.145.23:27:31.00#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.23:27:31.00#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.23:27:31.00#ibcon#ireg 8 cls_cnt 0 2006.145.23:27:31.00#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.23:27:31.07#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.23:27:31.07#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.23:27:31.09#ibcon#[27=BW32\r\n] 2006.145.23:27:31.12#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.23:27:31.12#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.23:27:31.12#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.23:27:31.12#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.23:27:31.12$setupk4/ifdk4 2006.145.23:27:31.12$ifdk4/lo= 2006.145.23:27:31.12$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.23:27:31.12$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.23:27:31.12$ifdk4/patch= 2006.145.23:27:31.12$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.23:27:31.12$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.23:27:31.12$setupk4/!*+20s 2006.145.23:27:34.14#trakl#Source acquired 2006.145.23:27:35.14#flagr#flagr/antenna,acquired 2006.145.23:27:37.75#abcon#<5=/08 1.5 5.5 19.00 741020.6\r\n> 2006.145.23:27:37.77#abcon#{5=INTERFACE CLEAR} 2006.145.23:27:37.83#abcon#[5=S1D000X0/0*\r\n] 2006.145.23:27:45.63$setupk4/"tpicd 2006.145.23:27:45.63$setupk4/echo=off 2006.145.23:27:45.63$setupk4/xlog=off 2006.145.23:27:45.63:!2006.145.23:31:10 2006.145.23:31:10.00:preob 2006.145.23:31:10.14/onsource/TRACKING 2006.145.23:31:10.14:!2006.145.23:31:20 2006.145.23:31:20.00:"tape 2006.145.23:31:20.00:"st=record 2006.145.23:31:20.00:data_valid=on 2006.145.23:31:20.00:midob 2006.145.23:31:20.14/onsource/TRACKING 2006.145.23:31:20.14/wx/19.11,1020.6,77 2006.145.23:31:20.20/cable/+6.5453E-03 2006.145.23:31:21.29/va/01,08,usb,yes,28,30 2006.145.23:31:21.29/va/02,07,usb,yes,30,31 2006.145.23:31:21.29/va/03,08,usb,yes,27,28 2006.145.23:31:21.29/va/04,07,usb,yes,31,33 2006.145.23:31:21.29/va/05,04,usb,yes,27,28 2006.145.23:31:21.29/va/06,04,usb,yes,30,30 2006.145.23:31:21.29/va/07,04,usb,yes,31,32 2006.145.23:31:21.29/va/08,04,usb,yes,26,32 2006.145.23:31:21.52/valo/01,524.99,yes,locked 2006.145.23:31:21.52/valo/02,534.99,yes,locked 2006.145.23:31:21.52/valo/03,564.99,yes,locked 2006.145.23:31:21.52/valo/04,624.99,yes,locked 2006.145.23:31:21.52/valo/05,734.99,yes,locked 2006.145.23:31:21.52/valo/06,814.99,yes,locked 2006.145.23:31:21.52/valo/07,864.99,yes,locked 2006.145.23:31:21.52/valo/08,884.99,yes,locked 2006.145.23:31:22.61/vb/01,03,usb,yes,36,33 2006.145.23:31:22.61/vb/02,04,usb,yes,31,31 2006.145.23:31:22.61/vb/03,04,usb,yes,28,31 2006.145.23:31:22.61/vb/04,04,usb,yes,32,31 2006.145.23:31:22.61/vb/05,04,usb,yes,25,27 2006.145.23:31:22.61/vb/06,04,usb,yes,29,26 2006.145.23:31:22.61/vb/07,04,usb,yes,29,29 2006.145.23:31:22.61/vb/08,04,usb,yes,27,30 2006.145.23:31:22.84/vblo/01,629.99,yes,locked 2006.145.23:31:22.84/vblo/02,634.99,yes,locked 2006.145.23:31:22.84/vblo/03,649.99,yes,locked 2006.145.23:31:22.84/vblo/04,679.99,yes,locked 2006.145.23:31:22.84/vblo/05,709.99,yes,locked 2006.145.23:31:22.84/vblo/06,719.99,yes,locked 2006.145.23:31:22.84/vblo/07,734.99,yes,locked 2006.145.23:31:22.84/vblo/08,744.99,yes,locked 2006.145.23:31:22.99/vabw/8 2006.145.23:31:23.14/vbbw/8 2006.145.23:31:23.23/xfe/off,on,16.0 2006.145.23:31:23.60/ifatt/23,28,28,28 2006.145.23:31:24.07/fmout-gps/S +4.2E-08 2006.145.23:31:24.11:!2006.145.23:33:20 2006.145.23:33:20.01:data_valid=off 2006.145.23:33:20.02:"et 2006.145.23:33:20.02:!+3s 2006.145.23:33:23.03:"tape 2006.145.23:33:23.03:postob 2006.145.23:33:23.13/cable/+6.5476E-03 2006.145.23:33:23.14/wx/19.21,1020.6,78 2006.145.23:33:23.22/fmout-gps/S +4.2E-08 2006.145.23:33:23.22:scan_name=145-2340,jd0605,210 2006.145.23:33:23.22:source=1044+719,104827.62,714335.9,2000.0,cw 2006.145.23:33:24.14#flagr#flagr/antenna,new-source 2006.145.23:33:24.15:checkk5 2006.145.23:33:24.61/chk_autoobs//k5ts1/ autoobs is running! 2006.145.23:33:25.05/chk_autoobs//k5ts2/ autoobs is running! 2006.145.23:33:25.51/chk_autoobs//k5ts3/ autoobs is running! 2006.145.23:33:25.93/chk_autoobs//k5ts4/ autoobs is running! 2006.145.23:33:26.34/chk_obsdata//k5ts1/T1452331??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.23:33:26.77/chk_obsdata//k5ts2/T1452331??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.23:33:27.23/chk_obsdata//k5ts3/T1452331??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.23:33:27.69/chk_obsdata//k5ts4/T1452331??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.145.23:33:28.47/k5log//k5ts1_log_newline 2006.145.23:33:29.23/k5log//k5ts2_log_newline 2006.145.23:33:29.97/k5log//k5ts3_log_newline 2006.145.23:33:30.71/k5log//k5ts4_log_newline 2006.145.23:33:30.73/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.23:33:30.74:setupk4=1 2006.145.23:33:30.74$setupk4/echo=on 2006.145.23:33:30.74$setupk4/pcalon 2006.145.23:33:30.74$pcalon/"no phase cal control is implemented here 2006.145.23:33:30.74$setupk4/"tpicd=stop 2006.145.23:33:30.74$setupk4/"rec=synch_on 2006.145.23:33:30.74$setupk4/"rec_mode=128 2006.145.23:33:30.74$setupk4/!* 2006.145.23:33:30.74$setupk4/recpk4 2006.145.23:33:30.74$recpk4/recpatch= 2006.145.23:33:30.74$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.23:33:30.74$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.23:33:30.74$setupk4/vck44 2006.145.23:33:30.74$vck44/valo=1,524.99 2006.145.23:33:30.74#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.23:33:30.74#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.23:33:30.74#ibcon#ireg 17 cls_cnt 0 2006.145.23:33:30.74#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.23:33:30.75#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.23:33:30.75#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.23:33:30.78#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.23:33:30.83#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.23:33:30.83#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.23:33:30.83#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.23:33:30.83#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.23:33:30.83$vck44/va=1,8 2006.145.23:33:30.83#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.23:33:30.83#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.23:33:30.83#ibcon#ireg 11 cls_cnt 2 2006.145.23:33:30.83#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.23:33:30.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.23:33:30.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.23:33:30.85#ibcon#[25=AT01-08\r\n] 2006.145.23:33:30.88#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.23:33:30.88#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.23:33:30.88#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.23:33:30.88#ibcon#ireg 7 cls_cnt 0 2006.145.23:33:30.88#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.23:33:31.02#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.23:33:31.02#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.23:33:31.04#ibcon#[25=USB\r\n] 2006.145.23:33:31.07#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.23:33:31.07#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.23:33:31.07#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.23:33:31.07#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.23:33:31.07$vck44/valo=2,534.99 2006.145.23:33:31.07#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.145.23:33:31.07#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.145.23:33:31.07#ibcon#ireg 17 cls_cnt 0 2006.145.23:33:31.07#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.23:33:31.07#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.145.23:33:31.07#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.23:33:31.10#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.23:33:31.14#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.145.23:33:31.14#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.145.23:33:31.14#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.23:33:31.14#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.23:33:31.14$vck44/va=2,7 2006.145.23:33:31.14#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.145.23:33:31.14#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.145.23:33:31.14#ibcon#ireg 11 cls_cnt 2 2006.145.23:33:31.14#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.23:33:31.19#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.145.23:33:31.19#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.23:33:31.21#ibcon#[25=AT02-07\r\n] 2006.145.23:33:31.24#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.145.23:33:31.24#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.145.23:33:31.24#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.145.23:33:31.24#ibcon#ireg 7 cls_cnt 0 2006.145.23:33:31.24#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.23:33:31.36#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.145.23:33:31.36#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.23:33:31.38#ibcon#[25=USB\r\n] 2006.145.23:33:31.41#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.145.23:33:31.41#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.145.23:33:31.41#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.23:33:31.41#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.23:33:31.41$vck44/valo=3,564.99 2006.145.23:33:31.41#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.23:33:31.41#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.23:33:31.41#ibcon#ireg 17 cls_cnt 0 2006.145.23:33:31.41#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.23:33:31.41#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.23:33:31.41#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.23:33:31.43#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.23:33:31.47#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.23:33:31.47#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.23:33:31.47#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.23:33:31.47#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.23:33:31.47$vck44/va=3,8 2006.145.23:33:31.47#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.23:33:31.47#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.23:33:31.47#ibcon#ireg 11 cls_cnt 2 2006.145.23:33:31.47#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.23:33:31.53#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.23:33:31.53#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.23:33:31.55#ibcon#[25=AT03-08\r\n] 2006.145.23:33:31.58#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.23:33:31.58#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.23:33:31.58#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.23:33:31.58#ibcon#ireg 7 cls_cnt 0 2006.145.23:33:31.58#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.23:33:31.70#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.23:33:31.70#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.23:33:31.72#ibcon#[25=USB\r\n] 2006.145.23:33:31.75#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.23:33:31.75#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.23:33:31.75#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.23:33:31.75#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.23:33:31.75$vck44/valo=4,624.99 2006.145.23:33:31.75#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.23:33:31.75#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.23:33:31.75#ibcon#ireg 17 cls_cnt 0 2006.145.23:33:31.75#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.23:33:31.75#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.23:33:31.75#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.23:33:31.77#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.23:33:31.81#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.23:33:31.81#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.23:33:31.81#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.23:33:31.81#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.23:33:31.81$vck44/va=4,7 2006.145.23:33:31.81#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.23:33:31.81#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.23:33:31.81#ibcon#ireg 11 cls_cnt 2 2006.145.23:33:31.81#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.23:33:31.87#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.23:33:31.87#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.23:33:31.89#ibcon#[25=AT04-07\r\n] 2006.145.23:33:31.92#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.23:33:31.92#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.23:33:31.92#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.23:33:31.92#ibcon#ireg 7 cls_cnt 0 2006.145.23:33:31.92#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.23:33:32.04#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.23:33:32.04#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.23:33:32.06#ibcon#[25=USB\r\n] 2006.145.23:33:32.09#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.23:33:32.09#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.23:33:32.09#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.23:33:32.09#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.23:33:32.09$vck44/valo=5,734.99 2006.145.23:33:32.09#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.23:33:32.09#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.23:33:32.09#ibcon#ireg 17 cls_cnt 0 2006.145.23:33:32.09#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.23:33:32.09#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.23:33:32.09#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.23:33:32.11#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.23:33:32.15#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.23:33:32.15#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.23:33:32.15#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.23:33:32.15#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.23:33:32.15$vck44/va=5,4 2006.145.23:33:32.15#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.23:33:32.15#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.23:33:32.15#ibcon#ireg 11 cls_cnt 2 2006.145.23:33:32.15#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.23:33:32.21#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.23:33:32.21#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.23:33:32.23#ibcon#[25=AT05-04\r\n] 2006.145.23:33:32.26#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.23:33:32.26#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.23:33:32.26#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.23:33:32.26#ibcon#ireg 7 cls_cnt 0 2006.145.23:33:32.26#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.23:33:32.38#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.23:33:32.38#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.23:33:32.40#ibcon#[25=USB\r\n] 2006.145.23:33:32.43#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.23:33:32.43#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.23:33:32.43#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.23:33:32.43#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.23:33:32.43$vck44/valo=6,814.99 2006.145.23:33:32.43#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.23:33:32.43#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.23:33:32.43#ibcon#ireg 17 cls_cnt 0 2006.145.23:33:32.43#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.23:33:32.43#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.23:33:32.43#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.23:33:32.46#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.23:33:32.50#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.23:33:32.50#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.23:33:32.50#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.23:33:32.50#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.23:33:32.50$vck44/va=6,4 2006.145.23:33:32.50#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.23:33:32.50#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.23:33:32.50#ibcon#ireg 11 cls_cnt 2 2006.145.23:33:32.50#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.23:33:32.55#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.23:33:32.55#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.23:33:32.57#ibcon#[25=AT06-04\r\n] 2006.145.23:33:32.60#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.23:33:32.60#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.23:33:32.60#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.23:33:32.60#ibcon#ireg 7 cls_cnt 0 2006.145.23:33:32.60#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.23:33:32.72#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.23:33:32.72#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.23:33:32.74#ibcon#[25=USB\r\n] 2006.145.23:33:32.77#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.23:33:32.77#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.23:33:32.77#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.23:33:32.77#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.23:33:32.77$vck44/valo=7,864.99 2006.145.23:33:32.77#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.23:33:32.77#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.23:33:32.77#ibcon#ireg 17 cls_cnt 0 2006.145.23:33:32.77#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.23:33:32.77#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.23:33:32.77#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.23:33:32.79#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.23:33:32.83#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.23:33:32.83#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.23:33:32.83#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.23:33:32.83#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.23:33:32.83$vck44/va=7,4 2006.145.23:33:32.83#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.23:33:32.83#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.23:33:32.83#ibcon#ireg 11 cls_cnt 2 2006.145.23:33:32.83#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.23:33:32.89#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.23:33:32.89#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.23:33:32.91#ibcon#[25=AT07-04\r\n] 2006.145.23:33:32.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.23:33:32.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.23:33:32.94#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.23:33:32.94#ibcon#ireg 7 cls_cnt 0 2006.145.23:33:32.94#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.23:33:33.06#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.23:33:33.06#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.23:33:33.08#ibcon#[25=USB\r\n] 2006.145.23:33:33.11#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.23:33:33.11#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.23:33:33.11#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.23:33:33.11#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.23:33:33.11$vck44/valo=8,884.99 2006.145.23:33:33.11#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.23:33:33.11#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.23:33:33.11#ibcon#ireg 17 cls_cnt 0 2006.145.23:33:33.11#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.23:33:33.11#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.23:33:33.11#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.23:33:33.13#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.23:33:33.17#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.23:33:33.17#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.23:33:33.17#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.23:33:33.17#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.23:33:33.17$vck44/va=8,4 2006.145.23:33:33.17#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.23:33:33.17#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.23:33:33.17#ibcon#ireg 11 cls_cnt 2 2006.145.23:33:33.17#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.23:33:33.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.23:33:33.23#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.23:33:33.25#ibcon#[25=AT08-04\r\n] 2006.145.23:33:33.28#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.23:33:33.28#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.23:33:33.28#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.23:33:33.28#ibcon#ireg 7 cls_cnt 0 2006.145.23:33:33.28#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.23:33:33.40#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.23:33:33.40#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.23:33:33.42#ibcon#[25=USB\r\n] 2006.145.23:33:33.45#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.23:33:33.45#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.23:33:33.45#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.23:33:33.45#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.23:33:33.45$vck44/vblo=1,629.99 2006.145.23:33:33.45#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.23:33:33.45#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.23:33:33.45#ibcon#ireg 17 cls_cnt 0 2006.145.23:33:33.45#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.23:33:33.45#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.23:33:33.45#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.23:33:33.47#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.23:33:33.51#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.23:33:33.51#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.23:33:33.51#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.23:33:33.51#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.23:33:33.51$vck44/vb=1,3 2006.145.23:33:33.51#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.145.23:33:33.51#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.145.23:33:33.51#ibcon#ireg 11 cls_cnt 2 2006.145.23:33:33.51#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.23:33:33.51#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.145.23:33:33.51#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.23:33:33.53#ibcon#[27=AT01-03\r\n] 2006.145.23:33:33.56#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.145.23:33:33.56#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.145.23:33:33.56#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.145.23:33:33.56#ibcon#ireg 7 cls_cnt 0 2006.145.23:33:33.56#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.23:33:33.68#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.145.23:33:33.68#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.23:33:33.70#ibcon#[27=USB\r\n] 2006.145.23:33:33.73#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.145.23:33:33.73#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.145.23:33:33.73#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.23:33:33.73#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.23:33:33.73$vck44/vblo=2,634.99 2006.145.23:33:33.73#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.23:33:33.73#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.23:33:33.73#ibcon#ireg 17 cls_cnt 0 2006.145.23:33:33.73#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.23:33:33.73#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.23:33:33.73#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.23:33:33.75#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.23:33:33.79#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.23:33:33.79#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.23:33:33.79#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.23:33:33.79#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.23:33:33.79$vck44/vb=2,4 2006.145.23:33:33.79#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.145.23:33:33.79#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.145.23:33:33.79#ibcon#ireg 11 cls_cnt 2 2006.145.23:33:33.79#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.23:33:33.84#abcon#<5=/08 1.5 5.5 19.23 751020.6\r\n> 2006.145.23:33:33.85#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.145.23:33:33.85#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.23:33:33.86#abcon#{5=INTERFACE CLEAR} 2006.145.23:33:33.87#ibcon#[27=AT02-04\r\n] 2006.145.23:33:33.90#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.145.23:33:33.90#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.145.23:33:33.90#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.145.23:33:33.90#ibcon#ireg 7 cls_cnt 0 2006.145.23:33:33.90#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.23:33:33.92#abcon#[5=S1D000X0/0*\r\n] 2006.145.23:33:34.02#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.145.23:33:34.02#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.23:33:34.04#ibcon#[27=USB\r\n] 2006.145.23:33:34.07#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.145.23:33:34.07#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.145.23:33:34.07#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.23:33:34.07#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.23:33:34.07$vck44/vblo=3,649.99 2006.145.23:33:34.07#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.145.23:33:34.07#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.145.23:33:34.07#ibcon#ireg 17 cls_cnt 0 2006.145.23:33:34.07#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.23:33:34.07#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.145.23:33:34.07#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.23:33:34.09#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.23:33:34.13#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.145.23:33:34.13#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.145.23:33:34.13#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.23:33:34.13#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.23:33:34.13$vck44/vb=3,4 2006.145.23:33:34.13#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.145.23:33:34.13#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.145.23:33:34.13#ibcon#ireg 11 cls_cnt 2 2006.145.23:33:34.13#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.23:33:34.19#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.145.23:33:34.19#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.23:33:34.21#ibcon#[27=AT03-04\r\n] 2006.145.23:33:34.24#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.145.23:33:34.24#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.145.23:33:34.24#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.145.23:33:34.24#ibcon#ireg 7 cls_cnt 0 2006.145.23:33:34.24#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.23:33:34.36#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.145.23:33:34.36#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.23:33:34.38#ibcon#[27=USB\r\n] 2006.145.23:33:34.41#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.145.23:33:34.41#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.145.23:33:34.41#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.23:33:34.41#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.23:33:34.41$vck44/vblo=4,679.99 2006.145.23:33:34.41#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.145.23:33:34.41#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.145.23:33:34.41#ibcon#ireg 17 cls_cnt 0 2006.145.23:33:34.41#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.23:33:34.41#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.145.23:33:34.41#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.23:33:34.43#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.23:33:34.47#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.145.23:33:34.47#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.145.23:33:34.47#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.23:33:34.47#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.23:33:34.47$vck44/vb=4,4 2006.145.23:33:34.47#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.145.23:33:34.47#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.145.23:33:34.47#ibcon#ireg 11 cls_cnt 2 2006.145.23:33:34.47#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.23:33:34.53#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.145.23:33:34.53#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.23:33:34.55#ibcon#[27=AT04-04\r\n] 2006.145.23:33:34.58#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.145.23:33:34.58#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.145.23:33:34.58#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.145.23:33:34.58#ibcon#ireg 7 cls_cnt 0 2006.145.23:33:34.58#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.23:33:34.70#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.145.23:33:34.70#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.23:33:34.72#ibcon#[27=USB\r\n] 2006.145.23:33:34.75#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.145.23:33:34.75#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.145.23:33:34.75#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.23:33:34.75#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.23:33:34.75$vck44/vblo=5,709.99 2006.145.23:33:34.75#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.145.23:33:34.75#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.145.23:33:34.75#ibcon#ireg 17 cls_cnt 0 2006.145.23:33:34.75#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.23:33:34.75#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.145.23:33:34.75#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.23:33:34.77#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.23:33:34.81#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.145.23:33:34.81#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.145.23:33:34.81#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.23:33:34.81#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.23:33:34.81$vck44/vb=5,4 2006.145.23:33:34.81#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.145.23:33:34.81#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.145.23:33:34.81#ibcon#ireg 11 cls_cnt 2 2006.145.23:33:34.81#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.23:33:34.87#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.145.23:33:34.87#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.23:33:34.89#ibcon#[27=AT05-04\r\n] 2006.145.23:33:34.92#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.145.23:33:34.92#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.145.23:33:34.92#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.145.23:33:34.92#ibcon#ireg 7 cls_cnt 0 2006.145.23:33:34.92#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.23:33:35.04#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.145.23:33:35.04#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.23:33:35.06#ibcon#[27=USB\r\n] 2006.145.23:33:35.09#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.145.23:33:35.09#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.145.23:33:35.09#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.23:33:35.09#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.23:33:35.09$vck44/vblo=6,719.99 2006.145.23:33:35.09#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.145.23:33:35.09#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.145.23:33:35.09#ibcon#ireg 17 cls_cnt 0 2006.145.23:33:35.09#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.23:33:35.09#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.145.23:33:35.09#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.23:33:35.11#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.23:33:35.15#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.145.23:33:35.15#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.145.23:33:35.15#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.23:33:35.15#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.23:33:35.15$vck44/vb=6,4 2006.145.23:33:35.15#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.145.23:33:35.15#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.145.23:33:35.15#ibcon#ireg 11 cls_cnt 2 2006.145.23:33:35.15#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.23:33:35.21#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.145.23:33:35.21#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.23:33:35.23#ibcon#[27=AT06-04\r\n] 2006.145.23:33:35.26#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.145.23:33:35.26#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.145.23:33:35.26#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.145.23:33:35.26#ibcon#ireg 7 cls_cnt 0 2006.145.23:33:35.26#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.23:33:35.38#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.145.23:33:35.38#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.23:33:35.40#ibcon#[27=USB\r\n] 2006.145.23:33:35.43#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.145.23:33:35.43#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.145.23:33:35.43#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.23:33:35.43#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.23:33:35.43$vck44/vblo=7,734.99 2006.145.23:33:35.43#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.23:33:35.43#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.23:33:35.43#ibcon#ireg 17 cls_cnt 0 2006.145.23:33:35.43#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.23:33:35.43#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.23:33:35.43#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.23:33:35.45#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.23:33:35.49#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.23:33:35.49#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.23:33:35.49#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.23:33:35.49#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.23:33:35.49$vck44/vb=7,4 2006.145.23:33:35.49#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.145.23:33:35.49#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.145.23:33:35.49#ibcon#ireg 11 cls_cnt 2 2006.145.23:33:35.49#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.23:33:35.55#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.145.23:33:35.55#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.23:33:35.57#ibcon#[27=AT07-04\r\n] 2006.145.23:33:35.60#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.145.23:33:35.60#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.145.23:33:35.60#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.145.23:33:35.60#ibcon#ireg 7 cls_cnt 0 2006.145.23:33:35.60#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.23:33:35.72#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.145.23:33:35.72#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.23:33:35.74#ibcon#[27=USB\r\n] 2006.145.23:33:35.77#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.145.23:33:35.77#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.145.23:33:35.77#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.23:33:35.77#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.23:33:35.77$vck44/vblo=8,744.99 2006.145.23:33:35.77#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.145.23:33:35.77#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.145.23:33:35.77#ibcon#ireg 17 cls_cnt 0 2006.145.23:33:35.77#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.23:33:35.77#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.145.23:33:35.77#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.23:33:35.79#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.23:33:35.83#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.145.23:33:35.83#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.145.23:33:35.83#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.23:33:35.83#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.23:33:35.83$vck44/vb=8,4 2006.145.23:33:35.83#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.145.23:33:35.83#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.145.23:33:35.83#ibcon#ireg 11 cls_cnt 2 2006.145.23:33:35.83#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.23:33:35.89#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.145.23:33:35.89#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.23:33:35.91#ibcon#[27=AT08-04\r\n] 2006.145.23:33:35.94#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.145.23:33:35.94#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.145.23:33:35.94#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.145.23:33:35.94#ibcon#ireg 7 cls_cnt 0 2006.145.23:33:35.94#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.23:33:36.06#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.145.23:33:36.06#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.23:33:36.08#ibcon#[27=USB\r\n] 2006.145.23:33:36.11#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.145.23:33:36.11#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.145.23:33:36.11#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.23:33:36.11#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.23:33:36.11$vck44/vabw=wide 2006.145.23:33:36.11#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.145.23:33:36.11#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.145.23:33:36.11#ibcon#ireg 8 cls_cnt 0 2006.145.23:33:36.11#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.23:33:36.11#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.145.23:33:36.11#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.23:33:36.13#ibcon#[25=BW32\r\n] 2006.145.23:33:36.16#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.145.23:33:36.16#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.145.23:33:36.16#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.23:33:36.16#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.23:33:36.16$vck44/vbbw=wide 2006.145.23:33:36.16#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.23:33:36.16#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.23:33:36.16#ibcon#ireg 8 cls_cnt 0 2006.145.23:33:36.16#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.23:33:36.23#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.23:33:36.23#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.23:33:36.25#ibcon#[27=BW32\r\n] 2006.145.23:33:36.28#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.23:33:36.28#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.23:33:36.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.23:33:36.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.23:33:36.28$setupk4/ifdk4 2006.145.23:33:36.28$ifdk4/lo= 2006.145.23:33:36.28$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.23:33:36.28$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.23:33:36.28$ifdk4/patch= 2006.145.23:33:36.28$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.23:33:36.28$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.23:33:36.28$setupk4/!*+20s 2006.145.23:33:44.01#abcon#<5=/08 1.5 5.5 19.24 751020.5\r\n> 2006.145.23:33:44.03#abcon#{5=INTERFACE CLEAR} 2006.145.23:33:44.09#abcon#[5=S1D000X0/0*\r\n] 2006.145.23:33:50.75$setupk4/"tpicd 2006.145.23:33:50.75$setupk4/echo=off 2006.145.23:33:50.75$setupk4/xlog=off 2006.145.23:33:50.75:!2006.145.23:40:03 2006.145.23:34:58.14#trakl#Source acquired 2006.145.23:34:59.14#flagr#flagr/antenna,acquired 2006.145.23:40:03.00:preob 2006.145.23:40:03.14/onsource/TRACKING 2006.145.23:40:03.14:!2006.145.23:40:13 2006.145.23:40:13.00:"tape 2006.145.23:40:13.00:"st=record 2006.145.23:40:13.00:data_valid=on 2006.145.23:40:13.00:midob 2006.145.23:40:14.14/onsource/TRACKING 2006.145.23:40:14.14/wx/19.51,1020.4,76 2006.145.23:40:14.37/cable/+6.5488E-03 2006.145.23:40:15.46/va/01,08,usb,yes,30,32 2006.145.23:40:15.46/va/02,07,usb,yes,32,33 2006.145.23:40:15.46/va/03,08,usb,yes,29,30 2006.145.23:40:15.46/va/04,07,usb,yes,33,35 2006.145.23:40:15.46/va/05,04,usb,yes,29,29 2006.145.23:40:15.46/va/06,04,usb,yes,32,32 2006.145.23:40:15.46/va/07,04,usb,yes,33,34 2006.145.23:40:15.46/va/08,04,usb,yes,28,33 2006.145.23:40:15.69/valo/01,524.99,yes,locked 2006.145.23:40:15.69/valo/02,534.99,yes,locked 2006.145.23:40:15.69/valo/03,564.99,yes,locked 2006.145.23:40:15.69/valo/04,624.99,yes,locked 2006.145.23:40:15.69/valo/05,734.99,yes,locked 2006.145.23:40:15.69/valo/06,814.99,yes,locked 2006.145.23:40:15.69/valo/07,864.99,yes,locked 2006.145.23:40:15.69/valo/08,884.99,yes,locked 2006.145.23:40:16.78/vb/01,03,usb,yes,36,34 2006.145.23:40:16.78/vb/02,04,usb,yes,32,32 2006.145.23:40:16.78/vb/03,04,usb,yes,29,32 2006.145.23:40:16.78/vb/04,04,usb,yes,33,32 2006.145.23:40:16.78/vb/05,04,usb,yes,26,28 2006.145.23:40:16.78/vb/06,04,usb,yes,30,26 2006.145.23:40:16.78/vb/07,04,usb,yes,30,30 2006.145.23:40:16.78/vb/08,04,usb,yes,27,31 2006.145.23:40:17.01/vblo/01,629.99,yes,locked 2006.145.23:40:17.01/vblo/02,634.99,yes,locked 2006.145.23:40:17.01/vblo/03,649.99,yes,locked 2006.145.23:40:17.01/vblo/04,679.99,yes,locked 2006.145.23:40:17.01/vblo/05,709.99,yes,locked 2006.145.23:40:17.01/vblo/06,719.99,yes,locked 2006.145.23:40:17.01/vblo/07,734.99,yes,locked 2006.145.23:40:17.01/vblo/08,744.99,yes,locked 2006.145.23:40:17.16/vabw/8 2006.145.23:40:17.31/vbbw/8 2006.145.23:40:17.40/xfe/off,on,15.2 2006.145.23:40:17.78/ifatt/23,28,28,28 2006.145.23:40:18.08/fmout-gps/S +4.0E-08 2006.145.23:40:18.16:!2006.145.23:43:43 2006.145.23:43:43.01:data_valid=off 2006.145.23:43:43.01:"et 2006.145.23:43:43.02:!+3s 2006.145.23:43:46.03:"tape 2006.145.23:43:46.03:postob 2006.145.23:43:46.13/cable/+6.5465E-03 2006.145.23:43:46.13/wx/19.68,1020.4,75 2006.145.23:43:46.22/fmout-gps/S +4.1E-08 2006.145.23:43:46.22:scan_name=145-2347,jd0605,400 2006.145.23:43:46.22:source=0059+581,010245.76,582411.1,2000.0,neutral 2006.145.23:43:47.13#flagr#flagr/antenna,new-source 2006.145.23:43:47.13:checkk5 2006.145.23:43:47.58/chk_autoobs//k5ts1/ autoobs is running! 2006.145.23:43:48.01/chk_autoobs//k5ts2/ autoobs is running! 2006.145.23:43:48.45/chk_autoobs//k5ts3/ autoobs is running! 2006.145.23:43:48.87/chk_autoobs//k5ts4/ autoobs is running! 2006.145.23:43:49.30/chk_obsdata//k5ts1/T1452340??a.dat file size is correct (nominal:840MB, actual:840MB). 2006.145.23:43:49.73/chk_obsdata//k5ts2/T1452340??b.dat file size is correct (nominal:840MB, actual:840MB). 2006.145.23:43:50.17/chk_obsdata//k5ts3/T1452340??c.dat file size is correct (nominal:840MB, actual:840MB). 2006.145.23:43:50.61/chk_obsdata//k5ts4/T1452340??d.dat file size is correct (nominal:840MB, actual:840MB). 2006.145.23:43:51.39/k5log//k5ts1_log_newline 2006.145.23:43:52.14/k5log//k5ts2_log_newline 2006.145.23:43:52.87/k5log//k5ts3_log_newline 2006.145.23:43:53.61/k5log//k5ts4_log_newline 2006.145.23:43:53.64/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.23:43:53.64:setupk4=1 2006.145.23:43:53.64$setupk4/echo=on 2006.145.23:43:53.64$setupk4/pcalon 2006.145.23:43:53.64$pcalon/"no phase cal control is implemented here 2006.145.23:43:53.64$setupk4/"tpicd=stop 2006.145.23:43:53.64$setupk4/"rec=synch_on 2006.145.23:43:53.64$setupk4/"rec_mode=128 2006.145.23:43:53.64$setupk4/!* 2006.145.23:43:53.64$setupk4/recpk4 2006.145.23:43:53.64$recpk4/recpatch= 2006.145.23:43:53.65$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.23:43:53.65$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.23:43:53.65$setupk4/vck44 2006.145.23:43:53.65$vck44/valo=1,524.99 2006.145.23:43:53.65#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.23:43:53.65#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.23:43:53.65#ibcon#ireg 17 cls_cnt 0 2006.145.23:43:53.65#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.23:43:53.65#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.23:43:53.65#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.23:43:53.68#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.23:43:53.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.23:43:53.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.23:43:53.73#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.23:43:53.73#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.23:43:53.73$vck44/va=1,8 2006.145.23:43:53.73#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.23:43:53.73#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.23:43:53.73#ibcon#ireg 11 cls_cnt 2 2006.145.23:43:53.73#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.23:43:53.73#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.23:43:53.73#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.23:43:53.75#ibcon#[25=AT01-08\r\n] 2006.145.23:43:53.78#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.23:43:53.78#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.23:43:53.78#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.23:43:53.78#ibcon#ireg 7 cls_cnt 0 2006.145.23:43:53.78#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.23:43:53.90#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.23:43:53.90#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.23:43:53.93#ibcon#[25=USB\r\n] 2006.145.23:43:53.96#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.23:43:53.96#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.23:43:53.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.23:43:53.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.23:43:53.96$vck44/valo=2,534.99 2006.145.23:43:53.96#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.23:43:53.96#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.23:43:53.96#ibcon#ireg 17 cls_cnt 0 2006.145.23:43:53.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.23:43:53.96#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.23:43:53.96#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.23:43:53.98#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.23:43:54.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.23:43:54.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.23:43:54.02#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.23:43:54.02#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.23:43:54.02$vck44/va=2,7 2006.145.23:43:54.02#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.23:43:54.02#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.23:43:54.02#ibcon#ireg 11 cls_cnt 2 2006.145.23:43:54.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.23:43:54.08#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.23:43:54.08#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.23:43:54.10#ibcon#[25=AT02-07\r\n] 2006.145.23:43:54.13#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.23:43:54.13#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.23:43:54.13#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.23:43:54.13#ibcon#ireg 7 cls_cnt 0 2006.145.23:43:54.13#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.23:43:54.25#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.23:43:54.25#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.23:43:54.27#ibcon#[25=USB\r\n] 2006.145.23:43:54.30#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.23:43:54.30#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.23:43:54.30#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.23:43:54.30#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.23:43:54.30$vck44/valo=3,564.99 2006.145.23:43:54.30#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.145.23:43:54.30#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.145.23:43:54.30#ibcon#ireg 17 cls_cnt 0 2006.145.23:43:54.30#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.23:43:54.30#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.145.23:43:54.30#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.23:43:54.32#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.23:43:54.35#abcon#<5=/07 2.3 3.7 19.69 731020.4\r\n> 2006.145.23:43:54.36#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.145.23:43:54.36#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.145.23:43:54.36#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.23:43:54.36#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.23:43:54.36$vck44/va=3,8 2006.145.23:43:54.36#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.23:43:54.36#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.23:43:54.36#ibcon#ireg 11 cls_cnt 2 2006.145.23:43:54.36#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.23:43:54.37#abcon#{5=INTERFACE CLEAR} 2006.145.23:43:54.42#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.23:43:54.42#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.23:43:54.43#abcon#[5=S1D000X0/0*\r\n] 2006.145.23:43:54.44#ibcon#[25=AT03-08\r\n] 2006.145.23:43:54.47#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.23:43:54.47#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.23:43:54.47#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.23:43:54.47#ibcon#ireg 7 cls_cnt 0 2006.145.23:43:54.47#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.23:43:54.59#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.23:43:54.59#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.23:43:54.61#ibcon#[25=USB\r\n] 2006.145.23:43:54.64#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.23:43:54.64#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.23:43:54.64#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.23:43:54.64#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.23:43:54.64$vck44/valo=4,624.99 2006.145.23:43:54.64#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.23:43:54.64#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.23:43:54.64#ibcon#ireg 17 cls_cnt 0 2006.145.23:43:54.64#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.23:43:54.64#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.23:43:54.64#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.23:43:54.66#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.23:43:54.70#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.23:43:54.70#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.23:43:54.70#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.23:43:54.70#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.23:43:54.70$vck44/va=4,7 2006.145.23:43:54.70#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.23:43:54.70#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.23:43:54.70#ibcon#ireg 11 cls_cnt 2 2006.145.23:43:54.70#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.23:43:54.76#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.23:43:54.76#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.23:43:54.78#ibcon#[25=AT04-07\r\n] 2006.145.23:43:54.81#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.23:43:54.81#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.23:43:54.81#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.23:43:54.81#ibcon#ireg 7 cls_cnt 0 2006.145.23:43:54.81#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.23:43:54.93#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.23:43:54.93#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.23:43:54.95#ibcon#[25=USB\r\n] 2006.145.23:43:54.98#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.23:43:54.98#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.23:43:54.98#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.23:43:54.98#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.23:43:54.98$vck44/valo=5,734.99 2006.145.23:43:54.98#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.23:43:54.98#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.23:43:54.98#ibcon#ireg 17 cls_cnt 0 2006.145.23:43:54.98#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.23:43:54.98#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.23:43:54.98#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.23:43:55.00#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.23:43:55.04#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.23:43:55.04#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.23:43:55.04#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.23:43:55.04#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.23:43:55.04$vck44/va=5,4 2006.145.23:43:55.04#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.23:43:55.04#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.23:43:55.04#ibcon#ireg 11 cls_cnt 2 2006.145.23:43:55.04#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.23:43:55.11#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.23:43:55.11#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.23:43:55.12#ibcon#[25=AT05-04\r\n] 2006.145.23:43:55.15#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.23:43:55.15#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.23:43:55.15#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.23:43:55.15#ibcon#ireg 7 cls_cnt 0 2006.145.23:43:55.15#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.23:43:55.28#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.23:43:55.28#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.23:43:55.30#ibcon#[25=USB\r\n] 2006.145.23:43:55.33#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.23:43:55.33#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.23:43:55.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.23:43:55.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.23:43:55.33$vck44/valo=6,814.99 2006.145.23:43:55.33#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.23:43:55.33#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.23:43:55.33#ibcon#ireg 17 cls_cnt 0 2006.145.23:43:55.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.23:43:55.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.23:43:55.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.23:43:55.36#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.23:43:55.40#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.23:43:55.40#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.23:43:55.40#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.23:43:55.40#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.23:43:55.40$vck44/va=6,4 2006.145.23:43:55.40#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.23:43:55.40#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.23:43:55.40#ibcon#ireg 11 cls_cnt 2 2006.145.23:43:55.40#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.23:43:55.45#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.23:43:55.45#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.23:43:55.47#ibcon#[25=AT06-04\r\n] 2006.145.23:43:55.50#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.23:43:55.50#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.23:43:55.50#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.23:43:55.50#ibcon#ireg 7 cls_cnt 0 2006.145.23:43:55.50#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.23:43:55.62#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.23:43:55.62#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.23:43:55.64#ibcon#[25=USB\r\n] 2006.145.23:43:55.67#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.23:43:55.67#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.23:43:55.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.23:43:55.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.23:43:55.67$vck44/valo=7,864.99 2006.145.23:43:55.67#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.23:43:55.67#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.23:43:55.67#ibcon#ireg 17 cls_cnt 0 2006.145.23:43:55.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.23:43:55.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.23:43:55.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.23:43:55.69#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.23:43:55.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.23:43:55.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.23:43:55.73#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.23:43:55.73#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.23:43:55.73$vck44/va=7,4 2006.145.23:43:55.73#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.23:43:55.73#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.23:43:55.73#ibcon#ireg 11 cls_cnt 2 2006.145.23:43:55.73#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.23:43:55.79#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.23:43:55.79#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.23:43:55.81#ibcon#[25=AT07-04\r\n] 2006.145.23:43:55.84#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.23:43:55.84#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.23:43:55.84#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.23:43:55.84#ibcon#ireg 7 cls_cnt 0 2006.145.23:43:55.84#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.23:43:55.96#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.23:43:55.96#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.23:43:55.98#ibcon#[25=USB\r\n] 2006.145.23:43:56.01#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.23:43:56.01#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.23:43:56.01#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.23:43:56.01#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.23:43:56.01$vck44/valo=8,884.99 2006.145.23:43:56.01#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.23:43:56.01#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.23:43:56.01#ibcon#ireg 17 cls_cnt 0 2006.145.23:43:56.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.23:43:56.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.23:43:56.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.23:43:56.03#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.23:43:56.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.23:43:56.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.23:43:56.07#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.23:43:56.07#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.23:43:56.07$vck44/va=8,4 2006.145.23:43:56.07#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.145.23:43:56.07#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.145.23:43:56.07#ibcon#ireg 11 cls_cnt 2 2006.145.23:43:56.07#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.23:43:56.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.145.23:43:56.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.23:43:56.15#ibcon#[25=AT08-04\r\n] 2006.145.23:43:56.18#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.145.23:43:56.18#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.145.23:43:56.18#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.145.23:43:56.18#ibcon#ireg 7 cls_cnt 0 2006.145.23:43:56.18#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.23:43:56.30#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.145.23:43:56.30#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.23:43:56.32#ibcon#[25=USB\r\n] 2006.145.23:43:56.35#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.145.23:43:56.35#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.145.23:43:56.35#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.23:43:56.35#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.23:43:56.35$vck44/vblo=1,629.99 2006.145.23:43:56.35#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.145.23:43:56.35#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.145.23:43:56.35#ibcon#ireg 17 cls_cnt 0 2006.145.23:43:56.35#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.23:43:56.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.145.23:43:56.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.23:43:56.37#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.23:43:56.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.145.23:43:56.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.145.23:43:56.41#ibcon#about to clear, iclass 11 cls_cnt 0 2006.145.23:43:56.41#ibcon#cleared, iclass 11 cls_cnt 0 2006.145.23:43:56.41$vck44/vb=1,3 2006.145.23:43:56.41#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.145.23:43:56.41#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.145.23:43:56.41#ibcon#ireg 11 cls_cnt 2 2006.145.23:43:56.41#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.23:43:56.41#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.145.23:43:56.41#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.23:43:56.43#ibcon#[27=AT01-03\r\n] 2006.145.23:43:56.46#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.145.23:43:56.46#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.145.23:43:56.46#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.145.23:43:56.46#ibcon#ireg 7 cls_cnt 0 2006.145.23:43:56.46#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.23:43:56.58#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.145.23:43:56.58#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.23:43:56.60#ibcon#[27=USB\r\n] 2006.145.23:43:56.63#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.145.23:43:56.63#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.145.23:43:56.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.145.23:43:56.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.145.23:43:56.63$vck44/vblo=2,634.99 2006.145.23:43:56.63#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.145.23:43:56.63#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.145.23:43:56.63#ibcon#ireg 17 cls_cnt 0 2006.145.23:43:56.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.23:43:56.63#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.145.23:43:56.63#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.23:43:56.65#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.23:43:56.69#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.145.23:43:56.69#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.145.23:43:56.69#ibcon#about to clear, iclass 15 cls_cnt 0 2006.145.23:43:56.69#ibcon#cleared, iclass 15 cls_cnt 0 2006.145.23:43:56.69$vck44/vb=2,4 2006.145.23:43:56.69#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.145.23:43:56.69#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.145.23:43:56.69#ibcon#ireg 11 cls_cnt 2 2006.145.23:43:56.69#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.23:43:56.75#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.145.23:43:56.75#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.23:43:56.77#ibcon#[27=AT02-04\r\n] 2006.145.23:43:56.80#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.145.23:43:56.80#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.145.23:43:56.80#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.145.23:43:56.80#ibcon#ireg 7 cls_cnt 0 2006.145.23:43:56.80#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.23:43:56.92#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.145.23:43:56.92#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.23:43:56.94#ibcon#[27=USB\r\n] 2006.145.23:43:56.97#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.145.23:43:56.97#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.145.23:43:56.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.145.23:43:56.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.145.23:43:56.97$vck44/vblo=3,649.99 2006.145.23:43:56.97#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.145.23:43:56.97#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.145.23:43:56.97#ibcon#ireg 17 cls_cnt 0 2006.145.23:43:56.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.23:43:56.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.145.23:43:56.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.23:43:56.99#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.23:43:57.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.145.23:43:57.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.145.23:43:57.03#ibcon#about to clear, iclass 19 cls_cnt 0 2006.145.23:43:57.03#ibcon#cleared, iclass 19 cls_cnt 0 2006.145.23:43:57.03$vck44/vb=3,4 2006.145.23:43:57.03#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.145.23:43:57.03#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.145.23:43:57.03#ibcon#ireg 11 cls_cnt 2 2006.145.23:43:57.03#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.23:43:57.09#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.145.23:43:57.09#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.23:43:57.11#ibcon#[27=AT03-04\r\n] 2006.145.23:43:57.14#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.145.23:43:57.14#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.145.23:43:57.14#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.145.23:43:57.14#ibcon#ireg 7 cls_cnt 0 2006.145.23:43:57.14#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.23:43:57.26#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.145.23:43:57.26#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.23:43:57.28#ibcon#[27=USB\r\n] 2006.145.23:43:57.31#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.145.23:43:57.31#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.145.23:43:57.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.145.23:43:57.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.145.23:43:57.31$vck44/vblo=4,679.99 2006.145.23:43:57.31#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.145.23:43:57.31#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.145.23:43:57.31#ibcon#ireg 17 cls_cnt 0 2006.145.23:43:57.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.23:43:57.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.145.23:43:57.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.23:43:57.33#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.23:43:57.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.145.23:43:57.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.145.23:43:57.37#ibcon#about to clear, iclass 23 cls_cnt 0 2006.145.23:43:57.37#ibcon#cleared, iclass 23 cls_cnt 0 2006.145.23:43:57.37$vck44/vb=4,4 2006.145.23:43:57.37#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.145.23:43:57.37#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.145.23:43:57.37#ibcon#ireg 11 cls_cnt 2 2006.145.23:43:57.37#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.23:43:57.43#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.145.23:43:57.43#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.23:43:57.45#ibcon#[27=AT04-04\r\n] 2006.145.23:43:57.48#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.145.23:43:57.48#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.145.23:43:57.48#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.145.23:43:57.48#ibcon#ireg 7 cls_cnt 0 2006.145.23:43:57.48#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.23:43:57.60#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.145.23:43:57.60#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.23:43:57.62#ibcon#[27=USB\r\n] 2006.145.23:43:57.65#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.145.23:43:57.65#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.145.23:43:57.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.145.23:43:57.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.145.23:43:57.65$vck44/vblo=5,709.99 2006.145.23:43:57.65#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.145.23:43:57.65#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.145.23:43:57.65#ibcon#ireg 17 cls_cnt 0 2006.145.23:43:57.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.23:43:57.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.145.23:43:57.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.23:43:57.67#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.23:43:57.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.145.23:43:57.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.145.23:43:57.71#ibcon#about to clear, iclass 27 cls_cnt 0 2006.145.23:43:57.71#ibcon#cleared, iclass 27 cls_cnt 0 2006.145.23:43:57.71$vck44/vb=5,4 2006.145.23:43:57.71#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.145.23:43:57.71#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.145.23:43:57.71#ibcon#ireg 11 cls_cnt 2 2006.145.23:43:57.71#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.23:43:57.77#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.145.23:43:57.77#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.23:43:57.79#ibcon#[27=AT05-04\r\n] 2006.145.23:43:57.82#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.145.23:43:57.82#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.145.23:43:57.82#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.145.23:43:57.82#ibcon#ireg 7 cls_cnt 0 2006.145.23:43:57.82#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.23:43:57.94#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.145.23:43:57.94#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.23:43:57.96#ibcon#[27=USB\r\n] 2006.145.23:43:57.99#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.145.23:43:57.99#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.145.23:43:57.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.145.23:43:57.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.145.23:43:57.99$vck44/vblo=6,719.99 2006.145.23:43:57.99#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.23:43:57.99#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.23:43:57.99#ibcon#ireg 17 cls_cnt 0 2006.145.23:43:57.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.23:43:57.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.23:43:57.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.23:43:58.01#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.23:43:58.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.23:43:58.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.23:43:58.05#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.23:43:58.05#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.23:43:58.05$vck44/vb=6,4 2006.145.23:43:58.05#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.145.23:43:58.05#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.145.23:43:58.05#ibcon#ireg 11 cls_cnt 2 2006.145.23:43:58.05#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.23:43:58.11#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.145.23:43:58.11#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.23:43:58.13#ibcon#[27=AT06-04\r\n] 2006.145.23:43:58.16#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.145.23:43:58.16#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.145.23:43:58.16#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.145.23:43:58.16#ibcon#ireg 7 cls_cnt 0 2006.145.23:43:58.16#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.23:43:58.28#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.145.23:43:58.28#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.23:43:58.30#ibcon#[27=USB\r\n] 2006.145.23:43:58.33#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.145.23:43:58.33#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.145.23:43:58.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.145.23:43:58.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.145.23:43:58.33$vck44/vblo=7,734.99 2006.145.23:43:58.33#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.145.23:43:58.33#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.145.23:43:58.33#ibcon#ireg 17 cls_cnt 0 2006.145.23:43:58.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.23:43:58.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.145.23:43:58.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.23:43:58.35#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.23:43:58.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.145.23:43:58.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.145.23:43:58.39#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.23:43:58.39#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.23:43:58.39$vck44/vb=7,4 2006.145.23:43:58.39#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.145.23:43:58.39#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.145.23:43:58.39#ibcon#ireg 11 cls_cnt 2 2006.145.23:43:58.39#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.23:43:58.45#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.145.23:43:58.45#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.23:43:58.47#ibcon#[27=AT07-04\r\n] 2006.145.23:43:58.50#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.145.23:43:58.50#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.145.23:43:58.50#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.145.23:43:58.50#ibcon#ireg 7 cls_cnt 0 2006.145.23:43:58.50#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.23:43:58.62#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.145.23:43:58.62#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.23:43:58.64#ibcon#[27=USB\r\n] 2006.145.23:43:58.67#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.145.23:43:58.67#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.145.23:43:58.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.145.23:43:58.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.145.23:43:58.67$vck44/vblo=8,744.99 2006.145.23:43:58.67#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.145.23:43:58.67#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.145.23:43:58.67#ibcon#ireg 17 cls_cnt 0 2006.145.23:43:58.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.23:43:58.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.145.23:43:58.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.23:43:58.69#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.23:43:58.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.145.23:43:58.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.145.23:43:58.73#ibcon#about to clear, iclass 39 cls_cnt 0 2006.145.23:43:58.73#ibcon#cleared, iclass 39 cls_cnt 0 2006.145.23:43:58.73$vck44/vb=8,4 2006.145.23:43:58.73#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.145.23:43:58.73#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.145.23:43:58.73#ibcon#ireg 11 cls_cnt 2 2006.145.23:43:58.73#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.23:43:58.79#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.145.23:43:58.79#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.23:43:58.81#ibcon#[27=AT08-04\r\n] 2006.145.23:43:58.84#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.145.23:43:58.84#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.145.23:43:58.84#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.145.23:43:58.84#ibcon#ireg 7 cls_cnt 0 2006.145.23:43:58.84#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.23:43:58.96#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.145.23:43:58.96#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.23:43:58.98#ibcon#[27=USB\r\n] 2006.145.23:43:59.01#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.145.23:43:59.01#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.145.23:43:59.01#ibcon#about to clear, iclass 3 cls_cnt 0 2006.145.23:43:59.01#ibcon#cleared, iclass 3 cls_cnt 0 2006.145.23:43:59.01$vck44/vabw=wide 2006.145.23:43:59.01#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.145.23:43:59.01#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.145.23:43:59.01#ibcon#ireg 8 cls_cnt 0 2006.145.23:43:59.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.23:43:59.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.145.23:43:59.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.23:43:59.03#ibcon#[25=BW32\r\n] 2006.145.23:43:59.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.145.23:43:59.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.145.23:43:59.06#ibcon#about to clear, iclass 5 cls_cnt 0 2006.145.23:43:59.06#ibcon#cleared, iclass 5 cls_cnt 0 2006.145.23:43:59.06$vck44/vbbw=wide 2006.145.23:43:59.06#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.145.23:43:59.06#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.145.23:43:59.06#ibcon#ireg 8 cls_cnt 0 2006.145.23:43:59.06#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.23:43:59.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.145.23:43:59.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.23:43:59.15#ibcon#[27=BW32\r\n] 2006.145.23:43:59.18#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.145.23:43:59.18#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.145.23:43:59.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.145.23:43:59.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.145.23:43:59.18$setupk4/ifdk4 2006.145.23:43:59.18$ifdk4/lo= 2006.145.23:43:59.18$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.23:43:59.18$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.23:43:59.18$ifdk4/patch= 2006.145.23:43:59.18$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.23:43:59.18$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.23:43:59.18$setupk4/!*+20s 2006.145.23:44:04.52#abcon#<5=/07 2.3 3.7 19.70 731020.4\r\n> 2006.145.23:44:04.54#abcon#{5=INTERFACE CLEAR} 2006.145.23:44:04.60#abcon#[5=S1D000X0/0*\r\n] 2006.145.23:44:12.13#trakl#Source acquired 2006.145.23:44:12.13#flagr#flagr/antenna,acquired 2006.145.23:44:13.65$setupk4/"tpicd 2006.145.23:44:13.65$setupk4/echo=off 2006.145.23:44:13.65$setupk4/xlog=off 2006.145.23:44:13.65:!2006.145.23:47:29 2006.145.23:47:29.00:preob 2006.145.23:47:29.14/onsource/TRACKING 2006.145.23:47:29.14:!2006.145.23:47:39 2006.145.23:47:39.00:"tape 2006.145.23:47:39.00:"st=record 2006.145.23:47:39.00:data_valid=on 2006.145.23:47:39.00:midob 2006.145.23:47:39.14/onsource/TRACKING 2006.145.23:47:39.14/wx/19.92,1020.4,74 2006.145.23:47:39.33/cable/+6.5482E-03 2006.145.23:47:40.42/va/01,08,usb,yes,28,30 2006.145.23:47:40.42/va/02,07,usb,yes,30,30 2006.145.23:47:40.42/va/03,08,usb,yes,27,28 2006.145.23:47:40.42/va/04,07,usb,yes,31,32 2006.145.23:47:40.42/va/05,04,usb,yes,27,27 2006.145.23:47:40.42/va/06,04,usb,yes,30,30 2006.145.23:47:40.42/va/07,04,usb,yes,30,32 2006.145.23:47:40.42/va/08,04,usb,yes,26,31 2006.145.23:47:40.65/valo/01,524.99,yes,locked 2006.145.23:47:40.65/valo/02,534.99,yes,locked 2006.145.23:47:40.65/valo/03,564.99,yes,locked 2006.145.23:47:40.65/valo/04,624.99,yes,locked 2006.145.23:47:40.65/valo/05,734.99,yes,locked 2006.145.23:47:40.65/valo/06,814.99,yes,locked 2006.145.23:47:40.65/valo/07,864.99,yes,locked 2006.145.23:47:40.65/valo/08,884.99,yes,locked 2006.145.23:47:41.74/vb/01,03,usb,yes,35,33 2006.145.23:47:41.74/vb/02,04,usb,yes,31,31 2006.145.23:47:41.74/vb/03,04,usb,yes,28,31 2006.145.23:47:41.74/vb/04,04,usb,yes,32,31 2006.145.23:47:41.74/vb/05,04,usb,yes,25,27 2006.145.23:47:41.74/vb/06,04,usb,yes,29,25 2006.145.23:47:41.74/vb/07,04,usb,yes,29,28 2006.145.23:47:41.74/vb/08,04,usb,yes,26,30 2006.145.23:47:41.97/vblo/01,629.99,yes,locked 2006.145.23:47:41.97/vblo/02,634.99,yes,locked 2006.145.23:47:41.97/vblo/03,649.99,yes,locked 2006.145.23:47:41.97/vblo/04,679.99,yes,locked 2006.145.23:47:41.97/vblo/05,709.99,yes,locked 2006.145.23:47:41.97/vblo/06,719.99,yes,locked 2006.145.23:47:41.97/vblo/07,734.99,yes,locked 2006.145.23:47:41.97/vblo/08,744.99,yes,locked 2006.145.23:47:42.12/vabw/8 2006.145.23:47:42.27/vbbw/8 2006.145.23:47:42.36/xfe/off,on,15.0 2006.145.23:47:42.75/ifatt/23,28,28,28 2006.145.23:47:43.07/fmout-gps/S +4.2E-08 2006.145.23:47:43.11:!2006.145.23:54:19 2006.145.23:54:19.00:data_valid=off 2006.145.23:54:19.00:"et 2006.145.23:54:19.00:!+3s 2006.145.23:54:22.02:"tape 2006.145.23:54:22.02:postob 2006.145.23:54:22.14/cable/+6.5463E-03 2006.145.23:54:22.14/wx/20.19,1020.4,76 2006.145.23:54:22.22/fmout-gps/S +4.2E-08 2006.145.23:54:22.22:scan_name=146-0000,jd0605,90 2006.145.23:54:22.22:source=0528+134,053056.42,133155.1,2000.0,cw 2006.145.23:54:24.14#flagr#flagr/antenna,new-source 2006.145.23:54:24.14:checkk5 2006.145.23:54:24.60/chk_autoobs//k5ts1/ autoobs is running! 2006.145.23:54:25.02/chk_autoobs//k5ts2/ autoobs is running! 2006.145.23:54:25.47/chk_autoobs//k5ts3/ autoobs is running! 2006.145.23:54:25.92/chk_autoobs//k5ts4/ autoobs is running! 2006.145.23:54:26.33/chk_obsdata//k5ts1/T1452347??a.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.145.23:54:26.77/chk_obsdata//k5ts2/T1452347??b.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.145.23:54:27.20/chk_obsdata//k5ts3/T1452347??c.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.145.23:54:27.62/chk_obsdata//k5ts4/T1452347??d.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.145.23:54:28.36/k5log//k5ts1_log_newline 2006.145.23:54:29.11/k5log//k5ts2_log_newline 2006.145.23:54:29.84/k5log//k5ts3_log_newline 2006.145.23:54:30.59/k5log//k5ts4_log_newline 2006.145.23:54:30.62/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.145.23:54:30.62:setupk4=1 2006.145.23:54:30.62$setupk4/echo=on 2006.145.23:54:30.62$setupk4/pcalon 2006.145.23:54:30.62$pcalon/"no phase cal control is implemented here 2006.145.23:54:30.62$setupk4/"tpicd=stop 2006.145.23:54:30.62$setupk4/"rec=synch_on 2006.145.23:54:30.62$setupk4/"rec_mode=128 2006.145.23:54:30.62$setupk4/!* 2006.145.23:54:30.62$setupk4/recpk4 2006.145.23:54:30.62$recpk4/recpatch= 2006.145.23:54:30.62$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.145.23:54:30.62$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.145.23:54:30.62$setupk4/vck44 2006.145.23:54:30.62$vck44/valo=1,524.99 2006.145.23:54:30.62#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.23:54:30.62#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.23:54:30.62#ibcon#ireg 17 cls_cnt 0 2006.145.23:54:30.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.23:54:30.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.23:54:30.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.23:54:30.66#ibcon#[26=FRQ=01,524.99\r\n] 2006.145.23:54:30.71#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.23:54:30.71#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.23:54:30.71#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.23:54:30.71#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.23:54:30.71$vck44/va=1,8 2006.145.23:54:30.71#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.23:54:30.71#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.23:54:30.71#ibcon#ireg 11 cls_cnt 2 2006.145.23:54:30.71#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.23:54:30.71#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.23:54:30.71#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.23:54:30.73#ibcon#[25=AT01-08\r\n] 2006.145.23:54:30.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.23:54:30.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.23:54:30.76#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.23:54:30.76#ibcon#ireg 7 cls_cnt 0 2006.145.23:54:30.76#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.23:54:30.88#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.23:54:30.88#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.23:54:30.90#ibcon#[25=USB\r\n] 2006.145.23:54:30.94#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.23:54:30.94#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.23:54:30.94#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.23:54:30.94#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.23:54:30.94$vck44/valo=2,534.99 2006.145.23:54:30.94#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.23:54:30.94#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.23:54:30.94#ibcon#ireg 17 cls_cnt 0 2006.145.23:54:30.94#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.23:54:30.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.23:54:30.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.23:54:30.96#ibcon#[26=FRQ=02,534.99\r\n] 2006.145.23:54:31.00#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.23:54:31.00#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.23:54:31.00#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.23:54:31.00#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.23:54:31.00$vck44/va=2,7 2006.145.23:54:31.00#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.23:54:31.00#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.23:54:31.00#ibcon#ireg 11 cls_cnt 2 2006.145.23:54:31.00#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.23:54:31.06#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.23:54:31.06#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.23:54:31.08#ibcon#[25=AT02-07\r\n] 2006.145.23:54:31.11#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.23:54:31.11#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.23:54:31.11#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.23:54:31.11#ibcon#ireg 7 cls_cnt 0 2006.145.23:54:31.11#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.23:54:31.23#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.23:54:31.23#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.23:54:31.25#ibcon#[25=USB\r\n] 2006.145.23:54:31.28#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.23:54:31.28#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.23:54:31.28#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.23:54:31.28#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.23:54:31.28$vck44/valo=3,564.99 2006.145.23:54:31.28#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.23:54:31.28#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.23:54:31.28#ibcon#ireg 17 cls_cnt 0 2006.145.23:54:31.28#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.23:54:31.28#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.23:54:31.28#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.23:54:31.30#ibcon#[26=FRQ=03,564.99\r\n] 2006.145.23:54:31.34#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.23:54:31.34#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.23:54:31.34#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.23:54:31.34#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.23:54:31.34$vck44/va=3,8 2006.145.23:54:31.34#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.23:54:31.34#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.23:54:31.34#ibcon#ireg 11 cls_cnt 2 2006.145.23:54:31.34#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.23:54:31.40#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.23:54:31.40#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.23:54:31.42#ibcon#[25=AT03-08\r\n] 2006.145.23:54:31.45#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.23:54:31.45#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.23:54:31.45#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.23:54:31.45#ibcon#ireg 7 cls_cnt 0 2006.145.23:54:31.45#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.23:54:31.57#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.23:54:31.57#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.23:54:31.59#ibcon#[25=USB\r\n] 2006.145.23:54:31.62#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.23:54:31.62#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.23:54:31.62#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.23:54:31.62#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.23:54:31.62$vck44/valo=4,624.99 2006.145.23:54:31.62#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.23:54:31.62#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.23:54:31.62#ibcon#ireg 17 cls_cnt 0 2006.145.23:54:31.62#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.23:54:31.62#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.23:54:31.62#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.23:54:31.64#ibcon#[26=FRQ=04,624.99\r\n] 2006.145.23:54:31.68#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.23:54:31.68#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.23:54:31.68#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.23:54:31.68#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.23:54:31.68$vck44/va=4,7 2006.145.23:54:31.68#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.23:54:31.68#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.23:54:31.68#ibcon#ireg 11 cls_cnt 2 2006.145.23:54:31.68#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.23:54:31.74#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.23:54:31.74#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.23:54:31.76#ibcon#[25=AT04-07\r\n] 2006.145.23:54:31.79#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.23:54:31.79#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.23:54:31.79#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.23:54:31.79#ibcon#ireg 7 cls_cnt 0 2006.145.23:54:31.79#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.23:54:31.91#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.23:54:31.91#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.23:54:31.93#ibcon#[25=USB\r\n] 2006.145.23:54:31.96#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.23:54:31.96#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.23:54:31.96#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.23:54:31.96#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.23:54:31.96$vck44/valo=5,734.99 2006.145.23:54:31.96#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.23:54:31.96#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.23:54:31.96#ibcon#ireg 17 cls_cnt 0 2006.145.23:54:31.96#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.23:54:31.96#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.23:54:31.96#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.23:54:31.98#ibcon#[26=FRQ=05,734.99\r\n] 2006.145.23:54:32.02#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.23:54:32.02#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.23:54:32.02#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.23:54:32.02#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.23:54:32.02$vck44/va=5,4 2006.145.23:54:32.02#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.23:54:32.02#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.23:54:32.02#ibcon#ireg 11 cls_cnt 2 2006.145.23:54:32.02#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.23:54:32.08#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.23:54:32.08#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.23:54:32.10#ibcon#[25=AT05-04\r\n] 2006.145.23:54:32.13#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.23:54:32.13#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.23:54:32.13#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.23:54:32.13#ibcon#ireg 7 cls_cnt 0 2006.145.23:54:32.13#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.23:54:32.25#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.23:54:32.25#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.23:54:32.27#ibcon#[25=USB\r\n] 2006.145.23:54:32.30#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.23:54:32.30#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.23:54:32.30#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.23:54:32.30#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.23:54:32.30$vck44/valo=6,814.99 2006.145.23:54:32.30#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.145.23:54:32.30#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.145.23:54:32.30#ibcon#ireg 17 cls_cnt 0 2006.145.23:54:32.30#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.23:54:32.30#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.145.23:54:32.30#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.23:54:32.32#ibcon#[26=FRQ=06,814.99\r\n] 2006.145.23:54:32.36#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.145.23:54:32.36#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.145.23:54:32.36#ibcon#about to clear, iclass 30 cls_cnt 0 2006.145.23:54:32.36#ibcon#cleared, iclass 30 cls_cnt 0 2006.145.23:54:32.36$vck44/va=6,4 2006.145.23:54:32.36#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.145.23:54:32.36#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.145.23:54:32.36#ibcon#ireg 11 cls_cnt 2 2006.145.23:54:32.36#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.23:54:32.42#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.145.23:54:32.42#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.23:54:32.44#ibcon#[25=AT06-04\r\n] 2006.145.23:54:32.47#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.145.23:54:32.47#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.145.23:54:32.47#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.145.23:54:32.47#ibcon#ireg 7 cls_cnt 0 2006.145.23:54:32.47#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.23:54:32.59#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.145.23:54:32.59#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.23:54:32.61#ibcon#[25=USB\r\n] 2006.145.23:54:32.64#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.145.23:54:32.64#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.145.23:54:32.64#ibcon#about to clear, iclass 32 cls_cnt 0 2006.145.23:54:32.64#ibcon#cleared, iclass 32 cls_cnt 0 2006.145.23:54:32.64$vck44/valo=7,864.99 2006.145.23:54:32.64#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.145.23:54:32.64#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.145.23:54:32.64#ibcon#ireg 17 cls_cnt 0 2006.145.23:54:32.64#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.23:54:32.64#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.145.23:54:32.64#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.23:54:32.66#ibcon#[26=FRQ=07,864.99\r\n] 2006.145.23:54:32.70#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.145.23:54:32.70#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.145.23:54:32.70#ibcon#about to clear, iclass 34 cls_cnt 0 2006.145.23:54:32.70#ibcon#cleared, iclass 34 cls_cnt 0 2006.145.23:54:32.70$vck44/va=7,4 2006.145.23:54:32.70#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.145.23:54:32.70#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.145.23:54:32.70#ibcon#ireg 11 cls_cnt 2 2006.145.23:54:32.70#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.23:54:32.76#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.145.23:54:32.76#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.23:54:32.78#ibcon#[25=AT07-04\r\n] 2006.145.23:54:32.81#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.145.23:54:32.81#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.145.23:54:32.81#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.145.23:54:32.81#ibcon#ireg 7 cls_cnt 0 2006.145.23:54:32.81#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.23:54:32.93#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.145.23:54:32.93#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.23:54:32.95#ibcon#[25=USB\r\n] 2006.145.23:54:32.98#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.145.23:54:32.98#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.145.23:54:32.98#ibcon#about to clear, iclass 36 cls_cnt 0 2006.145.23:54:32.98#ibcon#cleared, iclass 36 cls_cnt 0 2006.145.23:54:32.98$vck44/valo=8,884.99 2006.145.23:54:32.98#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.23:54:32.98#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.23:54:32.98#ibcon#ireg 17 cls_cnt 0 2006.145.23:54:32.98#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.23:54:32.98#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.23:54:32.98#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.23:54:33.00#ibcon#[26=FRQ=08,884.99\r\n] 2006.145.23:54:33.04#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.23:54:33.04#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.23:54:33.04#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.23:54:33.04#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.23:54:33.04$vck44/va=8,4 2006.145.23:54:33.04#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.23:54:33.04#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.23:54:33.04#ibcon#ireg 11 cls_cnt 2 2006.145.23:54:33.04#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.23:54:33.10#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.23:54:33.10#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.23:54:33.12#ibcon#[25=AT08-04\r\n] 2006.145.23:54:33.15#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.23:54:33.15#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.23:54:33.15#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.23:54:33.15#ibcon#ireg 7 cls_cnt 0 2006.145.23:54:33.15#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.23:54:33.27#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.23:54:33.27#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.23:54:33.29#ibcon#[25=USB\r\n] 2006.145.23:54:33.32#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.23:54:33.32#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.23:54:33.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.23:54:33.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.23:54:33.32$vck44/vblo=1,629.99 2006.145.23:54:33.32#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.23:54:33.32#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.23:54:33.32#ibcon#ireg 17 cls_cnt 0 2006.145.23:54:33.32#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.23:54:33.32#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.23:54:33.32#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.23:54:33.34#ibcon#[28=FRQ=01,629.99\r\n] 2006.145.23:54:33.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.23:54:33.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.23:54:33.38#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.23:54:33.38#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.23:54:33.38$vck44/vb=1,3 2006.145.23:54:33.38#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.145.23:54:33.38#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.145.23:54:33.38#ibcon#ireg 11 cls_cnt 2 2006.145.23:54:33.38#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.23:54:33.38#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.145.23:54:33.38#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.23:54:33.40#ibcon#[27=AT01-03\r\n] 2006.145.23:54:33.43#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.145.23:54:33.43#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.145.23:54:33.43#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.145.23:54:33.43#ibcon#ireg 7 cls_cnt 0 2006.145.23:54:33.43#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.23:54:33.55#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.145.23:54:33.55#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.23:54:33.57#ibcon#[27=USB\r\n] 2006.145.23:54:33.60#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.145.23:54:33.60#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.145.23:54:33.60#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.23:54:33.60#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.23:54:33.60$vck44/vblo=2,634.99 2006.145.23:54:33.60#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.145.23:54:33.60#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.145.23:54:33.60#ibcon#ireg 17 cls_cnt 0 2006.145.23:54:33.60#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.23:54:33.60#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.145.23:54:33.60#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.23:54:33.62#ibcon#[28=FRQ=02,634.99\r\n] 2006.145.23:54:33.66#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.145.23:54:33.66#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.145.23:54:33.66#ibcon#about to clear, iclass 10 cls_cnt 0 2006.145.23:54:33.66#ibcon#cleared, iclass 10 cls_cnt 0 2006.145.23:54:33.66$vck44/vb=2,4 2006.145.23:54:33.66#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.145.23:54:33.66#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.145.23:54:33.66#ibcon#ireg 11 cls_cnt 2 2006.145.23:54:33.66#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.23:54:33.72#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.145.23:54:33.72#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.23:54:33.74#ibcon#[27=AT02-04\r\n] 2006.145.23:54:33.77#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.145.23:54:33.77#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.145.23:54:33.77#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.145.23:54:33.77#ibcon#ireg 7 cls_cnt 0 2006.145.23:54:33.77#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.23:54:33.89#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.145.23:54:33.89#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.23:54:33.91#ibcon#[27=USB\r\n] 2006.145.23:54:33.94#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.145.23:54:33.94#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.145.23:54:33.94#ibcon#about to clear, iclass 12 cls_cnt 0 2006.145.23:54:33.94#ibcon#cleared, iclass 12 cls_cnt 0 2006.145.23:54:33.94$vck44/vblo=3,649.99 2006.145.23:54:33.94#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.145.23:54:33.94#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.145.23:54:33.94#ibcon#ireg 17 cls_cnt 0 2006.145.23:54:33.94#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.23:54:33.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.145.23:54:33.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.23:54:33.96#ibcon#[28=FRQ=03,649.99\r\n] 2006.145.23:54:34.00#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.145.23:54:34.00#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.145.23:54:34.00#ibcon#about to clear, iclass 14 cls_cnt 0 2006.145.23:54:34.00#ibcon#cleared, iclass 14 cls_cnt 0 2006.145.23:54:34.00$vck44/vb=3,4 2006.145.23:54:34.00#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.145.23:54:34.00#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.145.23:54:34.00#ibcon#ireg 11 cls_cnt 2 2006.145.23:54:34.00#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.23:54:34.06#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.145.23:54:34.06#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.23:54:34.08#ibcon#[27=AT03-04\r\n] 2006.145.23:54:34.11#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.145.23:54:34.11#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.145.23:54:34.11#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.145.23:54:34.11#ibcon#ireg 7 cls_cnt 0 2006.145.23:54:34.11#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.23:54:34.23#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.145.23:54:34.23#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.23:54:34.25#ibcon#[27=USB\r\n] 2006.145.23:54:34.28#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.145.23:54:34.28#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.145.23:54:34.28#ibcon#about to clear, iclass 16 cls_cnt 0 2006.145.23:54:34.28#ibcon#cleared, iclass 16 cls_cnt 0 2006.145.23:54:34.28$vck44/vblo=4,679.99 2006.145.23:54:34.28#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.145.23:54:34.28#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.145.23:54:34.28#ibcon#ireg 17 cls_cnt 0 2006.145.23:54:34.28#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.23:54:34.28#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.145.23:54:34.28#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.23:54:34.30#ibcon#[28=FRQ=04,679.99\r\n] 2006.145.23:54:34.34#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.145.23:54:34.34#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.145.23:54:34.34#ibcon#about to clear, iclass 18 cls_cnt 0 2006.145.23:54:34.34#ibcon#cleared, iclass 18 cls_cnt 0 2006.145.23:54:34.34$vck44/vb=4,4 2006.145.23:54:34.34#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.145.23:54:34.34#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.145.23:54:34.34#ibcon#ireg 11 cls_cnt 2 2006.145.23:54:34.34#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.23:54:34.40#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.145.23:54:34.40#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.23:54:34.42#ibcon#[27=AT04-04\r\n] 2006.145.23:54:34.45#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.145.23:54:34.45#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.145.23:54:34.45#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.145.23:54:34.45#ibcon#ireg 7 cls_cnt 0 2006.145.23:54:34.45#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.23:54:34.57#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.145.23:54:34.57#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.23:54:34.59#ibcon#[27=USB\r\n] 2006.145.23:54:34.62#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.145.23:54:34.62#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.145.23:54:34.62#ibcon#about to clear, iclass 20 cls_cnt 0 2006.145.23:54:34.62#ibcon#cleared, iclass 20 cls_cnt 0 2006.145.23:54:34.62$vck44/vblo=5,709.99 2006.145.23:54:34.62#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.145.23:54:34.62#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.145.23:54:34.62#ibcon#ireg 17 cls_cnt 0 2006.145.23:54:34.62#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.23:54:34.62#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.145.23:54:34.62#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.23:54:34.64#ibcon#[28=FRQ=05,709.99\r\n] 2006.145.23:54:34.68#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.145.23:54:34.68#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.145.23:54:34.68#ibcon#about to clear, iclass 22 cls_cnt 0 2006.145.23:54:34.68#ibcon#cleared, iclass 22 cls_cnt 0 2006.145.23:54:34.68$vck44/vb=5,4 2006.145.23:54:34.68#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.145.23:54:34.68#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.145.23:54:34.68#ibcon#ireg 11 cls_cnt 2 2006.145.23:54:34.68#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.23:54:34.74#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.145.23:54:34.74#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.23:54:34.76#ibcon#[27=AT05-04\r\n] 2006.145.23:54:34.79#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.145.23:54:34.79#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.145.23:54:34.79#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.145.23:54:34.79#ibcon#ireg 7 cls_cnt 0 2006.145.23:54:34.79#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.23:54:34.91#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.145.23:54:34.91#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.23:54:34.93#ibcon#[27=USB\r\n] 2006.145.23:54:34.96#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.145.23:54:34.96#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.145.23:54:34.96#ibcon#about to clear, iclass 24 cls_cnt 0 2006.145.23:54:34.96#ibcon#cleared, iclass 24 cls_cnt 0 2006.145.23:54:34.96$vck44/vblo=6,719.99 2006.145.23:54:34.96#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.145.23:54:34.96#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.145.23:54:34.96#ibcon#ireg 17 cls_cnt 0 2006.145.23:54:34.96#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.23:54:34.96#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.145.23:54:34.96#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.23:54:34.98#ibcon#[28=FRQ=06,719.99\r\n] 2006.145.23:54:35.02#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.145.23:54:35.02#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.145.23:54:35.02#ibcon#about to clear, iclass 26 cls_cnt 0 2006.145.23:54:35.02#ibcon#cleared, iclass 26 cls_cnt 0 2006.145.23:54:35.02$vck44/vb=6,4 2006.145.23:54:35.02#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.145.23:54:35.02#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.145.23:54:35.02#ibcon#ireg 11 cls_cnt 2 2006.145.23:54:35.02#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.23:54:35.08#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.145.23:54:35.08#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.23:54:35.10#ibcon#[27=AT06-04\r\n] 2006.145.23:54:35.13#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.145.23:54:35.13#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.145.23:54:35.13#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.145.23:54:35.13#ibcon#ireg 7 cls_cnt 0 2006.145.23:54:35.13#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.23:54:35.25#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.145.23:54:35.25#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.23:54:35.27#ibcon#[27=USB\r\n] 2006.145.23:54:35.30#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.145.23:54:35.30#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.145.23:54:35.30#ibcon#about to clear, iclass 28 cls_cnt 0 2006.145.23:54:35.30#ibcon#cleared, iclass 28 cls_cnt 0 2006.145.23:54:35.30$vck44/vblo=7,734.99 2006.145.23:54:35.30#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.145.23:54:35.30#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.145.23:54:35.30#ibcon#ireg 17 cls_cnt 0 2006.145.23:54:35.30#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.23:54:35.30#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.145.23:54:35.30#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.23:54:35.31#abcon#<5=/07 2.1 5.2 20.20 761020.4\r\n> 2006.145.23:54:35.32#ibcon#[28=FRQ=07,734.99\r\n] 2006.145.23:54:35.33#abcon#{5=INTERFACE CLEAR} 2006.145.23:54:35.36#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.145.23:54:35.36#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.145.23:54:35.36#ibcon#about to clear, iclass 31 cls_cnt 0 2006.145.23:54:35.36#ibcon#cleared, iclass 31 cls_cnt 0 2006.145.23:54:35.36$vck44/vb=7,4 2006.145.23:54:35.36#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.145.23:54:35.36#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.145.23:54:35.36#ibcon#ireg 11 cls_cnt 2 2006.145.23:54:35.36#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.23:54:35.39#abcon#[5=S1D000X0/0*\r\n] 2006.145.23:54:35.42#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.145.23:54:35.42#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.23:54:35.44#ibcon#[27=AT07-04\r\n] 2006.145.23:54:35.47#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.145.23:54:35.47#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.145.23:54:35.47#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.145.23:54:35.47#ibcon#ireg 7 cls_cnt 0 2006.145.23:54:35.47#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.23:54:35.59#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.145.23:54:35.59#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.23:54:35.61#ibcon#[27=USB\r\n] 2006.145.23:54:35.64#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.145.23:54:35.64#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.145.23:54:35.64#ibcon#about to clear, iclass 35 cls_cnt 0 2006.145.23:54:35.64#ibcon#cleared, iclass 35 cls_cnt 0 2006.145.23:54:35.64$vck44/vblo=8,744.99 2006.145.23:54:35.64#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.145.23:54:35.64#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.145.23:54:35.64#ibcon#ireg 17 cls_cnt 0 2006.145.23:54:35.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.23:54:35.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.145.23:54:35.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.23:54:35.66#ibcon#[28=FRQ=08,744.99\r\n] 2006.145.23:54:35.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.145.23:54:35.70#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.145.23:54:35.70#ibcon#about to clear, iclass 38 cls_cnt 0 2006.145.23:54:35.70#ibcon#cleared, iclass 38 cls_cnt 0 2006.145.23:54:35.70$vck44/vb=8,4 2006.145.23:54:35.70#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.145.23:54:35.70#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.145.23:54:35.70#ibcon#ireg 11 cls_cnt 2 2006.145.23:54:35.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.23:54:35.76#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.145.23:54:35.76#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.23:54:35.78#ibcon#[27=AT08-04\r\n] 2006.145.23:54:35.81#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.145.23:54:35.81#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.145.23:54:35.81#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.145.23:54:35.81#ibcon#ireg 7 cls_cnt 0 2006.145.23:54:35.81#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.23:54:35.93#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.145.23:54:35.93#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.23:54:35.95#ibcon#[27=USB\r\n] 2006.145.23:54:35.98#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.145.23:54:35.98#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.145.23:54:35.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.145.23:54:35.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.145.23:54:35.98$vck44/vabw=wide 2006.145.23:54:35.98#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.145.23:54:35.98#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.145.23:54:35.98#ibcon#ireg 8 cls_cnt 0 2006.145.23:54:35.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.23:54:35.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.145.23:54:35.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.23:54:36.00#ibcon#[25=BW32\r\n] 2006.145.23:54:36.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.145.23:54:36.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.145.23:54:36.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.145.23:54:36.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.145.23:54:36.03$vck44/vbbw=wide 2006.145.23:54:36.03#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.145.23:54:36.03#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.145.23:54:36.03#ibcon#ireg 8 cls_cnt 0 2006.145.23:54:36.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.23:54:36.10#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.145.23:54:36.10#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.23:54:36.12#ibcon#[27=BW32\r\n] 2006.145.23:54:36.15#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.145.23:54:36.15#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.145.23:54:36.15#ibcon#about to clear, iclass 6 cls_cnt 0 2006.145.23:54:36.15#ibcon#cleared, iclass 6 cls_cnt 0 2006.145.23:54:36.15$setupk4/ifdk4 2006.145.23:54:36.15$ifdk4/lo= 2006.145.23:54:36.15$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.145.23:54:36.15$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.145.23:54:36.15$ifdk4/patch= 2006.145.23:54:36.15$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.145.23:54:36.15$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.145.23:54:36.15$setupk4/!*+20s 2006.145.23:54:45.47#abcon#<5=/07 2.1 5.2 20.21 751020.4\r\n> 2006.145.23:54:45.50#abcon#{5=INTERFACE CLEAR} 2006.145.23:54:45.56#abcon#[5=S1D000X0/0*\r\n] 2006.145.23:54:50.65$setupk4/"tpicd 2006.145.23:54:50.65$setupk4/echo=off 2006.145.23:54:50.65$setupk4/xlog=off 2006.145.23:54:50.65:!2006.145.23:59:53 2006.145.23:55:06.13#trakl#Source acquired 2006.145.23:55:07.14#flagr#flagr/antenna,acquired 2006.145.23:59:53.00:preob 2006.145.23:59:53.14/onsource/TRACKING 2006.145.23:59:53.14:!2006.146.00:00:03 2006.146.00:00:03.00:"tape 2006.146.00:00:03.00:"st=record 2006.146.00:00:03.00:data_valid=on 2006.146.00:00:03.00:midob 2006.146.00:00:04.14/onsource/TRACKING 2006.146.00:00:04.14/wx/20.28,1020.4,74 2006.146.00:00:04.21/cable/+6.5456E-03 2006.146.00:00:05.30/va/01,08,usb,yes,29,31 2006.146.00:00:05.30/va/02,07,usb,yes,31,32 2006.146.00:00:05.30/va/03,08,usb,yes,28,29 2006.146.00:00:05.30/va/04,07,usb,yes,32,34 2006.146.00:00:05.30/va/05,04,usb,yes,28,28 2006.146.00:00:05.30/va/06,04,usb,yes,31,31 2006.146.00:00:05.30/va/07,04,usb,yes,32,33 2006.146.00:00:05.30/va/08,04,usb,yes,27,32 2006.146.00:00:05.53/valo/01,524.99,yes,locked 2006.146.00:00:05.53/valo/02,534.99,yes,locked 2006.146.00:00:05.53/valo/03,564.99,yes,locked 2006.146.00:00:05.53/valo/04,624.99,yes,locked 2006.146.00:00:05.53/valo/05,734.99,yes,locked 2006.146.00:00:05.53/valo/06,814.99,yes,locked 2006.146.00:00:05.53/valo/07,864.99,yes,locked 2006.146.00:00:05.53/valo/08,884.99,yes,locked 2006.146.00:00:06.62/vb/01,03,usb,yes,36,34 2006.146.00:00:06.62/vb/02,04,usb,yes,32,31 2006.146.00:00:06.62/vb/03,04,usb,yes,28,31 2006.146.00:00:06.62/vb/04,04,usb,yes,33,32 2006.146.00:00:06.62/vb/05,04,usb,yes,25,28 2006.146.00:00:06.62/vb/06,04,usb,yes,30,26 2006.146.00:00:06.62/vb/07,04,usb,yes,30,29 2006.146.00:00:06.62/vb/08,04,usb,yes,27,30 2006.146.00:00:06.85/vblo/01,629.99,yes,locked 2006.146.00:00:06.85/vblo/02,634.99,yes,locked 2006.146.00:00:06.85/vblo/03,649.99,yes,locked 2006.146.00:00:06.85/vblo/04,679.99,yes,locked 2006.146.00:00:06.85/vblo/05,709.99,yes,locked 2006.146.00:00:06.85/vblo/06,719.99,yes,locked 2006.146.00:00:06.85/vblo/07,734.99,yes,locked 2006.146.00:00:06.85/vblo/08,744.99,yes,locked 2006.146.00:00:07.00/vabw/8 2006.146.00:00:07.15/vbbw/8 2006.146.00:00:07.24/xfe/off,on,15.5 2006.146.00:00:07.62/ifatt/23,28,28,28 2006.146.00:00:08.07/fmout-gps/S +3.6E-08 2006.146.00:00:08.15:!2006.146.00:01:33 2006.146.00:01:33.01:data_valid=off 2006.146.00:01:33.02:"et 2006.146.00:01:33.02:!+3s 2006.146.00:01:36.05:"tape 2006.146.00:01:36.06:postob 2006.146.00:01:36.21/cable/+6.5442E-03 2006.146.00:01:36.22/wx/20.29,1020.5,72 2006.146.00:01:36.29/fmout-gps/S +3.5E-08 2006.146.00:01:36.29:scan_name=146-0005,jd0605,50 2006.146.00:01:36.30:source=0552+398,055530.81,394849.2,2000.0,cw 2006.146.00:01:37.13#flagr#flagr/antenna,new-source 2006.146.00:01:37.14:checkk5 2006.146.00:01:37.58/chk_autoobs//k5ts1/ autoobs is running! 2006.146.00:01:38.01/chk_autoobs//k5ts2/ autoobs is running! 2006.146.00:01:38.45/chk_autoobs//k5ts3/ autoobs is running! 2006.146.00:01:38.88/chk_autoobs//k5ts4/ autoobs is running! 2006.146.00:01:39.31/chk_obsdata//k5ts1/T1460000??a.dat file size is correct (nominal:360MB, actual:360MB). 2006.146.00:01:39.76/chk_obsdata//k5ts2/T1460000??b.dat file size is correct (nominal:360MB, actual:360MB). 2006.146.00:01:40.20/chk_obsdata//k5ts3/T1460000??c.dat file size is correct (nominal:360MB, actual:360MB). 2006.146.00:01:40.62/chk_obsdata//k5ts4/T1460000??d.dat file size is correct (nominal:360MB, actual:360MB). 2006.146.00:01:41.38/k5log//k5ts1_log_newline 2006.146.00:01:42.13/k5log//k5ts2_log_newline 2006.146.00:01:42.87/k5log//k5ts3_log_newline 2006.146.00:01:43.61/k5log//k5ts4_log_newline 2006.146.00:01:43.64/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.146.00:01:43.64:setupk4=1 2006.146.00:01:43.64$setupk4/echo=on 2006.146.00:01:43.64$setupk4/pcalon 2006.146.00:01:43.64$pcalon/"no phase cal control is implemented here 2006.146.00:01:43.64$setupk4/"tpicd=stop 2006.146.00:01:43.64$setupk4/"rec=synch_on 2006.146.00:01:43.64$setupk4/"rec_mode=128 2006.146.00:01:43.64$setupk4/!* 2006.146.00:01:43.64$setupk4/recpk4 2006.146.00:01:43.64$recpk4/recpatch= 2006.146.00:01:43.65$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.146.00:01:43.65$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.146.00:01:43.65$setupk4/vck44 2006.146.00:01:43.65$vck44/valo=1,524.99 2006.146.00:01:43.65#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.146.00:01:43.65#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.146.00:01:43.65#ibcon#ireg 17 cls_cnt 0 2006.146.00:01:43.65#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:01:43.65#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:01:43.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:01:43.68#ibcon#[26=FRQ=01,524.99\r\n] 2006.146.00:01:43.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:01:43.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:01:43.73#ibcon#about to clear, iclass 37 cls_cnt 0 2006.146.00:01:43.73#ibcon#cleared, iclass 37 cls_cnt 0 2006.146.00:01:43.73$vck44/va=1,8 2006.146.00:01:43.73#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.146.00:01:43.73#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.146.00:01:43.73#ibcon#ireg 11 cls_cnt 2 2006.146.00:01:43.73#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:01:43.73#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:01:43.73#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:01:43.75#ibcon#[25=AT01-08\r\n] 2006.146.00:01:43.78#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:01:43.78#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:01:43.78#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.146.00:01:43.78#ibcon#ireg 7 cls_cnt 0 2006.146.00:01:43.78#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:01:43.90#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:01:43.90#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:01:43.92#ibcon#[25=USB\r\n] 2006.146.00:01:43.97#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:01:43.97#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:01:43.97#ibcon#about to clear, iclass 39 cls_cnt 0 2006.146.00:01:43.97#ibcon#cleared, iclass 39 cls_cnt 0 2006.146.00:01:43.97$vck44/valo=2,534.99 2006.146.00:01:43.97#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.146.00:01:43.97#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.146.00:01:43.97#ibcon#ireg 17 cls_cnt 0 2006.146.00:01:43.97#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:01:43.97#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:01:43.97#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:01:43.98#ibcon#[26=FRQ=02,534.99\r\n] 2006.146.00:01:44.02#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:01:44.02#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:01:44.02#ibcon#about to clear, iclass 3 cls_cnt 0 2006.146.00:01:44.02#ibcon#cleared, iclass 3 cls_cnt 0 2006.146.00:01:44.02$vck44/va=2,7 2006.146.00:01:44.02#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.146.00:01:44.02#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.146.00:01:44.02#ibcon#ireg 11 cls_cnt 2 2006.146.00:01:44.02#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:01:44.09#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:01:44.09#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:01:44.11#ibcon#[25=AT02-07\r\n] 2006.146.00:01:44.14#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:01:44.14#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:01:44.14#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.146.00:01:44.14#ibcon#ireg 7 cls_cnt 0 2006.146.00:01:44.14#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:01:44.26#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:01:44.26#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:01:44.28#ibcon#[25=USB\r\n] 2006.146.00:01:44.31#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:01:44.31#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:01:44.31#ibcon#about to clear, iclass 5 cls_cnt 0 2006.146.00:01:44.31#ibcon#cleared, iclass 5 cls_cnt 0 2006.146.00:01:44.31$vck44/valo=3,564.99 2006.146.00:01:44.31#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.146.00:01:44.31#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.146.00:01:44.31#ibcon#ireg 17 cls_cnt 0 2006.146.00:01:44.31#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:01:44.31#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:01:44.31#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:01:44.33#ibcon#[26=FRQ=03,564.99\r\n] 2006.146.00:01:44.37#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:01:44.37#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:01:44.37#ibcon#about to clear, iclass 7 cls_cnt 0 2006.146.00:01:44.37#ibcon#cleared, iclass 7 cls_cnt 0 2006.146.00:01:44.37$vck44/va=3,8 2006.146.00:01:44.37#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.146.00:01:44.37#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.146.00:01:44.37#ibcon#ireg 11 cls_cnt 2 2006.146.00:01:44.37#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.146.00:01:44.43#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.146.00:01:44.43#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.146.00:01:44.45#ibcon#[25=AT03-08\r\n] 2006.146.00:01:44.48#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.146.00:01:44.48#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.146.00:01:44.48#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.146.00:01:44.48#ibcon#ireg 7 cls_cnt 0 2006.146.00:01:44.48#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.146.00:01:44.60#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.146.00:01:44.60#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.146.00:01:44.62#ibcon#[25=USB\r\n] 2006.146.00:01:44.65#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.146.00:01:44.65#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.146.00:01:44.65#ibcon#about to clear, iclass 11 cls_cnt 0 2006.146.00:01:44.65#ibcon#cleared, iclass 11 cls_cnt 0 2006.146.00:01:44.65$vck44/valo=4,624.99 2006.146.00:01:44.65#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.146.00:01:44.65#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.146.00:01:44.65#ibcon#ireg 17 cls_cnt 0 2006.146.00:01:44.65#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.146.00:01:44.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.146.00:01:44.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.146.00:01:44.67#ibcon#[26=FRQ=04,624.99\r\n] 2006.146.00:01:44.71#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.146.00:01:44.71#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.146.00:01:44.71#ibcon#about to clear, iclass 13 cls_cnt 0 2006.146.00:01:44.71#ibcon#cleared, iclass 13 cls_cnt 0 2006.146.00:01:44.71$vck44/va=4,7 2006.146.00:01:44.71#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.146.00:01:44.71#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.146.00:01:44.71#ibcon#ireg 11 cls_cnt 2 2006.146.00:01:44.71#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.146.00:01:44.77#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.146.00:01:44.77#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.146.00:01:44.79#ibcon#[25=AT04-07\r\n] 2006.146.00:01:44.82#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.146.00:01:44.82#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.146.00:01:44.82#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.146.00:01:44.82#ibcon#ireg 7 cls_cnt 0 2006.146.00:01:44.82#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.146.00:01:44.94#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.146.00:01:44.94#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.146.00:01:44.96#ibcon#[25=USB\r\n] 2006.146.00:01:44.99#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.146.00:01:44.99#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.146.00:01:44.99#ibcon#about to clear, iclass 15 cls_cnt 0 2006.146.00:01:44.99#ibcon#cleared, iclass 15 cls_cnt 0 2006.146.00:01:44.99$vck44/valo=5,734.99 2006.146.00:01:44.99#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.146.00:01:44.99#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.146.00:01:44.99#ibcon#ireg 17 cls_cnt 0 2006.146.00:01:44.99#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:01:44.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:01:44.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:01:45.01#ibcon#[26=FRQ=05,734.99\r\n] 2006.146.00:01:45.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:01:45.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:01:45.05#ibcon#about to clear, iclass 17 cls_cnt 0 2006.146.00:01:45.05#ibcon#cleared, iclass 17 cls_cnt 0 2006.146.00:01:45.05$vck44/va=5,4 2006.146.00:01:45.05#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.146.00:01:45.05#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.146.00:01:45.05#ibcon#ireg 11 cls_cnt 2 2006.146.00:01:45.05#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:01:45.11#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:01:45.11#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:01:45.13#ibcon#[25=AT05-04\r\n] 2006.146.00:01:45.16#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:01:45.16#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:01:45.16#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.146.00:01:45.16#ibcon#ireg 7 cls_cnt 0 2006.146.00:01:45.16#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:01:45.28#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:01:45.28#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:01:45.30#ibcon#[25=USB\r\n] 2006.146.00:01:45.33#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:01:45.33#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:01:45.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.146.00:01:45.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.146.00:01:45.33$vck44/valo=6,814.99 2006.146.00:01:45.33#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.146.00:01:45.33#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.146.00:01:45.33#ibcon#ireg 17 cls_cnt 0 2006.146.00:01:45.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:01:45.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:01:45.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:01:45.35#ibcon#[26=FRQ=06,814.99\r\n] 2006.146.00:01:45.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:01:45.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:01:45.39#ibcon#about to clear, iclass 21 cls_cnt 0 2006.146.00:01:45.39#ibcon#cleared, iclass 21 cls_cnt 0 2006.146.00:01:45.39$vck44/va=6,4 2006.146.00:01:45.39#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.146.00:01:45.39#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.146.00:01:45.39#ibcon#ireg 11 cls_cnt 2 2006.146.00:01:45.39#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:01:45.45#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:01:45.45#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:01:45.47#ibcon#[25=AT06-04\r\n] 2006.146.00:01:45.50#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:01:45.50#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:01:45.50#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.146.00:01:45.50#ibcon#ireg 7 cls_cnt 0 2006.146.00:01:45.50#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:01:45.62#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:01:45.62#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:01:45.64#ibcon#[25=USB\r\n] 2006.146.00:01:45.67#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:01:45.67#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:01:45.67#ibcon#about to clear, iclass 23 cls_cnt 0 2006.146.00:01:45.67#ibcon#cleared, iclass 23 cls_cnt 0 2006.146.00:01:45.67$vck44/valo=7,864.99 2006.146.00:01:45.67#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.146.00:01:45.67#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.146.00:01:45.67#ibcon#ireg 17 cls_cnt 0 2006.146.00:01:45.67#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:01:45.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:01:45.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:01:45.69#ibcon#[26=FRQ=07,864.99\r\n] 2006.146.00:01:45.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:01:45.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:01:45.73#ibcon#about to clear, iclass 25 cls_cnt 0 2006.146.00:01:45.73#ibcon#cleared, iclass 25 cls_cnt 0 2006.146.00:01:45.73$vck44/va=7,4 2006.146.00:01:45.73#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.146.00:01:45.73#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.146.00:01:45.73#ibcon#ireg 11 cls_cnt 2 2006.146.00:01:45.73#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.146.00:01:45.79#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.146.00:01:45.79#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.146.00:01:45.81#ibcon#[25=AT07-04\r\n] 2006.146.00:01:45.84#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.146.00:01:45.84#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.146.00:01:45.84#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.146.00:01:45.84#ibcon#ireg 7 cls_cnt 0 2006.146.00:01:45.84#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.146.00:01:45.96#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.146.00:01:45.96#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.146.00:01:45.98#ibcon#[25=USB\r\n] 2006.146.00:01:46.01#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.146.00:01:46.01#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.146.00:01:46.01#ibcon#about to clear, iclass 27 cls_cnt 0 2006.146.00:01:46.01#ibcon#cleared, iclass 27 cls_cnt 0 2006.146.00:01:46.01$vck44/valo=8,884.99 2006.146.00:01:46.01#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.146.00:01:46.01#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.146.00:01:46.01#ibcon#ireg 17 cls_cnt 0 2006.146.00:01:46.01#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:01:46.01#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:01:46.01#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:01:46.03#ibcon#[26=FRQ=08,884.99\r\n] 2006.146.00:01:46.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:01:46.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:01:46.07#ibcon#about to clear, iclass 29 cls_cnt 0 2006.146.00:01:46.07#ibcon#cleared, iclass 29 cls_cnt 0 2006.146.00:01:46.07$vck44/va=8,4 2006.146.00:01:46.07#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.146.00:01:46.07#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.146.00:01:46.07#ibcon#ireg 11 cls_cnt 2 2006.146.00:01:46.07#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.146.00:01:46.13#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.146.00:01:46.13#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.146.00:01:46.15#ibcon#[25=AT08-04\r\n] 2006.146.00:01:46.18#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.146.00:01:46.18#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.146.00:01:46.18#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.146.00:01:46.18#ibcon#ireg 7 cls_cnt 0 2006.146.00:01:46.18#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.146.00:01:46.30#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.146.00:01:46.30#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.146.00:01:46.33#ibcon#[25=USB\r\n] 2006.146.00:01:46.36#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.146.00:01:46.36#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.146.00:01:46.36#ibcon#about to clear, iclass 31 cls_cnt 0 2006.146.00:01:46.36#ibcon#cleared, iclass 31 cls_cnt 0 2006.146.00:01:46.36$vck44/vblo=1,629.99 2006.146.00:01:46.36#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.146.00:01:46.36#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.146.00:01:46.36#ibcon#ireg 17 cls_cnt 0 2006.146.00:01:46.36#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.146.00:01:46.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.146.00:01:46.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.146.00:01:46.38#ibcon#[28=FRQ=01,629.99\r\n] 2006.146.00:01:46.42#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.146.00:01:46.42#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.146.00:01:46.42#ibcon#about to clear, iclass 33 cls_cnt 0 2006.146.00:01:46.42#ibcon#cleared, iclass 33 cls_cnt 0 2006.146.00:01:46.42$vck44/vb=1,3 2006.146.00:01:46.42#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.146.00:01:46.42#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.146.00:01:46.42#ibcon#ireg 11 cls_cnt 2 2006.146.00:01:46.42#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.146.00:01:46.42#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.146.00:01:46.42#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.146.00:01:46.44#ibcon#[27=AT01-03\r\n] 2006.146.00:01:46.47#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.146.00:01:46.47#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.146.00:01:46.47#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.146.00:01:46.47#ibcon#ireg 7 cls_cnt 0 2006.146.00:01:46.47#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.146.00:01:46.59#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.146.00:01:46.59#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.146.00:01:46.61#ibcon#[27=USB\r\n] 2006.146.00:01:46.64#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.146.00:01:46.64#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.146.00:01:46.64#ibcon#about to clear, iclass 35 cls_cnt 0 2006.146.00:01:46.64#ibcon#cleared, iclass 35 cls_cnt 0 2006.146.00:01:46.64$vck44/vblo=2,634.99 2006.146.00:01:46.64#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.146.00:01:46.64#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.146.00:01:46.64#ibcon#ireg 17 cls_cnt 0 2006.146.00:01:46.64#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:01:46.64#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:01:46.64#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:01:46.66#ibcon#[28=FRQ=02,634.99\r\n] 2006.146.00:01:46.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:01:46.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:01:46.70#ibcon#about to clear, iclass 37 cls_cnt 0 2006.146.00:01:46.70#ibcon#cleared, iclass 37 cls_cnt 0 2006.146.00:01:46.70$vck44/vb=2,4 2006.146.00:01:46.70#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.146.00:01:46.70#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.146.00:01:46.70#ibcon#ireg 11 cls_cnt 2 2006.146.00:01:46.70#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:01:46.76#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:01:46.76#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:01:46.78#ibcon#[27=AT02-04\r\n] 2006.146.00:01:46.81#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:01:46.81#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:01:46.81#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.146.00:01:46.81#ibcon#ireg 7 cls_cnt 0 2006.146.00:01:46.81#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:01:46.93#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:01:46.93#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:01:46.95#ibcon#[27=USB\r\n] 2006.146.00:01:46.98#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:01:46.98#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:01:46.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.146.00:01:46.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.146.00:01:46.98$vck44/vblo=3,649.99 2006.146.00:01:46.98#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.146.00:01:46.98#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.146.00:01:46.98#ibcon#ireg 17 cls_cnt 0 2006.146.00:01:46.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:01:46.98#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:01:46.98#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:01:47.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.146.00:01:47.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:01:47.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:01:47.04#ibcon#about to clear, iclass 3 cls_cnt 0 2006.146.00:01:47.04#ibcon#cleared, iclass 3 cls_cnt 0 2006.146.00:01:47.04$vck44/vb=3,4 2006.146.00:01:47.04#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.146.00:01:47.04#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.146.00:01:47.04#ibcon#ireg 11 cls_cnt 2 2006.146.00:01:47.04#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:01:47.10#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:01:47.10#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:01:47.12#ibcon#[27=AT03-04\r\n] 2006.146.00:01:47.15#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:01:47.15#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:01:47.15#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.146.00:01:47.15#ibcon#ireg 7 cls_cnt 0 2006.146.00:01:47.15#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:01:47.27#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:01:47.27#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:01:47.29#ibcon#[27=USB\r\n] 2006.146.00:01:47.32#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:01:47.32#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:01:47.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.146.00:01:47.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.146.00:01:47.32$vck44/vblo=4,679.99 2006.146.00:01:47.32#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.146.00:01:47.32#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.146.00:01:47.32#ibcon#ireg 17 cls_cnt 0 2006.146.00:01:47.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:01:47.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:01:47.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:01:47.34#ibcon#[28=FRQ=04,679.99\r\n] 2006.146.00:01:47.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:01:47.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:01:47.38#ibcon#about to clear, iclass 7 cls_cnt 0 2006.146.00:01:47.38#ibcon#cleared, iclass 7 cls_cnt 0 2006.146.00:01:47.38$vck44/vb=4,4 2006.146.00:01:47.38#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.146.00:01:47.38#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.146.00:01:47.38#ibcon#ireg 11 cls_cnt 2 2006.146.00:01:47.38#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.146.00:01:47.44#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.146.00:01:47.44#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.146.00:01:47.46#ibcon#[27=AT04-04\r\n] 2006.146.00:01:47.49#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.146.00:01:47.49#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.146.00:01:47.49#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.146.00:01:47.49#ibcon#ireg 7 cls_cnt 0 2006.146.00:01:47.49#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.146.00:01:47.61#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.146.00:01:47.61#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.146.00:01:47.63#ibcon#[27=USB\r\n] 2006.146.00:01:47.66#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.146.00:01:47.66#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.146.00:01:47.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.146.00:01:47.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.146.00:01:47.66$vck44/vblo=5,709.99 2006.146.00:01:47.66#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.146.00:01:47.66#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.146.00:01:47.66#ibcon#ireg 17 cls_cnt 0 2006.146.00:01:47.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.146.00:01:47.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.146.00:01:47.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.146.00:01:47.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.146.00:01:47.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.146.00:01:47.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.146.00:01:47.72#ibcon#about to clear, iclass 13 cls_cnt 0 2006.146.00:01:47.72#ibcon#cleared, iclass 13 cls_cnt 0 2006.146.00:01:47.72$vck44/vb=5,4 2006.146.00:01:47.72#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.146.00:01:47.72#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.146.00:01:47.72#ibcon#ireg 11 cls_cnt 2 2006.146.00:01:47.72#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.146.00:01:47.78#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.146.00:01:47.78#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.146.00:01:47.80#ibcon#[27=AT05-04\r\n] 2006.146.00:01:47.83#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.146.00:01:47.83#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.146.00:01:47.83#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.146.00:01:47.83#ibcon#ireg 7 cls_cnt 0 2006.146.00:01:47.83#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.146.00:01:47.95#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.146.00:01:47.95#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.146.00:01:47.97#ibcon#[27=USB\r\n] 2006.146.00:01:48.00#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.146.00:01:48.00#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.146.00:01:48.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.146.00:01:48.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.146.00:01:48.00$vck44/vblo=6,719.99 2006.146.00:01:48.00#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.146.00:01:48.00#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.146.00:01:48.00#ibcon#ireg 17 cls_cnt 0 2006.146.00:01:48.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:01:48.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:01:48.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:01:48.02#ibcon#[28=FRQ=06,719.99\r\n] 2006.146.00:01:48.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:01:48.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:01:48.06#ibcon#about to clear, iclass 17 cls_cnt 0 2006.146.00:01:48.06#ibcon#cleared, iclass 17 cls_cnt 0 2006.146.00:01:48.06$vck44/vb=6,4 2006.146.00:01:48.06#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.146.00:01:48.06#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.146.00:01:48.06#ibcon#ireg 11 cls_cnt 2 2006.146.00:01:48.06#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:01:48.12#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:01:48.12#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:01:48.14#ibcon#[27=AT06-04\r\n] 2006.146.00:01:48.17#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:01:48.17#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:01:48.17#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.146.00:01:48.17#ibcon#ireg 7 cls_cnt 0 2006.146.00:01:48.17#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:01:48.29#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:01:48.29#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:01:48.31#ibcon#[27=USB\r\n] 2006.146.00:01:48.34#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:01:48.34#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:01:48.34#ibcon#about to clear, iclass 19 cls_cnt 0 2006.146.00:01:48.34#ibcon#cleared, iclass 19 cls_cnt 0 2006.146.00:01:48.34$vck44/vblo=7,734.99 2006.146.00:01:48.34#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.146.00:01:48.34#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.146.00:01:48.34#ibcon#ireg 17 cls_cnt 0 2006.146.00:01:48.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:01:48.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:01:48.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:01:48.36#ibcon#[28=FRQ=07,734.99\r\n] 2006.146.00:01:48.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:01:48.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:01:48.40#ibcon#about to clear, iclass 21 cls_cnt 0 2006.146.00:01:48.40#ibcon#cleared, iclass 21 cls_cnt 0 2006.146.00:01:48.40$vck44/vb=7,4 2006.146.00:01:48.40#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.146.00:01:48.40#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.146.00:01:48.40#ibcon#ireg 11 cls_cnt 2 2006.146.00:01:48.40#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:01:48.46#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:01:48.46#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:01:48.48#ibcon#[27=AT07-04\r\n] 2006.146.00:01:48.51#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:01:48.51#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:01:48.51#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.146.00:01:48.51#ibcon#ireg 7 cls_cnt 0 2006.146.00:01:48.51#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:01:48.63#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:01:48.63#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:01:48.65#ibcon#[27=USB\r\n] 2006.146.00:01:48.68#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:01:48.68#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:01:48.68#ibcon#about to clear, iclass 23 cls_cnt 0 2006.146.00:01:48.68#ibcon#cleared, iclass 23 cls_cnt 0 2006.146.00:01:48.68$vck44/vblo=8,744.99 2006.146.00:01:48.68#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.146.00:01:48.68#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.146.00:01:48.68#ibcon#ireg 17 cls_cnt 0 2006.146.00:01:48.68#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:01:48.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:01:48.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:01:48.70#ibcon#[28=FRQ=08,744.99\r\n] 2006.146.00:01:48.74#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:01:48.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:01:48.74#ibcon#about to clear, iclass 25 cls_cnt 0 2006.146.00:01:48.74#ibcon#cleared, iclass 25 cls_cnt 0 2006.146.00:01:48.74$vck44/vb=8,4 2006.146.00:01:48.74#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.146.00:01:48.74#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.146.00:01:48.74#ibcon#ireg 11 cls_cnt 2 2006.146.00:01:48.74#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.146.00:01:48.80#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.146.00:01:48.80#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.146.00:01:48.82#ibcon#[27=AT08-04\r\n] 2006.146.00:01:48.85#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.146.00:01:48.85#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.146.00:01:48.85#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.146.00:01:48.85#ibcon#ireg 7 cls_cnt 0 2006.146.00:01:48.85#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.146.00:01:48.97#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.146.00:01:48.97#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.146.00:01:48.99#ibcon#[27=USB\r\n] 2006.146.00:01:49.02#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.146.00:01:49.02#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.146.00:01:49.02#ibcon#about to clear, iclass 27 cls_cnt 0 2006.146.00:01:49.02#ibcon#cleared, iclass 27 cls_cnt 0 2006.146.00:01:49.02$vck44/vabw=wide 2006.146.00:01:49.02#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.146.00:01:49.02#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.146.00:01:49.02#ibcon#ireg 8 cls_cnt 0 2006.146.00:01:49.02#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:01:49.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:01:49.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:01:49.04#ibcon#[25=BW32\r\n] 2006.146.00:01:49.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:01:49.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:01:49.07#ibcon#about to clear, iclass 29 cls_cnt 0 2006.146.00:01:49.07#ibcon#cleared, iclass 29 cls_cnt 0 2006.146.00:01:49.07$vck44/vbbw=wide 2006.146.00:01:49.07#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.146.00:01:49.07#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.146.00:01:49.07#ibcon#ireg 8 cls_cnt 0 2006.146.00:01:49.07#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.146.00:01:49.14#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.146.00:01:49.14#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.146.00:01:49.16#ibcon#[27=BW32\r\n] 2006.146.00:01:49.19#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.146.00:01:49.19#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.146.00:01:49.19#ibcon#about to clear, iclass 31 cls_cnt 0 2006.146.00:01:49.19#ibcon#cleared, iclass 31 cls_cnt 0 2006.146.00:01:49.19$setupk4/ifdk4 2006.146.00:01:49.19$ifdk4/lo= 2006.146.00:01:49.19$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.146.00:01:49.19$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.146.00:01:49.19$ifdk4/patch= 2006.146.00:01:49.19$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.146.00:01:49.19$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.146.00:01:49.19$setupk4/!*+20s 2006.146.00:01:52.81#abcon#<5=/08 2.0 6.4 20.29 721020.5\r\n> 2006.146.00:01:52.83#abcon#{5=INTERFACE CLEAR} 2006.146.00:01:52.89#abcon#[5=S1D000X0/0*\r\n] 2006.146.00:01:59.13#trakl#Source acquired 2006.146.00:02:00.13#flagr#flagr/antenna,acquired 2006.146.00:02:02.98#abcon#<5=/08 2.0 6.4 20.28 731020.5\r\n> 2006.146.00:02:03.00#abcon#{5=INTERFACE CLEAR} 2006.146.00:02:03.06#abcon#[5=S1D000X0/0*\r\n] 2006.146.00:02:03.65$setupk4/"tpicd 2006.146.00:02:03.65$setupk4/echo=off 2006.146.00:02:03.65$setupk4/xlog=off 2006.146.00:02:03.65:!2006.146.00:05:09 2006.146.00:05:09.00:preob 2006.146.00:05:10.14/onsource/TRACKING 2006.146.00:05:10.14:!2006.146.00:05:19 2006.146.00:05:19.00:"tape 2006.146.00:05:19.00:"st=record 2006.146.00:05:19.00:data_valid=on 2006.146.00:05:19.00:midob 2006.146.00:05:19.14/onsource/TRACKING 2006.146.00:05:19.14/wx/20.29,1020.6,74 2006.146.00:05:19.24/cable/+6.5464E-03 2006.146.00:05:20.33/va/01,08,usb,yes,29,31 2006.146.00:05:20.33/va/02,07,usb,yes,31,31 2006.146.00:05:20.33/va/03,08,usb,yes,28,29 2006.146.00:05:20.33/va/04,07,usb,yes,32,33 2006.146.00:05:20.33/va/05,04,usb,yes,28,28 2006.146.00:05:20.33/va/06,04,usb,yes,31,31 2006.146.00:05:20.33/va/07,04,usb,yes,31,32 2006.146.00:05:20.33/va/08,04,usb,yes,27,32 2006.146.00:05:20.56/valo/01,524.99,yes,locked 2006.146.00:05:20.56/valo/02,534.99,yes,locked 2006.146.00:05:20.56/valo/03,564.99,yes,locked 2006.146.00:05:20.56/valo/04,624.99,yes,locked 2006.146.00:05:20.56/valo/05,734.99,yes,locked 2006.146.00:05:20.56/valo/06,814.99,yes,locked 2006.146.00:05:20.56/valo/07,864.99,yes,locked 2006.146.00:05:20.56/valo/08,884.99,yes,locked 2006.146.00:05:21.65/vb/01,03,usb,yes,36,33 2006.146.00:05:21.65/vb/02,04,usb,yes,31,31 2006.146.00:05:21.65/vb/03,04,usb,yes,28,31 2006.146.00:05:21.65/vb/04,04,usb,yes,32,31 2006.146.00:05:21.65/vb/05,04,usb,yes,25,28 2006.146.00:05:21.65/vb/06,04,usb,yes,30,26 2006.146.00:05:21.65/vb/07,04,usb,yes,29,29 2006.146.00:05:21.65/vb/08,04,usb,yes,27,30 2006.146.00:05:21.89/vblo/01,629.99,yes,locked 2006.146.00:05:21.89/vblo/02,634.99,yes,locked 2006.146.00:05:21.89/vblo/03,649.99,yes,locked 2006.146.00:05:21.89/vblo/04,679.99,yes,locked 2006.146.00:05:21.89/vblo/05,709.99,yes,locked 2006.146.00:05:21.89/vblo/06,719.99,yes,locked 2006.146.00:05:21.89/vblo/07,734.99,yes,locked 2006.146.00:05:21.89/vblo/08,744.99,yes,locked 2006.146.00:05:22.04/vabw/8 2006.146.00:05:22.19/vbbw/8 2006.146.00:05:22.28/xfe/off,on,14.7 2006.146.00:05:22.66/ifatt/23,28,28,28 2006.146.00:05:23.07/fmout-gps/S +3.7E-08 2006.146.00:05:23.11:!2006.146.00:06:09 2006.146.00:06:09.01:data_valid=off 2006.146.00:06:09.02:"et 2006.146.00:06:09.02:!+3s 2006.146.00:06:12.03:"tape 2006.146.00:06:12.04:postob 2006.146.00:06:12.24/cable/+6.5451E-03 2006.146.00:06:12.25/wx/20.29,1020.6,75 2006.146.00:06:12.32/fmout-gps/S +3.7E-08 2006.146.00:06:12.32:scan_name=146-0008,jd0605,310 2006.146.00:06:12.32:source=nrao150,035929.75,505750.2,2000.0,cw 2006.146.00:06:13.14#flagr#flagr/antenna,new-source 2006.146.00:06:13.14:checkk5 2006.146.00:06:13.59/chk_autoobs//k5ts1/ autoobs is running! 2006.146.00:06:14.02/chk_autoobs//k5ts2/ autoobs is running! 2006.146.00:06:14.47/chk_autoobs//k5ts3/ autoobs is running! 2006.146.00:06:14.89/chk_autoobs//k5ts4/ autoobs is running! 2006.146.00:06:15.32/chk_obsdata//k5ts1/T1460005??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.146.00:06:15.76/chk_obsdata//k5ts2/T1460005??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.146.00:06:16.19/chk_obsdata//k5ts3/T1460005??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.146.00:06:16.64/chk_obsdata//k5ts4/T1460005??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.146.00:06:17.40/k5log//k5ts1_log_newline 2006.146.00:06:18.14/k5log//k5ts2_log_newline 2006.146.00:06:18.90/k5log//k5ts3_log_newline 2006.146.00:06:19.65/k5log//k5ts4_log_newline 2006.146.00:06:19.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.146.00:06:19.67:setupk4=1 2006.146.00:06:19.67$setupk4/echo=on 2006.146.00:06:19.67$setupk4/pcalon 2006.146.00:06:19.67$pcalon/"no phase cal control is implemented here 2006.146.00:06:19.67$setupk4/"tpicd=stop 2006.146.00:06:19.67$setupk4/"rec=synch_on 2006.146.00:06:19.67$setupk4/"rec_mode=128 2006.146.00:06:19.67$setupk4/!* 2006.146.00:06:19.67$setupk4/recpk4 2006.146.00:06:19.67$recpk4/recpatch= 2006.146.00:06:19.68$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.146.00:06:19.68$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.146.00:06:19.68$setupk4/vck44 2006.146.00:06:19.68$vck44/valo=1,524.99 2006.146.00:06:19.68#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.146.00:06:19.68#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.146.00:06:19.68#ibcon#ireg 17 cls_cnt 0 2006.146.00:06:19.68#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.146.00:06:19.68#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.146.00:06:19.68#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.146.00:06:19.71#ibcon#[26=FRQ=01,524.99\r\n] 2006.146.00:06:19.76#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.146.00:06:19.76#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.146.00:06:19.76#ibcon#about to clear, iclass 36 cls_cnt 0 2006.146.00:06:19.76#ibcon#cleared, iclass 36 cls_cnt 0 2006.146.00:06:19.76$vck44/va=1,8 2006.146.00:06:19.76#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.146.00:06:19.76#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.146.00:06:19.76#ibcon#ireg 11 cls_cnt 2 2006.146.00:06:19.76#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.146.00:06:19.76#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.146.00:06:19.76#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.146.00:06:19.78#ibcon#[25=AT01-08\r\n] 2006.146.00:06:19.81#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.146.00:06:19.81#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.146.00:06:19.81#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.146.00:06:19.81#ibcon#ireg 7 cls_cnt 0 2006.146.00:06:19.81#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.146.00:06:19.93#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.146.00:06:19.93#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.146.00:06:19.95#ibcon#[25=USB\r\n] 2006.146.00:06:20.01#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.146.00:06:20.01#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.146.00:06:20.01#ibcon#about to clear, iclass 38 cls_cnt 0 2006.146.00:06:20.01#ibcon#cleared, iclass 38 cls_cnt 0 2006.146.00:06:20.01$vck44/valo=2,534.99 2006.146.00:06:20.01#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.146.00:06:20.01#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.146.00:06:20.01#ibcon#ireg 17 cls_cnt 0 2006.146.00:06:20.01#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.146.00:06:20.01#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.146.00:06:20.01#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.146.00:06:20.03#ibcon#[26=FRQ=02,534.99\r\n] 2006.146.00:06:20.07#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.146.00:06:20.07#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.146.00:06:20.07#ibcon#about to clear, iclass 40 cls_cnt 0 2006.146.00:06:20.07#ibcon#cleared, iclass 40 cls_cnt 0 2006.146.00:06:20.08$vck44/va=2,7 2006.146.00:06:20.08#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.146.00:06:20.08#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.146.00:06:20.08#ibcon#ireg 11 cls_cnt 2 2006.146.00:06:20.08#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.146.00:06:20.12#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.146.00:06:20.12#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.146.00:06:20.14#ibcon#[25=AT02-07\r\n] 2006.146.00:06:20.17#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.146.00:06:20.17#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.146.00:06:20.17#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.146.00:06:20.17#ibcon#ireg 7 cls_cnt 0 2006.146.00:06:20.17#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.146.00:06:20.29#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.146.00:06:20.29#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.146.00:06:20.31#ibcon#[25=USB\r\n] 2006.146.00:06:20.34#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.146.00:06:20.34#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.146.00:06:20.34#ibcon#about to clear, iclass 4 cls_cnt 0 2006.146.00:06:20.34#ibcon#cleared, iclass 4 cls_cnt 0 2006.146.00:06:20.34$vck44/valo=3,564.99 2006.146.00:06:20.34#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.146.00:06:20.34#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.146.00:06:20.34#ibcon#ireg 17 cls_cnt 0 2006.146.00:06:20.34#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.146.00:06:20.34#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.146.00:06:20.34#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.146.00:06:20.36#ibcon#[26=FRQ=03,564.99\r\n] 2006.146.00:06:20.40#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.146.00:06:20.40#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.146.00:06:20.40#ibcon#about to clear, iclass 6 cls_cnt 0 2006.146.00:06:20.40#ibcon#cleared, iclass 6 cls_cnt 0 2006.146.00:06:20.40$vck44/va=3,8 2006.146.00:06:20.40#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.146.00:06:20.40#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.146.00:06:20.40#ibcon#ireg 11 cls_cnt 2 2006.146.00:06:20.40#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.146.00:06:20.46#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.146.00:06:20.46#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.146.00:06:20.48#ibcon#[25=AT03-08\r\n] 2006.146.00:06:20.51#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.146.00:06:20.51#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.146.00:06:20.51#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.146.00:06:20.51#ibcon#ireg 7 cls_cnt 0 2006.146.00:06:20.51#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.146.00:06:20.63#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.146.00:06:20.63#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.146.00:06:20.65#ibcon#[25=USB\r\n] 2006.146.00:06:20.68#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.146.00:06:20.68#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.146.00:06:20.68#ibcon#about to clear, iclass 10 cls_cnt 0 2006.146.00:06:20.68#ibcon#cleared, iclass 10 cls_cnt 0 2006.146.00:06:20.68$vck44/valo=4,624.99 2006.146.00:06:20.68#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.146.00:06:20.68#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.146.00:06:20.68#ibcon#ireg 17 cls_cnt 0 2006.146.00:06:20.68#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.146.00:06:20.68#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.146.00:06:20.68#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.146.00:06:20.70#ibcon#[26=FRQ=04,624.99\r\n] 2006.146.00:06:20.74#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.146.00:06:20.74#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.146.00:06:20.74#ibcon#about to clear, iclass 12 cls_cnt 0 2006.146.00:06:20.74#ibcon#cleared, iclass 12 cls_cnt 0 2006.146.00:06:20.74$vck44/va=4,7 2006.146.00:06:20.74#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.146.00:06:20.74#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.146.00:06:20.74#ibcon#ireg 11 cls_cnt 2 2006.146.00:06:20.74#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.146.00:06:20.80#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.146.00:06:20.80#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.146.00:06:20.82#ibcon#[25=AT04-07\r\n] 2006.146.00:06:20.85#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.146.00:06:20.85#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.146.00:06:20.85#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.146.00:06:20.85#ibcon#ireg 7 cls_cnt 0 2006.146.00:06:20.85#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.146.00:06:20.97#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.146.00:06:20.97#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.146.00:06:20.99#ibcon#[25=USB\r\n] 2006.146.00:06:21.02#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.146.00:06:21.02#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.146.00:06:21.02#ibcon#about to clear, iclass 14 cls_cnt 0 2006.146.00:06:21.02#ibcon#cleared, iclass 14 cls_cnt 0 2006.146.00:06:21.02$vck44/valo=5,734.99 2006.146.00:06:21.02#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.146.00:06:21.02#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.146.00:06:21.02#ibcon#ireg 17 cls_cnt 0 2006.146.00:06:21.02#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.146.00:06:21.02#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.146.00:06:21.02#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.146.00:06:21.04#ibcon#[26=FRQ=05,734.99\r\n] 2006.146.00:06:21.08#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.146.00:06:21.08#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.146.00:06:21.08#ibcon#about to clear, iclass 16 cls_cnt 0 2006.146.00:06:21.08#ibcon#cleared, iclass 16 cls_cnt 0 2006.146.00:06:21.08$vck44/va=5,4 2006.146.00:06:21.08#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.146.00:06:21.08#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.146.00:06:21.08#ibcon#ireg 11 cls_cnt 2 2006.146.00:06:21.08#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.146.00:06:21.15#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.146.00:06:21.15#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.146.00:06:21.16#ibcon#[25=AT05-04\r\n] 2006.146.00:06:21.19#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.146.00:06:21.19#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.146.00:06:21.19#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.146.00:06:21.19#ibcon#ireg 7 cls_cnt 0 2006.146.00:06:21.19#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.146.00:06:21.31#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.146.00:06:21.31#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.146.00:06:21.33#ibcon#[25=USB\r\n] 2006.146.00:06:21.36#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.146.00:06:21.36#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.146.00:06:21.36#ibcon#about to clear, iclass 18 cls_cnt 0 2006.146.00:06:21.36#ibcon#cleared, iclass 18 cls_cnt 0 2006.146.00:06:21.36$vck44/valo=6,814.99 2006.146.00:06:21.36#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.146.00:06:21.36#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.146.00:06:21.36#ibcon#ireg 17 cls_cnt 0 2006.146.00:06:21.36#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.146.00:06:21.36#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.146.00:06:21.36#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.146.00:06:21.39#ibcon#[26=FRQ=06,814.99\r\n] 2006.146.00:06:21.43#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.146.00:06:21.43#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.146.00:06:21.43#ibcon#about to clear, iclass 20 cls_cnt 0 2006.146.00:06:21.43#ibcon#cleared, iclass 20 cls_cnt 0 2006.146.00:06:21.43$vck44/va=6,4 2006.146.00:06:21.43#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.146.00:06:21.43#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.146.00:06:21.43#ibcon#ireg 11 cls_cnt 2 2006.146.00:06:21.43#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.146.00:06:21.48#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.146.00:06:21.48#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.146.00:06:21.50#ibcon#[25=AT06-04\r\n] 2006.146.00:06:21.53#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.146.00:06:21.53#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.146.00:06:21.53#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.146.00:06:21.53#ibcon#ireg 7 cls_cnt 0 2006.146.00:06:21.53#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.146.00:06:21.65#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.146.00:06:21.65#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.146.00:06:21.67#ibcon#[25=USB\r\n] 2006.146.00:06:21.70#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.146.00:06:21.70#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.146.00:06:21.70#ibcon#about to clear, iclass 22 cls_cnt 0 2006.146.00:06:21.70#ibcon#cleared, iclass 22 cls_cnt 0 2006.146.00:06:21.70$vck44/valo=7,864.99 2006.146.00:06:21.70#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.146.00:06:21.70#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.146.00:06:21.70#ibcon#ireg 17 cls_cnt 0 2006.146.00:06:21.70#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.146.00:06:21.70#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.146.00:06:21.70#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.146.00:06:21.72#ibcon#[26=FRQ=07,864.99\r\n] 2006.146.00:06:21.76#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.146.00:06:21.76#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.146.00:06:21.76#ibcon#about to clear, iclass 24 cls_cnt 0 2006.146.00:06:21.76#ibcon#cleared, iclass 24 cls_cnt 0 2006.146.00:06:21.76$vck44/va=7,4 2006.146.00:06:21.76#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.146.00:06:21.76#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.146.00:06:21.76#ibcon#ireg 11 cls_cnt 2 2006.146.00:06:21.76#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.146.00:06:21.82#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.146.00:06:21.82#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.146.00:06:21.84#ibcon#[25=AT07-04\r\n] 2006.146.00:06:21.87#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.146.00:06:21.87#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.146.00:06:21.87#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.146.00:06:21.87#ibcon#ireg 7 cls_cnt 0 2006.146.00:06:21.87#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.146.00:06:21.99#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.146.00:06:21.99#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.146.00:06:22.01#ibcon#[25=USB\r\n] 2006.146.00:06:22.04#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.146.00:06:22.04#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.146.00:06:22.04#ibcon#about to clear, iclass 26 cls_cnt 0 2006.146.00:06:22.04#ibcon#cleared, iclass 26 cls_cnt 0 2006.146.00:06:22.04$vck44/valo=8,884.99 2006.146.00:06:22.04#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.146.00:06:22.04#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.146.00:06:22.04#ibcon#ireg 17 cls_cnt 0 2006.146.00:06:22.04#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.146.00:06:22.04#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.146.00:06:22.04#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.146.00:06:22.06#ibcon#[26=FRQ=08,884.99\r\n] 2006.146.00:06:22.10#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.146.00:06:22.10#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.146.00:06:22.10#ibcon#about to clear, iclass 28 cls_cnt 0 2006.146.00:06:22.10#ibcon#cleared, iclass 28 cls_cnt 0 2006.146.00:06:22.10$vck44/va=8,4 2006.146.00:06:22.10#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.146.00:06:22.10#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.146.00:06:22.10#ibcon#ireg 11 cls_cnt 2 2006.146.00:06:22.10#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.146.00:06:22.16#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.146.00:06:22.16#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.146.00:06:22.18#ibcon#[25=AT08-04\r\n] 2006.146.00:06:22.21#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.146.00:06:22.21#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.146.00:06:22.21#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.146.00:06:22.21#ibcon#ireg 7 cls_cnt 0 2006.146.00:06:22.21#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.146.00:06:22.33#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.146.00:06:22.33#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.146.00:06:22.35#ibcon#[25=USB\r\n] 2006.146.00:06:22.38#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.146.00:06:22.38#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.146.00:06:22.38#ibcon#about to clear, iclass 30 cls_cnt 0 2006.146.00:06:22.38#ibcon#cleared, iclass 30 cls_cnt 0 2006.146.00:06:22.38$vck44/vblo=1,629.99 2006.146.00:06:22.38#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.146.00:06:22.38#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.146.00:06:22.38#ibcon#ireg 17 cls_cnt 0 2006.146.00:06:22.38#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.146.00:06:22.38#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.146.00:06:22.38#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.146.00:06:22.40#ibcon#[28=FRQ=01,629.99\r\n] 2006.146.00:06:22.44#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.146.00:06:22.44#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.146.00:06:22.44#ibcon#about to clear, iclass 32 cls_cnt 0 2006.146.00:06:22.44#ibcon#cleared, iclass 32 cls_cnt 0 2006.146.00:06:22.44$vck44/vb=1,3 2006.146.00:06:22.44#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.146.00:06:22.44#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.146.00:06:22.44#ibcon#ireg 11 cls_cnt 2 2006.146.00:06:22.44#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.146.00:06:22.44#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.146.00:06:22.44#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.146.00:06:22.46#ibcon#[27=AT01-03\r\n] 2006.146.00:06:22.49#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.146.00:06:22.49#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.146.00:06:22.49#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.146.00:06:22.49#ibcon#ireg 7 cls_cnt 0 2006.146.00:06:22.49#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.146.00:06:22.61#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.146.00:06:22.61#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.146.00:06:22.66#ibcon#[27=USB\r\n] 2006.146.00:06:22.69#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.146.00:06:22.69#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.146.00:06:22.69#ibcon#about to clear, iclass 34 cls_cnt 0 2006.146.00:06:22.69#ibcon#cleared, iclass 34 cls_cnt 0 2006.146.00:06:22.69$vck44/vblo=2,634.99 2006.146.00:06:22.69#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.146.00:06:22.69#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.146.00:06:22.69#ibcon#ireg 17 cls_cnt 0 2006.146.00:06:22.69#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.146.00:06:22.69#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.146.00:06:22.69#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.146.00:06:22.71#ibcon#[28=FRQ=02,634.99\r\n] 2006.146.00:06:22.75#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.146.00:06:22.75#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.146.00:06:22.75#ibcon#about to clear, iclass 36 cls_cnt 0 2006.146.00:06:22.75#ibcon#cleared, iclass 36 cls_cnt 0 2006.146.00:06:22.75$vck44/vb=2,4 2006.146.00:06:22.75#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.146.00:06:22.75#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.146.00:06:22.75#ibcon#ireg 11 cls_cnt 2 2006.146.00:06:22.75#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.146.00:06:22.81#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.146.00:06:22.81#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.146.00:06:22.83#ibcon#[27=AT02-04\r\n] 2006.146.00:06:22.86#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.146.00:06:22.86#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.146.00:06:22.86#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.146.00:06:22.86#ibcon#ireg 7 cls_cnt 0 2006.146.00:06:22.86#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.146.00:06:22.98#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.146.00:06:22.98#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.146.00:06:23.00#ibcon#[27=USB\r\n] 2006.146.00:06:23.03#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.146.00:06:23.03#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.146.00:06:23.03#ibcon#about to clear, iclass 38 cls_cnt 0 2006.146.00:06:23.03#ibcon#cleared, iclass 38 cls_cnt 0 2006.146.00:06:23.03$vck44/vblo=3,649.99 2006.146.00:06:23.03#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.146.00:06:23.03#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.146.00:06:23.03#ibcon#ireg 17 cls_cnt 0 2006.146.00:06:23.03#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.146.00:06:23.03#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.146.00:06:23.03#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.146.00:06:23.05#ibcon#[28=FRQ=03,649.99\r\n] 2006.146.00:06:23.09#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.146.00:06:23.09#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.146.00:06:23.09#ibcon#about to clear, iclass 40 cls_cnt 0 2006.146.00:06:23.09#ibcon#cleared, iclass 40 cls_cnt 0 2006.146.00:06:23.09$vck44/vb=3,4 2006.146.00:06:23.09#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.146.00:06:23.09#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.146.00:06:23.09#ibcon#ireg 11 cls_cnt 2 2006.146.00:06:23.09#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.146.00:06:23.15#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.146.00:06:23.15#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.146.00:06:23.17#ibcon#[27=AT03-04\r\n] 2006.146.00:06:23.20#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.146.00:06:23.20#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.146.00:06:23.20#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.146.00:06:23.20#ibcon#ireg 7 cls_cnt 0 2006.146.00:06:23.20#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.146.00:06:23.32#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.146.00:06:23.32#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.146.00:06:23.34#ibcon#[27=USB\r\n] 2006.146.00:06:23.37#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.146.00:06:23.37#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.146.00:06:23.37#ibcon#about to clear, iclass 4 cls_cnt 0 2006.146.00:06:23.37#ibcon#cleared, iclass 4 cls_cnt 0 2006.146.00:06:23.37$vck44/vblo=4,679.99 2006.146.00:06:23.37#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.146.00:06:23.37#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.146.00:06:23.37#ibcon#ireg 17 cls_cnt 0 2006.146.00:06:23.37#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.146.00:06:23.37#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.146.00:06:23.37#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.146.00:06:23.39#ibcon#[28=FRQ=04,679.99\r\n] 2006.146.00:06:23.43#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.146.00:06:23.43#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.146.00:06:23.43#ibcon#about to clear, iclass 6 cls_cnt 0 2006.146.00:06:23.43#ibcon#cleared, iclass 6 cls_cnt 0 2006.146.00:06:23.43$vck44/vb=4,4 2006.146.00:06:23.43#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.146.00:06:23.43#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.146.00:06:23.43#ibcon#ireg 11 cls_cnt 2 2006.146.00:06:23.43#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.146.00:06:23.49#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.146.00:06:23.49#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.146.00:06:23.51#ibcon#[27=AT04-04\r\n] 2006.146.00:06:23.54#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.146.00:06:23.54#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.146.00:06:23.54#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.146.00:06:23.54#ibcon#ireg 7 cls_cnt 0 2006.146.00:06:23.54#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.146.00:06:23.66#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.146.00:06:23.66#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.146.00:06:23.68#ibcon#[27=USB\r\n] 2006.146.00:06:23.71#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.146.00:06:23.71#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.146.00:06:23.71#ibcon#about to clear, iclass 10 cls_cnt 0 2006.146.00:06:23.71#ibcon#cleared, iclass 10 cls_cnt 0 2006.146.00:06:23.71$vck44/vblo=5,709.99 2006.146.00:06:23.71#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.146.00:06:23.71#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.146.00:06:23.71#ibcon#ireg 17 cls_cnt 0 2006.146.00:06:23.71#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.146.00:06:23.71#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.146.00:06:23.71#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.146.00:06:23.73#ibcon#[28=FRQ=05,709.99\r\n] 2006.146.00:06:23.77#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.146.00:06:23.77#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.146.00:06:23.77#ibcon#about to clear, iclass 12 cls_cnt 0 2006.146.00:06:23.77#ibcon#cleared, iclass 12 cls_cnt 0 2006.146.00:06:23.77$vck44/vb=5,4 2006.146.00:06:23.77#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.146.00:06:23.77#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.146.00:06:23.77#ibcon#ireg 11 cls_cnt 2 2006.146.00:06:23.77#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.146.00:06:23.83#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.146.00:06:23.83#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.146.00:06:23.85#ibcon#[27=AT05-04\r\n] 2006.146.00:06:23.88#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.146.00:06:23.88#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.146.00:06:23.88#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.146.00:06:23.88#ibcon#ireg 7 cls_cnt 0 2006.146.00:06:23.88#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.146.00:06:24.00#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.146.00:06:24.00#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.146.00:06:24.02#ibcon#[27=USB\r\n] 2006.146.00:06:24.05#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.146.00:06:24.05#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.146.00:06:24.05#ibcon#about to clear, iclass 14 cls_cnt 0 2006.146.00:06:24.05#ibcon#cleared, iclass 14 cls_cnt 0 2006.146.00:06:24.05$vck44/vblo=6,719.99 2006.146.00:06:24.05#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.146.00:06:24.05#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.146.00:06:24.05#ibcon#ireg 17 cls_cnt 0 2006.146.00:06:24.05#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.146.00:06:24.05#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.146.00:06:24.05#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.146.00:06:24.07#ibcon#[28=FRQ=06,719.99\r\n] 2006.146.00:06:24.11#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.146.00:06:24.11#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.146.00:06:24.11#ibcon#about to clear, iclass 16 cls_cnt 0 2006.146.00:06:24.11#ibcon#cleared, iclass 16 cls_cnt 0 2006.146.00:06:24.11$vck44/vb=6,4 2006.146.00:06:24.11#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.146.00:06:24.11#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.146.00:06:24.11#ibcon#ireg 11 cls_cnt 2 2006.146.00:06:24.11#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.146.00:06:24.17#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.146.00:06:24.17#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.146.00:06:24.19#ibcon#[27=AT06-04\r\n] 2006.146.00:06:24.22#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.146.00:06:24.22#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.146.00:06:24.22#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.146.00:06:24.22#ibcon#ireg 7 cls_cnt 0 2006.146.00:06:24.22#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.146.00:06:24.34#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.146.00:06:24.34#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.146.00:06:24.36#ibcon#[27=USB\r\n] 2006.146.00:06:24.39#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.146.00:06:24.39#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.146.00:06:24.39#ibcon#about to clear, iclass 18 cls_cnt 0 2006.146.00:06:24.39#ibcon#cleared, iclass 18 cls_cnt 0 2006.146.00:06:24.39$vck44/vblo=7,734.99 2006.146.00:06:24.39#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.146.00:06:24.39#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.146.00:06:24.39#ibcon#ireg 17 cls_cnt 0 2006.146.00:06:24.39#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.146.00:06:24.39#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.146.00:06:24.39#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.146.00:06:24.41#ibcon#[28=FRQ=07,734.99\r\n] 2006.146.00:06:24.45#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.146.00:06:24.45#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.146.00:06:24.45#ibcon#about to clear, iclass 20 cls_cnt 0 2006.146.00:06:24.45#ibcon#cleared, iclass 20 cls_cnt 0 2006.146.00:06:24.45$vck44/vb=7,4 2006.146.00:06:24.45#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.146.00:06:24.45#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.146.00:06:24.45#ibcon#ireg 11 cls_cnt 2 2006.146.00:06:24.45#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.146.00:06:24.51#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.146.00:06:24.51#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.146.00:06:24.53#ibcon#[27=AT07-04\r\n] 2006.146.00:06:24.56#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.146.00:06:24.56#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.146.00:06:24.56#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.146.00:06:24.56#ibcon#ireg 7 cls_cnt 0 2006.146.00:06:24.56#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.146.00:06:24.68#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.146.00:06:24.68#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.146.00:06:24.70#ibcon#[27=USB\r\n] 2006.146.00:06:24.73#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.146.00:06:24.73#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.146.00:06:24.73#ibcon#about to clear, iclass 22 cls_cnt 0 2006.146.00:06:24.73#ibcon#cleared, iclass 22 cls_cnt 0 2006.146.00:06:24.73$vck44/vblo=8,744.99 2006.146.00:06:24.73#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.146.00:06:24.73#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.146.00:06:24.73#ibcon#ireg 17 cls_cnt 0 2006.146.00:06:24.73#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.146.00:06:24.73#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.146.00:06:24.73#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.146.00:06:24.75#ibcon#[28=FRQ=08,744.99\r\n] 2006.146.00:06:24.79#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.146.00:06:24.79#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.146.00:06:24.79#ibcon#about to clear, iclass 24 cls_cnt 0 2006.146.00:06:24.79#ibcon#cleared, iclass 24 cls_cnt 0 2006.146.00:06:24.79$vck44/vb=8,4 2006.146.00:06:24.79#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.146.00:06:24.79#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.146.00:06:24.79#ibcon#ireg 11 cls_cnt 2 2006.146.00:06:24.79#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.146.00:06:24.85#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.146.00:06:24.85#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.146.00:06:24.87#ibcon#[27=AT08-04\r\n] 2006.146.00:06:24.90#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.146.00:06:24.90#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.146.00:06:24.90#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.146.00:06:24.90#ibcon#ireg 7 cls_cnt 0 2006.146.00:06:24.90#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.146.00:06:25.02#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.146.00:06:25.02#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.146.00:06:25.04#ibcon#[27=USB\r\n] 2006.146.00:06:25.07#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.146.00:06:25.07#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.146.00:06:25.07#ibcon#about to clear, iclass 26 cls_cnt 0 2006.146.00:06:25.07#ibcon#cleared, iclass 26 cls_cnt 0 2006.146.00:06:25.07$vck44/vabw=wide 2006.146.00:06:25.07#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.146.00:06:25.07#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.146.00:06:25.07#ibcon#ireg 8 cls_cnt 0 2006.146.00:06:25.07#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.146.00:06:25.07#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.146.00:06:25.07#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.146.00:06:25.09#ibcon#[25=BW32\r\n] 2006.146.00:06:25.12#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.146.00:06:25.12#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.146.00:06:25.12#ibcon#about to clear, iclass 28 cls_cnt 0 2006.146.00:06:25.12#ibcon#cleared, iclass 28 cls_cnt 0 2006.146.00:06:25.12$vck44/vbbw=wide 2006.146.00:06:25.12#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.146.00:06:25.12#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.146.00:06:25.12#ibcon#ireg 8 cls_cnt 0 2006.146.00:06:25.12#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.146.00:06:25.19#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.146.00:06:25.19#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.146.00:06:25.21#ibcon#[27=BW32\r\n] 2006.146.00:06:25.24#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.146.00:06:25.24#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.146.00:06:25.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.146.00:06:25.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.146.00:06:25.24$setupk4/ifdk4 2006.146.00:06:25.24$ifdk4/lo= 2006.146.00:06:25.24$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.146.00:06:25.24$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.146.00:06:25.24$ifdk4/patch= 2006.146.00:06:25.24$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.146.00:06:25.24$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.146.00:06:25.24$setupk4/!*+20s 2006.146.00:06:27.40#abcon#<5=/08 1.9 6.4 20.30 751020.6\r\n> 2006.146.00:06:27.42#abcon#{5=INTERFACE CLEAR} 2006.146.00:06:27.48#abcon#[5=S1D000X0/0*\r\n] 2006.146.00:06:33.14#trakl#Source acquired 2006.146.00:06:35.14#flagr#flagr/antenna,acquired 2006.146.00:06:37.57#abcon#<5=/08 1.9 6.4 20.30 751020.6\r\n> 2006.146.00:06:37.59#abcon#{5=INTERFACE CLEAR} 2006.146.00:06:37.65#abcon#[5=S1D000X0/0*\r\n] 2006.146.00:06:39.68$setupk4/"tpicd 2006.146.00:06:39.68$setupk4/echo=off 2006.146.00:06:39.68$setupk4/xlog=off 2006.146.00:06:39.68:!2006.146.00:08:45 2006.146.00:08:45.00:preob 2006.146.00:08:45.14/onsource/TRACKING 2006.146.00:08:45.14:!2006.146.00:08:55 2006.146.00:08:55.00:"tape 2006.146.00:08:55.00:"st=record 2006.146.00:08:55.00:data_valid=on 2006.146.00:08:55.00:midob 2006.146.00:08:56.13/onsource/TRACKING 2006.146.00:08:56.13/wx/20.30,1020.6,72 2006.146.00:08:56.24/cable/+6.5470E-03 2006.146.00:08:57.33/va/01,08,usb,yes,28,30 2006.146.00:08:57.33/va/02,07,usb,yes,30,31 2006.146.00:08:57.33/va/03,08,usb,yes,28,29 2006.146.00:08:57.33/va/04,07,usb,yes,31,33 2006.146.00:08:57.33/va/05,04,usb,yes,27,28 2006.146.00:08:57.33/va/06,04,usb,yes,31,30 2006.146.00:08:57.33/va/07,04,usb,yes,31,32 2006.146.00:08:57.33/va/08,04,usb,yes,26,32 2006.146.00:08:57.56/valo/01,524.99,yes,locked 2006.146.00:08:57.56/valo/02,534.99,yes,locked 2006.146.00:08:57.56/valo/03,564.99,yes,locked 2006.146.00:08:57.56/valo/04,624.99,yes,locked 2006.146.00:08:57.56/valo/05,734.99,yes,locked 2006.146.00:08:57.56/valo/06,814.99,yes,locked 2006.146.00:08:57.56/valo/07,864.99,yes,locked 2006.146.00:08:57.56/valo/08,884.99,yes,locked 2006.146.00:08:58.65/vb/01,03,usb,yes,35,33 2006.146.00:08:58.65/vb/02,04,usb,yes,31,31 2006.146.00:08:58.65/vb/03,04,usb,yes,28,31 2006.146.00:08:58.65/vb/04,04,usb,yes,32,31 2006.146.00:08:58.65/vb/05,04,usb,yes,25,27 2006.146.00:08:58.65/vb/06,04,usb,yes,29,25 2006.146.00:08:58.65/vb/07,04,usb,yes,29,29 2006.146.00:08:58.65/vb/08,04,usb,yes,27,30 2006.146.00:08:58.88/vblo/01,629.99,yes,locked 2006.146.00:08:58.88/vblo/02,634.99,yes,locked 2006.146.00:08:58.88/vblo/03,649.99,yes,locked 2006.146.00:08:58.88/vblo/04,679.99,yes,locked 2006.146.00:08:58.88/vblo/05,709.99,yes,locked 2006.146.00:08:58.88/vblo/06,719.99,yes,locked 2006.146.00:08:58.88/vblo/07,734.99,yes,locked 2006.146.00:08:58.88/vblo/08,744.99,yes,locked 2006.146.00:08:59.03/vabw/8 2006.146.00:08:59.18/vbbw/8 2006.146.00:08:59.27/xfe/off,on,16.0 2006.146.00:08:59.64/ifatt/23,28,28,28 2006.146.00:09:00.07/fmout-gps/S +3.6E-08 2006.146.00:09:00.11:!2006.146.00:14:05 2006.146.00:14:05.00:data_valid=off 2006.146.00:14:05.00:"et 2006.146.00:14:05.00:!+3s 2006.146.00:14:08.01:"tape 2006.146.00:14:08.01:postob 2006.146.00:14:08.16/cable/+6.5451E-03 2006.146.00:14:08.16/wx/20.28,1020.6,71 2006.146.00:14:09.07/fmout-gps/S +3.8E-08 2006.146.00:14:09.07:scan_name=146-0018,jd0605,180 2006.146.00:14:09.07:source=0014+813,001708.47,813508.1,2000.0,neutral 2006.146.00:14:10.13:checkk5 2006.146.00:14:10.13#flagr#flagr/antenna,new-source 2006.146.00:14:10.58/chk_autoobs//k5ts1/ autoobs is running! 2006.146.00:14:11.02/chk_autoobs//k5ts2/ autoobs is running! 2006.146.00:14:11.46/chk_autoobs//k5ts3/ autoobs is running! 2006.146.00:14:11.91/chk_autoobs//k5ts4/ autoobs is running! 2006.146.00:14:12.34/chk_obsdata//k5ts1/T1460008??a.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.146.00:14:12.75/chk_obsdata//k5ts2/T1460008??b.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.146.00:14:13.12/chk_obsdata//k5ts3/T1460008??c.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.146.00:14:13.50/chk_obsdata//k5ts4/T1460008??d.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.146.00:14:14.32/k5log//k5ts1_log_newline 2006.146.00:14:15.10/k5log//k5ts2_log_newline 2006.146.00:14:15.86/k5log//k5ts3_log_newline 2006.146.00:14:16.61/k5log//k5ts4_log_newline 2006.146.00:14:16.63/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.146.00:14:16.63:setupk4=1 2006.146.00:14:16.63$setupk4/echo=on 2006.146.00:14:16.63$setupk4/pcalon 2006.146.00:14:16.63$pcalon/"no phase cal control is implemented here 2006.146.00:14:16.63$setupk4/"tpicd=stop 2006.146.00:14:16.63$setupk4/"rec=synch_on 2006.146.00:14:16.63$setupk4/"rec_mode=128 2006.146.00:14:16.63$setupk4/!* 2006.146.00:14:16.63$setupk4/recpk4 2006.146.00:14:16.63$recpk4/recpatch= 2006.146.00:14:16.63$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.146.00:14:16.63$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.146.00:14:16.63$setupk4/vck44 2006.146.00:14:16.63$vck44/valo=1,524.99 2006.146.00:14:16.63#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.146.00:14:16.63#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.146.00:14:16.63#ibcon#ireg 17 cls_cnt 0 2006.146.00:14:16.63#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.146.00:14:16.63#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.146.00:14:16.63#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.146.00:14:16.67#ibcon#[26=FRQ=01,524.99\r\n] 2006.146.00:14:16.72#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.146.00:14:16.72#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.146.00:14:16.72#ibcon#about to clear, iclass 5 cls_cnt 0 2006.146.00:14:16.72#ibcon#cleared, iclass 5 cls_cnt 0 2006.146.00:14:16.72$vck44/va=1,8 2006.146.00:14:16.72#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.146.00:14:16.72#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.146.00:14:16.72#ibcon#ireg 11 cls_cnt 2 2006.146.00:14:16.72#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.146.00:14:16.72#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.146.00:14:16.72#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.146.00:14:16.74#ibcon#[25=AT01-08\r\n] 2006.146.00:14:16.77#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.146.00:14:16.77#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.146.00:14:16.77#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.146.00:14:16.77#ibcon#ireg 7 cls_cnt 0 2006.146.00:14:16.77#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.146.00:14:16.91#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.146.00:14:16.91#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.146.00:14:16.92#ibcon#[25=USB\r\n] 2006.146.00:14:16.95#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.146.00:14:16.95#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.146.00:14:16.95#ibcon#about to clear, iclass 7 cls_cnt 0 2006.146.00:14:16.95#ibcon#cleared, iclass 7 cls_cnt 0 2006.146.00:14:16.95$vck44/valo=2,534.99 2006.146.00:14:16.95#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.146.00:14:16.95#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.146.00:14:16.95#ibcon#ireg 17 cls_cnt 0 2006.146.00:14:16.95#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.146.00:14:16.95#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.146.00:14:16.95#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.146.00:14:16.97#ibcon#[26=FRQ=02,534.99\r\n] 2006.146.00:14:17.01#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.146.00:14:17.01#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.146.00:14:17.01#ibcon#about to clear, iclass 11 cls_cnt 0 2006.146.00:14:17.01#ibcon#cleared, iclass 11 cls_cnt 0 2006.146.00:14:17.01$vck44/va=2,7 2006.146.00:14:17.01#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.146.00:14:17.01#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.146.00:14:17.01#ibcon#ireg 11 cls_cnt 2 2006.146.00:14:17.01#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.146.00:14:17.07#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.146.00:14:17.07#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.146.00:14:17.09#ibcon#[25=AT02-07\r\n] 2006.146.00:14:17.12#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.146.00:14:17.12#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.146.00:14:17.12#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.146.00:14:17.12#ibcon#ireg 7 cls_cnt 0 2006.146.00:14:17.12#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.146.00:14:17.24#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.146.00:14:17.24#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.146.00:14:17.26#ibcon#[25=USB\r\n] 2006.146.00:14:17.29#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.146.00:14:17.29#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.146.00:14:17.29#ibcon#about to clear, iclass 13 cls_cnt 0 2006.146.00:14:17.29#ibcon#cleared, iclass 13 cls_cnt 0 2006.146.00:14:17.29$vck44/valo=3,564.99 2006.146.00:14:17.29#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.146.00:14:17.29#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.146.00:14:17.29#ibcon#ireg 17 cls_cnt 0 2006.146.00:14:17.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.146.00:14:17.29#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.146.00:14:17.29#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.146.00:14:17.31#ibcon#[26=FRQ=03,564.99\r\n] 2006.146.00:14:17.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.146.00:14:17.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.146.00:14:17.35#ibcon#about to clear, iclass 15 cls_cnt 0 2006.146.00:14:17.35#ibcon#cleared, iclass 15 cls_cnt 0 2006.146.00:14:17.35$vck44/va=3,8 2006.146.00:14:17.35#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.146.00:14:17.35#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.146.00:14:17.35#ibcon#ireg 11 cls_cnt 2 2006.146.00:14:17.35#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.146.00:14:17.41#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.146.00:14:17.41#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.146.00:14:17.43#ibcon#[25=AT03-08\r\n] 2006.146.00:14:17.46#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.146.00:14:17.46#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.146.00:14:17.46#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.146.00:14:17.46#ibcon#ireg 7 cls_cnt 0 2006.146.00:14:17.46#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.146.00:14:17.58#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.146.00:14:17.58#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.146.00:14:17.60#ibcon#[25=USB\r\n] 2006.146.00:14:17.63#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.146.00:14:17.63#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.146.00:14:17.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.146.00:14:17.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.146.00:14:17.63$vck44/valo=4,624.99 2006.146.00:14:17.63#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.146.00:14:17.63#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.146.00:14:17.63#ibcon#ireg 17 cls_cnt 0 2006.146.00:14:17.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.146.00:14:17.63#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.146.00:14:17.63#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.146.00:14:17.65#ibcon#[26=FRQ=04,624.99\r\n] 2006.146.00:14:17.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.146.00:14:17.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.146.00:14:17.69#ibcon#about to clear, iclass 19 cls_cnt 0 2006.146.00:14:17.69#ibcon#cleared, iclass 19 cls_cnt 0 2006.146.00:14:17.69$vck44/va=4,7 2006.146.00:14:17.69#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.146.00:14:17.69#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.146.00:14:17.69#ibcon#ireg 11 cls_cnt 2 2006.146.00:14:17.69#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.146.00:14:17.75#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.146.00:14:17.75#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.146.00:14:17.77#ibcon#[25=AT04-07\r\n] 2006.146.00:14:17.80#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.146.00:14:17.80#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.146.00:14:17.80#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.146.00:14:17.80#ibcon#ireg 7 cls_cnt 0 2006.146.00:14:17.80#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.146.00:14:17.92#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.146.00:14:17.92#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.146.00:14:17.94#ibcon#[25=USB\r\n] 2006.146.00:14:17.97#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.146.00:14:17.97#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.146.00:14:17.97#ibcon#about to clear, iclass 21 cls_cnt 0 2006.146.00:14:17.97#ibcon#cleared, iclass 21 cls_cnt 0 2006.146.00:14:17.97$vck44/valo=5,734.99 2006.146.00:14:17.97#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.146.00:14:17.97#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.146.00:14:17.97#ibcon#ireg 17 cls_cnt 0 2006.146.00:14:17.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.146.00:14:17.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.146.00:14:17.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.146.00:14:17.99#ibcon#[26=FRQ=05,734.99\r\n] 2006.146.00:14:18.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.146.00:14:18.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.146.00:14:18.03#ibcon#about to clear, iclass 23 cls_cnt 0 2006.146.00:14:18.03#ibcon#cleared, iclass 23 cls_cnt 0 2006.146.00:14:18.03$vck44/va=5,4 2006.146.00:14:18.03#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.146.00:14:18.03#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.146.00:14:18.03#ibcon#ireg 11 cls_cnt 2 2006.146.00:14:18.03#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.146.00:14:18.09#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.146.00:14:18.09#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.146.00:14:18.11#ibcon#[25=AT05-04\r\n] 2006.146.00:14:18.14#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.146.00:14:18.14#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.146.00:14:18.14#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.146.00:14:18.14#ibcon#ireg 7 cls_cnt 0 2006.146.00:14:18.14#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.146.00:14:18.26#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.146.00:14:18.26#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.146.00:14:18.28#ibcon#[25=USB\r\n] 2006.146.00:14:18.31#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.146.00:14:18.31#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.146.00:14:18.31#ibcon#about to clear, iclass 25 cls_cnt 0 2006.146.00:14:18.31#ibcon#cleared, iclass 25 cls_cnt 0 2006.146.00:14:18.31$vck44/valo=6,814.99 2006.146.00:14:18.31#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.146.00:14:18.31#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.146.00:14:18.31#ibcon#ireg 17 cls_cnt 0 2006.146.00:14:18.31#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.146.00:14:18.31#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.146.00:14:18.31#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.146.00:14:18.34#ibcon#[26=FRQ=06,814.99\r\n] 2006.146.00:14:18.38#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.146.00:14:18.38#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.146.00:14:18.38#ibcon#about to clear, iclass 27 cls_cnt 0 2006.146.00:14:18.38#ibcon#cleared, iclass 27 cls_cnt 0 2006.146.00:14:18.38$vck44/va=6,4 2006.146.00:14:18.38#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.146.00:14:18.38#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.146.00:14:18.38#ibcon#ireg 11 cls_cnt 2 2006.146.00:14:18.38#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.146.00:14:18.43#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.146.00:14:18.43#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.146.00:14:18.45#ibcon#[25=AT06-04\r\n] 2006.146.00:14:18.48#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.146.00:14:18.48#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.146.00:14:18.48#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.146.00:14:18.48#ibcon#ireg 7 cls_cnt 0 2006.146.00:14:18.48#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.146.00:14:18.60#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.146.00:14:18.60#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.146.00:14:18.62#ibcon#[25=USB\r\n] 2006.146.00:14:18.65#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.146.00:14:18.65#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.146.00:14:18.65#ibcon#about to clear, iclass 29 cls_cnt 0 2006.146.00:14:18.65#ibcon#cleared, iclass 29 cls_cnt 0 2006.146.00:14:18.65$vck44/valo=7,864.99 2006.146.00:14:18.65#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.146.00:14:18.65#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.146.00:14:18.65#ibcon#ireg 17 cls_cnt 0 2006.146.00:14:18.65#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.146.00:14:18.65#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.146.00:14:18.65#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.146.00:14:18.67#ibcon#[26=FRQ=07,864.99\r\n] 2006.146.00:14:18.71#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.146.00:14:18.71#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.146.00:14:18.71#ibcon#about to clear, iclass 31 cls_cnt 0 2006.146.00:14:18.71#ibcon#cleared, iclass 31 cls_cnt 0 2006.146.00:14:18.71$vck44/va=7,4 2006.146.00:14:18.71#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.146.00:14:18.71#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.146.00:14:18.71#ibcon#ireg 11 cls_cnt 2 2006.146.00:14:18.71#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.146.00:14:18.77#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.146.00:14:18.77#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.146.00:14:18.79#ibcon#[25=AT07-04\r\n] 2006.146.00:14:18.82#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.146.00:14:18.82#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.146.00:14:18.82#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.146.00:14:18.82#ibcon#ireg 7 cls_cnt 0 2006.146.00:14:18.82#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.146.00:14:18.94#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.146.00:14:18.94#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.146.00:14:18.96#ibcon#[25=USB\r\n] 2006.146.00:14:18.99#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.146.00:14:18.99#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.146.00:14:18.99#ibcon#about to clear, iclass 33 cls_cnt 0 2006.146.00:14:18.99#ibcon#cleared, iclass 33 cls_cnt 0 2006.146.00:14:18.99$vck44/valo=8,884.99 2006.146.00:14:18.99#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.146.00:14:18.99#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.146.00:14:18.99#ibcon#ireg 17 cls_cnt 0 2006.146.00:14:18.99#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.146.00:14:18.99#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.146.00:14:18.99#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.146.00:14:19.01#ibcon#[26=FRQ=08,884.99\r\n] 2006.146.00:14:19.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.146.00:14:19.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.146.00:14:19.05#ibcon#about to clear, iclass 35 cls_cnt 0 2006.146.00:14:19.05#ibcon#cleared, iclass 35 cls_cnt 0 2006.146.00:14:19.05$vck44/va=8,4 2006.146.00:14:19.05#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.146.00:14:19.05#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.146.00:14:19.05#ibcon#ireg 11 cls_cnt 2 2006.146.00:14:19.05#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.146.00:14:19.11#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.146.00:14:19.11#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.146.00:14:19.13#ibcon#[25=AT08-04\r\n] 2006.146.00:14:19.16#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.146.00:14:19.16#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.146.00:14:19.16#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.146.00:14:19.16#ibcon#ireg 7 cls_cnt 0 2006.146.00:14:19.16#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.146.00:14:19.28#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.146.00:14:19.28#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.146.00:14:19.30#ibcon#[25=USB\r\n] 2006.146.00:14:19.33#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.146.00:14:19.33#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.146.00:14:19.33#ibcon#about to clear, iclass 37 cls_cnt 0 2006.146.00:14:19.33#ibcon#cleared, iclass 37 cls_cnt 0 2006.146.00:14:19.33$vck44/vblo=1,629.99 2006.146.00:14:19.33#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.146.00:14:19.33#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.146.00:14:19.33#ibcon#ireg 17 cls_cnt 0 2006.146.00:14:19.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.146.00:14:19.33#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.146.00:14:19.33#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.146.00:14:19.35#ibcon#[28=FRQ=01,629.99\r\n] 2006.146.00:14:19.39#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.146.00:14:19.39#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.146.00:14:19.39#ibcon#about to clear, iclass 39 cls_cnt 0 2006.146.00:14:19.39#ibcon#cleared, iclass 39 cls_cnt 0 2006.146.00:14:19.39$vck44/vb=1,3 2006.146.00:14:19.39#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.146.00:14:19.39#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.146.00:14:19.39#ibcon#ireg 11 cls_cnt 2 2006.146.00:14:19.39#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.146.00:14:19.39#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.146.00:14:19.39#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.146.00:14:19.41#ibcon#[27=AT01-03\r\n] 2006.146.00:14:19.44#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.146.00:14:19.44#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.146.00:14:19.44#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.146.00:14:19.44#ibcon#ireg 7 cls_cnt 0 2006.146.00:14:19.44#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.146.00:14:19.56#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.146.00:14:19.56#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.146.00:14:19.58#ibcon#[27=USB\r\n] 2006.146.00:14:19.61#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.146.00:14:19.61#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.146.00:14:19.61#ibcon#about to clear, iclass 3 cls_cnt 0 2006.146.00:14:19.61#ibcon#cleared, iclass 3 cls_cnt 0 2006.146.00:14:19.61$vck44/vblo=2,634.99 2006.146.00:14:19.61#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.146.00:14:19.61#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.146.00:14:19.61#ibcon#ireg 17 cls_cnt 0 2006.146.00:14:19.61#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.146.00:14:19.61#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.146.00:14:19.61#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.146.00:14:19.64#ibcon#[28=FRQ=02,634.99\r\n] 2006.146.00:14:19.68#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.146.00:14:19.68#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.146.00:14:19.68#ibcon#about to clear, iclass 5 cls_cnt 0 2006.146.00:14:19.68#ibcon#cleared, iclass 5 cls_cnt 0 2006.146.00:14:19.68$vck44/vb=2,4 2006.146.00:14:19.68#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.146.00:14:19.68#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.146.00:14:19.68#ibcon#ireg 11 cls_cnt 2 2006.146.00:14:19.68#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.146.00:14:19.73#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.146.00:14:19.73#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.146.00:14:19.75#ibcon#[27=AT02-04\r\n] 2006.146.00:14:19.78#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.146.00:14:19.78#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.146.00:14:19.78#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.146.00:14:19.78#ibcon#ireg 7 cls_cnt 0 2006.146.00:14:19.78#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.146.00:14:19.90#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.146.00:14:19.90#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.146.00:14:19.92#ibcon#[27=USB\r\n] 2006.146.00:14:19.95#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.146.00:14:19.95#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.146.00:14:19.95#ibcon#about to clear, iclass 7 cls_cnt 0 2006.146.00:14:19.95#ibcon#cleared, iclass 7 cls_cnt 0 2006.146.00:14:19.95$vck44/vblo=3,649.99 2006.146.00:14:19.95#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.146.00:14:19.95#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.146.00:14:19.95#ibcon#ireg 17 cls_cnt 0 2006.146.00:14:19.95#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.146.00:14:19.95#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.146.00:14:19.95#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.146.00:14:19.97#ibcon#[28=FRQ=03,649.99\r\n] 2006.146.00:14:20.01#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.146.00:14:20.01#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.146.00:14:20.01#ibcon#about to clear, iclass 11 cls_cnt 0 2006.146.00:14:20.01#ibcon#cleared, iclass 11 cls_cnt 0 2006.146.00:14:20.01$vck44/vb=3,4 2006.146.00:14:20.01#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.146.00:14:20.01#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.146.00:14:20.01#ibcon#ireg 11 cls_cnt 2 2006.146.00:14:20.01#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.146.00:14:20.07#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.146.00:14:20.07#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.146.00:14:20.09#ibcon#[27=AT03-04\r\n] 2006.146.00:14:20.12#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.146.00:14:20.12#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.146.00:14:20.12#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.146.00:14:20.12#ibcon#ireg 7 cls_cnt 0 2006.146.00:14:20.12#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.146.00:14:20.24#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.146.00:14:20.24#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.146.00:14:20.26#ibcon#[27=USB\r\n] 2006.146.00:14:20.29#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.146.00:14:20.29#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.146.00:14:20.29#ibcon#about to clear, iclass 13 cls_cnt 0 2006.146.00:14:20.29#ibcon#cleared, iclass 13 cls_cnt 0 2006.146.00:14:20.29$vck44/vblo=4,679.99 2006.146.00:14:20.29#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.146.00:14:20.29#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.146.00:14:20.29#ibcon#ireg 17 cls_cnt 0 2006.146.00:14:20.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.146.00:14:20.29#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.146.00:14:20.29#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.146.00:14:20.31#ibcon#[28=FRQ=04,679.99\r\n] 2006.146.00:14:20.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.146.00:14:20.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.146.00:14:20.35#ibcon#about to clear, iclass 15 cls_cnt 0 2006.146.00:14:20.35#ibcon#cleared, iclass 15 cls_cnt 0 2006.146.00:14:20.35$vck44/vb=4,4 2006.146.00:14:20.35#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.146.00:14:20.35#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.146.00:14:20.35#ibcon#ireg 11 cls_cnt 2 2006.146.00:14:20.35#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.146.00:14:20.41#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.146.00:14:20.41#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.146.00:14:20.43#ibcon#[27=AT04-04\r\n] 2006.146.00:14:20.46#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.146.00:14:20.46#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.146.00:14:20.46#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.146.00:14:20.46#ibcon#ireg 7 cls_cnt 0 2006.146.00:14:20.46#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.146.00:14:20.58#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.146.00:14:20.58#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.146.00:14:20.60#ibcon#[27=USB\r\n] 2006.146.00:14:20.63#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.146.00:14:20.63#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.146.00:14:20.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.146.00:14:20.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.146.00:14:20.63$vck44/vblo=5,709.99 2006.146.00:14:20.63#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.146.00:14:20.63#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.146.00:14:20.63#ibcon#ireg 17 cls_cnt 0 2006.146.00:14:20.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.146.00:14:20.63#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.146.00:14:20.63#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.146.00:14:20.65#ibcon#[28=FRQ=05,709.99\r\n] 2006.146.00:14:20.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.146.00:14:20.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.146.00:14:20.69#ibcon#about to clear, iclass 19 cls_cnt 0 2006.146.00:14:20.69#ibcon#cleared, iclass 19 cls_cnt 0 2006.146.00:14:20.69$vck44/vb=5,4 2006.146.00:14:20.69#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.146.00:14:20.69#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.146.00:14:20.69#ibcon#ireg 11 cls_cnt 2 2006.146.00:14:20.69#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.146.00:14:20.75#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.146.00:14:20.75#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.146.00:14:20.77#ibcon#[27=AT05-04\r\n] 2006.146.00:14:20.80#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.146.00:14:20.80#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.146.00:14:20.80#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.146.00:14:20.80#ibcon#ireg 7 cls_cnt 0 2006.146.00:14:20.80#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.146.00:14:20.92#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.146.00:14:20.92#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.146.00:14:20.94#ibcon#[27=USB\r\n] 2006.146.00:14:20.97#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.146.00:14:20.97#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.146.00:14:20.97#ibcon#about to clear, iclass 21 cls_cnt 0 2006.146.00:14:20.97#ibcon#cleared, iclass 21 cls_cnt 0 2006.146.00:14:20.97$vck44/vblo=6,719.99 2006.146.00:14:20.97#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.146.00:14:20.97#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.146.00:14:20.97#ibcon#ireg 17 cls_cnt 0 2006.146.00:14:20.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.146.00:14:20.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.146.00:14:20.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.146.00:14:20.99#ibcon#[28=FRQ=06,719.99\r\n] 2006.146.00:14:21.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.146.00:14:21.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.146.00:14:21.03#ibcon#about to clear, iclass 23 cls_cnt 0 2006.146.00:14:21.03#ibcon#cleared, iclass 23 cls_cnt 0 2006.146.00:14:21.03$vck44/vb=6,4 2006.146.00:14:21.03#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.146.00:14:21.03#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.146.00:14:21.03#ibcon#ireg 11 cls_cnt 2 2006.146.00:14:21.03#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.146.00:14:21.09#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.146.00:14:21.09#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.146.00:14:21.11#ibcon#[27=AT06-04\r\n] 2006.146.00:14:21.14#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.146.00:14:21.14#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.146.00:14:21.14#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.146.00:14:21.14#ibcon#ireg 7 cls_cnt 0 2006.146.00:14:21.14#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.146.00:14:21.26#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.146.00:14:21.26#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.146.00:14:21.28#ibcon#[27=USB\r\n] 2006.146.00:14:21.31#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.146.00:14:21.31#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.146.00:14:21.31#ibcon#about to clear, iclass 25 cls_cnt 0 2006.146.00:14:21.31#ibcon#cleared, iclass 25 cls_cnt 0 2006.146.00:14:21.31$vck44/vblo=7,734.99 2006.146.00:14:21.31#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.146.00:14:21.31#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.146.00:14:21.31#ibcon#ireg 17 cls_cnt 0 2006.146.00:14:21.31#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.146.00:14:21.31#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.146.00:14:21.31#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.146.00:14:21.33#ibcon#[28=FRQ=07,734.99\r\n] 2006.146.00:14:21.37#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.146.00:14:21.37#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.146.00:14:21.37#ibcon#about to clear, iclass 27 cls_cnt 0 2006.146.00:14:21.37#ibcon#cleared, iclass 27 cls_cnt 0 2006.146.00:14:21.37$vck44/vb=7,4 2006.146.00:14:21.37#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.146.00:14:21.37#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.146.00:14:21.37#ibcon#ireg 11 cls_cnt 2 2006.146.00:14:21.37#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.146.00:14:21.43#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.146.00:14:21.43#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.146.00:14:21.45#ibcon#[27=AT07-04\r\n] 2006.146.00:14:21.48#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.146.00:14:21.48#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.146.00:14:21.48#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.146.00:14:21.48#ibcon#ireg 7 cls_cnt 0 2006.146.00:14:21.48#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.146.00:14:21.60#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.146.00:14:21.60#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.146.00:14:21.62#ibcon#[27=USB\r\n] 2006.146.00:14:21.65#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.146.00:14:21.65#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.146.00:14:21.65#ibcon#about to clear, iclass 29 cls_cnt 0 2006.146.00:14:21.65#ibcon#cleared, iclass 29 cls_cnt 0 2006.146.00:14:21.65$vck44/vblo=8,744.99 2006.146.00:14:21.65#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.146.00:14:21.65#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.146.00:14:21.65#ibcon#ireg 17 cls_cnt 0 2006.146.00:14:21.65#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.146.00:14:21.65#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.146.00:14:21.65#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.146.00:14:21.67#ibcon#[28=FRQ=08,744.99\r\n] 2006.146.00:14:21.71#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.146.00:14:21.71#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.146.00:14:21.71#ibcon#about to clear, iclass 31 cls_cnt 0 2006.146.00:14:21.71#ibcon#cleared, iclass 31 cls_cnt 0 2006.146.00:14:21.71$vck44/vb=8,4 2006.146.00:14:21.71#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.146.00:14:21.71#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.146.00:14:21.71#ibcon#ireg 11 cls_cnt 2 2006.146.00:14:21.71#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.146.00:14:21.77#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.146.00:14:21.77#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.146.00:14:21.79#ibcon#[27=AT08-04\r\n] 2006.146.00:14:21.82#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.146.00:14:21.82#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.146.00:14:21.82#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.146.00:14:21.82#ibcon#ireg 7 cls_cnt 0 2006.146.00:14:21.82#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.146.00:14:21.94#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.146.00:14:21.94#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.146.00:14:21.96#ibcon#[27=USB\r\n] 2006.146.00:14:21.99#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.146.00:14:21.99#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.146.00:14:21.99#ibcon#about to clear, iclass 33 cls_cnt 0 2006.146.00:14:21.99#ibcon#cleared, iclass 33 cls_cnt 0 2006.146.00:14:21.99$vck44/vabw=wide 2006.146.00:14:21.99#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.146.00:14:21.99#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.146.00:14:21.99#ibcon#ireg 8 cls_cnt 0 2006.146.00:14:21.99#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.146.00:14:21.99#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.146.00:14:21.99#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.146.00:14:22.01#ibcon#[25=BW32\r\n] 2006.146.00:14:22.04#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.146.00:14:22.04#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.146.00:14:22.04#ibcon#about to clear, iclass 35 cls_cnt 0 2006.146.00:14:22.04#ibcon#cleared, iclass 35 cls_cnt 0 2006.146.00:14:22.04$vck44/vbbw=wide 2006.146.00:14:22.04#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.146.00:14:22.04#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.146.00:14:22.04#ibcon#ireg 8 cls_cnt 0 2006.146.00:14:22.04#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:14:22.11#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:14:22.11#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:14:22.13#ibcon#[27=BW32\r\n] 2006.146.00:14:22.16#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:14:22.16#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:14:22.16#ibcon#about to clear, iclass 37 cls_cnt 0 2006.146.00:14:22.16#ibcon#cleared, iclass 37 cls_cnt 0 2006.146.00:14:22.16$setupk4/ifdk4 2006.146.00:14:22.16$ifdk4/lo= 2006.146.00:14:22.16$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.146.00:14:22.16$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.146.00:14:22.16$ifdk4/patch= 2006.146.00:14:22.16$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.146.00:14:22.16$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.146.00:14:22.16$setupk4/!*+20s 2006.146.00:14:25.54#abcon#<5=/08 1.8 6.4 20.28 711020.6\r\n> 2006.146.00:14:25.56#abcon#{5=INTERFACE CLEAR} 2006.146.00:14:25.62#abcon#[5=S1D000X0/0*\r\n] 2006.146.00:14:35.71#abcon#<5=/08 1.9 6.4 20.28 711020.6\r\n> 2006.146.00:14:35.73#abcon#{5=INTERFACE CLEAR} 2006.146.00:14:35.81#abcon#[5=S1D000X0/0*\r\n] 2006.146.00:14:36.14#trakl#Source acquired 2006.146.00:14:36.64$setupk4/"tpicd 2006.146.00:14:36.64$setupk4/echo=off 2006.146.00:14:36.64$setupk4/xlog=off 2006.146.00:14:36.64:!2006.146.00:18:21 2006.146.00:14:38.14#flagr#flagr/antenna,acquired 2006.146.00:18:21.00:preob 2006.146.00:18:21.13/onsource/TRACKING 2006.146.00:18:21.13:!2006.146.00:18:31 2006.146.00:18:31.00:"tape 2006.146.00:18:31.00:"st=record 2006.146.00:18:31.00:data_valid=on 2006.146.00:18:31.00:midob 2006.146.00:18:32.13/onsource/TRACKING 2006.146.00:18:32.13/wx/20.32,1020.6,71 2006.146.00:18:32.25/cable/+6.5448E-03 2006.146.00:18:33.34/va/01,08,usb,yes,28,30 2006.146.00:18:33.34/va/02,07,usb,yes,30,31 2006.146.00:18:33.34/va/03,08,usb,yes,28,29 2006.146.00:18:33.34/va/04,07,usb,yes,31,33 2006.146.00:18:33.34/va/05,04,usb,yes,27,28 2006.146.00:18:33.34/va/06,04,usb,yes,31,30 2006.146.00:18:33.34/va/07,04,usb,yes,31,32 2006.146.00:18:33.34/va/08,04,usb,yes,26,32 2006.146.00:18:33.57/valo/01,524.99,yes,locked 2006.146.00:18:33.57/valo/02,534.99,yes,locked 2006.146.00:18:33.57/valo/03,564.99,yes,locked 2006.146.00:18:33.57/valo/04,624.99,yes,locked 2006.146.00:18:33.57/valo/05,734.99,yes,locked 2006.146.00:18:33.57/valo/06,814.99,yes,locked 2006.146.00:18:33.57/valo/07,864.99,yes,locked 2006.146.00:18:33.57/valo/08,884.99,yes,locked 2006.146.00:18:34.66/vb/01,03,usb,yes,36,34 2006.146.00:18:34.66/vb/02,04,usb,yes,31,31 2006.146.00:18:34.66/vb/03,04,usb,yes,28,31 2006.146.00:18:34.66/vb/04,04,usb,yes,33,32 2006.146.00:18:34.66/vb/05,04,usb,yes,25,28 2006.146.00:18:34.66/vb/06,04,usb,yes,30,26 2006.146.00:18:34.66/vb/07,04,usb,yes,29,29 2006.146.00:18:34.66/vb/08,04,usb,yes,27,30 2006.146.00:18:34.89/vblo/01,629.99,yes,locked 2006.146.00:18:34.89/vblo/02,634.99,yes,locked 2006.146.00:18:34.89/vblo/03,649.99,yes,locked 2006.146.00:18:34.89/vblo/04,679.99,yes,locked 2006.146.00:18:34.89/vblo/05,709.99,yes,locked 2006.146.00:18:34.89/vblo/06,719.99,yes,locked 2006.146.00:18:34.89/vblo/07,734.99,yes,locked 2006.146.00:18:34.89/vblo/08,744.99,yes,locked 2006.146.00:18:35.04/vabw/8 2006.146.00:18:35.19/vbbw/8 2006.146.00:18:35.28/xfe/off,on,15.2 2006.146.00:18:35.65/ifatt/23,28,28,28 2006.146.00:18:36.07/fmout-gps/S +3.8E-08 2006.146.00:18:36.15:!2006.146.00:21:31 2006.146.00:21:31.00:data_valid=off 2006.146.00:21:31.00:"et 2006.146.00:21:31.01:!+3s 2006.146.00:21:34.02:"tape 2006.146.00:21:34.02:postob 2006.146.00:21:34.13/cable/+6.5450E-03 2006.146.00:21:34.13/wx/20.36,1020.7,70 2006.146.00:21:35.07/fmout-gps/S +3.9E-08 2006.146.00:21:35.07:scan_name=146-0032,jd0605,80 2006.146.00:21:35.08:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.146.00:21:35.14#flagr#flagr/antenna,new-source 2006.146.00:21:36.14:checkk5 2006.146.00:21:36.57/chk_autoobs//k5ts1/ autoobs is running! 2006.146.00:21:37.01/chk_autoobs//k5ts2/ autoobs is running! 2006.146.00:21:37.45/chk_autoobs//k5ts3/ autoobs is running! 2006.146.00:21:37.88/chk_autoobs//k5ts4/ autoobs is running! 2006.146.00:21:38.32/chk_obsdata//k5ts1/T1460018??a.dat file size is correct (nominal:720MB, actual:720MB). 2006.146.00:21:38.77/chk_obsdata//k5ts2/T1460018??b.dat file size is correct (nominal:720MB, actual:720MB). 2006.146.00:21:39.22/chk_obsdata//k5ts3/T1460018??c.dat file size is correct (nominal:720MB, actual:720MB). 2006.146.00:21:39.64/chk_obsdata//k5ts4/T1460018??d.dat file size is correct (nominal:720MB, actual:720MB). 2006.146.00:21:40.40/k5log//k5ts1_log_newline 2006.146.00:21:41.14/k5log//k5ts2_log_newline 2006.146.00:21:41.88/k5log//k5ts3_log_newline 2006.146.00:21:42.65/k5log//k5ts4_log_newline 2006.146.00:21:42.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.146.00:21:42.67:setupk4=1 2006.146.00:21:42.67$setupk4/echo=on 2006.146.00:21:42.67$setupk4/pcalon 2006.146.00:21:42.67$pcalon/"no phase cal control is implemented here 2006.146.00:21:42.67$setupk4/"tpicd=stop 2006.146.00:21:42.67$setupk4/"rec=synch_on 2006.146.00:21:42.67$setupk4/"rec_mode=128 2006.146.00:21:42.67$setupk4/!* 2006.146.00:21:42.67$setupk4/recpk4 2006.146.00:21:42.67$recpk4/recpatch= 2006.146.00:21:42.67$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.146.00:21:42.67$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.146.00:21:42.67$setupk4/vck44 2006.146.00:21:42.67$vck44/valo=1,524.99 2006.146.00:21:42.67#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.146.00:21:42.67#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.146.00:21:42.67#ibcon#ireg 17 cls_cnt 0 2006.146.00:21:42.67#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.146.00:21:42.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.146.00:21:42.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.146.00:21:42.71#ibcon#[26=FRQ=01,524.99\r\n] 2006.146.00:21:42.76#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.146.00:21:42.76#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.146.00:21:42.76#ibcon#about to clear, iclass 34 cls_cnt 0 2006.146.00:21:42.76#ibcon#cleared, iclass 34 cls_cnt 0 2006.146.00:21:42.76$vck44/va=1,8 2006.146.00:21:42.76#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.146.00:21:42.76#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.146.00:21:42.76#ibcon#ireg 11 cls_cnt 2 2006.146.00:21:42.76#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.146.00:21:42.76#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.146.00:21:42.76#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.146.00:21:42.78#ibcon#[25=AT01-08\r\n] 2006.146.00:21:42.81#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.146.00:21:42.81#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.146.00:21:42.81#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.146.00:21:42.81#ibcon#ireg 7 cls_cnt 0 2006.146.00:21:42.81#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.146.00:21:42.93#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.146.00:21:42.93#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.146.00:21:42.95#ibcon#[25=USB\r\n] 2006.146.00:21:42.98#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.146.00:21:42.98#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.146.00:21:42.98#ibcon#about to clear, iclass 36 cls_cnt 0 2006.146.00:21:42.98#ibcon#cleared, iclass 36 cls_cnt 0 2006.146.00:21:42.98$vck44/valo=2,534.99 2006.146.00:21:42.98#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.146.00:21:42.98#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.146.00:21:42.98#ibcon#ireg 17 cls_cnt 0 2006.146.00:21:42.98#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.146.00:21:42.98#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.146.00:21:42.98#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.146.00:21:42.99#abcon#<5=/08 1.9 5.6 20.36 701020.7\r\n> 2006.146.00:21:43.00#ibcon#[26=FRQ=02,534.99\r\n] 2006.146.00:21:43.01#abcon#{5=INTERFACE CLEAR} 2006.146.00:21:43.04#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.146.00:21:43.04#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.146.00:21:43.04#ibcon#about to clear, iclass 39 cls_cnt 0 2006.146.00:21:43.04#ibcon#cleared, iclass 39 cls_cnt 0 2006.146.00:21:43.04$vck44/va=2,7 2006.146.00:21:43.04#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.146.00:21:43.04#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.146.00:21:43.04#ibcon#ireg 11 cls_cnt 2 2006.146.00:21:43.04#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:21:43.07#abcon#[5=S1D000X0/0*\r\n] 2006.146.00:21:43.10#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:21:43.10#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:21:43.12#ibcon#[25=AT02-07\r\n] 2006.146.00:21:43.15#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:21:43.15#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:21:43.15#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.146.00:21:43.15#ibcon#ireg 7 cls_cnt 0 2006.146.00:21:43.15#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:21:43.27#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:21:43.27#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:21:43.29#ibcon#[25=USB\r\n] 2006.146.00:21:43.32#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:21:43.32#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:21:43.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.146.00:21:43.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.146.00:21:43.32$vck44/valo=3,564.99 2006.146.00:21:43.32#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.146.00:21:43.32#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.146.00:21:43.32#ibcon#ireg 17 cls_cnt 0 2006.146.00:21:43.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.146.00:21:43.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.146.00:21:43.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.146.00:21:43.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.146.00:21:43.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.146.00:21:43.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.146.00:21:43.38#ibcon#about to clear, iclass 10 cls_cnt 0 2006.146.00:21:43.38#ibcon#cleared, iclass 10 cls_cnt 0 2006.146.00:21:43.38$vck44/va=3,8 2006.146.00:21:43.38#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.146.00:21:43.38#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.146.00:21:43.38#ibcon#ireg 11 cls_cnt 2 2006.146.00:21:43.38#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.146.00:21:43.44#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.146.00:21:43.44#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.146.00:21:43.46#ibcon#[25=AT03-08\r\n] 2006.146.00:21:43.49#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.146.00:21:43.49#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.146.00:21:43.49#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.146.00:21:43.49#ibcon#ireg 7 cls_cnt 0 2006.146.00:21:43.49#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.146.00:21:43.61#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.146.00:21:43.61#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.146.00:21:43.63#ibcon#[25=USB\r\n] 2006.146.00:21:43.66#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.146.00:21:43.66#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.146.00:21:43.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.146.00:21:43.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.146.00:21:43.66$vck44/valo=4,624.99 2006.146.00:21:43.66#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.146.00:21:43.66#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.146.00:21:43.66#ibcon#ireg 17 cls_cnt 0 2006.146.00:21:43.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.146.00:21:43.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.146.00:21:43.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.146.00:21:43.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.146.00:21:43.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.146.00:21:43.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.146.00:21:43.72#ibcon#about to clear, iclass 14 cls_cnt 0 2006.146.00:21:43.72#ibcon#cleared, iclass 14 cls_cnt 0 2006.146.00:21:43.72$vck44/va=4,7 2006.146.00:21:43.72#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.146.00:21:43.72#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.146.00:21:43.72#ibcon#ireg 11 cls_cnt 2 2006.146.00:21:43.72#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.146.00:21:43.78#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.146.00:21:43.78#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.146.00:21:43.80#ibcon#[25=AT04-07\r\n] 2006.146.00:21:43.83#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.146.00:21:43.83#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.146.00:21:43.83#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.146.00:21:43.83#ibcon#ireg 7 cls_cnt 0 2006.146.00:21:43.83#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.146.00:21:43.95#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.146.00:21:43.95#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.146.00:21:43.97#ibcon#[25=USB\r\n] 2006.146.00:21:44.00#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.146.00:21:44.00#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.146.00:21:44.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.146.00:21:44.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.146.00:21:44.00$vck44/valo=5,734.99 2006.146.00:21:44.00#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.146.00:21:44.00#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.146.00:21:44.00#ibcon#ireg 17 cls_cnt 0 2006.146.00:21:44.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.146.00:21:44.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.146.00:21:44.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.146.00:21:44.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.146.00:21:44.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.146.00:21:44.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.146.00:21:44.06#ibcon#about to clear, iclass 18 cls_cnt 0 2006.146.00:21:44.06#ibcon#cleared, iclass 18 cls_cnt 0 2006.146.00:21:44.06$vck44/va=5,4 2006.146.00:21:44.06#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.146.00:21:44.06#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.146.00:21:44.06#ibcon#ireg 11 cls_cnt 2 2006.146.00:21:44.06#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.146.00:21:44.12#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.146.00:21:44.12#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.146.00:21:44.14#ibcon#[25=AT05-04\r\n] 2006.146.00:21:44.17#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.146.00:21:44.17#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.146.00:21:44.17#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.146.00:21:44.17#ibcon#ireg 7 cls_cnt 0 2006.146.00:21:44.17#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.146.00:21:44.29#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.146.00:21:44.29#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.146.00:21:44.31#ibcon#[25=USB\r\n] 2006.146.00:21:44.34#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.146.00:21:44.34#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.146.00:21:44.34#ibcon#about to clear, iclass 20 cls_cnt 0 2006.146.00:21:44.34#ibcon#cleared, iclass 20 cls_cnt 0 2006.146.00:21:44.34$vck44/valo=6,814.99 2006.146.00:21:44.34#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.146.00:21:44.34#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.146.00:21:44.34#ibcon#ireg 17 cls_cnt 0 2006.146.00:21:44.34#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.146.00:21:44.34#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.146.00:21:44.34#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.146.00:21:44.36#ibcon#[26=FRQ=06,814.99\r\n] 2006.146.00:21:44.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.146.00:21:44.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.146.00:21:44.40#ibcon#about to clear, iclass 22 cls_cnt 0 2006.146.00:21:44.40#ibcon#cleared, iclass 22 cls_cnt 0 2006.146.00:21:44.40$vck44/va=6,4 2006.146.00:21:44.40#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.146.00:21:44.40#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.146.00:21:44.40#ibcon#ireg 11 cls_cnt 2 2006.146.00:21:44.40#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.146.00:21:44.46#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.146.00:21:44.46#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.146.00:21:44.48#ibcon#[25=AT06-04\r\n] 2006.146.00:21:44.51#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.146.00:21:44.51#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.146.00:21:44.51#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.146.00:21:44.51#ibcon#ireg 7 cls_cnt 0 2006.146.00:21:44.51#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.146.00:21:44.63#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.146.00:21:44.63#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.146.00:21:44.65#ibcon#[25=USB\r\n] 2006.146.00:21:44.68#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.146.00:21:44.68#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.146.00:21:44.68#ibcon#about to clear, iclass 24 cls_cnt 0 2006.146.00:21:44.68#ibcon#cleared, iclass 24 cls_cnt 0 2006.146.00:21:44.68$vck44/valo=7,864.99 2006.146.00:21:44.68#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.146.00:21:44.68#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.146.00:21:44.68#ibcon#ireg 17 cls_cnt 0 2006.146.00:21:44.68#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.146.00:21:44.68#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.146.00:21:44.68#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.146.00:21:44.70#ibcon#[26=FRQ=07,864.99\r\n] 2006.146.00:21:44.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.146.00:21:44.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.146.00:21:44.74#ibcon#about to clear, iclass 26 cls_cnt 0 2006.146.00:21:44.74#ibcon#cleared, iclass 26 cls_cnt 0 2006.146.00:21:44.74$vck44/va=7,4 2006.146.00:21:44.74#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.146.00:21:44.74#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.146.00:21:44.74#ibcon#ireg 11 cls_cnt 2 2006.146.00:21:44.74#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.146.00:21:44.80#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.146.00:21:44.80#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.146.00:21:44.82#ibcon#[25=AT07-04\r\n] 2006.146.00:21:44.85#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.146.00:21:44.85#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.146.00:21:44.85#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.146.00:21:44.85#ibcon#ireg 7 cls_cnt 0 2006.146.00:21:44.85#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.146.00:21:44.97#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.146.00:21:44.97#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.146.00:21:44.99#ibcon#[25=USB\r\n] 2006.146.00:21:45.02#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.146.00:21:45.02#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.146.00:21:45.02#ibcon#about to clear, iclass 28 cls_cnt 0 2006.146.00:21:45.02#ibcon#cleared, iclass 28 cls_cnt 0 2006.146.00:21:45.02$vck44/valo=8,884.99 2006.146.00:21:45.02#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.146.00:21:45.02#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.146.00:21:45.02#ibcon#ireg 17 cls_cnt 0 2006.146.00:21:45.02#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.146.00:21:45.02#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.146.00:21:45.02#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.146.00:21:45.04#ibcon#[26=FRQ=08,884.99\r\n] 2006.146.00:21:45.08#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.146.00:21:45.08#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.146.00:21:45.08#ibcon#about to clear, iclass 30 cls_cnt 0 2006.146.00:21:45.08#ibcon#cleared, iclass 30 cls_cnt 0 2006.146.00:21:45.08$vck44/va=8,4 2006.146.00:21:45.08#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.146.00:21:45.08#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.146.00:21:45.08#ibcon#ireg 11 cls_cnt 2 2006.146.00:21:45.08#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.146.00:21:45.14#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.146.00:21:45.14#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.146.00:21:45.16#ibcon#[25=AT08-04\r\n] 2006.146.00:21:45.19#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.146.00:21:45.19#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.146.00:21:45.19#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.146.00:21:45.19#ibcon#ireg 7 cls_cnt 0 2006.146.00:21:45.19#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.146.00:21:45.31#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.146.00:21:45.31#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.146.00:21:45.33#ibcon#[25=USB\r\n] 2006.146.00:21:45.36#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.146.00:21:45.36#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.146.00:21:45.36#ibcon#about to clear, iclass 32 cls_cnt 0 2006.146.00:21:45.36#ibcon#cleared, iclass 32 cls_cnt 0 2006.146.00:21:45.36$vck44/vblo=1,629.99 2006.146.00:21:45.36#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.146.00:21:45.36#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.146.00:21:45.36#ibcon#ireg 17 cls_cnt 0 2006.146.00:21:45.36#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.146.00:21:45.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.146.00:21:45.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.146.00:21:45.38#ibcon#[28=FRQ=01,629.99\r\n] 2006.146.00:21:45.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.146.00:21:45.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.146.00:21:45.42#ibcon#about to clear, iclass 34 cls_cnt 0 2006.146.00:21:45.42#ibcon#cleared, iclass 34 cls_cnt 0 2006.146.00:21:45.42$vck44/vb=1,3 2006.146.00:21:45.42#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.146.00:21:45.42#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.146.00:21:45.42#ibcon#ireg 11 cls_cnt 2 2006.146.00:21:45.42#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.146.00:21:45.42#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.146.00:21:45.42#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.146.00:21:45.44#ibcon#[27=AT01-03\r\n] 2006.146.00:21:45.47#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.146.00:21:45.47#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.146.00:21:45.47#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.146.00:21:45.47#ibcon#ireg 7 cls_cnt 0 2006.146.00:21:45.47#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.146.00:21:45.59#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.146.00:21:45.59#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.146.00:21:45.61#ibcon#[27=USB\r\n] 2006.146.00:21:45.64#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.146.00:21:45.64#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.146.00:21:45.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.146.00:21:45.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.146.00:21:45.64$vck44/vblo=2,634.99 2006.146.00:21:45.64#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.146.00:21:45.64#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.146.00:21:45.64#ibcon#ireg 17 cls_cnt 0 2006.146.00:21:45.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.146.00:21:45.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.146.00:21:45.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.146.00:21:45.66#ibcon#[28=FRQ=02,634.99\r\n] 2006.146.00:21:45.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.146.00:21:45.70#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.146.00:21:45.70#ibcon#about to clear, iclass 38 cls_cnt 0 2006.146.00:21:45.70#ibcon#cleared, iclass 38 cls_cnt 0 2006.146.00:21:45.70$vck44/vb=2,4 2006.146.00:21:45.70#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.146.00:21:45.70#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.146.00:21:45.70#ibcon#ireg 11 cls_cnt 2 2006.146.00:21:45.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.146.00:21:45.76#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.146.00:21:45.76#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.146.00:21:45.78#ibcon#[27=AT02-04\r\n] 2006.146.00:21:45.81#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.146.00:21:45.81#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.146.00:21:45.81#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.146.00:21:45.81#ibcon#ireg 7 cls_cnt 0 2006.146.00:21:45.81#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.146.00:21:45.93#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.146.00:21:45.93#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.146.00:21:45.95#ibcon#[27=USB\r\n] 2006.146.00:21:45.98#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.146.00:21:45.98#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.146.00:21:45.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.146.00:21:45.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.146.00:21:45.98$vck44/vblo=3,649.99 2006.146.00:21:45.98#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.146.00:21:45.98#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.146.00:21:45.98#ibcon#ireg 17 cls_cnt 0 2006.146.00:21:45.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.146.00:21:45.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.146.00:21:45.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.146.00:21:46.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.146.00:21:46.04#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.146.00:21:46.04#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.146.00:21:46.04#ibcon#about to clear, iclass 4 cls_cnt 0 2006.146.00:21:46.04#ibcon#cleared, iclass 4 cls_cnt 0 2006.146.00:21:46.04$vck44/vb=3,4 2006.146.00:21:46.04#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.146.00:21:46.04#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.146.00:21:46.04#ibcon#ireg 11 cls_cnt 2 2006.146.00:21:46.04#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.146.00:21:46.10#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.146.00:21:46.10#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.146.00:21:46.12#ibcon#[27=AT03-04\r\n] 2006.146.00:21:46.15#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.146.00:21:46.15#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.146.00:21:46.15#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.146.00:21:46.15#ibcon#ireg 7 cls_cnt 0 2006.146.00:21:46.15#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.146.00:21:46.27#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.146.00:21:46.27#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.146.00:21:46.29#ibcon#[27=USB\r\n] 2006.146.00:21:46.32#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.146.00:21:46.32#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.146.00:21:46.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.146.00:21:46.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.146.00:21:46.32$vck44/vblo=4,679.99 2006.146.00:21:46.32#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.146.00:21:46.32#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.146.00:21:46.32#ibcon#ireg 17 cls_cnt 0 2006.146.00:21:46.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.146.00:21:46.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.146.00:21:46.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.146.00:21:46.34#ibcon#[28=FRQ=04,679.99\r\n] 2006.146.00:21:46.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.146.00:21:46.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.146.00:21:46.38#ibcon#about to clear, iclass 10 cls_cnt 0 2006.146.00:21:46.38#ibcon#cleared, iclass 10 cls_cnt 0 2006.146.00:21:46.38$vck44/vb=4,4 2006.146.00:21:46.38#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.146.00:21:46.38#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.146.00:21:46.38#ibcon#ireg 11 cls_cnt 2 2006.146.00:21:46.38#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.146.00:21:46.44#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.146.00:21:46.44#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.146.00:21:46.46#ibcon#[27=AT04-04\r\n] 2006.146.00:21:46.49#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.146.00:21:46.49#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.146.00:21:46.49#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.146.00:21:46.49#ibcon#ireg 7 cls_cnt 0 2006.146.00:21:46.49#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.146.00:21:46.61#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.146.00:21:46.61#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.146.00:21:46.63#ibcon#[27=USB\r\n] 2006.146.00:21:46.66#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.146.00:21:46.66#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.146.00:21:46.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.146.00:21:46.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.146.00:21:46.66$vck44/vblo=5,709.99 2006.146.00:21:46.66#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.146.00:21:46.66#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.146.00:21:46.66#ibcon#ireg 17 cls_cnt 0 2006.146.00:21:46.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.146.00:21:46.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.146.00:21:46.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.146.00:21:46.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.146.00:21:46.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.146.00:21:46.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.146.00:21:46.72#ibcon#about to clear, iclass 14 cls_cnt 0 2006.146.00:21:46.72#ibcon#cleared, iclass 14 cls_cnt 0 2006.146.00:21:46.72$vck44/vb=5,4 2006.146.00:21:46.72#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.146.00:21:46.72#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.146.00:21:46.72#ibcon#ireg 11 cls_cnt 2 2006.146.00:21:46.72#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.146.00:21:46.78#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.146.00:21:46.78#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.146.00:21:46.80#ibcon#[27=AT05-04\r\n] 2006.146.00:21:46.83#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.146.00:21:46.83#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.146.00:21:46.83#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.146.00:21:46.83#ibcon#ireg 7 cls_cnt 0 2006.146.00:21:46.83#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.146.00:21:46.95#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.146.00:21:46.95#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.146.00:21:46.97#ibcon#[27=USB\r\n] 2006.146.00:21:47.00#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.146.00:21:47.00#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.146.00:21:47.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.146.00:21:47.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.146.00:21:47.00$vck44/vblo=6,719.99 2006.146.00:21:47.00#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.146.00:21:47.00#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.146.00:21:47.00#ibcon#ireg 17 cls_cnt 0 2006.146.00:21:47.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.146.00:21:47.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.146.00:21:47.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.146.00:21:47.02#ibcon#[28=FRQ=06,719.99\r\n] 2006.146.00:21:47.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.146.00:21:47.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.146.00:21:47.06#ibcon#about to clear, iclass 18 cls_cnt 0 2006.146.00:21:47.06#ibcon#cleared, iclass 18 cls_cnt 0 2006.146.00:21:47.06$vck44/vb=6,4 2006.146.00:21:47.06#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.146.00:21:47.06#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.146.00:21:47.06#ibcon#ireg 11 cls_cnt 2 2006.146.00:21:47.06#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.146.00:21:47.12#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.146.00:21:47.12#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.146.00:21:47.14#ibcon#[27=AT06-04\r\n] 2006.146.00:21:47.17#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.146.00:21:47.17#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.146.00:21:47.17#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.146.00:21:47.17#ibcon#ireg 7 cls_cnt 0 2006.146.00:21:47.17#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.146.00:21:47.29#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.146.00:21:47.29#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.146.00:21:47.31#ibcon#[27=USB\r\n] 2006.146.00:21:47.34#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.146.00:21:47.34#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.146.00:21:47.34#ibcon#about to clear, iclass 20 cls_cnt 0 2006.146.00:21:47.34#ibcon#cleared, iclass 20 cls_cnt 0 2006.146.00:21:47.34$vck44/vblo=7,734.99 2006.146.00:21:47.34#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.146.00:21:47.34#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.146.00:21:47.34#ibcon#ireg 17 cls_cnt 0 2006.146.00:21:47.34#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.146.00:21:47.34#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.146.00:21:47.34#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.146.00:21:47.36#ibcon#[28=FRQ=07,734.99\r\n] 2006.146.00:21:47.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.146.00:21:47.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.146.00:21:47.40#ibcon#about to clear, iclass 22 cls_cnt 0 2006.146.00:21:47.40#ibcon#cleared, iclass 22 cls_cnt 0 2006.146.00:21:47.40$vck44/vb=7,4 2006.146.00:21:47.40#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.146.00:21:47.40#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.146.00:21:47.40#ibcon#ireg 11 cls_cnt 2 2006.146.00:21:47.40#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.146.00:21:47.46#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.146.00:21:47.46#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.146.00:21:47.48#ibcon#[27=AT07-04\r\n] 2006.146.00:21:47.51#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.146.00:21:47.51#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.146.00:21:47.51#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.146.00:21:47.51#ibcon#ireg 7 cls_cnt 0 2006.146.00:21:47.51#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.146.00:21:47.63#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.146.00:21:47.63#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.146.00:21:47.65#ibcon#[27=USB\r\n] 2006.146.00:21:47.68#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.146.00:21:47.68#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.146.00:21:47.68#ibcon#about to clear, iclass 24 cls_cnt 0 2006.146.00:21:47.68#ibcon#cleared, iclass 24 cls_cnt 0 2006.146.00:21:47.68$vck44/vblo=8,744.99 2006.146.00:21:47.68#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.146.00:21:47.68#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.146.00:21:47.68#ibcon#ireg 17 cls_cnt 0 2006.146.00:21:47.68#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.146.00:21:47.68#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.146.00:21:47.68#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.146.00:21:47.70#ibcon#[28=FRQ=08,744.99\r\n] 2006.146.00:21:47.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.146.00:21:47.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.146.00:21:47.74#ibcon#about to clear, iclass 26 cls_cnt 0 2006.146.00:21:47.74#ibcon#cleared, iclass 26 cls_cnt 0 2006.146.00:21:47.74$vck44/vb=8,4 2006.146.00:21:47.74#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.146.00:21:47.74#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.146.00:21:47.74#ibcon#ireg 11 cls_cnt 2 2006.146.00:21:47.74#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.146.00:21:47.80#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.146.00:21:47.80#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.146.00:21:47.82#ibcon#[27=AT08-04\r\n] 2006.146.00:21:47.85#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.146.00:21:47.85#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.146.00:21:47.85#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.146.00:21:47.85#ibcon#ireg 7 cls_cnt 0 2006.146.00:21:47.85#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.146.00:21:47.97#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.146.00:21:47.97#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.146.00:21:47.99#ibcon#[27=USB\r\n] 2006.146.00:21:48.02#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.146.00:21:48.02#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.146.00:21:48.02#ibcon#about to clear, iclass 28 cls_cnt 0 2006.146.00:21:48.02#ibcon#cleared, iclass 28 cls_cnt 0 2006.146.00:21:48.02$vck44/vabw=wide 2006.146.00:21:48.02#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.146.00:21:48.02#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.146.00:21:48.02#ibcon#ireg 8 cls_cnt 0 2006.146.00:21:48.02#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.146.00:21:48.02#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.146.00:21:48.02#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.146.00:21:48.04#ibcon#[25=BW32\r\n] 2006.146.00:21:48.07#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.146.00:21:48.07#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.146.00:21:48.07#ibcon#about to clear, iclass 30 cls_cnt 0 2006.146.00:21:48.07#ibcon#cleared, iclass 30 cls_cnt 0 2006.146.00:21:48.07$vck44/vbbw=wide 2006.146.00:21:48.07#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.146.00:21:48.07#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.146.00:21:48.07#ibcon#ireg 8 cls_cnt 0 2006.146.00:21:48.07#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.146.00:21:48.14#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.146.00:21:48.14#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.146.00:21:48.16#ibcon#[27=BW32\r\n] 2006.146.00:21:48.19#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.146.00:21:48.19#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.146.00:21:48.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.146.00:21:48.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.146.00:21:48.19$setupk4/ifdk4 2006.146.00:21:48.19$ifdk4/lo= 2006.146.00:21:48.19$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.146.00:21:48.19$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.146.00:21:48.19$ifdk4/patch= 2006.146.00:21:48.19$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.146.00:21:48.19$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.146.00:21:48.19$setupk4/!*+20s 2006.146.00:21:53.16#abcon#<5=/08 1.9 5.6 20.36 701020.7\r\n> 2006.146.00:21:53.18#abcon#{5=INTERFACE CLEAR} 2006.146.00:21:53.24#abcon#[5=S1D000X0/0*\r\n] 2006.146.00:22:02.68$setupk4/"tpicd 2006.146.00:22:02.68$setupk4/echo=off 2006.146.00:22:02.68$setupk4/xlog=off 2006.146.00:22:02.68:!2006.146.00:32:06 2006.146.00:22:13.14#trakl#Source acquired 2006.146.00:22:14.14#flagr#flagr/antenna,acquired 2006.146.00:32:06.00:preob 2006.146.00:32:06.14/onsource/TRACKING 2006.146.00:32:06.14:!2006.146.00:32:16 2006.146.00:32:16.00:"tape 2006.146.00:32:16.00:"st=record 2006.146.00:32:16.00:data_valid=on 2006.146.00:32:16.00:midob 2006.146.00:32:17.14/onsource/TRACKING 2006.146.00:32:17.14/wx/20.43,1020.7,71 2006.146.00:32:17.24/cable/+6.5460E-03 2006.146.00:32:18.33/va/01,08,usb,yes,29,31 2006.146.00:32:18.33/va/02,07,usb,yes,31,32 2006.146.00:32:18.33/va/03,08,usb,yes,28,29 2006.146.00:32:18.33/va/04,07,usb,yes,32,34 2006.146.00:32:18.33/va/05,04,usb,yes,28,29 2006.146.00:32:18.33/va/06,04,usb,yes,31,31 2006.146.00:32:18.33/va/07,04,usb,yes,32,33 2006.146.00:32:18.33/va/08,04,usb,yes,27,33 2006.146.00:32:18.56/valo/01,524.99,yes,locked 2006.146.00:32:18.56/valo/02,534.99,yes,locked 2006.146.00:32:18.56/valo/03,564.99,yes,locked 2006.146.00:32:18.56/valo/04,624.99,yes,locked 2006.146.00:32:18.56/valo/05,734.99,yes,locked 2006.146.00:32:18.56/valo/06,814.99,yes,locked 2006.146.00:32:18.56/valo/07,864.99,yes,locked 2006.146.00:32:18.56/valo/08,884.99,yes,locked 2006.146.00:32:19.65/vb/01,03,usb,yes,37,34 2006.146.00:32:19.65/vb/02,04,usb,yes,32,32 2006.146.00:32:19.65/vb/03,04,usb,yes,29,32 2006.146.00:32:19.65/vb/04,04,usb,yes,33,32 2006.146.00:32:19.65/vb/05,04,usb,yes,26,28 2006.146.00:32:19.65/vb/06,04,usb,yes,30,27 2006.146.00:32:19.65/vb/07,04,usb,yes,30,30 2006.146.00:32:19.65/vb/08,04,usb,yes,28,31 2006.146.00:32:19.89/vblo/01,629.99,yes,locked 2006.146.00:32:19.89/vblo/02,634.99,yes,locked 2006.146.00:32:19.89/vblo/03,649.99,yes,locked 2006.146.00:32:19.89/vblo/04,679.99,yes,locked 2006.146.00:32:19.89/vblo/05,709.99,yes,locked 2006.146.00:32:19.89/vblo/06,719.99,yes,locked 2006.146.00:32:19.89/vblo/07,734.99,yes,locked 2006.146.00:32:19.89/vblo/08,744.99,yes,locked 2006.146.00:32:20.04/vabw/8 2006.146.00:32:20.19/vbbw/8 2006.146.00:32:20.28/xfe/off,on,14.2 2006.146.00:32:20.66/ifatt/23,28,28,28 2006.146.00:32:21.07/fmout-gps/S +4.3E-08 2006.146.00:32:21.11:!2006.146.00:33:36 2006.146.00:33:36.02:data_valid=off 2006.146.00:33:36.02:"et 2006.146.00:33:36.02:!+3s 2006.146.00:33:39.05:"tape 2006.146.00:33:39.10:postob 2006.146.00:33:39.29/cable/+6.5430E-03 2006.146.00:33:39.30/wx/20.45,1020.7,71 2006.146.00:33:39.38/fmout-gps/S +4.2E-08 2006.146.00:33:39.38:scan_name=146-0037,jd0605,210 2006.146.00:33:39.38:source=3c446,222547.26,-045701.4,2000.0,ccw 2006.146.00:33:40.15#flagr#flagr/antenna,new-source 2006.146.00:33:40.15:checkk5 2006.146.00:33:40.58/chk_autoobs//k5ts1/ autoobs is running! 2006.146.00:33:41.03/chk_autoobs//k5ts2/ autoobs is running! 2006.146.00:33:41.48/chk_autoobs//k5ts3/ autoobs is running! 2006.146.00:33:41.91/chk_autoobs//k5ts4/ autoobs is running! 2006.146.00:33:42.34/chk_obsdata//k5ts1/T1460032??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.146.00:33:42.78/chk_obsdata//k5ts2/T1460032??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.146.00:33:43.23/chk_obsdata//k5ts3/T1460032??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.146.00:33:43.65/chk_obsdata//k5ts4/T1460032??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.146.00:33:44.43/k5log//k5ts1_log_newline 2006.146.00:33:45.18/k5log//k5ts2_log_newline 2006.146.00:33:45.94/k5log//k5ts3_log_newline 2006.146.00:33:46.69/k5log//k5ts4_log_newline 2006.146.00:33:46.71/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.146.00:33:46.71:setupk4=1 2006.146.00:33:46.71$setupk4/echo=on 2006.146.00:33:46.71$setupk4/pcalon 2006.146.00:33:46.71$pcalon/"no phase cal control is implemented here 2006.146.00:33:46.71$setupk4/"tpicd=stop 2006.146.00:33:46.72$setupk4/"rec=synch_on 2006.146.00:33:46.72$setupk4/"rec_mode=128 2006.146.00:33:46.72$setupk4/!* 2006.146.00:33:46.72$setupk4/recpk4 2006.146.00:33:46.72$recpk4/recpatch= 2006.146.00:33:46.72$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.146.00:33:46.72$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.146.00:33:46.72$setupk4/vck44 2006.146.00:33:46.72$vck44/valo=1,524.99 2006.146.00:33:46.72#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.146.00:33:46.72#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.146.00:33:46.72#ibcon#ireg 17 cls_cnt 0 2006.146.00:33:46.72#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.146.00:33:46.72#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.146.00:33:46.72#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.146.00:33:46.76#ibcon#[26=FRQ=01,524.99\r\n] 2006.146.00:33:46.80#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.146.00:33:46.80#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.146.00:33:46.80#ibcon#about to clear, iclass 33 cls_cnt 0 2006.146.00:33:46.80#ibcon#cleared, iclass 33 cls_cnt 0 2006.146.00:33:46.81$vck44/va=1,8 2006.146.00:33:46.81#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.146.00:33:46.81#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.146.00:33:46.81#ibcon#ireg 11 cls_cnt 2 2006.146.00:33:46.81#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.146.00:33:46.81#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.146.00:33:46.81#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.146.00:33:46.82#ibcon#[25=AT01-08\r\n] 2006.146.00:33:46.85#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.146.00:33:46.85#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.146.00:33:46.85#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.146.00:33:46.85#ibcon#ireg 7 cls_cnt 0 2006.146.00:33:46.85#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.146.00:33:46.98#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.146.00:33:46.98#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.146.00:33:47.00#ibcon#[25=USB\r\n] 2006.146.00:33:47.02#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.146.00:33:47.02#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.146.00:33:47.02#ibcon#about to clear, iclass 35 cls_cnt 0 2006.146.00:33:47.02#ibcon#cleared, iclass 35 cls_cnt 0 2006.146.00:33:47.03$vck44/valo=2,534.99 2006.146.00:33:47.03#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.146.00:33:47.03#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.146.00:33:47.03#ibcon#ireg 17 cls_cnt 0 2006.146.00:33:47.03#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:33:47.03#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:33:47.03#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:33:47.06#ibcon#[26=FRQ=02,534.99\r\n] 2006.146.00:33:47.09#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:33:47.09#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:33:47.09#ibcon#about to clear, iclass 37 cls_cnt 0 2006.146.00:33:47.09#ibcon#cleared, iclass 37 cls_cnt 0 2006.146.00:33:47.10$vck44/va=2,7 2006.146.00:33:47.10#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.146.00:33:47.10#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.146.00:33:47.10#ibcon#ireg 11 cls_cnt 2 2006.146.00:33:47.10#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:33:47.13#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:33:47.13#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:33:47.15#ibcon#[25=AT02-07\r\n] 2006.146.00:33:47.18#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:33:47.18#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:33:47.18#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.146.00:33:47.18#ibcon#ireg 7 cls_cnt 0 2006.146.00:33:47.18#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:33:47.30#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:33:47.30#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:33:47.32#ibcon#[25=USB\r\n] 2006.146.00:33:47.35#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:33:47.35#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:33:47.35#ibcon#about to clear, iclass 39 cls_cnt 0 2006.146.00:33:47.35#ibcon#cleared, iclass 39 cls_cnt 0 2006.146.00:33:47.36$vck44/valo=3,564.99 2006.146.00:33:47.36#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.146.00:33:47.36#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.146.00:33:47.36#ibcon#ireg 17 cls_cnt 0 2006.146.00:33:47.36#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:33:47.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:33:47.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:33:47.37#ibcon#[26=FRQ=03,564.99\r\n] 2006.146.00:33:47.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:33:47.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:33:47.41#ibcon#about to clear, iclass 3 cls_cnt 0 2006.146.00:33:47.41#ibcon#cleared, iclass 3 cls_cnt 0 2006.146.00:33:47.42$vck44/va=3,8 2006.146.00:33:47.42#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.146.00:33:47.42#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.146.00:33:47.42#ibcon#ireg 11 cls_cnt 2 2006.146.00:33:47.42#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:33:47.46#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:33:47.46#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:33:47.48#ibcon#[25=AT03-08\r\n] 2006.146.00:33:47.51#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:33:47.51#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:33:47.51#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.146.00:33:47.51#ibcon#ireg 7 cls_cnt 0 2006.146.00:33:47.51#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:33:47.63#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:33:47.63#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:33:47.65#ibcon#[25=USB\r\n] 2006.146.00:33:47.68#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:33:47.68#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:33:47.68#ibcon#about to clear, iclass 5 cls_cnt 0 2006.146.00:33:47.68#ibcon#cleared, iclass 5 cls_cnt 0 2006.146.00:33:47.69$vck44/valo=4,624.99 2006.146.00:33:47.69#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.146.00:33:47.69#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.146.00:33:47.69#ibcon#ireg 17 cls_cnt 0 2006.146.00:33:47.69#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:33:47.69#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:33:47.69#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:33:47.70#ibcon#[26=FRQ=04,624.99\r\n] 2006.146.00:33:47.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:33:47.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:33:47.74#ibcon#about to clear, iclass 7 cls_cnt 0 2006.146.00:33:47.74#ibcon#cleared, iclass 7 cls_cnt 0 2006.146.00:33:47.75$vck44/va=4,7 2006.146.00:33:47.75#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.146.00:33:47.75#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.146.00:33:47.75#ibcon#ireg 11 cls_cnt 2 2006.146.00:33:47.75#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.146.00:33:47.79#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.146.00:33:47.79#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.146.00:33:47.81#ibcon#[25=AT04-07\r\n] 2006.146.00:33:47.84#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.146.00:33:47.84#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.146.00:33:47.84#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.146.00:33:47.84#ibcon#ireg 7 cls_cnt 0 2006.146.00:33:47.84#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.146.00:33:47.96#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.146.00:33:47.96#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.146.00:33:47.98#ibcon#[25=USB\r\n] 2006.146.00:33:48.01#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.146.00:33:48.01#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.146.00:33:48.01#ibcon#about to clear, iclass 11 cls_cnt 0 2006.146.00:33:48.01#ibcon#cleared, iclass 11 cls_cnt 0 2006.146.00:33:48.02$vck44/valo=5,734.99 2006.146.00:33:48.02#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.146.00:33:48.02#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.146.00:33:48.02#ibcon#ireg 17 cls_cnt 0 2006.146.00:33:48.02#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.146.00:33:48.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.146.00:33:48.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.146.00:33:48.03#ibcon#[26=FRQ=05,734.99\r\n] 2006.146.00:33:48.09#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.146.00:33:48.09#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.146.00:33:48.09#ibcon#about to clear, iclass 13 cls_cnt 0 2006.146.00:33:48.09#ibcon#cleared, iclass 13 cls_cnt 0 2006.146.00:33:48.09$vck44/va=5,4 2006.146.00:33:48.09#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.146.00:33:48.09#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.146.00:33:48.09#ibcon#ireg 11 cls_cnt 2 2006.146.00:33:48.09#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.146.00:33:48.12#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.146.00:33:48.12#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.146.00:33:48.15#ibcon#[25=AT05-04\r\n] 2006.146.00:33:48.18#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.146.00:33:48.18#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.146.00:33:48.18#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.146.00:33:48.18#ibcon#ireg 7 cls_cnt 0 2006.146.00:33:48.18#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.146.00:33:48.29#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.146.00:33:48.29#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.146.00:33:48.31#ibcon#[25=USB\r\n] 2006.146.00:33:48.34#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.146.00:33:48.34#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.146.00:33:48.34#ibcon#about to clear, iclass 15 cls_cnt 0 2006.146.00:33:48.34#ibcon#cleared, iclass 15 cls_cnt 0 2006.146.00:33:48.35$vck44/valo=6,814.99 2006.146.00:33:48.35#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.146.00:33:48.35#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.146.00:33:48.35#ibcon#ireg 17 cls_cnt 0 2006.146.00:33:48.35#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:33:48.35#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:33:48.35#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:33:48.38#ibcon#[26=FRQ=06,814.99\r\n] 2006.146.00:33:48.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:33:48.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:33:48.41#ibcon#about to clear, iclass 17 cls_cnt 0 2006.146.00:33:48.41#ibcon#cleared, iclass 17 cls_cnt 0 2006.146.00:33:48.42$vck44/va=6,4 2006.146.00:33:48.42#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.146.00:33:48.42#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.146.00:33:48.42#ibcon#ireg 11 cls_cnt 2 2006.146.00:33:48.42#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:33:48.45#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:33:48.45#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:33:48.47#ibcon#[25=AT06-04\r\n] 2006.146.00:33:48.50#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:33:48.50#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:33:48.50#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.146.00:33:48.50#ibcon#ireg 7 cls_cnt 0 2006.146.00:33:48.50#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:33:48.62#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:33:48.62#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:33:48.64#ibcon#[25=USB\r\n] 2006.146.00:33:48.67#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:33:48.67#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:33:48.67#ibcon#about to clear, iclass 19 cls_cnt 0 2006.146.00:33:48.67#ibcon#cleared, iclass 19 cls_cnt 0 2006.146.00:33:48.68$vck44/valo=7,864.99 2006.146.00:33:48.68#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.146.00:33:48.68#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.146.00:33:48.68#ibcon#ireg 17 cls_cnt 0 2006.146.00:33:48.68#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:33:48.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:33:48.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:33:48.69#ibcon#[26=FRQ=07,864.99\r\n] 2006.146.00:33:48.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:33:48.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:33:48.73#ibcon#about to clear, iclass 21 cls_cnt 0 2006.146.00:33:48.73#ibcon#cleared, iclass 21 cls_cnt 0 2006.146.00:33:48.74$vck44/va=7,4 2006.146.00:33:48.74#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.146.00:33:48.74#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.146.00:33:48.74#ibcon#ireg 11 cls_cnt 2 2006.146.00:33:48.74#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:33:48.78#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:33:48.78#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:33:48.80#ibcon#[25=AT07-04\r\n] 2006.146.00:33:48.83#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:33:48.83#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:33:48.83#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.146.00:33:48.83#ibcon#ireg 7 cls_cnt 0 2006.146.00:33:48.83#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:33:48.95#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:33:48.95#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:33:48.97#ibcon#[25=USB\r\n] 2006.146.00:33:49.00#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:33:49.00#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:33:49.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.146.00:33:49.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.146.00:33:49.01$vck44/valo=8,884.99 2006.146.00:33:49.01#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.146.00:33:49.01#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.146.00:33:49.01#ibcon#ireg 17 cls_cnt 0 2006.146.00:33:49.01#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:33:49.01#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:33:49.01#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:33:49.02#ibcon#[26=FRQ=08,884.99\r\n] 2006.146.00:33:49.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:33:49.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:33:49.06#ibcon#about to clear, iclass 25 cls_cnt 0 2006.146.00:33:49.06#ibcon#cleared, iclass 25 cls_cnt 0 2006.146.00:33:49.07$vck44/va=8,4 2006.146.00:33:49.07#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.146.00:33:49.07#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.146.00:33:49.07#ibcon#ireg 11 cls_cnt 2 2006.146.00:33:49.07#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.146.00:33:49.11#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.146.00:33:49.11#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.146.00:33:49.13#ibcon#[25=AT08-04\r\n] 2006.146.00:33:49.16#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.146.00:33:49.16#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.146.00:33:49.16#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.146.00:33:49.16#ibcon#ireg 7 cls_cnt 0 2006.146.00:33:49.16#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.146.00:33:49.28#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.146.00:33:49.28#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.146.00:33:49.30#ibcon#[25=USB\r\n] 2006.146.00:33:49.33#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.146.00:33:49.33#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.146.00:33:49.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.146.00:33:49.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.146.00:33:49.34$vck44/vblo=1,629.99 2006.146.00:33:49.34#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.146.00:33:49.34#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.146.00:33:49.34#ibcon#ireg 17 cls_cnt 0 2006.146.00:33:49.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:33:49.34#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:33:49.34#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:33:49.35#ibcon#[28=FRQ=01,629.99\r\n] 2006.146.00:33:49.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:33:49.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:33:49.39#ibcon#about to clear, iclass 29 cls_cnt 0 2006.146.00:33:49.39#ibcon#cleared, iclass 29 cls_cnt 0 2006.146.00:33:49.40$vck44/vb=1,3 2006.146.00:33:49.40#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.146.00:33:49.40#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.146.00:33:49.40#ibcon#ireg 11 cls_cnt 2 2006.146.00:33:49.40#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.146.00:33:49.40#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.146.00:33:49.40#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.146.00:33:49.41#ibcon#[27=AT01-03\r\n] 2006.146.00:33:49.44#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.146.00:33:49.44#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.146.00:33:49.44#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.146.00:33:49.44#ibcon#ireg 7 cls_cnt 0 2006.146.00:33:49.44#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.146.00:33:49.56#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.146.00:33:49.56#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.146.00:33:49.58#ibcon#[27=USB\r\n] 2006.146.00:33:49.61#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.146.00:33:49.61#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.146.00:33:49.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.146.00:33:49.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.146.00:33:49.62$vck44/vblo=2,634.99 2006.146.00:33:49.62#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.146.00:33:49.62#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.146.00:33:49.62#ibcon#ireg 17 cls_cnt 0 2006.146.00:33:49.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.146.00:33:49.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.146.00:33:49.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.146.00:33:49.63#ibcon#[28=FRQ=02,634.99\r\n] 2006.146.00:33:49.67#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.146.00:33:49.67#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.146.00:33:49.67#ibcon#about to clear, iclass 33 cls_cnt 0 2006.146.00:33:49.67#ibcon#cleared, iclass 33 cls_cnt 0 2006.146.00:33:49.68$vck44/vb=2,4 2006.146.00:33:49.68#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.146.00:33:49.68#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.146.00:33:49.68#ibcon#ireg 11 cls_cnt 2 2006.146.00:33:49.68#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.146.00:33:49.72#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.146.00:33:49.72#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.146.00:33:49.74#ibcon#[27=AT02-04\r\n] 2006.146.00:33:49.77#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.146.00:33:49.77#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.146.00:33:49.77#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.146.00:33:49.77#ibcon#ireg 7 cls_cnt 0 2006.146.00:33:49.77#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.146.00:33:49.89#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.146.00:33:49.89#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.146.00:33:49.91#ibcon#[27=USB\r\n] 2006.146.00:33:49.94#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.146.00:33:49.94#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.146.00:33:49.94#ibcon#about to clear, iclass 35 cls_cnt 0 2006.146.00:33:49.94#ibcon#cleared, iclass 35 cls_cnt 0 2006.146.00:33:49.95$vck44/vblo=3,649.99 2006.146.00:33:49.95#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.146.00:33:49.95#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.146.00:33:49.95#ibcon#ireg 17 cls_cnt 0 2006.146.00:33:49.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:33:49.95#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:33:49.95#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:33:49.96#ibcon#[28=FRQ=03,649.99\r\n] 2006.146.00:33:50.00#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:33:50.00#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:33:50.00#ibcon#about to clear, iclass 37 cls_cnt 0 2006.146.00:33:50.00#ibcon#cleared, iclass 37 cls_cnt 0 2006.146.00:33:50.01$vck44/vb=3,4 2006.146.00:33:50.01#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.146.00:33:50.01#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.146.00:33:50.01#ibcon#ireg 11 cls_cnt 2 2006.146.00:33:50.01#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:33:50.05#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:33:50.05#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:33:50.07#ibcon#[27=AT03-04\r\n] 2006.146.00:33:50.10#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:33:50.10#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:33:50.10#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.146.00:33:50.10#ibcon#ireg 7 cls_cnt 0 2006.146.00:33:50.10#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:33:50.22#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:33:50.22#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:33:50.24#ibcon#[27=USB\r\n] 2006.146.00:33:50.27#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:33:50.27#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:33:50.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.146.00:33:50.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.146.00:33:50.28$vck44/vblo=4,679.99 2006.146.00:33:50.28#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.146.00:33:50.28#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.146.00:33:50.28#ibcon#ireg 17 cls_cnt 0 2006.146.00:33:50.28#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:33:50.28#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:33:50.28#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:33:50.29#ibcon#[28=FRQ=04,679.99\r\n] 2006.146.00:33:50.33#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:33:50.33#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:33:50.33#ibcon#about to clear, iclass 3 cls_cnt 0 2006.146.00:33:50.33#ibcon#cleared, iclass 3 cls_cnt 0 2006.146.00:33:50.34$vck44/vb=4,4 2006.146.00:33:50.34#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.146.00:33:50.34#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.146.00:33:50.34#ibcon#ireg 11 cls_cnt 2 2006.146.00:33:50.34#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:33:50.38#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:33:50.38#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:33:50.40#ibcon#[27=AT04-04\r\n] 2006.146.00:33:50.43#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:33:50.43#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:33:50.43#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.146.00:33:50.43#ibcon#ireg 7 cls_cnt 0 2006.146.00:33:50.43#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:33:50.55#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:33:50.55#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:33:50.57#ibcon#[27=USB\r\n] 2006.146.00:33:50.60#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:33:50.60#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:33:50.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.146.00:33:50.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.146.00:33:50.61$vck44/vblo=5,709.99 2006.146.00:33:50.61#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.146.00:33:50.61#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.146.00:33:50.61#ibcon#ireg 17 cls_cnt 0 2006.146.00:33:50.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:33:50.61#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:33:50.61#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:33:50.62#ibcon#[28=FRQ=05,709.99\r\n] 2006.146.00:33:50.66#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:33:50.66#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:33:50.66#ibcon#about to clear, iclass 7 cls_cnt 0 2006.146.00:33:50.66#ibcon#cleared, iclass 7 cls_cnt 0 2006.146.00:33:50.67$vck44/vb=5,4 2006.146.00:33:50.67#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.146.00:33:50.67#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.146.00:33:50.67#ibcon#ireg 11 cls_cnt 2 2006.146.00:33:50.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.146.00:33:50.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.146.00:33:50.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.146.00:33:50.73#ibcon#[27=AT05-04\r\n] 2006.146.00:33:50.76#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.146.00:33:50.76#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.146.00:33:50.76#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.146.00:33:50.76#ibcon#ireg 7 cls_cnt 0 2006.146.00:33:50.76#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.146.00:33:50.88#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.146.00:33:50.88#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.146.00:33:50.90#ibcon#[27=USB\r\n] 2006.146.00:33:50.93#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.146.00:33:50.93#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.146.00:33:50.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.146.00:33:50.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.146.00:33:50.94$vck44/vblo=6,719.99 2006.146.00:33:50.94#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.146.00:33:50.94#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.146.00:33:50.94#ibcon#ireg 17 cls_cnt 0 2006.146.00:33:50.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.146.00:33:50.94#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.146.00:33:50.94#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.146.00:33:50.95#ibcon#[28=FRQ=06,719.99\r\n] 2006.146.00:33:50.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.146.00:33:50.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.146.00:33:50.99#ibcon#about to clear, iclass 13 cls_cnt 0 2006.146.00:33:50.99#ibcon#cleared, iclass 13 cls_cnt 0 2006.146.00:33:51.00$vck44/vb=6,4 2006.146.00:33:51.00#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.146.00:33:51.00#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.146.00:33:51.00#ibcon#ireg 11 cls_cnt 2 2006.146.00:33:51.00#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.146.00:33:51.04#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.146.00:33:51.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.146.00:33:51.06#ibcon#[27=AT06-04\r\n] 2006.146.00:33:51.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.146.00:33:51.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.146.00:33:51.09#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.146.00:33:51.09#ibcon#ireg 7 cls_cnt 0 2006.146.00:33:51.09#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.146.00:33:51.21#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.146.00:33:51.21#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.146.00:33:51.23#ibcon#[27=USB\r\n] 2006.146.00:33:51.26#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.146.00:33:51.26#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.146.00:33:51.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.146.00:33:51.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.146.00:33:51.27$vck44/vblo=7,734.99 2006.146.00:33:51.27#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.146.00:33:51.27#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.146.00:33:51.27#ibcon#ireg 17 cls_cnt 0 2006.146.00:33:51.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:33:51.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:33:51.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:33:51.28#ibcon#[28=FRQ=07,734.99\r\n] 2006.146.00:33:51.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:33:51.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:33:51.32#ibcon#about to clear, iclass 17 cls_cnt 0 2006.146.00:33:51.32#ibcon#cleared, iclass 17 cls_cnt 0 2006.146.00:33:51.33$vck44/vb=7,4 2006.146.00:33:51.33#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.146.00:33:51.33#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.146.00:33:51.33#ibcon#ireg 11 cls_cnt 2 2006.146.00:33:51.33#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:33:51.37#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:33:51.37#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:33:51.39#ibcon#[27=AT07-04\r\n] 2006.146.00:33:51.42#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:33:51.42#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:33:51.42#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.146.00:33:51.42#ibcon#ireg 7 cls_cnt 0 2006.146.00:33:51.42#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:33:51.54#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:33:51.54#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:33:51.56#ibcon#[27=USB\r\n] 2006.146.00:33:51.59#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:33:51.59#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:33:51.59#ibcon#about to clear, iclass 19 cls_cnt 0 2006.146.00:33:51.59#ibcon#cleared, iclass 19 cls_cnt 0 2006.146.00:33:51.60$vck44/vblo=8,744.99 2006.146.00:33:51.60#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.146.00:33:51.60#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.146.00:33:51.60#ibcon#ireg 17 cls_cnt 0 2006.146.00:33:51.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:33:51.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:33:51.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:33:51.61#ibcon#[28=FRQ=08,744.99\r\n] 2006.146.00:33:51.65#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:33:51.65#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:33:51.65#ibcon#about to clear, iclass 21 cls_cnt 0 2006.146.00:33:51.65#ibcon#cleared, iclass 21 cls_cnt 0 2006.146.00:33:51.66$vck44/vb=8,4 2006.146.00:33:51.66#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.146.00:33:51.66#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.146.00:33:51.66#ibcon#ireg 11 cls_cnt 2 2006.146.00:33:51.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:33:51.70#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:33:51.70#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:33:51.72#ibcon#[27=AT08-04\r\n] 2006.146.00:33:51.75#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:33:51.75#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:33:51.75#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.146.00:33:51.75#ibcon#ireg 7 cls_cnt 0 2006.146.00:33:51.75#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:33:51.87#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:33:51.87#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:33:51.89#ibcon#[27=USB\r\n] 2006.146.00:33:51.92#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:33:51.92#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:33:51.92#ibcon#about to clear, iclass 23 cls_cnt 0 2006.146.00:33:51.92#ibcon#cleared, iclass 23 cls_cnt 0 2006.146.00:33:51.93$vck44/vabw=wide 2006.146.00:33:51.93#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.146.00:33:51.93#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.146.00:33:51.93#ibcon#ireg 8 cls_cnt 0 2006.146.00:33:51.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:33:51.93#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:33:51.93#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:33:51.94#ibcon#[25=BW32\r\n] 2006.146.00:33:51.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:33:51.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:33:51.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.146.00:33:51.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.146.00:33:51.98$vck44/vbbw=wide 2006.146.00:33:51.98#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.146.00:33:51.98#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.146.00:33:51.98#ibcon#ireg 8 cls_cnt 0 2006.146.00:33:51.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.146.00:33:52.03#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.146.00:33:52.03#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.146.00:33:52.05#ibcon#[27=BW32\r\n] 2006.146.00:33:52.08#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.146.00:33:52.08#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.146.00:33:52.08#ibcon#about to clear, iclass 27 cls_cnt 0 2006.146.00:33:52.08#ibcon#cleared, iclass 27 cls_cnt 0 2006.146.00:33:52.09$setupk4/ifdk4 2006.146.00:33:52.09$ifdk4/lo= 2006.146.00:33:52.09$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.146.00:33:52.09$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.146.00:33:52.09$ifdk4/patch= 2006.146.00:33:52.09$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.146.00:33:52.09$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.146.00:33:52.09$setupk4/!*+20s 2006.146.00:33:55.54#abcon#<5=/08 1.9 5.3 20.46 701020.7\r\n> 2006.146.00:33:55.56#abcon#{5=INTERFACE CLEAR} 2006.146.00:33:55.62#abcon#[5=S1D000X0/0*\r\n] 2006.146.00:34:00.14#trakl#Source acquired 2006.146.00:34:02.14#flagr#flagr/antenna,acquired 2006.146.00:34:05.71#abcon#<5=/08 1.9 5.3 20.46 701020.7\r\n> 2006.146.00:34:05.73#abcon#{5=INTERFACE CLEAR} 2006.146.00:34:05.79#abcon#[5=S1D000X0/0*\r\n] 2006.146.00:34:06.74$setupk4/"tpicd 2006.146.00:34:06.74$setupk4/echo=off 2006.146.00:34:06.74$setupk4/xlog=off 2006.146.00:34:06.75:!2006.146.00:37:32 2006.146.00:37:32.01:preob 2006.146.00:37:33.14/onsource/TRACKING 2006.146.00:37:33.14:!2006.146.00:37:42 2006.146.00:37:42.00:"tape 2006.146.00:37:42.00:"st=record 2006.146.00:37:42.00:data_valid=on 2006.146.00:37:42.00:midob 2006.146.00:37:42.14/onsource/TRACKING 2006.146.00:37:42.15/wx/20.52,1020.7,67 2006.146.00:37:42.31/cable/+6.5453E-03 2006.146.00:37:43.40/va/01,08,usb,yes,30,32 2006.146.00:37:43.40/va/02,07,usb,yes,32,33 2006.146.00:37:43.40/va/03,08,usb,yes,29,30 2006.146.00:37:43.40/va/04,07,usb,yes,33,35 2006.146.00:37:43.40/va/05,04,usb,yes,29,29 2006.146.00:37:43.40/va/06,04,usb,yes,32,32 2006.146.00:37:43.40/va/07,04,usb,yes,33,34 2006.146.00:37:43.40/va/08,04,usb,yes,28,33 2006.146.00:37:43.63/valo/01,524.99,yes,locked 2006.146.00:37:43.63/valo/02,534.99,yes,locked 2006.146.00:37:43.63/valo/03,564.99,yes,locked 2006.146.00:37:43.63/valo/04,624.99,yes,locked 2006.146.00:37:43.63/valo/05,734.99,yes,locked 2006.146.00:37:43.63/valo/06,814.99,yes,locked 2006.146.00:37:43.63/valo/07,864.99,yes,locked 2006.146.00:37:43.63/valo/08,884.99,yes,locked 2006.146.00:37:44.72/vb/01,03,usb,yes,37,34 2006.146.00:37:44.72/vb/02,04,usb,yes,32,32 2006.146.00:37:44.72/vb/03,04,usb,yes,29,32 2006.146.00:37:44.72/vb/04,04,usb,yes,33,32 2006.146.00:37:44.72/vb/05,04,usb,yes,26,28 2006.146.00:37:44.72/vb/06,04,usb,yes,30,27 2006.146.00:37:44.72/vb/07,04,usb,yes,30,30 2006.146.00:37:44.72/vb/08,04,usb,yes,28,31 2006.146.00:37:44.95/vblo/01,629.99,yes,locked 2006.146.00:37:44.95/vblo/02,634.99,yes,locked 2006.146.00:37:44.95/vblo/03,649.99,yes,locked 2006.146.00:37:44.95/vblo/04,679.99,yes,locked 2006.146.00:37:44.95/vblo/05,709.99,yes,locked 2006.146.00:37:44.95/vblo/06,719.99,yes,locked 2006.146.00:37:44.95/vblo/07,734.99,yes,locked 2006.146.00:37:44.95/vblo/08,744.99,yes,locked 2006.146.00:37:45.10/vabw/8 2006.146.00:37:45.25/vbbw/8 2006.146.00:37:45.43/xfe/off,on,16.0 2006.146.00:37:45.82/ifatt/23,28,28,28 2006.146.00:37:46.07/fmout-gps/S +4.3E-08 2006.146.00:37:46.12:!2006.146.00:41:12 2006.146.00:41:12.01:data_valid=off 2006.146.00:41:12.02:"et 2006.146.00:41:12.02:!+3s 2006.146.00:41:15.05:"tape 2006.146.00:41:15.09:postob 2006.146.00:41:15.20/cable/+6.5439E-03 2006.146.00:41:15.21/wx/20.60,1020.7,68 2006.146.00:41:15.30/fmout-gps/S +4.5E-08 2006.146.00:41:15.31:scan_name=146-0043,jd0605,130 2006.146.00:41:15.31:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.146.00:41:16.13#flagr#flagr/antenna,new-source 2006.146.00:41:16.14:checkk5 2006.146.00:41:16.58/chk_autoobs//k5ts1/ autoobs is running! 2006.146.00:41:17.00/chk_autoobs//k5ts2/ autoobs is running! 2006.146.00:41:17.44/chk_autoobs//k5ts3/ autoobs is running! 2006.146.00:41:17.88/chk_autoobs//k5ts4/ autoobs is running! 2006.146.00:41:18.32/chk_obsdata//k5ts1/T1460037??a.dat file size is correct (nominal:840MB, actual:836MB). 2006.146.00:41:18.76/chk_obsdata//k5ts2/T1460037??b.dat file size is correct (nominal:840MB, actual:836MB). 2006.146.00:41:19.19/chk_obsdata//k5ts3/T1460037??c.dat file size is correct (nominal:840MB, actual:836MB). 2006.146.00:41:19.63/chk_obsdata//k5ts4/T1460037??d.dat file size is correct (nominal:840MB, actual:836MB). 2006.146.00:41:20.39/k5log//k5ts1_log_newline 2006.146.00:41:21.14/k5log//k5ts2_log_newline 2006.146.00:41:21.90/k5log//k5ts3_log_newline 2006.146.00:41:22.65/k5log//k5ts4_log_newline 2006.146.00:41:22.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.146.00:41:22.67:setupk4=1 2006.146.00:41:22.67$setupk4/echo=on 2006.146.00:41:22.67$setupk4/pcalon 2006.146.00:41:22.67$pcalon/"no phase cal control is implemented here 2006.146.00:41:22.68$setupk4/"tpicd=stop 2006.146.00:41:22.68$setupk4/"rec=synch_on 2006.146.00:41:22.68$setupk4/"rec_mode=128 2006.146.00:41:22.68$setupk4/!* 2006.146.00:41:22.68$setupk4/recpk4 2006.146.00:41:22.68$recpk4/recpatch= 2006.146.00:41:22.68$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.146.00:41:22.68$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.146.00:41:22.68$setupk4/vck44 2006.146.00:41:22.68$vck44/valo=1,524.99 2006.146.00:41:22.68#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.146.00:41:22.68#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.146.00:41:22.68#ibcon#ireg 17 cls_cnt 0 2006.146.00:41:22.68#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.146.00:41:22.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.146.00:41:22.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.146.00:41:22.72#ibcon#[26=FRQ=01,524.99\r\n] 2006.146.00:41:22.76#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.146.00:41:22.76#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.146.00:41:22.76#ibcon#about to clear, iclass 28 cls_cnt 0 2006.146.00:41:22.76#ibcon#cleared, iclass 28 cls_cnt 0 2006.146.00:41:22.76$vck44/va=1,8 2006.146.00:41:22.76#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.146.00:41:22.76#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.146.00:41:22.76#ibcon#ireg 11 cls_cnt 2 2006.146.00:41:22.76#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.146.00:41:22.76#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.146.00:41:22.76#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.146.00:41:22.78#ibcon#[25=AT01-08\r\n] 2006.146.00:41:22.81#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.146.00:41:22.81#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.146.00:41:22.81#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.146.00:41:22.81#ibcon#ireg 7 cls_cnt 0 2006.146.00:41:22.81#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.146.00:41:22.94#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.146.00:41:22.94#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.146.00:41:22.95#ibcon#[25=USB\r\n] 2006.146.00:41:22.98#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.146.00:41:22.98#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.146.00:41:22.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.146.00:41:22.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.146.00:41:22.98$vck44/valo=2,534.99 2006.146.00:41:22.98#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.146.00:41:22.98#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.146.00:41:22.98#ibcon#ireg 17 cls_cnt 0 2006.146.00:41:22.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.146.00:41:22.98#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.146.00:41:22.98#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.146.00:41:23.01#ibcon#[26=FRQ=02,534.99\r\n] 2006.146.00:41:23.05#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.146.00:41:23.05#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.146.00:41:23.05#ibcon#about to clear, iclass 32 cls_cnt 0 2006.146.00:41:23.05#ibcon#cleared, iclass 32 cls_cnt 0 2006.146.00:41:23.05$vck44/va=2,7 2006.146.00:41:23.05#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.146.00:41:23.05#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.146.00:41:23.05#ibcon#ireg 11 cls_cnt 2 2006.146.00:41:23.05#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.146.00:41:23.10#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.146.00:41:23.10#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.146.00:41:23.12#ibcon#[25=AT02-07\r\n] 2006.146.00:41:23.15#abcon#<5=/08 2.0 5.9 20.61 691020.7\r\n> 2006.146.00:41:23.15#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.146.00:41:23.15#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.146.00:41:23.15#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.146.00:41:23.15#ibcon#ireg 7 cls_cnt 0 2006.146.00:41:23.15#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.146.00:41:23.17#abcon#{5=INTERFACE CLEAR} 2006.146.00:41:23.23#abcon#[5=S1D000X0/0*\r\n] 2006.146.00:41:23.27#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.146.00:41:23.27#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.146.00:41:23.29#ibcon#[25=USB\r\n] 2006.146.00:41:23.32#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.146.00:41:23.32#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.146.00:41:23.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.146.00:41:23.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.146.00:41:23.32$vck44/valo=3,564.99 2006.146.00:41:23.32#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.146.00:41:23.32#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.146.00:41:23.32#ibcon#ireg 17 cls_cnt 0 2006.146.00:41:23.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.146.00:41:23.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.146.00:41:23.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.146.00:41:23.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.146.00:41:23.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.146.00:41:23.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.146.00:41:23.38#ibcon#about to clear, iclass 40 cls_cnt 0 2006.146.00:41:23.38#ibcon#cleared, iclass 40 cls_cnt 0 2006.146.00:41:23.38$vck44/va=3,8 2006.146.00:41:23.38#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.146.00:41:23.38#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.146.00:41:23.38#ibcon#ireg 11 cls_cnt 2 2006.146.00:41:23.38#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.146.00:41:23.44#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.146.00:41:23.44#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.146.00:41:23.46#ibcon#[25=AT03-08\r\n] 2006.146.00:41:23.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.146.00:41:23.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.146.00:41:23.49#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.146.00:41:23.49#ibcon#ireg 7 cls_cnt 0 2006.146.00:41:23.49#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.146.00:41:23.61#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.146.00:41:23.61#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.146.00:41:23.63#ibcon#[25=USB\r\n] 2006.146.00:41:23.66#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.146.00:41:23.66#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.146.00:41:23.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.146.00:41:23.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.146.00:41:23.66$vck44/valo=4,624.99 2006.146.00:41:23.66#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.146.00:41:23.66#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.146.00:41:23.66#ibcon#ireg 17 cls_cnt 0 2006.146.00:41:23.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.146.00:41:23.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.146.00:41:23.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.146.00:41:23.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.146.00:41:23.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.146.00:41:23.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.146.00:41:23.72#ibcon#about to clear, iclass 6 cls_cnt 0 2006.146.00:41:23.72#ibcon#cleared, iclass 6 cls_cnt 0 2006.146.00:41:23.72$vck44/va=4,7 2006.146.00:41:23.72#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.146.00:41:23.72#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.146.00:41:23.72#ibcon#ireg 11 cls_cnt 2 2006.146.00:41:23.72#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.146.00:41:23.78#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.146.00:41:23.78#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.146.00:41:23.80#ibcon#[25=AT04-07\r\n] 2006.146.00:41:23.83#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.146.00:41:23.83#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.146.00:41:23.83#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.146.00:41:23.83#ibcon#ireg 7 cls_cnt 0 2006.146.00:41:23.83#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.146.00:41:23.95#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.146.00:41:23.95#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.146.00:41:23.97#ibcon#[25=USB\r\n] 2006.146.00:41:24.00#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.146.00:41:24.00#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.146.00:41:24.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.146.00:41:24.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.146.00:41:24.00$vck44/valo=5,734.99 2006.146.00:41:24.00#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.146.00:41:24.00#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.146.00:41:24.00#ibcon#ireg 17 cls_cnt 0 2006.146.00:41:24.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.146.00:41:24.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.146.00:41:24.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.146.00:41:24.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.146.00:41:24.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.146.00:41:24.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.146.00:41:24.06#ibcon#about to clear, iclass 12 cls_cnt 0 2006.146.00:41:24.06#ibcon#cleared, iclass 12 cls_cnt 0 2006.146.00:41:24.06$vck44/va=5,4 2006.146.00:41:24.06#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.146.00:41:24.06#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.146.00:41:24.06#ibcon#ireg 11 cls_cnt 2 2006.146.00:41:24.06#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.146.00:41:24.13#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.146.00:41:24.13#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.146.00:41:24.15#ibcon#[25=AT05-04\r\n] 2006.146.00:41:24.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.146.00:41:24.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.146.00:41:24.17#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.146.00:41:24.17#ibcon#ireg 7 cls_cnt 0 2006.146.00:41:24.17#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.146.00:41:24.29#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.146.00:41:24.29#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.146.00:41:24.31#ibcon#[25=USB\r\n] 2006.146.00:41:24.34#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.146.00:41:24.34#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.146.00:41:24.34#ibcon#about to clear, iclass 14 cls_cnt 0 2006.146.00:41:24.34#ibcon#cleared, iclass 14 cls_cnt 0 2006.146.00:41:24.34$vck44/valo=6,814.99 2006.146.00:41:24.34#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.146.00:41:24.34#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.146.00:41:24.34#ibcon#ireg 17 cls_cnt 0 2006.146.00:41:24.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.146.00:41:24.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.146.00:41:24.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.146.00:41:24.36#ibcon#[26=FRQ=06,814.99\r\n] 2006.146.00:41:24.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.146.00:41:24.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.146.00:41:24.40#ibcon#about to clear, iclass 16 cls_cnt 0 2006.146.00:41:24.40#ibcon#cleared, iclass 16 cls_cnt 0 2006.146.00:41:24.40$vck44/va=6,4 2006.146.00:41:24.40#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.146.00:41:24.40#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.146.00:41:24.40#ibcon#ireg 11 cls_cnt 2 2006.146.00:41:24.40#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.146.00:41:24.46#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.146.00:41:24.46#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.146.00:41:24.48#ibcon#[25=AT06-04\r\n] 2006.146.00:41:24.51#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.146.00:41:24.51#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.146.00:41:24.51#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.146.00:41:24.51#ibcon#ireg 7 cls_cnt 0 2006.146.00:41:24.51#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.146.00:41:24.63#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.146.00:41:24.63#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.146.00:41:24.65#ibcon#[25=USB\r\n] 2006.146.00:41:24.68#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.146.00:41:24.68#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.146.00:41:24.68#ibcon#about to clear, iclass 18 cls_cnt 0 2006.146.00:41:24.68#ibcon#cleared, iclass 18 cls_cnt 0 2006.146.00:41:24.68$vck44/valo=7,864.99 2006.146.00:41:24.68#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.146.00:41:24.68#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.146.00:41:24.68#ibcon#ireg 17 cls_cnt 0 2006.146.00:41:24.68#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.146.00:41:24.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.146.00:41:24.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.146.00:41:24.70#ibcon#[26=FRQ=07,864.99\r\n] 2006.146.00:41:24.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.146.00:41:24.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.146.00:41:24.74#ibcon#about to clear, iclass 20 cls_cnt 0 2006.146.00:41:24.74#ibcon#cleared, iclass 20 cls_cnt 0 2006.146.00:41:24.74$vck44/va=7,4 2006.146.00:41:24.74#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.146.00:41:24.74#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.146.00:41:24.74#ibcon#ireg 11 cls_cnt 2 2006.146.00:41:24.74#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.146.00:41:24.80#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.146.00:41:24.80#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.146.00:41:24.82#ibcon#[25=AT07-04\r\n] 2006.146.00:41:24.85#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.146.00:41:24.85#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.146.00:41:24.85#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.146.00:41:24.85#ibcon#ireg 7 cls_cnt 0 2006.146.00:41:24.85#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.146.00:41:24.97#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.146.00:41:24.97#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.146.00:41:24.99#ibcon#[25=USB\r\n] 2006.146.00:41:25.02#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.146.00:41:25.02#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.146.00:41:25.02#ibcon#about to clear, iclass 22 cls_cnt 0 2006.146.00:41:25.02#ibcon#cleared, iclass 22 cls_cnt 0 2006.146.00:41:25.02$vck44/valo=8,884.99 2006.146.00:41:25.02#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.146.00:41:25.02#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.146.00:41:25.02#ibcon#ireg 17 cls_cnt 0 2006.146.00:41:25.02#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.146.00:41:25.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.146.00:41:25.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.146.00:41:25.04#ibcon#[26=FRQ=08,884.99\r\n] 2006.146.00:41:25.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.146.00:41:25.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.146.00:41:25.08#ibcon#about to clear, iclass 24 cls_cnt 0 2006.146.00:41:25.08#ibcon#cleared, iclass 24 cls_cnt 0 2006.146.00:41:25.08$vck44/va=8,4 2006.146.00:41:25.08#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.146.00:41:25.08#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.146.00:41:25.08#ibcon#ireg 11 cls_cnt 2 2006.146.00:41:25.08#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.146.00:41:25.14#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.146.00:41:25.14#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.146.00:41:25.16#ibcon#[25=AT08-04\r\n] 2006.146.00:41:25.19#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.146.00:41:25.19#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.146.00:41:25.19#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.146.00:41:25.19#ibcon#ireg 7 cls_cnt 0 2006.146.00:41:25.19#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.146.00:41:25.31#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.146.00:41:25.31#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.146.00:41:25.33#ibcon#[25=USB\r\n] 2006.146.00:41:25.36#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.146.00:41:25.36#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.146.00:41:25.36#ibcon#about to clear, iclass 26 cls_cnt 0 2006.146.00:41:25.36#ibcon#cleared, iclass 26 cls_cnt 0 2006.146.00:41:25.36$vck44/vblo=1,629.99 2006.146.00:41:25.36#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.146.00:41:25.36#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.146.00:41:25.36#ibcon#ireg 17 cls_cnt 0 2006.146.00:41:25.36#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.146.00:41:25.36#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.146.00:41:25.36#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.146.00:41:25.38#ibcon#[28=FRQ=01,629.99\r\n] 2006.146.00:41:25.42#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.146.00:41:25.42#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.146.00:41:25.42#ibcon#about to clear, iclass 28 cls_cnt 0 2006.146.00:41:25.42#ibcon#cleared, iclass 28 cls_cnt 0 2006.146.00:41:25.42$vck44/vb=1,3 2006.146.00:41:25.42#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.146.00:41:25.42#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.146.00:41:25.42#ibcon#ireg 11 cls_cnt 2 2006.146.00:41:25.42#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.146.00:41:25.42#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.146.00:41:25.42#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.146.00:41:25.44#ibcon#[27=AT01-03\r\n] 2006.146.00:41:25.47#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.146.00:41:25.47#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.146.00:41:25.47#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.146.00:41:25.47#ibcon#ireg 7 cls_cnt 0 2006.146.00:41:25.47#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.146.00:41:25.59#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.146.00:41:25.59#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.146.00:41:25.61#ibcon#[27=USB\r\n] 2006.146.00:41:25.64#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.146.00:41:25.64#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.146.00:41:25.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.146.00:41:25.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.146.00:41:25.64$vck44/vblo=2,634.99 2006.146.00:41:25.64#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.146.00:41:25.64#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.146.00:41:25.64#ibcon#ireg 17 cls_cnt 0 2006.146.00:41:25.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.146.00:41:25.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.146.00:41:25.64#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.146.00:41:25.66#ibcon#[28=FRQ=02,634.99\r\n] 2006.146.00:41:25.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.146.00:41:25.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.146.00:41:25.70#ibcon#about to clear, iclass 32 cls_cnt 0 2006.146.00:41:25.70#ibcon#cleared, iclass 32 cls_cnt 0 2006.146.00:41:25.70$vck44/vb=2,4 2006.146.00:41:25.70#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.146.00:41:25.70#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.146.00:41:25.70#ibcon#ireg 11 cls_cnt 2 2006.146.00:41:25.70#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.146.00:41:25.76#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.146.00:41:25.76#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.146.00:41:25.78#ibcon#[27=AT02-04\r\n] 2006.146.00:41:25.81#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.146.00:41:25.81#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.146.00:41:25.81#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.146.00:41:25.81#ibcon#ireg 7 cls_cnt 0 2006.146.00:41:25.81#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.146.00:41:25.93#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.146.00:41:25.93#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.146.00:41:25.95#ibcon#[27=USB\r\n] 2006.146.00:41:25.98#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.146.00:41:25.98#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.146.00:41:25.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.146.00:41:25.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.146.00:41:25.98$vck44/vblo=3,649.99 2006.146.00:41:25.98#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.146.00:41:25.98#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.146.00:41:25.98#ibcon#ireg 17 cls_cnt 0 2006.146.00:41:25.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.146.00:41:25.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.146.00:41:25.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.146.00:41:26.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.146.00:41:26.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.146.00:41:26.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.146.00:41:26.04#ibcon#about to clear, iclass 36 cls_cnt 0 2006.146.00:41:26.04#ibcon#cleared, iclass 36 cls_cnt 0 2006.146.00:41:26.04$vck44/vb=3,4 2006.146.00:41:26.04#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.146.00:41:26.04#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.146.00:41:26.04#ibcon#ireg 11 cls_cnt 2 2006.146.00:41:26.04#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.146.00:41:26.10#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.146.00:41:26.10#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.146.00:41:26.12#ibcon#[27=AT03-04\r\n] 2006.146.00:41:26.15#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.146.00:41:26.15#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.146.00:41:26.15#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.146.00:41:26.15#ibcon#ireg 7 cls_cnt 0 2006.146.00:41:26.15#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.146.00:41:26.27#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.146.00:41:26.27#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.146.00:41:26.29#ibcon#[27=USB\r\n] 2006.146.00:41:26.32#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.146.00:41:26.32#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.146.00:41:26.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.146.00:41:26.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.146.00:41:26.32$vck44/vblo=4,679.99 2006.146.00:41:26.32#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.146.00:41:26.32#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.146.00:41:26.32#ibcon#ireg 17 cls_cnt 0 2006.146.00:41:26.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.146.00:41:26.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.146.00:41:26.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.146.00:41:26.34#ibcon#[28=FRQ=04,679.99\r\n] 2006.146.00:41:26.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.146.00:41:26.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.146.00:41:26.38#ibcon#about to clear, iclass 40 cls_cnt 0 2006.146.00:41:26.38#ibcon#cleared, iclass 40 cls_cnt 0 2006.146.00:41:26.38$vck44/vb=4,4 2006.146.00:41:26.38#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.146.00:41:26.38#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.146.00:41:26.38#ibcon#ireg 11 cls_cnt 2 2006.146.00:41:26.38#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.146.00:41:26.44#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.146.00:41:26.44#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.146.00:41:26.46#ibcon#[27=AT04-04\r\n] 2006.146.00:41:26.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.146.00:41:26.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.146.00:41:26.49#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.146.00:41:26.49#ibcon#ireg 7 cls_cnt 0 2006.146.00:41:26.49#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.146.00:41:26.61#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.146.00:41:26.61#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.146.00:41:26.63#ibcon#[27=USB\r\n] 2006.146.00:41:26.66#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.146.00:41:26.66#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.146.00:41:26.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.146.00:41:26.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.146.00:41:26.66$vck44/vblo=5,709.99 2006.146.00:41:26.66#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.146.00:41:26.66#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.146.00:41:26.66#ibcon#ireg 17 cls_cnt 0 2006.146.00:41:26.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.146.00:41:26.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.146.00:41:26.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.146.00:41:26.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.146.00:41:26.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.146.00:41:26.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.146.00:41:26.72#ibcon#about to clear, iclass 6 cls_cnt 0 2006.146.00:41:26.72#ibcon#cleared, iclass 6 cls_cnt 0 2006.146.00:41:26.72$vck44/vb=5,4 2006.146.00:41:26.72#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.146.00:41:26.72#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.146.00:41:26.72#ibcon#ireg 11 cls_cnt 2 2006.146.00:41:26.72#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.146.00:41:26.78#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.146.00:41:26.78#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.146.00:41:26.80#ibcon#[27=AT05-04\r\n] 2006.146.00:41:26.83#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.146.00:41:26.83#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.146.00:41:26.83#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.146.00:41:26.83#ibcon#ireg 7 cls_cnt 0 2006.146.00:41:26.83#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.146.00:41:26.95#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.146.00:41:26.95#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.146.00:41:26.97#ibcon#[27=USB\r\n] 2006.146.00:41:27.00#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.146.00:41:27.00#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.146.00:41:27.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.146.00:41:27.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.146.00:41:27.00$vck44/vblo=6,719.99 2006.146.00:41:27.00#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.146.00:41:27.00#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.146.00:41:27.00#ibcon#ireg 17 cls_cnt 0 2006.146.00:41:27.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.146.00:41:27.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.146.00:41:27.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.146.00:41:27.02#ibcon#[28=FRQ=06,719.99\r\n] 2006.146.00:41:27.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.146.00:41:27.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.146.00:41:27.06#ibcon#about to clear, iclass 12 cls_cnt 0 2006.146.00:41:27.06#ibcon#cleared, iclass 12 cls_cnt 0 2006.146.00:41:27.06$vck44/vb=6,4 2006.146.00:41:27.06#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.146.00:41:27.06#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.146.00:41:27.06#ibcon#ireg 11 cls_cnt 2 2006.146.00:41:27.06#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.146.00:41:27.12#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.146.00:41:27.12#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.146.00:41:27.14#ibcon#[27=AT06-04\r\n] 2006.146.00:41:27.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.146.00:41:27.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.146.00:41:27.17#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.146.00:41:27.17#ibcon#ireg 7 cls_cnt 0 2006.146.00:41:27.17#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.146.00:41:27.29#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.146.00:41:27.29#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.146.00:41:27.31#ibcon#[27=USB\r\n] 2006.146.00:41:27.34#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.146.00:41:27.34#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.146.00:41:27.34#ibcon#about to clear, iclass 14 cls_cnt 0 2006.146.00:41:27.34#ibcon#cleared, iclass 14 cls_cnt 0 2006.146.00:41:27.34$vck44/vblo=7,734.99 2006.146.00:41:27.34#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.146.00:41:27.34#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.146.00:41:27.34#ibcon#ireg 17 cls_cnt 0 2006.146.00:41:27.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.146.00:41:27.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.146.00:41:27.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.146.00:41:27.36#ibcon#[28=FRQ=07,734.99\r\n] 2006.146.00:41:27.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.146.00:41:27.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.146.00:41:27.40#ibcon#about to clear, iclass 16 cls_cnt 0 2006.146.00:41:27.40#ibcon#cleared, iclass 16 cls_cnt 0 2006.146.00:41:27.40$vck44/vb=7,4 2006.146.00:41:27.40#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.146.00:41:27.40#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.146.00:41:27.40#ibcon#ireg 11 cls_cnt 2 2006.146.00:41:27.40#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.146.00:41:27.46#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.146.00:41:27.46#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.146.00:41:27.48#ibcon#[27=AT07-04\r\n] 2006.146.00:41:27.51#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.146.00:41:27.51#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.146.00:41:27.51#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.146.00:41:27.51#ibcon#ireg 7 cls_cnt 0 2006.146.00:41:27.51#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.146.00:41:27.63#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.146.00:41:27.63#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.146.00:41:27.65#ibcon#[27=USB\r\n] 2006.146.00:41:27.68#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.146.00:41:27.68#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.146.00:41:27.68#ibcon#about to clear, iclass 18 cls_cnt 0 2006.146.00:41:27.68#ibcon#cleared, iclass 18 cls_cnt 0 2006.146.00:41:27.68$vck44/vblo=8,744.99 2006.146.00:41:27.68#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.146.00:41:27.68#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.146.00:41:27.68#ibcon#ireg 17 cls_cnt 0 2006.146.00:41:27.68#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.146.00:41:27.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.146.00:41:27.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.146.00:41:27.70#ibcon#[28=FRQ=08,744.99\r\n] 2006.146.00:41:27.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.146.00:41:27.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.146.00:41:27.74#ibcon#about to clear, iclass 20 cls_cnt 0 2006.146.00:41:27.74#ibcon#cleared, iclass 20 cls_cnt 0 2006.146.00:41:27.74$vck44/vb=8,4 2006.146.00:41:27.74#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.146.00:41:27.74#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.146.00:41:27.74#ibcon#ireg 11 cls_cnt 2 2006.146.00:41:27.74#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.146.00:41:27.80#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.146.00:41:27.80#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.146.00:41:27.82#ibcon#[27=AT08-04\r\n] 2006.146.00:41:27.85#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.146.00:41:27.85#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.146.00:41:27.85#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.146.00:41:27.85#ibcon#ireg 7 cls_cnt 0 2006.146.00:41:27.85#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.146.00:41:27.97#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.146.00:41:27.97#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.146.00:41:27.99#ibcon#[27=USB\r\n] 2006.146.00:41:28.02#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.146.00:41:28.02#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.146.00:41:28.02#ibcon#about to clear, iclass 22 cls_cnt 0 2006.146.00:41:28.02#ibcon#cleared, iclass 22 cls_cnt 0 2006.146.00:41:28.02$vck44/vabw=wide 2006.146.00:41:28.02#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.146.00:41:28.02#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.146.00:41:28.02#ibcon#ireg 8 cls_cnt 0 2006.146.00:41:28.02#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.146.00:41:28.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.146.00:41:28.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.146.00:41:28.04#ibcon#[25=BW32\r\n] 2006.146.00:41:28.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.146.00:41:28.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.146.00:41:28.07#ibcon#about to clear, iclass 24 cls_cnt 0 2006.146.00:41:28.07#ibcon#cleared, iclass 24 cls_cnt 0 2006.146.00:41:28.07$vck44/vbbw=wide 2006.146.00:41:28.07#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.146.00:41:28.07#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.146.00:41:28.07#ibcon#ireg 8 cls_cnt 0 2006.146.00:41:28.07#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.146.00:41:28.14#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.146.00:41:28.14#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.146.00:41:28.16#ibcon#[27=BW32\r\n] 2006.146.00:41:28.19#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.146.00:41:28.19#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.146.00:41:28.19#ibcon#about to clear, iclass 26 cls_cnt 0 2006.146.00:41:28.19#ibcon#cleared, iclass 26 cls_cnt 0 2006.146.00:41:28.19$setupk4/ifdk4 2006.146.00:41:28.19$ifdk4/lo= 2006.146.00:41:28.19$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.146.00:41:28.19$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.146.00:41:28.19$ifdk4/patch= 2006.146.00:41:28.19$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.146.00:41:28.19$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.146.00:41:28.19$setupk4/!*+20s 2006.146.00:41:33.32#abcon#<5=/08 2.1 5.9 20.61 691020.7\r\n> 2006.146.00:41:33.34#abcon#{5=INTERFACE CLEAR} 2006.146.00:41:33.42#abcon#[5=S1D000X0/0*\r\n] 2006.146.00:41:38.14#trakl#Source acquired 2006.146.00:41:38.14#flagr#flagr/antenna,acquired 2006.146.00:41:42.69$setupk4/"tpicd 2006.146.00:41:42.69$setupk4/echo=off 2006.146.00:41:42.69$setupk4/xlog=off 2006.146.00:41:42.69:!2006.146.00:43:38 2006.146.00:43:38.00:preob 2006.146.00:43:39.13/onsource/TRACKING 2006.146.00:43:39.13:!2006.146.00:43:48 2006.146.00:43:48.00:"tape 2006.146.00:43:48.00:"st=record 2006.146.00:43:48.00:data_valid=on 2006.146.00:43:48.00:midob 2006.146.00:43:48.13/onsource/TRACKING 2006.146.00:43:48.13/wx/20.68,1020.7,69 2006.146.00:43:48.33/cable/+6.5439E-03 2006.146.00:43:49.42/va/01,08,usb,yes,29,31 2006.146.00:43:49.42/va/02,07,usb,yes,31,31 2006.146.00:43:49.42/va/03,08,usb,yes,28,29 2006.146.00:43:49.42/va/04,07,usb,yes,31,33 2006.146.00:43:49.42/va/05,04,usb,yes,27,28 2006.146.00:43:49.42/va/06,04,usb,yes,31,31 2006.146.00:43:49.42/va/07,04,usb,yes,31,32 2006.146.00:43:49.42/va/08,04,usb,yes,26,32 2006.146.00:43:49.65/valo/01,524.99,yes,locked 2006.146.00:43:49.65/valo/02,534.99,yes,locked 2006.146.00:43:49.65/valo/03,564.99,yes,locked 2006.146.00:43:49.65/valo/04,624.99,yes,locked 2006.146.00:43:49.65/valo/05,734.99,yes,locked 2006.146.00:43:49.65/valo/06,814.99,yes,locked 2006.146.00:43:49.65/valo/07,864.99,yes,locked 2006.146.00:43:49.65/valo/08,884.99,yes,locked 2006.146.00:43:50.74/vb/01,03,usb,yes,36,34 2006.146.00:43:50.74/vb/02,04,usb,yes,32,31 2006.146.00:43:50.74/vb/03,04,usb,yes,28,31 2006.146.00:43:50.74/vb/04,04,usb,yes,33,32 2006.146.00:43:50.74/vb/05,04,usb,yes,25,28 2006.146.00:43:50.74/vb/06,04,usb,yes,30,26 2006.146.00:43:50.74/vb/07,04,usb,yes,30,29 2006.146.00:43:50.74/vb/08,04,usb,yes,27,30 2006.146.00:43:50.97/vblo/01,629.99,yes,locked 2006.146.00:43:50.97/vblo/02,634.99,yes,locked 2006.146.00:43:50.97/vblo/03,649.99,yes,locked 2006.146.00:43:50.97/vblo/04,679.99,yes,locked 2006.146.00:43:50.97/vblo/05,709.99,yes,locked 2006.146.00:43:50.97/vblo/06,719.99,yes,locked 2006.146.00:43:50.97/vblo/07,734.99,yes,locked 2006.146.00:43:50.97/vblo/08,744.99,yes,locked 2006.146.00:43:51.12/vabw/8 2006.146.00:43:51.27/vbbw/8 2006.146.00:43:51.36/xfe/off,on,15.2 2006.146.00:43:51.74/ifatt/23,28,28,28 2006.146.00:43:52.07/fmout-gps/S +4.5E-08 2006.146.00:43:52.15:!2006.146.00:45:58 2006.146.00:45:58.01:data_valid=off 2006.146.00:45:58.02:"et 2006.146.00:45:58.02:!+3s 2006.146.00:46:01.03:"tape 2006.146.00:46:01.04:postob 2006.146.00:46:01.17/cable/+6.5462E-03 2006.146.00:46:01.18/wx/20.72,1020.6,70 2006.146.00:46:01.23/fmout-gps/S +4.5E-08 2006.146.00:46:01.23:scan_name=146-0052,jd0605,50 2006.146.00:46:01.23:source=0552+398,055530.81,394849.2,2000.0,cw 2006.146.00:46:03.14#flagr#flagr/antenna,new-source 2006.146.00:46:03.15:checkk5 2006.146.00:46:03.59/chk_autoobs//k5ts1/ autoobs is running! 2006.146.00:46:04.02/chk_autoobs//k5ts2/ autoobs is running! 2006.146.00:46:04.45/chk_autoobs//k5ts3/ autoobs is running! 2006.146.00:46:04.89/chk_autoobs//k5ts4/ autoobs is running! 2006.146.00:46:05.32/chk_obsdata//k5ts1/T1460043??a.dat file size is correct (nominal:520MB, actual:516MB). 2006.146.00:46:05.76/chk_obsdata//k5ts2/T1460043??b.dat file size is correct (nominal:520MB, actual:516MB). 2006.146.00:46:06.19/chk_obsdata//k5ts3/T1460043??c.dat file size is correct (nominal:520MB, actual:516MB). 2006.146.00:46:06.63/chk_obsdata//k5ts4/T1460043??d.dat file size is correct (nominal:520MB, actual:516MB). 2006.146.00:46:07.40/k5log//k5ts1_log_newline 2006.146.00:46:08.15/k5log//k5ts2_log_newline 2006.146.00:46:08.90/k5log//k5ts3_log_newline 2006.146.00:46:09.64/k5log//k5ts4_log_newline 2006.146.00:46:09.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.146.00:46:09.67:setupk4=1 2006.146.00:46:09.67$setupk4/echo=on 2006.146.00:46:09.67$setupk4/pcalon 2006.146.00:46:09.67$pcalon/"no phase cal control is implemented here 2006.146.00:46:09.67$setupk4/"tpicd=stop 2006.146.00:46:09.67$setupk4/"rec=synch_on 2006.146.00:46:09.67$setupk4/"rec_mode=128 2006.146.00:46:09.67$setupk4/!* 2006.146.00:46:09.67$setupk4/recpk4 2006.146.00:46:09.67$recpk4/recpatch= 2006.146.00:46:09.67$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.146.00:46:09.67$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.146.00:46:09.67$setupk4/vck44 2006.146.00:46:09.67$vck44/valo=1,524.99 2006.146.00:46:09.67#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.146.00:46:09.67#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.146.00:46:09.67#ibcon#ireg 17 cls_cnt 0 2006.146.00:46:09.67#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.146.00:46:09.67#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.146.00:46:09.67#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.146.00:46:09.71#ibcon#[26=FRQ=01,524.99\r\n] 2006.146.00:46:09.76#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.146.00:46:09.76#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.146.00:46:09.76#ibcon#about to clear, iclass 35 cls_cnt 0 2006.146.00:46:09.76#ibcon#cleared, iclass 35 cls_cnt 0 2006.146.00:46:09.76$vck44/va=1,8 2006.146.00:46:09.76#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.146.00:46:09.76#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.146.00:46:09.76#ibcon#ireg 11 cls_cnt 2 2006.146.00:46:09.76#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.146.00:46:09.76#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.146.00:46:09.76#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.146.00:46:09.78#ibcon#[25=AT01-08\r\n] 2006.146.00:46:09.81#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.146.00:46:09.81#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.146.00:46:09.81#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.146.00:46:09.81#ibcon#ireg 7 cls_cnt 0 2006.146.00:46:09.81#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.146.00:46:09.95#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.146.00:46:09.95#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.146.00:46:09.96#ibcon#[25=USB\r\n] 2006.146.00:46:09.99#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.146.00:46:09.99#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.146.00:46:09.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.146.00:46:09.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.146.00:46:09.99$vck44/valo=2,534.99 2006.146.00:46:09.99#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.146.00:46:09.99#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.146.00:46:09.99#ibcon#ireg 17 cls_cnt 0 2006.146.00:46:09.99#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.146.00:46:09.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.146.00:46:09.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.146.00:46:10.03#ibcon#[26=FRQ=02,534.99\r\n] 2006.146.00:46:10.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.146.00:46:10.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.146.00:46:10.07#ibcon#about to clear, iclass 39 cls_cnt 0 2006.146.00:46:10.07#ibcon#cleared, iclass 39 cls_cnt 0 2006.146.00:46:10.07$vck44/va=2,7 2006.146.00:46:10.07#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.146.00:46:10.07#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.146.00:46:10.07#ibcon#ireg 11 cls_cnt 2 2006.146.00:46:10.07#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.146.00:46:10.11#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.146.00:46:10.11#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.146.00:46:10.13#ibcon#[25=AT02-07\r\n] 2006.146.00:46:10.16#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.146.00:46:10.16#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.146.00:46:10.16#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.146.00:46:10.16#ibcon#ireg 7 cls_cnt 0 2006.146.00:46:10.16#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.146.00:46:10.28#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.146.00:46:10.28#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.146.00:46:10.30#ibcon#[25=USB\r\n] 2006.146.00:46:10.33#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.146.00:46:10.33#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.146.00:46:10.33#ibcon#about to clear, iclass 3 cls_cnt 0 2006.146.00:46:10.33#ibcon#cleared, iclass 3 cls_cnt 0 2006.146.00:46:10.33$vck44/valo=3,564.99 2006.146.00:46:10.33#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.146.00:46:10.33#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.146.00:46:10.33#ibcon#ireg 17 cls_cnt 0 2006.146.00:46:10.33#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.146.00:46:10.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.146.00:46:10.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.146.00:46:10.35#ibcon#[26=FRQ=03,564.99\r\n] 2006.146.00:46:10.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.146.00:46:10.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.146.00:46:10.39#ibcon#about to clear, iclass 5 cls_cnt 0 2006.146.00:46:10.39#ibcon#cleared, iclass 5 cls_cnt 0 2006.146.00:46:10.39$vck44/va=3,8 2006.146.00:46:10.39#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.146.00:46:10.39#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.146.00:46:10.39#ibcon#ireg 11 cls_cnt 2 2006.146.00:46:10.39#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.146.00:46:10.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.146.00:46:10.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.146.00:46:10.47#ibcon#[25=AT03-08\r\n] 2006.146.00:46:10.50#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.146.00:46:10.50#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.146.00:46:10.50#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.146.00:46:10.50#ibcon#ireg 7 cls_cnt 0 2006.146.00:46:10.50#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.146.00:46:10.62#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.146.00:46:10.62#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.146.00:46:10.64#ibcon#[25=USB\r\n] 2006.146.00:46:10.67#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.146.00:46:10.67#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.146.00:46:10.67#ibcon#about to clear, iclass 7 cls_cnt 0 2006.146.00:46:10.67#ibcon#cleared, iclass 7 cls_cnt 0 2006.146.00:46:10.67$vck44/valo=4,624.99 2006.146.00:46:10.67#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.146.00:46:10.67#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.146.00:46:10.67#ibcon#ireg 17 cls_cnt 0 2006.146.00:46:10.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.146.00:46:10.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.146.00:46:10.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.146.00:46:10.69#ibcon#[26=FRQ=04,624.99\r\n] 2006.146.00:46:10.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.146.00:46:10.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.146.00:46:10.73#ibcon#about to clear, iclass 11 cls_cnt 0 2006.146.00:46:10.73#ibcon#cleared, iclass 11 cls_cnt 0 2006.146.00:46:10.73$vck44/va=4,7 2006.146.00:46:10.73#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.146.00:46:10.73#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.146.00:46:10.73#ibcon#ireg 11 cls_cnt 2 2006.146.00:46:10.73#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.146.00:46:10.79#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.146.00:46:10.79#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.146.00:46:10.81#ibcon#[25=AT04-07\r\n] 2006.146.00:46:10.84#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.146.00:46:10.84#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.146.00:46:10.84#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.146.00:46:10.84#ibcon#ireg 7 cls_cnt 0 2006.146.00:46:10.84#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.146.00:46:10.96#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.146.00:46:10.96#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.146.00:46:10.98#ibcon#[25=USB\r\n] 2006.146.00:46:11.01#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.146.00:46:11.01#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.146.00:46:11.01#ibcon#about to clear, iclass 13 cls_cnt 0 2006.146.00:46:11.01#ibcon#cleared, iclass 13 cls_cnt 0 2006.146.00:46:11.01$vck44/valo=5,734.99 2006.146.00:46:11.01#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.146.00:46:11.01#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.146.00:46:11.01#ibcon#ireg 17 cls_cnt 0 2006.146.00:46:11.01#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.146.00:46:11.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.146.00:46:11.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.146.00:46:11.03#ibcon#[26=FRQ=05,734.99\r\n] 2006.146.00:46:11.07#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.146.00:46:11.07#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.146.00:46:11.07#ibcon#about to clear, iclass 15 cls_cnt 0 2006.146.00:46:11.07#ibcon#cleared, iclass 15 cls_cnt 0 2006.146.00:46:11.07$vck44/va=5,4 2006.146.00:46:11.07#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.146.00:46:11.07#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.146.00:46:11.07#ibcon#ireg 11 cls_cnt 2 2006.146.00:46:11.07#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.146.00:46:11.13#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.146.00:46:11.13#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.146.00:46:11.15#ibcon#[25=AT05-04\r\n] 2006.146.00:46:11.18#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.146.00:46:11.18#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.146.00:46:11.18#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.146.00:46:11.18#ibcon#ireg 7 cls_cnt 0 2006.146.00:46:11.18#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.146.00:46:11.30#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.146.00:46:11.30#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.146.00:46:11.32#ibcon#[25=USB\r\n] 2006.146.00:46:11.35#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.146.00:46:11.35#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.146.00:46:11.35#ibcon#about to clear, iclass 17 cls_cnt 0 2006.146.00:46:11.35#ibcon#cleared, iclass 17 cls_cnt 0 2006.146.00:46:11.35$vck44/valo=6,814.99 2006.146.00:46:11.35#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.146.00:46:11.35#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.146.00:46:11.35#ibcon#ireg 17 cls_cnt 0 2006.146.00:46:11.35#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.146.00:46:11.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.146.00:46:11.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.146.00:46:11.38#ibcon#[26=FRQ=06,814.99\r\n] 2006.146.00:46:11.42#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.146.00:46:11.42#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.146.00:46:11.42#ibcon#about to clear, iclass 19 cls_cnt 0 2006.146.00:46:11.42#ibcon#cleared, iclass 19 cls_cnt 0 2006.146.00:46:11.42$vck44/va=6,4 2006.146.00:46:11.42#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.146.00:46:11.42#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.146.00:46:11.42#ibcon#ireg 11 cls_cnt 2 2006.146.00:46:11.42#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.146.00:46:11.47#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.146.00:46:11.47#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.146.00:46:11.49#ibcon#[25=AT06-04\r\n] 2006.146.00:46:11.52#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.146.00:46:11.52#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.146.00:46:11.52#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.146.00:46:11.52#ibcon#ireg 7 cls_cnt 0 2006.146.00:46:11.52#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.146.00:46:11.64#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.146.00:46:11.64#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.146.00:46:11.66#ibcon#[25=USB\r\n] 2006.146.00:46:11.69#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.146.00:46:11.69#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.146.00:46:11.69#ibcon#about to clear, iclass 21 cls_cnt 0 2006.146.00:46:11.69#ibcon#cleared, iclass 21 cls_cnt 0 2006.146.00:46:11.69$vck44/valo=7,864.99 2006.146.00:46:11.69#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.146.00:46:11.69#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.146.00:46:11.69#ibcon#ireg 17 cls_cnt 0 2006.146.00:46:11.69#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.146.00:46:11.69#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.146.00:46:11.69#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.146.00:46:11.71#ibcon#[26=FRQ=07,864.99\r\n] 2006.146.00:46:11.75#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.146.00:46:11.75#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.146.00:46:11.75#ibcon#about to clear, iclass 23 cls_cnt 0 2006.146.00:46:11.75#ibcon#cleared, iclass 23 cls_cnt 0 2006.146.00:46:11.75$vck44/va=7,4 2006.146.00:46:11.75#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.146.00:46:11.75#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.146.00:46:11.75#ibcon#ireg 11 cls_cnt 2 2006.146.00:46:11.75#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.146.00:46:11.81#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.146.00:46:11.81#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.146.00:46:11.83#ibcon#[25=AT07-04\r\n] 2006.146.00:46:11.86#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.146.00:46:11.86#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.146.00:46:11.86#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.146.00:46:11.86#ibcon#ireg 7 cls_cnt 0 2006.146.00:46:11.86#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.146.00:46:11.98#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.146.00:46:11.98#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.146.00:46:12.00#ibcon#[25=USB\r\n] 2006.146.00:46:12.03#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.146.00:46:12.03#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.146.00:46:12.03#ibcon#about to clear, iclass 25 cls_cnt 0 2006.146.00:46:12.03#ibcon#cleared, iclass 25 cls_cnt 0 2006.146.00:46:12.03$vck44/valo=8,884.99 2006.146.00:46:12.03#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.146.00:46:12.03#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.146.00:46:12.03#ibcon#ireg 17 cls_cnt 0 2006.146.00:46:12.03#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.146.00:46:12.03#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.146.00:46:12.03#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.146.00:46:12.05#ibcon#[26=FRQ=08,884.99\r\n] 2006.146.00:46:12.09#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.146.00:46:12.09#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.146.00:46:12.09#ibcon#about to clear, iclass 27 cls_cnt 0 2006.146.00:46:12.09#ibcon#cleared, iclass 27 cls_cnt 0 2006.146.00:46:12.09$vck44/va=8,4 2006.146.00:46:12.09#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.146.00:46:12.09#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.146.00:46:12.09#ibcon#ireg 11 cls_cnt 2 2006.146.00:46:12.09#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.146.00:46:12.15#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.146.00:46:12.15#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.146.00:46:12.17#ibcon#[25=AT08-04\r\n] 2006.146.00:46:12.20#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.146.00:46:12.20#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.146.00:46:12.20#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.146.00:46:12.20#ibcon#ireg 7 cls_cnt 0 2006.146.00:46:12.20#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.146.00:46:12.32#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.146.00:46:12.32#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.146.00:46:12.34#ibcon#[25=USB\r\n] 2006.146.00:46:12.37#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.146.00:46:12.37#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.146.00:46:12.37#ibcon#about to clear, iclass 29 cls_cnt 0 2006.146.00:46:12.37#ibcon#cleared, iclass 29 cls_cnt 0 2006.146.00:46:12.37$vck44/vblo=1,629.99 2006.146.00:46:12.37#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.146.00:46:12.37#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.146.00:46:12.37#ibcon#ireg 17 cls_cnt 0 2006.146.00:46:12.37#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.146.00:46:12.37#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.146.00:46:12.37#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.146.00:46:12.39#ibcon#[28=FRQ=01,629.99\r\n] 2006.146.00:46:12.43#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.146.00:46:12.43#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.146.00:46:12.43#ibcon#about to clear, iclass 31 cls_cnt 0 2006.146.00:46:12.43#ibcon#cleared, iclass 31 cls_cnt 0 2006.146.00:46:12.43$vck44/vb=1,3 2006.146.00:46:12.43#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.146.00:46:12.43#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.146.00:46:12.43#ibcon#ireg 11 cls_cnt 2 2006.146.00:46:12.43#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.146.00:46:12.43#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.146.00:46:12.43#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.146.00:46:12.45#ibcon#[27=AT01-03\r\n] 2006.146.00:46:12.48#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.146.00:46:12.48#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.146.00:46:12.48#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.146.00:46:12.48#ibcon#ireg 7 cls_cnt 0 2006.146.00:46:12.48#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.146.00:46:12.60#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.146.00:46:12.60#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.146.00:46:12.62#ibcon#[27=USB\r\n] 2006.146.00:46:12.65#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.146.00:46:12.65#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.146.00:46:12.65#ibcon#about to clear, iclass 33 cls_cnt 0 2006.146.00:46:12.65#ibcon#cleared, iclass 33 cls_cnt 0 2006.146.00:46:12.65$vck44/vblo=2,634.99 2006.146.00:46:12.65#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.146.00:46:12.65#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.146.00:46:12.65#ibcon#ireg 17 cls_cnt 0 2006.146.00:46:12.65#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.146.00:46:12.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.146.00:46:12.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.146.00:46:12.67#ibcon#[28=FRQ=02,634.99\r\n] 2006.146.00:46:12.71#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.146.00:46:12.71#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.146.00:46:12.71#ibcon#about to clear, iclass 35 cls_cnt 0 2006.146.00:46:12.71#ibcon#cleared, iclass 35 cls_cnt 0 2006.146.00:46:12.71$vck44/vb=2,4 2006.146.00:46:12.71#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.146.00:46:12.71#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.146.00:46:12.71#ibcon#ireg 11 cls_cnt 2 2006.146.00:46:12.71#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.146.00:46:12.77#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.146.00:46:12.77#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.146.00:46:12.79#ibcon#[27=AT02-04\r\n] 2006.146.00:46:12.82#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.146.00:46:12.82#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.146.00:46:12.82#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.146.00:46:12.82#ibcon#ireg 7 cls_cnt 0 2006.146.00:46:12.82#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.146.00:46:12.94#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.146.00:46:12.94#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.146.00:46:12.96#ibcon#[27=USB\r\n] 2006.146.00:46:12.99#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.146.00:46:12.99#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.146.00:46:12.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.146.00:46:12.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.146.00:46:12.99$vck44/vblo=3,649.99 2006.146.00:46:12.99#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.146.00:46:12.99#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.146.00:46:12.99#ibcon#ireg 17 cls_cnt 0 2006.146.00:46:12.99#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.146.00:46:12.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.146.00:46:12.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.146.00:46:13.01#ibcon#[28=FRQ=03,649.99\r\n] 2006.146.00:46:13.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.146.00:46:13.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.146.00:46:13.05#ibcon#about to clear, iclass 39 cls_cnt 0 2006.146.00:46:13.05#ibcon#cleared, iclass 39 cls_cnt 0 2006.146.00:46:13.05$vck44/vb=3,4 2006.146.00:46:13.05#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.146.00:46:13.05#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.146.00:46:13.05#ibcon#ireg 11 cls_cnt 2 2006.146.00:46:13.05#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.146.00:46:13.11#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.146.00:46:13.11#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.146.00:46:13.13#ibcon#[27=AT03-04\r\n] 2006.146.00:46:13.16#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.146.00:46:13.16#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.146.00:46:13.16#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.146.00:46:13.16#ibcon#ireg 7 cls_cnt 0 2006.146.00:46:13.16#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.146.00:46:13.28#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.146.00:46:13.28#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.146.00:46:13.30#ibcon#[27=USB\r\n] 2006.146.00:46:13.33#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.146.00:46:13.33#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.146.00:46:13.33#ibcon#about to clear, iclass 3 cls_cnt 0 2006.146.00:46:13.33#ibcon#cleared, iclass 3 cls_cnt 0 2006.146.00:46:13.33$vck44/vblo=4,679.99 2006.146.00:46:13.33#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.146.00:46:13.33#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.146.00:46:13.33#ibcon#ireg 17 cls_cnt 0 2006.146.00:46:13.33#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.146.00:46:13.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.146.00:46:13.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.146.00:46:13.35#ibcon#[28=FRQ=04,679.99\r\n] 2006.146.00:46:13.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.146.00:46:13.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.146.00:46:13.39#ibcon#about to clear, iclass 5 cls_cnt 0 2006.146.00:46:13.39#ibcon#cleared, iclass 5 cls_cnt 0 2006.146.00:46:13.39$vck44/vb=4,4 2006.146.00:46:13.39#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.146.00:46:13.39#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.146.00:46:13.39#ibcon#ireg 11 cls_cnt 2 2006.146.00:46:13.39#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.146.00:46:13.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.146.00:46:13.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.146.00:46:13.47#ibcon#[27=AT04-04\r\n] 2006.146.00:46:13.50#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.146.00:46:13.50#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.146.00:46:13.50#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.146.00:46:13.50#ibcon#ireg 7 cls_cnt 0 2006.146.00:46:13.50#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.146.00:46:13.62#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.146.00:46:13.62#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.146.00:46:13.64#ibcon#[27=USB\r\n] 2006.146.00:46:13.67#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.146.00:46:13.67#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.146.00:46:13.67#ibcon#about to clear, iclass 7 cls_cnt 0 2006.146.00:46:13.67#ibcon#cleared, iclass 7 cls_cnt 0 2006.146.00:46:13.67$vck44/vblo=5,709.99 2006.146.00:46:13.67#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.146.00:46:13.67#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.146.00:46:13.67#ibcon#ireg 17 cls_cnt 0 2006.146.00:46:13.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.146.00:46:13.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.146.00:46:13.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.146.00:46:13.69#ibcon#[28=FRQ=05,709.99\r\n] 2006.146.00:46:13.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.146.00:46:13.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.146.00:46:13.73#ibcon#about to clear, iclass 11 cls_cnt 0 2006.146.00:46:13.73#ibcon#cleared, iclass 11 cls_cnt 0 2006.146.00:46:13.73$vck44/vb=5,4 2006.146.00:46:13.73#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.146.00:46:13.73#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.146.00:46:13.73#ibcon#ireg 11 cls_cnt 2 2006.146.00:46:13.73#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.146.00:46:13.79#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.146.00:46:13.79#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.146.00:46:13.81#ibcon#[27=AT05-04\r\n] 2006.146.00:46:13.84#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.146.00:46:13.84#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.146.00:46:13.84#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.146.00:46:13.84#ibcon#ireg 7 cls_cnt 0 2006.146.00:46:13.84#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.146.00:46:13.96#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.146.00:46:13.96#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.146.00:46:13.98#ibcon#[27=USB\r\n] 2006.146.00:46:14.01#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.146.00:46:14.01#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.146.00:46:14.01#ibcon#about to clear, iclass 13 cls_cnt 0 2006.146.00:46:14.01#ibcon#cleared, iclass 13 cls_cnt 0 2006.146.00:46:14.01$vck44/vblo=6,719.99 2006.146.00:46:14.01#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.146.00:46:14.01#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.146.00:46:14.01#ibcon#ireg 17 cls_cnt 0 2006.146.00:46:14.01#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.146.00:46:14.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.146.00:46:14.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.146.00:46:14.03#ibcon#[28=FRQ=06,719.99\r\n] 2006.146.00:46:14.07#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.146.00:46:14.07#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.146.00:46:14.07#ibcon#about to clear, iclass 15 cls_cnt 0 2006.146.00:46:14.07#ibcon#cleared, iclass 15 cls_cnt 0 2006.146.00:46:14.07$vck44/vb=6,4 2006.146.00:46:14.07#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.146.00:46:14.07#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.146.00:46:14.07#ibcon#ireg 11 cls_cnt 2 2006.146.00:46:14.07#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.146.00:46:14.13#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.146.00:46:14.13#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.146.00:46:14.15#ibcon#[27=AT06-04\r\n] 2006.146.00:46:14.18#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.146.00:46:14.18#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.146.00:46:14.18#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.146.00:46:14.18#ibcon#ireg 7 cls_cnt 0 2006.146.00:46:14.18#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.146.00:46:14.30#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.146.00:46:14.30#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.146.00:46:14.32#ibcon#[27=USB\r\n] 2006.146.00:46:14.35#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.146.00:46:14.35#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.146.00:46:14.35#ibcon#about to clear, iclass 17 cls_cnt 0 2006.146.00:46:14.35#ibcon#cleared, iclass 17 cls_cnt 0 2006.146.00:46:14.35$vck44/vblo=7,734.99 2006.146.00:46:14.35#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.146.00:46:14.35#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.146.00:46:14.35#ibcon#ireg 17 cls_cnt 0 2006.146.00:46:14.35#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.146.00:46:14.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.146.00:46:14.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.146.00:46:14.37#ibcon#[28=FRQ=07,734.99\r\n] 2006.146.00:46:14.41#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.146.00:46:14.41#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.146.00:46:14.41#ibcon#about to clear, iclass 19 cls_cnt 0 2006.146.00:46:14.41#ibcon#cleared, iclass 19 cls_cnt 0 2006.146.00:46:14.41$vck44/vb=7,4 2006.146.00:46:14.41#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.146.00:46:14.41#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.146.00:46:14.41#ibcon#ireg 11 cls_cnt 2 2006.146.00:46:14.41#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.146.00:46:14.47#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.146.00:46:14.47#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.146.00:46:14.49#ibcon#[27=AT07-04\r\n] 2006.146.00:46:14.52#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.146.00:46:14.52#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.146.00:46:14.52#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.146.00:46:14.52#ibcon#ireg 7 cls_cnt 0 2006.146.00:46:14.52#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.146.00:46:14.64#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.146.00:46:14.64#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.146.00:46:14.66#ibcon#[27=USB\r\n] 2006.146.00:46:14.69#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.146.00:46:14.69#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.146.00:46:14.69#ibcon#about to clear, iclass 21 cls_cnt 0 2006.146.00:46:14.69#ibcon#cleared, iclass 21 cls_cnt 0 2006.146.00:46:14.69$vck44/vblo=8,744.99 2006.146.00:46:14.69#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.146.00:46:14.69#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.146.00:46:14.69#ibcon#ireg 17 cls_cnt 0 2006.146.00:46:14.69#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.146.00:46:14.69#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.146.00:46:14.69#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.146.00:46:14.71#ibcon#[28=FRQ=08,744.99\r\n] 2006.146.00:46:14.75#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.146.00:46:14.75#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.146.00:46:14.75#ibcon#about to clear, iclass 23 cls_cnt 0 2006.146.00:46:14.75#ibcon#cleared, iclass 23 cls_cnt 0 2006.146.00:46:14.75$vck44/vb=8,4 2006.146.00:46:14.75#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.146.00:46:14.75#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.146.00:46:14.75#ibcon#ireg 11 cls_cnt 2 2006.146.00:46:14.75#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.146.00:46:14.81#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.146.00:46:14.81#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.146.00:46:14.83#ibcon#[27=AT08-04\r\n] 2006.146.00:46:14.86#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.146.00:46:14.86#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.146.00:46:14.86#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.146.00:46:14.86#ibcon#ireg 7 cls_cnt 0 2006.146.00:46:14.86#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.146.00:46:14.98#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.146.00:46:14.98#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.146.00:46:15.00#ibcon#[27=USB\r\n] 2006.146.00:46:15.03#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.146.00:46:15.03#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.146.00:46:15.03#ibcon#about to clear, iclass 25 cls_cnt 0 2006.146.00:46:15.03#ibcon#cleared, iclass 25 cls_cnt 0 2006.146.00:46:15.03$vck44/vabw=wide 2006.146.00:46:15.03#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.146.00:46:15.03#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.146.00:46:15.03#ibcon#ireg 8 cls_cnt 0 2006.146.00:46:15.03#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.146.00:46:15.03#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.146.00:46:15.03#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.146.00:46:15.05#ibcon#[25=BW32\r\n] 2006.146.00:46:15.08#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.146.00:46:15.08#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.146.00:46:15.08#ibcon#about to clear, iclass 27 cls_cnt 0 2006.146.00:46:15.08#ibcon#cleared, iclass 27 cls_cnt 0 2006.146.00:46:15.08$vck44/vbbw=wide 2006.146.00:46:15.08#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.146.00:46:15.08#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.146.00:46:15.08#ibcon#ireg 8 cls_cnt 0 2006.146.00:46:15.08#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:46:15.15#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:46:15.15#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:46:15.17#ibcon#[27=BW32\r\n] 2006.146.00:46:15.20#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:46:15.20#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:46:15.20#ibcon#about to clear, iclass 29 cls_cnt 0 2006.146.00:46:15.20#ibcon#cleared, iclass 29 cls_cnt 0 2006.146.00:46:15.20$setupk4/ifdk4 2006.146.00:46:15.20$ifdk4/lo= 2006.146.00:46:15.20$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.146.00:46:15.20$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.146.00:46:15.20$ifdk4/patch= 2006.146.00:46:15.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.146.00:46:15.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.146.00:46:15.20$setupk4/!*+20s 2006.146.00:46:18.10#abcon#<5=/09 2.3 6.1 20.74 691020.6\r\n> 2006.146.00:46:18.12#abcon#{5=INTERFACE CLEAR} 2006.146.00:46:18.18#abcon#[5=S1D000X0/0*\r\n] 2006.146.00:46:28.27#abcon#<5=/09 2.2 6.1 20.74 691020.5\r\n> 2006.146.00:46:28.29#abcon#{5=INTERFACE CLEAR} 2006.146.00:46:28.35#abcon#[5=S1D000X0/0*\r\n] 2006.146.00:46:29.68$setupk4/"tpicd 2006.146.00:46:29.68$setupk4/echo=off 2006.146.00:46:29.68$setupk4/xlog=off 2006.146.00:46:29.68:!2006.146.00:52:24 2006.146.00:46:57.14#trakl#Source acquired 2006.146.00:46:58.14#flagr#flagr/antenna,acquired 2006.146.00:52:24.00:preob 2006.146.00:52:24.13/onsource/TRACKING 2006.146.00:52:24.13:!2006.146.00:52:34 2006.146.00:52:34.00:"tape 2006.146.00:52:34.00:"st=record 2006.146.00:52:34.00:data_valid=on 2006.146.00:52:34.00:midob 2006.146.00:52:34.13/onsource/TRACKING 2006.146.00:52:34.13/wx/21.00,1020.3,67 2006.146.00:52:34.32/cable/+6.5415E-03 2006.146.00:52:35.41/va/01,08,usb,yes,28,31 2006.146.00:52:35.41/va/02,07,usb,yes,30,31 2006.146.00:52:35.41/va/03,08,usb,yes,28,29 2006.146.00:52:35.41/va/04,07,usb,yes,31,33 2006.146.00:52:35.41/va/05,04,usb,yes,27,28 2006.146.00:52:35.41/va/06,04,usb,yes,31,31 2006.146.00:52:35.41/va/07,04,usb,yes,31,32 2006.146.00:52:35.41/va/08,04,usb,yes,26,32 2006.146.00:52:35.64/valo/01,524.99,yes,locked 2006.146.00:52:35.64/valo/02,534.99,yes,locked 2006.146.00:52:35.64/valo/03,564.99,yes,locked 2006.146.00:52:35.64/valo/04,624.99,yes,locked 2006.146.00:52:35.64/valo/05,734.99,yes,locked 2006.146.00:52:35.64/valo/06,814.99,yes,locked 2006.146.00:52:35.64/valo/07,864.99,yes,locked 2006.146.00:52:35.64/valo/08,884.99,yes,locked 2006.146.00:52:36.73/vb/01,03,usb,yes,36,33 2006.146.00:52:36.73/vb/02,04,usb,yes,31,31 2006.146.00:52:36.73/vb/03,04,usb,yes,28,31 2006.146.00:52:36.73/vb/04,04,usb,yes,32,31 2006.146.00:52:36.73/vb/05,04,usb,yes,25,27 2006.146.00:52:36.73/vb/06,04,usb,yes,29,26 2006.146.00:52:36.73/vb/07,04,usb,yes,29,29 2006.146.00:52:36.73/vb/08,04,usb,yes,27,30 2006.146.00:52:36.97/vblo/01,629.99,yes,locked 2006.146.00:52:36.97/vblo/02,634.99,yes,locked 2006.146.00:52:36.97/vblo/03,649.99,yes,locked 2006.146.00:52:36.97/vblo/04,679.99,yes,locked 2006.146.00:52:36.97/vblo/05,709.99,yes,locked 2006.146.00:52:36.97/vblo/06,719.99,yes,locked 2006.146.00:52:36.97/vblo/07,734.99,yes,locked 2006.146.00:52:36.97/vblo/08,744.99,yes,locked 2006.146.00:52:37.12/vabw/8 2006.146.00:52:37.27/vbbw/8 2006.146.00:52:37.36/xfe/off,on,14.7 2006.146.00:52:37.75/ifatt/23,28,28,28 2006.146.00:52:38.08/fmout-gps/S +4.1E-08 2006.146.00:52:38.12:!2006.146.00:53:24 2006.146.00:53:24.01:data_valid=off 2006.146.00:53:24.01:"et 2006.146.00:53:24.02:!+3s 2006.146.00:53:27.03:"tape 2006.146.00:53:27.03:postob 2006.146.00:53:27.21/cable/+6.5444E-03 2006.146.00:53:27.21/wx/21.04,1020.3,67 2006.146.00:53:27.30/fmout-gps/S +4.1E-08 2006.146.00:53:27.30:scan_name=146-0056,jd0605,90 2006.146.00:53:27.30:source=0528+134,053056.42,133155.1,2000.0,cw 2006.146.00:53:28.14#flagr#flagr/antenna,new-source 2006.146.00:53:28.14:checkk5 2006.146.00:53:28.59/chk_autoobs//k5ts1/ autoobs is running! 2006.146.00:53:29.03/chk_autoobs//k5ts2/ autoobs is running! 2006.146.00:53:29.47/chk_autoobs//k5ts3/ autoobs is running! 2006.146.00:53:29.90/chk_autoobs//k5ts4/ autoobs is running! 2006.146.00:53:30.33/chk_obsdata//k5ts1/T1460052??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.146.00:53:30.76/chk_obsdata//k5ts2/T1460052??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.146.00:53:31.21/chk_obsdata//k5ts3/T1460052??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.146.00:53:31.65/chk_obsdata//k5ts4/T1460052??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.146.00:53:32.42/k5log//k5ts1_log_newline 2006.146.00:53:33.18/k5log//k5ts2_log_newline 2006.146.00:53:33.91/k5log//k5ts3_log_newline 2006.146.00:53:34.64/k5log//k5ts4_log_newline 2006.146.00:53:34.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.146.00:53:34.67:setupk4=1 2006.146.00:53:34.67$setupk4/echo=on 2006.146.00:53:34.67$setupk4/pcalon 2006.146.00:53:34.67$pcalon/"no phase cal control is implemented here 2006.146.00:53:34.67$setupk4/"tpicd=stop 2006.146.00:53:34.67$setupk4/"rec=synch_on 2006.146.00:53:34.67$setupk4/"rec_mode=128 2006.146.00:53:34.67$setupk4/!* 2006.146.00:53:34.67$setupk4/recpk4 2006.146.00:53:34.67$recpk4/recpatch= 2006.146.00:53:34.67$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.146.00:53:34.67$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.146.00:53:34.67$setupk4/vck44 2006.146.00:53:34.67$vck44/valo=1,524.99 2006.146.00:53:34.67#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.146.00:53:34.67#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.146.00:53:34.67#ibcon#ireg 17 cls_cnt 0 2006.146.00:53:34.67#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.146.00:53:34.67#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.146.00:53:34.67#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.146.00:53:34.71#ibcon#[26=FRQ=01,524.99\r\n] 2006.146.00:53:34.76#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.146.00:53:34.76#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.146.00:53:34.76#ibcon#about to clear, iclass 26 cls_cnt 0 2006.146.00:53:34.76#ibcon#cleared, iclass 26 cls_cnt 0 2006.146.00:53:34.76$vck44/va=1,8 2006.146.00:53:34.76#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.146.00:53:34.76#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.146.00:53:34.76#ibcon#ireg 11 cls_cnt 2 2006.146.00:53:34.76#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.146.00:53:34.76#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.146.00:53:34.76#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.146.00:53:34.78#ibcon#[25=AT01-08\r\n] 2006.146.00:53:34.81#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.146.00:53:34.81#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.146.00:53:34.81#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.146.00:53:34.81#ibcon#ireg 7 cls_cnt 0 2006.146.00:53:34.81#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.146.00:53:34.93#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.146.00:53:34.93#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.146.00:53:34.95#ibcon#[25=USB\r\n] 2006.146.00:53:34.98#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.146.00:53:34.98#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.146.00:53:34.98#ibcon#about to clear, iclass 28 cls_cnt 0 2006.146.00:53:34.98#ibcon#cleared, iclass 28 cls_cnt 0 2006.146.00:53:34.98$vck44/valo=2,534.99 2006.146.00:53:34.98#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.146.00:53:34.98#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.146.00:53:34.98#ibcon#ireg 17 cls_cnt 0 2006.146.00:53:34.98#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.146.00:53:34.98#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.146.00:53:34.98#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.146.00:53:35.01#ibcon#[26=FRQ=02,534.99\r\n] 2006.146.00:53:35.05#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.146.00:53:35.05#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.146.00:53:35.05#ibcon#about to clear, iclass 30 cls_cnt 0 2006.146.00:53:35.05#ibcon#cleared, iclass 30 cls_cnt 0 2006.146.00:53:35.05$vck44/va=2,7 2006.146.00:53:35.05#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.146.00:53:35.05#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.146.00:53:35.05#ibcon#ireg 11 cls_cnt 2 2006.146.00:53:35.05#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.146.00:53:35.10#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.146.00:53:35.10#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.146.00:53:35.12#ibcon#[25=AT02-07\r\n] 2006.146.00:53:35.15#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.146.00:53:35.15#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.146.00:53:35.15#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.146.00:53:35.15#ibcon#ireg 7 cls_cnt 0 2006.146.00:53:35.15#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.146.00:53:35.27#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.146.00:53:35.27#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.146.00:53:35.29#ibcon#[25=USB\r\n] 2006.146.00:53:35.32#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.146.00:53:35.32#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.146.00:53:35.32#ibcon#about to clear, iclass 32 cls_cnt 0 2006.146.00:53:35.32#ibcon#cleared, iclass 32 cls_cnt 0 2006.146.00:53:35.32$vck44/valo=3,564.99 2006.146.00:53:35.32#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.146.00:53:35.32#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.146.00:53:35.32#ibcon#ireg 17 cls_cnt 0 2006.146.00:53:35.32#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.146.00:53:35.32#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.146.00:53:35.32#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.146.00:53:35.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.146.00:53:35.38#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.146.00:53:35.38#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.146.00:53:35.38#ibcon#about to clear, iclass 34 cls_cnt 0 2006.146.00:53:35.38#ibcon#cleared, iclass 34 cls_cnt 0 2006.146.00:53:35.38$vck44/va=3,8 2006.146.00:53:35.38#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.146.00:53:35.38#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.146.00:53:35.38#ibcon#ireg 11 cls_cnt 2 2006.146.00:53:35.38#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.146.00:53:35.44#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.146.00:53:35.44#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.146.00:53:35.46#ibcon#[25=AT03-08\r\n] 2006.146.00:53:35.49#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.146.00:53:35.49#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.146.00:53:35.49#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.146.00:53:35.49#ibcon#ireg 7 cls_cnt 0 2006.146.00:53:35.49#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.146.00:53:35.61#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.146.00:53:35.61#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.146.00:53:35.63#ibcon#[25=USB\r\n] 2006.146.00:53:35.66#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.146.00:53:35.66#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.146.00:53:35.66#ibcon#about to clear, iclass 36 cls_cnt 0 2006.146.00:53:35.66#ibcon#cleared, iclass 36 cls_cnt 0 2006.146.00:53:35.66$vck44/valo=4,624.99 2006.146.00:53:35.66#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.146.00:53:35.66#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.146.00:53:35.66#ibcon#ireg 17 cls_cnt 0 2006.146.00:53:35.66#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.146.00:53:35.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.146.00:53:35.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.146.00:53:35.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.146.00:53:35.70#abcon#<5=/08 1.9 6.2 21.04 671020.3\r\n> 2006.146.00:53:35.72#abcon#{5=INTERFACE CLEAR} 2006.146.00:53:35.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.146.00:53:35.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.146.00:53:35.72#ibcon#about to clear, iclass 39 cls_cnt 0 2006.146.00:53:35.72#ibcon#cleared, iclass 39 cls_cnt 0 2006.146.00:53:35.72$vck44/va=4,7 2006.146.00:53:35.72#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.146.00:53:35.72#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.146.00:53:35.72#ibcon#ireg 11 cls_cnt 2 2006.146.00:53:35.72#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:53:35.78#abcon#[5=S1D000X0/0*\r\n] 2006.146.00:53:35.78#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:53:35.78#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:53:35.80#ibcon#[25=AT04-07\r\n] 2006.146.00:53:35.83#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:53:35.83#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:53:35.83#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.146.00:53:35.83#ibcon#ireg 7 cls_cnt 0 2006.146.00:53:35.83#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:53:35.95#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:53:35.95#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:53:35.97#ibcon#[25=USB\r\n] 2006.146.00:53:36.00#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:53:36.00#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:53:36.00#ibcon#about to clear, iclass 5 cls_cnt 0 2006.146.00:53:36.00#ibcon#cleared, iclass 5 cls_cnt 0 2006.146.00:53:36.00$vck44/valo=5,734.99 2006.146.00:53:36.00#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.146.00:53:36.00#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.146.00:53:36.00#ibcon#ireg 17 cls_cnt 0 2006.146.00:53:36.00#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.146.00:53:36.00#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.146.00:53:36.00#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.146.00:53:36.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.146.00:53:36.06#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.146.00:53:36.06#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.146.00:53:36.06#ibcon#about to clear, iclass 10 cls_cnt 0 2006.146.00:53:36.06#ibcon#cleared, iclass 10 cls_cnt 0 2006.146.00:53:36.06$vck44/va=5,4 2006.146.00:53:36.06#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.146.00:53:36.06#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.146.00:53:36.06#ibcon#ireg 11 cls_cnt 2 2006.146.00:53:36.06#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.146.00:53:36.12#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.146.00:53:36.12#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.146.00:53:36.14#ibcon#[25=AT05-04\r\n] 2006.146.00:53:36.17#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.146.00:53:36.17#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.146.00:53:36.17#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.146.00:53:36.17#ibcon#ireg 7 cls_cnt 0 2006.146.00:53:36.17#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.146.00:53:36.29#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.146.00:53:36.29#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.146.00:53:36.31#ibcon#[25=USB\r\n] 2006.146.00:53:36.36#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.146.00:53:36.36#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.146.00:53:36.36#ibcon#about to clear, iclass 12 cls_cnt 0 2006.146.00:53:36.36#ibcon#cleared, iclass 12 cls_cnt 0 2006.146.00:53:36.36$vck44/valo=6,814.99 2006.146.00:53:36.36#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.146.00:53:36.36#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.146.00:53:36.36#ibcon#ireg 17 cls_cnt 0 2006.146.00:53:36.36#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.146.00:53:36.36#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.146.00:53:36.36#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.146.00:53:36.37#ibcon#[26=FRQ=06,814.99\r\n] 2006.146.00:53:36.41#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.146.00:53:36.41#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.146.00:53:36.41#ibcon#about to clear, iclass 14 cls_cnt 0 2006.146.00:53:36.41#ibcon#cleared, iclass 14 cls_cnt 0 2006.146.00:53:36.41$vck44/va=6,4 2006.146.00:53:36.41#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.146.00:53:36.41#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.146.00:53:36.41#ibcon#ireg 11 cls_cnt 2 2006.146.00:53:36.41#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.146.00:53:36.48#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.146.00:53:36.48#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.146.00:53:36.50#ibcon#[25=AT06-04\r\n] 2006.146.00:53:36.53#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.146.00:53:36.53#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.146.00:53:36.53#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.146.00:53:36.53#ibcon#ireg 7 cls_cnt 0 2006.146.00:53:36.53#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.146.00:53:36.65#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.146.00:53:36.65#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.146.00:53:36.67#ibcon#[25=USB\r\n] 2006.146.00:53:36.70#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.146.00:53:36.70#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.146.00:53:36.70#ibcon#about to clear, iclass 16 cls_cnt 0 2006.146.00:53:36.70#ibcon#cleared, iclass 16 cls_cnt 0 2006.146.00:53:36.70$vck44/valo=7,864.99 2006.146.00:53:36.70#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.146.00:53:36.70#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.146.00:53:36.70#ibcon#ireg 17 cls_cnt 0 2006.146.00:53:36.70#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.146.00:53:36.70#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.146.00:53:36.70#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.146.00:53:36.72#ibcon#[26=FRQ=07,864.99\r\n] 2006.146.00:53:36.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.146.00:53:36.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.146.00:53:36.76#ibcon#about to clear, iclass 18 cls_cnt 0 2006.146.00:53:36.76#ibcon#cleared, iclass 18 cls_cnt 0 2006.146.00:53:36.76$vck44/va=7,4 2006.146.00:53:36.76#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.146.00:53:36.76#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.146.00:53:36.76#ibcon#ireg 11 cls_cnt 2 2006.146.00:53:36.76#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.146.00:53:36.82#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.146.00:53:36.82#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.146.00:53:36.84#ibcon#[25=AT07-04\r\n] 2006.146.00:53:36.87#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.146.00:53:36.87#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.146.00:53:36.87#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.146.00:53:36.87#ibcon#ireg 7 cls_cnt 0 2006.146.00:53:36.87#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.146.00:53:36.99#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.146.00:53:36.99#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.146.00:53:37.01#ibcon#[25=USB\r\n] 2006.146.00:53:37.04#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.146.00:53:37.04#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.146.00:53:37.04#ibcon#about to clear, iclass 20 cls_cnt 0 2006.146.00:53:37.04#ibcon#cleared, iclass 20 cls_cnt 0 2006.146.00:53:37.04$vck44/valo=8,884.99 2006.146.00:53:37.04#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.146.00:53:37.04#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.146.00:53:37.04#ibcon#ireg 17 cls_cnt 0 2006.146.00:53:37.04#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.146.00:53:37.04#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.146.00:53:37.04#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.146.00:53:37.06#ibcon#[26=FRQ=08,884.99\r\n] 2006.146.00:53:37.10#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.146.00:53:37.10#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.146.00:53:37.10#ibcon#about to clear, iclass 22 cls_cnt 0 2006.146.00:53:37.10#ibcon#cleared, iclass 22 cls_cnt 0 2006.146.00:53:37.10$vck44/va=8,4 2006.146.00:53:37.10#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.146.00:53:37.10#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.146.00:53:37.10#ibcon#ireg 11 cls_cnt 2 2006.146.00:53:37.10#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.146.00:53:37.16#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.146.00:53:37.16#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.146.00:53:37.18#ibcon#[25=AT08-04\r\n] 2006.146.00:53:37.21#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.146.00:53:37.21#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.146.00:53:37.21#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.146.00:53:37.21#ibcon#ireg 7 cls_cnt 0 2006.146.00:53:37.21#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.146.00:53:37.33#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.146.00:53:37.33#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.146.00:53:37.35#ibcon#[25=USB\r\n] 2006.146.00:53:37.38#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.146.00:53:37.38#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.146.00:53:37.38#ibcon#about to clear, iclass 24 cls_cnt 0 2006.146.00:53:37.38#ibcon#cleared, iclass 24 cls_cnt 0 2006.146.00:53:37.38$vck44/vblo=1,629.99 2006.146.00:53:37.38#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.146.00:53:37.38#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.146.00:53:37.38#ibcon#ireg 17 cls_cnt 0 2006.146.00:53:37.38#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.146.00:53:37.38#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.146.00:53:37.38#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.146.00:53:37.40#ibcon#[28=FRQ=01,629.99\r\n] 2006.146.00:53:37.44#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.146.00:53:37.44#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.146.00:53:37.44#ibcon#about to clear, iclass 26 cls_cnt 0 2006.146.00:53:37.44#ibcon#cleared, iclass 26 cls_cnt 0 2006.146.00:53:37.44$vck44/vb=1,3 2006.146.00:53:37.44#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.146.00:53:37.44#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.146.00:53:37.44#ibcon#ireg 11 cls_cnt 2 2006.146.00:53:37.44#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.146.00:53:37.44#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.146.00:53:37.44#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.146.00:53:37.46#ibcon#[27=AT01-03\r\n] 2006.146.00:53:37.49#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.146.00:53:37.49#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.146.00:53:37.49#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.146.00:53:37.49#ibcon#ireg 7 cls_cnt 0 2006.146.00:53:37.49#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.146.00:53:37.61#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.146.00:53:37.61#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.146.00:53:37.63#ibcon#[27=USB\r\n] 2006.146.00:53:37.66#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.146.00:53:37.66#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.146.00:53:37.66#ibcon#about to clear, iclass 28 cls_cnt 0 2006.146.00:53:37.66#ibcon#cleared, iclass 28 cls_cnt 0 2006.146.00:53:37.66$vck44/vblo=2,634.99 2006.146.00:53:37.66#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.146.00:53:37.66#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.146.00:53:37.66#ibcon#ireg 17 cls_cnt 0 2006.146.00:53:37.66#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.146.00:53:37.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.146.00:53:37.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.146.00:53:37.68#ibcon#[28=FRQ=02,634.99\r\n] 2006.146.00:53:37.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.146.00:53:37.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.146.00:53:37.72#ibcon#about to clear, iclass 30 cls_cnt 0 2006.146.00:53:37.72#ibcon#cleared, iclass 30 cls_cnt 0 2006.146.00:53:37.72$vck44/vb=2,4 2006.146.00:53:37.72#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.146.00:53:37.72#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.146.00:53:37.72#ibcon#ireg 11 cls_cnt 2 2006.146.00:53:37.72#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.146.00:53:37.78#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.146.00:53:37.78#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.146.00:53:37.80#ibcon#[27=AT02-04\r\n] 2006.146.00:53:37.83#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.146.00:53:37.83#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.146.00:53:37.83#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.146.00:53:37.83#ibcon#ireg 7 cls_cnt 0 2006.146.00:53:37.83#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.146.00:53:37.95#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.146.00:53:37.95#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.146.00:53:37.97#ibcon#[27=USB\r\n] 2006.146.00:53:38.00#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.146.00:53:38.00#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.146.00:53:38.00#ibcon#about to clear, iclass 32 cls_cnt 0 2006.146.00:53:38.00#ibcon#cleared, iclass 32 cls_cnt 0 2006.146.00:53:38.00$vck44/vblo=3,649.99 2006.146.00:53:38.00#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.146.00:53:38.00#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.146.00:53:38.00#ibcon#ireg 17 cls_cnt 0 2006.146.00:53:38.00#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.146.00:53:38.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.146.00:53:38.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.146.00:53:38.02#ibcon#[28=FRQ=03,649.99\r\n] 2006.146.00:53:38.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.146.00:53:38.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.146.00:53:38.06#ibcon#about to clear, iclass 34 cls_cnt 0 2006.146.00:53:38.06#ibcon#cleared, iclass 34 cls_cnt 0 2006.146.00:53:38.06$vck44/vb=3,4 2006.146.00:53:38.06#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.146.00:53:38.06#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.146.00:53:38.06#ibcon#ireg 11 cls_cnt 2 2006.146.00:53:38.06#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.146.00:53:38.12#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.146.00:53:38.12#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.146.00:53:38.14#ibcon#[27=AT03-04\r\n] 2006.146.00:53:38.17#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.146.00:53:38.17#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.146.00:53:38.17#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.146.00:53:38.17#ibcon#ireg 7 cls_cnt 0 2006.146.00:53:38.17#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.146.00:53:38.29#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.146.00:53:38.29#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.146.00:53:38.31#ibcon#[27=USB\r\n] 2006.146.00:53:38.34#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.146.00:53:38.34#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.146.00:53:38.34#ibcon#about to clear, iclass 36 cls_cnt 0 2006.146.00:53:38.34#ibcon#cleared, iclass 36 cls_cnt 0 2006.146.00:53:38.34$vck44/vblo=4,679.99 2006.146.00:53:38.34#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.146.00:53:38.34#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.146.00:53:38.34#ibcon#ireg 17 cls_cnt 0 2006.146.00:53:38.34#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.146.00:53:38.34#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.146.00:53:38.34#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.146.00:53:38.36#ibcon#[28=FRQ=04,679.99\r\n] 2006.146.00:53:38.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.146.00:53:38.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.146.00:53:38.40#ibcon#about to clear, iclass 38 cls_cnt 0 2006.146.00:53:38.40#ibcon#cleared, iclass 38 cls_cnt 0 2006.146.00:53:38.40$vck44/vb=4,4 2006.146.00:53:38.40#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.146.00:53:38.40#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.146.00:53:38.40#ibcon#ireg 11 cls_cnt 2 2006.146.00:53:38.40#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.146.00:53:38.46#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.146.00:53:38.46#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.146.00:53:38.48#ibcon#[27=AT04-04\r\n] 2006.146.00:53:38.51#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.146.00:53:38.51#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.146.00:53:38.51#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.146.00:53:38.51#ibcon#ireg 7 cls_cnt 0 2006.146.00:53:38.51#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.146.00:53:38.63#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.146.00:53:38.63#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.146.00:53:38.65#ibcon#[27=USB\r\n] 2006.146.00:53:38.68#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.146.00:53:38.68#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.146.00:53:38.68#ibcon#about to clear, iclass 40 cls_cnt 0 2006.146.00:53:38.68#ibcon#cleared, iclass 40 cls_cnt 0 2006.146.00:53:38.68$vck44/vblo=5,709.99 2006.146.00:53:38.68#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.146.00:53:38.68#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.146.00:53:38.68#ibcon#ireg 17 cls_cnt 0 2006.146.00:53:38.68#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.146.00:53:38.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.146.00:53:38.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.146.00:53:38.70#ibcon#[28=FRQ=05,709.99\r\n] 2006.146.00:53:38.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.146.00:53:38.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.146.00:53:38.74#ibcon#about to clear, iclass 4 cls_cnt 0 2006.146.00:53:38.74#ibcon#cleared, iclass 4 cls_cnt 0 2006.146.00:53:38.74$vck44/vb=5,4 2006.146.00:53:38.74#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.146.00:53:38.74#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.146.00:53:38.74#ibcon#ireg 11 cls_cnt 2 2006.146.00:53:38.74#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.146.00:53:38.80#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.146.00:53:38.80#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.146.00:53:38.82#ibcon#[27=AT05-04\r\n] 2006.146.00:53:38.85#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.146.00:53:38.85#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.146.00:53:38.85#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.146.00:53:38.85#ibcon#ireg 7 cls_cnt 0 2006.146.00:53:38.85#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.146.00:53:38.97#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.146.00:53:38.97#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.146.00:53:38.99#ibcon#[27=USB\r\n] 2006.146.00:53:39.02#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.146.00:53:39.02#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.146.00:53:39.02#ibcon#about to clear, iclass 6 cls_cnt 0 2006.146.00:53:39.02#ibcon#cleared, iclass 6 cls_cnt 0 2006.146.00:53:39.02$vck44/vblo=6,719.99 2006.146.00:53:39.02#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.146.00:53:39.02#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.146.00:53:39.02#ibcon#ireg 17 cls_cnt 0 2006.146.00:53:39.02#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.146.00:53:39.02#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.146.00:53:39.02#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.146.00:53:39.04#ibcon#[28=FRQ=06,719.99\r\n] 2006.146.00:53:39.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.146.00:53:39.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.146.00:53:39.08#ibcon#about to clear, iclass 10 cls_cnt 0 2006.146.00:53:39.08#ibcon#cleared, iclass 10 cls_cnt 0 2006.146.00:53:39.08$vck44/vb=6,4 2006.146.00:53:39.08#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.146.00:53:39.08#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.146.00:53:39.08#ibcon#ireg 11 cls_cnt 2 2006.146.00:53:39.08#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.146.00:53:39.14#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.146.00:53:39.14#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.146.00:53:39.16#ibcon#[27=AT06-04\r\n] 2006.146.00:53:39.19#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.146.00:53:39.19#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.146.00:53:39.19#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.146.00:53:39.19#ibcon#ireg 7 cls_cnt 0 2006.146.00:53:39.19#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.146.00:53:39.31#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.146.00:53:39.31#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.146.00:53:39.33#ibcon#[27=USB\r\n] 2006.146.00:53:39.36#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.146.00:53:39.36#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.146.00:53:39.36#ibcon#about to clear, iclass 12 cls_cnt 0 2006.146.00:53:39.36#ibcon#cleared, iclass 12 cls_cnt 0 2006.146.00:53:39.36$vck44/vblo=7,734.99 2006.146.00:53:39.36#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.146.00:53:39.36#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.146.00:53:39.36#ibcon#ireg 17 cls_cnt 0 2006.146.00:53:39.36#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.146.00:53:39.36#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.146.00:53:39.36#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.146.00:53:39.38#ibcon#[28=FRQ=07,734.99\r\n] 2006.146.00:53:39.42#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.146.00:53:39.42#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.146.00:53:39.42#ibcon#about to clear, iclass 14 cls_cnt 0 2006.146.00:53:39.42#ibcon#cleared, iclass 14 cls_cnt 0 2006.146.00:53:39.42$vck44/vb=7,4 2006.146.00:53:39.42#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.146.00:53:39.42#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.146.00:53:39.42#ibcon#ireg 11 cls_cnt 2 2006.146.00:53:39.42#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.146.00:53:39.48#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.146.00:53:39.48#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.146.00:53:39.50#ibcon#[27=AT07-04\r\n] 2006.146.00:53:39.53#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.146.00:53:39.53#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.146.00:53:39.53#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.146.00:53:39.53#ibcon#ireg 7 cls_cnt 0 2006.146.00:53:39.53#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.146.00:53:39.65#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.146.00:53:39.65#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.146.00:53:39.67#ibcon#[27=USB\r\n] 2006.146.00:53:39.70#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.146.00:53:39.70#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.146.00:53:39.70#ibcon#about to clear, iclass 16 cls_cnt 0 2006.146.00:53:39.70#ibcon#cleared, iclass 16 cls_cnt 0 2006.146.00:53:39.70$vck44/vblo=8,744.99 2006.146.00:53:39.70#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.146.00:53:39.70#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.146.00:53:39.70#ibcon#ireg 17 cls_cnt 0 2006.146.00:53:39.70#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.146.00:53:39.70#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.146.00:53:39.70#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.146.00:53:39.72#ibcon#[28=FRQ=08,744.99\r\n] 2006.146.00:53:39.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.146.00:53:39.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.146.00:53:39.76#ibcon#about to clear, iclass 18 cls_cnt 0 2006.146.00:53:39.76#ibcon#cleared, iclass 18 cls_cnt 0 2006.146.00:53:39.76$vck44/vb=8,4 2006.146.00:53:39.76#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.146.00:53:39.76#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.146.00:53:39.76#ibcon#ireg 11 cls_cnt 2 2006.146.00:53:39.76#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.146.00:53:39.82#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.146.00:53:39.82#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.146.00:53:39.84#ibcon#[27=AT08-04\r\n] 2006.146.00:53:39.87#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.146.00:53:39.87#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.146.00:53:39.87#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.146.00:53:39.87#ibcon#ireg 7 cls_cnt 0 2006.146.00:53:39.87#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.146.00:53:39.99#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.146.00:53:39.99#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.146.00:53:40.01#ibcon#[27=USB\r\n] 2006.146.00:53:40.04#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.146.00:53:40.04#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.146.00:53:40.04#ibcon#about to clear, iclass 20 cls_cnt 0 2006.146.00:53:40.04#ibcon#cleared, iclass 20 cls_cnt 0 2006.146.00:53:40.04$vck44/vabw=wide 2006.146.00:53:40.04#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.146.00:53:40.04#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.146.00:53:40.04#ibcon#ireg 8 cls_cnt 0 2006.146.00:53:40.04#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.146.00:53:40.04#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.146.00:53:40.04#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.146.00:53:40.06#ibcon#[25=BW32\r\n] 2006.146.00:53:40.09#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.146.00:53:40.09#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.146.00:53:40.09#ibcon#about to clear, iclass 22 cls_cnt 0 2006.146.00:53:40.09#ibcon#cleared, iclass 22 cls_cnt 0 2006.146.00:53:40.09$vck44/vbbw=wide 2006.146.00:53:40.09#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.146.00:53:40.09#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.146.00:53:40.09#ibcon#ireg 8 cls_cnt 0 2006.146.00:53:40.09#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.146.00:53:40.16#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.146.00:53:40.16#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.146.00:53:40.18#ibcon#[27=BW32\r\n] 2006.146.00:53:40.21#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.146.00:53:40.21#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.146.00:53:40.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.146.00:53:40.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.146.00:53:40.21$setupk4/ifdk4 2006.146.00:53:40.21$ifdk4/lo= 2006.146.00:53:40.21$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.146.00:53:40.21$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.146.00:53:40.21$ifdk4/patch= 2006.146.00:53:40.21$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.146.00:53:40.21$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.146.00:53:40.21$setupk4/!*+20s 2006.146.00:53:45.87#abcon#<5=/08 1.9 6.2 21.05 661020.3\r\n> 2006.146.00:53:45.89#abcon#{5=INTERFACE CLEAR} 2006.146.00:53:45.95#abcon#[5=S1D000X0/0*\r\n] 2006.146.00:53:49.14#trakl#Source acquired 2006.146.00:53:50.14#flagr#flagr/antenna,acquired 2006.146.00:53:54.68$setupk4/"tpicd 2006.146.00:53:54.68$setupk4/echo=off 2006.146.00:53:54.68$setupk4/xlog=off 2006.146.00:53:54.68:!2006.146.00:55:50 2006.146.00:55:50.00:preob 2006.146.00:55:51.14/onsource/TRACKING 2006.146.00:55:51.14:!2006.146.00:56:00 2006.146.00:56:00.00:"tape 2006.146.00:56:00.00:"st=record 2006.146.00:56:00.00:data_valid=on 2006.146.00:56:00.00:midob 2006.146.00:56:00.14/onsource/TRACKING 2006.146.00:56:00.14/wx/21.08,1020.3,66 2006.146.00:56:00.22/cable/+6.5427E-03 2006.146.00:56:01.31/va/01,08,usb,yes,28,31 2006.146.00:56:01.31/va/02,07,usb,yes,30,31 2006.146.00:56:01.31/va/03,08,usb,yes,28,29 2006.146.00:56:01.31/va/04,07,usb,yes,31,33 2006.146.00:56:01.31/va/05,04,usb,yes,27,28 2006.146.00:56:01.31/va/06,04,usb,yes,31,31 2006.146.00:56:01.31/va/07,04,usb,yes,31,32 2006.146.00:56:01.31/va/08,04,usb,yes,26,32 2006.146.00:56:01.54/valo/01,524.99,yes,locked 2006.146.00:56:01.54/valo/02,534.99,yes,locked 2006.146.00:56:01.54/valo/03,564.99,yes,locked 2006.146.00:56:01.54/valo/04,624.99,yes,locked 2006.146.00:56:01.54/valo/05,734.99,yes,locked 2006.146.00:56:01.54/valo/06,814.99,yes,locked 2006.146.00:56:01.54/valo/07,864.99,yes,locked 2006.146.00:56:01.54/valo/08,884.99,yes,locked 2006.146.00:56:02.63/vb/01,03,usb,yes,36,33 2006.146.00:56:02.63/vb/02,04,usb,yes,31,31 2006.146.00:56:02.63/vb/03,04,usb,yes,28,31 2006.146.00:56:02.63/vb/04,04,usb,yes,32,31 2006.146.00:56:02.63/vb/05,04,usb,yes,25,28 2006.146.00:56:02.63/vb/06,04,usb,yes,30,26 2006.146.00:56:02.63/vb/07,04,usb,yes,29,29 2006.146.00:56:02.63/vb/08,04,usb,yes,27,30 2006.146.00:56:02.86/vblo/01,629.99,yes,locked 2006.146.00:56:02.86/vblo/02,634.99,yes,locked 2006.146.00:56:02.86/vblo/03,649.99,yes,locked 2006.146.00:56:02.86/vblo/04,679.99,yes,locked 2006.146.00:56:02.86/vblo/05,709.99,yes,locked 2006.146.00:56:02.86/vblo/06,719.99,yes,locked 2006.146.00:56:02.86/vblo/07,734.99,yes,locked 2006.146.00:56:02.86/vblo/08,744.99,yes,locked 2006.146.00:56:03.01/vabw/8 2006.146.00:56:03.16/vbbw/8 2006.146.00:56:03.25/xfe/off,on,15.2 2006.146.00:56:03.62/ifatt/23,28,28,28 2006.146.00:56:04.07/fmout-gps/S +4.2E-08 2006.146.00:56:04.11:!2006.146.00:57:30 2006.146.00:57:30.01:data_valid=off 2006.146.00:57:30.01:"et 2006.146.00:57:30.02:!+3s 2006.146.00:57:33.03:"tape 2006.146.00:57:33.03:postob 2006.146.00:57:33.16/cable/+6.5420E-03 2006.146.00:57:33.16/wx/21.08,1020.4,66 2006.146.00:57:33.22/fmout-gps/S +4.1E-08 2006.146.00:57:33.22:scan_name=146-0100,jd0605,40 2006.146.00:57:33.22:source=0727-115,073019.11,-114112.6,2000.0,cw 2006.146.00:57:34.14#flagr#flagr/antenna,new-source 2006.146.00:57:34.14:checkk5 2006.146.00:57:34.59/chk_autoobs//k5ts1/ autoobs is running! 2006.146.00:57:35.02/chk_autoobs//k5ts2/ autoobs is running! 2006.146.00:57:35.46/chk_autoobs//k5ts3/ autoobs is running! 2006.146.00:57:35.89/chk_autoobs//k5ts4/ autoobs is running! 2006.146.00:57:36.31/chk_obsdata//k5ts1/T1460056??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.146.00:57:36.75/chk_obsdata//k5ts2/T1460056??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.146.00:57:37.18/chk_obsdata//k5ts3/T1460056??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.146.00:57:37.62/chk_obsdata//k5ts4/T1460056??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.146.00:57:38.38/k5log//k5ts1_log_newline 2006.146.00:57:39.11/k5log//k5ts2_log_newline 2006.146.00:57:39.86/k5log//k5ts3_log_newline 2006.146.00:57:40.60/k5log//k5ts4_log_newline 2006.146.00:57:40.63/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.146.00:57:40.63:setupk4=1 2006.146.00:57:40.63$setupk4/echo=on 2006.146.00:57:40.63$setupk4/pcalon 2006.146.00:57:40.63$pcalon/"no phase cal control is implemented here 2006.146.00:57:40.63$setupk4/"tpicd=stop 2006.146.00:57:40.63$setupk4/"rec=synch_on 2006.146.00:57:40.63$setupk4/"rec_mode=128 2006.146.00:57:40.63$setupk4/!* 2006.146.00:57:40.63$setupk4/recpk4 2006.146.00:57:40.63$recpk4/recpatch= 2006.146.00:57:40.63$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.146.00:57:40.63$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.146.00:57:40.63$setupk4/vck44 2006.146.00:57:40.63$vck44/valo=1,524.99 2006.146.00:57:40.63#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.146.00:57:40.63#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.146.00:57:40.63#ibcon#ireg 17 cls_cnt 0 2006.146.00:57:40.63#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:57:40.63#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:57:40.63#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:57:40.67#ibcon#[26=FRQ=01,524.99\r\n] 2006.146.00:57:40.72#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:57:40.72#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:57:40.72#ibcon#about to clear, iclass 17 cls_cnt 0 2006.146.00:57:40.72#ibcon#cleared, iclass 17 cls_cnt 0 2006.146.00:57:40.72$vck44/va=1,8 2006.146.00:57:40.72#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.146.00:57:40.72#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.146.00:57:40.72#ibcon#ireg 11 cls_cnt 2 2006.146.00:57:40.72#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:57:40.72#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:57:40.72#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:57:40.74#ibcon#[25=AT01-08\r\n] 2006.146.00:57:40.77#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:57:40.77#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:57:40.77#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.146.00:57:40.77#ibcon#ireg 7 cls_cnt 0 2006.146.00:57:40.77#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:57:40.90#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:57:40.90#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:57:40.91#ibcon#[25=USB\r\n] 2006.146.00:57:40.94#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:57:40.94#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:57:40.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.146.00:57:40.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.146.00:57:40.94$vck44/valo=2,534.99 2006.146.00:57:40.94#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.146.00:57:40.94#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.146.00:57:40.94#ibcon#ireg 17 cls_cnt 0 2006.146.00:57:40.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:57:40.94#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:57:40.94#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:57:40.97#ibcon#[26=FRQ=02,534.99\r\n] 2006.146.00:57:41.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:57:41.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:57:41.02#ibcon#about to clear, iclass 21 cls_cnt 0 2006.146.00:57:41.02#ibcon#cleared, iclass 21 cls_cnt 0 2006.146.00:57:41.02$vck44/va=2,7 2006.146.00:57:41.02#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.146.00:57:41.02#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.146.00:57:41.02#ibcon#ireg 11 cls_cnt 2 2006.146.00:57:41.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:57:41.06#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:57:41.06#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:57:41.08#ibcon#[25=AT02-07\r\n] 2006.146.00:57:41.11#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:57:41.11#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:57:41.11#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.146.00:57:41.11#ibcon#ireg 7 cls_cnt 0 2006.146.00:57:41.11#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:57:41.23#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:57:41.23#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:57:41.25#ibcon#[25=USB\r\n] 2006.146.00:57:41.28#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:57:41.28#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:57:41.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.146.00:57:41.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.146.00:57:41.28$vck44/valo=3,564.99 2006.146.00:57:41.28#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.146.00:57:41.28#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.146.00:57:41.28#ibcon#ireg 17 cls_cnt 0 2006.146.00:57:41.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:57:41.28#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:57:41.28#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:57:41.30#ibcon#[26=FRQ=03,564.99\r\n] 2006.146.00:57:41.34#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:57:41.34#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:57:41.34#ibcon#about to clear, iclass 25 cls_cnt 0 2006.146.00:57:41.34#ibcon#cleared, iclass 25 cls_cnt 0 2006.146.00:57:41.34$vck44/va=3,8 2006.146.00:57:41.34#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.146.00:57:41.34#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.146.00:57:41.34#ibcon#ireg 11 cls_cnt 2 2006.146.00:57:41.34#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.146.00:57:41.40#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.146.00:57:41.40#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.146.00:57:41.42#ibcon#[25=AT03-08\r\n] 2006.146.00:57:41.45#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.146.00:57:41.45#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.146.00:57:41.45#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.146.00:57:41.45#ibcon#ireg 7 cls_cnt 0 2006.146.00:57:41.45#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.146.00:57:41.57#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.146.00:57:41.57#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.146.00:57:41.59#ibcon#[25=USB\r\n] 2006.146.00:57:41.62#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.146.00:57:41.62#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.146.00:57:41.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.146.00:57:41.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.146.00:57:41.62$vck44/valo=4,624.99 2006.146.00:57:41.62#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.146.00:57:41.62#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.146.00:57:41.62#ibcon#ireg 17 cls_cnt 0 2006.146.00:57:41.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:57:41.62#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:57:41.62#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:57:41.64#ibcon#[26=FRQ=04,624.99\r\n] 2006.146.00:57:41.68#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:57:41.68#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:57:41.68#ibcon#about to clear, iclass 29 cls_cnt 0 2006.146.00:57:41.68#ibcon#cleared, iclass 29 cls_cnt 0 2006.146.00:57:41.68$vck44/va=4,7 2006.146.00:57:41.68#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.146.00:57:41.68#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.146.00:57:41.68#ibcon#ireg 11 cls_cnt 2 2006.146.00:57:41.68#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.146.00:57:41.74#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.146.00:57:41.74#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.146.00:57:41.76#ibcon#[25=AT04-07\r\n] 2006.146.00:57:41.79#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.146.00:57:41.79#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.146.00:57:41.79#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.146.00:57:41.79#ibcon#ireg 7 cls_cnt 0 2006.146.00:57:41.79#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.146.00:57:41.91#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.146.00:57:41.91#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.146.00:57:41.93#ibcon#[25=USB\r\n] 2006.146.00:57:41.96#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.146.00:57:41.96#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.146.00:57:41.96#ibcon#about to clear, iclass 31 cls_cnt 0 2006.146.00:57:41.96#ibcon#cleared, iclass 31 cls_cnt 0 2006.146.00:57:41.96$vck44/valo=5,734.99 2006.146.00:57:41.96#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.146.00:57:41.96#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.146.00:57:41.96#ibcon#ireg 17 cls_cnt 0 2006.146.00:57:41.96#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.146.00:57:41.96#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.146.00:57:41.96#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.146.00:57:41.98#ibcon#[26=FRQ=05,734.99\r\n] 2006.146.00:57:42.02#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.146.00:57:42.02#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.146.00:57:42.02#ibcon#about to clear, iclass 33 cls_cnt 0 2006.146.00:57:42.02#ibcon#cleared, iclass 33 cls_cnt 0 2006.146.00:57:42.02$vck44/va=5,4 2006.146.00:57:42.02#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.146.00:57:42.02#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.146.00:57:42.02#ibcon#ireg 11 cls_cnt 2 2006.146.00:57:42.02#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.146.00:57:42.08#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.146.00:57:42.08#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.146.00:57:42.10#ibcon#[25=AT05-04\r\n] 2006.146.00:57:42.13#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.146.00:57:42.13#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.146.00:57:42.13#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.146.00:57:42.13#ibcon#ireg 7 cls_cnt 0 2006.146.00:57:42.13#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.146.00:57:42.25#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.146.00:57:42.25#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.146.00:57:42.27#ibcon#[25=USB\r\n] 2006.146.00:57:42.30#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.146.00:57:42.30#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.146.00:57:42.30#ibcon#about to clear, iclass 35 cls_cnt 0 2006.146.00:57:42.30#ibcon#cleared, iclass 35 cls_cnt 0 2006.146.00:57:42.30$vck44/valo=6,814.99 2006.146.00:57:42.30#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.146.00:57:42.30#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.146.00:57:42.30#ibcon#ireg 17 cls_cnt 0 2006.146.00:57:42.30#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:57:42.30#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:57:42.30#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:57:42.33#ibcon#[26=FRQ=06,814.99\r\n] 2006.146.00:57:42.37#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:57:42.37#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:57:42.37#ibcon#about to clear, iclass 37 cls_cnt 0 2006.146.00:57:42.37#ibcon#cleared, iclass 37 cls_cnt 0 2006.146.00:57:42.37$vck44/va=6,4 2006.146.00:57:42.37#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.146.00:57:42.37#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.146.00:57:42.37#ibcon#ireg 11 cls_cnt 2 2006.146.00:57:42.37#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:57:42.42#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:57:42.42#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:57:42.44#ibcon#[25=AT06-04\r\n] 2006.146.00:57:42.47#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:57:42.47#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:57:42.47#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.146.00:57:42.47#ibcon#ireg 7 cls_cnt 0 2006.146.00:57:42.47#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:57:42.59#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:57:42.59#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:57:42.61#ibcon#[25=USB\r\n] 2006.146.00:57:42.64#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:57:42.64#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:57:42.64#ibcon#about to clear, iclass 39 cls_cnt 0 2006.146.00:57:42.64#ibcon#cleared, iclass 39 cls_cnt 0 2006.146.00:57:42.64$vck44/valo=7,864.99 2006.146.00:57:42.64#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.146.00:57:42.64#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.146.00:57:42.64#ibcon#ireg 17 cls_cnt 0 2006.146.00:57:42.64#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:57:42.64#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:57:42.64#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:57:42.66#ibcon#[26=FRQ=07,864.99\r\n] 2006.146.00:57:42.70#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:57:42.70#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:57:42.70#ibcon#about to clear, iclass 3 cls_cnt 0 2006.146.00:57:42.70#ibcon#cleared, iclass 3 cls_cnt 0 2006.146.00:57:42.70$vck44/va=7,4 2006.146.00:57:42.70#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.146.00:57:42.70#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.146.00:57:42.70#ibcon#ireg 11 cls_cnt 2 2006.146.00:57:42.70#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:57:42.76#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:57:42.76#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:57:42.78#ibcon#[25=AT07-04\r\n] 2006.146.00:57:42.81#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:57:42.81#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:57:42.81#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.146.00:57:42.81#ibcon#ireg 7 cls_cnt 0 2006.146.00:57:42.81#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:57:42.93#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:57:42.93#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:57:42.95#ibcon#[25=USB\r\n] 2006.146.00:57:42.98#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:57:42.98#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:57:42.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.146.00:57:42.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.146.00:57:42.98$vck44/valo=8,884.99 2006.146.00:57:42.98#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.146.00:57:42.98#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.146.00:57:42.98#ibcon#ireg 17 cls_cnt 0 2006.146.00:57:42.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:57:42.98#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:57:42.98#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:57:43.00#ibcon#[26=FRQ=08,884.99\r\n] 2006.146.00:57:43.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:57:43.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:57:43.04#ibcon#about to clear, iclass 7 cls_cnt 0 2006.146.00:57:43.04#ibcon#cleared, iclass 7 cls_cnt 0 2006.146.00:57:43.04$vck44/va=8,4 2006.146.00:57:43.04#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.146.00:57:43.04#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.146.00:57:43.04#ibcon#ireg 11 cls_cnt 2 2006.146.00:57:43.04#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.146.00:57:43.10#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.146.00:57:43.10#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.146.00:57:43.12#ibcon#[25=AT08-04\r\n] 2006.146.00:57:43.15#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.146.00:57:43.15#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.146.00:57:43.15#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.146.00:57:43.15#ibcon#ireg 7 cls_cnt 0 2006.146.00:57:43.15#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.146.00:57:43.27#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.146.00:57:43.27#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.146.00:57:43.29#ibcon#[25=USB\r\n] 2006.146.00:57:43.32#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.146.00:57:43.32#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.146.00:57:43.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.146.00:57:43.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.146.00:57:43.32$vck44/vblo=1,629.99 2006.146.00:57:43.32#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.146.00:57:43.32#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.146.00:57:43.32#ibcon#ireg 17 cls_cnt 0 2006.146.00:57:43.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.146.00:57:43.32#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.146.00:57:43.32#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.146.00:57:43.34#ibcon#[28=FRQ=01,629.99\r\n] 2006.146.00:57:43.38#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.146.00:57:43.38#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.146.00:57:43.38#ibcon#about to clear, iclass 13 cls_cnt 0 2006.146.00:57:43.38#ibcon#cleared, iclass 13 cls_cnt 0 2006.146.00:57:43.38$vck44/vb=1,3 2006.146.00:57:43.38#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.146.00:57:43.38#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.146.00:57:43.38#ibcon#ireg 11 cls_cnt 2 2006.146.00:57:43.38#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.146.00:57:43.38#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.146.00:57:43.38#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.146.00:57:43.40#ibcon#[27=AT01-03\r\n] 2006.146.00:57:43.43#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.146.00:57:43.43#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.146.00:57:43.43#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.146.00:57:43.43#ibcon#ireg 7 cls_cnt 0 2006.146.00:57:43.43#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.146.00:57:43.55#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.146.00:57:43.55#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.146.00:57:43.57#ibcon#[27=USB\r\n] 2006.146.00:57:43.60#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.146.00:57:43.60#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.146.00:57:43.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.146.00:57:43.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.146.00:57:43.60$vck44/vblo=2,634.99 2006.146.00:57:43.60#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.146.00:57:43.60#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.146.00:57:43.60#ibcon#ireg 17 cls_cnt 0 2006.146.00:57:43.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:57:43.60#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:57:43.60#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:57:43.62#ibcon#[28=FRQ=02,634.99\r\n] 2006.146.00:57:43.66#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:57:43.66#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.146.00:57:43.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.146.00:57:43.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.146.00:57:43.66$vck44/vb=2,4 2006.146.00:57:43.66#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.146.00:57:43.66#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.146.00:57:43.66#ibcon#ireg 11 cls_cnt 2 2006.146.00:57:43.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:57:43.72#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:57:43.72#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:57:43.74#ibcon#[27=AT02-04\r\n] 2006.146.00:57:43.77#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:57:43.77#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.146.00:57:43.77#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.146.00:57:43.77#ibcon#ireg 7 cls_cnt 0 2006.146.00:57:43.77#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:57:43.89#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:57:43.89#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:57:43.91#ibcon#[27=USB\r\n] 2006.146.00:57:43.94#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:57:43.94#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.146.00:57:43.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.146.00:57:43.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.146.00:57:43.94$vck44/vblo=3,649.99 2006.146.00:57:43.94#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.146.00:57:43.94#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.146.00:57:43.94#ibcon#ireg 17 cls_cnt 0 2006.146.00:57:43.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:57:43.94#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:57:43.94#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:57:43.96#ibcon#[28=FRQ=03,649.99\r\n] 2006.146.00:57:44.00#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:57:44.00#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.146.00:57:44.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.146.00:57:44.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.146.00:57:44.00$vck44/vb=3,4 2006.146.00:57:44.00#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.146.00:57:44.00#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.146.00:57:44.00#ibcon#ireg 11 cls_cnt 2 2006.146.00:57:44.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:57:44.06#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:57:44.06#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:57:44.08#ibcon#[27=AT03-04\r\n] 2006.146.00:57:44.11#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:57:44.11#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.146.00:57:44.11#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.146.00:57:44.11#ibcon#ireg 7 cls_cnt 0 2006.146.00:57:44.11#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:57:44.23#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:57:44.23#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:57:44.25#ibcon#[27=USB\r\n] 2006.146.00:57:44.28#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:57:44.28#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.146.00:57:44.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.146.00:57:44.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.146.00:57:44.28$vck44/vblo=4,679.99 2006.146.00:57:44.28#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.146.00:57:44.28#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.146.00:57:44.28#ibcon#ireg 17 cls_cnt 0 2006.146.00:57:44.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:57:44.28#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:57:44.28#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:57:44.30#ibcon#[28=FRQ=04,679.99\r\n] 2006.146.00:57:44.34#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:57:44.34#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.146.00:57:44.34#ibcon#about to clear, iclass 25 cls_cnt 0 2006.146.00:57:44.34#ibcon#cleared, iclass 25 cls_cnt 0 2006.146.00:57:44.34$vck44/vb=4,4 2006.146.00:57:44.34#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.146.00:57:44.34#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.146.00:57:44.34#ibcon#ireg 11 cls_cnt 2 2006.146.00:57:44.34#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.146.00:57:44.40#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.146.00:57:44.40#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.146.00:57:44.42#ibcon#[27=AT04-04\r\n] 2006.146.00:57:44.45#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.146.00:57:44.45#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.146.00:57:44.45#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.146.00:57:44.45#ibcon#ireg 7 cls_cnt 0 2006.146.00:57:44.45#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.146.00:57:44.57#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.146.00:57:44.57#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.146.00:57:44.59#ibcon#[27=USB\r\n] 2006.146.00:57:44.62#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.146.00:57:44.62#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.146.00:57:44.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.146.00:57:44.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.146.00:57:44.62$vck44/vblo=5,709.99 2006.146.00:57:44.62#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.146.00:57:44.62#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.146.00:57:44.62#ibcon#ireg 17 cls_cnt 0 2006.146.00:57:44.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:57:44.62#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:57:44.62#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:57:44.64#ibcon#[28=FRQ=05,709.99\r\n] 2006.146.00:57:44.68#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:57:44.68#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.146.00:57:44.68#ibcon#about to clear, iclass 29 cls_cnt 0 2006.146.00:57:44.68#ibcon#cleared, iclass 29 cls_cnt 0 2006.146.00:57:44.68$vck44/vb=5,4 2006.146.00:57:44.68#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.146.00:57:44.68#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.146.00:57:44.68#ibcon#ireg 11 cls_cnt 2 2006.146.00:57:44.68#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.146.00:57:44.74#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.146.00:57:44.74#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.146.00:57:44.76#ibcon#[27=AT05-04\r\n] 2006.146.00:57:44.79#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.146.00:57:44.79#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.146.00:57:44.79#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.146.00:57:44.79#ibcon#ireg 7 cls_cnt 0 2006.146.00:57:44.79#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.146.00:57:44.91#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.146.00:57:44.91#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.146.00:57:44.93#ibcon#[27=USB\r\n] 2006.146.00:57:44.96#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.146.00:57:44.96#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.146.00:57:44.96#ibcon#about to clear, iclass 31 cls_cnt 0 2006.146.00:57:44.96#ibcon#cleared, iclass 31 cls_cnt 0 2006.146.00:57:44.96$vck44/vblo=6,719.99 2006.146.00:57:44.96#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.146.00:57:44.96#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.146.00:57:44.96#ibcon#ireg 17 cls_cnt 0 2006.146.00:57:44.96#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.146.00:57:44.96#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.146.00:57:44.96#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.146.00:57:44.98#ibcon#[28=FRQ=06,719.99\r\n] 2006.146.00:57:45.02#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.146.00:57:45.02#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.146.00:57:45.02#ibcon#about to clear, iclass 33 cls_cnt 0 2006.146.00:57:45.02#ibcon#cleared, iclass 33 cls_cnt 0 2006.146.00:57:45.02$vck44/vb=6,4 2006.146.00:57:45.02#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.146.00:57:45.02#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.146.00:57:45.02#ibcon#ireg 11 cls_cnt 2 2006.146.00:57:45.02#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.146.00:57:45.08#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.146.00:57:45.08#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.146.00:57:45.10#ibcon#[27=AT06-04\r\n] 2006.146.00:57:45.13#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.146.00:57:45.13#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.146.00:57:45.13#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.146.00:57:45.13#ibcon#ireg 7 cls_cnt 0 2006.146.00:57:45.13#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.146.00:57:45.25#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.146.00:57:45.25#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.146.00:57:45.27#ibcon#[27=USB\r\n] 2006.146.00:57:45.30#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.146.00:57:45.30#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.146.00:57:45.30#ibcon#about to clear, iclass 35 cls_cnt 0 2006.146.00:57:45.30#ibcon#cleared, iclass 35 cls_cnt 0 2006.146.00:57:45.30$vck44/vblo=7,734.99 2006.146.00:57:45.30#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.146.00:57:45.30#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.146.00:57:45.30#ibcon#ireg 17 cls_cnt 0 2006.146.00:57:45.30#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:57:45.30#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:57:45.30#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:57:45.32#ibcon#[28=FRQ=07,734.99\r\n] 2006.146.00:57:45.36#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:57:45.36#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.146.00:57:45.36#ibcon#about to clear, iclass 37 cls_cnt 0 2006.146.00:57:45.36#ibcon#cleared, iclass 37 cls_cnt 0 2006.146.00:57:45.36$vck44/vb=7,4 2006.146.00:57:45.36#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.146.00:57:45.36#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.146.00:57:45.36#ibcon#ireg 11 cls_cnt 2 2006.146.00:57:45.36#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:57:45.42#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:57:45.42#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:57:45.44#ibcon#[27=AT07-04\r\n] 2006.146.00:57:45.47#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:57:45.47#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.146.00:57:45.47#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.146.00:57:45.47#ibcon#ireg 7 cls_cnt 0 2006.146.00:57:45.47#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:57:45.59#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:57:45.59#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:57:45.61#ibcon#[27=USB\r\n] 2006.146.00:57:45.64#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:57:45.64#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.146.00:57:45.64#ibcon#about to clear, iclass 39 cls_cnt 0 2006.146.00:57:45.64#ibcon#cleared, iclass 39 cls_cnt 0 2006.146.00:57:45.64$vck44/vblo=8,744.99 2006.146.00:57:45.64#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.146.00:57:45.64#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.146.00:57:45.64#ibcon#ireg 17 cls_cnt 0 2006.146.00:57:45.64#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:57:45.64#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:57:45.64#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:57:45.66#ibcon#[28=FRQ=08,744.99\r\n] 2006.146.00:57:45.70#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:57:45.70#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.146.00:57:45.70#ibcon#about to clear, iclass 3 cls_cnt 0 2006.146.00:57:45.70#ibcon#cleared, iclass 3 cls_cnt 0 2006.146.00:57:45.70$vck44/vb=8,4 2006.146.00:57:45.70#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.146.00:57:45.70#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.146.00:57:45.70#ibcon#ireg 11 cls_cnt 2 2006.146.00:57:45.70#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:57:45.76#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:57:45.76#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:57:45.78#ibcon#[27=AT08-04\r\n] 2006.146.00:57:45.81#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:57:45.81#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.146.00:57:45.81#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.146.00:57:45.81#ibcon#ireg 7 cls_cnt 0 2006.146.00:57:45.81#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:57:45.93#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:57:45.93#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:57:45.95#ibcon#[27=USB\r\n] 2006.146.00:57:45.98#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:57:45.98#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.146.00:57:45.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.146.00:57:45.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.146.00:57:45.98$vck44/vabw=wide 2006.146.00:57:45.98#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.146.00:57:45.98#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.146.00:57:45.98#ibcon#ireg 8 cls_cnt 0 2006.146.00:57:45.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:57:45.98#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:57:45.98#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:57:46.00#ibcon#[25=BW32\r\n] 2006.146.00:57:46.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:57:46.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.146.00:57:46.03#ibcon#about to clear, iclass 7 cls_cnt 0 2006.146.00:57:46.03#ibcon#cleared, iclass 7 cls_cnt 0 2006.146.00:57:46.03$vck44/vbbw=wide 2006.146.00:57:46.03#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.146.00:57:46.03#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.146.00:57:46.03#ibcon#ireg 8 cls_cnt 0 2006.146.00:57:46.03#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.146.00:57:46.10#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.146.00:57:46.10#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.146.00:57:46.12#ibcon#[27=BW32\r\n] 2006.146.00:57:46.15#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.146.00:57:46.15#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.146.00:57:46.15#ibcon#about to clear, iclass 11 cls_cnt 0 2006.146.00:57:46.15#ibcon#cleared, iclass 11 cls_cnt 0 2006.146.00:57:46.15$setupk4/ifdk4 2006.146.00:57:46.15$ifdk4/lo= 2006.146.00:57:46.15$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.146.00:57:46.15$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.146.00:57:46.15$ifdk4/patch= 2006.146.00:57:46.15$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.146.00:57:46.15$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.146.00:57:46.15$setupk4/!*+20s 2006.146.00:57:49.95#abcon#<5=/09 2.0 6.1 21.07 651020.4\r\n> 2006.146.00:57:49.97#abcon#{5=INTERFACE CLEAR} 2006.146.00:57:50.03#abcon#[5=S1D000X0/0*\r\n] 2006.146.00:58:00.14#trakl#Source acquired 2006.146.00:58:00.14#flagr#flagr/antenna,acquired 2006.146.00:58:00.26#abcon#<5=/09 2.0 6.9 21.07 661020.4\r\n> 2006.146.00:58:00.28#abcon#{5=INTERFACE CLEAR} 2006.146.00:58:00.34#abcon#[5=S1D000X0/0*\r\n] 2006.146.00:58:00.64$setupk4/"tpicd 2006.146.00:58:00.64$setupk4/echo=off 2006.146.00:58:00.64$setupk4/xlog=off 2006.146.00:58:00.64:!2006.146.01:00:36 2006.146.01:00:36.00:preob 2006.146.01:00:37.13/onsource/TRACKING 2006.146.01:00:37.13:!2006.146.01:00:46 2006.146.01:00:46.00:"tape 2006.146.01:00:46.00:"st=record 2006.146.01:00:46.00:data_valid=on 2006.146.01:00:46.00:midob 2006.146.01:00:46.13/onsource/TRACKING 2006.146.01:00:46.13/wx/21.03,1020.4,67 2006.146.01:00:46.33/cable/+6.5417E-03 2006.146.01:00:47.42/va/01,08,usb,yes,37,39 2006.146.01:00:47.42/va/02,07,usb,yes,39,40 2006.146.01:00:47.42/va/03,08,usb,yes,36,37 2006.146.01:00:47.42/va/04,07,usb,yes,41,43 2006.146.01:00:47.42/va/05,04,usb,yes,36,37 2006.146.01:00:47.42/va/06,04,usb,yes,40,40 2006.146.01:00:47.42/va/07,04,usb,yes,40,42 2006.146.01:00:47.42/va/08,04,usb,yes,35,41 2006.146.01:00:47.65/valo/01,524.99,yes,locked 2006.146.01:00:47.65/valo/02,534.99,yes,locked 2006.146.01:00:47.65/valo/03,564.99,yes,locked 2006.146.01:00:47.65/valo/04,624.99,yes,locked 2006.146.01:00:47.65/valo/05,734.99,yes,locked 2006.146.01:00:47.65/valo/06,814.99,yes,locked 2006.146.01:00:47.65/valo/07,864.99,yes,locked 2006.146.01:00:47.65/valo/08,884.99,yes,locked 2006.146.01:00:48.74/vb/01,03,usb,yes,41,43 2006.146.01:00:48.74/vb/02,04,usb,yes,36,39 2006.146.01:00:48.74/vb/03,04,usb,yes,33,36 2006.146.01:00:48.74/vb/04,04,usb,yes,37,36 2006.146.01:00:48.74/vb/05,04,usb,yes,30,32 2006.146.01:00:48.74/vb/06,04,usb,yes,35,31 2006.146.01:00:48.74/vb/07,04,usb,yes,34,34 2006.146.01:00:48.74/vb/08,04,usb,yes,32,35 2006.146.01:00:48.97/vblo/01,629.99,yes,locked 2006.146.01:00:48.97/vblo/02,634.99,yes,locked 2006.146.01:00:48.97/vblo/03,649.99,yes,locked 2006.146.01:00:48.97/vblo/04,679.99,yes,locked 2006.146.01:00:48.97/vblo/05,709.99,yes,locked 2006.146.01:00:48.97/vblo/06,719.99,yes,locked 2006.146.01:00:48.97/vblo/07,734.99,yes,locked 2006.146.01:00:48.97/vblo/08,744.99,yes,locked 2006.146.01:00:49.12/vabw/8 2006.146.01:00:49.27/vbbw/8 2006.146.01:00:49.39/xfe/off,on,15.0 2006.146.01:00:49.77/ifatt/23,28,28,28 2006.146.01:00:50.07/fmout-gps/S +4.1E-08 2006.146.01:00:50.15:!2006.146.01:01:26 2006.146.01:01:26.00:data_valid=off 2006.146.01:01:26.00:"et 2006.146.01:01:26.01:!+3s 2006.146.01:01:29.02:"tape 2006.146.01:01:29.02:postob 2006.146.01:01:29.22/cable/+6.5425E-03 2006.146.01:01:29.22/wx/21.01,1020.5,67 2006.146.01:01:29.31/fmout-gps/S +4.0E-08 2006.146.01:01:29.31:scan_name=146-0102,jd0605,250 2006.146.01:01:29.31:source=cta26,033930.94,-014635.8,2000.0,cw 2006.146.01:01:31.14#flagr#flagr/antenna,new-source 2006.146.01:01:31.14:checkk5 2006.146.01:01:31.59/chk_autoobs//k5ts1/ autoobs is running! 2006.146.01:01:32.01/chk_autoobs//k5ts2/ autoobs is running! 2006.146.01:01:32.45/chk_autoobs//k5ts3/ autoobs is running! 2006.146.01:01:32.88/chk_autoobs//k5ts4/ autoobs is running! 2006.146.01:01:33.32/chk_obsdata//k5ts1/T1460100??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.146.01:01:33.76/chk_obsdata//k5ts2/T1460100??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.146.01:01:34.20/chk_obsdata//k5ts3/T1460100??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.146.01:01:34.64/chk_obsdata//k5ts4/T1460100??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.146.01:01:35.38/k5log//k5ts1_log_newline 2006.146.01:01:36.13/k5log//k5ts2_log_newline 2006.146.01:01:36.87/k5log//k5ts3_log_newline 2006.146.01:01:37.61/k5log//k5ts4_log_newline 2006.146.01:01:37.64/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.146.01:01:37.64:setupk4=1 2006.146.01:01:37.64$setupk4/echo=on 2006.146.01:01:37.64$setupk4/pcalon 2006.146.01:01:37.64$pcalon/"no phase cal control is implemented here 2006.146.01:01:37.64$setupk4/"tpicd=stop 2006.146.01:01:37.64$setupk4/"rec=synch_on 2006.146.01:01:37.64$setupk4/"rec_mode=128 2006.146.01:01:37.64$setupk4/!* 2006.146.01:01:37.64$setupk4/recpk4 2006.146.01:01:37.64$recpk4/recpatch= 2006.146.01:01:37.64$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.146.01:01:37.64$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.146.01:01:37.64$setupk4/vck44 2006.146.01:01:37.64$vck44/valo=1,524.99 2006.146.01:01:37.64#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.146.01:01:37.64#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.146.01:01:37.64#ibcon#ireg 17 cls_cnt 0 2006.146.01:01:37.64#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.146.01:01:37.64#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.146.01:01:37.64#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.146.01:01:37.68#ibcon#[26=FRQ=01,524.99\r\n] 2006.146.01:01:37.73#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.146.01:01:37.73#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.146.01:01:37.73#ibcon#about to clear, iclass 36 cls_cnt 0 2006.146.01:01:37.73#ibcon#cleared, iclass 36 cls_cnt 0 2006.146.01:01:37.73$vck44/va=1,8 2006.146.01:01:37.73#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.146.01:01:37.73#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.146.01:01:37.73#ibcon#ireg 11 cls_cnt 2 2006.146.01:01:37.73#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.146.01:01:37.73#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.146.01:01:37.73#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.146.01:01:37.75#ibcon#[25=AT01-08\r\n] 2006.146.01:01:37.78#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.146.01:01:37.78#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.146.01:01:37.78#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.146.01:01:37.78#ibcon#ireg 7 cls_cnt 0 2006.146.01:01:37.78#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.146.01:01:37.90#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.146.01:01:37.90#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.146.01:01:37.92#ibcon#[25=USB\r\n] 2006.146.01:01:37.97#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.146.01:01:37.97#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.146.01:01:37.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.146.01:01:37.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.146.01:01:37.97$vck44/valo=2,534.99 2006.146.01:01:37.97#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.146.01:01:37.97#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.146.01:01:37.97#ibcon#ireg 17 cls_cnt 0 2006.146.01:01:37.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.146.01:01:37.97#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.146.01:01:37.97#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.146.01:01:37.98#ibcon#[26=FRQ=02,534.99\r\n] 2006.146.01:01:38.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.146.01:01:38.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.146.01:01:38.02#ibcon#about to clear, iclass 40 cls_cnt 0 2006.146.01:01:38.02#ibcon#cleared, iclass 40 cls_cnt 0 2006.146.01:01:38.02$vck44/va=2,7 2006.146.01:01:38.02#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.146.01:01:38.02#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.146.01:01:38.02#ibcon#ireg 11 cls_cnt 2 2006.146.01:01:38.02#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.146.01:01:38.09#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.146.01:01:38.09#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.146.01:01:38.11#ibcon#[25=AT02-07\r\n] 2006.146.01:01:38.14#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.146.01:01:38.14#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.146.01:01:38.14#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.146.01:01:38.14#ibcon#ireg 7 cls_cnt 0 2006.146.01:01:38.14#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.146.01:01:38.26#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.146.01:01:38.26#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.146.01:01:38.28#ibcon#[25=USB\r\n] 2006.146.01:01:38.31#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.146.01:01:38.31#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.146.01:01:38.31#ibcon#about to clear, iclass 4 cls_cnt 0 2006.146.01:01:38.31#ibcon#cleared, iclass 4 cls_cnt 0 2006.146.01:01:38.31$vck44/valo=3,564.99 2006.146.01:01:38.31#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.146.01:01:38.31#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.146.01:01:38.31#ibcon#ireg 17 cls_cnt 0 2006.146.01:01:38.31#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.146.01:01:38.31#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.146.01:01:38.31#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.146.01:01:38.33#ibcon#[26=FRQ=03,564.99\r\n] 2006.146.01:01:38.37#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.146.01:01:38.37#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.146.01:01:38.37#ibcon#about to clear, iclass 6 cls_cnt 0 2006.146.01:01:38.37#ibcon#cleared, iclass 6 cls_cnt 0 2006.146.01:01:38.37$vck44/va=3,8 2006.146.01:01:38.37#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.146.01:01:38.37#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.146.01:01:38.37#ibcon#ireg 11 cls_cnt 2 2006.146.01:01:38.37#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.146.01:01:38.43#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.146.01:01:38.43#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.146.01:01:38.45#ibcon#[25=AT03-08\r\n] 2006.146.01:01:38.48#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.146.01:01:38.48#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.146.01:01:38.48#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.146.01:01:38.48#ibcon#ireg 7 cls_cnt 0 2006.146.01:01:38.48#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.146.01:01:38.60#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.146.01:01:38.60#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.146.01:01:38.62#ibcon#[25=USB\r\n] 2006.146.01:01:38.65#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.146.01:01:38.65#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.146.01:01:38.65#ibcon#about to clear, iclass 10 cls_cnt 0 2006.146.01:01:38.65#ibcon#cleared, iclass 10 cls_cnt 0 2006.146.01:01:38.65$vck44/valo=4,624.99 2006.146.01:01:38.65#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.146.01:01:38.65#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.146.01:01:38.65#ibcon#ireg 17 cls_cnt 0 2006.146.01:01:38.65#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.146.01:01:38.65#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.146.01:01:38.65#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.146.01:01:38.67#ibcon#[26=FRQ=04,624.99\r\n] 2006.146.01:01:38.71#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.146.01:01:38.71#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.146.01:01:38.71#ibcon#about to clear, iclass 12 cls_cnt 0 2006.146.01:01:38.71#ibcon#cleared, iclass 12 cls_cnt 0 2006.146.01:01:38.71$vck44/va=4,7 2006.146.01:01:38.71#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.146.01:01:38.71#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.146.01:01:38.71#ibcon#ireg 11 cls_cnt 2 2006.146.01:01:38.71#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.146.01:01:38.77#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.146.01:01:38.77#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.146.01:01:38.79#ibcon#[25=AT04-07\r\n] 2006.146.01:01:38.82#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.146.01:01:38.82#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.146.01:01:38.82#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.146.01:01:38.82#ibcon#ireg 7 cls_cnt 0 2006.146.01:01:38.82#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.146.01:01:38.94#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.146.01:01:38.94#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.146.01:01:38.96#ibcon#[25=USB\r\n] 2006.146.01:01:38.99#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.146.01:01:38.99#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.146.01:01:38.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.146.01:01:38.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.146.01:01:38.99$vck44/valo=5,734.99 2006.146.01:01:38.99#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.146.01:01:38.99#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.146.01:01:38.99#ibcon#ireg 17 cls_cnt 0 2006.146.01:01:38.99#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.146.01:01:38.99#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.146.01:01:38.99#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.146.01:01:39.01#ibcon#[26=FRQ=05,734.99\r\n] 2006.146.01:01:39.05#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.146.01:01:39.05#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.146.01:01:39.05#ibcon#about to clear, iclass 16 cls_cnt 0 2006.146.01:01:39.05#ibcon#cleared, iclass 16 cls_cnt 0 2006.146.01:01:39.05$vck44/va=5,4 2006.146.01:01:39.05#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.146.01:01:39.05#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.146.01:01:39.05#ibcon#ireg 11 cls_cnt 2 2006.146.01:01:39.05#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.146.01:01:39.11#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.146.01:01:39.11#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.146.01:01:39.13#ibcon#[25=AT05-04\r\n] 2006.146.01:01:39.16#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.146.01:01:39.16#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.146.01:01:39.16#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.146.01:01:39.16#ibcon#ireg 7 cls_cnt 0 2006.146.01:01:39.16#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.146.01:01:39.28#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.146.01:01:39.28#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.146.01:01:39.30#ibcon#[25=USB\r\n] 2006.146.01:01:39.33#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.146.01:01:39.33#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.146.01:01:39.33#ibcon#about to clear, iclass 18 cls_cnt 0 2006.146.01:01:39.33#ibcon#cleared, iclass 18 cls_cnt 0 2006.146.01:01:39.33$vck44/valo=6,814.99 2006.146.01:01:39.33#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.146.01:01:39.33#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.146.01:01:39.33#ibcon#ireg 17 cls_cnt 0 2006.146.01:01:39.33#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.146.01:01:39.33#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.146.01:01:39.33#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.146.01:01:39.35#ibcon#[26=FRQ=06,814.99\r\n] 2006.146.01:01:39.39#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.146.01:01:39.39#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.146.01:01:39.39#ibcon#about to clear, iclass 20 cls_cnt 0 2006.146.01:01:39.39#ibcon#cleared, iclass 20 cls_cnt 0 2006.146.01:01:39.39$vck44/va=6,4 2006.146.01:01:39.39#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.146.01:01:39.39#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.146.01:01:39.39#ibcon#ireg 11 cls_cnt 2 2006.146.01:01:39.39#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.146.01:01:39.45#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.146.01:01:39.45#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.146.01:01:39.47#ibcon#[25=AT06-04\r\n] 2006.146.01:01:39.50#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.146.01:01:39.50#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.146.01:01:39.50#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.146.01:01:39.50#ibcon#ireg 7 cls_cnt 0 2006.146.01:01:39.50#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.146.01:01:39.62#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.146.01:01:39.62#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.146.01:01:39.64#ibcon#[25=USB\r\n] 2006.146.01:01:39.67#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.146.01:01:39.67#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.146.01:01:39.67#ibcon#about to clear, iclass 22 cls_cnt 0 2006.146.01:01:39.67#ibcon#cleared, iclass 22 cls_cnt 0 2006.146.01:01:39.67$vck44/valo=7,864.99 2006.146.01:01:39.67#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.146.01:01:39.67#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.146.01:01:39.67#ibcon#ireg 17 cls_cnt 0 2006.146.01:01:39.67#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.146.01:01:39.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.146.01:01:39.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.146.01:01:39.69#ibcon#[26=FRQ=07,864.99\r\n] 2006.146.01:01:39.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.146.01:01:39.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.146.01:01:39.73#ibcon#about to clear, iclass 24 cls_cnt 0 2006.146.01:01:39.73#ibcon#cleared, iclass 24 cls_cnt 0 2006.146.01:01:39.73$vck44/va=7,4 2006.146.01:01:39.73#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.146.01:01:39.73#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.146.01:01:39.73#ibcon#ireg 11 cls_cnt 2 2006.146.01:01:39.73#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.146.01:01:39.79#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.146.01:01:39.79#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.146.01:01:39.81#ibcon#[25=AT07-04\r\n] 2006.146.01:01:39.84#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.146.01:01:39.84#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.146.01:01:39.84#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.146.01:01:39.84#ibcon#ireg 7 cls_cnt 0 2006.146.01:01:39.84#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.146.01:01:39.96#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.146.01:01:39.96#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.146.01:01:39.98#ibcon#[25=USB\r\n] 2006.146.01:01:40.01#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.146.01:01:40.01#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.146.01:01:40.01#ibcon#about to clear, iclass 26 cls_cnt 0 2006.146.01:01:40.01#ibcon#cleared, iclass 26 cls_cnt 0 2006.146.01:01:40.01$vck44/valo=8,884.99 2006.146.01:01:40.01#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.146.01:01:40.01#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.146.01:01:40.01#ibcon#ireg 17 cls_cnt 0 2006.146.01:01:40.01#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.146.01:01:40.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.146.01:01:40.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.146.01:01:40.03#ibcon#[26=FRQ=08,884.99\r\n] 2006.146.01:01:40.07#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.146.01:01:40.07#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.146.01:01:40.07#ibcon#about to clear, iclass 28 cls_cnt 0 2006.146.01:01:40.07#ibcon#cleared, iclass 28 cls_cnt 0 2006.146.01:01:40.07$vck44/va=8,4 2006.146.01:01:40.07#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.146.01:01:40.07#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.146.01:01:40.07#ibcon#ireg 11 cls_cnt 2 2006.146.01:01:40.07#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.146.01:01:40.13#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.146.01:01:40.13#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.146.01:01:40.15#ibcon#[25=AT08-04\r\n] 2006.146.01:01:40.18#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.146.01:01:40.18#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.146.01:01:40.18#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.146.01:01:40.18#ibcon#ireg 7 cls_cnt 0 2006.146.01:01:40.18#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.146.01:01:40.30#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.146.01:01:40.30#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.146.01:01:40.32#ibcon#[25=USB\r\n] 2006.146.01:01:40.35#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.146.01:01:40.35#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.146.01:01:40.35#ibcon#about to clear, iclass 30 cls_cnt 0 2006.146.01:01:40.35#ibcon#cleared, iclass 30 cls_cnt 0 2006.146.01:01:40.35$vck44/vblo=1,629.99 2006.146.01:01:40.35#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.146.01:01:40.35#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.146.01:01:40.35#ibcon#ireg 17 cls_cnt 0 2006.146.01:01:40.35#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.146.01:01:40.35#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.146.01:01:40.35#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.146.01:01:40.37#ibcon#[28=FRQ=01,629.99\r\n] 2006.146.01:01:40.41#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.146.01:01:40.41#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.146.01:01:40.41#ibcon#about to clear, iclass 32 cls_cnt 0 2006.146.01:01:40.41#ibcon#cleared, iclass 32 cls_cnt 0 2006.146.01:01:40.41$vck44/vb=1,3 2006.146.01:01:40.41#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.146.01:01:40.41#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.146.01:01:40.41#ibcon#ireg 11 cls_cnt 2 2006.146.01:01:40.41#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.146.01:01:40.41#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.146.01:01:40.41#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.146.01:01:40.43#ibcon#[27=AT01-03\r\n] 2006.146.01:01:40.46#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.146.01:01:40.46#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.146.01:01:40.46#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.146.01:01:40.46#ibcon#ireg 7 cls_cnt 0 2006.146.01:01:40.46#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.146.01:01:40.58#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.146.01:01:40.58#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.146.01:01:40.60#ibcon#[27=USB\r\n] 2006.146.01:01:40.63#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.146.01:01:40.63#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.146.01:01:40.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.146.01:01:40.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.146.01:01:40.63$vck44/vblo=2,634.99 2006.146.01:01:40.63#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.146.01:01:40.63#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.146.01:01:40.63#ibcon#ireg 17 cls_cnt 0 2006.146.01:01:40.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.146.01:01:40.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.146.01:01:40.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.146.01:01:40.65#ibcon#[28=FRQ=02,634.99\r\n] 2006.146.01:01:40.69#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.146.01:01:40.69#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.146.01:01:40.69#ibcon#about to clear, iclass 36 cls_cnt 0 2006.146.01:01:40.69#ibcon#cleared, iclass 36 cls_cnt 0 2006.146.01:01:40.69$vck44/vb=2,4 2006.146.01:01:40.69#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.146.01:01:40.69#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.146.01:01:40.69#ibcon#ireg 11 cls_cnt 2 2006.146.01:01:40.69#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.146.01:01:40.75#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.146.01:01:40.75#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.146.01:01:40.77#ibcon#[27=AT02-04\r\n] 2006.146.01:01:40.80#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.146.01:01:40.80#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.146.01:01:40.80#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.146.01:01:40.80#ibcon#ireg 7 cls_cnt 0 2006.146.01:01:40.80#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.146.01:01:40.92#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.146.01:01:40.92#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.146.01:01:40.94#ibcon#[27=USB\r\n] 2006.146.01:01:40.97#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.146.01:01:40.97#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.146.01:01:40.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.146.01:01:40.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.146.01:01:40.97$vck44/vblo=3,649.99 2006.146.01:01:40.97#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.146.01:01:40.97#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.146.01:01:40.97#ibcon#ireg 17 cls_cnt 0 2006.146.01:01:40.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.146.01:01:40.97#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.146.01:01:40.97#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.146.01:01:40.99#ibcon#[28=FRQ=03,649.99\r\n] 2006.146.01:01:41.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.146.01:01:41.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.146.01:01:41.03#ibcon#about to clear, iclass 40 cls_cnt 0 2006.146.01:01:41.03#ibcon#cleared, iclass 40 cls_cnt 0 2006.146.01:01:41.03$vck44/vb=3,4 2006.146.01:01:41.03#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.146.01:01:41.03#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.146.01:01:41.03#ibcon#ireg 11 cls_cnt 2 2006.146.01:01:41.03#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.146.01:01:41.09#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.146.01:01:41.09#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.146.01:01:41.11#ibcon#[27=AT03-04\r\n] 2006.146.01:01:41.14#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.146.01:01:41.14#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.146.01:01:41.14#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.146.01:01:41.14#ibcon#ireg 7 cls_cnt 0 2006.146.01:01:41.14#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.146.01:01:41.26#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.146.01:01:41.26#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.146.01:01:41.28#ibcon#[27=USB\r\n] 2006.146.01:01:41.31#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.146.01:01:41.31#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.146.01:01:41.31#ibcon#about to clear, iclass 4 cls_cnt 0 2006.146.01:01:41.31#ibcon#cleared, iclass 4 cls_cnt 0 2006.146.01:01:41.31$vck44/vblo=4,679.99 2006.146.01:01:41.31#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.146.01:01:41.31#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.146.01:01:41.31#ibcon#ireg 17 cls_cnt 0 2006.146.01:01:41.31#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.146.01:01:41.31#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.146.01:01:41.31#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.146.01:01:41.33#ibcon#[28=FRQ=04,679.99\r\n] 2006.146.01:01:41.37#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.146.01:01:41.37#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.146.01:01:41.37#ibcon#about to clear, iclass 6 cls_cnt 0 2006.146.01:01:41.37#ibcon#cleared, iclass 6 cls_cnt 0 2006.146.01:01:41.37$vck44/vb=4,4 2006.146.01:01:41.37#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.146.01:01:41.37#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.146.01:01:41.37#ibcon#ireg 11 cls_cnt 2 2006.146.01:01:41.37#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.146.01:01:41.43#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.146.01:01:41.43#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.146.01:01:41.45#ibcon#[27=AT04-04\r\n] 2006.146.01:01:41.48#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.146.01:01:41.48#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.146.01:01:41.48#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.146.01:01:41.48#ibcon#ireg 7 cls_cnt 0 2006.146.01:01:41.48#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.146.01:01:41.60#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.146.01:01:41.60#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.146.01:01:41.62#ibcon#[27=USB\r\n] 2006.146.01:01:41.65#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.146.01:01:41.65#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.146.01:01:41.65#ibcon#about to clear, iclass 10 cls_cnt 0 2006.146.01:01:41.65#ibcon#cleared, iclass 10 cls_cnt 0 2006.146.01:01:41.65$vck44/vblo=5,709.99 2006.146.01:01:41.65#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.146.01:01:41.65#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.146.01:01:41.65#ibcon#ireg 17 cls_cnt 0 2006.146.01:01:41.65#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.146.01:01:41.65#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.146.01:01:41.65#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.146.01:01:41.67#ibcon#[28=FRQ=05,709.99\r\n] 2006.146.01:01:41.71#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.146.01:01:41.71#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.146.01:01:41.71#ibcon#about to clear, iclass 12 cls_cnt 0 2006.146.01:01:41.71#ibcon#cleared, iclass 12 cls_cnt 0 2006.146.01:01:41.71$vck44/vb=5,4 2006.146.01:01:41.71#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.146.01:01:41.71#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.146.01:01:41.71#ibcon#ireg 11 cls_cnt 2 2006.146.01:01:41.71#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.146.01:01:41.77#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.146.01:01:41.77#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.146.01:01:41.79#ibcon#[27=AT05-04\r\n] 2006.146.01:01:41.82#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.146.01:01:41.82#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.146.01:01:41.82#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.146.01:01:41.82#ibcon#ireg 7 cls_cnt 0 2006.146.01:01:41.82#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.146.01:01:41.94#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.146.01:01:41.94#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.146.01:01:41.96#ibcon#[27=USB\r\n] 2006.146.01:01:41.99#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.146.01:01:41.99#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.146.01:01:41.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.146.01:01:41.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.146.01:01:41.99$vck44/vblo=6,719.99 2006.146.01:01:41.99#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.146.01:01:41.99#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.146.01:01:41.99#ibcon#ireg 17 cls_cnt 0 2006.146.01:01:41.99#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.146.01:01:41.99#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.146.01:01:41.99#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.146.01:01:42.01#ibcon#[28=FRQ=06,719.99\r\n] 2006.146.01:01:42.05#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.146.01:01:42.05#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.146.01:01:42.05#ibcon#about to clear, iclass 16 cls_cnt 0 2006.146.01:01:42.05#ibcon#cleared, iclass 16 cls_cnt 0 2006.146.01:01:42.05$vck44/vb=6,4 2006.146.01:01:42.05#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.146.01:01:42.05#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.146.01:01:42.05#ibcon#ireg 11 cls_cnt 2 2006.146.01:01:42.05#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.146.01:01:42.11#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.146.01:01:42.11#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.146.01:01:42.13#ibcon#[27=AT06-04\r\n] 2006.146.01:01:42.16#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.146.01:01:42.16#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.146.01:01:42.16#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.146.01:01:42.16#ibcon#ireg 7 cls_cnt 0 2006.146.01:01:42.16#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.146.01:01:42.28#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.146.01:01:42.28#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.146.01:01:42.30#ibcon#[27=USB\r\n] 2006.146.01:01:42.33#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.146.01:01:42.33#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.146.01:01:42.33#ibcon#about to clear, iclass 18 cls_cnt 0 2006.146.01:01:42.33#ibcon#cleared, iclass 18 cls_cnt 0 2006.146.01:01:42.33$vck44/vblo=7,734.99 2006.146.01:01:42.33#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.146.01:01:42.33#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.146.01:01:42.33#ibcon#ireg 17 cls_cnt 0 2006.146.01:01:42.33#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.146.01:01:42.33#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.146.01:01:42.33#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.146.01:01:42.35#ibcon#[28=FRQ=07,734.99\r\n] 2006.146.01:01:42.39#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.146.01:01:42.39#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.146.01:01:42.39#ibcon#about to clear, iclass 20 cls_cnt 0 2006.146.01:01:42.39#ibcon#cleared, iclass 20 cls_cnt 0 2006.146.01:01:42.39$vck44/vb=7,4 2006.146.01:01:42.39#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.146.01:01:42.39#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.146.01:01:42.39#ibcon#ireg 11 cls_cnt 2 2006.146.01:01:42.39#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.146.01:01:42.45#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.146.01:01:42.45#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.146.01:01:42.47#ibcon#[27=AT07-04\r\n] 2006.146.01:01:42.50#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.146.01:01:42.50#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.146.01:01:42.50#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.146.01:01:42.50#ibcon#ireg 7 cls_cnt 0 2006.146.01:01:42.50#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.146.01:01:42.62#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.146.01:01:42.62#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.146.01:01:42.64#ibcon#[27=USB\r\n] 2006.146.01:01:42.67#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.146.01:01:42.67#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.146.01:01:42.67#ibcon#about to clear, iclass 22 cls_cnt 0 2006.146.01:01:42.67#ibcon#cleared, iclass 22 cls_cnt 0 2006.146.01:01:42.67$vck44/vblo=8,744.99 2006.146.01:01:42.67#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.146.01:01:42.67#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.146.01:01:42.67#ibcon#ireg 17 cls_cnt 0 2006.146.01:01:42.67#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.146.01:01:42.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.146.01:01:42.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.146.01:01:42.69#ibcon#[28=FRQ=08,744.99\r\n] 2006.146.01:01:42.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.146.01:01:42.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.146.01:01:42.73#ibcon#about to clear, iclass 24 cls_cnt 0 2006.146.01:01:42.73#ibcon#cleared, iclass 24 cls_cnt 0 2006.146.01:01:42.73$vck44/vb=8,4 2006.146.01:01:42.73#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.146.01:01:42.73#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.146.01:01:42.73#ibcon#ireg 11 cls_cnt 2 2006.146.01:01:42.73#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.146.01:01:42.79#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.146.01:01:42.79#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.146.01:01:42.81#ibcon#[27=AT08-04\r\n] 2006.146.01:01:42.84#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.146.01:01:42.84#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.146.01:01:42.84#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.146.01:01:42.84#ibcon#ireg 7 cls_cnt 0 2006.146.01:01:42.84#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.146.01:01:42.96#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.146.01:01:42.96#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.146.01:01:42.98#ibcon#[27=USB\r\n] 2006.146.01:01:43.01#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.146.01:01:43.01#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.146.01:01:43.01#ibcon#about to clear, iclass 26 cls_cnt 0 2006.146.01:01:43.01#ibcon#cleared, iclass 26 cls_cnt 0 2006.146.01:01:43.01$vck44/vabw=wide 2006.146.01:01:43.01#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.146.01:01:43.01#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.146.01:01:43.01#ibcon#ireg 8 cls_cnt 0 2006.146.01:01:43.01#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.146.01:01:43.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.146.01:01:43.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.146.01:01:43.03#ibcon#[25=BW32\r\n] 2006.146.01:01:43.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.146.01:01:43.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.146.01:01:43.06#ibcon#about to clear, iclass 28 cls_cnt 0 2006.146.01:01:43.06#ibcon#cleared, iclass 28 cls_cnt 0 2006.146.01:01:43.06$vck44/vbbw=wide 2006.146.01:01:43.06#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.146.01:01:43.06#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.146.01:01:43.06#ibcon#ireg 8 cls_cnt 0 2006.146.01:01:43.06#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.146.01:01:43.13#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.146.01:01:43.13#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.146.01:01:43.15#ibcon#[27=BW32\r\n] 2006.146.01:01:43.18#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.146.01:01:43.18#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.146.01:01:43.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.146.01:01:43.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.146.01:01:43.18$setupk4/ifdk4 2006.146.01:01:43.18$ifdk4/lo= 2006.146.01:01:43.18$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.146.01:01:43.18$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.146.01:01:43.18$ifdk4/patch= 2006.146.01:01:43.18$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.146.01:01:43.18$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.146.01:01:43.18$setupk4/!*+20s 2006.146.01:01:44.00#abcon#<5=/09 2.0 6.9 21.00 681020.5\r\n> 2006.146.01:01:44.02#abcon#{5=INTERFACE CLEAR} 2006.146.01:01:44.08#abcon#[5=S1D000X0/0*\r\n] 2006.146.01:01:54.17#abcon#<5=/09 2.0 6.9 21.00 671020.5\r\n> 2006.146.01:01:54.19#abcon#{5=INTERFACE CLEAR} 2006.146.01:01:54.25#abcon#[5=S1D000X0/0*\r\n] 2006.146.01:01:57.14#trakl#Source acquired 2006.146.01:01:57.65$setupk4/"tpicd 2006.146.01:01:57.65$setupk4/echo=off 2006.146.01:01:57.65$setupk4/xlog=off 2006.146.01:01:57.65:!2006.146.01:01:56 2006.146.01:01:57.65:preob 2006.146.01:01:58.14/onsource/TRACKING 2006.146.01:01:58.14:!2006.146.01:02:06 2006.146.01:01:59.14#flagr#flagr/antenna,acquired 2006.146.01:02:06.00:"tape 2006.146.01:02:06.00:"st=record 2006.146.01:02:06.00:data_valid=on 2006.146.01:02:06.00:midob 2006.146.01:02:07.14/onsource/TRACKING 2006.146.01:02:07.14/wx/21.00,1020.5,66 2006.146.01:02:07.32/cable/+6.5419E-03 2006.146.01:02:08.41/va/01,08,usb,yes,28,30 2006.146.01:02:08.41/va/02,07,usb,yes,30,31 2006.146.01:02:08.41/va/03,08,usb,yes,27,29 2006.146.01:02:08.41/va/04,07,usb,yes,31,33 2006.146.01:02:08.41/va/05,04,usb,yes,27,28 2006.146.01:02:08.41/va/06,04,usb,yes,31,30 2006.146.01:02:08.41/va/07,04,usb,yes,31,32 2006.146.01:02:08.41/va/08,04,usb,yes,26,32 2006.146.01:02:08.64/valo/01,524.99,yes,locked 2006.146.01:02:08.64/valo/02,534.99,yes,locked 2006.146.01:02:08.64/valo/03,564.99,yes,locked 2006.146.01:02:08.64/valo/04,624.99,yes,locked 2006.146.01:02:08.64/valo/05,734.99,yes,locked 2006.146.01:02:08.64/valo/06,814.99,yes,locked 2006.146.01:02:08.64/valo/07,864.99,yes,locked 2006.146.01:02:08.64/valo/08,884.99,yes,locked 2006.146.01:02:09.73/vb/01,03,usb,yes,36,33 2006.146.01:02:09.73/vb/02,04,usb,yes,31,31 2006.146.01:02:09.73/vb/03,04,usb,yes,28,31 2006.146.01:02:09.73/vb/04,04,usb,yes,32,31 2006.146.01:02:09.73/vb/05,04,usb,yes,25,27 2006.146.01:02:09.73/vb/06,04,usb,yes,29,26 2006.146.01:02:09.73/vb/07,04,usb,yes,29,29 2006.146.01:02:09.73/vb/08,04,usb,yes,27,30 2006.146.01:02:09.96/vblo/01,629.99,yes,locked 2006.146.01:02:09.96/vblo/02,634.99,yes,locked 2006.146.01:02:09.96/vblo/03,649.99,yes,locked 2006.146.01:02:09.96/vblo/04,679.99,yes,locked 2006.146.01:02:09.96/vblo/05,709.99,yes,locked 2006.146.01:02:09.96/vblo/06,719.99,yes,locked 2006.146.01:02:09.96/vblo/07,734.99,yes,locked 2006.146.01:02:09.96/vblo/08,744.99,yes,locked 2006.146.01:02:10.11/vabw/8 2006.146.01:02:10.26/vbbw/8 2006.146.01:02:10.37/xfe/off,on,15.2 2006.146.01:02:10.74/ifatt/23,28,28,28 2006.146.01:02:11.07/fmout-gps/S +4.0E-08 2006.146.01:02:11.15:!2006.146.01:06:16 2006.146.01:06:16.00:data_valid=off 2006.146.01:06:16.00:"et 2006.146.01:06:16.00:!+3s 2006.146.01:06:19.02:"tape 2006.146.01:06:19.02:postob 2006.146.01:06:19.09/cable/+6.5439E-03 2006.146.01:06:19.09/wx/20.89,1020.4,68 2006.146.01:06:20.08/fmout-gps/S +4.0E-08 2006.146.01:06:20.08:scan_name=146-0115,jd0605,784 2006.146.01:06:20.08:source=0458-020,050112.81,-015914.3,2000.0,cw 2006.146.01:06:21.14#flagr#flagr/antenna,new-source 2006.146.01:06:21.14:checkk5 2006.146.01:06:21.60/chk_autoobs//k5ts1/ autoobs is running! 2006.146.01:06:22.02/chk_autoobs//k5ts2/ autoobs is running! 2006.146.01:06:22.47/chk_autoobs//k5ts3/ autoobs is running! 2006.146.01:06:22.90/chk_autoobs//k5ts4/ autoobs is running! 2006.146.01:06:23.32/chk_obsdata//k5ts1/T1460102??a.dat file size is correct (nominal:1000MB, actual:996MB). 2006.146.01:06:23.76/chk_obsdata//k5ts2/T1460102??b.dat file size is correct (nominal:1000MB, actual:996MB). 2006.146.01:06:24.18/chk_obsdata//k5ts3/T1460102??c.dat file size is correct (nominal:1000MB, actual:996MB). 2006.146.01:06:24.64/chk_obsdata//k5ts4/T1460102??d.dat file size is correct (nominal:1000MB, actual:996MB). 2006.146.01:06:25.39/k5log//k5ts1_log_newline 2006.146.01:06:26.14/k5log//k5ts2_log_newline 2006.146.01:06:26.87/k5log//k5ts3_log_newline 2006.146.01:06:27.60/k5log//k5ts4_log_newline 2006.146.01:06:27.63/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.146.01:06:27.63:setupk4=1 2006.146.01:06:27.63$setupk4/echo=on 2006.146.01:06:27.63$setupk4/pcalon 2006.146.01:06:27.63$pcalon/"no phase cal control is implemented here 2006.146.01:06:27.63$setupk4/"tpicd=stop 2006.146.01:06:27.63$setupk4/"rec=synch_on 2006.146.01:06:27.63$setupk4/"rec_mode=128 2006.146.01:06:27.63$setupk4/!* 2006.146.01:06:27.63$setupk4/recpk4 2006.146.01:06:27.63$recpk4/recpatch= 2006.146.01:06:27.63$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.146.01:06:27.63$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.146.01:06:27.63$setupk4/vck44 2006.146.01:06:27.63$vck44/valo=1,524.99 2006.146.01:06:27.63#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.146.01:06:27.63#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.146.01:06:27.63#ibcon#ireg 17 cls_cnt 0 2006.146.01:06:27.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.146.01:06:27.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.146.01:06:27.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.146.01:06:27.65#ibcon#[26=FRQ=01,524.99\r\n] 2006.146.01:06:27.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.146.01:06:27.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.146.01:06:27.70#ibcon#about to clear, iclass 39 cls_cnt 0 2006.146.01:06:27.70#ibcon#cleared, iclass 39 cls_cnt 0 2006.146.01:06:27.70$vck44/va=1,8 2006.146.01:06:27.70#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.146.01:06:27.70#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.146.01:06:27.70#ibcon#ireg 11 cls_cnt 2 2006.146.01:06:27.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.146.01:06:27.70#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.146.01:06:27.70#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.146.01:06:27.72#ibcon#[25=AT01-08\r\n] 2006.146.01:06:27.75#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.146.01:06:27.75#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.146.01:06:27.75#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.146.01:06:27.75#ibcon#ireg 7 cls_cnt 0 2006.146.01:06:27.75#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.146.01:06:27.87#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.146.01:06:27.87#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.146.01:06:27.89#ibcon#[25=USB\r\n] 2006.146.01:06:27.93#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.146.01:06:27.93#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.146.01:06:27.93#ibcon#about to clear, iclass 3 cls_cnt 0 2006.146.01:06:27.93#ibcon#cleared, iclass 3 cls_cnt 0 2006.146.01:06:27.94$vck44/valo=2,534.99 2006.146.01:06:27.94#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.146.01:06:27.94#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.146.01:06:27.94#ibcon#ireg 17 cls_cnt 0 2006.146.01:06:27.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.146.01:06:27.94#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.146.01:06:27.94#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.146.01:06:27.95#ibcon#[26=FRQ=02,534.99\r\n] 2006.146.01:06:27.99#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.146.01:06:27.99#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.146.01:06:27.99#ibcon#about to clear, iclass 5 cls_cnt 0 2006.146.01:06:27.99#ibcon#cleared, iclass 5 cls_cnt 0 2006.146.01:06:27.99$vck44/va=2,7 2006.146.01:06:27.99#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.146.01:06:27.99#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.146.01:06:27.99#ibcon#ireg 11 cls_cnt 2 2006.146.01:06:27.99#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.146.01:06:28.05#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.146.01:06:28.05#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.146.01:06:28.07#ibcon#[25=AT02-07\r\n] 2006.146.01:06:28.10#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.146.01:06:28.10#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.146.01:06:28.10#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.146.01:06:28.10#ibcon#ireg 7 cls_cnt 0 2006.146.01:06:28.10#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.146.01:06:28.22#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.146.01:06:28.22#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.146.01:06:28.24#ibcon#[25=USB\r\n] 2006.146.01:06:28.27#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.146.01:06:28.27#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.146.01:06:28.27#ibcon#about to clear, iclass 7 cls_cnt 0 2006.146.01:06:28.27#ibcon#cleared, iclass 7 cls_cnt 0 2006.146.01:06:28.27$vck44/valo=3,564.99 2006.146.01:06:28.27#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.146.01:06:28.27#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.146.01:06:28.27#ibcon#ireg 17 cls_cnt 0 2006.146.01:06:28.27#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.146.01:06:28.27#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.146.01:06:28.27#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.146.01:06:28.29#ibcon#[26=FRQ=03,564.99\r\n] 2006.146.01:06:28.33#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.146.01:06:28.33#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.146.01:06:28.33#ibcon#about to clear, iclass 11 cls_cnt 0 2006.146.01:06:28.33#ibcon#cleared, iclass 11 cls_cnt 0 2006.146.01:06:28.33$vck44/va=3,8 2006.146.01:06:28.33#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.146.01:06:28.33#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.146.01:06:28.33#ibcon#ireg 11 cls_cnt 2 2006.146.01:06:28.33#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.146.01:06:28.39#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.146.01:06:28.39#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.146.01:06:28.41#ibcon#[25=AT03-08\r\n] 2006.146.01:06:28.44#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.146.01:06:28.44#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.146.01:06:28.44#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.146.01:06:28.44#ibcon#ireg 7 cls_cnt 0 2006.146.01:06:28.44#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.146.01:06:28.56#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.146.01:06:28.56#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.146.01:06:28.58#ibcon#[25=USB\r\n] 2006.146.01:06:28.61#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.146.01:06:28.61#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.146.01:06:28.61#ibcon#about to clear, iclass 13 cls_cnt 0 2006.146.01:06:28.61#ibcon#cleared, iclass 13 cls_cnt 0 2006.146.01:06:28.61$vck44/valo=4,624.99 2006.146.01:06:28.61#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.146.01:06:28.61#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.146.01:06:28.61#ibcon#ireg 17 cls_cnt 0 2006.146.01:06:28.61#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.146.01:06:28.61#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.146.01:06:28.61#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.146.01:06:28.63#ibcon#[26=FRQ=04,624.99\r\n] 2006.146.01:06:28.67#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.146.01:06:28.67#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.146.01:06:28.67#ibcon#about to clear, iclass 15 cls_cnt 0 2006.146.01:06:28.67#ibcon#cleared, iclass 15 cls_cnt 0 2006.146.01:06:28.67$vck44/va=4,7 2006.146.01:06:28.67#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.146.01:06:28.67#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.146.01:06:28.67#ibcon#ireg 11 cls_cnt 2 2006.146.01:06:28.67#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.146.01:06:28.73#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.146.01:06:28.73#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.146.01:06:28.75#ibcon#[25=AT04-07\r\n] 2006.146.01:06:28.76#abcon#<5=/09 2.1 6.9 20.89 671020.4\r\n> 2006.146.01:06:28.78#abcon#{5=INTERFACE CLEAR} 2006.146.01:06:28.78#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.146.01:06:28.78#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.146.01:06:28.78#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.146.01:06:28.78#ibcon#ireg 7 cls_cnt 0 2006.146.01:06:28.78#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.146.01:06:28.84#abcon#[5=S1D000X0/0*\r\n] 2006.146.01:06:28.90#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.146.01:06:28.90#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.146.01:06:28.92#ibcon#[25=USB\r\n] 2006.146.01:06:28.95#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.146.01:06:28.95#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.146.01:06:28.95#ibcon#about to clear, iclass 17 cls_cnt 0 2006.146.01:06:28.95#ibcon#cleared, iclass 17 cls_cnt 0 2006.146.01:06:28.95$vck44/valo=5,734.99 2006.146.01:06:28.95#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.146.01:06:28.95#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.146.01:06:28.95#ibcon#ireg 17 cls_cnt 0 2006.146.01:06:28.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.146.01:06:28.95#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.146.01:06:28.95#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.146.01:06:28.97#ibcon#[26=FRQ=05,734.99\r\n] 2006.146.01:06:29.01#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.146.01:06:29.01#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.146.01:06:29.01#ibcon#about to clear, iclass 23 cls_cnt 0 2006.146.01:06:29.01#ibcon#cleared, iclass 23 cls_cnt 0 2006.146.01:06:29.01$vck44/va=5,4 2006.146.01:06:29.01#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.146.01:06:29.01#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.146.01:06:29.01#ibcon#ireg 11 cls_cnt 2 2006.146.01:06:29.01#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.146.01:06:29.08#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.146.01:06:29.08#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.146.01:06:29.10#ibcon#[25=AT05-04\r\n] 2006.146.01:06:29.13#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.146.01:06:29.13#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.146.01:06:29.13#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.146.01:06:29.13#ibcon#ireg 7 cls_cnt 0 2006.146.01:06:29.13#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.146.01:06:29.25#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.146.01:06:29.25#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.146.01:06:29.27#ibcon#[25=USB\r\n] 2006.146.01:06:29.31#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.146.01:06:29.31#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.146.01:06:29.31#ibcon#about to clear, iclass 25 cls_cnt 0 2006.146.01:06:29.31#ibcon#cleared, iclass 25 cls_cnt 0 2006.146.01:06:29.31$vck44/valo=6,814.99 2006.146.01:06:29.31#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.146.01:06:29.31#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.146.01:06:29.31#ibcon#ireg 17 cls_cnt 0 2006.146.01:06:29.31#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.146.01:06:29.31#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.146.01:06:29.31#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.146.01:06:29.33#ibcon#[26=FRQ=06,814.99\r\n] 2006.146.01:06:29.37#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.146.01:06:29.37#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.146.01:06:29.37#ibcon#about to clear, iclass 27 cls_cnt 0 2006.146.01:06:29.37#ibcon#cleared, iclass 27 cls_cnt 0 2006.146.01:06:29.37$vck44/va=6,4 2006.146.01:06:29.37#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.146.01:06:29.37#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.146.01:06:29.37#ibcon#ireg 11 cls_cnt 2 2006.146.01:06:29.37#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.146.01:06:29.43#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.146.01:06:29.43#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.146.01:06:29.45#ibcon#[25=AT06-04\r\n] 2006.146.01:06:29.48#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.146.01:06:29.48#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.146.01:06:29.48#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.146.01:06:29.48#ibcon#ireg 7 cls_cnt 0 2006.146.01:06:29.48#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.146.01:06:29.60#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.146.01:06:29.60#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.146.01:06:29.62#ibcon#[25=USB\r\n] 2006.146.01:06:29.65#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.146.01:06:29.65#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.146.01:06:29.65#ibcon#about to clear, iclass 29 cls_cnt 0 2006.146.01:06:29.65#ibcon#cleared, iclass 29 cls_cnt 0 2006.146.01:06:29.65$vck44/valo=7,864.99 2006.146.01:06:29.65#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.146.01:06:29.65#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.146.01:06:29.65#ibcon#ireg 17 cls_cnt 0 2006.146.01:06:29.65#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.146.01:06:29.65#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.146.01:06:29.65#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.146.01:06:29.67#ibcon#[26=FRQ=07,864.99\r\n] 2006.146.01:06:29.71#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.146.01:06:29.71#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.146.01:06:29.71#ibcon#about to clear, iclass 31 cls_cnt 0 2006.146.01:06:29.71#ibcon#cleared, iclass 31 cls_cnt 0 2006.146.01:06:29.71$vck44/va=7,4 2006.146.01:06:29.71#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.146.01:06:29.71#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.146.01:06:29.71#ibcon#ireg 11 cls_cnt 2 2006.146.01:06:29.71#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.146.01:06:29.77#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.146.01:06:29.77#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.146.01:06:29.79#ibcon#[25=AT07-04\r\n] 2006.146.01:06:29.82#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.146.01:06:29.82#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.146.01:06:29.82#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.146.01:06:29.82#ibcon#ireg 7 cls_cnt 0 2006.146.01:06:29.82#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.146.01:06:29.94#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.146.01:06:29.94#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.146.01:06:29.96#ibcon#[25=USB\r\n] 2006.146.01:06:29.99#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.146.01:06:29.99#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.146.01:06:29.99#ibcon#about to clear, iclass 33 cls_cnt 0 2006.146.01:06:29.99#ibcon#cleared, iclass 33 cls_cnt 0 2006.146.01:06:29.99$vck44/valo=8,884.99 2006.146.01:06:29.99#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.146.01:06:29.99#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.146.01:06:29.99#ibcon#ireg 17 cls_cnt 0 2006.146.01:06:29.99#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.146.01:06:29.99#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.146.01:06:29.99#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.146.01:06:30.01#ibcon#[26=FRQ=08,884.99\r\n] 2006.146.01:06:30.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.146.01:06:30.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.146.01:06:30.05#ibcon#about to clear, iclass 35 cls_cnt 0 2006.146.01:06:30.05#ibcon#cleared, iclass 35 cls_cnt 0 2006.146.01:06:30.05$vck44/va=8,4 2006.146.01:06:30.05#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.146.01:06:30.05#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.146.01:06:30.05#ibcon#ireg 11 cls_cnt 2 2006.146.01:06:30.05#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.146.01:06:30.11#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.146.01:06:30.11#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.146.01:06:30.13#ibcon#[25=AT08-04\r\n] 2006.146.01:06:30.16#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.146.01:06:30.16#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.146.01:06:30.16#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.146.01:06:30.16#ibcon#ireg 7 cls_cnt 0 2006.146.01:06:30.16#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.146.01:06:30.28#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.146.01:06:30.28#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.146.01:06:30.30#ibcon#[25=USB\r\n] 2006.146.01:06:30.33#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.146.01:06:30.33#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.146.01:06:30.33#ibcon#about to clear, iclass 37 cls_cnt 0 2006.146.01:06:30.33#ibcon#cleared, iclass 37 cls_cnt 0 2006.146.01:06:30.33$vck44/vblo=1,629.99 2006.146.01:06:30.33#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.146.01:06:30.33#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.146.01:06:30.33#ibcon#ireg 17 cls_cnt 0 2006.146.01:06:30.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.146.01:06:30.33#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.146.01:06:30.33#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.146.01:06:30.35#ibcon#[28=FRQ=01,629.99\r\n] 2006.146.01:06:30.39#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.146.01:06:30.39#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.146.01:06:30.39#ibcon#about to clear, iclass 39 cls_cnt 0 2006.146.01:06:30.39#ibcon#cleared, iclass 39 cls_cnt 0 2006.146.01:06:30.39$vck44/vb=1,3 2006.146.01:06:30.39#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.146.01:06:30.39#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.146.01:06:30.39#ibcon#ireg 11 cls_cnt 2 2006.146.01:06:30.39#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.146.01:06:30.39#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.146.01:06:30.39#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.146.01:06:30.41#ibcon#[27=AT01-03\r\n] 2006.146.01:06:30.46#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.146.01:06:30.46#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.146.01:06:30.46#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.146.01:06:30.46#ibcon#ireg 7 cls_cnt 0 2006.146.01:06:30.46#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.146.01:06:30.58#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.146.01:06:30.58#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.146.01:06:30.60#ibcon#[27=USB\r\n] 2006.146.01:06:30.63#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.146.01:06:30.63#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.146.01:06:30.63#ibcon#about to clear, iclass 3 cls_cnt 0 2006.146.01:06:30.63#ibcon#cleared, iclass 3 cls_cnt 0 2006.146.01:06:30.63$vck44/vblo=2,634.99 2006.146.01:06:30.63#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.146.01:06:30.63#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.146.01:06:30.63#ibcon#ireg 17 cls_cnt 0 2006.146.01:06:30.63#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.146.01:06:30.63#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.146.01:06:30.63#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.146.01:06:30.65#ibcon#[28=FRQ=02,634.99\r\n] 2006.146.01:06:30.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.146.01:06:30.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.146.01:06:30.69#ibcon#about to clear, iclass 5 cls_cnt 0 2006.146.01:06:30.69#ibcon#cleared, iclass 5 cls_cnt 0 2006.146.01:06:30.69$vck44/vb=2,4 2006.146.01:06:30.69#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.146.01:06:30.69#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.146.01:06:30.69#ibcon#ireg 11 cls_cnt 2 2006.146.01:06:30.69#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.146.01:06:30.75#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.146.01:06:30.75#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.146.01:06:30.77#ibcon#[27=AT02-04\r\n] 2006.146.01:06:30.80#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.146.01:06:30.80#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.146.01:06:30.80#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.146.01:06:30.80#ibcon#ireg 7 cls_cnt 0 2006.146.01:06:30.80#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.146.01:06:30.92#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.146.01:06:30.92#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.146.01:06:30.94#ibcon#[27=USB\r\n] 2006.146.01:06:30.97#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.146.01:06:30.97#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.146.01:06:30.97#ibcon#about to clear, iclass 7 cls_cnt 0 2006.146.01:06:30.97#ibcon#cleared, iclass 7 cls_cnt 0 2006.146.01:06:30.97$vck44/vblo=3,649.99 2006.146.01:06:30.97#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.146.01:06:30.97#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.146.01:06:30.97#ibcon#ireg 17 cls_cnt 0 2006.146.01:06:30.97#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.146.01:06:30.97#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.146.01:06:30.97#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.146.01:06:30.99#ibcon#[28=FRQ=03,649.99\r\n] 2006.146.01:06:31.03#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.146.01:06:31.03#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.146.01:06:31.03#ibcon#about to clear, iclass 11 cls_cnt 0 2006.146.01:06:31.03#ibcon#cleared, iclass 11 cls_cnt 0 2006.146.01:06:31.03$vck44/vb=3,4 2006.146.01:06:31.03#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.146.01:06:31.03#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.146.01:06:31.03#ibcon#ireg 11 cls_cnt 2 2006.146.01:06:31.03#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.146.01:06:31.09#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.146.01:06:31.09#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.146.01:06:31.11#ibcon#[27=AT03-04\r\n] 2006.146.01:06:31.14#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.146.01:06:31.14#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.146.01:06:31.14#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.146.01:06:31.14#ibcon#ireg 7 cls_cnt 0 2006.146.01:06:31.14#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.146.01:06:31.26#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.146.01:06:31.26#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.146.01:06:31.28#ibcon#[27=USB\r\n] 2006.146.01:06:31.31#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.146.01:06:31.31#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.146.01:06:31.31#ibcon#about to clear, iclass 13 cls_cnt 0 2006.146.01:06:31.31#ibcon#cleared, iclass 13 cls_cnt 0 2006.146.01:06:31.31$vck44/vblo=4,679.99 2006.146.01:06:31.31#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.146.01:06:31.31#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.146.01:06:31.31#ibcon#ireg 17 cls_cnt 0 2006.146.01:06:31.31#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.146.01:06:31.31#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.146.01:06:31.31#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.146.01:06:31.33#ibcon#[28=FRQ=04,679.99\r\n] 2006.146.01:06:31.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.146.01:06:31.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.146.01:06:31.37#ibcon#about to clear, iclass 15 cls_cnt 0 2006.146.01:06:31.37#ibcon#cleared, iclass 15 cls_cnt 0 2006.146.01:06:31.37$vck44/vb=4,4 2006.146.01:06:31.37#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.146.01:06:31.37#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.146.01:06:31.37#ibcon#ireg 11 cls_cnt 2 2006.146.01:06:31.37#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.146.01:06:31.43#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.146.01:06:31.43#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.146.01:06:31.45#ibcon#[27=AT04-04\r\n] 2006.146.01:06:31.48#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.146.01:06:31.48#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.146.01:06:31.48#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.146.01:06:31.48#ibcon#ireg 7 cls_cnt 0 2006.146.01:06:31.48#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.146.01:06:31.60#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.146.01:06:31.60#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.146.01:06:31.62#ibcon#[27=USB\r\n] 2006.146.01:06:31.65#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.146.01:06:31.65#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.146.01:06:31.65#ibcon#about to clear, iclass 17 cls_cnt 0 2006.146.01:06:31.65#ibcon#cleared, iclass 17 cls_cnt 0 2006.146.01:06:31.65$vck44/vblo=5,709.99 2006.146.01:06:31.65#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.146.01:06:31.65#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.146.01:06:31.65#ibcon#ireg 17 cls_cnt 0 2006.146.01:06:31.65#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.146.01:06:31.65#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.146.01:06:31.65#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.146.01:06:31.67#ibcon#[28=FRQ=05,709.99\r\n] 2006.146.01:06:31.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.146.01:06:31.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.146.01:06:31.71#ibcon#about to clear, iclass 19 cls_cnt 0 2006.146.01:06:31.71#ibcon#cleared, iclass 19 cls_cnt 0 2006.146.01:06:31.71$vck44/vb=5,4 2006.146.01:06:31.71#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.146.01:06:31.71#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.146.01:06:31.71#ibcon#ireg 11 cls_cnt 2 2006.146.01:06:31.71#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.146.01:06:31.77#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.146.01:06:31.77#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.146.01:06:31.79#ibcon#[27=AT05-04\r\n] 2006.146.01:06:31.82#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.146.01:06:31.82#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.146.01:06:31.82#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.146.01:06:31.82#ibcon#ireg 7 cls_cnt 0 2006.146.01:06:31.82#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.146.01:06:31.94#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.146.01:06:31.94#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.146.01:06:31.96#ibcon#[27=USB\r\n] 2006.146.01:06:31.99#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.146.01:06:31.99#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.146.01:06:31.99#ibcon#about to clear, iclass 21 cls_cnt 0 2006.146.01:06:31.99#ibcon#cleared, iclass 21 cls_cnt 0 2006.146.01:06:31.99$vck44/vblo=6,719.99 2006.146.01:06:31.99#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.146.01:06:31.99#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.146.01:06:31.99#ibcon#ireg 17 cls_cnt 0 2006.146.01:06:31.99#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.146.01:06:31.99#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.146.01:06:31.99#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.146.01:06:32.01#ibcon#[28=FRQ=06,719.99\r\n] 2006.146.01:06:32.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.146.01:06:32.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.146.01:06:32.05#ibcon#about to clear, iclass 23 cls_cnt 0 2006.146.01:06:32.05#ibcon#cleared, iclass 23 cls_cnt 0 2006.146.01:06:32.05$vck44/vb=6,4 2006.146.01:06:32.05#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.146.01:06:32.05#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.146.01:06:32.05#ibcon#ireg 11 cls_cnt 2 2006.146.01:06:32.05#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.146.01:06:32.11#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.146.01:06:32.11#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.146.01:06:32.13#ibcon#[27=AT06-04\r\n] 2006.146.01:06:32.16#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.146.01:06:32.16#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.146.01:06:32.16#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.146.01:06:32.16#ibcon#ireg 7 cls_cnt 0 2006.146.01:06:32.16#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.146.01:06:32.28#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.146.01:06:32.28#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.146.01:06:32.30#ibcon#[27=USB\r\n] 2006.146.01:06:32.33#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.146.01:06:32.33#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.146.01:06:32.33#ibcon#about to clear, iclass 25 cls_cnt 0 2006.146.01:06:32.33#ibcon#cleared, iclass 25 cls_cnt 0 2006.146.01:06:32.33$vck44/vblo=7,734.99 2006.146.01:06:32.33#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.146.01:06:32.33#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.146.01:06:32.33#ibcon#ireg 17 cls_cnt 0 2006.146.01:06:32.33#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.146.01:06:32.33#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.146.01:06:32.33#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.146.01:06:32.35#ibcon#[28=FRQ=07,734.99\r\n] 2006.146.01:06:32.39#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.146.01:06:32.39#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.146.01:06:32.39#ibcon#about to clear, iclass 27 cls_cnt 0 2006.146.01:06:32.39#ibcon#cleared, iclass 27 cls_cnt 0 2006.146.01:06:32.39$vck44/vb=7,4 2006.146.01:06:32.39#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.146.01:06:32.39#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.146.01:06:32.39#ibcon#ireg 11 cls_cnt 2 2006.146.01:06:32.39#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.146.01:06:32.45#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.146.01:06:32.45#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.146.01:06:32.47#ibcon#[27=AT07-04\r\n] 2006.146.01:06:32.50#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.146.01:06:32.50#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.146.01:06:32.50#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.146.01:06:32.50#ibcon#ireg 7 cls_cnt 0 2006.146.01:06:32.50#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.146.01:06:32.62#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.146.01:06:32.62#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.146.01:06:32.64#ibcon#[27=USB\r\n] 2006.146.01:06:32.67#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.146.01:06:32.67#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.146.01:06:32.67#ibcon#about to clear, iclass 29 cls_cnt 0 2006.146.01:06:32.67#ibcon#cleared, iclass 29 cls_cnt 0 2006.146.01:06:32.67$vck44/vblo=8,744.99 2006.146.01:06:32.67#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.146.01:06:32.67#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.146.01:06:32.67#ibcon#ireg 17 cls_cnt 0 2006.146.01:06:32.67#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.146.01:06:32.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.146.01:06:32.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.146.01:06:32.69#ibcon#[28=FRQ=08,744.99\r\n] 2006.146.01:06:32.73#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.146.01:06:32.73#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.146.01:06:32.73#ibcon#about to clear, iclass 31 cls_cnt 0 2006.146.01:06:32.73#ibcon#cleared, iclass 31 cls_cnt 0 2006.146.01:06:32.73$vck44/vb=8,4 2006.146.01:06:32.73#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.146.01:06:32.73#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.146.01:06:32.73#ibcon#ireg 11 cls_cnt 2 2006.146.01:06:32.73#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.146.01:06:32.79#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.146.01:06:32.79#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.146.01:06:32.81#ibcon#[27=AT08-04\r\n] 2006.146.01:06:32.84#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.146.01:06:32.84#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.146.01:06:32.84#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.146.01:06:32.84#ibcon#ireg 7 cls_cnt 0 2006.146.01:06:32.84#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.146.01:06:32.96#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.146.01:06:32.96#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.146.01:06:32.98#ibcon#[27=USB\r\n] 2006.146.01:06:33.01#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.146.01:06:33.01#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.146.01:06:33.01#ibcon#about to clear, iclass 33 cls_cnt 0 2006.146.01:06:33.01#ibcon#cleared, iclass 33 cls_cnt 0 2006.146.01:06:33.01$vck44/vabw=wide 2006.146.01:06:33.01#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.146.01:06:33.01#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.146.01:06:33.01#ibcon#ireg 8 cls_cnt 0 2006.146.01:06:33.01#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.146.01:06:33.01#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.146.01:06:33.01#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.146.01:06:33.03#ibcon#[25=BW32\r\n] 2006.146.01:06:33.06#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.146.01:06:33.06#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.146.01:06:33.06#ibcon#about to clear, iclass 35 cls_cnt 0 2006.146.01:06:33.06#ibcon#cleared, iclass 35 cls_cnt 0 2006.146.01:06:33.06$vck44/vbbw=wide 2006.146.01:06:33.06#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.146.01:06:33.06#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.146.01:06:33.06#ibcon#ireg 8 cls_cnt 0 2006.146.01:06:33.06#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.146.01:06:33.13#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.146.01:06:33.13#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.146.01:06:33.15#ibcon#[27=BW32\r\n] 2006.146.01:06:33.18#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.146.01:06:33.18#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.146.01:06:33.18#ibcon#about to clear, iclass 37 cls_cnt 0 2006.146.01:06:33.18#ibcon#cleared, iclass 37 cls_cnt 0 2006.146.01:06:33.18$setupk4/ifdk4 2006.146.01:06:33.18$ifdk4/lo= 2006.146.01:06:33.18$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.146.01:06:33.18$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.146.01:06:33.18$ifdk4/patch= 2006.146.01:06:33.18$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.146.01:06:33.18$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.146.01:06:33.18$setupk4/!*+20s 2006.146.01:06:38.93#abcon#<5=/09 2.1 6.9 20.88 671020.4\r\n> 2006.146.01:06:38.95#abcon#{5=INTERFACE CLEAR} 2006.146.01:06:39.01#abcon#[5=S1D000X0/0*\r\n] 2006.146.01:06:41.14#trakl#Source acquired 2006.146.01:06:43.14#flagr#flagr/antenna,acquired 2006.146.01:06:47.64$setupk4/"tpicd 2006.146.01:06:47.64$setupk4/echo=off 2006.146.01:06:47.64$setupk4/xlog=off 2006.146.01:06:47.64:!2006.146.01:15:36 2006.146.01:15:36.00:preob 2006.146.01:15:36.14/onsource/TRACKING 2006.146.01:15:36.14:!2006.146.01:15:46 2006.146.01:15:46.00:"tape 2006.146.01:15:46.00:"st=record 2006.146.01:15:46.00:data_valid=on 2006.146.01:15:46.00:midob 2006.146.01:15:46.14/onsource/TRACKING 2006.146.01:15:46.15/wx/20.79,1020.2,68 2006.146.01:15:46.20/cable/+6.5441E-03 2006.146.01:15:47.29/va/01,08,usb,yes,28,30 2006.146.01:15:47.29/va/02,07,usb,yes,30,31 2006.146.01:15:47.29/va/03,08,usb,yes,28,29 2006.146.01:15:47.29/va/04,07,usb,yes,31,33 2006.146.01:15:47.29/va/05,04,usb,yes,27,28 2006.146.01:15:47.29/va/06,04,usb,yes,31,30 2006.146.01:15:47.29/va/07,04,usb,yes,31,32 2006.146.01:15:47.29/va/08,04,usb,yes,26,32 2006.146.01:15:47.52/valo/01,524.99,yes,locked 2006.146.01:15:47.52/valo/02,534.99,yes,locked 2006.146.01:15:47.52/valo/03,564.99,yes,locked 2006.146.01:15:47.52/valo/04,624.99,yes,locked 2006.146.01:15:47.52/valo/05,734.99,yes,locked 2006.146.01:15:47.52/valo/06,814.99,yes,locked 2006.146.01:15:47.52/valo/07,864.99,yes,locked 2006.146.01:15:47.52/valo/08,884.99,yes,locked 2006.146.01:15:48.61/vb/01,03,usb,yes,36,33 2006.146.01:15:48.61/vb/02,04,usb,yes,31,31 2006.146.01:15:48.61/vb/03,04,usb,yes,28,31 2006.146.01:15:48.61/vb/04,04,usb,yes,32,31 2006.146.01:15:48.61/vb/05,04,usb,yes,25,27 2006.146.01:15:48.61/vb/06,04,usb,yes,29,26 2006.146.01:15:48.61/vb/07,04,usb,yes,29,29 2006.146.01:15:48.61/vb/08,04,usb,yes,27,30 2006.146.01:15:48.84/vblo/01,629.99,yes,locked 2006.146.01:15:48.84/vblo/02,634.99,yes,locked 2006.146.01:15:48.84/vblo/03,649.99,yes,locked 2006.146.01:15:48.84/vblo/04,679.99,yes,locked 2006.146.01:15:48.84/vblo/05,709.99,yes,locked 2006.146.01:15:48.84/vblo/06,719.99,yes,locked 2006.146.01:15:48.84/vblo/07,734.99,yes,locked 2006.146.01:15:48.84/vblo/08,744.99,yes,locked 2006.146.01:15:48.99/vabw/8 2006.146.01:15:49.14/vbbw/8 2006.146.01:15:49.23/xfe/off,on,15.2 2006.146.01:15:49.60/ifatt/23,28,28,28 2006.146.01:15:50.07/fmout-gps/S +4.0E-08 2006.146.01:15:50.12:!2006.146.01:28:50 2006.146.01:27:19.14#trakl#Off source 2006.146.01:27:19.14?ERROR st -7 Antenna off-source! 2006.146.01:27:19.14#trakl#az 137.110 el 42.752 azerr*cos(el) 0.0003 elerr 0.0182 2006.146.01:27:21.14#flagr#flagr/antenna,off-source 2006.146.01:27:26.14#trakl#Source re-acquired 2006.146.01:27:27.14#flagr#flagr/antenna,re-acquired 2006.146.01:28:50.00:data_valid=off 2006.146.01:28:50.00:"et 2006.146.01:28:50.01:!+3s 2006.146.01:28:53.02:"tape 2006.146.01:28:53.02:postob 2006.146.01:28:53.21/cable/+6.5409E-03 2006.146.01:28:53.21/wx/20.99,1020.1,66 2006.146.01:28:53.28/fmout-gps/S +4.2E-08 2006.146.01:28:53.28:scan_name=146-0129,jd0605,40 2006.146.01:28:53.28:source=3c446,222547.26,-045701.4,2000.0,cw 2006.146.01:28:55.14#flagr#flagr/antenna,new-source 2006.146.01:28:55.14:checkk5 2006.146.01:28:55.52/chk_autoobs//k5ts1/ autoobs is running! 2006.146.01:28:55.90/chk_autoobs//k5ts2/ autoobs is running! 2006.146.01:28:56.29/chk_autoobs//k5ts3/ autoobs is running! 2006.146.01:28:56.66/chk_autoobs//k5ts4/ autoobs is running! 2006.146.01:28:57.33/chk_obsdata//k5ts1/T1460115??a.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.146.01:28:58.39/chk_obsdata//k5ts2/T1460115??b.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.146.01:28:59.12/chk_obsdata//k5ts3/T1460115??c.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.146.01:28:59.88/chk_obsdata//k5ts4/T1460115??d.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.146.01:29:00.64/k5log//k5ts1_log_newline 2006.146.01:29:01.38/k5log//k5ts2_log_newline 2006.146.01:29:02.08/k5log//k5ts3_log_newline 2006.146.01:29:02.83/k5log//k5ts4_log_newline 2006.146.01:29:02.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.146.01:29:02.85:setupk4=1 2006.146.01:29:02.85$setupk4/echo=on 2006.146.01:29:02.85$setupk4/pcalon 2006.146.01:29:02.85$pcalon/"no phase cal control is implemented here 2006.146.01:29:02.85$setupk4/"tpicd=stop 2006.146.01:29:02.85$setupk4/"rec=synch_on 2006.146.01:29:02.85$setupk4/"rec_mode=128 2006.146.01:29:02.85$setupk4/!* 2006.146.01:29:02.85$setupk4/recpk4 2006.146.01:29:02.85$recpk4/recpatch= 2006.146.01:29:02.85$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.146.01:29:02.85$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.146.01:29:02.85$setupk4/vck44 2006.146.01:29:02.85$vck44/valo=1,524.99 2006.146.01:29:02.85#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.146.01:29:02.85#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.146.01:29:02.85#ibcon#ireg 17 cls_cnt 0 2006.146.01:29:02.85#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.146.01:29:02.85#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.146.01:29:02.85#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.146.01:29:02.89#ibcon#[26=FRQ=01,524.99\r\n] 2006.146.01:29:02.94#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.146.01:29:02.94#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.146.01:29:02.94#ibcon#about to clear, iclass 36 cls_cnt 0 2006.146.01:29:02.94#ibcon#cleared, iclass 36 cls_cnt 0 2006.146.01:29:02.94$vck44/va=1,8 2006.146.01:29:02.94#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.146.01:29:02.94#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.146.01:29:02.94#ibcon#ireg 11 cls_cnt 2 2006.146.01:29:02.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.146.01:29:02.94#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.146.01:29:02.94#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.146.01:29:02.96#ibcon#[25=AT01-08\r\n] 2006.146.01:29:02.99#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.146.01:29:02.99#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.146.01:29:02.99#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.146.01:29:02.99#ibcon#ireg 7 cls_cnt 0 2006.146.01:29:02.99#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.146.01:29:03.13#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.146.01:29:03.13#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.146.01:29:03.15#ibcon#[25=USB\r\n] 2006.146.01:29:03.18#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.146.01:29:03.18#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.146.01:29:03.18#ibcon#about to clear, iclass 38 cls_cnt 0 2006.146.01:29:03.18#ibcon#cleared, iclass 38 cls_cnt 0 2006.146.01:29:03.18$vck44/valo=2,534.99 2006.146.01:29:03.18#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.146.01:29:03.18#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.146.01:29:03.18#ibcon#ireg 17 cls_cnt 0 2006.146.01:29:03.18#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.146.01:29:03.18#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.146.01:29:03.18#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.146.01:29:03.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.146.01:29:03.25#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.146.01:29:03.25#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.146.01:29:03.25#ibcon#about to clear, iclass 40 cls_cnt 0 2006.146.01:29:03.25#ibcon#cleared, iclass 40 cls_cnt 0 2006.146.01:29:03.25$vck44/va=2,7 2006.146.01:29:03.25#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.146.01:29:03.25#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.146.01:29:03.25#ibcon#ireg 11 cls_cnt 2 2006.146.01:29:03.25#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.146.01:29:03.30#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.146.01:29:03.30#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.146.01:29:03.32#ibcon#[25=AT02-07\r\n] 2006.146.01:29:03.35#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.146.01:29:03.35#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.146.01:29:03.35#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.146.01:29:03.35#ibcon#ireg 7 cls_cnt 0 2006.146.01:29:03.35#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.146.01:29:03.47#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.146.01:29:03.47#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.146.01:29:03.49#ibcon#[25=USB\r\n] 2006.146.01:29:03.52#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.146.01:29:03.52#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.146.01:29:03.52#ibcon#about to clear, iclass 4 cls_cnt 0 2006.146.01:29:03.52#ibcon#cleared, iclass 4 cls_cnt 0 2006.146.01:29:03.52$vck44/valo=3,564.99 2006.146.01:29:03.52#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.146.01:29:03.52#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.146.01:29:03.52#ibcon#ireg 17 cls_cnt 0 2006.146.01:29:03.52#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.146.01:29:03.52#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.146.01:29:03.52#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.146.01:29:03.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.146.01:29:03.58#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.146.01:29:03.58#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.146.01:29:03.58#ibcon#about to clear, iclass 6 cls_cnt 0 2006.146.01:29:03.58#ibcon#cleared, iclass 6 cls_cnt 0 2006.146.01:29:03.58$vck44/va=3,8 2006.146.01:29:03.58#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.146.01:29:03.58#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.146.01:29:03.58#ibcon#ireg 11 cls_cnt 2 2006.146.01:29:03.58#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.146.01:29:03.64#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.146.01:29:03.64#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.146.01:29:03.66#ibcon#[25=AT03-08\r\n] 2006.146.01:29:03.69#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.146.01:29:03.69#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.146.01:29:03.69#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.146.01:29:03.69#ibcon#ireg 7 cls_cnt 0 2006.146.01:29:03.69#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.146.01:29:03.81#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.146.01:29:03.81#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.146.01:29:03.83#ibcon#[25=USB\r\n] 2006.146.01:29:03.86#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.146.01:29:03.86#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.146.01:29:03.86#ibcon#about to clear, iclass 10 cls_cnt 0 2006.146.01:29:03.86#ibcon#cleared, iclass 10 cls_cnt 0 2006.146.01:29:03.86$vck44/valo=4,624.99 2006.146.01:29:03.86#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.146.01:29:03.86#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.146.01:29:03.86#ibcon#ireg 17 cls_cnt 0 2006.146.01:29:03.86#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.146.01:29:03.86#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.146.01:29:03.86#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.146.01:29:03.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.146.01:29:03.92#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.146.01:29:03.92#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.146.01:29:03.92#ibcon#about to clear, iclass 12 cls_cnt 0 2006.146.01:29:03.92#ibcon#cleared, iclass 12 cls_cnt 0 2006.146.01:29:03.92$vck44/va=4,7 2006.146.01:29:03.92#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.146.01:29:03.92#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.146.01:29:03.92#ibcon#ireg 11 cls_cnt 2 2006.146.01:29:03.92#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.146.01:29:03.98#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.146.01:29:03.98#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.146.01:29:04.00#ibcon#[25=AT04-07\r\n] 2006.146.01:29:04.03#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.146.01:29:04.03#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.146.01:29:04.03#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.146.01:29:04.03#ibcon#ireg 7 cls_cnt 0 2006.146.01:29:04.03#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.146.01:29:04.15#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.146.01:29:04.15#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.146.01:29:04.17#ibcon#[25=USB\r\n] 2006.146.01:29:04.20#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.146.01:29:04.20#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.146.01:29:04.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.146.01:29:04.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.146.01:29:04.20$vck44/valo=5,734.99 2006.146.01:29:04.20#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.146.01:29:04.20#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.146.01:29:04.20#ibcon#ireg 17 cls_cnt 0 2006.146.01:29:04.20#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.146.01:29:04.20#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.146.01:29:04.20#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.146.01:29:04.22#ibcon#[26=FRQ=05,734.99\r\n] 2006.146.01:29:04.26#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.146.01:29:04.26#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.146.01:29:04.26#ibcon#about to clear, iclass 16 cls_cnt 0 2006.146.01:29:04.26#ibcon#cleared, iclass 16 cls_cnt 0 2006.146.01:29:04.26$vck44/va=5,4 2006.146.01:29:04.26#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.146.01:29:04.26#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.146.01:29:04.26#ibcon#ireg 11 cls_cnt 2 2006.146.01:29:04.26#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.146.01:29:04.32#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.146.01:29:04.32#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.146.01:29:04.34#ibcon#[25=AT05-04\r\n] 2006.146.01:29:04.37#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.146.01:29:04.37#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.146.01:29:04.37#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.146.01:29:04.37#ibcon#ireg 7 cls_cnt 0 2006.146.01:29:04.37#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.146.01:29:04.49#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.146.01:29:04.49#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.146.01:29:04.51#ibcon#[25=USB\r\n] 2006.146.01:29:04.54#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.146.01:29:04.54#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.146.01:29:04.54#ibcon#about to clear, iclass 18 cls_cnt 0 2006.146.01:29:04.54#ibcon#cleared, iclass 18 cls_cnt 0 2006.146.01:29:04.54$vck44/valo=6,814.99 2006.146.01:29:04.54#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.146.01:29:04.54#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.146.01:29:04.54#ibcon#ireg 17 cls_cnt 0 2006.146.01:29:04.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.146.01:29:04.54#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.146.01:29:04.54#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.146.01:29:04.57#ibcon#[26=FRQ=06,814.99\r\n] 2006.146.01:29:04.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.146.01:29:04.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.146.01:29:04.61#ibcon#about to clear, iclass 20 cls_cnt 0 2006.146.01:29:04.61#ibcon#cleared, iclass 20 cls_cnt 0 2006.146.01:29:04.61$vck44/va=6,4 2006.146.01:29:04.61#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.146.01:29:04.61#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.146.01:29:04.61#ibcon#ireg 11 cls_cnt 2 2006.146.01:29:04.61#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.146.01:29:04.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.146.01:29:04.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.146.01:29:04.68#ibcon#[25=AT06-04\r\n] 2006.146.01:29:04.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.146.01:29:04.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.146.01:29:04.71#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.146.01:29:04.71#ibcon#ireg 7 cls_cnt 0 2006.146.01:29:04.71#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.146.01:29:04.83#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.146.01:29:04.83#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.146.01:29:04.85#ibcon#[25=USB\r\n] 2006.146.01:29:04.88#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.146.01:29:04.88#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.146.01:29:04.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.146.01:29:04.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.146.01:29:04.88$vck44/valo=7,864.99 2006.146.01:29:04.88#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.146.01:29:04.88#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.146.01:29:04.88#ibcon#ireg 17 cls_cnt 0 2006.146.01:29:04.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.146.01:29:04.88#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.146.01:29:04.88#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.146.01:29:04.90#ibcon#[26=FRQ=07,864.99\r\n] 2006.146.01:29:04.94#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.146.01:29:04.94#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.146.01:29:04.94#ibcon#about to clear, iclass 24 cls_cnt 0 2006.146.01:29:04.94#ibcon#cleared, iclass 24 cls_cnt 0 2006.146.01:29:04.94$vck44/va=7,4 2006.146.01:29:04.94#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.146.01:29:04.94#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.146.01:29:04.94#ibcon#ireg 11 cls_cnt 2 2006.146.01:29:04.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.146.01:29:05.00#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.146.01:29:05.00#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.146.01:29:05.02#ibcon#[25=AT07-04\r\n] 2006.146.01:29:05.05#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.146.01:29:05.05#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.146.01:29:05.05#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.146.01:29:05.05#ibcon#ireg 7 cls_cnt 0 2006.146.01:29:05.05#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.146.01:29:05.17#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.146.01:29:05.17#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.146.01:29:05.19#ibcon#[25=USB\r\n] 2006.146.01:29:05.22#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.146.01:29:05.22#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.146.01:29:05.22#ibcon#about to clear, iclass 26 cls_cnt 0 2006.146.01:29:05.22#ibcon#cleared, iclass 26 cls_cnt 0 2006.146.01:29:05.22$vck44/valo=8,884.99 2006.146.01:29:05.22#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.146.01:29:05.22#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.146.01:29:05.22#ibcon#ireg 17 cls_cnt 0 2006.146.01:29:05.22#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.146.01:29:05.22#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.146.01:29:05.22#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.146.01:29:05.24#ibcon#[26=FRQ=08,884.99\r\n] 2006.146.01:29:05.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.146.01:29:05.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.146.01:29:05.28#ibcon#about to clear, iclass 28 cls_cnt 0 2006.146.01:29:05.28#ibcon#cleared, iclass 28 cls_cnt 0 2006.146.01:29:05.28$vck44/va=8,4 2006.146.01:29:05.28#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.146.01:29:05.28#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.146.01:29:05.28#ibcon#ireg 11 cls_cnt 2 2006.146.01:29:05.28#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.146.01:29:05.34#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.146.01:29:05.34#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.146.01:29:05.36#ibcon#[25=AT08-04\r\n] 2006.146.01:29:05.39#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.146.01:29:05.39#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.146.01:29:05.39#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.146.01:29:05.39#ibcon#ireg 7 cls_cnt 0 2006.146.01:29:05.39#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.146.01:29:05.51#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.146.01:29:05.51#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.146.01:29:05.53#ibcon#[25=USB\r\n] 2006.146.01:29:05.56#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.146.01:29:05.56#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.146.01:29:05.56#ibcon#about to clear, iclass 30 cls_cnt 0 2006.146.01:29:05.56#ibcon#cleared, iclass 30 cls_cnt 0 2006.146.01:29:05.56$vck44/vblo=1,629.99 2006.146.01:29:05.56#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.146.01:29:05.56#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.146.01:29:05.56#ibcon#ireg 17 cls_cnt 0 2006.146.01:29:05.56#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.146.01:29:05.56#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.146.01:29:05.56#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.146.01:29:05.58#ibcon#[28=FRQ=01,629.99\r\n] 2006.146.01:29:05.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.146.01:29:05.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.146.01:29:05.63#ibcon#about to clear, iclass 32 cls_cnt 0 2006.146.01:29:05.63#ibcon#cleared, iclass 32 cls_cnt 0 2006.146.01:29:05.63$vck44/vb=1,3 2006.146.01:29:05.63#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.146.01:29:05.63#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.146.01:29:05.63#ibcon#ireg 11 cls_cnt 2 2006.146.01:29:05.63#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.146.01:29:05.63#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.146.01:29:05.63#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.146.01:29:05.64#ibcon#[27=AT01-03\r\n] 2006.146.01:29:05.67#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.146.01:29:05.67#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.146.01:29:05.67#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.146.01:29:05.67#ibcon#ireg 7 cls_cnt 0 2006.146.01:29:05.67#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.146.01:29:05.79#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.146.01:29:05.79#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.146.01:29:05.81#ibcon#[27=USB\r\n] 2006.146.01:29:05.84#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.146.01:29:05.84#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.146.01:29:05.84#ibcon#about to clear, iclass 34 cls_cnt 0 2006.146.01:29:05.84#ibcon#cleared, iclass 34 cls_cnt 0 2006.146.01:29:05.84$vck44/vblo=2,634.99 2006.146.01:29:05.84#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.146.01:29:05.84#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.146.01:29:05.84#ibcon#ireg 17 cls_cnt 0 2006.146.01:29:05.84#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.146.01:29:05.84#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.146.01:29:05.84#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.146.01:29:05.86#ibcon#[28=FRQ=02,634.99\r\n] 2006.146.01:29:05.90#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.146.01:29:05.90#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.146.01:29:05.90#ibcon#about to clear, iclass 36 cls_cnt 0 2006.146.01:29:05.90#ibcon#cleared, iclass 36 cls_cnt 0 2006.146.01:29:05.90$vck44/vb=2,4 2006.146.01:29:05.90#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.146.01:29:05.90#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.146.01:29:05.90#ibcon#ireg 11 cls_cnt 2 2006.146.01:29:05.90#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.146.01:29:05.96#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.146.01:29:05.96#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.146.01:29:05.98#ibcon#[27=AT02-04\r\n] 2006.146.01:29:06.01#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.146.01:29:06.01#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.146.01:29:06.01#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.146.01:29:06.01#ibcon#ireg 7 cls_cnt 0 2006.146.01:29:06.01#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.146.01:29:06.13#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.146.01:29:06.13#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.146.01:29:06.15#ibcon#[27=USB\r\n] 2006.146.01:29:06.18#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.146.01:29:06.18#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.146.01:29:06.18#ibcon#about to clear, iclass 38 cls_cnt 0 2006.146.01:29:06.18#ibcon#cleared, iclass 38 cls_cnt 0 2006.146.01:29:06.18$vck44/vblo=3,649.99 2006.146.01:29:06.18#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.146.01:29:06.18#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.146.01:29:06.18#ibcon#ireg 17 cls_cnt 0 2006.146.01:29:06.18#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.146.01:29:06.18#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.146.01:29:06.18#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.146.01:29:06.20#ibcon#[28=FRQ=03,649.99\r\n] 2006.146.01:29:06.24#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.146.01:29:06.24#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.146.01:29:06.24#ibcon#about to clear, iclass 40 cls_cnt 0 2006.146.01:29:06.24#ibcon#cleared, iclass 40 cls_cnt 0 2006.146.01:29:06.24$vck44/vb=3,4 2006.146.01:29:06.24#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.146.01:29:06.24#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.146.01:29:06.24#ibcon#ireg 11 cls_cnt 2 2006.146.01:29:06.24#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.146.01:29:06.30#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.146.01:29:06.30#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.146.01:29:06.32#ibcon#[27=AT03-04\r\n] 2006.146.01:29:06.35#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.146.01:29:06.35#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.146.01:29:06.35#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.146.01:29:06.35#ibcon#ireg 7 cls_cnt 0 2006.146.01:29:06.35#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.146.01:29:06.47#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.146.01:29:06.47#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.146.01:29:06.49#ibcon#[27=USB\r\n] 2006.146.01:29:06.52#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.146.01:29:06.52#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.146.01:29:06.52#ibcon#about to clear, iclass 4 cls_cnt 0 2006.146.01:29:06.52#ibcon#cleared, iclass 4 cls_cnt 0 2006.146.01:29:06.52$vck44/vblo=4,679.99 2006.146.01:29:06.52#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.146.01:29:06.52#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.146.01:29:06.52#ibcon#ireg 17 cls_cnt 0 2006.146.01:29:06.52#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.146.01:29:06.52#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.146.01:29:06.52#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.146.01:29:06.54#ibcon#[28=FRQ=04,679.99\r\n] 2006.146.01:29:06.58#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.146.01:29:06.58#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.146.01:29:06.58#ibcon#about to clear, iclass 6 cls_cnt 0 2006.146.01:29:06.58#ibcon#cleared, iclass 6 cls_cnt 0 2006.146.01:29:06.58$vck44/vb=4,4 2006.146.01:29:06.58#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.146.01:29:06.58#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.146.01:29:06.58#ibcon#ireg 11 cls_cnt 2 2006.146.01:29:06.58#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.146.01:29:06.64#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.146.01:29:06.64#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.146.01:29:06.66#ibcon#[27=AT04-04\r\n] 2006.146.01:29:06.69#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.146.01:29:06.69#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.146.01:29:06.69#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.146.01:29:06.69#ibcon#ireg 7 cls_cnt 0 2006.146.01:29:06.69#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.146.01:29:06.81#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.146.01:29:06.81#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.146.01:29:06.83#ibcon#[27=USB\r\n] 2006.146.01:29:06.86#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.146.01:29:06.86#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.146.01:29:06.86#ibcon#about to clear, iclass 10 cls_cnt 0 2006.146.01:29:06.86#ibcon#cleared, iclass 10 cls_cnt 0 2006.146.01:29:06.86$vck44/vblo=5,709.99 2006.146.01:29:06.86#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.146.01:29:06.86#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.146.01:29:06.86#ibcon#ireg 17 cls_cnt 0 2006.146.01:29:06.86#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.146.01:29:06.86#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.146.01:29:06.86#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.146.01:29:06.88#ibcon#[28=FRQ=05,709.99\r\n] 2006.146.01:29:06.92#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.146.01:29:06.92#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.146.01:29:06.92#ibcon#about to clear, iclass 12 cls_cnt 0 2006.146.01:29:06.92#ibcon#cleared, iclass 12 cls_cnt 0 2006.146.01:29:06.92$vck44/vb=5,4 2006.146.01:29:06.92#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.146.01:29:06.92#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.146.01:29:06.92#ibcon#ireg 11 cls_cnt 2 2006.146.01:29:06.92#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.146.01:29:06.98#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.146.01:29:06.98#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.146.01:29:07.00#ibcon#[27=AT05-04\r\n] 2006.146.01:29:07.03#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.146.01:29:07.03#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.146.01:29:07.03#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.146.01:29:07.03#ibcon#ireg 7 cls_cnt 0 2006.146.01:29:07.03#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.146.01:29:07.15#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.146.01:29:07.15#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.146.01:29:07.17#ibcon#[27=USB\r\n] 2006.146.01:29:07.20#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.146.01:29:07.20#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.146.01:29:07.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.146.01:29:07.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.146.01:29:07.20$vck44/vblo=6,719.99 2006.146.01:29:07.20#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.146.01:29:07.20#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.146.01:29:07.20#ibcon#ireg 17 cls_cnt 0 2006.146.01:29:07.20#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.146.01:29:07.20#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.146.01:29:07.20#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.146.01:29:07.22#ibcon#[28=FRQ=06,719.99\r\n] 2006.146.01:29:07.26#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.146.01:29:07.26#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.146.01:29:07.26#ibcon#about to clear, iclass 16 cls_cnt 0 2006.146.01:29:07.26#ibcon#cleared, iclass 16 cls_cnt 0 2006.146.01:29:07.26$vck44/vb=6,4 2006.146.01:29:07.26#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.146.01:29:07.26#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.146.01:29:07.26#ibcon#ireg 11 cls_cnt 2 2006.146.01:29:07.26#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.146.01:29:07.32#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.146.01:29:07.32#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.146.01:29:07.34#ibcon#[27=AT06-04\r\n] 2006.146.01:29:07.37#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.146.01:29:07.37#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.146.01:29:07.37#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.146.01:29:07.37#ibcon#ireg 7 cls_cnt 0 2006.146.01:29:07.37#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.146.01:29:07.49#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.146.01:29:07.49#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.146.01:29:07.51#ibcon#[27=USB\r\n] 2006.146.01:29:07.54#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.146.01:29:07.54#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.146.01:29:07.54#ibcon#about to clear, iclass 18 cls_cnt 0 2006.146.01:29:07.54#ibcon#cleared, iclass 18 cls_cnt 0 2006.146.01:29:07.54$vck44/vblo=7,734.99 2006.146.01:29:07.54#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.146.01:29:07.54#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.146.01:29:07.54#ibcon#ireg 17 cls_cnt 0 2006.146.01:29:07.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.146.01:29:07.54#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.146.01:29:07.54#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.146.01:29:07.56#ibcon#[28=FRQ=07,734.99\r\n] 2006.146.01:29:07.60#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.146.01:29:07.60#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.146.01:29:07.60#ibcon#about to clear, iclass 20 cls_cnt 0 2006.146.01:29:07.60#ibcon#cleared, iclass 20 cls_cnt 0 2006.146.01:29:07.60$vck44/vb=7,4 2006.146.01:29:07.60#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.146.01:29:07.60#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.146.01:29:07.60#ibcon#ireg 11 cls_cnt 2 2006.146.01:29:07.60#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.146.01:29:07.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.146.01:29:07.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.146.01:29:07.68#ibcon#[27=AT07-04\r\n] 2006.146.01:29:07.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.146.01:29:07.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.146.01:29:07.71#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.146.01:29:07.71#ibcon#ireg 7 cls_cnt 0 2006.146.01:29:07.71#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.146.01:29:07.83#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.146.01:29:07.83#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.146.01:29:07.85#ibcon#[27=USB\r\n] 2006.146.01:29:07.88#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.146.01:29:07.88#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.146.01:29:07.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.146.01:29:07.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.146.01:29:07.88$vck44/vblo=8,744.99 2006.146.01:29:07.88#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.146.01:29:07.88#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.146.01:29:07.88#ibcon#ireg 17 cls_cnt 0 2006.146.01:29:07.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.146.01:29:07.88#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.146.01:29:07.88#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.146.01:29:07.90#ibcon#[28=FRQ=08,744.99\r\n] 2006.146.01:29:07.94#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.146.01:29:07.94#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.146.01:29:07.94#ibcon#about to clear, iclass 24 cls_cnt 0 2006.146.01:29:07.94#ibcon#cleared, iclass 24 cls_cnt 0 2006.146.01:29:07.94$vck44/vb=8,4 2006.146.01:29:07.94#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.146.01:29:07.94#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.146.01:29:07.94#ibcon#ireg 11 cls_cnt 2 2006.146.01:29:07.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.146.01:29:08.00#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.146.01:29:08.00#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.146.01:29:08.02#ibcon#[27=AT08-04\r\n] 2006.146.01:29:08.05#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.146.01:29:08.05#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.146.01:29:08.05#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.146.01:29:08.05#ibcon#ireg 7 cls_cnt 0 2006.146.01:29:08.05#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.146.01:29:08.17#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.146.01:29:08.17#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.146.01:29:08.19#ibcon#[27=USB\r\n] 2006.146.01:29:08.22#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.146.01:29:08.22#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.146.01:29:08.22#ibcon#about to clear, iclass 26 cls_cnt 0 2006.146.01:29:08.22#ibcon#cleared, iclass 26 cls_cnt 0 2006.146.01:29:08.22$vck44/vabw=wide 2006.146.01:29:08.22#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.146.01:29:08.22#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.146.01:29:08.22#ibcon#ireg 8 cls_cnt 0 2006.146.01:29:08.22#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.146.01:29:08.22#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.146.01:29:08.22#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.146.01:29:08.24#ibcon#[25=BW32\r\n] 2006.146.01:29:08.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.146.01:29:08.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.146.01:29:08.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.146.01:29:08.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.146.01:29:08.27$vck44/vbbw=wide 2006.146.01:29:08.27#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.146.01:29:08.27#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.146.01:29:08.27#ibcon#ireg 8 cls_cnt 0 2006.146.01:29:08.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.146.01:29:08.34#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.146.01:29:08.34#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.146.01:29:08.36#ibcon#[27=BW32\r\n] 2006.146.01:29:08.39#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.146.01:29:08.39#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.146.01:29:08.39#ibcon#about to clear, iclass 30 cls_cnt 0 2006.146.01:29:08.39#ibcon#cleared, iclass 30 cls_cnt 0 2006.146.01:29:08.39$setupk4/ifdk4 2006.146.01:29:08.39$ifdk4/lo= 2006.146.01:29:08.39$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.146.01:29:08.39$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.146.01:29:08.39$ifdk4/patch= 2006.146.01:29:08.39$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.146.01:29:08.39$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.146.01:29:08.39$setupk4/!*+20s 2006.146.01:29:11.96#abcon#<5=/09 2.4 6.6 21.00 661020.1\r\n> 2006.146.01:29:11.98#abcon#{5=INTERFACE CLEAR} 2006.146.01:29:12.04#abcon#[5=S1D000X0/0*\r\n] 2006.146.01:29:22.13#abcon#<5=/09 2.4 6.5 21.00 661020.1\r\n> 2006.146.01:29:22.15#abcon#{5=INTERFACE CLEAR} 2006.146.01:29:22.21#abcon#[5=S1D000X0/0*\r\n] 2006.146.01:29:22.86$setupk4/"tpicd 2006.146.01:29:22.86$setupk4/echo=off 2006.146.01:29:22.86$setupk4/xlog=off 2006.146.01:29:22.86:!2006.146.01:29:43 2006.146.01:29:40.14#trakl#Source acquired 2006.146.01:29:41.14#flagr#flagr/antenna,acquired 2006.146.01:29:43.00:preob 2006.146.01:29:43.14/onsource/TRACKING 2006.146.01:29:43.14:!2006.146.01:29:53 2006.146.01:29:53.00:"tape 2006.146.01:29:53.00:"st=record 2006.146.01:29:53.00:data_valid=on 2006.146.01:29:53.00:midob 2006.146.01:29:53.14/onsource/TRACKING 2006.146.01:29:53.14/wx/21.01,1020.1,66 2006.146.01:29:53.33/cable/+6.5425E-03 2006.146.01:29:54.42/va/01,08,usb,yes,32,34 2006.146.01:29:54.42/va/02,07,usb,yes,34,35 2006.146.01:29:54.42/va/03,08,usb,yes,31,32 2006.146.01:29:54.42/va/04,07,usb,yes,35,37 2006.146.01:29:54.42/va/05,04,usb,yes,31,32 2006.146.01:29:54.42/va/06,04,usb,yes,35,34 2006.146.01:29:54.42/va/07,04,usb,yes,35,36 2006.146.01:29:54.42/va/08,04,usb,yes,30,36 2006.146.01:29:54.65/valo/01,524.99,yes,locked 2006.146.01:29:54.65/valo/02,534.99,yes,locked 2006.146.01:29:54.65/valo/03,564.99,yes,locked 2006.146.01:29:54.65/valo/04,624.99,yes,locked 2006.146.01:29:54.65/valo/05,734.99,yes,locked 2006.146.01:29:54.65/valo/06,814.99,yes,locked 2006.146.01:29:54.65/valo/07,864.99,yes,locked 2006.146.01:29:54.65/valo/08,884.99,yes,locked 2006.146.01:29:55.74/vb/01,03,usb,yes,38,36 2006.146.01:29:55.74/vb/02,04,usb,yes,34,33 2006.146.01:29:55.74/vb/03,04,usb,yes,30,33 2006.146.01:29:55.74/vb/04,04,usb,yes,35,34 2006.146.01:29:55.74/vb/05,04,usb,yes,27,30 2006.146.01:29:55.74/vb/06,04,usb,yes,32,28 2006.146.01:29:55.74/vb/07,04,usb,yes,32,31 2006.146.01:29:55.74/vb/08,04,usb,yes,29,32 2006.146.01:29:55.98/vblo/01,629.99,yes,locked 2006.146.01:29:55.98/vblo/02,634.99,yes,locked 2006.146.01:29:55.98/vblo/03,649.99,yes,locked 2006.146.01:29:55.98/vblo/04,679.99,yes,locked 2006.146.01:29:55.98/vblo/05,709.99,yes,locked 2006.146.01:29:55.98/vblo/06,719.99,yes,locked 2006.146.01:29:55.98/vblo/07,734.99,yes,locked 2006.146.01:29:55.98/vblo/08,744.99,yes,locked 2006.146.01:29:56.13/vabw/8 2006.146.01:29:56.28/vbbw/8 2006.146.01:29:56.37/xfe/off,on,14.7 2006.146.01:29:56.77/ifatt/23,28,28,28 2006.146.01:29:57.07/fmout-gps/S +4.2E-08 2006.146.01:29:57.15:!2006.146.01:30:33 2006.146.01:30:33.00:data_valid=off 2006.146.01:30:33.00:"et 2006.146.01:30:33.01:!+3s 2006.146.01:30:36.02:"tape 2006.146.01:30:36.02:postob 2006.146.01:30:36.24/cable/+6.5421E-03 2006.146.01:30:36.24/wx/21.02,1020.0,67 2006.146.01:30:36.31/fmout-gps/S +4.2E-08 2006.146.01:30:36.31:scan_name=146-0136,jd0605,120 2006.146.01:30:36.32:source=2136+141,213901.31,142336.0,2000.0,cw 2006.146.01:30:38.14#flagr#flagr/antenna,new-source 2006.146.01:30:38.14:checkk5 2006.146.01:30:38.57/chk_autoobs//k5ts1/ autoobs is running! 2006.146.01:30:39.02/chk_autoobs//k5ts2/ autoobs is running! 2006.146.01:30:39.46/chk_autoobs//k5ts3/ autoobs is running! 2006.146.01:30:39.90/chk_autoobs//k5ts4/ autoobs is running! 2006.146.01:30:40.35/chk_obsdata//k5ts1/T1460129??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.146.01:30:40.79/chk_obsdata//k5ts2/T1460129??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.146.01:30:41.23/chk_obsdata//k5ts3/T1460129??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.146.01:30:41.67/chk_obsdata//k5ts4/T1460129??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.146.01:30:42.45/k5log//k5ts1_log_newline 2006.146.01:30:43.20/k5log//k5ts2_log_newline 2006.146.01:30:43.94/k5log//k5ts3_log_newline 2006.146.01:30:44.69/k5log//k5ts4_log_newline 2006.146.01:30:44.71/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.146.01:30:44.71:setupk4=1 2006.146.01:30:44.71$setupk4/echo=on 2006.146.01:30:44.71$setupk4/pcalon 2006.146.01:30:44.71$pcalon/"no phase cal control is implemented here 2006.146.01:30:44.71$setupk4/"tpicd=stop 2006.146.01:30:44.71$setupk4/"rec=synch_on 2006.146.01:30:44.71$setupk4/"rec_mode=128 2006.146.01:30:44.71$setupk4/!* 2006.146.01:30:44.71$setupk4/recpk4 2006.146.01:30:44.71$recpk4/recpatch= 2006.146.01:30:44.71$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.146.01:30:44.71$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.146.01:30:44.71$setupk4/vck44 2006.146.01:30:44.71$vck44/valo=1,524.99 2006.146.01:30:44.71#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.146.01:30:44.71#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.146.01:30:44.71#ibcon#ireg 17 cls_cnt 0 2006.146.01:30:44.71#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.146.01:30:44.71#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.146.01:30:44.71#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.146.01:30:44.75#ibcon#[26=FRQ=01,524.99\r\n] 2006.146.01:30:44.80#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.146.01:30:44.80#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.146.01:30:44.80#ibcon#about to clear, iclass 39 cls_cnt 0 2006.146.01:30:44.80#ibcon#cleared, iclass 39 cls_cnt 0 2006.146.01:30:44.80$vck44/va=1,8 2006.146.01:30:44.80#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.146.01:30:44.80#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.146.01:30:44.80#ibcon#ireg 11 cls_cnt 2 2006.146.01:30:44.80#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.146.01:30:44.80#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.146.01:30:44.80#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.146.01:30:44.82#ibcon#[25=AT01-08\r\n] 2006.146.01:30:44.85#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.146.01:30:44.85#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.146.01:30:44.85#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.146.01:30:44.85#ibcon#ireg 7 cls_cnt 0 2006.146.01:30:44.85#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.146.01:30:44.98#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.146.01:30:44.98#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.146.01:30:44.99#ibcon#[25=USB\r\n] 2006.146.01:30:45.02#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.146.01:30:45.02#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.146.01:30:45.02#ibcon#about to clear, iclass 3 cls_cnt 0 2006.146.01:30:45.02#ibcon#cleared, iclass 3 cls_cnt 0 2006.146.01:30:45.02$vck44/valo=2,534.99 2006.146.01:30:45.02#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.146.01:30:45.02#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.146.01:30:45.02#ibcon#ireg 17 cls_cnt 0 2006.146.01:30:45.02#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.146.01:30:45.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.146.01:30:45.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.146.01:30:45.05#ibcon#[26=FRQ=02,534.99\r\n] 2006.146.01:30:45.09#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.146.01:30:45.09#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.146.01:30:45.09#ibcon#about to clear, iclass 5 cls_cnt 0 2006.146.01:30:45.09#ibcon#cleared, iclass 5 cls_cnt 0 2006.146.01:30:45.09$vck44/va=2,7 2006.146.01:30:45.09#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.146.01:30:45.09#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.146.01:30:45.09#ibcon#ireg 11 cls_cnt 2 2006.146.01:30:45.09#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.146.01:30:45.14#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.146.01:30:45.14#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.146.01:30:45.16#ibcon#[25=AT02-07\r\n] 2006.146.01:30:45.19#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.146.01:30:45.19#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.146.01:30:45.19#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.146.01:30:45.19#ibcon#ireg 7 cls_cnt 0 2006.146.01:30:45.19#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.146.01:30:45.31#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.146.01:30:45.31#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.146.01:30:45.33#ibcon#[25=USB\r\n] 2006.146.01:30:45.36#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.146.01:30:45.36#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.146.01:30:45.36#ibcon#about to clear, iclass 7 cls_cnt 0 2006.146.01:30:45.36#ibcon#cleared, iclass 7 cls_cnt 0 2006.146.01:30:45.36$vck44/valo=3,564.99 2006.146.01:30:45.36#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.146.01:30:45.36#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.146.01:30:45.36#ibcon#ireg 17 cls_cnt 0 2006.146.01:30:45.36#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.146.01:30:45.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.146.01:30:45.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.146.01:30:45.38#ibcon#[26=FRQ=03,564.99\r\n] 2006.146.01:30:45.42#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.146.01:30:45.42#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.146.01:30:45.42#ibcon#about to clear, iclass 11 cls_cnt 0 2006.146.01:30:45.42#ibcon#cleared, iclass 11 cls_cnt 0 2006.146.01:30:45.42$vck44/va=3,8 2006.146.01:30:45.42#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.146.01:30:45.42#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.146.01:30:45.42#ibcon#ireg 11 cls_cnt 2 2006.146.01:30:45.42#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.146.01:30:45.48#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.146.01:30:45.48#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.146.01:30:45.50#ibcon#[25=AT03-08\r\n] 2006.146.01:30:45.53#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.146.01:30:45.53#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.146.01:30:45.53#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.146.01:30:45.53#ibcon#ireg 7 cls_cnt 0 2006.146.01:30:45.53#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.146.01:30:45.65#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.146.01:30:45.65#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.146.01:30:45.67#ibcon#[25=USB\r\n] 2006.146.01:30:45.70#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.146.01:30:45.70#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.146.01:30:45.70#ibcon#about to clear, iclass 13 cls_cnt 0 2006.146.01:30:45.70#ibcon#cleared, iclass 13 cls_cnt 0 2006.146.01:30:45.70$vck44/valo=4,624.99 2006.146.01:30:45.70#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.146.01:30:45.70#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.146.01:30:45.70#ibcon#ireg 17 cls_cnt 0 2006.146.01:30:45.70#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.146.01:30:45.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.146.01:30:45.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.146.01:30:45.72#ibcon#[26=FRQ=04,624.99\r\n] 2006.146.01:30:45.76#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.146.01:30:45.76#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.146.01:30:45.76#ibcon#about to clear, iclass 15 cls_cnt 0 2006.146.01:30:45.76#ibcon#cleared, iclass 15 cls_cnt 0 2006.146.01:30:45.76$vck44/va=4,7 2006.146.01:30:45.76#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.146.01:30:45.76#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.146.01:30:45.76#ibcon#ireg 11 cls_cnt 2 2006.146.01:30:45.76#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.146.01:30:45.82#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.146.01:30:45.82#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.146.01:30:45.84#ibcon#[25=AT04-07\r\n] 2006.146.01:30:45.87#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.146.01:30:45.87#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.146.01:30:45.87#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.146.01:30:45.87#ibcon#ireg 7 cls_cnt 0 2006.146.01:30:45.87#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.146.01:30:45.99#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.146.01:30:45.99#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.146.01:30:46.01#ibcon#[25=USB\r\n] 2006.146.01:30:46.04#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.146.01:30:46.04#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.146.01:30:46.04#ibcon#about to clear, iclass 17 cls_cnt 0 2006.146.01:30:46.04#ibcon#cleared, iclass 17 cls_cnt 0 2006.146.01:30:46.04$vck44/valo=5,734.99 2006.146.01:30:46.04#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.146.01:30:46.04#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.146.01:30:46.04#ibcon#ireg 17 cls_cnt 0 2006.146.01:30:46.04#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.146.01:30:46.04#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.146.01:30:46.04#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.146.01:30:46.06#ibcon#[26=FRQ=05,734.99\r\n] 2006.146.01:30:46.10#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.146.01:30:46.10#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.146.01:30:46.10#ibcon#about to clear, iclass 19 cls_cnt 0 2006.146.01:30:46.10#ibcon#cleared, iclass 19 cls_cnt 0 2006.146.01:30:46.10$vck44/va=5,4 2006.146.01:30:46.10#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.146.01:30:46.10#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.146.01:30:46.10#ibcon#ireg 11 cls_cnt 2 2006.146.01:30:46.10#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.146.01:30:46.16#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.146.01:30:46.16#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.146.01:30:46.18#ibcon#[25=AT05-04\r\n] 2006.146.01:30:46.21#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.146.01:30:46.21#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.146.01:30:46.21#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.146.01:30:46.21#ibcon#ireg 7 cls_cnt 0 2006.146.01:30:46.21#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.146.01:30:46.33#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.146.01:30:46.33#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.146.01:30:46.35#ibcon#[25=USB\r\n] 2006.146.01:30:46.38#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.146.01:30:46.38#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.146.01:30:46.38#ibcon#about to clear, iclass 21 cls_cnt 0 2006.146.01:30:46.38#ibcon#cleared, iclass 21 cls_cnt 0 2006.146.01:30:46.38$vck44/valo=6,814.99 2006.146.01:30:46.38#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.146.01:30:46.38#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.146.01:30:46.38#ibcon#ireg 17 cls_cnt 0 2006.146.01:30:46.38#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.146.01:30:46.38#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.146.01:30:46.38#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.146.01:30:46.40#ibcon#[26=FRQ=06,814.99\r\n] 2006.146.01:30:46.44#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.146.01:30:46.44#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.146.01:30:46.44#ibcon#about to clear, iclass 23 cls_cnt 0 2006.146.01:30:46.44#ibcon#cleared, iclass 23 cls_cnt 0 2006.146.01:30:46.44$vck44/va=6,4 2006.146.01:30:46.44#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.146.01:30:46.44#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.146.01:30:46.44#ibcon#ireg 11 cls_cnt 2 2006.146.01:30:46.44#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.146.01:30:46.50#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.146.01:30:46.50#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.146.01:30:46.52#ibcon#[25=AT06-04\r\n] 2006.146.01:30:46.55#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.146.01:30:46.55#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.146.01:30:46.55#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.146.01:30:46.55#ibcon#ireg 7 cls_cnt 0 2006.146.01:30:46.55#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.146.01:30:46.67#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.146.01:30:46.67#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.146.01:30:46.69#ibcon#[25=USB\r\n] 2006.146.01:30:46.72#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.146.01:30:46.72#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.146.01:30:46.72#ibcon#about to clear, iclass 25 cls_cnt 0 2006.146.01:30:46.72#ibcon#cleared, iclass 25 cls_cnt 0 2006.146.01:30:46.72$vck44/valo=7,864.99 2006.146.01:30:46.72#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.146.01:30:46.72#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.146.01:30:46.72#ibcon#ireg 17 cls_cnt 0 2006.146.01:30:46.72#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.146.01:30:46.72#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.146.01:30:46.72#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.146.01:30:46.74#ibcon#[26=FRQ=07,864.99\r\n] 2006.146.01:30:46.78#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.146.01:30:46.78#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.146.01:30:46.78#ibcon#about to clear, iclass 27 cls_cnt 0 2006.146.01:30:46.78#ibcon#cleared, iclass 27 cls_cnt 0 2006.146.01:30:46.78$vck44/va=7,4 2006.146.01:30:46.78#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.146.01:30:46.78#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.146.01:30:46.78#ibcon#ireg 11 cls_cnt 2 2006.146.01:30:46.78#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.146.01:30:46.84#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.146.01:30:46.84#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.146.01:30:46.86#ibcon#[25=AT07-04\r\n] 2006.146.01:30:46.89#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.146.01:30:46.89#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.146.01:30:46.89#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.146.01:30:46.89#ibcon#ireg 7 cls_cnt 0 2006.146.01:30:46.89#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.146.01:30:47.01#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.146.01:30:47.01#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.146.01:30:47.03#ibcon#[25=USB\r\n] 2006.146.01:30:47.06#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.146.01:30:47.06#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.146.01:30:47.06#ibcon#about to clear, iclass 29 cls_cnt 0 2006.146.01:30:47.06#ibcon#cleared, iclass 29 cls_cnt 0 2006.146.01:30:47.06$vck44/valo=8,884.99 2006.146.01:30:47.06#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.146.01:30:47.06#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.146.01:30:47.06#ibcon#ireg 17 cls_cnt 0 2006.146.01:30:47.06#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.146.01:30:47.06#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.146.01:30:47.06#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.146.01:30:47.08#ibcon#[26=FRQ=08,884.99\r\n] 2006.146.01:30:47.12#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.146.01:30:47.12#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.146.01:30:47.12#ibcon#about to clear, iclass 31 cls_cnt 0 2006.146.01:30:47.12#ibcon#cleared, iclass 31 cls_cnt 0 2006.146.01:30:47.12$vck44/va=8,4 2006.146.01:30:47.12#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.146.01:30:47.12#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.146.01:30:47.12#ibcon#ireg 11 cls_cnt 2 2006.146.01:30:47.12#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.146.01:30:47.18#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.146.01:30:47.18#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.146.01:30:47.20#ibcon#[25=AT08-04\r\n] 2006.146.01:30:47.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.146.01:30:47.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.146.01:30:47.23#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.146.01:30:47.23#ibcon#ireg 7 cls_cnt 0 2006.146.01:30:47.23#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.146.01:30:47.35#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.146.01:30:47.35#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.146.01:30:47.37#ibcon#[25=USB\r\n] 2006.146.01:30:47.40#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.146.01:30:47.40#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.146.01:30:47.40#ibcon#about to clear, iclass 33 cls_cnt 0 2006.146.01:30:47.40#ibcon#cleared, iclass 33 cls_cnt 0 2006.146.01:30:47.40$vck44/vblo=1,629.99 2006.146.01:30:47.40#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.146.01:30:47.40#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.146.01:30:47.40#ibcon#ireg 17 cls_cnt 0 2006.146.01:30:47.40#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.146.01:30:47.40#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.146.01:30:47.40#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.146.01:30:47.42#ibcon#[28=FRQ=01,629.99\r\n] 2006.146.01:30:47.46#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.146.01:30:47.46#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.146.01:30:47.46#ibcon#about to clear, iclass 35 cls_cnt 0 2006.146.01:30:47.46#ibcon#cleared, iclass 35 cls_cnt 0 2006.146.01:30:47.46$vck44/vb=1,3 2006.146.01:30:47.46#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.146.01:30:47.46#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.146.01:30:47.46#ibcon#ireg 11 cls_cnt 2 2006.146.01:30:47.46#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.146.01:30:47.46#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.146.01:30:47.46#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.146.01:30:47.48#ibcon#[27=AT01-03\r\n] 2006.146.01:30:47.51#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.146.01:30:47.51#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.146.01:30:47.51#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.146.01:30:47.51#ibcon#ireg 7 cls_cnt 0 2006.146.01:30:47.51#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.146.01:30:47.63#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.146.01:30:47.63#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.146.01:30:47.65#ibcon#[27=USB\r\n] 2006.146.01:30:47.68#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.146.01:30:47.68#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.146.01:30:47.68#ibcon#about to clear, iclass 37 cls_cnt 0 2006.146.01:30:47.68#ibcon#cleared, iclass 37 cls_cnt 0 2006.146.01:30:47.68$vck44/vblo=2,634.99 2006.146.01:30:47.68#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.146.01:30:47.68#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.146.01:30:47.68#ibcon#ireg 17 cls_cnt 0 2006.146.01:30:47.68#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.146.01:30:47.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.146.01:30:47.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.146.01:30:47.70#ibcon#[28=FRQ=02,634.99\r\n] 2006.146.01:30:47.74#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.146.01:30:47.74#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.146.01:30:47.74#ibcon#about to clear, iclass 39 cls_cnt 0 2006.146.01:30:47.74#ibcon#cleared, iclass 39 cls_cnt 0 2006.146.01:30:47.74$vck44/vb=2,4 2006.146.01:30:47.74#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.146.01:30:47.74#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.146.01:30:47.74#ibcon#ireg 11 cls_cnt 2 2006.146.01:30:47.74#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.146.01:30:47.80#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.146.01:30:47.80#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.146.01:30:47.82#ibcon#[27=AT02-04\r\n] 2006.146.01:30:47.85#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.146.01:30:47.85#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.146.01:30:47.85#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.146.01:30:47.85#ibcon#ireg 7 cls_cnt 0 2006.146.01:30:47.85#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.146.01:30:47.97#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.146.01:30:47.97#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.146.01:30:47.99#ibcon#[27=USB\r\n] 2006.146.01:30:48.02#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.146.01:30:48.02#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.146.01:30:48.02#ibcon#about to clear, iclass 3 cls_cnt 0 2006.146.01:30:48.02#ibcon#cleared, iclass 3 cls_cnt 0 2006.146.01:30:48.02$vck44/vblo=3,649.99 2006.146.01:30:48.02#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.146.01:30:48.02#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.146.01:30:48.02#ibcon#ireg 17 cls_cnt 0 2006.146.01:30:48.02#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.146.01:30:48.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.146.01:30:48.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.146.01:30:48.04#ibcon#[28=FRQ=03,649.99\r\n] 2006.146.01:30:48.08#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.146.01:30:48.08#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.146.01:30:48.08#ibcon#about to clear, iclass 5 cls_cnt 0 2006.146.01:30:48.08#ibcon#cleared, iclass 5 cls_cnt 0 2006.146.01:30:48.08$vck44/vb=3,4 2006.146.01:30:48.08#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.146.01:30:48.08#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.146.01:30:48.08#ibcon#ireg 11 cls_cnt 2 2006.146.01:30:48.08#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.146.01:30:48.14#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.146.01:30:48.14#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.146.01:30:48.16#ibcon#[27=AT03-04\r\n] 2006.146.01:30:48.19#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.146.01:30:48.19#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.146.01:30:48.19#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.146.01:30:48.19#ibcon#ireg 7 cls_cnt 0 2006.146.01:30:48.19#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.146.01:30:48.31#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.146.01:30:48.31#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.146.01:30:48.33#ibcon#[27=USB\r\n] 2006.146.01:30:48.36#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.146.01:30:48.36#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.146.01:30:48.36#ibcon#about to clear, iclass 7 cls_cnt 0 2006.146.01:30:48.36#ibcon#cleared, iclass 7 cls_cnt 0 2006.146.01:30:48.36$vck44/vblo=4,679.99 2006.146.01:30:48.36#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.146.01:30:48.36#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.146.01:30:48.36#ibcon#ireg 17 cls_cnt 0 2006.146.01:30:48.36#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.146.01:30:48.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.146.01:30:48.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.146.01:30:48.38#ibcon#[28=FRQ=04,679.99\r\n] 2006.146.01:30:48.42#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.146.01:30:48.42#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.146.01:30:48.42#ibcon#about to clear, iclass 11 cls_cnt 0 2006.146.01:30:48.42#ibcon#cleared, iclass 11 cls_cnt 0 2006.146.01:30:48.42$vck44/vb=4,4 2006.146.01:30:48.42#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.146.01:30:48.42#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.146.01:30:48.42#ibcon#ireg 11 cls_cnt 2 2006.146.01:30:48.42#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.146.01:30:48.48#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.146.01:30:48.48#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.146.01:30:48.50#ibcon#[27=AT04-04\r\n] 2006.146.01:30:48.53#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.146.01:30:48.53#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.146.01:30:48.53#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.146.01:30:48.53#ibcon#ireg 7 cls_cnt 0 2006.146.01:30:48.53#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.146.01:30:48.65#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.146.01:30:48.65#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.146.01:30:48.67#ibcon#[27=USB\r\n] 2006.146.01:30:48.70#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.146.01:30:48.70#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.146.01:30:48.70#ibcon#about to clear, iclass 13 cls_cnt 0 2006.146.01:30:48.70#ibcon#cleared, iclass 13 cls_cnt 0 2006.146.01:30:48.70$vck44/vblo=5,709.99 2006.146.01:30:48.70#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.146.01:30:48.70#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.146.01:30:48.70#ibcon#ireg 17 cls_cnt 0 2006.146.01:30:48.70#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.146.01:30:48.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.146.01:30:48.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.146.01:30:48.72#ibcon#[28=FRQ=05,709.99\r\n] 2006.146.01:30:48.76#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.146.01:30:48.76#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.146.01:30:48.76#ibcon#about to clear, iclass 15 cls_cnt 0 2006.146.01:30:48.76#ibcon#cleared, iclass 15 cls_cnt 0 2006.146.01:30:48.76$vck44/vb=5,4 2006.146.01:30:48.76#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.146.01:30:48.76#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.146.01:30:48.76#ibcon#ireg 11 cls_cnt 2 2006.146.01:30:48.76#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.146.01:30:48.82#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.146.01:30:48.82#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.146.01:30:48.84#ibcon#[27=AT05-04\r\n] 2006.146.01:30:48.87#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.146.01:30:48.87#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.146.01:30:48.87#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.146.01:30:48.87#ibcon#ireg 7 cls_cnt 0 2006.146.01:30:48.87#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.146.01:30:48.99#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.146.01:30:48.99#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.146.01:30:49.01#ibcon#[27=USB\r\n] 2006.146.01:30:49.04#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.146.01:30:49.04#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.146.01:30:49.04#ibcon#about to clear, iclass 17 cls_cnt 0 2006.146.01:30:49.04#ibcon#cleared, iclass 17 cls_cnt 0 2006.146.01:30:49.04$vck44/vblo=6,719.99 2006.146.01:30:49.04#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.146.01:30:49.04#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.146.01:30:49.04#ibcon#ireg 17 cls_cnt 0 2006.146.01:30:49.04#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.146.01:30:49.04#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.146.01:30:49.04#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.146.01:30:49.06#ibcon#[28=FRQ=06,719.99\r\n] 2006.146.01:30:49.10#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.146.01:30:49.10#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.146.01:30:49.10#ibcon#about to clear, iclass 19 cls_cnt 0 2006.146.01:30:49.10#ibcon#cleared, iclass 19 cls_cnt 0 2006.146.01:30:49.10$vck44/vb=6,4 2006.146.01:30:49.10#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.146.01:30:49.10#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.146.01:30:49.10#ibcon#ireg 11 cls_cnt 2 2006.146.01:30:49.10#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.146.01:30:49.16#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.146.01:30:49.16#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.146.01:30:49.18#ibcon#[27=AT06-04\r\n] 2006.146.01:30:49.21#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.146.01:30:49.21#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.146.01:30:49.21#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.146.01:30:49.21#ibcon#ireg 7 cls_cnt 0 2006.146.01:30:49.21#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.146.01:30:49.33#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.146.01:30:49.33#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.146.01:30:49.35#ibcon#[27=USB\r\n] 2006.146.01:30:49.38#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.146.01:30:49.38#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.146.01:30:49.38#ibcon#about to clear, iclass 21 cls_cnt 0 2006.146.01:30:49.38#ibcon#cleared, iclass 21 cls_cnt 0 2006.146.01:30:49.38$vck44/vblo=7,734.99 2006.146.01:30:49.38#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.146.01:30:49.38#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.146.01:30:49.38#ibcon#ireg 17 cls_cnt 0 2006.146.01:30:49.38#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.146.01:30:49.38#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.146.01:30:49.38#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.146.01:30:49.40#ibcon#[28=FRQ=07,734.99\r\n] 2006.146.01:30:49.44#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.146.01:30:49.44#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.146.01:30:49.44#ibcon#about to clear, iclass 23 cls_cnt 0 2006.146.01:30:49.44#ibcon#cleared, iclass 23 cls_cnt 0 2006.146.01:30:49.44$vck44/vb=7,4 2006.146.01:30:49.44#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.146.01:30:49.44#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.146.01:30:49.44#ibcon#ireg 11 cls_cnt 2 2006.146.01:30:49.44#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.146.01:30:49.50#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.146.01:30:49.50#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.146.01:30:49.52#ibcon#[27=AT07-04\r\n] 2006.146.01:30:49.55#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.146.01:30:49.55#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.146.01:30:49.55#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.146.01:30:49.55#ibcon#ireg 7 cls_cnt 0 2006.146.01:30:49.55#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.146.01:30:49.67#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.146.01:30:49.67#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.146.01:30:49.69#ibcon#[27=USB\r\n] 2006.146.01:30:49.72#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.146.01:30:49.72#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.146.01:30:49.72#ibcon#about to clear, iclass 25 cls_cnt 0 2006.146.01:30:49.72#ibcon#cleared, iclass 25 cls_cnt 0 2006.146.01:30:49.72$vck44/vblo=8,744.99 2006.146.01:30:49.72#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.146.01:30:49.72#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.146.01:30:49.72#ibcon#ireg 17 cls_cnt 0 2006.146.01:30:49.72#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.146.01:30:49.72#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.146.01:30:49.72#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.146.01:30:49.74#ibcon#[28=FRQ=08,744.99\r\n] 2006.146.01:30:49.78#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.146.01:30:49.78#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.146.01:30:49.78#ibcon#about to clear, iclass 27 cls_cnt 0 2006.146.01:30:49.78#ibcon#cleared, iclass 27 cls_cnt 0 2006.146.01:30:49.78$vck44/vb=8,4 2006.146.01:30:49.78#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.146.01:30:49.78#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.146.01:30:49.78#ibcon#ireg 11 cls_cnt 2 2006.146.01:30:49.78#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.146.01:30:49.84#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.146.01:30:49.84#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.146.01:30:49.86#ibcon#[27=AT08-04\r\n] 2006.146.01:30:49.89#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.146.01:30:49.89#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.146.01:30:49.89#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.146.01:30:49.89#ibcon#ireg 7 cls_cnt 0 2006.146.01:30:49.89#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.146.01:30:50.01#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.146.01:30:50.01#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.146.01:30:50.03#ibcon#[27=USB\r\n] 2006.146.01:30:50.06#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.146.01:30:50.06#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.146.01:30:50.06#ibcon#about to clear, iclass 29 cls_cnt 0 2006.146.01:30:50.06#ibcon#cleared, iclass 29 cls_cnt 0 2006.146.01:30:50.06$vck44/vabw=wide 2006.146.01:30:50.06#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.146.01:30:50.06#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.146.01:30:50.06#ibcon#ireg 8 cls_cnt 0 2006.146.01:30:50.06#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.146.01:30:50.06#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.146.01:30:50.06#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.146.01:30:50.08#ibcon#[25=BW32\r\n] 2006.146.01:30:50.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.146.01:30:50.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.146.01:30:50.11#ibcon#about to clear, iclass 31 cls_cnt 0 2006.146.01:30:50.11#ibcon#cleared, iclass 31 cls_cnt 0 2006.146.01:30:50.11$vck44/vbbw=wide 2006.146.01:30:50.11#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.146.01:30:50.11#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.146.01:30:50.11#ibcon#ireg 8 cls_cnt 0 2006.146.01:30:50.11#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.146.01:30:50.18#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.146.01:30:50.18#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.146.01:30:50.20#ibcon#[27=BW32\r\n] 2006.146.01:30:50.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.146.01:30:50.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.146.01:30:50.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.146.01:30:50.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.146.01:30:50.23$setupk4/ifdk4 2006.146.01:30:50.23$ifdk4/lo= 2006.146.01:30:50.23$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.146.01:30:50.23$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.146.01:30:50.23$ifdk4/patch= 2006.146.01:30:50.23$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.146.01:30:50.23$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.146.01:30:50.23$setupk4/!*+20s 2006.146.01:30:53.67#abcon#<5=/09 2.3 6.2 21.03 661020.1\r\n> 2006.146.01:30:53.69#abcon#{5=INTERFACE CLEAR} 2006.146.01:30:53.75#abcon#[5=S1D000X0/0*\r\n] 2006.146.01:30:55.14#trakl#Source acquired 2006.146.01:30:57.14#flagr#flagr/antenna,acquired 2006.146.01:31:03.84#abcon#<5=/08 2.2 6.2 21.03 661020.0\r\n> 2006.146.01:31:03.86#abcon#{5=INTERFACE CLEAR} 2006.146.01:31:03.92#abcon#[5=S1D000X0/0*\r\n] 2006.146.01:31:04.72$setupk4/"tpicd 2006.146.01:31:04.72$setupk4/echo=off 2006.146.01:31:04.72$setupk4/xlog=off 2006.146.01:31:04.72:!2006.146.01:36:39 2006.146.01:36:39.00:preob 2006.146.01:36:40.14/onsource/TRACKING 2006.146.01:36:40.14:!2006.146.01:36:49 2006.146.01:36:49.00:"tape 2006.146.01:36:49.00:"st=record 2006.146.01:36:49.00:data_valid=on 2006.146.01:36:49.00:midob 2006.146.01:36:49.14/onsource/TRACKING 2006.146.01:36:49.14/wx/21.09,1019.9,67 2006.146.01:36:49.25/cable/+6.5395E-03 2006.146.01:36:50.34/va/01,08,usb,yes,32,34 2006.146.01:36:50.34/va/02,07,usb,yes,34,35 2006.146.01:36:50.34/va/03,08,usb,yes,31,32 2006.146.01:36:50.34/va/04,07,usb,yes,35,37 2006.146.01:36:50.34/va/05,04,usb,yes,31,31 2006.146.01:36:50.34/va/06,04,usb,yes,34,34 2006.146.01:36:50.34/va/07,04,usb,yes,35,36 2006.146.01:36:50.34/va/08,04,usb,yes,29,35 2006.146.01:36:50.57/valo/01,524.99,yes,locked 2006.146.01:36:50.57/valo/02,534.99,yes,locked 2006.146.01:36:50.57/valo/03,564.99,yes,locked 2006.146.01:36:50.57/valo/04,624.99,yes,locked 2006.146.01:36:50.57/valo/05,734.99,yes,locked 2006.146.01:36:50.57/valo/06,814.99,yes,locked 2006.146.01:36:50.57/valo/07,864.99,yes,locked 2006.146.01:36:50.57/valo/08,884.99,yes,locked 2006.146.01:36:51.66/vb/01,03,usb,yes,38,35 2006.146.01:36:51.66/vb/02,04,usb,yes,33,33 2006.146.01:36:51.66/vb/03,04,usb,yes,30,33 2006.146.01:36:51.66/vb/04,04,usb,yes,34,33 2006.146.01:36:51.66/vb/05,04,usb,yes,27,29 2006.146.01:36:51.66/vb/06,04,usb,yes,31,28 2006.146.01:36:51.66/vb/07,04,usb,yes,31,31 2006.146.01:36:51.66/vb/08,04,usb,yes,29,32 2006.146.01:36:51.90/vblo/01,629.99,yes,locked 2006.146.01:36:51.90/vblo/02,634.99,yes,locked 2006.146.01:36:51.90/vblo/03,649.99,yes,locked 2006.146.01:36:51.90/vblo/04,679.99,yes,locked 2006.146.01:36:51.90/vblo/05,709.99,yes,locked 2006.146.01:36:51.90/vblo/06,719.99,yes,locked 2006.146.01:36:51.90/vblo/07,734.99,yes,locked 2006.146.01:36:51.90/vblo/08,744.99,yes,locked 2006.146.01:36:52.05/vabw/8 2006.146.01:36:52.22/vbbw/8 2006.146.01:36:52.31/xfe/off,on,14.5 2006.146.01:36:52.69/ifatt/23,28,28,28 2006.146.01:36:53.07/fmout-gps/S +4.2E-08 2006.146.01:36:53.15:!2006.146.01:38:49 2006.146.01:38:49.00:data_valid=off 2006.146.01:38:49.00:"et 2006.146.01:38:49.01:!+3s 2006.146.01:38:52.02:"tape 2006.146.01:38:52.02:postob 2006.146.01:38:52.10/cable/+6.5418E-03 2006.146.01:38:52.10/wx/21.14,1019.8,68 2006.146.01:38:53.08/fmout-gps/S +4.3E-08 2006.146.01:38:53.08:scan_name=146-0144,jd0605,150 2006.146.01:38:53.09:source=2201+315,220314.98,314538.3,2000.0,cw 2006.146.01:38:53.14#flagr#flagr/antenna,new-source 2006.146.01:38:54.14:checkk5 2006.146.01:38:54.82/chk_autoobs//k5ts1/ autoobs is running! 2006.146.01:38:55.35/chk_autoobs//k5ts2/ autoobs is running! 2006.146.01:38:55.81/chk_autoobs//k5ts3/ autoobs is running! 2006.146.01:38:56.38/chk_autoobs//k5ts4/ autoobs is running! 2006.146.01:38:56.93/chk_obsdata//k5ts1/T1460136??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.146.01:38:57.41/chk_obsdata//k5ts2/T1460136??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.146.01:38:57.89/chk_obsdata//k5ts3/T1460136??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.146.01:38:58.41/chk_obsdata//k5ts4/T1460136??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.146.01:38:59.53/k5log//k5ts1_log_newline 2006.146.01:39:00.53/k5log//k5ts2_log_newline 2006.146.01:39:01.71/k5log//k5ts3_log_newline 2006.146.01:39:02.84/k5log//k5ts4_log_newline 2006.146.01:39:02.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.146.01:39:02.86:setupk4=1 2006.146.01:39:02.86$setupk4/echo=on 2006.146.01:39:02.86$setupk4/pcalon 2006.146.01:39:02.86$pcalon/"no phase cal control is implemented here 2006.146.01:39:02.86$setupk4/"tpicd=stop 2006.146.01:39:02.86$setupk4/"rec=synch_on 2006.146.01:39:02.86$setupk4/"rec_mode=128 2006.146.01:39:02.86$setupk4/!* 2006.146.01:39:02.86$setupk4/recpk4 2006.146.01:39:02.86$recpk4/recpatch= 2006.146.01:39:02.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.146.01:39:02.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.146.01:39:02.87$setupk4/vck44 2006.146.01:39:02.87$vck44/valo=1,524.99 2006.146.01:39:02.87#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.146.01:39:02.87#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.146.01:39:02.87#ibcon#ireg 17 cls_cnt 0 2006.146.01:39:02.87#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.146.01:39:02.87#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.146.01:39:02.87#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.146.01:39:02.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.146.01:39:02.96#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.146.01:39:02.96#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.146.01:39:02.96#ibcon#about to clear, iclass 7 cls_cnt 0 2006.146.01:39:02.96#ibcon#cleared, iclass 7 cls_cnt 0 2006.146.01:39:02.96$vck44/va=1,8 2006.146.01:39:02.96#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.146.01:39:02.96#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.146.01:39:02.96#ibcon#ireg 11 cls_cnt 2 2006.146.01:39:02.96#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.146.01:39:02.96#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.146.01:39:02.96#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.146.01:39:02.98#ibcon#[25=AT01-08\r\n] 2006.146.01:39:03.01#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.146.01:39:03.01#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.146.01:39:03.01#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.146.01:39:03.01#ibcon#ireg 7 cls_cnt 0 2006.146.01:39:03.01#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.146.01:39:03.13#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.146.01:39:03.13#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.146.01:39:03.15#ibcon#[25=USB\r\n] 2006.146.01:39:03.20#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.146.01:39:03.20#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.146.01:39:03.20#ibcon#about to clear, iclass 11 cls_cnt 0 2006.146.01:39:03.20#ibcon#cleared, iclass 11 cls_cnt 0 2006.146.01:39:03.20$vck44/valo=2,534.99 2006.146.01:39:03.20#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.146.01:39:03.20#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.146.01:39:03.20#ibcon#ireg 17 cls_cnt 0 2006.146.01:39:03.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.146.01:39:03.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.146.01:39:03.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.146.01:39:03.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.146.01:39:03.25#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.146.01:39:03.25#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.146.01:39:03.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.146.01:39:03.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.146.01:39:03.25$vck44/va=2,7 2006.146.01:39:03.25#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.146.01:39:03.25#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.146.01:39:03.25#ibcon#ireg 11 cls_cnt 2 2006.146.01:39:03.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.146.01:39:03.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.146.01:39:03.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.146.01:39:03.34#ibcon#[25=AT02-07\r\n] 2006.146.01:39:03.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.146.01:39:03.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.146.01:39:03.37#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.146.01:39:03.37#ibcon#ireg 7 cls_cnt 0 2006.146.01:39:03.37#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.146.01:39:03.49#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.146.01:39:03.49#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.146.01:39:03.51#ibcon#[25=USB\r\n] 2006.146.01:39:03.54#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.146.01:39:03.54#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.146.01:39:03.54#ibcon#about to clear, iclass 15 cls_cnt 0 2006.146.01:39:03.54#ibcon#cleared, iclass 15 cls_cnt 0 2006.146.01:39:03.54$vck44/valo=3,564.99 2006.146.01:39:03.54#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.146.01:39:03.54#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.146.01:39:03.54#ibcon#ireg 17 cls_cnt 0 2006.146.01:39:03.54#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.146.01:39:03.54#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.146.01:39:03.54#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.146.01:39:03.57#ibcon#[26=FRQ=03,564.99\r\n] 2006.146.01:39:03.61#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.146.01:39:03.61#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.146.01:39:03.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.146.01:39:03.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.146.01:39:03.61$vck44/va=3,8 2006.146.01:39:03.61#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.146.01:39:03.61#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.146.01:39:03.61#ibcon#ireg 11 cls_cnt 2 2006.146.01:39:03.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.146.01:39:03.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.146.01:39:03.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.146.01:39:03.68#ibcon#[25=AT03-08\r\n] 2006.146.01:39:03.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.146.01:39:03.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.146.01:39:03.71#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.146.01:39:03.71#ibcon#ireg 7 cls_cnt 0 2006.146.01:39:03.71#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.146.01:39:03.83#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.146.01:39:03.83#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.146.01:39:03.85#ibcon#[25=USB\r\n] 2006.146.01:39:03.88#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.146.01:39:03.88#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.146.01:39:03.88#ibcon#about to clear, iclass 19 cls_cnt 0 2006.146.01:39:03.88#ibcon#cleared, iclass 19 cls_cnt 0 2006.146.01:39:03.88$vck44/valo=4,624.99 2006.146.01:39:03.88#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.146.01:39:03.88#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.146.01:39:03.88#ibcon#ireg 17 cls_cnt 0 2006.146.01:39:03.88#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.146.01:39:03.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.146.01:39:03.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.146.01:39:03.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.146.01:39:03.94#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.146.01:39:03.94#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.146.01:39:03.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.146.01:39:03.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.146.01:39:03.94$vck44/va=4,7 2006.146.01:39:03.94#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.146.01:39:03.94#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.146.01:39:03.94#ibcon#ireg 11 cls_cnt 2 2006.146.01:39:03.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.146.01:39:04.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.146.01:39:04.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.146.01:39:04.02#ibcon#[25=AT04-07\r\n] 2006.146.01:39:04.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.146.01:39:04.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.146.01:39:04.05#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.146.01:39:04.05#ibcon#ireg 7 cls_cnt 0 2006.146.01:39:04.05#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.146.01:39:04.17#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.146.01:39:04.17#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.146.01:39:04.19#ibcon#[25=USB\r\n] 2006.146.01:39:04.22#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.146.01:39:04.22#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.146.01:39:04.22#ibcon#about to clear, iclass 23 cls_cnt 0 2006.146.01:39:04.22#ibcon#cleared, iclass 23 cls_cnt 0 2006.146.01:39:04.22$vck44/valo=5,734.99 2006.146.01:39:04.22#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.146.01:39:04.22#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.146.01:39:04.22#ibcon#ireg 17 cls_cnt 0 2006.146.01:39:04.22#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.146.01:39:04.22#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.146.01:39:04.22#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.146.01:39:04.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.146.01:39:04.28#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.146.01:39:04.28#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.146.01:39:04.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.146.01:39:04.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.146.01:39:04.28$vck44/va=5,4 2006.146.01:39:04.28#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.146.01:39:04.28#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.146.01:39:04.28#ibcon#ireg 11 cls_cnt 2 2006.146.01:39:04.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.146.01:39:04.34#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.146.01:39:04.34#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.146.01:39:04.36#ibcon#[25=AT05-04\r\n] 2006.146.01:39:04.39#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.146.01:39:04.39#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.146.01:39:04.39#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.146.01:39:04.39#ibcon#ireg 7 cls_cnt 0 2006.146.01:39:04.39#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.146.01:39:04.51#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.146.01:39:04.51#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.146.01:39:04.53#ibcon#[25=USB\r\n] 2006.146.01:39:04.56#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.146.01:39:04.56#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.146.01:39:04.56#ibcon#about to clear, iclass 27 cls_cnt 0 2006.146.01:39:04.56#ibcon#cleared, iclass 27 cls_cnt 0 2006.146.01:39:04.56$vck44/valo=6,814.99 2006.146.01:39:04.56#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.146.01:39:04.56#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.146.01:39:04.56#ibcon#ireg 17 cls_cnt 0 2006.146.01:39:04.56#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.146.01:39:04.56#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.146.01:39:04.56#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.146.01:39:04.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.146.01:39:04.62#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.146.01:39:04.62#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.146.01:39:04.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.146.01:39:04.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.146.01:39:04.62$vck44/va=6,4 2006.146.01:39:04.62#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.146.01:39:04.62#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.146.01:39:04.62#ibcon#ireg 11 cls_cnt 2 2006.146.01:39:04.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.146.01:39:04.66#abcon#<5=/08 1.7 5.8 21.15 661019.8\r\n> 2006.146.01:39:04.68#abcon#{5=INTERFACE CLEAR} 2006.146.01:39:04.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.146.01:39:04.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.146.01:39:04.70#ibcon#[25=AT06-04\r\n] 2006.146.01:39:04.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.146.01:39:04.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.146.01:39:04.73#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.146.01:39:04.73#ibcon#ireg 7 cls_cnt 0 2006.146.01:39:04.73#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.146.01:39:04.74#abcon#[5=S1D000X0/0*\r\n] 2006.146.01:39:04.85#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.146.01:39:04.85#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.146.01:39:04.87#ibcon#[25=USB\r\n] 2006.146.01:39:04.90#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.146.01:39:04.90#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.146.01:39:04.90#ibcon#about to clear, iclass 32 cls_cnt 0 2006.146.01:39:04.90#ibcon#cleared, iclass 32 cls_cnt 0 2006.146.01:39:04.90$vck44/valo=7,864.99 2006.146.01:39:04.90#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.146.01:39:04.90#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.146.01:39:04.90#ibcon#ireg 17 cls_cnt 0 2006.146.01:39:04.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.146.01:39:04.90#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.146.01:39:04.90#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.146.01:39:04.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.146.01:39:04.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.146.01:39:04.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.146.01:39:04.96#ibcon#about to clear, iclass 37 cls_cnt 0 2006.146.01:39:04.96#ibcon#cleared, iclass 37 cls_cnt 0 2006.146.01:39:04.96$vck44/va=7,4 2006.146.01:39:04.96#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.146.01:39:04.96#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.146.01:39:04.96#ibcon#ireg 11 cls_cnt 2 2006.146.01:39:04.96#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.146.01:39:05.02#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.146.01:39:05.02#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.146.01:39:05.04#ibcon#[25=AT07-04\r\n] 2006.146.01:39:05.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.146.01:39:05.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.146.01:39:05.07#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.146.01:39:05.07#ibcon#ireg 7 cls_cnt 0 2006.146.01:39:05.07#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.146.01:39:05.19#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.146.01:39:05.19#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.146.01:39:05.21#ibcon#[25=USB\r\n] 2006.146.01:39:05.24#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.146.01:39:05.24#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.146.01:39:05.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.146.01:39:05.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.146.01:39:05.24$vck44/valo=8,884.99 2006.146.01:39:05.24#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.146.01:39:05.24#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.146.01:39:05.24#ibcon#ireg 17 cls_cnt 0 2006.146.01:39:05.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.146.01:39:05.24#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.146.01:39:05.24#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.146.01:39:05.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.146.01:39:05.30#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.146.01:39:05.30#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.146.01:39:05.30#ibcon#about to clear, iclass 3 cls_cnt 0 2006.146.01:39:05.30#ibcon#cleared, iclass 3 cls_cnt 0 2006.146.01:39:05.30$vck44/va=8,4 2006.146.01:39:05.30#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.146.01:39:05.30#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.146.01:39:05.30#ibcon#ireg 11 cls_cnt 2 2006.146.01:39:05.30#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.146.01:39:05.36#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.146.01:39:05.36#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.146.01:39:05.38#ibcon#[25=AT08-04\r\n] 2006.146.01:39:05.41#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.146.01:39:05.41#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.146.01:39:05.41#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.146.01:39:05.41#ibcon#ireg 7 cls_cnt 0 2006.146.01:39:05.41#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.146.01:39:05.53#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.146.01:39:05.53#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.146.01:39:05.55#ibcon#[25=USB\r\n] 2006.146.01:39:05.58#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.146.01:39:05.58#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.146.01:39:05.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.146.01:39:05.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.146.01:39:05.58$vck44/vblo=1,629.99 2006.146.01:39:05.58#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.146.01:39:05.58#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.146.01:39:05.58#ibcon#ireg 17 cls_cnt 0 2006.146.01:39:05.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.146.01:39:05.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.146.01:39:05.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.146.01:39:05.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.146.01:39:05.64#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.146.01:39:05.64#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.146.01:39:05.64#ibcon#about to clear, iclass 7 cls_cnt 0 2006.146.01:39:05.64#ibcon#cleared, iclass 7 cls_cnt 0 2006.146.01:39:05.64$vck44/vb=1,3 2006.146.01:39:05.64#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.146.01:39:05.64#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.146.01:39:05.64#ibcon#ireg 11 cls_cnt 2 2006.146.01:39:05.64#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.146.01:39:05.64#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.146.01:39:05.64#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.146.01:39:05.66#ibcon#[27=AT01-03\r\n] 2006.146.01:39:05.69#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.146.01:39:05.69#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.146.01:39:05.69#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.146.01:39:05.69#ibcon#ireg 7 cls_cnt 0 2006.146.01:39:05.69#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.146.01:39:05.81#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.146.01:39:05.81#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.146.01:39:05.83#ibcon#[27=USB\r\n] 2006.146.01:39:05.86#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.146.01:39:05.86#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.146.01:39:05.86#ibcon#about to clear, iclass 11 cls_cnt 0 2006.146.01:39:05.86#ibcon#cleared, iclass 11 cls_cnt 0 2006.146.01:39:05.86$vck44/vblo=2,634.99 2006.146.01:39:05.86#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.146.01:39:05.86#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.146.01:39:05.86#ibcon#ireg 17 cls_cnt 0 2006.146.01:39:05.86#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.146.01:39:05.86#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.146.01:39:05.86#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.146.01:39:05.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.146.01:39:05.92#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.146.01:39:05.92#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.146.01:39:05.92#ibcon#about to clear, iclass 13 cls_cnt 0 2006.146.01:39:05.92#ibcon#cleared, iclass 13 cls_cnt 0 2006.146.01:39:05.92$vck44/vb=2,4 2006.146.01:39:05.92#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.146.01:39:05.92#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.146.01:39:05.92#ibcon#ireg 11 cls_cnt 2 2006.146.01:39:05.92#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.146.01:39:05.98#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.146.01:39:05.98#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.146.01:39:06.00#ibcon#[27=AT02-04\r\n] 2006.146.01:39:06.03#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.146.01:39:06.03#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.146.01:39:06.03#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.146.01:39:06.03#ibcon#ireg 7 cls_cnt 0 2006.146.01:39:06.03#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.146.01:39:06.15#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.146.01:39:06.15#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.146.01:39:06.17#ibcon#[27=USB\r\n] 2006.146.01:39:06.20#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.146.01:39:06.20#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.146.01:39:06.20#ibcon#about to clear, iclass 15 cls_cnt 0 2006.146.01:39:06.20#ibcon#cleared, iclass 15 cls_cnt 0 2006.146.01:39:06.20$vck44/vblo=3,649.99 2006.146.01:39:06.20#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.146.01:39:06.20#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.146.01:39:06.20#ibcon#ireg 17 cls_cnt 0 2006.146.01:39:06.20#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.146.01:39:06.20#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.146.01:39:06.20#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.146.01:39:06.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.146.01:39:06.26#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.146.01:39:06.26#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.146.01:39:06.26#ibcon#about to clear, iclass 17 cls_cnt 0 2006.146.01:39:06.26#ibcon#cleared, iclass 17 cls_cnt 0 2006.146.01:39:06.26$vck44/vb=3,4 2006.146.01:39:06.26#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.146.01:39:06.26#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.146.01:39:06.26#ibcon#ireg 11 cls_cnt 2 2006.146.01:39:06.26#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.146.01:39:06.32#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.146.01:39:06.32#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.146.01:39:06.34#ibcon#[27=AT03-04\r\n] 2006.146.01:39:06.37#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.146.01:39:06.37#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.146.01:39:06.37#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.146.01:39:06.37#ibcon#ireg 7 cls_cnt 0 2006.146.01:39:06.37#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.146.01:39:06.49#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.146.01:39:06.49#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.146.01:39:06.51#ibcon#[27=USB\r\n] 2006.146.01:39:06.54#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.146.01:39:06.54#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.146.01:39:06.54#ibcon#about to clear, iclass 19 cls_cnt 0 2006.146.01:39:06.54#ibcon#cleared, iclass 19 cls_cnt 0 2006.146.01:39:06.54$vck44/vblo=4,679.99 2006.146.01:39:06.54#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.146.01:39:06.54#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.146.01:39:06.54#ibcon#ireg 17 cls_cnt 0 2006.146.01:39:06.54#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.146.01:39:06.54#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.146.01:39:06.54#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.146.01:39:06.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.146.01:39:06.60#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.146.01:39:06.60#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.146.01:39:06.60#ibcon#about to clear, iclass 21 cls_cnt 0 2006.146.01:39:06.60#ibcon#cleared, iclass 21 cls_cnt 0 2006.146.01:39:06.60$vck44/vb=4,4 2006.146.01:39:06.60#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.146.01:39:06.60#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.146.01:39:06.60#ibcon#ireg 11 cls_cnt 2 2006.146.01:39:06.60#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.146.01:39:06.66#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.146.01:39:06.66#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.146.01:39:06.68#ibcon#[27=AT04-04\r\n] 2006.146.01:39:06.71#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.146.01:39:06.71#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.146.01:39:06.71#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.146.01:39:06.71#ibcon#ireg 7 cls_cnt 0 2006.146.01:39:06.71#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.146.01:39:06.83#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.146.01:39:06.83#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.146.01:39:06.85#ibcon#[27=USB\r\n] 2006.146.01:39:06.88#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.146.01:39:06.88#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.146.01:39:06.88#ibcon#about to clear, iclass 23 cls_cnt 0 2006.146.01:39:06.88#ibcon#cleared, iclass 23 cls_cnt 0 2006.146.01:39:06.88$vck44/vblo=5,709.99 2006.146.01:39:06.88#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.146.01:39:06.88#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.146.01:39:06.88#ibcon#ireg 17 cls_cnt 0 2006.146.01:39:06.88#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.146.01:39:06.88#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.146.01:39:06.88#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.146.01:39:06.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.146.01:39:06.94#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.146.01:39:06.94#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.146.01:39:06.94#ibcon#about to clear, iclass 25 cls_cnt 0 2006.146.01:39:06.94#ibcon#cleared, iclass 25 cls_cnt 0 2006.146.01:39:06.94$vck44/vb=5,4 2006.146.01:39:06.94#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.146.01:39:06.94#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.146.01:39:06.94#ibcon#ireg 11 cls_cnt 2 2006.146.01:39:06.94#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.146.01:39:07.00#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.146.01:39:07.00#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.146.01:39:07.02#ibcon#[27=AT05-04\r\n] 2006.146.01:39:07.05#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.146.01:39:07.05#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.146.01:39:07.05#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.146.01:39:07.05#ibcon#ireg 7 cls_cnt 0 2006.146.01:39:07.05#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.146.01:39:07.17#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.146.01:39:07.17#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.146.01:39:07.19#ibcon#[27=USB\r\n] 2006.146.01:39:07.22#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.146.01:39:07.22#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.146.01:39:07.22#ibcon#about to clear, iclass 27 cls_cnt 0 2006.146.01:39:07.22#ibcon#cleared, iclass 27 cls_cnt 0 2006.146.01:39:07.22$vck44/vblo=6,719.99 2006.146.01:39:07.22#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.146.01:39:07.22#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.146.01:39:07.22#ibcon#ireg 17 cls_cnt 0 2006.146.01:39:07.22#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.146.01:39:07.22#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.146.01:39:07.22#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.146.01:39:07.24#ibcon#[28=FRQ=06,719.99\r\n] 2006.146.01:39:07.28#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.146.01:39:07.28#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.146.01:39:07.28#ibcon#about to clear, iclass 29 cls_cnt 0 2006.146.01:39:07.28#ibcon#cleared, iclass 29 cls_cnt 0 2006.146.01:39:07.28$vck44/vb=6,4 2006.146.01:39:07.28#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.146.01:39:07.28#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.146.01:39:07.28#ibcon#ireg 11 cls_cnt 2 2006.146.01:39:07.28#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.146.01:39:07.34#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.146.01:39:07.34#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.146.01:39:07.36#ibcon#[27=AT06-04\r\n] 2006.146.01:39:07.39#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.146.01:39:07.39#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.146.01:39:07.39#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.146.01:39:07.39#ibcon#ireg 7 cls_cnt 0 2006.146.01:39:07.39#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.146.01:39:07.51#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.146.01:39:07.51#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.146.01:39:07.53#ibcon#[27=USB\r\n] 2006.146.01:39:07.56#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.146.01:39:07.56#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.146.01:39:07.56#ibcon#about to clear, iclass 31 cls_cnt 0 2006.146.01:39:07.56#ibcon#cleared, iclass 31 cls_cnt 0 2006.146.01:39:07.56$vck44/vblo=7,734.99 2006.146.01:39:07.56#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.146.01:39:07.56#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.146.01:39:07.56#ibcon#ireg 17 cls_cnt 0 2006.146.01:39:07.56#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.146.01:39:07.56#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.146.01:39:07.56#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.146.01:39:07.58#ibcon#[28=FRQ=07,734.99\r\n] 2006.146.01:39:07.62#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.146.01:39:07.62#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.146.01:39:07.62#ibcon#about to clear, iclass 33 cls_cnt 0 2006.146.01:39:07.62#ibcon#cleared, iclass 33 cls_cnt 0 2006.146.01:39:07.62$vck44/vb=7,4 2006.146.01:39:07.62#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.146.01:39:07.62#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.146.01:39:07.62#ibcon#ireg 11 cls_cnt 2 2006.146.01:39:07.62#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.146.01:39:07.68#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.146.01:39:07.68#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.146.01:39:07.70#ibcon#[27=AT07-04\r\n] 2006.146.01:39:07.73#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.146.01:39:07.73#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.146.01:39:07.73#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.146.01:39:07.73#ibcon#ireg 7 cls_cnt 0 2006.146.01:39:07.73#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.146.01:39:07.85#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.146.01:39:07.85#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.146.01:39:07.87#ibcon#[27=USB\r\n] 2006.146.01:39:07.90#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.146.01:39:07.90#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.146.01:39:07.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.146.01:39:07.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.146.01:39:07.90$vck44/vblo=8,744.99 2006.146.01:39:07.90#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.146.01:39:07.90#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.146.01:39:07.90#ibcon#ireg 17 cls_cnt 0 2006.146.01:39:07.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.146.01:39:07.90#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.146.01:39:07.90#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.146.01:39:07.92#ibcon#[28=FRQ=08,744.99\r\n] 2006.146.01:39:07.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.146.01:39:07.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.146.01:39:07.96#ibcon#about to clear, iclass 37 cls_cnt 0 2006.146.01:39:07.96#ibcon#cleared, iclass 37 cls_cnt 0 2006.146.01:39:07.96$vck44/vb=8,4 2006.146.01:39:07.96#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.146.01:39:07.96#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.146.01:39:07.96#ibcon#ireg 11 cls_cnt 2 2006.146.01:39:07.96#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.146.01:39:08.02#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.146.01:39:08.02#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.146.01:39:08.04#ibcon#[27=AT08-04\r\n] 2006.146.01:39:08.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.146.01:39:08.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.146.01:39:08.07#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.146.01:39:08.07#ibcon#ireg 7 cls_cnt 0 2006.146.01:39:08.07#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.146.01:39:08.19#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.146.01:39:08.19#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.146.01:39:08.21#ibcon#[27=USB\r\n] 2006.146.01:39:08.24#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.146.01:39:08.24#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.146.01:39:08.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.146.01:39:08.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.146.01:39:08.24$vck44/vabw=wide 2006.146.01:39:08.24#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.146.01:39:08.24#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.146.01:39:08.24#ibcon#ireg 8 cls_cnt 0 2006.146.01:39:08.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.146.01:39:08.24#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.146.01:39:08.24#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.146.01:39:08.26#ibcon#[25=BW32\r\n] 2006.146.01:39:08.29#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.146.01:39:08.29#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.146.01:39:08.29#ibcon#about to clear, iclass 3 cls_cnt 0 2006.146.01:39:08.29#ibcon#cleared, iclass 3 cls_cnt 0 2006.146.01:39:08.29$vck44/vbbw=wide 2006.146.01:39:08.29#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.146.01:39:08.29#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.146.01:39:08.29#ibcon#ireg 8 cls_cnt 0 2006.146.01:39:08.29#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.146.01:39:08.36#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.146.01:39:08.36#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.146.01:39:08.38#ibcon#[27=BW32\r\n] 2006.146.01:39:08.41#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.146.01:39:08.41#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.146.01:39:08.41#ibcon#about to clear, iclass 5 cls_cnt 0 2006.146.01:39:08.41#ibcon#cleared, iclass 5 cls_cnt 0 2006.146.01:39:08.41$setupk4/ifdk4 2006.146.01:39:08.41$ifdk4/lo= 2006.146.01:39:08.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.146.01:39:08.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.146.01:39:08.41$ifdk4/patch= 2006.146.01:39:08.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.146.01:39:08.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.146.01:39:08.41$setupk4/!*+20s 2006.146.01:39:10.14#trakl#Source acquired 2006.146.01:39:11.14#flagr#flagr/antenna,acquired 2006.146.01:39:14.83#abcon#<5=/08 1.7 5.8 21.15 651019.8\r\n> 2006.146.01:39:14.85#abcon#{5=INTERFACE CLEAR} 2006.146.01:39:14.91#abcon#[5=S1D000X0/0*\r\n] 2006.146.01:39:22.87$setupk4/"tpicd 2006.146.01:39:22.87$setupk4/echo=off 2006.146.01:39:22.87$setupk4/xlog=off 2006.146.01:39:22.87:!2006.146.01:44:15 2006.146.01:40:26.14#trakl#Off source 2006.146.01:40:26.14?ERROR st -7 Antenna off-source! 2006.146.01:40:26.14#trakl#az 291.040 el 27.082 azerr*cos(el) 0.0174 elerr -0.0016 2006.146.01:40:26.14#flagr#flagr/antenna,off-source 2006.146.01:40:32.14#trakl#Source re-acquired 2006.146.01:40:32.14#flagr#flagr/antenna,re-acquired 2006.146.01:44:15.00:preob 2006.146.01:44:15.14/onsource/TRACKING 2006.146.01:44:15.14:!2006.146.01:44:25 2006.146.01:44:25.00:"tape 2006.146.01:44:25.00:"st=record 2006.146.01:44:25.00:data_valid=on 2006.146.01:44:25.00:midob 2006.146.01:44:26.14/onsource/TRACKING 2006.146.01:44:26.14/wx/21.15,1019.7,63 2006.146.01:44:26.21/cable/+6.5399E-03 2006.146.01:44:27.30/va/01,08,usb,yes,29,32 2006.146.01:44:27.30/va/02,07,usb,yes,32,32 2006.146.01:44:27.30/va/03,08,usb,yes,29,30 2006.146.01:44:27.30/va/04,07,usb,yes,32,34 2006.146.01:44:27.30/va/05,04,usb,yes,28,29 2006.146.01:44:27.30/va/06,04,usb,yes,32,32 2006.146.01:44:27.30/va/07,04,usb,yes,32,33 2006.146.01:44:27.30/va/08,04,usb,yes,27,33 2006.146.01:44:27.53/valo/01,524.99,yes,locked 2006.146.01:44:27.53/valo/02,534.99,yes,locked 2006.146.01:44:27.53/valo/03,564.99,yes,locked 2006.146.01:44:27.53/valo/04,624.99,yes,locked 2006.146.01:44:27.53/valo/05,734.99,yes,locked 2006.146.01:44:27.53/valo/06,814.99,yes,locked 2006.146.01:44:27.53/valo/07,864.99,yes,locked 2006.146.01:44:27.53/valo/08,884.99,yes,locked 2006.146.01:44:28.62/vb/01,03,usb,yes,37,34 2006.146.01:44:28.62/vb/02,04,usb,yes,32,32 2006.146.01:44:28.62/vb/03,04,usb,yes,29,32 2006.146.01:44:28.62/vb/04,04,usb,yes,34,33 2006.146.01:44:28.62/vb/05,04,usb,yes,26,29 2006.146.01:44:28.62/vb/06,04,usb,yes,31,27 2006.146.01:44:28.62/vb/07,04,usb,yes,30,30 2006.146.01:44:28.62/vb/08,04,usb,yes,28,31 2006.146.01:44:28.85/vblo/01,629.99,yes,locked 2006.146.01:44:28.85/vblo/02,634.99,yes,locked 2006.146.01:44:28.85/vblo/03,649.99,yes,locked 2006.146.01:44:28.85/vblo/04,679.99,yes,locked 2006.146.01:44:28.85/vblo/05,709.99,yes,locked 2006.146.01:44:28.85/vblo/06,719.99,yes,locked 2006.146.01:44:28.85/vblo/07,734.99,yes,locked 2006.146.01:44:28.85/vblo/08,744.99,yes,locked 2006.146.01:44:29.00/vabw/8 2006.146.01:44:29.15/vbbw/8 2006.146.01:44:29.35/xfe/off,on,15.2 2006.146.01:44:29.74/ifatt/23,28,28,28 2006.146.01:44:30.08/fmout-gps/S +4.0E-08 2006.146.01:44:30.16:!2006.146.01:46:55 2006.146.01:46:55.00:data_valid=off 2006.146.01:46:55.00:"et 2006.146.01:46:55.00:!+3s 2006.146.01:46:58.02:"tape 2006.146.01:46:58.02:postob 2006.146.01:46:58.08/cable/+6.5390E-03 2006.146.01:46:58.08/wx/21.17,1019.7,64 2006.146.01:46:58.15/fmout-gps/S +4.1E-08 2006.146.01:46:58.15:scan_name=146-0154,jd0605,80 2006.146.01:46:58.15:source=0528+134,053056.42,133155.1,2000.0,cw 2006.146.01:46:59.14#flagr#flagr/antenna,new-source 2006.146.01:46:59.14:checkk5 2006.146.01:46:59.60/chk_autoobs//k5ts1/ autoobs is running! 2006.146.01:47:00.03/chk_autoobs//k5ts2/ autoobs is running! 2006.146.01:47:00.52/chk_autoobs//k5ts3/ autoobs is running! 2006.146.01:47:00.99/chk_autoobs//k5ts4/ autoobs is running! 2006.146.01:47:01.49/chk_obsdata//k5ts1/T1460144??a.dat file size is correct (nominal:600MB, actual:596MB). 2006.146.01:47:02.13/chk_obsdata//k5ts2/T1460144??b.dat file size is correct (nominal:600MB, actual:596MB). 2006.146.01:47:02.88/chk_obsdata//k5ts3/T1460144??c.dat file size is correct (nominal:600MB, actual:596MB). 2006.146.01:47:03.42/chk_obsdata//k5ts4/T1460144??d.dat file size is correct (nominal:600MB, actual:596MB). 2006.146.01:47:04.35/k5log//k5ts1_log_newline 2006.146.01:47:05.17/k5log//k5ts2_log_newline 2006.146.01:47:06.09/k5log//k5ts3_log_newline 2006.146.01:47:07.52/k5log//k5ts4_log_newline 2006.146.01:47:07.54/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.146.01:47:07.55:setupk4=1 2006.146.01:47:07.55$setupk4/echo=on 2006.146.01:47:07.55$setupk4/pcalon 2006.146.01:47:07.55$pcalon/"no phase cal control is implemented here 2006.146.01:47:07.55$setupk4/"tpicd=stop 2006.146.01:47:07.55$setupk4/"rec=synch_on 2006.146.01:47:07.55$setupk4/"rec_mode=128 2006.146.01:47:07.55$setupk4/!* 2006.146.01:47:07.55$setupk4/recpk4 2006.146.01:47:07.55$recpk4/recpatch= 2006.146.01:47:07.55$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.146.01:47:07.55$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.146.01:47:07.56$setupk4/vck44 2006.146.01:47:07.56$vck44/valo=1,524.99 2006.146.01:47:07.56#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.146.01:47:07.56#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.146.01:47:07.56#ibcon#ireg 17 cls_cnt 0 2006.146.01:47:07.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.146.01:47:07.56#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.146.01:47:07.56#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.146.01:47:07.60#ibcon#[26=FRQ=01,524.99\r\n] 2006.146.01:47:07.65#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.146.01:47:07.65#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.146.01:47:07.65#ibcon#about to clear, iclass 22 cls_cnt 0 2006.146.01:47:07.65#ibcon#cleared, iclass 22 cls_cnt 0 2006.146.01:47:07.66$vck44/va=1,8 2006.146.01:47:07.66#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.146.01:47:07.66#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.146.01:47:07.66#ibcon#ireg 11 cls_cnt 2 2006.146.01:47:07.66#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.146.01:47:07.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.146.01:47:07.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.146.01:47:07.69#ibcon#[25=AT01-08\r\n] 2006.146.01:47:07.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.146.01:47:07.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.146.01:47:07.73#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.146.01:47:07.73#ibcon#ireg 7 cls_cnt 0 2006.146.01:47:07.73#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.146.01:47:07.85#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.146.01:47:07.85#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.146.01:47:07.87#ibcon#[25=USB\r\n] 2006.146.01:47:07.90#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.146.01:47:07.90#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.146.01:47:07.90#ibcon#about to clear, iclass 24 cls_cnt 0 2006.146.01:47:07.90#ibcon#cleared, iclass 24 cls_cnt 0 2006.146.01:47:07.90$vck44/valo=2,534.99 2006.146.01:47:07.90#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.146.01:47:07.90#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.146.01:47:07.90#ibcon#ireg 17 cls_cnt 0 2006.146.01:47:07.90#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.146.01:47:07.90#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.146.01:47:07.90#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.146.01:47:07.92#ibcon#[26=FRQ=02,534.99\r\n] 2006.146.01:47:07.96#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.146.01:47:07.96#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.146.01:47:07.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.146.01:47:07.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.146.01:47:07.96$vck44/va=2,7 2006.146.01:47:07.96#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.146.01:47:07.96#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.146.01:47:07.96#ibcon#ireg 11 cls_cnt 2 2006.146.01:47:07.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.146.01:47:08.02#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.146.01:47:08.02#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.146.01:47:08.04#ibcon#[25=AT02-07\r\n] 2006.146.01:47:08.07#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.146.01:47:08.07#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.146.01:47:08.07#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.146.01:47:08.07#ibcon#ireg 7 cls_cnt 0 2006.146.01:47:08.07#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.146.01:47:08.19#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.146.01:47:08.19#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.146.01:47:08.21#ibcon#[25=USB\r\n] 2006.146.01:47:08.24#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.146.01:47:08.24#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.146.01:47:08.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.146.01:47:08.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.146.01:47:08.24$vck44/valo=3,564.99 2006.146.01:47:08.24#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.146.01:47:08.24#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.146.01:47:08.24#ibcon#ireg 17 cls_cnt 0 2006.146.01:47:08.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.146.01:47:08.24#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.146.01:47:08.24#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.146.01:47:08.26#ibcon#[26=FRQ=03,564.99\r\n] 2006.146.01:47:08.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.146.01:47:08.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.146.01:47:08.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.146.01:47:08.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.146.01:47:08.30$vck44/va=3,8 2006.146.01:47:08.30#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.146.01:47:08.30#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.146.01:47:08.30#ibcon#ireg 11 cls_cnt 2 2006.146.01:47:08.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.146.01:47:08.36#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.146.01:47:08.36#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.146.01:47:08.38#ibcon#[25=AT03-08\r\n] 2006.146.01:47:08.41#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.146.01:47:08.41#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.146.01:47:08.41#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.146.01:47:08.41#ibcon#ireg 7 cls_cnt 0 2006.146.01:47:08.41#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.146.01:47:08.53#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.146.01:47:08.53#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.146.01:47:08.55#ibcon#[25=USB\r\n] 2006.146.01:47:08.58#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.146.01:47:08.58#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.146.01:47:08.58#ibcon#about to clear, iclass 32 cls_cnt 0 2006.146.01:47:08.58#ibcon#cleared, iclass 32 cls_cnt 0 2006.146.01:47:08.58$vck44/valo=4,624.99 2006.146.01:47:08.58#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.146.01:47:08.58#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.146.01:47:08.58#ibcon#ireg 17 cls_cnt 0 2006.146.01:47:08.58#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.146.01:47:08.58#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.146.01:47:08.58#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.146.01:47:08.60#ibcon#[26=FRQ=04,624.99\r\n] 2006.146.01:47:08.64#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.146.01:47:08.64#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.146.01:47:08.64#ibcon#about to clear, iclass 34 cls_cnt 0 2006.146.01:47:08.64#ibcon#cleared, iclass 34 cls_cnt 0 2006.146.01:47:08.64$vck44/va=4,7 2006.146.01:47:08.64#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.146.01:47:08.64#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.146.01:47:08.64#ibcon#ireg 11 cls_cnt 2 2006.146.01:47:08.64#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.146.01:47:08.70#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.146.01:47:08.70#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.146.01:47:08.72#ibcon#[25=AT04-07\r\n] 2006.146.01:47:08.75#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.146.01:47:08.75#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.146.01:47:08.75#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.146.01:47:08.75#ibcon#ireg 7 cls_cnt 0 2006.146.01:47:08.75#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.146.01:47:08.87#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.146.01:47:08.87#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.146.01:47:08.89#ibcon#[25=USB\r\n] 2006.146.01:47:08.92#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.146.01:47:08.92#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.146.01:47:08.92#ibcon#about to clear, iclass 36 cls_cnt 0 2006.146.01:47:08.92#ibcon#cleared, iclass 36 cls_cnt 0 2006.146.01:47:08.92$vck44/valo=5,734.99 2006.146.01:47:08.92#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.146.01:47:08.92#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.146.01:47:08.92#ibcon#ireg 17 cls_cnt 0 2006.146.01:47:08.92#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.146.01:47:08.92#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.146.01:47:08.92#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.146.01:47:08.94#ibcon#[26=FRQ=05,734.99\r\n] 2006.146.01:47:08.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.146.01:47:08.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.146.01:47:08.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.146.01:47:08.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.146.01:47:08.98$vck44/va=5,4 2006.146.01:47:08.98#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.146.01:47:08.98#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.146.01:47:08.98#ibcon#ireg 11 cls_cnt 2 2006.146.01:47:08.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.146.01:47:09.04#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.146.01:47:09.04#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.146.01:47:09.06#ibcon#[25=AT05-04\r\n] 2006.146.01:47:09.09#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.146.01:47:09.09#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.146.01:47:09.09#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.146.01:47:09.09#ibcon#ireg 7 cls_cnt 0 2006.146.01:47:09.09#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.146.01:47:09.21#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.146.01:47:09.21#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.146.01:47:09.23#ibcon#[25=USB\r\n] 2006.146.01:47:09.28#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.146.01:47:09.28#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.146.01:47:09.28#ibcon#about to clear, iclass 40 cls_cnt 0 2006.146.01:47:09.28#ibcon#cleared, iclass 40 cls_cnt 0 2006.146.01:47:09.28$vck44/valo=6,814.99 2006.146.01:47:09.28#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.146.01:47:09.28#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.146.01:47:09.28#ibcon#ireg 17 cls_cnt 0 2006.146.01:47:09.28#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.146.01:47:09.28#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.146.01:47:09.28#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.146.01:47:09.30#ibcon#[26=FRQ=06,814.99\r\n] 2006.146.01:47:09.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.146.01:47:09.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.146.01:47:09.34#ibcon#about to clear, iclass 4 cls_cnt 0 2006.146.01:47:09.34#ibcon#cleared, iclass 4 cls_cnt 0 2006.146.01:47:09.34$vck44/va=6,4 2006.146.01:47:09.34#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.146.01:47:09.34#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.146.01:47:09.34#ibcon#ireg 11 cls_cnt 2 2006.146.01:47:09.34#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.146.01:47:09.40#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.146.01:47:09.40#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.146.01:47:09.42#ibcon#[25=AT06-04\r\n] 2006.146.01:47:09.45#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.146.01:47:09.45#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.146.01:47:09.45#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.146.01:47:09.45#ibcon#ireg 7 cls_cnt 0 2006.146.01:47:09.45#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.146.01:47:09.57#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.146.01:47:09.57#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.146.01:47:09.59#ibcon#[25=USB\r\n] 2006.146.01:47:09.62#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.146.01:47:09.62#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.146.01:47:09.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.146.01:47:09.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.146.01:47:09.62$vck44/valo=7,864.99 2006.146.01:47:09.62#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.146.01:47:09.62#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.146.01:47:09.62#ibcon#ireg 17 cls_cnt 0 2006.146.01:47:09.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.146.01:47:09.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.146.01:47:09.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.146.01:47:09.64#ibcon#[26=FRQ=07,864.99\r\n] 2006.146.01:47:09.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.146.01:47:09.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.146.01:47:09.68#ibcon#about to clear, iclass 10 cls_cnt 0 2006.146.01:47:09.68#ibcon#cleared, iclass 10 cls_cnt 0 2006.146.01:47:09.68$vck44/va=7,4 2006.146.01:47:09.68#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.146.01:47:09.68#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.146.01:47:09.68#ibcon#ireg 11 cls_cnt 2 2006.146.01:47:09.68#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.146.01:47:09.74#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.146.01:47:09.74#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.146.01:47:09.76#ibcon#[25=AT07-04\r\n] 2006.146.01:47:09.79#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.146.01:47:09.79#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.146.01:47:09.79#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.146.01:47:09.79#ibcon#ireg 7 cls_cnt 0 2006.146.01:47:09.79#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.146.01:47:09.91#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.146.01:47:09.91#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.146.01:47:09.93#ibcon#[25=USB\r\n] 2006.146.01:47:09.96#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.146.01:47:09.96#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.146.01:47:09.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.146.01:47:09.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.146.01:47:09.96$vck44/valo=8,884.99 2006.146.01:47:09.96#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.146.01:47:09.96#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.146.01:47:09.96#ibcon#ireg 17 cls_cnt 0 2006.146.01:47:09.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.146.01:47:09.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.146.01:47:09.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.146.01:47:09.98#ibcon#[26=FRQ=08,884.99\r\n] 2006.146.01:47:10.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.146.01:47:10.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.146.01:47:10.02#ibcon#about to clear, iclass 14 cls_cnt 0 2006.146.01:47:10.02#ibcon#cleared, iclass 14 cls_cnt 0 2006.146.01:47:10.02$vck44/va=8,4 2006.146.01:47:10.02#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.146.01:47:10.02#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.146.01:47:10.02#ibcon#ireg 11 cls_cnt 2 2006.146.01:47:10.02#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.146.01:47:10.08#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.146.01:47:10.08#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.146.01:47:10.10#ibcon#[25=AT08-04\r\n] 2006.146.01:47:10.13#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.146.01:47:10.13#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.146.01:47:10.13#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.146.01:47:10.13#ibcon#ireg 7 cls_cnt 0 2006.146.01:47:10.13#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.146.01:47:10.25#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.146.01:47:10.25#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.146.01:47:10.27#ibcon#[25=USB\r\n] 2006.146.01:47:10.30#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.146.01:47:10.30#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.146.01:47:10.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.146.01:47:10.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.146.01:47:10.30$vck44/vblo=1,629.99 2006.146.01:47:10.30#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.146.01:47:10.30#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.146.01:47:10.30#ibcon#ireg 17 cls_cnt 0 2006.146.01:47:10.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.146.01:47:10.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.146.01:47:10.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.146.01:47:10.32#ibcon#[28=FRQ=01,629.99\r\n] 2006.146.01:47:10.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.146.01:47:10.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.146.01:47:10.36#ibcon#about to clear, iclass 18 cls_cnt 0 2006.146.01:47:10.36#ibcon#cleared, iclass 18 cls_cnt 0 2006.146.01:47:10.36$vck44/vb=1,3 2006.146.01:47:10.36#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.146.01:47:10.36#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.146.01:47:10.36#ibcon#ireg 11 cls_cnt 2 2006.146.01:47:10.36#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.146.01:47:10.36#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.146.01:47:10.36#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.146.01:47:10.38#ibcon#[27=AT01-03\r\n] 2006.146.01:47:10.41#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.146.01:47:10.41#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.146.01:47:10.41#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.146.01:47:10.41#ibcon#ireg 7 cls_cnt 0 2006.146.01:47:10.41#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.146.01:47:10.53#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.146.01:47:10.53#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.146.01:47:10.55#ibcon#[27=USB\r\n] 2006.146.01:47:10.58#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.146.01:47:10.58#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.146.01:47:10.58#ibcon#about to clear, iclass 20 cls_cnt 0 2006.146.01:47:10.58#ibcon#cleared, iclass 20 cls_cnt 0 2006.146.01:47:10.58$vck44/vblo=2,634.99 2006.146.01:47:10.58#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.146.01:47:10.58#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.146.01:47:10.58#ibcon#ireg 17 cls_cnt 0 2006.146.01:47:10.58#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.146.01:47:10.58#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.146.01:47:10.58#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.146.01:47:10.60#ibcon#[28=FRQ=02,634.99\r\n] 2006.146.01:47:10.64#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.146.01:47:10.64#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.146.01:47:10.64#ibcon#about to clear, iclass 22 cls_cnt 0 2006.146.01:47:10.64#ibcon#cleared, iclass 22 cls_cnt 0 2006.146.01:47:10.64$vck44/vb=2,4 2006.146.01:47:10.64#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.146.01:47:10.64#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.146.01:47:10.64#ibcon#ireg 11 cls_cnt 2 2006.146.01:47:10.64#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.146.01:47:10.70#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.146.01:47:10.70#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.146.01:47:10.72#ibcon#[27=AT02-04\r\n] 2006.146.01:47:10.75#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.146.01:47:10.75#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.146.01:47:10.75#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.146.01:47:10.75#ibcon#ireg 7 cls_cnt 0 2006.146.01:47:10.75#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.146.01:47:10.87#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.146.01:47:10.87#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.146.01:47:10.89#ibcon#[27=USB\r\n] 2006.146.01:47:10.92#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.146.01:47:10.92#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.146.01:47:10.92#ibcon#about to clear, iclass 24 cls_cnt 0 2006.146.01:47:10.92#ibcon#cleared, iclass 24 cls_cnt 0 2006.146.01:47:10.92$vck44/vblo=3,649.99 2006.146.01:47:10.92#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.146.01:47:10.92#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.146.01:47:10.92#ibcon#ireg 17 cls_cnt 0 2006.146.01:47:10.92#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.146.01:47:10.92#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.146.01:47:10.92#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.146.01:47:10.94#ibcon#[28=FRQ=03,649.99\r\n] 2006.146.01:47:10.98#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.146.01:47:10.98#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.146.01:47:10.98#ibcon#about to clear, iclass 26 cls_cnt 0 2006.146.01:47:10.98#ibcon#cleared, iclass 26 cls_cnt 0 2006.146.01:47:10.98$vck44/vb=3,4 2006.146.01:47:10.98#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.146.01:47:10.98#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.146.01:47:10.98#ibcon#ireg 11 cls_cnt 2 2006.146.01:47:10.98#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.146.01:47:11.04#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.146.01:47:11.04#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.146.01:47:11.06#ibcon#[27=AT03-04\r\n] 2006.146.01:47:11.09#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.146.01:47:11.09#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.146.01:47:11.09#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.146.01:47:11.09#ibcon#ireg 7 cls_cnt 0 2006.146.01:47:11.09#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.146.01:47:11.21#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.146.01:47:11.21#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.146.01:47:11.23#ibcon#[27=USB\r\n] 2006.146.01:47:11.26#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.146.01:47:11.26#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.146.01:47:11.26#ibcon#about to clear, iclass 28 cls_cnt 0 2006.146.01:47:11.26#ibcon#cleared, iclass 28 cls_cnt 0 2006.146.01:47:11.26$vck44/vblo=4,679.99 2006.146.01:47:11.26#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.146.01:47:11.26#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.146.01:47:11.26#ibcon#ireg 17 cls_cnt 0 2006.146.01:47:11.26#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.146.01:47:11.26#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.146.01:47:11.26#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.146.01:47:11.28#ibcon#[28=FRQ=04,679.99\r\n] 2006.146.01:47:11.32#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.146.01:47:11.32#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.146.01:47:11.32#ibcon#about to clear, iclass 30 cls_cnt 0 2006.146.01:47:11.32#ibcon#cleared, iclass 30 cls_cnt 0 2006.146.01:47:11.32$vck44/vb=4,4 2006.146.01:47:11.32#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.146.01:47:11.32#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.146.01:47:11.32#ibcon#ireg 11 cls_cnt 2 2006.146.01:47:11.32#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.146.01:47:11.38#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.146.01:47:11.38#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.146.01:47:11.40#ibcon#[27=AT04-04\r\n] 2006.146.01:47:11.43#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.146.01:47:11.43#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.146.01:47:11.43#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.146.01:47:11.43#ibcon#ireg 7 cls_cnt 0 2006.146.01:47:11.43#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.146.01:47:11.55#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.146.01:47:11.55#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.146.01:47:11.57#ibcon#[27=USB\r\n] 2006.146.01:47:11.60#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.146.01:47:11.60#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.146.01:47:11.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.146.01:47:11.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.146.01:47:11.60$vck44/vblo=5,709.99 2006.146.01:47:11.60#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.146.01:47:11.60#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.146.01:47:11.60#ibcon#ireg 17 cls_cnt 0 2006.146.01:47:11.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.146.01:47:11.60#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.146.01:47:11.60#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.146.01:47:11.62#ibcon#[28=FRQ=05,709.99\r\n] 2006.146.01:47:11.66#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.146.01:47:11.66#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.146.01:47:11.66#ibcon#about to clear, iclass 34 cls_cnt 0 2006.146.01:47:11.66#ibcon#cleared, iclass 34 cls_cnt 0 2006.146.01:47:11.66$vck44/vb=5,4 2006.146.01:47:11.66#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.146.01:47:11.66#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.146.01:47:11.66#ibcon#ireg 11 cls_cnt 2 2006.146.01:47:11.66#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.146.01:47:11.72#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.146.01:47:11.72#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.146.01:47:11.74#ibcon#[27=AT05-04\r\n] 2006.146.01:47:11.77#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.146.01:47:11.77#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.146.01:47:11.77#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.146.01:47:11.77#ibcon#ireg 7 cls_cnt 0 2006.146.01:47:11.77#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.146.01:47:11.89#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.146.01:47:11.89#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.146.01:47:11.91#ibcon#[27=USB\r\n] 2006.146.01:47:11.94#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.146.01:47:11.94#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.146.01:47:11.94#ibcon#about to clear, iclass 36 cls_cnt 0 2006.146.01:47:11.94#ibcon#cleared, iclass 36 cls_cnt 0 2006.146.01:47:11.94$vck44/vblo=6,719.99 2006.146.01:47:11.94#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.146.01:47:11.94#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.146.01:47:11.94#ibcon#ireg 17 cls_cnt 0 2006.146.01:47:11.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.146.01:47:11.94#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.146.01:47:11.94#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.146.01:47:11.96#ibcon#[28=FRQ=06,719.99\r\n] 2006.146.01:47:12.00#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.146.01:47:12.00#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.146.01:47:12.00#ibcon#about to clear, iclass 38 cls_cnt 0 2006.146.01:47:12.00#ibcon#cleared, iclass 38 cls_cnt 0 2006.146.01:47:12.00$vck44/vb=6,4 2006.146.01:47:12.00#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.146.01:47:12.00#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.146.01:47:12.00#ibcon#ireg 11 cls_cnt 2 2006.146.01:47:12.00#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.146.01:47:12.06#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.146.01:47:12.06#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.146.01:47:12.08#ibcon#[27=AT06-04\r\n] 2006.146.01:47:12.11#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.146.01:47:12.11#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.146.01:47:12.11#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.146.01:47:12.11#ibcon#ireg 7 cls_cnt 0 2006.146.01:47:12.11#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.146.01:47:12.23#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.146.01:47:12.23#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.146.01:47:12.25#ibcon#[27=USB\r\n] 2006.146.01:47:12.28#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.146.01:47:12.28#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.146.01:47:12.28#ibcon#about to clear, iclass 40 cls_cnt 0 2006.146.01:47:12.28#ibcon#cleared, iclass 40 cls_cnt 0 2006.146.01:47:12.28$vck44/vblo=7,734.99 2006.146.01:47:12.28#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.146.01:47:12.28#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.146.01:47:12.28#ibcon#ireg 17 cls_cnt 0 2006.146.01:47:12.28#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.146.01:47:12.28#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.146.01:47:12.28#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.146.01:47:12.30#ibcon#[28=FRQ=07,734.99\r\n] 2006.146.01:47:12.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.146.01:47:12.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.146.01:47:12.34#ibcon#about to clear, iclass 4 cls_cnt 0 2006.146.01:47:12.34#ibcon#cleared, iclass 4 cls_cnt 0 2006.146.01:47:12.34$vck44/vb=7,4 2006.146.01:47:12.34#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.146.01:47:12.34#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.146.01:47:12.34#ibcon#ireg 11 cls_cnt 2 2006.146.01:47:12.34#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.146.01:47:12.40#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.146.01:47:12.40#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.146.01:47:12.42#ibcon#[27=AT07-04\r\n] 2006.146.01:47:12.45#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.146.01:47:12.45#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.146.01:47:12.45#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.146.01:47:12.45#ibcon#ireg 7 cls_cnt 0 2006.146.01:47:12.45#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.146.01:47:12.57#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.146.01:47:12.57#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.146.01:47:12.59#ibcon#[27=USB\r\n] 2006.146.01:47:12.62#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.146.01:47:12.62#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.146.01:47:12.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.146.01:47:12.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.146.01:47:12.62$vck44/vblo=8,744.99 2006.146.01:47:12.62#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.146.01:47:12.62#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.146.01:47:12.62#ibcon#ireg 17 cls_cnt 0 2006.146.01:47:12.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.146.01:47:12.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.146.01:47:12.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.146.01:47:12.64#ibcon#[28=FRQ=08,744.99\r\n] 2006.146.01:47:12.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.146.01:47:12.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.146.01:47:12.68#ibcon#about to clear, iclass 10 cls_cnt 0 2006.146.01:47:12.68#ibcon#cleared, iclass 10 cls_cnt 0 2006.146.01:47:12.68$vck44/vb=8,4 2006.146.01:47:12.68#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.146.01:47:12.68#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.146.01:47:12.68#ibcon#ireg 11 cls_cnt 2 2006.146.01:47:12.68#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.146.01:47:12.74#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.146.01:47:12.74#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.146.01:47:12.76#ibcon#[27=AT08-04\r\n] 2006.146.01:47:12.79#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.146.01:47:12.79#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.146.01:47:12.79#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.146.01:47:12.79#ibcon#ireg 7 cls_cnt 0 2006.146.01:47:12.79#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.146.01:47:12.91#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.146.01:47:12.91#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.146.01:47:12.93#ibcon#[27=USB\r\n] 2006.146.01:47:12.96#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.146.01:47:12.96#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.146.01:47:12.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.146.01:47:12.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.146.01:47:12.96$vck44/vabw=wide 2006.146.01:47:12.96#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.146.01:47:12.96#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.146.01:47:12.96#ibcon#ireg 8 cls_cnt 0 2006.146.01:47:12.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.146.01:47:12.96#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.146.01:47:12.96#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.146.01:47:12.98#ibcon#[25=BW32\r\n] 2006.146.01:47:13.00#abcon#<5=/09 1.8 7.5 21.18 641019.7\r\n> 2006.146.01:47:13.01#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.146.01:47:13.01#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.146.01:47:13.01#ibcon#about to clear, iclass 15 cls_cnt 0 2006.146.01:47:13.01#ibcon#cleared, iclass 15 cls_cnt 0 2006.146.01:47:13.01$vck44/vbbw=wide 2006.146.01:47:13.01#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.146.01:47:13.01#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.146.01:47:13.01#ibcon#ireg 8 cls_cnt 0 2006.146.01:47:13.01#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.146.01:47:13.02#abcon#{5=INTERFACE CLEAR} 2006.146.01:47:13.08#abcon#[5=S1D000X0/0*\r\n] 2006.146.01:47:13.08#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.146.01:47:13.08#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.146.01:47:13.10#ibcon#[27=BW32\r\n] 2006.146.01:47:13.13#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.146.01:47:13.13#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.146.01:47:13.13#ibcon#about to clear, iclass 19 cls_cnt 0 2006.146.01:47:13.13#ibcon#cleared, iclass 19 cls_cnt 0 2006.146.01:47:13.13$setupk4/ifdk4 2006.146.01:47:13.13$ifdk4/lo= 2006.146.01:47:13.13$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.146.01:47:13.13$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.146.01:47:13.13$ifdk4/patch= 2006.146.01:47:13.13$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.146.01:47:13.13$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.146.01:47:13.13$setupk4/!*+20s 2006.146.01:47:23.17#abcon#<5=/09 1.8 7.6 21.18 651019.7\r\n> 2006.146.01:47:23.21#abcon#{5=INTERFACE CLEAR} 2006.146.01:47:23.27#abcon#[5=S1D000X0/0*\r\n] 2006.146.01:47:27.56$setupk4/"tpicd 2006.146.01:47:27.56$setupk4/echo=off 2006.146.01:47:27.56$setupk4/xlog=off 2006.146.01:47:27.56:!2006.146.01:54:37 2006.146.01:48:02.14#trakl#Source acquired 2006.146.01:48:04.14#flagr#flagr/antenna,acquired 2006.146.01:54:37.00:preob 2006.146.01:54:38.14/onsource/TRACKING 2006.146.01:54:38.14:!2006.146.01:54:47 2006.146.01:54:47.00:"tape 2006.146.01:54:47.00:"st=record 2006.146.01:54:47.00:data_valid=on 2006.146.01:54:47.00:midob 2006.146.01:54:47.14/onsource/TRACKING 2006.146.01:54:47.14/wx/21.21,1019.5,65 2006.146.01:54:47.24/cable/+6.5386E-03 2006.146.01:54:48.33/va/01,08,usb,yes,28,30 2006.146.01:54:48.33/va/02,07,usb,yes,30,31 2006.146.01:54:48.33/va/03,08,usb,yes,27,28 2006.146.01:54:48.33/va/04,07,usb,yes,31,33 2006.146.01:54:48.33/va/05,04,usb,yes,27,28 2006.146.01:54:48.33/va/06,04,usb,yes,30,30 2006.146.01:54:48.33/va/07,04,usb,yes,31,32 2006.146.01:54:48.33/va/08,04,usb,yes,26,32 2006.146.01:54:48.56/valo/01,524.99,yes,locked 2006.146.01:54:48.56/valo/02,534.99,yes,locked 2006.146.01:54:48.56/valo/03,564.99,yes,locked 2006.146.01:54:48.56/valo/04,624.99,yes,locked 2006.146.01:54:48.56/valo/05,734.99,yes,locked 2006.146.01:54:48.56/valo/06,814.99,yes,locked 2006.146.01:54:48.56/valo/07,864.99,yes,locked 2006.146.01:54:48.56/valo/08,884.99,yes,locked 2006.146.01:54:49.65/vb/01,03,usb,yes,35,33 2006.146.01:54:49.65/vb/02,04,usb,yes,31,30 2006.146.01:54:49.65/vb/03,04,usb,yes,28,31 2006.146.01:54:49.65/vb/04,04,usb,yes,32,31 2006.146.01:54:49.65/vb/05,04,usb,yes,25,27 2006.146.01:54:49.65/vb/06,04,usb,yes,29,25 2006.146.01:54:49.65/vb/07,04,usb,yes,29,29 2006.146.01:54:49.65/vb/08,04,usb,yes,26,30 2006.146.01:54:49.89/vblo/01,629.99,yes,locked 2006.146.01:54:49.89/vblo/02,634.99,yes,locked 2006.146.01:54:49.89/vblo/03,649.99,yes,locked 2006.146.01:54:49.89/vblo/04,679.99,yes,locked 2006.146.01:54:49.89/vblo/05,709.99,yes,locked 2006.146.01:54:49.89/vblo/06,719.99,yes,locked 2006.146.01:54:49.89/vblo/07,734.99,yes,locked 2006.146.01:54:49.89/vblo/08,744.99,yes,locked 2006.146.01:54:50.04/vabw/8 2006.146.01:54:50.19/vbbw/8 2006.146.01:54:50.36/xfe/off,on,15.5 2006.146.01:54:50.75/ifatt/23,28,28,28 2006.146.01:54:51.07/fmout-gps/S +4.0E-08 2006.146.01:54:51.12:!2006.146.01:56:07 2006.146.01:56:07.01:data_valid=off 2006.146.01:56:07.02:"et 2006.146.01:56:07.02:!+3s 2006.146.01:56:10.05:"tape 2006.146.01:56:10.10:postob 2006.146.01:56:10.20/cable/+6.5400E-03 2006.146.01:56:10.21/wx/21.19,1019.5,66 2006.146.01:56:10.29/fmout-gps/S +4.0E-08 2006.146.01:56:10.30:"unlod=1 2006.146.01:56:10.30:sched_end 2006.146.01:56:10.31&sched_end/stopcheck 2006.146.01:56:10.31&stopcheck/sy=killall check_fsrun.pl 2006.146.01:56:10.32&stopcheck/" sy=killall chmem.sh 2006.146.01:56:10.40:checkk5last 2006.146.01:56:10.40&checkk5last/chk_obsdata=1 2006.146.01:56:10.41&checkk5last/chk_obsdata=2 2006.146.01:56:10.41&checkk5last/chk_obsdata=3 2006.146.01:56:10.42&checkk5last/chk_obsdata=4 2006.146.01:56:10.42&checkk5last/k5log=1 2006.146.01:56:10.43&checkk5last/k5log=2 2006.146.01:56:10.43&checkk5last/k5log=3 2006.146.01:56:10.43&checkk5last/k5log=4 2006.146.01:56:10.44&checkk5last/obsinfo 2006.146.01:56:11.02/chk_obsdata//k5ts1/T1460154??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.146.01:56:11.79/chk_obsdata//k5ts2/T1460154??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.146.01:56:12.52/chk_obsdata//k5ts3/T1460154??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.146.01:56:13.02/chk_obsdata//k5ts4/T1460154??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.146.01:56:13.90/k5log//k5ts1_log_newline 2006.146.01:56:14.76/k5log//k5ts2_log_newline 2006.146.01:56:15.92/k5log//k5ts3_log_newline 2006.146.01:56:16.98/k5log//k5ts4_log_newline 2006.146.01:56:17.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.146.01:56:17.00:sy=cp /usr2/log/jd0605ts.log /usr2/log_backup/ 2006.146.01:56:17.13:*end of schedule 2006.146.01:58:32.09;cable 2006.146.01:58:32.18/cable/+6.5392E-03 2006.146.01:59:14.49;cablelong 2006.146.01:59:14.61/cablelong/+7.0918E-03 2006.146.01:59:16.89;cablediff 2006.146.01:59:16.90/cablediff/552.6e-6,+ 2006.146.02:00:07.49;cable 2006.146.02:00:07.64/cable/+6.5394E-03 2006.146.02:00:11.56;wx 2006.146.02:00:11.56/wx/21.10,1019.6,66 2006.146.02:00:19.95;"Sky is cloudy. 2006.146.02:00:32.60;xfe 2006.146.02:00:32.69/xfe/off,on,15.0 2006.146.02:00:38.31;clockoff 2006.146.02:00:39.07/fmout-gps/S +4.1E-08 2006.146.02:00:49.31;proc=point 2006.146.02:00:52.32;initp 2006.146.02:00:52.32&initp/"setup 2006.146.02:00:52.32&initp/abib=p2,pr 2006.146.02:00:52.32&initp/abib=p1,pr 2006.146.02:00:52.32&initp/!+1s 2006.146.02:00:52.32&initp/abib=p2,ln 2006.146.02:00:52.32&initp/abib=p2,rm3en 2006.146.02:00:52.32&initp/abib=p2,fm2en 2006.146.02:00:52.32&initp/abib=p2,ap 2006.146.02:00:52.32&initp/abib=p2 2006.146.02:00:52.32&initp/abib=p1,ln 2006.146.02:00:52.32&initp/abib=p1,rm3en 2006.146.02:00:52.32&initp/abib=p1,fm2en 2006.146.02:00:52.32&initp/"meter 1 (u6) has s band 2006.146.02:00:52.32&initp/abib=p1,ap 2006.146.02:00:52.32&initp/abib=p1 2006.146.02:00:52.32&initp/caloff 2006.146.02:00:52.32&initp/user_device=u5,7680,usb,rcp,750 2006.146.02:00:52.32&initp/user_device=u6,1600,usb,rcp,750 2006.146.02:00:52.32&initp/sigon 2006.146.02:00:52.32&initp/"sample fivept set-up for azel antenna with mark iii/iv rack 2006.146.02:00:52.32&initp/"fivept=azel,-2,9,.4,1,i1,120 2006.146.02:00:52.32&initp/"sample fivept set-up for xyns antenna with vlba/4 rack 2006.146.02:00:52.32&initp/"fivept=xyns,-2,9,.4,1,ia,120 2006.146.02:00:52.32&initp/" for tsukuba 2006.146.02:00:52.32&initp/"fivept=azel,-2,9,.4,1,u5,120 2006.146.02:00:52.32&initp/fivept=azel,-2,7,.3,1,u5,120 2006.146.02:00:52.32&initp/" sample onoff set-up for mark iii/iv 2006.146.02:00:52.32&initp/"onoff=2,1,75,3,120,all 2006.146.02:00:52.32&initp/" sample onoff set-up for vlba/4 2006.146.02:00:52.32&initp/"onoff=2,1,75,3,120,allu,ia,ib,ic 2006.146.02:00:52.32&initp/" for tsukuba 2006.146.02:00:52.32&initp/"onoff=2,1,75,3,120,u5,u6 2006.146.02:00:52.32&initp/" changed wait time into 60 sec (04-jun-2004 -sk-) 2006.146.02:00:52.32&initp/onoff=2,1,75,3,60,u5,u6 2006.146.02:00:52.32&initp/check= 2006.146.02:00:52.32&initp/sy=go aquir & 2006.146.02:00:54.34/abib/+0.0590E-03 2006.146.02:00:55.24/abib/+0.0410E-03 2006.146.02:00:55.24&caloff/"rx=*,*,*,*,*,*,off 2006.146.02:00:55.24&sigon/ifatt=23,28,28,28 2006.146.02:00:55.24&sigon/!+2s 2006.146.02:01:16.37;taurusa 2006.146.02:01:16.38&taurusa/source=taurusa,053432.,+220058,2000. 2006.146.02:01:17.14#flagr#flagr/antenna,new-source 2006.146.02:01:31.14#trakl#Source acquired 2006.146.02:01:33.14#flagr#flagr/antenna,acquired 2006.146.02:03:18.34;onoff 2006.146.02:03:18.34?ERROR q1 -307 WARNING: Source structure correction greater than 20% for detector u5. 2006.146.02:03:18.34#onoff# De Center TCal Flux DPFU Gain Product LO T FWHM 2006.146.02:03:18.34#onoff#APR u5 8430.00 -100. 357.5 0.167000 1.00000 0.167000 7680.00 c 0.07768 2006.146.02:03:18.34#onoff#APR u6 2350.00 -100. 773.7 0.209000 1.00000 0.209000 1600.00 c 0.27867 2006.146.02:03:19.14#onoff#ORIG 7399.1 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 2006.146.02:03:20.42#onoff#ONSO 1.3 0.00000 0.00000 u5 131 u6 133 2006.146.02:03:32.37#onoff#OFFS 13.2 1.79667 0.00000 u5 57 u6 43 2006.146.02:03:32.37;sigoffnf 2006.146.02:03:32.37&sigoffnf/sigoff 2006.146.02:03:32.37&sigoffnf/sy=go onoff & 2006.146.02:03:32.37&sigoff/ifatt=81,81,81,81 2006.146.02:03:32.37&sigoff/!+2s 2006.146.02:03:35.75;sigonnf 2006.146.02:03:35.76&sigonnf/sigon 2006.146.02:03:35.76&sigonnf/sy=go onoff & 2006.146.02:03:37.95#onoff#ZERO 16.6 1.79667 0.00000 u5 0 u6 0 2006.146.02:03:48.38#onoff#ONSO 29.2 0.00000 0.00000 u5 132 u6 130 2006.146.02:03:59.38#onoff#OFFS 40.2 -1.79667 -0.00000 u5 57 u6 42 2006.146.02:04:13.37#onoff#ONSO 54.2 0.00000 0.00000 u5 131 u6 131 2006.146.02:04:13.37#onoff#SIG u5 0.00 0.00 2.2 0.000 0.000 0.00 2006.146.02:04:13.37#onoff#SIG u6 0.00 0.00 10.6 0.000 0.000 0.00 2006.146.02:04:13.37#onoff# source Az El De I P Center Comp Tsys SEFD Tcal(j) Tcal(r) 2006.146.02:04:13.37#onoff#VAL taurusa 110.9 60.9 u5 5 r 8430.00 1.0000 -100. 274.1 0.000 0.0000 2006.146.02:04:13.37?ERROR nf -7 WARNING: Source structure correction greater than 20% for detector u5. 2006.146.02:04:13.37#onoff#VAL taurusa 110.9 60.9 u6 6 r 2350.00 1.0000 -100. 370.2 0.000 0.0000 2006.146.02:04:13.37#onoff# source Az El De I P Center Comp Tsys SEFD Tcal(j) Tcal(r) 2006.146.02:04:26.13;casa 2006.146.02:04:26.14&casa/source=casa,232324.8,+584859.,2000. 2006.146.02:04:28.14#flagr#flagr/antenna,new-source 2006.146.02:05:24.14#trakl#Source acquired 2006.146.02:05:26.14#flagr#flagr/antenna,acquired 2006.146.02:05:29.23;onoff 2006.146.02:05:29.24?ERROR q1 -307 WARNING: Source structure correction greater than 20% for detector u5. 2006.146.02:05:29.24#onoff# De Center TCal Flux DPFU Gain Product LO T FWHM 2006.146.02:05:29.24#onoff#APR u5 8430.00 -100. 343.8 0.167000 1.00000 0.167000 7680.00 p 0.07768 2006.146.02:05:29.24#onoff#APR u6 2350.00 -100. 1101.1 0.209000 1.00000 0.209000 1600.00 p 0.27867 2006.146.02:05:30.14#onoff#ORIG 7530.1 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 2006.146.02:05:31.38#onoff#ONSO 1.2 0.00000 0.00000 u5 123 u6 197 2006.146.02:05:41.38#onoff#OFFS 11.2 1.18317 0.00000 u5 59 u6 45 2006.146.02:05:41.38;sigoffnf 2006.146.02:05:44.79;sigonnf 2006.146.02:05:46.98#onoff#ZERO 14.6 1.18317 0.00000 u5 0 u6 0 2006.146.02:05:58.38#onoff#ONSO 28.2 0.00000 0.00000 u5 123 u6 195 2006.146.02:06:10.37#onoff#OFFS 40.2 -1.18317 -0.00000 u5 59 u6 44 2006.146.02:06:20.42#onoff#ONSO 50.3 0.00000 0.00000 u5 122 u6 196 2006.146.02:06:20.42#onoff#SIG u5 0.00 0.00 2.7 0.000 0.000 0.00 2006.146.02:06:20.42#onoff#SIG u6 0.00 0.00 7.2 0.000 0.000 0.00 2006.146.02:06:20.42#onoff# source Az El De I P Center Comp Tsys SEFD Tcal(j) Tcal(r) 2006.146.02:06:20.42#onoff#VAL casa 320.2 43.4 u5 5 r 8430.00 1.0000 -100. 318.6 0.000 0.0000 2006.146.02:06:20.42?ERROR nf -7 WARNING: Source structure correction greater than 20% for detector u5. 2006.146.02:06:20.42#onoff#VAL casa 320.2 43.4 u6 6 r 2350.00 1.0000 -100. 323.4 0.000 0.0000 2006.146.02:06:20.42#onoff# source Az El De I P Center Comp Tsys SEFD Tcal(j) Tcal(r) 2006.146.02:06:43.56;source=azel,0d,88d 2006.146.02:06:44.13#flagr#flagr/antenna,new-source 2006.146.02:07:09.13#trakl#Source acquired 2006.146.02:07:09.13#flagr#flagr/antenna,acquired 2006.146.02:07:20.45;caltsys 2006.146.02:07:20.45&caltsys/xfe=on,off 2006.146.02:07:20.45&caltsys/fe=off,,,,noise 2006.146.02:07:20.46&caltsys/tpi=u5,u6 2006.146.02:07:20.46&caltsys/ifatt=max,max,max,max 2006.146.02:07:20.47&caltsys/tpzero=u5,u6 2006.146.02:07:20.47&caltsys/ifatt=old,old,old,old 2006.146.02:07:20.48&caltsys/xfe=on,on 2006.146.02:07:20.48&caltsys/fe=on,,,,noise 2006.146.02:07:20.48&caltsys/tpical=u5,u6 2006.146.02:07:20.55&caltsys/tpdiff=u5,u6 2006.146.02:07:20.55&caltsys/xfe=off,off 2006.146.02:07:20.55&caltsys/fe=on,,,,pcal 2006.146.02:07:20.55&caltsys/user_device=u5,7681,usb,rcp,750 2006.146.02:07:20.55&caltsys/user_device=u6,1601,usb,rcp,750 2006.146.02:07:20.55&caltsys/caltemp=u5,u6 2006.146.02:07:20.55&caltsys/tsys=u5,u6 2006.146.02:07:22.36/tpi/u5,57 2006.146.02:07:22.36/tpi/u6,42 2006.146.02:07:23.75/tpzero/u5,0 2006.146.02:07:23.75/tpzero/u6,0 2006.146.02:07:25.66/tpical/u5,137 2006.146.02:07:25.66/tpical/u6,82 2006.146.02:07:25.67/tpdiff/u5,80 2006.146.02:07:25.67/tpdiff/u6,40 2006.146.02:07:26.12/caltemp/u5,69.580 2006.146.02:07:26.13/caltemp/u6,70.400 2006.146.02:07:26.13/tsys/u5,49.6 2006.146.02:07:26.13/tsys/u6,73.9 2006.146.02:07:43.02;stow 2006.146.02:07:43.02&stow/source=idle 2006.146.02:07:43.02&stow/"this is stow command. 2006.146.02:07:43.03&stow/antenna=m3 2006.146.02:07:44.13#flagr#flagr/antenna,new-source 2006.146.02:16:02.24;standby 2006.146.02:16:02.24&standby/"this is standby command. 2006.146.02:16:02.24&standby/antenna=m0 2006.146.02:16:06.73;terminate 2006.146.02:16:06.73:*boss terminated